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[ot] scripts/opentitan: swexit.py: rewrite this tool to use DV SIM window
`rv_core_ibex.SW_FATAL_ERR` has been deprecated a long time ago, however this smoke test generator had not been updated. See 7ba08ff Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
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‎scripts/opentitan/swexit.py‎

Lines changed: 126 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,16 @@
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#!/usr/bin/env python3
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# Copyright (c) 2023-2024 Rivos, Inc.
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# Copyright (c) 2023-2025 Rivos, Inc.
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# SPDX-License-Identifier: Apache2
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"""OpenTitan exit code generator for QEMU.
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Generate a small RV32I instruction bytestream to instruct the Ibex core to
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trigger a VM shutdown, using a dedicated HW register.
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This generator avoids adding a dependency on a RISC-V toolchain for the sake
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of smoke-testing an Ibex/OpenTitan VM.
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:author: Emmanuel Blot <eblot@rivosinc.com>
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"""
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@@ -14,44 +20,135 @@
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from typing import Union
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import sys
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# pylint: disable=missing-function-docstring
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BASE_ADDRESS = {
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'earlgrey': 0x411f0000,
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'darjeeling': 0x211f0000,
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'ibexdemo': 0x20000,
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SOC_CONSTANTS = {
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'earlgrey': (0x411f0000, 0x80),
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'darjeeling': (0x211f0000, 0x440),
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'ibexdemo': (0x20000, None)
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}
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LUI_MASK = (1 << 12) - 1
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"""Supported SoCs, with controller base address and register offset."""
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TEST_STATUS_PASSED = 0x900d # 'good'
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"""Special code to signal a successful completion to DV SIM register."""
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OPCODE = {
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'addi': 0b000_00000_0010011,
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'lui': 0b0110111,
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'srli': 0b101_00000_0010011,
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'ssli': 0b001_00000_0010011,
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'sw': 0b010_00000_0100011,
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'wfi': 0x10500073,
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}
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"""RV32I binary opcodes used in code generator."""
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def to_int(value: Union[int, str]) -> int:
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"""Argparser helper to parse decimal or hexadecimal integer strings."""
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if isinstance(value, int):
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return value
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return int(value.strip(), value.startswith('0x') and 16 or 10)
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34-
def opentitan_code(addr: int) -> bytes:
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addr &= ~LUI_MASK
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lui = addr | 0x537
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return spack('<IIII',
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lui, # lui a0,addr # ibex_core_wrapper base
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0xc0de05b7, # lui a1,0xc0de0 # exit code (0)
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0x00b52423, # sw a1,8(a0) # write to sw_fatal_err
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0x10500073) # wfi # stop here
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def rd_u(reg: int) -> int:
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"""Destination register for U-type instruction."""
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return reg << 7
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def imm_u(imm: int) -> int:
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"""Immediate value for U-type instruction."""
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return imm << 12
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def mask_u(imm: int) -> int:
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"""Mask immediate value for U-type instruction."""
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return imm & ~((1 << 12) - 1)
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def imm_i(imm: int) -> int:
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"""Immediate value for I-type instruction."""
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return imm << 20
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def rs1_i(reg: int) -> int:
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"""Source register for I-type instruction."""
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return reg << 15
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def rd_i(reg: int) -> int:
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"""Destination register for I-type instruction."""
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return reg << 7
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def shamt_i(imm: int) -> int:
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"""Shift ammount for I-type instruction."""
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return imm << 20
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def rs1_s(reg: int) -> int:
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"""First source register for S-type instruction."""
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return reg << 15
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def rs2_s(reg: int) -> int:
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"""Second source register for S-type instruction."""
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return reg << 20
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def off_s(imm: int) -> int:
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"""Offset value for S-type instruction."""
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off_hi = (imm >> 5) << 25
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off_lo = (imm & 0b11111) << 7
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return off_hi | off_lo
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def opentitan_code(addr: int, offset: int) -> bytes:
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"""Exit code generation using DV SIM status register.
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:param addr: Ibex wrapper controller base address
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:param offset: Offset of the DV SIM status register.
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:return: RV32I instruction stream
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"""
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assert 0 <= offset < (1 << 11) # 12 bit, signed int
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instructions = [
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# lui a0,addr # ibex_core_wrapper base
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mask_u(addr) | rd_u(10) | OPCODE['lui'],
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# lui a1,status # "test" status
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imm_u(TEST_STATUS_PASSED) | rd_u(11) | OPCODE['lui'],
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# srli a1,a1,12 # shift down status
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shamt_i(12) | rs1_i(11) | rd_i(11) | OPCODE['srli'],
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# sw a1,offset(a0) # write to DV SIM offset
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off_s(offset) | rs2_s(11) | rs1_s(10) | OPCODE['sw'],
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# wfi # stop here
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OPCODE['wfi'],
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# illegal instruction
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0x0
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]
126+
return spack(f'<{len(instructions)}I', *instructions)
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43128

44129
def ibexdemo_code(addr: int) -> bytes:
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addr &= ~LUI_MASK
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lui = addr | 0x537
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return spack('<IIII',
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lui, # lui a0,addr # simulator_ctrl base
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0x00100593, # li a1,1 # set bit 0 to exit
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0x00b52423, # sw a1,8(a0) # write to sim_ctrl
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0x10500073) # wfi # stop here
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"""Exit code generation for Ibex demo machine.
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:param addr: Controller base address
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:return: RV32I instruction stream
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"""
135+
instructions = [
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# lui a0,addr # simulator_ctrl base
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mask_u(addr) | rd_u(10) | OPCODE['lui'],
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# li a1,1 # set bit 0 to exit
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imm_i(1) | rs1_i(0) | rd_i(11) | OPCODE['addi'],
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# sw a1,offset(a0) # write to DV SIM offset
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off_s(0x8) | rs2_s(11) | rs1_s(10) | OPCODE['sw'],
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# wfi # stop here
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OPCODE['wfi'],
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# illegal instruction
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0x0
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]
147+
return spack(f'<{len(instructions)}I', *instructions)
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53149

54150
def main():
151+
"""Entry point."""
55152
debug = False
56153
try:
57154
desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
@@ -62,7 +159,7 @@ def main():
62159
argparser.add_argument('-b', '--base', type=to_int, default=0x80,
63160
help='Offset for the first instruction '
64161
'(default: 0x80)')
65-
argparser.add_argument('-t', '--soc', choices=list(BASE_ADDRESS),
162+
argparser.add_argument('-t', '--soc', choices=list(SOC_CONSTANTS),
66163
help='SoC type', required=True)
67164
argparser.add_argument('-o', '--output', type=FileType('wb'),
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help='output file, default to stdout')
@@ -71,11 +168,14 @@ def main():
71168
args = argparser.parse_args()
72169
debug = args.debug
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74-
addr = args.address if args.address else BASE_ADDRESS[args.soc]
171+
addr = args.address if args.address else SOC_CONSTANTS[args.soc][0]
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if args.soc == 'ibexdemo':
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bincode = ibexdemo_code(addr)
77174
else:
78-
bincode = opentitan_code(addr)
175+
offset = SOC_CONSTANTS.get(args.soc)[1]
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if offset is None:
177+
argparser.error('Unsupported SoC type')
178+
bincode = opentitan_code(addr, offset)
79179
out = args.output or sys.stdout.buffer
80180
padding = bytes(args.base)
81181
out.write(padding)

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