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ot_sram_ctrl: change the defaut pace delay for initialization #483

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ot_sram_ctrl: change the defaut pace delay for initialization

ot_sram_ctrl: change the defaut pace delay for initialization #483

Triggered via pull request December 5, 2025 11:11
@rivos-eblotrivos-eblot
synchronize #308
rivos-eblot:dev/ebl/sram_init_pace
Status Failure
Total duration 42m 54s
Artifacts 3

ci_regression.yml

on: pull_request
ROM  /  EG Regression
42m 50s
ROM / EG Regression
ROM_EXT  /  EG Regression
26m 48s
ROM_EXT / EG Regression
SiVal ROM_EXT  /  EG Regression
38m 29s
SiVal ROM_EXT / EG Regression
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6 errors and 5 warnings
ROM_EXT / EG Regression
Process completed with exit code 1.
ROM_EXT / EG Regression
There were some unexpected test failures
SiVal ROM_EXT / EG Regression
Process completed with exit code 1.
SiVal ROM_EXT / EG Regression
There were some unexpected test failures
ROM / EG Regression
Process completed with exit code 1.
ROM / EG Regression
There were some unexpected test failures
ROM_EXT / EG Regression
Failed to restore: Cache service responded with 400
SiVal ROM_EXT / EG Regression
Some tests passed which we did not expect
SiVal ROM_EXT / EG Regression
Failed to restore: Cache service responded with 400
ROM / EG Regression
Some tests passed which we did not expect
ROM / EG Regression
Failed to restore: Cache service responded with 400

Artifacts

Produced during runtime
Name Size Digest
sim_qemu_rom_ext-bazel-test-results Expired
146 KB
sha256:4179829064d09a790e60f47dcab385f5b30b43f00d995defa0016de58c8c3437
sim_qemu_rom_with_fake_keys-bazel-test-results Expired
146 KB
sha256:a32e5153c926fa6d3b73058a577c0d6585386c7acabb215bd55e1b80769150f5
sim_qemu_sival_rom_ext-bazel-test-results Expired
127 KB
sha256:4b4e0349cd04b44d2c1adebc7d75165ba8b8064838406a55a33306f78d8a88cf