diff --git a/syn/ibex_top_lr_synth_conf.tcl b/syn/ibex_top_lr_synth_conf.tcl
index f3f8622d6..8c3898147 100644
--- a/syn/ibex_top_lr_synth_conf.tcl
+++ b/syn/ibex_top_lr_synth_conf.tcl
@@ -7,13 +7,13 @@
 #
 # {instr_req_o 70.0}
 #
-# as an output means the instr_req_o output must be stable by 60% of total clock
-# cycle
+# as an output means the instr_req_o output must be stable by 70% of total clock
+# cycle,
 #
 # {instr_gnt_i 30.0}
 #
 # as an input means the instr_gnt_i input will be stable by 30% of the total
-# clock cycle
+# clock cycle.
 
 # These IO constraints are an educated guess, they effectively assume there's a
 # bit of external logic on the inputs and outputs but not much before they reach
@@ -46,11 +46,11 @@ set lr_synth_inputs [list {test_en_i      0.0 } \
                           {debug_req_i    10.0} \
                           {fetch_enable_i 0.0 }]
 
-# clock and reset IO names (at top-level)
+# Clock and reset IO names (at top-level).
 set lr_synth_clk_input clk_i
 set lr_synth_rst_input rst_ni
 
-# clock period in ps, this gives a 250 MHz clock.  using the nangate45 library
+# Clock period in ps, this gives a 250 MHz clock.  using the nangate45 library
 # Ibex can happily meet this on all paths with the lr_synth_abc_clk_uprate
 # setting below. With a lower uprate timing may not be met.
 set lr_synth_clk_period 4000.0