priv jal

Author: krmtrk

env/riscv-arch-test/ceres/model_test.h

@@ -42,21 +42,32 @@
 rvtest_trap_handler:                                                    \
     csrr t0, mcause;                                                    \
     csrr t1, mepc;                                                      \
-    li t2, 3;                   /* EBREAK mcause */                     \
+    /* Check EBREAK (mcause = 3) */                                     \
+    li t2, 3;                                                           \
     bne t0, t2, 1f;                                                     \
-    lhu t3, 0(t1);              /* Load instruction */                  \
-    andi t3, t3, 0x3;           /* Check if compressed */               \
+    /* EBREAK: check if compressed */                                   \
+    lhu t3, 0(t1);                                                      \
+    andi t3, t3, 0x3;                                                   \
     li t4, 0x3;                                                         \
-    beq t3, t4, 2f;             /* If 0x3, it's 32-bit */               \
+    beq t3, t4, 2f;                                                     \
     addi t1, t1, 2;             /* Compressed: PC += 2 */               \
     j 3f;                                                               \
 2:  addi t1, t1, 4;             /* 32-bit: PC += 4 */                   \
 3:  csrw mepc, t1;                                                      \
     mret;                                                               \
-1:  li t2, 11;                  /* ECALL mcause */                      \
+1:  /* Check ECALL (mcause = 11) */                                     \
+    li t2, 11;                                                          \
     bne t0, t2, 4f;                                                     \
-    j halt_loop;                /* ECALL = halt */                      \
-4:  addi t1, t1, 4;             /* Unknown: skip 4 bytes */             \
+    /* ECALL: check if it's exit syscall (a7 = 93) */                   \
+    li t2, 93;                                                          \
+    bne a7, t2, 5f;                                                     \
+    j halt_loop;                /* Exit syscall = halt */               \
+5:  /* Normal ECALL: advance PC and return */                           \
+    addi t1, t1, 4;                                                     \
+    csrw mepc, t1;                                                      \
+    mret;                                                               \
+4:  /* Other exceptions: advance PC and return */                       \
+    addi t1, t1, 4;                                                     \
     csrw mepc, t1;                                                      \
     mret;                                                               \
 _rvtest_boot_continue:                                                  \

rtl/core/cpu.sv

@@ -598,7 +598,7 @@ module cpu
     end
     excp_mask = '0;
     excp_mask = {1'b0, ex_exc_type != NO_EXCEPTION, de_active_exc_type != NO_EXCEPTION, fe_active_exc_type != NO_EXCEPTION};
-    fe_trap_active = |{excp_mask[3:1], pipe1.exc_type != NO_EXCEPTION};
+    fe_trap_active = |{excp_mask[3:1], de_active_exc_type != NO_EXCEPTION};
     trap_active = |excp_mask[3:1];
     de_trap_active = de_active_exc_type != NO_EXCEPTION;
     priority_flush = ex_exc_type != NO_EXCEPTION ? 3:

rtl/core/stage01_fetch/compressed_decoder.sv

@@ -225,8 +225,8 @@ module compressed_decoder
 
       3'b010: begin
         // C.LI: addi rd, x0, imm
+        // Note: rd=x0 is HINT (valid, treated as NOP)
         c1_instr = gen_i_type(get_imm_ci(), REG_ZERO, FUNCT3_ADD, rd_rs1_full, OPCODE_OPIMM);
-        if (rd_rs1_full == REG_ZERO) c1_illegal = 1'b1;  // rd=x0 is reserved
       end
 
       3'b011: begin
@@ -235,10 +235,12 @@ module compressed_decoder
           c1_instr = gen_i_type(get_imm_addi16sp(), REG_SP, FUNCT3_ADD, REG_SP, OPCODE_OPIMM);
         end else begin
           // C.LUI: lui rd, nzimm
+          // Note: rd=x0 is HINT (valid, treated as NOP)
           c1_instr = gen_u_type(get_imm_lui(), rd_rs1_full, OPCODE_LUI);
         end
         // Check for reserved encodings
-        if (rd_rs1_full == REG_ZERO) c1_illegal = 1'b1;
+        // Note: rd=x0 case goes to C.LUI which is HINT, not illegal
+        // But nzimm=0 is reserved for both C.ADDI16SP and C.LUI
         if ({instr_i[12], instr_i[6:2]} == 6'b0) c1_illegal = 1'b1;  // nzimm=0 is reserved
       end
 
@@ -316,8 +318,8 @@ module compressed_decoder
     case (funct3)
       3'b000: begin
         // C.SLLI: slli rd, rd, shamt
+        // Note: rd=x0 is HINT (valid, treated as NOP)
         c2_instr = gen_i_type({7'b0, get_shamt()}, rd_rs1_full, FUNCT3_SLL, rd_rs1_full, OPCODE_OPIMM);
-        if (rd_rs1_full == REG_ZERO) c2_illegal = 1'b1;  // rd=x0 is reserved
         if (instr_i[12] || get_shamt() == 5'b0) c2_illegal = 1'b1;  // shamt[5]=1 or shamt=0 is reserved
       end
 

rtl/core/stage01_fetch/fetch.sv

@@ -57,6 +57,7 @@ module fetch
   icache_req_t            abuff_icache_req;  // Raw request from align_buffer
   icache_req_t            icache_req;  // Gated request to cache
   blowX_res_t             buff_lowX_res;
+  logic                   buf_lookup_ack;
 
   // ============================================================================
   // PC Register: Program Counter yönetimi
@@ -198,7 +199,6 @@ module fetch
   end
 
   // Track pending request to icache - reset on response or new request from buffer
-  logic buf_lookup_ack;
   /* verilator lint_off UNUSEDSIGNAL */
   logic prev_icache_req_valid;
   /* verilator lint_on UNUSEDSIGNAL */

rtl/include/writeback_log.svh

@@ -120,7 +120,7 @@ end
     // ============================================================
     // 3) REGISTER WRITE ONLY (normal ALU, load result, jump-link, etc.)
     // ============================================================
-    else if (instr_type_i inside {i_lb, i_lh, i_lw, i_lbu, i_lhu}) begin
+    else if (instr_type_i inside {i_lb, i_lh, i_lw, i_lbu, i_lhu} && rd_addr_i != 0) begin
       automatic string spacing = (rd_addr_i < 10) ? "  " : " ";
       $fwrite(trace_fd,
         "core    0: 3 0x%08h (0x%08h) x%0d%s0x%08h mem 0x%08h\n",
@@ -130,6 +130,15 @@ end
       );
     end
 
+    // Load to x0 - just log memory access without register write
+    else if (instr_type_i inside {i_lb, i_lh, i_lw, i_lbu, i_lhu} && rd_addr_i == 0) begin
+      $fwrite(trace_fd,
+        "core   0: 3 0x%08h (0x%08h) mem 0x%08h\n",
+        pc_i, fe_tracer_i.inst,
+        alu_result_i
+      );
+    end
+
     else if (rf_rw_en_i && rd_addr_i != 0) begin
       automatic string spacing = (rd_addr_i < 10) ? "  " : " ";
       $fwrite(trace_fd,
@@ -258,13 +267,16 @@ task automatic check_pass_fail();
   end
 endtask
 
+// TOHOST check - only for riscv-tests (isa tests), not arch tests
+// When addr_check_enabled is true, pass/fail is determined by PC addresses
+// When addr_check_enabled is false, use TOHOST memory-mapped register
 always @(posedge clk_i) begin
   automatic logic        we = wr_en_i;
   automatic logic        valid = `SOC.pipe4.dcache_valid;
   automatic logic [31:0] addr = `SOC.pipe4.alu_result;
   automatic logic [31:0] data = `SOC.pipe4.write_data;
 
-  if (addr_check_enabled && valid && we && addr == 32'h80001000) begin
+  if (!addr_check_enabled && valid && we && addr == 32'h80001000) begin
     if (data == 32'h1) begin
       $display("🎉 TOHOST PASS");
       $finish;

rtl/wrapper/ceres_wrapper.sv

@@ -34,7 +34,7 @@ module ceres_wrapper
     parameter int unsigned BAUD_RATE   = 115200,
 
     // Memory Configuration
-    parameter int unsigned RAM_SIZE_KB = 128,
+    parameter int unsigned RAM_SIZE_KB = 1024,
     parameter int unsigned RAM_LATENCY = 16,
 
     // Peripheral Configuration