L2cache (#1)

* feat: Integrate L2 cache support and enhance memory management

- Added L2 cache module (l2_cache_top_v2.sv) for improved memory performance with non-blocking write-back capabilities.
- Updated memory arbiter and CPU modules to accommodate L2 cache interactions and downstream stall handling.
- Enhanced fetch and execution stages to manage flush cycles and stall conditions effectively.
- Refactored memory request handling to support uncached transactions and store buffer management.
- Modified parameter definitions in ceres_param.sv to include L2 cache configurations and derived parameters.
- Updated build scripts to include new L2 cache source files and configurations.

* refactor: Update CPU and memory modules for improved pipeline handling and introduce store buffer

- Renamed `pipe2_drained_q` to `pipe2_frozen` in the CPU module for clarity in stall handling.
- Removed redundant logic for tracking pipe2 drainage, simplifying the pipeline control flow.
- Enhanced memory module with a new store buffer implementation to manage store transactions and forwarding.
- Updated `ceres_param.sv` to define parameters for the store buffer, including depth and pointer width.
- Improved memory request handling to accommodate new store buffer functionality and maintain pipeline integrity.

* refactor: Standardize signal declarations in CPU and memory modules

- Introduced `logic` type for various signals in the CPU, memory, and cache modules to enhance clarity and consistency.
- Replaced `wire` declarations with `logic` for signals such as `fi_start`, `fi_has_dirty`, and `dcache_busy` to improve readability and maintainability.
- Updated assignments for these signals to ensure proper functionality within the modules.
- Enhanced overall code structure by ensuring uniformity in signal types across the design.

* refactor: Replace l2_cache_top_v2 with nbmbmp_l2_cache and remove legacy files

- Replaced the existing L2 cache module (l2_cache_top_v2.sv) with a new implementation (nbmbmp_l2_cache.sv) that supports non-blocking write-back capabilities.
- Deleted the old l2_cache.sv file to eliminate redundancy and streamline the codebase.
- Updated the CPU module to instantiate the new nbmbmp_l2_cache, ensuring compatibility with the revised memory architecture.
- Made minor adjustments to parameter definitions in ceres_param.sv to reflect the new cache structure.

* refactor: Transition from CERES to Level RISC-V across project files

- Updated project references from CERES to Level RISC-V in various files, including documentation, makefiles, and configuration scripts.
- Modified .gitignore to track new Level RISC-V specific directories and files.
- Adjusted svlint configuration to reflect the new project name.
- Enhanced README and mkdocs.yml for consistent branding and updated documentation links.
- Refactored OpenLane scripts to align with the Level RISC-V design structure.
- Removed obsolete files related to the CERES project to streamline the codebase.

* refactor: Update makefile and documentation for SIM_FAST integration

- Renamed FAST_SIM to SIM_FAST in the makefile for consistency and clarity.
- Updated related documentation and examples to reflect the new SIM_FAST variable.
- Added mkdocs_hooks.py to manage the generation of the test results dashboard.
- Enhanced .gitignore to exclude generated dashboard files and updated README with dashboard usage instructions.
- Introduced new dashboard preview images for improved documentation.

---------

Co-authored-by: Kerim Turak <kerimturak@hotmail.com>

Author: kerimturak

.github/copilot-instructions.md

@@ -1,13 +1,13 @@
-# Copilot Instructions for CERES RISC-V Project
+# Copilot Instructions for Level RISC-V Project
 
 ## Project Overview
 
-This is **CERES RISC-V** - a lightweight, modular 32-bit RISC-V processor core implementing the **RV32IMC** instruction set with CSR and FENCE support. The project is designed for learning, experimentation, and FPGA deployment.
+This is **Level RISC-V** - a lightweight, modular 32-bit RISC-V processor core implementing the **RV32IMC** instruction set with CSR and FENCE support. The project is designed for learning, experimentation, and FPGA deployment.
 
 ## Technology Stack
 
 - **Hardware Description Language**: SystemVerilog (IEEE 1800-2017)
-- **Simulation Tools**: Verilator (primary), ModelSim, Icarus Verilog
+- **Simulation Tools**: Verilator (primary), ModelSim
 - **Synthesis**: Yosys
 - **Toolchain**: riscv32-unknown-elf-gcc
 - **Scripting**: Python 3, Bash/Zsh, Make
@@ -34,7 +34,7 @@ rtl/                    # RTL source files
 │   ├── cpu.sv          # Top-level CPU module
 │   └── hazard_unit.sv  # Pipeline hazard handling
 ├── include/            # Header files (.svh)
-│   ├── ceres_defines.svh      # Global defines & feature flags
+│   ├── level_defines.svh      # Global defines & feature flags
 │   ├── exception_priority.svh # Exception handling
 │   ├── fetch_log.svh          # Fetch stage logging
 │   └── writeback_log.svh      # Writeback logging
@@ -50,7 +50,7 @@ rtl/                    # RTL source files
 │   ├── wdt/            # Watchdog timer
 │   └── vga/            # VGA controller
 ├── pkg/                # SystemVerilog packages
-│   └── ceres_param.sv  # Central configuration (1000+ lines)
+│   └── level_param.sv  # Central configuration (1000+ lines)
 ├── ram/                # Memory modules
 ├── tracer/             # Instruction tracer (Konata support)
 ├── util/               # Utility modules
@@ -62,13 +62,7 @@ sim/                    # Simulation files
 └── do/                 # ModelSim DO files
 
 script/                 # Build and test scripts
-├── makefiles/          # Modular makefiles
-│   ├── config/         # Configuration (config.mk, profiles.mk, paths.mk)
-│   ├── sim/            # Simulator configs (verilator.mk, modelsim.mk)
-│   ├── test/           # Test runners (isa, arch, imperas, coremark)
-│   ├── synth/          # Synthesis (yosys.mk)
-│   ├── lint/           # Linting rules
-│   └── tools/          # Utilities (clean, waveform viewers)
+├── makefiles/          # Optional local.mk (config/); rules live in repo root makefile
 ├── python/             # Python utilities
 ├── shell/              # Shell scripts
 └── config/             # JSON test configurations
@@ -105,14 +99,14 @@ build/                  # Build outputs
 - Filename matches module name
 - Headers in `rtl/include/` with `.svh` extension
 - Packages in `rtl/pkg/` with `_pkg.sv` or `_param.sv` suffix
-- Import `ceres_param` package for all parameters
+- Import `level_param` package for all parameters
 
 ### Code Example Template
 
 ```systemverilog
 // Module description
 module module_name
-  import ceres_param::*;
+  import level_param::*;
 #(
     parameter int PARAM_NAME = 32
 ) (
@@ -168,7 +162,7 @@ endmodule
 - **PMP/PMA**: Physical Memory Protection
 - **Bus**: Wishbone B4 compatible
 
-### Core Parameters (from `ceres_param.sv`)
+### Core Parameters (from `level_param.sv`)
 
 ```systemverilog
 // Core
@@ -230,7 +224,7 @@ GPIO_WIDTH = 32
 | `cs_reg_file` | `rtl/core/stage03_execute/cs_reg_file.sv` | CSR register file |
 | `memory_stage` | `rtl/core/stage04_memory/` | Memory access |
 | `writeback_stage` | `rtl/core/stage05_writeback/` | Register writeback |
-| `ceres_param` | `rtl/pkg/ceres_param.sv` | All parameters & types |
+| `level_param` | `rtl/pkg/level_param.sv` | All parameters & types |
 
 ---
 
@@ -242,13 +236,10 @@ GPIO_WIDTH = 32
 # === BUILD ===
 make verilate           # Build Verilator model
 make compile            # Compile with ModelSim
-make iverilog           # Compile with Icarus Verilog
 
 # === SIMULATION ===
-make simulate           # Run batch simulation (ModelSim)
-make simulate_gui       # Run GUI simulation with waveforms
+make simulate           # ModelSim/Questa (add GUI=1 for GUI)
 make run_verilator      # Run Verilator simulation
-make run_icarus         # Run Icarus simulation
 
 # === TEST SUITES ===
 make isa                # All ISA tests (riscv-tests)
@@ -270,8 +261,8 @@ make run_batch          # Run multiple tests from list
 make list_tests         # List available tests
 
 # === COREMARK ===
-make cm                 # Build and run CoreMark
-make cm_run             # Quick CoreMark run (skip rebuild)
+make run_coremark       # Build (if needed) + run CoreMark on Verilator
+make run_coremark       # CoreMark: build if needed + Verilator sim
 make coremark           # Build CoreMark only
 make coremark_help      # Show CoreMark help
 
@@ -330,7 +321,7 @@ MODE=test         # RISC-V test mode with assertions
 make run T=rv32ui-p-add LOG_COMMIT=1
 
 # Run CoreMark in fast mode with branch stats
-make cm SIM_FAST=1 LOG_BP=1 SIM_UART_MONITOR=1
+make run_coremark SIM_FAST=1 LOG_BP=1 SIM_UART_MONITOR=1
 
 # Run all ISA tests with commit log
 make isa LOG_COMMIT=1
@@ -355,7 +346,7 @@ The makefile auto-detects test type from name:
 
 ---
 
-## Feature Flags (ceres_defines.svh)
+## Feature Flags (level_defines.svh)
 
 ```systemverilog
 // Multiplier implementation (only one active)
@@ -429,15 +420,15 @@ The makefile auto-detects test type from name:
 
 1. Create file in appropriate `rtl/` subdirectory
 2. Follow naming conventions (lowercase, underscores)
-3. Import `ceres_param` package: `import ceres_param::*;`
-4. Add to filelist in `script/makefiles/config/sources.mk`
+3. Import `level_param` package: `import level_param::*;`
+4. Add the new file path to `rtl/flist.f` (one `rtl/...` path per line; `makefile` reads `SV_SOURCES` from there)
 5. Update testbench if needed
 6. Run `make lint` to verify
 
 ### Adding a New Peripheral
 
 1. Create directory under `rtl/periph/`
-2. Define register offsets in `ceres_param.sv`
+2. Define register offsets in `level_param.sv`
 3. Add to peripheral bus decoder
 4. Create software header file
 5. Add test program in `sim/test/`
@@ -479,7 +470,7 @@ make formal_prove        # Proof mode
 2. **Active Development**: Check `docs/AI_ENHANCEMENT_PLANS.md` for planned features
 3. **Testing**: Always run `make quick` or `make lint` before committing
 4. **Formal**: Use `make formal` for formal verification checks
-5. **Package**: Always import `ceres_param` for parameters and types
+5. **Package**: Always import `level_param` for parameters and types
 6. **Reset**: Active-low reset (`i_rst_n`), synchronous design
 
 ---
@@ -488,26 +479,26 @@ make formal_prove        # Proof mode
 
 | File | Purpose |
 |------|---------|
-| `rtl/pkg/ceres_param.sv` | **Central config** - ALL parameters, types, enums, structs |
-| `rtl/include/ceres_defines.svh` | Feature flags, trace controls |
+| `rtl/pkg/level_param.sv` | **Central config** - ALL parameters, types, enums, structs |
+| `rtl/include/level_defines.svh` | Feature flags, trace controls |
 | `rtl/core/cpu.sv` | Top-level CPU module |
 | `rtl/core/hazard_unit.sv` | Pipeline hazard detection |
-| `script/makefiles/config/config.mk` | Build configuration |
-| `script/makefiles/config/profiles.mk` | Build profiles (debug/release/test) |
-| `makefile` | Top-level build entry point |
+| `makefile` | **Unified** build/test rules (paths, toolchain, Verilator, tests, synth) |
+| `rtl/flist.f` | RTL file list → `SV_SOURCES` (one `rtl/...` path per line) |
+| `script/makefiles/config/local.mk` | Optional local overrides (`-include`) |
 | `docs/architecture.md` | Full architecture documentation |
 | `docs/INDEX.md` | Documentation index |
 
 ---
 
-## Enumeration Types (from ceres_param.sv)
+## Enumeration Types (from level_param.sv)
 
 Common enums used throughout RTL - always use these instead of magic numbers:
 
 ```systemverilog
 // ALU operations, branch types, memory operations, CSR operations
 // Exception codes, privilege levels, etc.
-// See rtl/pkg/ceres_param.sv for complete list
+// See rtl/pkg/level_param.sv for complete list
 ```
 
 ---

.github/workflows/ci.yml

@@ -1,11 +1,11 @@
 # ============================================================
-# CERES RISC-V — Continuous Integration Pipeline
+# Level RISC-V — Continuous Integration Pipeline
 # ============================================================
 # Triggers on push and pull requests to main branch
 # Runs ISA tests, Architecture tests, and generates reports
 # ============================================================
 
-name: CERES CI
+name: LEVEL CI
 
 on:
   # push:
@@ -345,7 +345,7 @@ jobs:
     steps:
       - name: Check test results
         run: |
-          echo "## CERES RISC-V Test Results" >> $GITHUB_STEP_SUMMARY
+          echo "## Level RISC-V Test Results" >> $GITHUB_STEP_SUMMARY
           echo "" >> $GITHUB_STEP_SUMMARY
           echo "| Job | Status |" >> $GITHUB_STEP_SUMMARY
           echo "|-----|--------|" >> $GITHUB_STEP_SUMMARY

.gitignore

@@ -14,18 +14,20 @@ riscv-privileged.pdf
 riscv-unprivileged.pdf
 # MkDocs site
 site/
+# Copied from results/logs by mkdocs_hooks.py (do not commit)
+docs/dashboard.html
 */__pycache__/
 *.pyc
 
-# Allow tracking spike-pk inside env/coremark (coremark is globally ignored)
+# Track CoreMark port sources under env/coremark (name "coremark" may be ignored elsewhere)
 !env/coremark/
-!env/coremark/spike-pk/
-!env/coremark/spike-pk/**
+!env/coremark/levelv/
+!env/coremark/levelv/**
 !env/coremark/minimal/
 !env/coremark/minimal/**
 
 # OpenLane generated artifacts
-asic/openlane/designs/ceres_wrapper/src/
-asic/openlane/designs/ceres_wrapper/runs/
-asic/openlane/designs/ceres_wrapper/sources_manifest.txt
-asic/openlane/designs/ceres_wrapper/src/ceres_wrapper_sv2v.v
+asic/openlane/designs/level_wrapper/src/
+asic/openlane/designs/level_wrapper/runs/
+asic/openlane/designs/level_wrapper/sources_manifest.txt
+asic/openlane/designs/level_wrapper/src/level_wrapper_sv2v.v

.svlint.toml

@@ -1,5 +1,5 @@
 # =========================================
-# svlint Configuration for CERES RISC-V
+# svlint Configuration for Level RISC-V
 # https://github.com/dalance/svlint
 # =========================================