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@@ -45,6 +45,18 @@ _Avoid_: syscall, normal memory-mapped device
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The CPU mode that models instruction flow through fetch, decode, issue, execute, writeback, and commit with speculative execution and in-order retirement.
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_Avoid_: OOO blob, pipeline code
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**Structural Constraint Simulator**:
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The modeling role for the out-of-order CPU: capture the timing and resource constraints that explain performance behavior without attempting cycle-accurate RTL reproduction.
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_Avoid_: full RTL replica, teaching-only Tomasulo model, functional-only simulator
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**Completion Fabric**:
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The out-of-order pipeline's result-completion boundary that arbitrates when executed work becomes visible to wakeup, physical-register writeback, and ROB completion.
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_Avoid_: treating the Common Data Bus as the long-term domain boundary
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**Completion Backpressure**:
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The structural constraint where an execution unit that has produced a result must keep holding it when the Completion Fabric cannot accept another completion event in the current cycle.
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_Avoid_: silently buffering every completed result in an unbounded queue
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**Stage Context**:
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A stage-specific adapter that exposes only the state and actions a pipeline stage needs for one execution step.
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_Avoid_: passing raw `CPUState` as the stage interface
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## Relationships
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- An **Out-of-Order Pipeline** executes each stage through a **Stage Context**.
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- A **Structural Constraint Simulator** should model performance-visible resource contention while keeping implementation detail below full RTL fidelity.
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- A **Completion Fabric** replaces the Common Data Bus as the domain concept for execution-result completion; any CDB-like queue is only a legacy or migration detail.
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-**Completion Backpressure** keeps completed execution units occupied when completion bandwidth is exhausted.
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- The **Simulator** owns the run lifecycle and may create a **Reference Execution Context** when **DiffTest** is enabled for an out-of-order run.
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- A **Checkpoint Runner** drives the **Simulator** over an **Instruction Window** after importing a workload slice.
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-**Address Translation** delegates Sv39-specific page-table traversal to the **SV39 Page Walker** and is constrained by **Privilege State**.
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## Flagged Ambiguities
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- Use **Execute Memory Order** for the decision and accounting around memory-order speculation. Use **OOO Recovery** for the shared pipeline cleanup rules.
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- Use **Structural Constraint Simulator** for the intended OOO modeling fidelity; do not describe this direction as full RTL reproduction or as a purely functional simulator.
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- Use **Completion Fabric** for the future result-completion boundary; use Common Data Bus only when referring to legacy implementation or migration work.
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- Use **Completion Backpressure** when completion bandwidth stalls a completed execution unit; do not model this as an always-available result queue.
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- Use **Address Translation** for the fetch/load/store translation boundary. Use **SV39 Page Walker** only for the Sv39 page-table walk inside that boundary.
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- Use **DiffTest** for commit-time reference comparison, not for ordinary unit tests or benchmark result checks.
The out-of-order CPU will use **Completion Fabric** as the domain concept for execution-result completion instead of continuing to treat the Common Data Bus as the architecture boundary. Existing CDB-shaped code may remain during migration, but the design direction is to reduce or remove it because a single global bus hides performance-visible distinctions between wakeup, physical-register writeback, and ROB completion.
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**Status**: accepted
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**Considered Options**
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- Keep CDB as the primary concept and add more limits around it.
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- Retire CDB as a domain concept and migrate toward a Completion Fabric with separate completion consumers.
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**Consequences**
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- New design docs and tests should describe completion behavior in terms of Completion Fabric rather than CDB.
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- Migration can be incremental; existing CDB queues do not need to disappear in the first patch.
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- The first implementation should focus on completion-event arbitration and fanout to existing wakeup, physical-register writeback, and ROB-completion consumers.
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- More realistic bypass, wakeup, and select networks are deferred until the Completion Fabric boundary is established.
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- The first implementation should model completion backpressure: a completed execution unit keeps holding its result when completion bandwidth is exhausted instead of placing every result into an unbounded queue.
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- IPC improvement is not an acceptance criterion for the first implementation. A lower IPC is acceptable when it follows from modeling a previously missing structural constraint more realistically.
PERF_COUNTER_DEF(STALL_EXECUTE_RESOURCE_BLOCKED, "cpu.stall.execute_resource_blocked", "Execute stalled because ready instructions wait for resources")
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PERF_COUNTER_DEF(STALL_EXECUTE_NO_UNIT, "cpu.stall.execute_no_unit", "Execute stage had ready instruction but no execution unit")
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PERF_COUNTER_DEF(STALL_EXECUTE_AMO_WAIT, "cpu.stall.execute_amo_wait", "AMO delayed by older uncommitted store-like operations")
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PERF_COUNTER_DEF(STALL_COMPLETION_PORT_BUSY, "cpu.stall.completion_port_busy", "Execution result held because completion fabric bandwidth was exhausted")
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PERF_COUNTER_DEF(STALL_MEMORY_REPLAY_PORT_BUSY, "cpu.stall.memory_replay_port_busy", "Memory inflight completion delayed because replay ports were exhausted")
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PERF_COUNTER_DEF(LOAD_REPLAYS, "cpu.memory.load_replays", "Load instructions replayed due to memory ordering")
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