Cleanup.

Author: gonsolo

Makefile

@@ -14,7 +14,7 @@ tt_gds:
 	$(TT_TOOL) --create-user-config --ihp
 	$(TT_TOOL) --harden --ihp
 nix:
-	nix develop --command make all
+	nix develop --command make borg_test tt_test tt_docs #tt_gds
 clean:
 	git clean -dfx
 .PHONY: all borg_test clean generate_verilog just_test test tt_docs tt_gds tt_test tt_test_only \

borg/src/Borg.scala

@@ -5,7 +5,6 @@ package borg
 
 import chisel3._
 import chisel3.util.MuxLookup
-//import hardfloat._
 
 class Borg extends Module {
     val io = IO(new Bundle {
@@ -55,7 +54,7 @@ class Borg extends Module {
     io.data_out := MuxLookup(io.address, 0.U(32.W)) (Seq(
       ADDR_A      -> operand_A_bits,
       ADDR_B      -> operand_B_bits,
-      ADDR_RESULT -> result_bits // Output the 32-bit result
+      ADDR_RESULT -> result_bits
     ))
 
     io.data_ready := true.B

test/.gitignore

@@ -1 +1,2 @@
 /tags
+/tb.fst