Using SIDkick pico 2040DAC in MBHP MIDIbox SIDv1?

[Jimi-Heinrich]

Hi,

there was a thread already discussing this for a bit (#76):

#76

but the OP didn't engage anymore. I have the same question, because I explicitly bought the excellent SIDkick pico 2040DAC from retro8bitshop exactly for this. Alas, putting it into the midibox SIDv1 doesnt work – no sound at all. You can see the relevant schematics, etc in #76. I have everything to sort it out, i guess. A working midibox Sidv1, a working SIDkick pico 2040DAC, A C64, an oscilloscope, a logic analyser. I also can compile from the source code (assembler) of the midibox (but i suck at assembler).

The ideal solution would be finding out, what is exactly the difference in the initialisation and put that in the midibox SIDv1 code. Or one could investigate, if the SIDkick pico is able to recognize if it's in a non-C64 environment, and account for that.

So if you llike, we could engage on a investigation, how to get the SIDkick pico 2040DAC working in a midibox Sidv1.

Cheers,
Jimi

[frntc]

Hi,

hm, I've completely forgotten about that. I had a quick look, it does not seem that there's a minimal midibox variant which I could easily put together to fiddle around with it. Can you use your logic analyzer and log CLK, CS, RW, A0 and Dx when sending commands to alter the voice #0 frequency?

(did you also try to connect directly to the line-out of the SKpico?)

[Jimi-Heinrich]

Hey, Yeah. Great! Yes, it's been a while. I'm willing to be your eyes and ears on this one. And yes, I tried directly getting the signal from the line-out (but will double check).

One thing I know from the top of my head is, that RW is fixed to VSS(GND).

I will do the logic plot and post it here. My logic analyzer only has 8 ports, so I cannot analyze all at once. So bear with me. it might take a day or two.

[Jimi-Heinrich]

So here are screenshots and .logicdata (Saleae Logic.app format)

1. from a startup sequence,
2. from sending some notes rising a halftone

I used the signals: CLK, CS#, A0 and D0-D4

if you need more or different readings, I'd be happy to supply them.

All the Best,
Thilo

sidbox startup 4 MHz, 40 M Samples [6] 2026-5-13 22-24-4.zip


Notes and rests 4 MHz, 12 M Samples [10] 2026-5-14 8-8-7.zip

[frntc]

That was quick! Unfortunately I cannot open these files in Pulseview (it cannot handle the .logicdata format and documentation sounds as if this is a weird format not even supported by newer Saleae software?).

Can you a) record some cycles with higher frequency (as high as possible, e.g. >=24MHz, I should be able to see signal behavior in the range of tens of nanoseconds), and b) export to some other file format so that I can explore in Pulseview? (maybe it's better if you send me these files by mail?)

[Jimi-Heinrich]

I used a very old version (1.2) of Saleae Logic. i now installed PulseView and here are the two files in the same configuration. Alas, although my litte logic anaylzer says "i can go to 24Mnz, like the big boys", it only accepts sample rates of max 16MHz. So that's what i used. I hope that's enough. If you need specific configs (rising/falling edge etc.) please let me know.

EDIT:
Sorry the data was not correct i think, here are proper ones.

more midibox startup + rising notes pulseview 2026-5-14 17-12-41.zip

[frntc]

Thanks for the data! If your LA measures correctly, then it looks indeed surprisingly different from a real c64/c128:

• the clock-signal has phases of quite unequal length
• even worse: the chip select signal is low for 1.25 full cycles and low at the beginning of two Phi2=LOW phases. This seems to be outside the SID specs, but apparently can work. Once I find the time I can prepare a test firmware (but I'm not going to post it here, let me know your mail address, you can find mine in the source code)

[Jimi-Heinrich]

Brilliant! thanks a lot.
I just send you a mail.