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realtek: irq: backport upstream patches
The interrupt driver downstream patches have been sent upstream and got accepted. Backport them and make the driver free of downstream hacks. Link: openwrt#23679 Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
1 parent 0a64c7a commit f4ddf8d

9 files changed

Lines changed: 870 additions & 428 deletions

‎target/linux/realtek/patches-6.18/032-01-v7.2-irqchip-irq-realtek-rtl-Add-simplify-register-helper.patch‎

Lines changed: 135 additions & 0 deletions
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From 167883f75f83088a2b32c85ce5e3d0cd1cef157b Mon Sep 17 00:00:00 2001
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From: Markus Stockhausen <markus.stockhausen@gmx.de>
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Date: Thu, 4 Jun 2026 20:25:05 +0200
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Subject: [PATCH 1/8] irqchip/irq-realtek-rtl: Add/simplify register helpers
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The Realtek interrupt controller has two important registers that are used
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by the driver in several places
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- GIMR: global interrupt mask register
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- IRR: Interrupt routing registers
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The usage of these registers is very inconsistent. GIMR is addressed
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directly while IRR has a helper that needs a macro as an input. Harmonize
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this by providing consistent helpers that improve code readability.
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The callers of these helpers use classic lock/unlock functions and
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sometimes use the wrong locking helper. E.g. irqsave variants are used in
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mask/unmask although not needed. Adapt and fix the surrounding call
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locations.
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Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
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Signed-off-by: Thomas Gleixner <tglx@kernel.org>
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Link: https://patch.msgid.link/20260604182506.1113440-2-markus.stockhausen@gmx.de
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---
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drivers/irqchip/irq-realtek-rtl.c | 64 +++++++++++++++----------------
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1 file changed, 32 insertions(+), 32 deletions(-)
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--- a/drivers/irqchip/irq-realtek-rtl.c
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+++ b/drivers/irqchip/irq-realtek-rtl.c
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@@ -37,10 +37,29 @@ static void __iomem *realtek_ictl_base;
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#define IRR_OFFSET(idx) (4 * (3 - (idx * 4) / 32))
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#define IRR_SHIFT(idx) ((idx * 4) % 32)
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-static void write_irr(void __iomem *irr0, int idx, u32 value)
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+static inline void enable_gimr(unsigned int hw_irq)
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{
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- unsigned int offset = IRR_OFFSET(idx);
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- unsigned int shift = IRR_SHIFT(idx);
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+ u32 gimr;
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+
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+ gimr = readl(REG(RTL_ICTL_GIMR));
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+ gimr |= BIT(hw_irq);
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+ writel(gimr, REG(RTL_ICTL_GIMR));
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+}
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+
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+static inline void disable_gimr(unsigned int hw_irq)
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+{
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+ u32 gimr;
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+
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+ gimr = readl(REG(RTL_ICTL_GIMR));
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+ gimr &= ~BIT(hw_irq);
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+ writel(gimr, REG(RTL_ICTL_GIMR));
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+}
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+
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+static void write_irr(int hw_irq, u32 value)
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+{
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+ void __iomem *irr0 = REG(RTL_ICTL_IRR0);
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+ unsigned int offset = IRR_OFFSET(hw_irq);
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+ unsigned int shift = IRR_SHIFT(hw_irq);
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u32 irr;
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irr = readl(irr0 + offset) & ~(0xf << shift);
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@@ -50,30 +69,14 @@ static void write_irr(void __iomem *irr0
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static void realtek_ictl_unmask_irq(struct irq_data *i)
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{
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- unsigned long flags;
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- u32 value;
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-
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- raw_spin_lock_irqsave(&irq_lock, flags);
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-
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- value = readl(REG(RTL_ICTL_GIMR));
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- value |= BIT(i->hwirq);
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- writel(value, REG(RTL_ICTL_GIMR));
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-
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- raw_spin_unlock_irqrestore(&irq_lock, flags);
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+ guard(raw_spinlock)(&irq_lock);
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+ enable_gimr(i->hwirq);
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}
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static void realtek_ictl_mask_irq(struct irq_data *i)
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{
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- unsigned long flags;
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- u32 value;
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-
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- raw_spin_lock_irqsave(&irq_lock, flags);
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-
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- value = readl(REG(RTL_ICTL_GIMR));
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- value &= ~BIT(i->hwirq);
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- writel(value, REG(RTL_ICTL_GIMR));
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-
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- raw_spin_unlock_irqrestore(&irq_lock, flags);
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+ guard(raw_spinlock)(&irq_lock);
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+ disable_gimr(i->hwirq);
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}
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static struct irq_chip realtek_ictl_irq = {
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@@ -84,13 +87,10 @@ static struct irq_chip realtek_ictl_irq
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static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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- unsigned long flags;
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-
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irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq);
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- raw_spin_lock_irqsave(&irq_lock, flags);
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- write_irr(REG(RTL_ICTL_IRR0), hw, 1);
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- raw_spin_unlock_irqrestore(&irq_lock, flags);
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+ guard(raw_spinlock_irqsave)(&irq_lock);
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+ write_irr(hw, 1);
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return 0;
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}
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@@ -127,7 +127,6 @@ static int __init realtek_rtl_of_init(st
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{
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struct of_phandle_args oirq;
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struct irq_domain *domain;
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- unsigned int soc_irq;
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int parent_irq;
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realtek_ictl_base = of_iomap(node, 0);
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@@ -135,9 +134,10 @@ static int __init realtek_rtl_of_init(st
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return -ENXIO;
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/* Disable all cascaded interrupts and clear routing */
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- writel(0, REG(RTL_ICTL_GIMR));
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- for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++)
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- write_irr(REG(RTL_ICTL_IRR0), soc_irq, 0);
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+ for (unsigned int hw_irq = 0; hw_irq < RTL_ICTL_NUM_INPUTS; hw_irq++) {
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+ disable_gimr(hw_irq);
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+ write_irr(hw_irq, 0);
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+ }
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if (WARN_ON(!of_irq_count(node))) {
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/*

‎target/linux/realtek/patches-6.18/032-02-v7.2-irqchip-irq-realtek-rtl-Add-multicore-support.patch‎

Lines changed: 184 additions & 0 deletions
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From a1a35c09241f0577cc40f65d7372fed01138619d Mon Sep 17 00:00:00 2001
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From: Markus Stockhausen <markus.stockhausen@gmx.de>
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Date: Thu, 4 Jun 2026 20:25:06 +0200
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Subject: [PATCH 2/8] irqchip/irq-realtek-rtl: Add multicore support
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The Realtek interrupt driver currently supports only single core
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systems. So the higher end devices like RTL839x and RTL930x with
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dual VPEs must be driven with NR_CPU=1. Enhance the driver to
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support multicore (dual VPE) systems. For this:
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- Extend the register map for multiple cores
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- Search for multiple CPU cores in the devicetree
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- Improve the register helpers to support multiple cores
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- Add an affinity setter
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- Enhance the IRQ handler for multiple cores
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Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
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Signed-off-by: Thomas Gleixner <tglx@kernel.org>
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Link: https://patch.msgid.link/20260604182506.1113440-3-markus.stockhausen@gmx.de
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---
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drivers/irqchip/irq-realtek-rtl.c | 82 ++++++++++++++++++++-----------
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1 file changed, 54 insertions(+), 28 deletions(-)
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--- a/drivers/irqchip/irq-realtek-rtl.c
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+++ b/drivers/irqchip/irq-realtek-rtl.c
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@@ -23,10 +23,10 @@
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#define RTL_ICTL_NUM_INPUTS 32
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-#define REG(x) (realtek_ictl_base + x)
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+#define REG(cpu, x) (realtek_ictl_base[cpu] + x)
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static DEFINE_RAW_SPINLOCK(irq_lock);
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-static void __iomem *realtek_ictl_base;
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+static void __iomem *realtek_ictl_base[NR_CPUS];
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/*
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* IRR0-IRR3 store 4 bits per interrupt, but Realtek uses inverted numbering,
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@@ -37,27 +37,27 @@ static void __iomem *realtek_ictl_base;
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#define IRR_OFFSET(idx) (4 * (3 - (idx * 4) / 32))
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#define IRR_SHIFT(idx) ((idx * 4) % 32)
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-static inline void enable_gimr(unsigned int hw_irq)
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+static inline void enable_gimr(unsigned int cpu, unsigned int hw_irq)
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{
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u32 gimr;
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- gimr = readl(REG(RTL_ICTL_GIMR));
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+ gimr = readl(REG(cpu, RTL_ICTL_GIMR));
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gimr |= BIT(hw_irq);
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- writel(gimr, REG(RTL_ICTL_GIMR));
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+ writel(gimr, REG(cpu, RTL_ICTL_GIMR));
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}
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-static inline void disable_gimr(unsigned int hw_irq)
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+static inline void disable_gimr(unsigned int cpu, unsigned int hw_irq)
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{
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u32 gimr;
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- gimr = readl(REG(RTL_ICTL_GIMR));
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+ gimr = readl(REG(cpu, RTL_ICTL_GIMR));
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gimr &= ~BIT(hw_irq);
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- writel(gimr, REG(RTL_ICTL_GIMR));
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+ writel(gimr, REG(cpu, RTL_ICTL_GIMR));
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}
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-static void write_irr(int hw_irq, u32 value)
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+static void write_irr(unsigned int cpu, int hw_irq, u32 value)
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{
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- void __iomem *irr0 = REG(RTL_ICTL_IRR0);
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+ void __iomem *irr0 = REG(cpu, RTL_ICTL_IRR0);
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unsigned int offset = IRR_OFFSET(hw_irq);
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unsigned int shift = IRR_SHIFT(hw_irq);
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u32 irr;
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@@ -69,28 +69,51 @@ static void write_irr(int hw_irq, u32 va
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static void realtek_ictl_unmask_irq(struct irq_data *i)
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{
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+ unsigned int cpu;
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+
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guard(raw_spinlock)(&irq_lock);
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- enable_gimr(i->hwirq);
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+ for_each_cpu(cpu, irq_data_get_effective_affinity_mask(i))
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+ enable_gimr(cpu, i->hwirq);
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}
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static void realtek_ictl_mask_irq(struct irq_data *i)
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{
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+ unsigned int cpu;
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+
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guard(raw_spinlock)(&irq_lock);
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- disable_gimr(i->hwirq);
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+ for_each_cpu(cpu, irq_data_get_effective_affinity_mask(i))
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+ disable_gimr(cpu, i->hwirq);
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+}
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+
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+static int realtek_ictl_irq_affinity(struct irq_data *i, const struct cpumask *dest, bool force)
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+{
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+ if (!irqd_irq_masked(i))
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+ realtek_ictl_mask_irq(i);
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+
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+ irq_data_update_effective_affinity(i, dest);
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+
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+ if (!irqd_irq_masked(i))
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+ realtek_ictl_unmask_irq(i);
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+
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+ return IRQ_SET_MASK_OK;
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}
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static struct irq_chip realtek_ictl_irq = {
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- .name = "realtek-rtl-intc",
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- .irq_mask = realtek_ictl_mask_irq,
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- .irq_unmask = realtek_ictl_unmask_irq,
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+ .name = "realtek-rtl-intc",
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+ .irq_mask = realtek_ictl_mask_irq,
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+ .irq_unmask = realtek_ictl_unmask_irq,
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+ .irq_set_affinity = realtek_ictl_irq_affinity,
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};
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static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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+ unsigned int cpu;
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+
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irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq);
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guard(raw_spinlock_irqsave)(&irq_lock);
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- write_irr(hw, 1);
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+ for_each_present_cpu(cpu)
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+ write_irr(cpu, hw, 1);
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return 0;
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}
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@@ -103,12 +126,13 @@ static const struct irq_domain_ops irq_d
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static void realtek_irq_dispatch(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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+ unsigned int cpu = smp_processor_id();
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struct irq_domain *domain;
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unsigned long pending;
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unsigned int soc_int;
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chained_irq_enter(chip, desc);
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- pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR));
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+ pending = readl(REG(cpu, RTL_ICTL_GIMR)) & readl(REG(cpu, RTL_ICTL_GISR));
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if (unlikely(!pending)) {
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spurious_interrupt();
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@@ -116,7 +140,7 @@ static void realtek_irq_dispatch(struct
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}
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domain = irq_desc_get_handler_data(desc);
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- for_each_set_bit(soc_int, &pending, 32)
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+ for_each_set_bit(soc_int, &pending, RTL_ICTL_NUM_INPUTS)
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generic_handle_domain_irq(domain, soc_int);
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out:
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@@ -127,16 +151,18 @@ static int __init realtek_rtl_of_init(st
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{
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struct of_phandle_args oirq;
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struct irq_domain *domain;
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- int parent_irq;
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+ int cpu, parent_irq;
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- realtek_ictl_base = of_iomap(node, 0);
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- if (!realtek_ictl_base)
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- return -ENXIO;
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-
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- /* Disable all cascaded interrupts and clear routing */
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- for (unsigned int hw_irq = 0; hw_irq < RTL_ICTL_NUM_INPUTS; hw_irq++) {
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- disable_gimr(hw_irq);
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- write_irr(hw_irq, 0);
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+ for_each_present_cpu(cpu) {
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+ realtek_ictl_base[cpu] = of_iomap(node, cpu);
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+ if (!realtek_ictl_base[cpu])
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+ return -ENXIO;
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+
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+ /* Disable all cascaded interrupts and clear routing */
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+ for (unsigned int hw_irq = 0; hw_irq < RTL_ICTL_NUM_INPUTS; hw_irq++) {
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+ disable_gimr(cpu, hw_irq);
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+ write_irr(cpu, hw_irq, 0);
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+ }
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}
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if (WARN_ON(!of_irq_count(node))) {

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