PDN Generation Error

[nishit0072e]

Description

For any Lower to Medium Sized design error persist in PDN generation

[PDN-0185] Insufficient width (11.04 um) to add straps on layer met4 in grid "stdcell_grid" with total strap width 21.7 um and offset 16.32 um.

Expected Behavior

It should run flawlessly

Environment report

Failed to get Docker info: [Errno 2] No such file or directory: 'docker'
kernel: Linux
kernel_version: 6.1.85+
supported: True
distro: ubuntu
distro_version: 22.04
python_version: 3.11.11
python_path:
  - /usr/local/bin
  - /env/python
  - /usr/lib/python311.zip
  - /usr/lib/python3.11
  - /usr/lib/python3.11/lib-dynload
  - /usr/local/lib/python3.11/dist-packages
  - /usr/lib/python3/dist-packages
tkinter: True
container_info: None
nix_info:
  version_string: nix (Nix) 2.27.1
  channels:
    nixpkgs: https://nixos.org/channels/nixpkgs-unstable
  nix_command: True
  flakes: True

Reproduction material

Verilog Code SingleCycleCPU.v:
// 1. Program Counter (PC) Module
module PC (
input wire clk, rst,
input wire [7:0] next_pc,
output reg [7:0] pc_out
);
always @(posedge clk or posedge rst) begin
if (rst)
pc_out <= 8'b0;
else
pc_out <= next_pc;
end
endmodule

// 2. Instruction Memory (IM) Module
module InstructionMemory (
input wire [7:0] pc,
output reg [15:0] instruction
);
reg [15:0] mem [0:255];

// For synthesis, hardcode a small instruction set or leave as ROM
initial begin
    mem[0] = 16'b0000000000000000; // NOP
    mem[1] = 16'b0000011000100001; // ADDI r1, r0, 1
    mem[2] = 16'b0000011001000010; // ADDI r2, r0, 2
    mem[3] = 16'b0010010010000000; // SUB r4, r1, r2
    // Add more instructions as needed
end

always @(*) begin
    instruction = mem[pc];
end

endmodule

// 3. Instruction Decoder Module
module Decoder (
input wire [15:0] instr,
output reg [2:0] opcode, rs1, rs2, rd, alu_control,
output reg [7:0] imm
);
always @(*) begin
opcode = instr[15:13];
rd = instr[12:10];
rs1 = instr[9:7];
rs2 = instr[6:4];
imm = instr[7:0];

    case (opcode)
        3'b000: alu_control = 3'b000; // ADD
        3'b001: alu_control = 3'b001; // SUB
        3'b010: alu_control = 3'b010; // AND (used for LOAD)
        3'b011: alu_control = 3'b011; // OR (used for STORE)
        3'b100: alu_control = 3'b100; // XOR
        default: alu_control = 3'b000;
    endcase
end

endmodule

// 4. Register File Module
module RegisterFile (
input wire clk, regWrite,
input wire [2:0] rs1, rs2, rd,
input wire [7:0] write_data,
output reg [7:0] read_data1, read_data2
);
reg [7:0] regs [0:7];

// Synchronous write
always @(posedge clk) begin
    if (regWrite && rd != 3'b000) // Protect r0
        regs[rd] <= write_data;
end

// Asynchronous read
always @(*) begin
    read_data1 = regs[rs1];
    read_data2 = regs[rs2];
end

endmodule

// 5. ALU Module
module ALU (
input wire [7:0] a, b,
input wire [2:0] alu_control,
output reg [7:0] alu_result
);
always @(*) begin
case (alu_control)
3'b000: alu_result = a + b; // ADD
3'b001: alu_result = a - b; // SUB
3'b010: alu_result = a & b; // AND
3'b011: alu_result = a | b; // OR
3'b100: alu_result = a ^ b; // XOR
default: alu_result = 8'b0;
endcase
end
endmodule

// 6. Data Memory Module
module DataMemory (
input wire clk, memRead, memWrite,
input wire [7:0] addr, write_data,
output reg [7:0] read_data
);
reg [7:0] mem [0:255];

// Synchronous write
always @(posedge clk) begin
    if (memWrite)
        mem[addr] <= write_data;
end

// Asynchronous read
always @(*) begin
    if (memRead)
        read_data = mem[addr];
    else
        read_data = 8'b0;
end

endmodule

// 7. Control Unit Module
module ControlUnit (
input wire [2:0] opcode,
output reg regWrite, memRead, memWrite, aluSrc
);
always @(*) begin
case (opcode)
3'b000: {regWrite, memRead, memWrite, aluSrc} = 4'b1001; // ADDI (imm)
3'b001: {regWrite, memRead, memWrite, aluSrc} = 4'b1000; // SUB (reg)
3'b010: {regWrite, memRead, memWrite, aluSrc} = 4'b0110; // LOAD (imm)
3'b011: {regWrite, memRead, memWrite, aluSrc} = 4'b0010; // STORE (imm)
3'b100: {regWrite, memRead, memWrite, aluSrc} = 4'b1001; // XOR (imm)
default: {regWrite, memRead, memWrite, aluSrc} = 4'b0000;
endcase
end
endmodule

// 8. Immediate Generator Module
module ImmediateGenerator (
input wire [7:0] imm_in,
output reg [7:0] imm_out
);
always @(*) begin
imm_out = imm_in;
end
endmodule

// 9. Top-Level Single-Cycle CPU Module
module SingleCycleCPU (
input wire clk, rst
);
wire [7:0] pc, next_pc, reg_data1, reg_data2, alu_result, mem_out, write_data;
wire [15:0] instr;
wire [2:0] opcode, rs1, rs2, rd, alu_control;
wire regWrite, memRead, memWrite, aluSrc;
wire [7:0] imm, imm_extended;

// Instantiate Modules
PC pc_reg (.clk(clk), .rst(rst), .next_pc(next_pc), .pc_out(pc));
InstructionMemory imem (.pc(pc), .instruction(instr));
Decoder decoder (.instr(instr), .opcode(opcode), .rs1(rs1), .rs2(rs2), .rd(rd), .alu_control(alu_control), .imm(imm));
ControlUnit control (.opcode(opcode), .regWrite(regWrite), .memRead(memRead), .memWrite(memWrite), .aluSrc(aluSrc));
RegisterFile rf (.clk(clk), .regWrite(regWrite), .rs1(rs1), .rs2(rs2), .rd(rd), .write_data(write_data), .read_data1(reg_data1), .read_data2(reg_data2));
ImmediateGenerator immGen (.imm_in(imm), .imm_out(imm_extended));
ALU alu (.a(reg_data1), .b(aluSrc ? imm_extended : reg_data2), .alu_control(alu_control), .alu_result(alu_result));
DataMemory dmem (.clk(clk), .memRead(memRead), .memWrite(memWrite), .addr(alu_result), .write_data(reg_data2), .read_data(mem_out));

assign next_pc = pc + 8'd1;
assign write_data = memRead ? mem_out : alu_result;

endmodule

Relevant log output

everything should be done