verilog-hdl-datapath/mux.v at main · arian-fallahpour/verilog-hdl-datapath · GitHub

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// 2-to-1 mux
module mux2(
	input wire x1,
	input wire x2,
	input wire s,
	output wire y
);
	assign y = s ? x2 : x1;
endmodule

// 3-to-1 mux
module mux3(
	input wire x1,
	input wire x2,
	input wire x3,
	input wire [1:0] s,
	output reg y
);
	always @(*) begin
		case (s)
			2'b00: y = x1;
			2'b01: y = x2;
			2'b10: y = x3;
			default: y = 1'b0;
		endcase
	end
endmodule

// 4-to-1 mux
module mux4(
	input wire x1,
	input wire x2,
	input wire x3,
	input wire x4,
	input wire [1:0] s,
	output reg y
);
	always @(*) begin
		case (s)
			2'b00: y = x1;
			2'b01: y = x2;
			2'b10: y = x3;
			2'b11: y = x4;
			default: y = 1'bx;
		endcase
	end
endmodule