alu.v.bak

module ALU_Control(
	input [1:0] ALUOp,
	input [10:0] Opcode,
	output reg [3:0] ALUControl
);
	always @(*) begin
		case (ALUOp)
			2'b00: ALUControl = 4'b0010; // Load/store (always add)
			2'b01: ALUControl = 4'b0111;
			2'b10: begin
				case (Opcode)
					11'b10001011000: ALUControl = 4'b0010; // add
					11'b11001011000: ALUControl = 4'b0110; // subtract
					11'b10001010000: ALUControl = 4'b0000; // AND
					11'b10101010000: ALUControl = 4'b0001; // ORR
					default: 	     ALUControl = 4'b1111; // undefined
				endcase
			end
			default: ALUControl = 4'b0010; // Default to add
		endcase
	end
endmodule;

module ALU_32bit(
	input [31:0] a,
	input [31:0] b,
	input [3:0] ALUControl,
	output reg [31:0] result,
	ouput zero
);
	assign zero = (result == 32'b0)
	
	always @(*) begin
		case (ALUControl)
			4'b0000: result = a & b;
			4'b0001: result = a | b;
			4'b0010: result = a + b;
			4'b0110: result = a - b;
			4'b0111: result = b;
			4'b1100: result = ~(a | b);
			default: result = 32'b0;
		endcase
	end
endmodule