AIM Build Failed : Run vpl: FINISHED. Run Status: impl ERROR

[Prathmesh-shalu141]

I am trying to build AIM for Input_Bitwidth = 1024 & PL_Freq = 104, but it failed after running build.sh.
The error is attached below for more details.

[ZhuopingYang]

@Prathmesh-shalu141 It might be because of a routing issue. Could you provide more details about runme.log?

[Prathmesh-shalu141]

@ZhuopingYang i have attached the file from '/home/cselab/AIM-main/templete/_x/link/vivado/vpl/prj/prj.runs/impl_1/runme.log'.

As you mentioned in the earlier issue i have kept pl freq (lower) as 104 and updated checkfreq.py so that it should not update pl freq again. Here is the modified code for checkfreq.py :

import re
import linecache
import os
timing_rpt_path = r"./_x/reports/link/imp/impl_1_xilinx_vck190_base_wrapper_timing_summary_routed.rpt"

if not (os.path.exists(timing_rpt_path)):
exit(2)

WNS = float(linecache.getline(timing_rpt_path, 140).split()[0])
makefile_path = r"./Makefile"
freq = float(linecache.getline(makefile_path, 121).split()[3])
cycle = 1e9 / freq
new_cycle = cycle - WNS + 0.001

new_freq = int((1e9 / new_cycle) / 1e6)
#freq_diff = (new_freq - int((freq / 1e6)))

freq_diff = 0
if freq_diff >= 0 and freq_diff < 10:
exit(0)
elif WNS >= 0:
exit(0)
else:
code = ""
with open("Makefile", "r") as f:
code = f.read()
code = re.sub(r"--pl-freq=\d+", "--pl-freq=" + str(new_freq), code)
code = re.sub(r"CLFLAGS += --clock.defaultFreqHz \d+", "CLFLAGS += --clock.defaultFreqHz " + str(new_freq) + "000000", code)
with open("Makefile", "w") as f:
f.write(code)
with open("freq", "w") as f:
f.write(str(new_freq))
exit(1)

runme.log

[ZhuopingYang]

@ Prathmesh-shalu141, after browsing the log file, I think this error is caused by routing congestion. As AIM's DSE tries to maximize the throughput while only considering the hardware resource constraints (without placement and routing optimization on the FPGA side), even if the resource constraints are met, the number of PEs can be too large to be routed. This issue seems obvious and significant when applying AIM to smaller integer multiplications (< 4096 bits). If you are reproducing the experiments in the paper, please try larger integer multiplications as in the paper. If you must use 1024-bit multiplication, decreasing the PE number in the AIM.py (line 62) probably works.

[Prathmesh-shalu141]

@ZhuopingYang got the same issue for input bit width 8192 and PL freq 140.

runme.log

[ZhuopingYang]

@Prathmesh-shalu141 It seems the FPGA implementation got an error due to routing congestion, which is usually because too many hardware resources, such as LUT, BRAM, etc., are used. I would recommend using fewer PEs to reduce the required hardware resources so that Vivado can finish routing.

[Prathmesh-shalu141]

@ZhuopingYang Yes, I tried with lower pe values and it worked. So we can't always pick the same PE which AIM.py generates, right?(i have even tried for 26K bits and it failed but when i lowered PE values it worked).

[ZhuopingYang]

@Prathmesh-shalu141 Yes, if you get errors in PL implementation, it's hard to solve, even if there are still enough hardware resources (LUT, BRAM, etc.) available due to the complex interconnection. It may require more low-level and complicated placement/routing optimizations. Instead, if you encounter errors in AIE routing, you can still try to optimize the AIE placement in the aie_graph.h by changing the location of each AIE (adf::location<kernel>), but this would be tricky.

[Prathmesh-shalu141]

@ZhuopingYang i have one doubt. does AIM doing multiplication of multiple operands of same bitwidth parallely ? Lets say PE=5 means each PE computing LIM of given input bit width.

[ZhuopingYang]

@Prathmesh-shalu141 Yes, the two operands of each multiplication should have the same bitwidth, and all PEs' inputs should have the same bitwidth.