Could you explain why the prescale should be set to Fclk / (baud * 8) according to verilog code?

[wuzh07]

In my understanding of verilog code, it seems like (prescale * 8) * 9 bits * baud = Fclk.
*8 because prescale_reg <= (prescale << 3) in verilog code.
*9 because of the transferred 9 bits in 1 symbol.
I'm confused about

The prescale input determines the data rate - it should be set to Fclk / (baud * 8).

Do I understand the code in a wrong way?

[alexforencich]

The code waits for prescale*8 clock cycles for each bit transferred. And for RS-232, one bit is one symbol so the baud rate is the same as the bit rate.