[BUG] Unresolved BUFGCE module during build with SYNTHESIS=1 flag enabled

[Gs-ygc]

Related component: build | simulation framework | cosim with a REF
Describe the bug
During the build process, an error occurs when compiling the file DifftestClockGate.v (located at /nfs/home/leguochun/workload/XSAI/difftest/src/test/vsrc/common/DifftestClockGate.v). The error message indicates that the instance bufgce_1 of the design unit BUFGCE is unresolved, suggesting that the BUFGCE module was not successfully analyzed or is missing from the required libraries.
To Reproduce

1. Clone the repository containing the DiffTest source code.
2. Navigate to the project directory and ensure the relevant source files (including DifftestClockGate.v) are present.
3. Run the build command:

make sim-verilog -j16 CONFIG=$(PLDM_CONFIG_DEFAULT) \
                       PLDM=1 MFC=1 NUM_CORES=1\
					   WITH_DRAMSIM3=1 \
                       WITH_CHISELDB=0 WITH_CONSTANTIN=0 \
                       SIM_MEM_SIZE=8 \
                       DEBUG_ARGS="--difftest-config ZESNHP"
make pldm-build PLDM=1 WITH_CHISELDB=0 SIM_MEM_SIZE=8 SYNTHESIS=1
# If SYNTHESIS=1 is not enabled, the compilation will pass normally.

5. Observe the error: Instance 'bufgce_1' of design unit 'BUFGCE' is unresolved during the compilation of DifftestClockGate.v. Expected behavior
   The build process should complete successfully without any unresolved module errors, indicating that all required design units (including BUFGCE) are properly analyzed and linked.

What you expect us (DiffTest developers) to do for you
Investigate why the BUFGCE module is unresolved during compilation and provide guidance on resolving the dependency (e.g., ensuring the correct libraries are included or the module is properly defined).
Additional context
The error occurs at line 24 of DifftestClockGate.v, and the build fails with [FLOW_FAILED] Failure to build target (vhelab). The build environment appears to be using a Verilog-based simulation flow, and the issue may relate to missing or misconfigured library dependencies for the BUFGCE primitive.

[Gs-ygc]

The codebase I am currently working with is at commit 24a7f37. I was unable to locate any references to the BUFGCE module or its associated definitions throughout the codebase.

[xiaokamikami]

DifftestClockGate.v is no need to introduce the comprehensive process of Paladin. BUFGCE is a primitive directly from Vivado.

[klin02]

difftest/src/test/vsrc/common/DifftestClockGate.v

Line 25 in f129fce

`ifdef SYNTHESIS

This bug will only occur when we enable both Difftest Acceleration config and SYNTHESIS.
You can bypass this bug by passing DifftestMacros.svh or simplify assign Q=CK;
We will also add a more strict MACRO wrapper in this module later.