From 51174fb0a65b6513d1c546dc9575a0f83c9bbea2 Mon Sep 17 00:00:00 2001 From: Rrraaaeee Date: Fri, 9 Jan 2026 09:57:05 +0000 Subject: [PATCH] fix uninitialized reg arr for VlWhole staticInst type --- src/arch/riscv/isa/vector/base/vector_mem.temp.isa | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/riscv/isa/vector/base/vector_mem.temp.isa b/src/arch/riscv/isa/vector/base/vector_mem.temp.isa index a8e5b71f99..e97eef0940 100644 --- a/src/arch/riscv/isa/vector/base/vector_mem.temp.isa +++ b/src/arch/riscv/isa/vector/base/vector_mem.temp.isa @@ -423,6 +423,8 @@ def template VlWholeConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst _machInst) : %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s) { + %(set_reg_idx_arr)s; + size_t NFIELDS = machInst.nf + 1; eew = 8; StaticInstPtr microop;