(add --unsafe-hold-vio) Preserve VIO rails across applet load?

[i-infra]

I have a workflow where I need to preserve the state of the voltage rails while switching applets, in my particular case, to configure a part, and then use the configuration with another applet. There's not enough FPGA gate space to build a combination applet.

Digging into the source, it looks like the current behavior (disable Vio on applet load) is intentional for safety reasons, as referenced in #552 and #96, where outputs all go HIGH at the specified bus output, through a 33o resistor, for the duration of the ~1-2ms FPGA configuration process. With some sensitive parts, this could be an issue, but I have not yet found any hardware that dies fighting ie) 3.3v through 33o (or larger, depending upon external/attached hardware) for a millisecond or two.

Wondering if there's any willingness to entertain an "--unsafe-hold-Vio" flag which would functionally make the paths added in f050f51 conditional (duplicating the path & costing extra space? adding a parameter to fpga_reset?) and route the hold-vio path through a new req->bRequest == USB_REQ_FPGA_CFG_UNSAFE_HOLD_VIO

More docs @ https://gist.github.com/i-infra/ca4ae0ad7f9a0886412f32a06e0a0cba and modded .ihex @ https://gist.github.com/i-infra/44f7266bc714a92900299f067123ce48.

As always, thanks so much @whitequark @marcan etc!! <3

[whitequark]

Wondering if there's any willingness to entertain an "--unsafe-hold-Vio" flag which would functionally make the paths added in f050f51 conditional

In principle, yes, but I would want to be absolutely sure that we agree on the nature of the problem it's solving. To be clear, I'm not questioning your use case, just your safety evaluation. At a crude approximation, the configuration bitstream is 100 kB and it's shifted out at 5 MHz. That translates to 160 ms of contention. Are you absolutely sure you are OK with 160 ms of 3.3 V sunk through a roughly 50 ohm total output impedance? That's a maximum of 66 mA current into a dead short.

[i-infra]

Safety evaluation cross-check is appreciated 100%! Just because it hasn't caused issues yet doesn't mean it won't... torn between adding an interposer on the 0.1" headers with ~1ko series resistors and bodging 0805 10ko pulldown resistors across pins 2 and 5 of the output buffers.

Did a bunch of reading to try and improve safety margins for unmodified hardware: https://github.com/nmi-leipzig/compact_bitstream might be interesting, looks like an implementation of

C. Fritzsch, J. Hoffmann and M. Bogdan, "Reduction of Bitstream Size for Low-Cost iCE40 FPGAs," 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL), Belfast, United Kingdom, 2022, pp. 117-122, doi: 10.1109/FPL57034.2022.00028.

which would reduce the duration of contention, but not eliminate it.

[whitequark]

Can you measure the pulse you get with a scope?