gateware.pll_deprecated: remove.

Author: whitequark

software/glasgow/gateware/pll_deprecated.py

@@ -11,5 +11,201 @@ class GlasgowECP5Platform(GlasgowPlatform, LatticeECP5Platform):
     def bitstream_filename(self, design_name):
         return f"{design_name}.bit"
 
-    def get_pll(self, pll):
-        raise NotImplementedError("get_pll() not implemented for ECP5")
+
+# This is copied from `amaranth.vendor._lattice.InnerBuffer` as-is.
+class _InnerBuffer(wiring.Component):
+    """A private component used to implement ``lib.io`` buffers.
+
+    Works like ``lib.io.Buffer``, with the following differences:
+
+    - ``port.invert`` is ignored (handling the inversion is the outer buffer's responsibility)
+    - ``t`` is per-pin inverted output enable
+    """
+
+    def __init__(self, direction, port):
+        self.direction = direction
+        self.port = port
+        members = {}
+        if direction is not io.Direction.Output:
+            members["i"] = wiring.In(len(port))
+        if direction is not io.Direction.Input:
+            members["o"] = wiring.Out(len(port))
+            members["t"] = wiring.Out(len(port))
+        super().__init__(wiring.Signature(members).flip())
+
+    def elaborate(self, platform):
+        m = Module()
+
+        if isinstance(self.port, io.SingleEndedPort):
+            io_port = self.port.io
+        elif isinstance(self.port, io.DifferentialPort):
+            io_port = self.port.p
+        else:
+            raise TypeError(f"Unknown port type {self.port!r}")
+
+        for bit in range(len(self.port)):
+            name = f"buf{bit}"
+            if self.direction is io.Direction.Input:
+                m.submodules[name] = Instance("IB",
+                    i_I=io_port[bit],
+                    o_O=self.i[bit],
+                )
+            elif self.direction is io.Direction.Output:
+                m.submodules[name] = Instance("OBZ",
+                    i_T=self.t[bit],
+                    i_I=self.o[bit],
+                    o_O=io_port[bit],
+                )
+            elif self.direction is io.Direction.Bidir:
+                m.submodules[name] = Instance("BB",
+                    i_T=self.t[bit],
+                    i_I=self.o[bit],
+                    o_O=self.i[bit],
+                    io_B=io_port[bit],
+                )
+            else:
+                assert False # :nocov:
+
+        return m
+
+
+# Patterned after `io.DDRBuffer`, but with somewhat more questionable design choices. Would likely
+# not be accepted upstream as-is for a number of reasons; a major one is that IDDRX2F.ALIGNWD input
+# is not connected at all.
+class QDRBuffer(wiring.Component):
+    class Signature(wiring.Signature):
+        def __init__(self, direction, width):
+            self._direction = io.Direction(direction)
+            self._width = operator.index(width)
+            members = {}
+            if self._direction is not io.Direction.Output:
+                members["i"] = wiring.In(data.ArrayLayout(self._width, 4))
+            if self._direction is not io.Direction.Input:
+                members["o"] = wiring.Out(data.ArrayLayout(self._width, 4))
+                members["oe"] = wiring.Out(1, init=int(self._direction is io.Direction.Output))
+            super().__init__(members)
+
+        @property
+        def direction(self):
+            return self._direction
+
+        @property
+        def width(self):
+            return self._width
+
+        def __eq__(self, other):
+            return (type(self) is type(other) and self.direction == other.direction and
+                    self.width == other.width)
+
+        def __repr__(self):
+            return f"QDRBuffer.Signature({self.direction}, {self.width})"
+
+    def __init__(self, direction, port, *, i_domain=None, o_domain=None):
+        if not isinstance(port, io.PortLike):
+            raise TypeError(f"'port' must be a 'PortLike', not {port!r}")
+        self._port = port
+        super().__init__(QDRBuffer.Signature(direction, len(port)).flip())
+        if self.signature.direction is not io.Direction.Output:
+            self._i_domain = i_domain or "sync"
+        else:
+            if i_domain is not None:
+                raise ValueError("Output buffer doesn't have an input domain")
+            self._i_domain = None
+        if self.signature.direction is not io.Direction.Input:
+            self._o_domain = o_domain or "sync"
+        else:
+            if o_domain is not None:
+                raise ValueError("Input buffer doesn't have an output domain")
+            self._o_domain = None
+        if port.direction is io.Direction.Input and self.direction is not io.Direction.Input:
+            raise ValueError(f"Input port cannot be used with {self.direction.name} buffer")
+        if port.direction is io.Direction.Output and self.direction is not io.Direction.Output:
+            raise ValueError(f"Output port cannot be used with {self.direction.name} buffer")
+
+    @property
+    def port(self):
+        return self._port
+
+    @property
+    def direction(self):
+        return self.signature.direction
+
+    @property
+    def i_domain(self):
+        return self._i_domain
+
+    @property
+    def o_domain(self):
+        return self._o_domain
+
+    def elaborate(self, platform):
+        assert isinstance(platform, LatticeECP5Platform), "QDR buffers are only supported on ECP5"
+
+        m = Module()
+
+        m.submodules.buf = buf = _InnerBuffer(self.direction, self.port)
+        inv_mask = sum(inv << bit for bit, inv in enumerate(self.port.invert))
+
+        if self.direction is not io.Direction.Output:
+            m.submodules += RequirePosedge(self.i_domain)
+            i0_inv = Signal(len(self.port))
+            i1_inv = Signal(len(self.port))
+            i2_inv = Signal(len(self.port))
+            i3_inv = Signal(len(self.port))
+            for bit in range(len(self.port)):
+                m.submodules[f"i_ddr{bit}"] = Instance("IDDRX2F",
+                    # https://github.com/YosysHQ/nextpnr/issues/1749
+                    # i_ALIGNWD=0,
+                    i_SCLK=ClockSignal(self.i_domain),
+                    i_ECLK=ClockSignal("edge"),
+                    i_RST=ResetSignal("edge"),
+                    i_D=buf.i[bit],
+                    o_Q0=i0_inv[bit],
+                    o_Q1=i1_inv[bit],
+                    o_Q2=i2_inv[bit],
+                    o_Q3=i3_inv[bit],
+                )
+            m.d.comb += self.i[0].eq(i0_inv ^ inv_mask)
+            m.d.comb += self.i[1].eq(i1_inv ^ inv_mask)
+            m.d.comb += self.i[2].eq(i2_inv ^ inv_mask)
+            m.d.comb += self.i[3].eq(i3_inv ^ inv_mask)
+
+        if self.direction is not io.Direction.Input:
+            m.submodules += RequirePosedge(self.o_domain)
+            o0_inv = Signal(len(self.port))
+            o1_inv = Signal(len(self.port))
+            o2_inv = Signal(len(self.port))
+            o3_inv = Signal(len(self.port))
+            m.d.comb += [
+                o0_inv.eq(self.o[0] ^ inv_mask),
+                o1_inv.eq(self.o[1] ^ inv_mask),
+                o2_inv.eq(self.o[2] ^ inv_mask),
+                o3_inv.eq(self.o[3] ^ inv_mask),
+            ]
+            for bit in range(len(self.port)):
+                m.submodules[f"o_ddr{bit}"] = Instance("ODDRX2F",
+                    i_SCLK=ClockSignal(self.o_domain),
+                    i_ECLK=ClockSignal("edge"),
+                    i_RST=ResetSignal("edge"),
+                    i_D0=o0_inv[bit],
+                    i_D1=o1_inv[bit],
+                    i_D2=o2_inv[bit],
+                    i_D3=o3_inv[bit],
+                    o_Q=buf.o[bit],
+                )
+
+            oe = ~self.oe
+            for stage in range(2):
+                oe_reg = Signal(name=f"oe_delay{stage}")
+                m.d[self.o_domain] += oe_reg.eq(oe)
+                oe = oe_reg
+            for bit in range(len(buf.t)):
+                m.submodules[f"oe_ff{bit}"] = Instance("OFS1P3DX",
+                    i_SCLK=ClockSignal(self.o_domain),
+                    i_SP=Const(1),
+                    i_CD=ResetSignal("edge"),
+                    i_D=oe,
+                    o_Q=buf.t[bit],
+                )
+
+        return m

software/glasgow/hardware/platform/ecp5.py

@@ -1,8 +1,6 @@
 from amaranth import *
-from amaranth.lib.cdc import ResetSynchronizer
 from amaranth.vendor import LatticeICE40Platform
 
-from ..build_plan import GatewareBuildError
 from . import GlasgowPlatform
 
 
@@ -12,100 +10,3 @@
 class GlasgowICE40Platform(GlasgowPlatform, LatticeICE40Platform):
     def bitstream_filename(self, design_name):
         return f"{design_name}.bin"
-
-    def get_pll(self, pll, simple_feedback=True):
-        if not 10e6 <= pll.f_in <= 133e6:
-            pll.logger.error("PLL: f_in (%.3f MHz) must be between 10 and 133 MHz",
-                             pll.f_in / 1e6)
-            raise GatewareBuildError("PLL f_in out of range")
-
-        if not 16e6 <= pll.f_out <= 275e6:
-            pll.logger.error("PLL: f_out (%.3f MHz) must be between 16 and 275 MHz",
-                             pll.f_out / 1e6)
-            raise GatewareBuildError("PLL f_out out of range")
-
-        # The documentation in the iCE40 PLL Usage Guide incorrectly lists the
-        # maximum value of DIVF as 63, when it is only limited to 63 when using
-        # feedback modes other that SIMPLE.
-        if simple_feedback:
-            divf_max = 128
-        else:
-            divf_max = 64
-
-        variants = []
-        for divr in range(0, 16):
-            f_pfd = pll.f_in / (divr + 1)
-            if not 10e6 <= f_pfd <= 133e6:
-                continue
-
-            for divf in range(0, divf_max):
-                if simple_feedback:
-                    f_vco = f_pfd * (divf + 1)
-                    if not 533e6 <= f_vco <= 1066e6:
-                        continue
-
-                    for divq in range(1, 7):
-                        f_out = f_vco * (2 ** -divq)
-                        variants.append((divr, divf, divq, f_pfd, f_out))
-
-                else:
-                    for divq in range(1, 7):
-                        f_vco = f_pfd * (divf + 1) * (2 ** divq)
-                        if not 533e6 <= f_vco <= 1066e6:
-                            continue
-
-                        f_out = f_vco * (2 ** -divq)
-                        variants.append((divr, divf, divq, f_pfd, f_out))
-
-        if not variants:
-            pll.logger.error("PLL: f_in (%.3f MHz) to f_out (%.3f) constraints not satisfiable",
-                             pll.f_in / 1e6, pll.f_out / 1e6)
-            raise GatewareBuildError("PLL f_in/f_out out of range")
-
-        def f_out_diff(variant):
-            *_, f_out = variant
-            return abs(f_out - pll.f_out)
-        divr, divf, divq, f_pfd, f_out = min(variants, key=f_out_diff)
-
-        if f_pfd < 17:
-            filter_range = 1
-        elif f_pfd < 26:
-            filter_range = 2
-        elif f_pfd < 44:
-            filter_range = 3
-        elif f_pfd < 66:
-            filter_range = 4
-        elif f_pfd < 101:
-            filter_range = 5
-        else:
-            filter_range = 6
-
-        if simple_feedback:
-            feedback_path = "SIMPLE"
-        else:
-            feedback_path = "NON_SIMPLE"
-
-        ppm = abs(pll.f_out - f_out) / pll.f_out * 1e6
-
-        pll.logger.debug("PLL: f_in=%.3f f_out(req)=%.3f f_out(act)=%.3f [MHz] ppm=%d",
-                         pll.f_in / 1e6, pll.f_out / 1e6, f_out / 1e6, ppm)
-        pll.logger.trace("iCE40 PLL: feedback_path=%s divr=%d divf=%d divq=%d filter_range=%d",
-                         feedback_path, divr, divf, divq, filter_range)
-
-        m = Module()
-        locked = Signal()
-        m.submodules.reset_sync = ResetSynchronizer(~locked, domain=pll.odomain)
-        m.submodules.pll_core = Instance("SB_PLL40_CORE",
-            p_FEEDBACK_PATH=feedback_path,
-            p_PLLOUT_SELECT="GENCLK",
-            p_DIVR=divr,
-            p_DIVF=divf,
-            p_DIVQ=divq,
-            p_FILTER_RANGE=filter_range,
-            i_REFERENCECLK=ClockSignal(pll.idomain),
-            o_PLLOUTCORE=ClockSignal(pll.odomain),
-            i_RESETB=~ResetSignal(pll.idomain),
-            o_LOCK=locked,
-            i_BYPASS=Const(0),
-        )
-        return m