From 1369f6f8c0e95d604749be9ab001f8d485ab4aa8 Mon Sep 17 00:00:00 2001 From: kirbyydoge Date: Tue, 23 May 2023 19:30:08 +0300 Subject: [PATCH 1/5] Add ZC706 Vivado Project --- .../ZC706/ZC706.srcs/sim_1/tb_instr_mem.v | 80 + .../ZC706/ZC706.srcs/sim_1/tb_pcie_top.sv | 349 + .../ZC706.srcs/sim_1/tb_pcie_txn_buffer.v | 101 + .../axis_clock_converter.xci | 133 + .../sources_1/ip/data_fifo/data_fifo.xci | 594 + .../ip/instr_blk_mem/instr_blk_mem.xci | 316 + .../instr_blk_mem_sim/instr_blk_mem_sim.xci | 319 + .../sources_1/ip/instr_fifo/instr_fifo.xci | 593 + .../pcie_7x_0/doc/pcie_7x_v3_3_changelog.txt | 280 + .../sources_1/ip/pcie_7x_0/pcie_7x_0.dcp | Bin 0 -> 1227449 bytes .../sources_1/ip/pcie_7x_0/pcie_7x_0.veo | 240 + .../sources_1/ip/pcie_7x_0/pcie_7x_0.vho | 425 + .../sources_1/ip/pcie_7x_0/pcie_7x_0.xci | 631 + .../sources_1/ip/pcie_7x_0/pcie_7x_0.xml | 12604 +++ .../ip/pcie_7x_0/pcie_7x_0_sim_netlist.v | 66137 +++++++++++++ .../ip/pcie_7x_0/pcie_7x_0_sim_netlist.vhdl | 79081 ++++++++++++++++ .../sources_1/ip/pcie_7x_0/pcie_7x_0_stub.v | 241 + .../ip/pcie_7x_0/pcie_7x_0_stub.vhdl | 205 + .../sources_1/ip/pcie_7x_0/sim/pcie_7x_0.v | 1096 + .../pcie_7x_0/source/pcie_7x_0-PCIE_X0Y0.xdc | 156 + .../pcie_7x_0/source/pcie_7x_0_axi_basic_rx.v | 212 + .../source/pcie_7x_0_axi_basic_rx_null_gen.v | 383 + .../source/pcie_7x_0_axi_basic_rx_pipeline.v | 623 + .../source/pcie_7x_0_axi_basic_top.v | 282 + .../pcie_7x_0/source/pcie_7x_0_axi_basic_tx.v | 260 + .../source/pcie_7x_0_axi_basic_tx_pipeline.v | 543 + .../source/pcie_7x_0_axi_basic_tx_thrtl_ctl.v | 784 + .../ip/pcie_7x_0/source/pcie_7x_0_core_top.v | 2152 + .../ip/pcie_7x_0/source/pcie_7x_0_gt_common.v | 166 + .../source/pcie_7x_0_gt_rx_valid_filter_7x.v | 285 + .../ip/pcie_7x_0/source/pcie_7x_0_gt_top.v | 1027 + .../pcie_7x_0/source/pcie_7x_0_gt_wrapper.v | 2369 + .../source/pcie_7x_0_gtp_cpllpd_ovrd.v | 68 + .../pcie_7x_0/source/pcie_7x_0_gtp_pipe_drp.v | 370 + .../source/pcie_7x_0_gtp_pipe_rate.v | 461 + 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.../pcie_7x_0/source/pcie_7x_0_qpll_reset.v | 370 + .../pcie_7x_0/source/pcie_7x_0_qpll_wrapper.v | 439 + .../ip/pcie_7x_0/source/pcie_7x_0_rxeq_scan.v | 366 + .../sources_1/ip/pcie_7x_0/synth/pcie_7x_0.v | 1106 + .../ip/pcie_7x_0/synth/pcie_7x_0_ooc.xdc | 76 + .../ip/pcie_7x_0/sys_clk_gen_ps_v.txt | 1 + .../sources_1/ip/pr_read_mem/pr_read_mem.xci | 318 + .../sources_1/ip/pr_ref_mem/pr_ref_mem.xci | 319 + .../sources_1/ip/rdback_fifo/rdback_fifo.xci | 585 + .../sources_1/ip/scratchpad/scratchpad.xci | 316 + .../ip/zq_calib_mem/zq_calib_mem.xci | 319 + projects/ZC706/ZC706.xpr | 1194 + projects/ZC706/coe/pr_read.coe | 15 + projects/ZC706/coe/pr_ref.coe | 51 + projects/ZC706/coe/pr_zq.coe | 42 + projects/ZC706/coe/simmem.coe | 398 + projects/ZC706/constraints/SODIMM.xdc | 819 + projects/ZC706/verilog/ddr3_adapter.v | 161 + projects/ZC706/verilog/instruction_buffer.v | 164 + projects/ZC706/verilog/pcie_app_7x.v | 207 + projects/ZC706/verilog/pcie_softmc_app.v | 957 + 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100644 projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_samp.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_oclkdelay_cal.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_prbs_rdlvl.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_rdlvl.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_tempmon.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_top.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_wrcal.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_wrlvl.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_prbs_gen.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_skip_calib_tap.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_infrastructure.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_iodelay_ctrl.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_poc_cc.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_poc_edge_store.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_poc_meta.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_poc_pd.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_poc_tap_base.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_poc_top.v create mode 100644 projects/ZC706/verilog/phy/mig_7series_v4_0_tempmon.v create mode 100644 projects/ZC706/verilog/project.vh create mode 100644 projects/ZC706/verilog/softmc_top.v create mode 100644 projects/ZC706/verilog/zc706_pcie_4x_gen2.v create mode 100644 projects/ZC706/verilog/zc706_pcie_4x_gen2_pipe_clock.v diff --git a/projects/ZC706/ZC706.srcs/sim_1/tb_instr_mem.v b/projects/ZC706/ZC706.srcs/sim_1/tb_instr_mem.v new file mode 100644 index 0000000..8417af0 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sim_1/tb_instr_mem.v @@ -0,0 +1,80 @@ +`timescale 1ns / 1ps + +module tb_instr_mem(); + +localparam FIFO_SCALE = 4; +localparam DATA_WIDTH = 64; +localparam KEEP_WIDTH = DATA_WIDTH / 8; + +reg clk; +reg reset; + +reg [DATA_WIDTH-1:0] s_axis_tdata; +reg s_axis_tvalid; +reg [KEEP_WIDTH-1:0] s_axis_tkeep; +wire s_axis_tready; + +wire [DATA_WIDTH*FIFO_SCALE-1:0] m_axis_tdata; +wire m_axis_tvalid; +reg m_axis_tready; + +instruction_buffer #( + .C_DATA_WIDTH(DATA_WIDTH), + .FIFO_WIDTH(FIFO_SCALE * DATA_WIDTH) +) uut( + .clk(clk), + .reset(reset), + .s_axis_tdata(s_axis_tdata), + .s_axis_tready(s_axis_tready), + .s_axis_tkeep(s_axis_tkeep), + .s_axis_tvalid(s_axis_tvalid), + .m_axis_tdata(m_axis_tdata), + .m_axis_tready(m_axis_tready), + .m_axis_tvalid(m_axis_tvalid) +); + +always begin + clk = 0; + #5; + clk = 1; + #5; +end + +localparam TEST_LEN = 16; +reg [DATA_WIDTH-1:0] data [0:TEST_LEN-1]; +reg [KEEP_WIDTH-1:0] data_keep [0:TEST_LEN-1]; + +integer i; +integer j; +initial begin + for (i = 0; i < TEST_LEN; i = i+1) begin + for (j = 0; j < 8; j = j+1) begin + data[i][(KEEP_WIDTH - j - 1) * 8 +: 8] = (8 * i + j) & 'hFF; + end + /* + data_keep[i] = i % 4 == 0 ? 'h0F : + i % 4 == 1 ? 'hF0 : + i % 4 == 2 ? 'h0F : 'hFF ; + */ + data_keep[i] = i == 0 ? 'h0F : 'hFF ; + end + reset = 1; + s_axis_tdata = 0; + s_axis_tvalid = 0; + m_axis_tready = 0; + repeat(10) begin @(posedge clk); end #1; + reset = 0; + for (i = 0; i < TEST_LEN;) begin + s_axis_tdata = data[i]; + s_axis_tkeep = data_keep[i]; + s_axis_tvalid = 1; + if (s_axis_tready && s_axis_tvalid) begin + i = i+1; + end + @(posedge clk) #1; + end + s_axis_tvalid = 0; + m_axis_tready = 1; +end + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sim_1/tb_pcie_top.sv b/projects/ZC706/ZC706.srcs/sim_1/tb_pcie_top.sv new file mode 100644 index 0000000..6a406a2 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sim_1/tb_pcie_top.sv @@ -0,0 +1,349 @@ +`timescale 1ns / 1ps + +module tb_pcie_top(); + +localparam SOFTMC_STREAM_WIDTH = 256; +localparam C_DATA_WIDTH = 64; +localparam C_ADDR_WIDTH = 64; +localparam KEEP_WIDTH = C_DATA_WIDTH / 8; + +reg user_clk; +reg user_reset; +reg user_lnk_up; + +reg [7:0] cfg_bus_number; +reg [4:0] cfg_device_number; +reg [2:0] cfg_function_number; +wire cfg_interrupt; +wire cfg_interrupt_assert; +reg cfg_interrupt_rdy; +wire [7:0] cfg_interrupt_di; +reg cfg_interrupt_msienable; + +wire m_axis_rx_tready; +reg [C_DATA_WIDTH-1:0] m_axis_rx_tdata; +reg [KEEP_WIDTH-1:0] m_axis_rx_tkeep; +reg m_axis_rx_tlast; +reg m_axis_rx_tvalid; +reg [21:0] m_axis_rx_tuser; +reg tx_src_dsc; + +wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata; +wire [KEEP_WIDTH-1:0] s_axis_tx_tkeep; +wire s_axis_tx_tlast; +wire s_axis_tx_tvalid; +reg s_axis_tx_tready; + +reg cfg_to_turnoff; +wire cfg_turnoff_ok; +reg [15:0] cfg_completer_id; + +wire [9:0] pci_cfg_dwaddr; +wire pci_cfg_rd_en; +wire [31:0] pci_cfg_dout; +wire pci_cfg_rd_wr_done; + +wire [15:0] cfg_dcommand; +reg [15:0] cfg_command; + +wire [SOFTMC_STREAM_WIDTH-1:0] softmc_h2c_tdata; +wire softmc_h2c_tvalid; +reg softmc_h2c_tready; +wire softmc_h2c_tlast; + +reg [SOFTMC_STREAM_WIDTH-1:0] softmc_c2h_tdata; +reg softmc_c2h_tvalid; +wire softmc_c2h_tready; +reg softmc_c2h_tlast; + +pcie_app_softmc uut( + .user_clk(user_clk), + .user_reset(user_reset), + .user_lnk_up(user_lnk_up), + + .softmc_h2c_tdata(softmc_h2c_tdata), + .softmc_h2c_tvalid(softmc_h2c_tvalid), + .softmc_h2c_tready(softmc_h2c_tready), + .softmc_h2c_tlast(softmc_h2c_tlast), + + .softmc_c2h_tdata(softmc_c2h_tdata), + .softmc_c2h_tvalid(softmc_c2h_tvalid), + .softmc_c2h_tready(softmc_c2h_tready), + .softmc_c2h_tlast(softmc_c2h_tlast), + + .cfg_bus_number(cfg_bus_number), + .cfg_device_number(cfg_device_number), + .cfg_function_number(cfg_function_number), + .cfg_interrupt(cfg_interrupt), + .cfg_interrupt_assert(cfg_interrupt_assert), + .cfg_interrupt_rdy(cfg_interrupt_rdy), + .cfg_interrupt_di(cfg_interrupt_di), + .cfg_interrupt_msienable(cfg_interrupt_msienable), + + .cfg_dcommand(cfg_dcommand), + .cfg_command(cfg_command), + + .pci_cfg_dwaddr(pci_cfg_dwaddr), + .pci_cfg_rd_en(pci_cfg_rd_en), + .pci_cfg_dout(pci_cfg_dout), + .pci_cfg_rd_wr_done(pci_cfg_rd_wr_done), + + .m_axis_rx_tready(m_axis_rx_tready), + .m_axis_rx_tdata(m_axis_rx_tdata), + .m_axis_rx_tkeep(m_axis_rx_tkeep), + .m_axis_rx_tlast(m_axis_rx_tlast), + .m_axis_rx_tvalid(m_axis_rx_tvalid), + .m_axis_rx_tuser(m_axis_rx_tuser), + + .tx_src_dsc(tx_src_dsc), + + .s_axis_tx_tdata(s_axis_tx_tdata), + .s_axis_tx_tkeep(s_axis_tx_tkeep), + .s_axis_tx_tlast(s_axis_tx_tlast), + .s_axis_tx_tvalid(s_axis_tx_tvalid), + .s_axis_tx_tready(s_axis_tx_tready), + + .cfg_to_turnoff(cfg_to_turnoff), + .cfg_turnoff_ok(cfg_turnoff_ok), + .cfg_completer_id(cfg_completer_id) +); + +always begin + user_clk = 0; + #5; + user_clk = 1; + #5; +end + + +// PCIe IP CFG Channel Simulation +localparam READ_LATENCY = 'd3; + +reg cfg_read_en; +reg cfg_read_en_prev; +wire cfg_read_en_spike; + +reg [31:0] cfg_dout [0:READ_LATENCY-1]; +reg cfg_rd_done [0:READ_LATENCY-1]; + +assign cfg_read_en_spike = cfg_read_en && !cfg_read_en_prev; +assign pci_cfg_dout = cfg_dout[0]; +assign pci_cfg_rd_wr_done = cfg_rd_done[0]; +assign cfg_dcommand = 'b0000_0000_0000_0000; + +integer j; +always @(posedge user_clk) begin + cfg_read_en <= pci_cfg_rd_en; + cfg_read_en_prev <= cfg_read_en; + cfg_dout[READ_LATENCY-1] <= pci_cfg_dwaddr == 'h04 ? 'hf0100000 : + pci_cfg_dwaddr == 'h05 ? 'hf0900000 : 'hffffffff; + cfg_rd_done[READ_LATENCY-1] <= cfg_read_en_spike; + for(j = 0; j < READ_LATENCY - 1; j = j + 1) begin + cfg_dout[j] <= cfg_dout[j+1]; + cfg_rd_done[j] <= cfg_rd_done[j+1]; + end +end + +// c2h data generator +localparam c2h_cap = 1024 * 8 * 8 / SOFTMC_STREAM_WIDTH; +reg [31:0] c2h_count; +reg [15:0] c2h_repeat; +always @(posedge user_clk) begin + if (user_reset) begin + softmc_c2h_tdata <= 0; + softmc_c2h_tvalid <= 0; + softmc_c2h_tlast <= 0; + c2h_repeat <= 0; + c2h_count <= 0; + end + else if (softmc_c2h_tready && softmc_c2h_tvalid) begin + softmc_c2h_tdata <= {(SOFTMC_STREAM_WIDTH/16){c2h_repeat}}; + softmc_c2h_tvalid <= c2h_count < (c2h_cap - 1); + softmc_c2h_tlast <= c2h_count == (c2h_cap - 2); + c2h_repeat <= c2h_repeat + (c2h_count < (c2h_cap - 1) ? 1 : 0); + c2h_count <= c2h_count + 1; + end + else if (!softmc_c2h_tvalid) begin + softmc_c2h_tdata <= {(SOFTMC_STREAM_WIDTH/16){c2h_repeat}}; + softmc_c2h_tvalid <= c2h_count < (c2h_cap); + softmc_c2h_tlast <= c2h_count == (c2h_cap - 1); + c2h_repeat <= c2h_repeat + (c2h_count < (c2h_cap) ? 1 : 0); + end +end + +always @(posedge user_clk) begin + if (cfg_interrupt) begin + cfg_command <= 'b0000_0100_0000_0100; + end + else begin + cfg_command <= 'b0000_0000_0000_0100; + end +end + +// TLPs +localparam CMD_LEN = 8; +localparam TEST_DATA_LEN = 10 + 2; // 20 Data + 3 Header -> 12 in DW pacets + +reg [C_DATA_WIDTH-1:0] tb_dw_queue [0:CMD_LEN-1]; +reg [KEEP_WIDTH-1:0] tb_keep_queue [0:CMD_LEN-1]; +reg tb_tlast_queue [0:CMD_LEN-1]; +reg [21:0] tb_user_queue [0:CMD_LEN-1]; + +reg [C_DATA_WIDTH-1:0] tb_cmp_queue [0:TEST_DATA_LEN-1]; +reg [KEEP_WIDTH-1:0] tb_cmp_keep_queue [0:TEST_DATA_LEN-1]; +reg tb_cmp_tlast_queue [0:TEST_DATA_LEN-1]; +reg [21:0] tb_cmp_user_queue [0:TEST_DATA_LEN-1]; + +integer i; +reg [7:0] data_repeat; +initial begin + softmc_h2c_tready = 0; + + tb_cmp_queue ['h00] = 'h0000000f_4a000014; + tb_cmp_keep_queue ['h00] = 'hff; + tb_cmp_tlast_queue ['h00] = 'h0; + tb_cmp_user_queue ['h00] = 'b00000000; + tb_cmp_queue ['h01] = 'h01010101_00000100; + tb_cmp_keep_queue ['h01] = 'hff; + tb_cmp_tlast_queue ['h01] = 'h0; + tb_cmp_user_queue ['h01] = 'b00000000; + for (i = 0; i < 9; i = i + 1) begin + data_repeat = 2 * i + 3; + tb_cmp_queue ['h02 + i][63:32] = {4{data_repeat}}; + data_repeat = 2 * i + 2; + tb_cmp_queue ['h02 + i][31:0] = {4{data_repeat}}; + tb_cmp_keep_queue ['h02 + i] = 'hff; + tb_cmp_tlast_queue ['h02 + i] = 'h0; + tb_cmp_user_queue ['h02 + i] = 'b00000000; + end + tb_cmp_queue ['h0b] = 'h00000000_14141414; + tb_cmp_keep_queue ['h0b] = 'h0f; + tb_cmp_tlast_queue ['h0b] = 'h1; + tb_cmp_user_queue ['h0b] = 'b00000000; + + tb_dw_queue ['h00] = 'h0000000f_40000001; + tb_keep_queue ['h00] = 'hff; + tb_tlast_queue ['h00] = 'h0; + tb_user_queue ['h00] = 'b00000100; + tb_dw_queue ['h01] = 'h000001f8_f0100008; + tb_keep_queue ['h01] = 'hff; + tb_tlast_queue ['h01] = 'h1; + tb_user_queue ['h01] = 'b00000100; + tb_dw_queue ['h02] = 'h0000000f_40000001; + tb_keep_queue ['h02] = 'hff; + tb_tlast_queue ['h02] = 'h0; + tb_user_queue ['h02] = 'b00000100; + tb_dw_queue ['h03] = 'h01000000_f0100004; + tb_keep_queue ['h03] = 'hff; + tb_tlast_queue ['h03] = 'h1; + tb_user_queue ['h03] = 'b00000100; + tb_dw_queue ['h04] = 'h0000000f_40000001; + tb_keep_queue ['h04] = 'hff; + tb_tlast_queue ['h04] = 'h0; + tb_user_queue ['h04] = 'b00000100; + tb_dw_queue ['h05] = 'h09005000_f0100000; + tb_keep_queue ['h05] = 'hff; + tb_tlast_queue ['h05] = 'h1; + tb_user_queue ['h05] = 'b00000100; + tb_dw_queue ['h06] = 'h0000000f_40000001; + tb_keep_queue ['h06] = 'hff; + tb_tlast_queue ['h06] = 'h0; + tb_user_queue ['h06] = 'b00000100; + tb_dw_queue ['h07] = 'h000002f8_f0100014; + tb_keep_queue ['h07] = 'hff; + tb_tlast_queue ['h07] = 'h1; + tb_user_queue ['h07] = 'b00000100; + + cfg_interrupt_msienable = 0; + + cfg_bus_number = 0; + cfg_device_number = 1; + cfg_function_number = 0; + cfg_interrupt_rdy = 0; + user_reset = 1; + user_lnk_up = 0; + m_axis_rx_tvalid = 0; + s_axis_tx_tready = 0; + #100; + @(posedge user_clk) #1; + user_reset = 0; + user_lnk_up = 1; + cfg_interrupt_rdy = 1; + s_axis_tx_tready = 1; + softmc_h2c_tready = 1; + + for (i = 0; i < CMD_LEN; ) begin + m_axis_rx_tdata = tb_dw_queue[i]; + m_axis_rx_tkeep = tb_keep_queue[i]; + m_axis_rx_tlast = tb_tlast_queue[i]; + m_axis_rx_tuser = tb_user_queue[i]; + m_axis_rx_tvalid = 1; + if (m_axis_rx_tready && m_axis_rx_tvalid) begin + i = i + 1; + end + @(posedge user_clk) #1; + end + m_axis_rx_tvalid = 0; + m_axis_rx_tlast = 0; + m_axis_rx_tkeep = 0; + + wait(s_axis_tx_tlast); + @(posedge user_clk) #1; + for (i = 0; i < TEST_DATA_LEN; ) begin + m_axis_rx_tdata = tb_cmp_queue[i]; + m_axis_rx_tkeep = tb_cmp_keep_queue[i]; + m_axis_rx_tlast = tb_cmp_tlast_queue[i]; + m_axis_rx_tuser = tb_cmp_user_queue[i]; + m_axis_rx_tvalid = 1; + if (m_axis_rx_tready && m_axis_rx_tvalid) begin + i = i + 1; + end + @(posedge user_clk) #1; + end + m_axis_rx_tvalid = 0; + m_axis_rx_tlast = 0; + m_axis_rx_tkeep = 0; + + wait(c2h_count == c2h_cap); + tb_dw_queue ['h00] = 'h0000000f_40000001; + tb_keep_queue ['h00] = 'hff; + tb_tlast_queue ['h00] = 'h0; + tb_user_queue ['h00] = 'b00000100; + tb_dw_queue ['h01] = 'h000002f8_f0100008; + tb_keep_queue ['h01] = 'hff; + tb_tlast_queue ['h01] = 'h1; + tb_user_queue ['h01] = 'b00000100; + tb_dw_queue ['h02] = 'h0000000f_40000001; + tb_keep_queue ['h02] = 'hff; + tb_tlast_queue ['h02] = 'h0; + tb_user_queue ['h02] = 'b00000100; + tb_dw_queue ['h03] = 'h01000000_f0100004; + tb_keep_queue ['h03] = 'hff; + tb_tlast_queue ['h03] = 'h1; + tb_user_queue ['h03] = 'b00000100; + tb_dw_queue ['h04] = 'h0000000f_40000001; + tb_keep_queue ['h04] = 'hff; + tb_tlast_queue ['h04] = 'h0; + tb_user_queue ['h04] = 'b00000100; + tb_dw_queue ['h05] = 'h03000020_f0100000; + tb_keep_queue ['h05] = 'hff; + tb_tlast_queue ['h05] = 'h1; + tb_user_queue ['h05] = 'b00000100; + + for (i = 0; i < CMD_LEN; ) begin + m_axis_rx_tdata = tb_dw_queue[i]; + m_axis_rx_tkeep = tb_keep_queue[i]; + m_axis_rx_tlast = tb_tlast_queue[i]; + m_axis_rx_tuser = tb_user_queue[i]; + m_axis_rx_tvalid = 1; + if (m_axis_rx_tready && m_axis_rx_tvalid) begin + i = i + 1; + end + @(posedge user_clk) #1; + end + m_axis_rx_tvalid = 0; + m_axis_rx_tlast = 0; + m_axis_rx_tkeep = 0; +end + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sim_1/tb_pcie_txn_buffer.v b/projects/ZC706/ZC706.srcs/sim_1/tb_pcie_txn_buffer.v new file mode 100644 index 0000000..8fc4050 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sim_1/tb_pcie_txn_buffer.v @@ -0,0 +1,101 @@ +`timescale 1ns / 1ps + +module tb_pcie_txn_buffer(); + +localparam C_IN_DATA_WIDTH = 128; +localparam C_OUT_DATA_WIDTH = 64; +localparam C_IN_KEEP = C_IN_DATA_WIDTH / 8; +localparam C_OUT_KEEP = C_OUT_DATA_WIDTH / 8; +localparam DATA_COUNT_WIDTH = 32; + +reg clk; +reg reset; +reg [C_IN_DATA_WIDTH-1:0] s_axis_tdata; +reg [C_IN_KEEP-1:0] s_axis_tkeep; +reg s_axis_tvalid; +wire s_axis_tready; +reg s_axis_tlast; +wire [C_OUT_DATA_WIDTH-1:0] m_axis_tdata; +wire [C_OUT_DATA_WIDTH/2-1:0] m_axis_upper_half_data; +wire [C_OUT_KEEP-1:0] m_axis_tkeep; +wire [C_OUT_KEEP/2-1:0] m_axis_upper_half_keep; +wire m_axis_tvalid; +wire m_axis_upper_half_valid; +reg m_axis_tready; +reg m_axis_upper_half_ready; +wire [DATA_COUNT_WIDTH-1:0] data_count; +wire programmed_stop; + +pcie_txn_buffer #( + .C_IN_DATA_WIDTH(C_IN_DATA_WIDTH), + .C_OUT_DATA_WIDTH(C_OUT_DATA_WIDTH) +) uut ( + .clk(clk), + .reset(reset), + .s_axis_tdata(s_axis_tdata), + .s_axis_tkeep(s_axis_tkeep), + .s_axis_tvalid(s_axis_tvalid), + .s_axis_tready(s_axis_tready), + .s_axis_tlast(s_axis_tlast), + .m_axis_tdata(m_axis_tdata), + .m_axis_upper_half_data(m_axis_upper_half_data), + .m_axis_tkeep(m_axis_tkeep), + .m_axis_upper_half_keep(m_axis_upper_half_keep), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_upper_half_valid(m_axis_upper_half_valid), + .m_axis_tready(m_axis_tready), + .m_axis_upper_half_ready(m_axis_upper_half_ready), + .data_count(data_count), + .programmed_stop(programmed_stop) +); + +always begin + clk = 0; + #5; + clk = 1; + #5; +end + +integer i; + +localparam WRITE_LENGTH = 16; + +initial begin + s_axis_tdata = 0; + s_axis_tkeep = 0; + s_axis_tvalid = 0; + s_axis_tlast = 0; + m_axis_tready = 0; + m_axis_upper_half_ready = 0; + reset = 1; + repeat (10) @(posedge clk) #1; + reset = 0; + for (i = 0; i < WRITE_LENGTH;) begin + s_axis_tdata = {C_IN_KEEP{i[C_IN_KEEP-1:0]}}; + s_axis_tkeep = {C_IN_KEEP{1'b1}}; + s_axis_tvalid = 1; + if (s_axis_tready && s_axis_tvalid) begin + i = i + 1; + end + @(posedge clk) #2; + end + s_axis_tvalid = 0; + m_axis_tready = 0; + m_axis_upper_half_ready = 0; + wait(m_axis_tvalid); + @(posedge clk) #2; + m_axis_tready = 0; + m_axis_upper_half_ready = 1; + @(posedge clk) #2; + m_axis_tready = 1; + m_axis_upper_half_ready = 0; + wait(!m_axis_tvalid); + @(posedge clk) #2; + m_axis_tready = 1; + m_axis_upper_half_ready = 1; + repeat(5) @(posedge clk) #2; + m_axis_tready = 0; + m_axis_upper_half_ready = 0; +end + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci new file mode 100644 index 0000000..0a1221f --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci @@ -0,0 +1,133 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axis_clock_converter + + + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + ACTIVE_LOW + + + + 100000000 + 0 + 0 + 0.000 + 0 + ACTIVE_LOW + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + ACTIVE_LOW + + + + 100000000 + 0 + 0 + 0.000 + 0 + ACTIVE_LOW + 0 + 0b00000000000000000000000000011011 + 256 + 1 + 1 + 1 + zynq + 1 + 2 + 2 + 1 + 0 + 1:2 + axis_clock_converter + 1 + 1 + 0 + 1 + 2 + 32 + 0 + 0 + 0 + zynq + xilinx.com:zc706:part0:1.4 + + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 23 + TRUE + ../../../../ZC706.gen/sources_1/ip/axis_clock_converter + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/data_fifo/data_fifo.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/data_fifo/data_fifo.xci new file mode 100644 index 0000000..488039f --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/data_fifo/data_fifo.xci @@ -0,0 +1,594 @@ + + + xilinx.com + xci + unknown + 1.0 + + + data_fifo + + + + + + 100000000 + 0 + 0 + 0.000 + + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 1 + 0 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 1 + 0 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 256 + 1 + 1 + 32 + 32 + 1 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 1 + 0 + 10 + BlankString + 18 + 288 + 32 + 64 + 32 + 64 + 2 + 0 + 18 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + 2 + 1 + 2 + 0 + 1 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 4kx4 + 512x72 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 62 + 14 + 1022 + 14 + 1022 + 14 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 63 + 15 + 1023 + 15 + 1023 + 15 + 1021 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 64 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 6 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + data_fifo + 64 + false + 10 + false + false + 0 + 2 + 62 + 14 + 1022 + 14 + 1022 + 14 + 3 + false + false + true + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + true + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Block_RAM + 1 + 1022 + 63 + 15 + 1023 + 15 + 1023 + 15 + 1021 + false + true + false + 0 + AXI_STREAM + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 18 + 1024 + 64 + 16 + 1024 + 16 + 1024 + 16 + false + 18 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 32 + 0 + 0 + 32 + 32 + 0 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + xilinx.com:zc706:part0:1.4 + + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + ../../../../ZC706.gen/sources_1/ip/data_fifo + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci new file mode 100644 index 0000000..bf2af3a --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci @@ -0,0 +1,316 @@ + + + xilinx.com + xci + unknown + 1.0 + + + instr_blk_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.000 + 0 + 11 + 11 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 4 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 10.698001 mW + zynq + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + instr_blk_mem.mem + no_coe_file_loaded + 0 + 0 + 0 + 0 + 1 + 2048 + 2048 + 1 + 1 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 2048 + 2048 + WRITE_FIRST + WRITE_FIRST + 64 + 64 + zynq + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + no_coe_file_loaded + ALL + instr_blk_mem + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 2048 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + zynq + xilinx.com:zc706:part0:1.4 + + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + ../../../../ZC706.gen/sources_1/ip/instr_blk_mem + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xci new file mode 100644 index 0000000..7b74ab8 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xci @@ -0,0 +1,319 @@ + + + xilinx.com + xci + unknown + 1.0 + + + instr_blk_mem_sim + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.000 + 0 + 10 + 10 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 2 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 5.9043 mW + zynq + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + instr_blk_mem_sim.mem + instr_blk_mem_sim.mif + 0 + 1 + 0 + 0 + 1 + 1024 + 1024 + 1 + 1 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1024 + 1024 + WRITE_FIRST + WRITE_FIRST + 64 + 64 + zynq + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../coe/simmem.coe + ALL + instr_blk_mem_sim + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + true + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 1024 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + zynq + xilinx.com:zc706:part0:1.4 + + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + ../../../../ZC706.gen/sources_1/ip/instr_blk_mem_sim + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/instr_fifo/instr_fifo.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/instr_fifo/instr_fifo.xci new file mode 100644 index 0000000..83e0abc --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/instr_fifo/instr_fifo.xci @@ -0,0 +1,593 @@ + + + xilinx.com + xci + unknown + 1.0 + + + instr_fifo + + + + + + 100000000 + 0 + 0 + 0.000 + + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 256 + 1 + 1 + 32 + 32 + 1 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 1 + 0 + 10 + BlankString + 18 + 257 + 32 + 64 + 32 + 64 + 2 + 0 + 18 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + 2 + 1 + 2 + 0 + 1 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 4kx4 + 2kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 2046 + 14 + 1022 + 14 + 1022 + 14 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 2047 + 15 + 1023 + 15 + 1023 + 15 + 1021 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 2048 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 11 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + instr_fifo + 64 + false + 10 + false + false + 0 + 2 + 2046 + 14 + 1022 + 14 + 1022 + 14 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + true + true + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Block_RAM + 1 + 1022 + 2047 + 15 + 1023 + 15 + 1023 + 15 + 1021 + false + false + false + 0 + AXI_STREAM + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 18 + 1024 + 2048 + 16 + 1024 + 16 + 1024 + 16 + false + 18 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 32 + 0 + 0 + 32 + 32 + 0 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + xilinx.com:zc706:part0:1.4 + + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + ../../../../ZC706.gen/sources_1/ip/instr_fifo + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/doc/pcie_7x_v3_3_changelog.txt b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/doc/pcie_7x_v3_3_changelog.txt new file mode 100644 index 0000000..32c4ed5 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/doc/pcie_7x_v3_3_changelog.txt @@ -0,0 +1,280 @@ +2020.2: + * Version 3.3 (Rev. 14) + * General: Added Zynq 7z030i,7z035i,7z045i and 7z100i device support + +2020.1.1: + * Version 3.3 (Rev. 13) + * No changes + +2020.1: + * Version 3.3 (Rev. 13) + * Revision change in one or more subcores + +2019.2.2: + * Version 3.3 (Rev. 12) + * No changes + +2019.2.1: + * Version 3.3 (Rev. 12) + * No changes + +2019.2: + * Version 3.3 (Rev. 12) + * Revision change in one or more subcores + +2019.1.3: + * Version 3.3 (Rev. 11) + * No changes + +2019.1.2: + * Version 3.3 (Rev. 11) + * No changes + +2019.1.1: + * Version 3.3 (Rev. 11) + * No changes + +2019.1: + * Version 3.3 (Rev. 11) + * General: Added new device xa7k160t. + * Revision change in one or more subcores + +2018.3.1: + * Version 3.3 (Rev. 10) + * No changes + +2018.3: + * Version 3.3 (Rev. 10) + * Bug Fix: Fixed JTAG debugger Issue. + * Bug Fix: Added waviers for lint errors. + * Revision change in one or more subcores + +2018.2: + * Version 3.3 (Rev. 9) + * Bug Fix: Updated MSIX TABLE & PBA OFFSET parameters. Which effects MSI-X functionality + * Revision change in one or more subcores + +2018.1: + * Version 3.3 (Rev. 8) + * General: Added support for xa7a12t(cpg238,csg325) and xa7a25t(cpg238,csg325) devices + * Revision change in one or more subcores + +2017.4: + * Version 3.3 (Rev. 7) + * General: Removed 'xx' in the Interface values + * Revision change in one or more subcores + +2017.3: + * Version 3.3 (Rev. 6) + * Bug Fix: Updated arrow colors for JTAG debugger LTSSM graph + * Feature Enhancement: Enabled support for cpg238 package for devices - xc7a12t,xc7a12ti,xc7a12tl,xc7a25t,xc7z25ti and xc7a25tl + * Revision change in one or more subcores + +2017.2: + * Version 3.3 (Rev. 5) + * Revision change in one or more subcores + +2017.1: + * Version 3.3 (Rev. 4) + * Bug Fix: Removed unwanted display messages + * Bug Fix: Removed option to select 250Mhz of UserClk_freq (AXI Interface Frequency) for the devices xc7z015,xc7z15i and xc7z12s since the timing does not meet + * Feature Enhancement: Added JTAG debugger support to debug LTSSM, Reset sequence and Rx detect sequence.User option is added in the 'Add.Debug Options' GUI page + * Revision change in one or more subcores + +2016.4: + * Version 3.3 (Rev. 3) + * General: Added support for xc7a12tl and xc7a25tl devices + * Revision change in one or more subcores + +2016.3: + * Version 3.3 (Rev. 2) + * Bug Fix: Updated text in core configuration GUI to display Capabilities Register value as 0x0142 when Slot Implemented option is selected for Rootport Mode + * Other: Added support for xc7a12t,xc7a12t,xc7a25t,xc7a25ti and xc7z012s devices + * Revision change in one or more subcores + +2016.2: + * Version 3.3 (Rev. 1) + * Reduced the number of characters on a single line by making a multi-line attribute assignment. + * Added CDC registers to the pl_phy_lnk_up and pl_received_hot_rst PCIe outputs. + * Revision change in one or more subcores + +2016.1: + * Version 3.3 + * Modified the width of pipe_tx_*_sigs, common_commands_in and common_commands_out + * Added Tandem support for xc7z035 + * Modified the mapping of logical and physical external pipe interface ports for End Point configurations so that it can be connected to Root Port instance directly + * Fixed issue with the default values of 'Base Class Menu' and 'Sub Class Interface Menu' and 'Class Code' update when Lookup Assistant option is used + * Removed the dependency of 'Include Shared Logic(clocking)in example design' on 'External PIPE Interface' pipe mode simulation option.No changes made to the 'Enable Pipe mode Simulation' option + * Revision change in one or more subcores + +2015.4.2: + * Version 3.2 (Rev. 1) + * No changes + +2015.4.1: + * Version 3.2 (Rev. 1) + * No changes + +2015.4: + * Version 3.2 (Rev. 1) + * Fixed unresolved instances of sys_clk_gen used in pipe mode simulations. This module is now delivered in 'source' directory + +2015.3: + * Version 3.2 + * For EXTERNAL PIPE INTERFACE mode, a new file xil_sig2pipe.v is delivered in the simulation directory and it replaces the phy_sig_gen.v. BFM/VIP’s should interface with the xil_sig2pipe instance in board.v + * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances + * Revision change in one or more subcores + +2015.2.1: + * Version 3.1 (Rev. 1) + * No changes + +2015.2: + * Version 3.1 (Rev. 1) + * Fixed GTP DRP write issue - (Xilinx Answer 62770) + * Added support for xq7z100 device + * Added support for Post Synthesis/Implementation netlist simulation for EP/Verilog mode, for non-PIPE mode only + +2015.1: + * Version 3.1 + * Added support for xc7a35ti,xc7a50ti,xc7a75ti,xc7a100ti and xc7a200ti devices. + * Added non-default input port pipe_txinhibit. + * Fixed issue with invalid link width and speeds for -1 speed grade for devices xc7z030i and xc7z015i devices (x8 is not supported and incase of xc7z015i only Gen1 speeds are supported when speedgrade -1 is selected). + * Added support for new packages: fbv484,fbv676,ffv1156,ffv900,fbv900 and ffv901 + * Added shared logic support for RP configuration. + * Modified the External Pipe Interface as Master for Rootport configuration and Slave for Endpoint and Legacy Endpoint configurations. + * Update to generate a 100MHz icap_clk for tandem configurations rather than using the ref_clk input. + * Removed 250Mhz User clock frequency option for all -1,-1I,-1M,-1Q,-1L speedgrades of Artix7 family. + +2014.4.1: + * Version 3.0 (Rev. 4) + * No changes + +2014.4: + * Version 3.0 (Rev. 4) + * Enhancement to allow debug cores to work better within Tandem designs. Build_stage1.tcl now runs befor place_design and handles bscan primitives. + * Added support for Artix7 xc7a15t, xc7a15tl and xa7a15t devices + * Added support for Zynq xc7z035 device + * Changed the pipe mode simulation options in GUI to radio buttons (No change in the functionality) + +2014.3: + * Version 3.0 (Rev. 3) + * Enabled PIPE Sim support for Root Port configuration + * Added support for Kintex7 Low voltage (0.9v) variants, for only Gen1 speed + * Added support for Kintex7 Defense grade Low voltage (0.9v) variants, for only Gen1 speed + * Fixed CPLL Power spike on power up issue (AR59294) + +2014.2: + * Version 3.0 (Rev. 2) + * Added AZynq7030 device support + * Added QArtix 50t device support + * Enabled PIPE simulation and External PIPE interface support only when shared logic option Shared Logic (clocking) in example design is selected + +2014.1: + * Version 3.0 (Rev. 1) + * Added Zynq7015 device support + * Added 35t,50t and 75t support for Artix7l and Aartix7 devices + * Added cpg236 and csg325 packages support for Artix7 devices + * Enabled Tandem PROM configuration support for Zynq 7030 and for Zynq7045 devices + * Enabled Tandem Configuration support for Kintex 420T device + * Changed the directory structure of the core without affecting the design hierarchy + +2013.4: + * Version 3.0 + * Added XC7Z200TSBG484 device support + * Added support Artix7 35t, 50t and 75t devices + * Added port level enablement for icap and startup signal interfaces + * Added 3 new ports - pipe_rxstatus, pipe_eyescandataerror and pipe_dmonitordout to the transceiver debug interface + * Added logic to power down CPLL until it is required during the PCIe link bring-up + +2013.3: + * Version 2.2 + * Reduced Warnings in Simulations + * Reduced Warnings in Synthesis + * Implemented Shared Logic for Clocking and Transeciver GT Common blocks to include either in core or example design + * Implemented Tarnsceiver Core Debug interface. Brought the debug signals to the port level + * Brought the Ext GT DRP signals upto the core top port level + * Added support for IPI integrator + * Updated xdc to match IP hierarchy + * Added support for Cadence IES and Synopsys VCS Simulators + * Added support for upgrade from previous versions + * Added support for Zynq 7100 device + * Added new pages Shared Logic and Core interface Parameters in GUI in Advanced mode + * Added Enablement of PCIe DRP interface and made the option true by default + * PCIe Sideband interface is broken into several smaller interfaces to connect with DMA IP in IPI + * Added support for External PIPE interface mode + +2013.2: + * Version 2.1 + * Enhancements in the Tandem Logic - added STARTUP Premitive and new ports related to this premitive (static ports) + * Removed the redundant blocks related to Tandem configuration logic + * Added AER_CAP_ECRC_GEN_CAPABLE parameter in XGUI + * Added option to select the Internal or external clocking module (Parameter PCIE_EXT_CLK) + * Marked Artix7 (fgg484 and fbg484) and Zynq devices as production. Added GES_and_Production option for Silicon_Rev parameter. Updated the Auto-Upgrade Script + * Added support for Artix7 and Kintex7 Lowvoltage family + * Shortened the example design xdc file name (PG updated) + * IPI Level 0 Support + * Added OOC flow support + * Fixed CDC issues with GT wrappers + * Removed the BETA tag for Tandem PROM and Tandem PCIe options + * For x8g1, 128-bit interface width configuration, Removed the optional 250MHz. Updated the Auto-upgrade script + +2013.1: + * Version 2.0 + * Lower case ports for Verilog + * Added Zynq Support + * Fixed Reset Sequence issue with GTPs + * Fixed TXOUTCLK flatline issue + * Fixed the issue with GUI to select the optional frequency for g2x4, 128-bit configuration. Now the selection for 250Mhz optional frequency is removed as it is not supported configuration + * Fixed XSIM issues with VHDL version of the core + * Changed upper case portlevel signals to lower case (clocking interface for partial re-configuration and ICAP interface) + * Added pipe_mmcm_rst_n signal at the port level as input in the core top file. + * All Kintex devices, Virtex 2000T, Artix 100t/ffg676, 200T/fbg676,ffg1156 are marked as Production. Option is added in GUI to select GES_and_Production + * Tandem Configuration - The option is enabled independent of the Dev board selection for Kintex 325/ffg900 and Virtex 485/ffg1761/PCIe Block X1Y0 + * Tandem Confguration - Create Bin files for stage 2, Back Up & restore of bitstream generation settings + +(c) Copyright 2002 - 2020 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.dcp b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..34352e386a73eda5148572eee25a0c93c2bacf04 GIT binary patch literal 1227449 zcmaHyb97}*x9($gj1D{L*xIpeCmq|iZQHgwwr$(Cla8&Me&6$rd+t4V+&|V>RnMOF z)Eaw?U2Fbo)|Qn31w#b_0)hhSwz&JnQ<8a&h64>Glr&|WO1ixF>vqw%^<&)cPR#<{pp}t^oKvUuIlx z-%(y&M!daW4exC}I&A5%L?$2zy*(XoMfA^hm$aoXF`>IMK5y49@Va2FX*=yuAG>h0 zxNtn*@5bo1{*L?2 zmFv4rrUs{mGPDOE*A#41bEBfN%1TM`WmQH<`=vx&?nsRMrT>M4g^AE~gOv1QQ&jnK z@*9b0*ae!}D3!s*TW8OXL!W-d(Seow1yUD=tTU2g5YVjMs+ zwnN2sg0O3f_BcAWxI4l()*B=RZXk>h>q5qH4dk_Ua34dJ?m9FeKX{r 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zAX*)O1|qa(<|P-Q>s3Fn pci_exp_txp, + pci_exp_txn => pci_exp_txn, + pci_exp_rxp => pci_exp_rxp, + pci_exp_rxn => pci_exp_rxn, + pipe_pclk_in => pipe_pclk_in, + pipe_rxusrclk_in => pipe_rxusrclk_in, + pipe_rxoutclk_in => pipe_rxoutclk_in, + pipe_dclk_in => pipe_dclk_in, + pipe_userclk1_in => pipe_userclk1_in, + pipe_userclk2_in => pipe_userclk2_in, + pipe_oobclk_in => pipe_oobclk_in, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_txoutclk_out => pipe_txoutclk_out, + pipe_rxoutclk_out => pipe_rxoutclk_out, + pipe_pclk_sel_out => pipe_pclk_sel_out, + pipe_gen3_out => pipe_gen3_out, + user_clk_out => user_clk_out, + user_reset_out => user_reset_out, + user_lnk_up => user_lnk_up, + user_app_rdy => user_app_rdy, + tx_buf_av => tx_buf_av, + tx_cfg_req => tx_cfg_req, + tx_err_drop => tx_err_drop, + s_axis_tx_tready => s_axis_tx_tready, + s_axis_tx_tdata => s_axis_tx_tdata, + s_axis_tx_tkeep => s_axis_tx_tkeep, + s_axis_tx_tlast => s_axis_tx_tlast, + s_axis_tx_tvalid => s_axis_tx_tvalid, + s_axis_tx_tuser => s_axis_tx_tuser, + tx_cfg_gnt => tx_cfg_gnt, + m_axis_rx_tdata => m_axis_rx_tdata, + m_axis_rx_tkeep => m_axis_rx_tkeep, + m_axis_rx_tlast => m_axis_rx_tlast, + m_axis_rx_tvalid => m_axis_rx_tvalid, + m_axis_rx_tready => m_axis_rx_tready, + m_axis_rx_tuser => m_axis_rx_tuser, + rx_np_ok => rx_np_ok, + rx_np_req => rx_np_req, + fc_cpld => fc_cpld, + fc_cplh => fc_cplh, + fc_npd => fc_npd, + fc_nph => fc_nph, + fc_pd => fc_pd, + fc_ph => fc_ph, + fc_sel => fc_sel, + cfg_mgmt_do => cfg_mgmt_do, + cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done, + cfg_status => cfg_status, + cfg_command => cfg_command, + cfg_dstatus => cfg_dstatus, + cfg_dcommand => cfg_dcommand, + cfg_lstatus => cfg_lstatus, + cfg_lcommand => cfg_lcommand, + cfg_dcommand2 => cfg_dcommand2, + cfg_pcie_link_state => cfg_pcie_link_state, + cfg_pmcsr_pme_en => cfg_pmcsr_pme_en, + cfg_pmcsr_powerstate => cfg_pmcsr_powerstate, + cfg_pmcsr_pme_status => cfg_pmcsr_pme_status, + cfg_received_func_lvl_rst => cfg_received_func_lvl_rst, + cfg_mgmt_di => cfg_mgmt_di, + cfg_mgmt_byte_en => cfg_mgmt_byte_en, + cfg_mgmt_dwaddr => cfg_mgmt_dwaddr, + cfg_mgmt_wr_en => cfg_mgmt_wr_en, + cfg_mgmt_rd_en => cfg_mgmt_rd_en, + cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly, + cfg_err_ecrc => cfg_err_ecrc, + cfg_err_ur => cfg_err_ur, + cfg_err_cpl_timeout => cfg_err_cpl_timeout, + cfg_err_cpl_unexpect => cfg_err_cpl_unexpect, + cfg_err_cpl_abort => cfg_err_cpl_abort, + cfg_err_posted => cfg_err_posted, + cfg_err_cor => cfg_err_cor, + cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked, + cfg_err_internal_cor => cfg_err_internal_cor, + cfg_err_malformed => cfg_err_malformed, + cfg_err_mc_blocked => cfg_err_mc_blocked, + cfg_err_poisoned => cfg_err_poisoned, + cfg_err_norecovery => cfg_err_norecovery, + cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header, + cfg_err_cpl_rdy => cfg_err_cpl_rdy, + cfg_err_locked => cfg_err_locked, + cfg_err_acs => cfg_err_acs, + cfg_err_internal_uncor => cfg_err_internal_uncor, + cfg_trn_pending => cfg_trn_pending, + cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s, + cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1, + cfg_pm_force_state_en => cfg_pm_force_state_en, + cfg_pm_force_state => cfg_pm_force_state, + cfg_dsn => cfg_dsn, + cfg_interrupt => cfg_interrupt, + cfg_interrupt_rdy => cfg_interrupt_rdy, + cfg_interrupt_assert => cfg_interrupt_assert, + cfg_interrupt_di => cfg_interrupt_di, + cfg_interrupt_do => cfg_interrupt_do, + cfg_interrupt_mmenable => cfg_interrupt_mmenable, + cfg_interrupt_msienable => cfg_interrupt_msienable, + cfg_interrupt_msixenable => cfg_interrupt_msixenable, + cfg_interrupt_msixfm => cfg_interrupt_msixfm, + cfg_interrupt_stat => cfg_interrupt_stat, + cfg_pciecap_interrupt_msgnum => cfg_pciecap_interrupt_msgnum, + cfg_to_turnoff => cfg_to_turnoff, + cfg_turnoff_ok => cfg_turnoff_ok, + cfg_bus_number => cfg_bus_number, + cfg_device_number => cfg_device_number, + cfg_function_number => cfg_function_number, + cfg_pm_wake => cfg_pm_wake, + cfg_pm_send_pme_to => cfg_pm_send_pme_to, + cfg_ds_bus_number => cfg_ds_bus_number, + cfg_ds_device_number => cfg_ds_device_number, + cfg_ds_function_number => cfg_ds_function_number, + cfg_mgmt_wr_rw1c_as_rw => cfg_mgmt_wr_rw1c_as_rw, + cfg_msg_received => cfg_msg_received, + cfg_msg_data => cfg_msg_data, + cfg_bridge_serr_en => cfg_bridge_serr_en, + cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse, + cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en, + cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en, + cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en, + cfg_root_control_pme_int_en => cfg_root_control_pme_int_en, + cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en, + cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en, + cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en, + cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received, + cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received, + cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received, + cfg_msg_received_err_cor => cfg_msg_received_err_cor, + cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal, + cfg_msg_received_err_fatal => cfg_msg_received_err_fatal, + cfg_msg_received_pm_as_nak => cfg_msg_received_pm_as_nak, + cfg_msg_received_pm_pme => cfg_msg_received_pm_pme, + cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack, + cfg_msg_received_assert_int_a => cfg_msg_received_assert_int_a, + cfg_msg_received_assert_int_b => cfg_msg_received_assert_int_b, + cfg_msg_received_assert_int_c => cfg_msg_received_assert_int_c, + cfg_msg_received_assert_int_d => cfg_msg_received_assert_int_d, + cfg_msg_received_deassert_int_a => cfg_msg_received_deassert_int_a, + cfg_msg_received_deassert_int_b => cfg_msg_received_deassert_int_b, + cfg_msg_received_deassert_int_c => cfg_msg_received_deassert_int_c, + cfg_msg_received_deassert_int_d => cfg_msg_received_deassert_int_d, + cfg_msg_received_setslotpowerlimit => cfg_msg_received_setslotpowerlimit, + pl_directed_link_change => pl_directed_link_change, + pl_directed_link_width => pl_directed_link_width, + pl_directed_link_speed => pl_directed_link_speed, + pl_directed_link_auton => pl_directed_link_auton, + pl_upstream_prefer_deemph => pl_upstream_prefer_deemph, + pl_sel_lnk_rate => pl_sel_lnk_rate, + pl_sel_lnk_width => pl_sel_lnk_width, + pl_ltssm_state => pl_ltssm_state, + pl_lane_reversal_mode => pl_lane_reversal_mode, + pl_phy_lnk_up => pl_phy_lnk_up, + pl_tx_pm_state => pl_tx_pm_state, + pl_rx_pm_state => pl_rx_pm_state, + pl_link_upcfg_cap => pl_link_upcfg_cap, + pl_link_gen2_cap => pl_link_gen2_cap, + pl_link_partner_gen2_supported => pl_link_partner_gen2_supported, + pl_initial_link_width => pl_initial_link_width, + pl_directed_change_done => pl_directed_change_done, + pl_received_hot_rst => pl_received_hot_rst, + pl_transmit_hot_rst => pl_transmit_hot_rst, + pl_downstream_deemph_source => pl_downstream_deemph_source, + cfg_err_aer_headerlog => cfg_err_aer_headerlog, + cfg_aer_interrupt_msgnum => cfg_aer_interrupt_msgnum, + cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set, + cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en, + cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en, + cfg_vc_tcvc_map => cfg_vc_tcvc_map, + sys_clk => sys_clk, + sys_rst_n => sys_rst_n, + pipe_mmcm_rst_n => pipe_mmcm_rst_n, + pcie_drp_clk => pcie_drp_clk, + pcie_drp_en => pcie_drp_en, + pcie_drp_we => pcie_drp_we, + pcie_drp_addr => pcie_drp_addr, + pcie_drp_di => pcie_drp_di, + pcie_drp_do => pcie_drp_do, + pcie_drp_rdy => pcie_drp_rdy + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file pcie_7x_0.vhd when simulating +-- the core, pcie_7x_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.xci new file mode 100644 index 0000000..c708fa2 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.xci @@ -0,0 +1,631 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pcie_7x_0 + + + + + + 100000000 + 0 + 0 + 0.000 + + 0 + 0 + 0.000 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 22 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + TRUE + TRUE + TRUE + TRUE + 64 + FALSE + TRUE + FALSE + FALSE + FALSE + 4 + FALSE + TRUE + FALSE + FALSE + TRUE + TRUE + FALSE + FALSE + FALSE + FFFF0000 + 00000000 + 00000000 + 00000000 + 00000000 + 00000000 + 0 + 000 + FALSE + FALSE + FALSE + 000 + FALSE + 000000 + FALSE + TRUE + pcie_7x_0 + TRUE + TRUE + FALSE + 0010 + 2 + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + 00 + FALSE + 0 + TRUE + FALSE + FALSE + FALSE + FALSE + FALSE + 100 + TRUE + 000 + 00000000000 + 0 + 7 + 3FF + 973 + 36 + 24 + 12 + 949 + 32 + true + 00 + FALSE + 10C + FALSE + 0000 + FALSE + 0 + 0000 + FALSE + 1 + 0 + TRUE + FALSE + 0 + FALSE + FALSE + 00 + 0 + 0 + 0 + 0 + 000 + 3F + 0 + 00 + FALSE + TRUE + 0 + TRUE + 0 + 60 + 0F + 000 + 00 + 00 + 00 + 00 + 00 + 00 + 0 + 0 + 0 + 0 + 0 + 0 + 000 + FALSE + 00001 + 00001 + 00001 + 00001 + 00001 + 00001 + 0 + 0 + 0 + FALSE + FALSE + 0 + FFF + 2 + 0 + 2 + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + 0 + FALSE + FALSE + 0 + 0 + 2 + TRUE + 30 + 0 + 2 + 0 + TRUE + TRUE + FALSE + TRUE + TRUE + 000 + FALSE + FALSE + 000 + 000 + FALSE + 000 + ZC706 + 2 + 00000000 + 050000 + 3 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 7024 + 0000 + 0 + 0 + 0 + 0 + 0 + 000 + 111 + FALSE + 1 + TRUE + 2 + 000100 + 011 + TRUE + 3 + 0 + 00 + 0F + 00 + 00 + 00 + 00 + 00 + 00 + 00 + 00 + 00 + TRUE + 0007 + 10EE + 10EE + 00000000 + Absolute + 0000 + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + Maximum_of_64_ns + No_limit + false + 1M + 1M + 1M + 1M + 1M + 1M + 0 + 0 + 0 + 0 + 0 + 0 + false + true + false + Kilobytes + 64 + Memory + false + false + false + Megabytes + 1 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + Memory_controller + false + false + 00000000 + 05 + 00 + 00 + pcie_7x_0 + 1 + false + false + Range_B + true + 0 + 0 + 0 + 0 + true + 0 + 0 + 0 + 0 + false + true + 0 + 0 + 0 + 0 + false + 0 + 0 + 0 + 0 + false + true + true + -3.5 + 7024 + PCI_Express_Endpoint_device + false + false + false + false + 00 + false + 3FF + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + Kilobytes + 2 + false + false + false + false + Disabled + true + 64_bit + INTA + 5.0_GT/s + true + false + false + false + BAR_0 + 0 + BAR_0 + 0 + 1 + 1024_bytes + X4 + 1_vector + true + 000000 + false + 3F + X0Y0 + false + true + None + High + No_function_number_bits_used + Disabled + false + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 64_byte + 0 + false + Custom + true + 100_MHz + Add + 0000 + 00 + false + GES_and_Production + false + false + false + false + false + false + false + 0 + false + false + 0 + 0 + RAM + 0007 + 10EE + 00 + None + 4'h2 + false + true + true + false + true + false + 250 + false + false + false + 10EE + ZC706 + true + true + true + true + false + true + false + false + false + false + false + true + Basic + None + false + true + true + false + false + zynq + xilinx.com:zc706:part0:1.2 + + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 14 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.xml b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.xml new file mode 100644 index 0000000..0e2f8e2 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.xml @@ -0,0 +1,12604 @@ + + + xilinx.com + customized_ip + pcie_7x_0 + 1.0 + + + m_axis_rx + + + + + + + TDATA + + + m_axis_rx_tdata + + + + + TKEEP + + + m_axis_rx_tkeep + + + + + TLAST + + + m_axis_rx_tlast + + + + + TREADY + + + m_axis_rx_tready + + + + + TUSER + + + m_axis_rx_tuser + + + + + TVALID + + + m_axis_rx_tvalid + + + + + + TDATA_NUM_BYTES + 8 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 22 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + s_axis_tx + + + + + + + TDATA + + + s_axis_tx_tdata + + + + + TKEEP + + + s_axis_tx_tkeep + + + + + TLAST + + + s_axis_tx_tlast + + + + + TREADY + + + s_axis_tx_tready + + + + + TUSER + + + s_axis_tx_tuser + + + + + TVALID + + + s_axis_tx_tvalid + + + + + + TDATA_NUM_BYTES + 8 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 4 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 1 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + icap + icap + ICAP Interface + + + + + + + clk + + + icap_clk + + + + + csib + + + icap_csib + + + + + i + + + icap_i + + + + + o + + + icap_o + + + + + rdwrb + + + icap_rdwrb + + + + + + + false + + + + + + startup + startup + STARTUP Interface + + + + + + + cfgclk + + + startup_cfgclk + + + + + cfgmclk + + + startup_cfgmclk + + + + + clk + + + startup_clk + + + + + eos + + + startup_eos + + + + + gsr + + + startup_gsr + + + + + gts + + + startup_gts + + + + + keyclearb + + + startup_keyclearb + + + + + pack + + + startup_pack + + + + + preq + + + startup_preq + + + + + userdoneo + + + startup_usrdoneo + + + + + usrcclko + + + startup_usrcclko + + + + + usrclkts + + + startup_usrcclkts + + + + + usrdonets + + + startup_usrdonets + + + + + + + false + + + + + + pcie_7x_mgt + pcie_7x_mgt + PCI Express Serial Link + + + + + + + rxn + + + pci_exp_rxn + + + + + rxp + + + pci_exp_rxp + + + + + txn + + + pci_exp_txn + + + + + txp + + + pci_exp_txp + + + + + + pipe_clock + pipe_clock + PCIe External Pipe Clock + + + + + + + dclk_in + + + pipe_dclk_in + + + + + gen3_out + + + pipe_gen3_out + + + + + mmcm_lock_in + + + pipe_mmcm_lock_in + + + + + mmcm_rst_n + + + pipe_mmcm_rst_n + + + + + oobclk_in + + + pipe_oobclk_in + + + + + pclk_in + + + pipe_pclk_in + + + + + pclk_sel_out + + + pipe_pclk_sel_out + + + + + rxoutclk_in + + + pipe_rxoutclk_in + + + + + rxoutclk_out + + + pipe_rxoutclk_out + + + + + rxusrclk_in + + + pipe_rxusrclk_in + + + + + txoutclk_out + + + pipe_txoutclk_out + + + + + userclk1_in + + + pipe_userclk1_in + + + + + userclk2_in + + + pipe_userclk2_in + + + + + + + true + + + + + + drp + drp + DRP interface + + + + + + + DADDR + + + pcie_drp_addr + + + + + DEN + + + pcie_drp_en + + + + + DI + + + pcie_drp_di + + + + + DO + + + pcie_drp_do + + + + + DRDY + + + pcie_drp_rdy + + + + + DWE + + + pcie_drp_we + + + + + + + true + + + + + + CLK.sys_clk + CLK.sys_clk + sys_clk interface + + + + + + + CLK + + + sys_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + CLK.user_clk_out + CLK.user_clk_out + user_clk_out interface + + + + + + + CLK + + + user_clk_out + + + + + + ASSOCIATED_BUSIF + m_axis_rx:s_axis_tx + + + FREQ_HZ + 125000000 + + + ASSOCIATED_RESET + user_reset_out + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.sys_rst_n + RST.sys_rst_n + sys_rst_n interface + + + + + + + RST + + + sys_rst_n + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + RST.user_reset_out + RST.user_reset_out + user_reset_out Interface + + + + + + + RST + + + user_reset_out + + + + + + POLARITY + ACTIVE_HIGH + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + pcie2_cfg_err + pcie2_cfg_err + pcie config error for gen2 + + + + + + + acs + + + cfg_err_acs + + + + + aer_ecrc_check_en + + + cfg_aer_ecrc_check_en + + + + + aer_ecrc_gen_en + + + cfg_aer_ecrc_gen_en + + + + + aer_interrupt_msgnum + + + cfg_aer_interrupt_msgnum + + + + + atomic_egress_blocked + + + cfg_err_atomic_egress_blocked + + + + + cor + + + cfg_err_cor + + + + + cpl_abort + + + cfg_err_cpl_abort + + + + + cpl_rdy + + + cfg_err_cpl_rdy + + + + + cpl_timeout + + + cfg_err_cpl_timeout + + + + + cpl_unexpect + + + cfg_err_cpl_unexpect + + + + + ecrc + + + cfg_err_ecrc + + + + + err_aer_headerlog + + + cfg_err_aer_headerlog + + + + + err_aer_headerlog_set + + + cfg_err_aer_headerlog_set + + + + + internal_cor + + + cfg_err_internal_cor + + + + + internal_uncor + + + cfg_err_internal_uncor + + + + + locked + + + cfg_err_locked + + + + + malformed + + + cfg_err_malformed + + + + + mc_blocked + + + cfg_err_mc_blocked + + + + + norecovery + + + cfg_err_norecovery + + + + + poisoned + + + cfg_err_poisoned + + + + + posted + + + cfg_err_posted + + + + + tlp_cpl_header + + + cfg_err_tlp_cpl_header + + + + + ur + + + cfg_err_ur + + + + + + + true + + + + + + pcie2_cfg_interrupt + pcie2_cfg_interrupt + pcie config interrupt for gen2 + + + + + + + assert + + + cfg_interrupt_assert + + + + + interrupt + + + cfg_interrupt + + + + + mmenable + + + cfg_interrupt_mmenable + + + + + msienable + + + cfg_interrupt_msienable + + + + + msixenable + + + cfg_interrupt_msixenable + + + + + msixfm + + + cfg_interrupt_msixfm + + + + + pciecap_interrupt_msgnum + + + cfg_pciecap_interrupt_msgnum + + + + + rdy + + + cfg_interrupt_rdy + + + + + read_data + + + cfg_interrupt_do + + + + + stat + + + cfg_interrupt_stat + + + + + write_data + + + cfg_interrupt_di + + + + + + pcie2_cfg_status + pcie2_cfg_status + pcie config status for gen2 + + + + + + + aer_rooterr_corr_err_received + + + cfg_aer_rooterr_corr_err_received + + + + + aer_rooterr_corr_err_reporting_en + + + cfg_aer_rooterr_corr_err_reporting_en + + + + + aer_rooterr_fatal_err_received + + + cfg_aer_rooterr_fatal_err_received + + + + + aer_rooterr_fatal_err_reporting_en + + + cfg_aer_rooterr_fatal_err_reporting_en + + + + + aer_rooterr_non_fatal_err_received + + + cfg_aer_rooterr_non_fatal_err_received + + + + + aer_rooterr_non_fatal_err_reporting_en + + + cfg_aer_rooterr_non_fatal_err_reporting_en + + + + + bridge_serr_en + + + cfg_bridge_serr_en + + + + + bus_number + + + cfg_bus_number + + + + + command + + + cfg_command + + + + + dcommand + + + cfg_dcommand + + + + + dcommand2 + + + cfg_dcommand2 + + + + + device_number + + + cfg_device_number + + + + + dstatus + + + cfg_dstatus + + + + + function_number + + + cfg_function_number + + + + + lcommand + + + cfg_lcommand + + + + + lstatus + + + cfg_lstatus + + + + + pcie_link_state + + + cfg_pcie_link_state + + + + + pmcsr_pme_en + + + cfg_pmcsr_pme_en + + + + + pmcsr_pme_status + + + cfg_pmcsr_pme_status + + + + + pmcsr_powerstate + + + cfg_pmcsr_powerstate + + + + + received_func_lvl_rst + + + cfg_received_func_lvl_rst + + + + + root_control_pme_int_en + + + cfg_root_control_pme_int_en + + + + + root_control_syserr_corr_err_en + + + cfg_root_control_syserr_corr_err_en + + + + + root_control_syserr_fatal_err_en + + + cfg_root_control_syserr_fatal_err_en + + + + + root_control_syserr_non_fatal_err_en + + + cfg_root_control_syserr_non_fatal_err_en + + + + + slot_control_electromech_il_ctl_pulse + + + cfg_slot_control_electromech_il_ctl_pulse + + + + + status + + + cfg_status + + + + + turnoff + + + cfg_to_turnoff + + + + + tx_buf_av + + + tx_buf_av + + + + + tx_cfg_req + + + tx_cfg_req + + + + + tx_err_drop + + + tx_err_drop + + + + + vc_tcvc_map + + + cfg_vc_tcvc_map + + + + + + + true + + + + + + pcie_cfg_fc + pcie_cfg_fc + pcie config flowcontrol + + + + + + + CPLD + + + fc_cpld + + + + + CPLH + + + fc_cplh + + + + + NPD + + + fc_npd + + + + + NPH + + + fc_nph + + + + + PD + + + fc_pd + + + + + PH + + + fc_ph + + + + + SEL + + + fc_sel + + + + + + + true + + + + + + pcie2_cfg_control + pcie2_cfg_control + pcie config control for gen2 + + + + + + + ds_bus_number + + + cfg_ds_bus_number + + + + + ds_device_number + + + cfg_ds_device_number + + + + + ds_function_number + + + cfg_ds_function_number + + + + + dsn + + + cfg_dsn + + + + + pm_force_state + + + cfg_pm_force_state + + + + + pm_force_state_en + + + cfg_pm_force_state_en + + + + + pm_halt_aspm_l0s + + + cfg_pm_halt_aspm_l0s + + + + + pm_halt_aspm_l1 + + + cfg_pm_halt_aspm_l1 + + + + + pm_send_pme_to + + + cfg_pm_send_pme_to + + + + + pm_wake + + + cfg_pm_wake + + + + + rx_np_ok + + + rx_np_ok + + + + + rx_np_req + + + rx_np_req + + + + + trn_pending + + + cfg_trn_pending + + + + + turnoff_ok + + + cfg_turnoff_ok + + + + + tx_cfg_gnt + + + tx_cfg_gnt + + + + + + + true + + + + + + pcie2_cfg_msg_rcvd + pcie2_cfg_msg_rcvd + pcie config message received for gen2 + + + + + + + assert_int_a + + + cfg_msg_received_assert_int_a + + + + + assert_int_b + + + cfg_msg_received_assert_int_b + + + + + assert_int_c + + + cfg_msg_received_assert_int_c + + + + + assert_int_d + + + cfg_msg_received_assert_int_d + + + + + data + + + cfg_msg_data + + + + + deassert_int_a + + + cfg_msg_received_deassert_int_a + + + + + deassert_int_b + + + cfg_msg_received_deassert_int_b + + + + + deassert_int_c + + + cfg_msg_received_deassert_int_c + + + + + deassert_int_d + + + cfg_msg_received_deassert_int_d + + + + + err_cor + + + cfg_msg_received_err_cor + + + + + err_fatal + + + cfg_msg_received_err_fatal + + + + + err_non_fatal + + + cfg_msg_received_err_non_fatal + + + + + pm_pme + + + cfg_msg_received_pm_pme + + + + + pme_to_ack + + + cfg_msg_received_pme_to_ack + + + + + received + + + cfg_msg_received + + + + + received_pm_as_nak + + + cfg_msg_received_pm_as_nak + + + + + received_setslotpowerlimit + + + cfg_msg_received_setslotpowerlimit + + + + + + + true + + + + + + pcie_cfg_mgmt + pcie_cfg_mgmt + pcie config management for gen2 + + + + + + + ADDR + + + cfg_mgmt_dwaddr + + + + + BYTE_EN + + + cfg_mgmt_byte_en + + + + + READ_DATA + + + cfg_mgmt_do + + + + + READ_EN + + + cfg_mgmt_rd_en + + + + + READ_WRITE_DONE + + + cfg_mgmt_rd_wr_done + + + + + READONLY + + + cfg_mgmt_wr_readonly + + + + + TYPE1_CFG_REG_ACCESS + + + cfg_mgmt_wr_rw1c_as_rw + + + + + WRITE_DATA + + + cfg_mgmt_di + + + + + WRITE_EN + + + cfg_mgmt_wr_en + + + + + + + true + + + + + + pcie_qpll_drp + pcie_qpll_drp + pcie qpll drp for gen2 + + + + + + + clk + + + qpll_drp_clk + + + + + crscode + + + qpll_drp_crscode + + + + + done + + + qpll_drp_done + + + + + fsm + + + qpll_drp_fsm + + + + + gen3 + + + qpll_drp_gen3 + + + + + ovrd + + + qpll_drp_ovrd + + + + + qplld + + + qpll_qplld + + + + + qplllock + + + qpll_qplllock + + + + + qplloutclk + + + qpll_qplloutclk + + + + + qplloutrefclk + + + qpll_qplloutrefclk + + + + + qpllreset + + + qpll_qpllreset + + + + + reset + + + qpll_drp_reset + + + + + rst_n + + + qpll_drp_rst_n + + + + + start + + + qpll_drp_start + + + + + + + false + + + + + + pcie_sharedlogic_int_clk + pcie_sharedlogic_int_clk + pcie sharedlogic internal clock for gen2 + + + + + + + dclk + + + int_dclk_out + + + + + mmcm_lock + + + int_mmcm_lock_out + + + + + oobclk + + + int_oobclk_out + + + + + pclk_sel_slave + + + int_pclk_sel_slave + + + + + pclk_slave + + + int_pclk_out_slave + + + + + pipe_rxusrclk + + + int_pipe_rxusrclk_out + + + + + qplllock + + + int_qplllock_out + + + + + qplloutclk + + + int_qplloutclk_out + + + + + qplloutrefclk + + + int_qplloutrefclk_out + + + + + rxoutclk + + + int_rxoutclk_out + + + + + usrclk1 + + + int_userclk1_out + + + + + usrclk2 + + + int_userclk2_out + + + + + + + false + + + + + + transceiver_debug + transceiver_debug + Transceiver Debug Interface + + + + + + + cpll_lock + + + pipe_cpll_lock + + + + + debug + + + pipe_debug + + + + + debug_0 + + + pipe_debug_0 + + + + + debug_1 + + + pipe_debug_1 + + + + + debug_2 + + + pipe_debug_2 + + + + + debug_3 + + + pipe_debug_3 + + + + + debug_4 + + + pipe_debug_4 + + + + + debug_5 + + + pipe_debug_5 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+ + pipe_rxprbscntreset + + + + + rxprbserr + + + pipe_rxprbserr + + + + + rxprbssel + + + pipe_rxprbssel + + + + + rxstatus + + + pipe_rxstatus + + + + + rxsyncdone + + + pipe_rxsyncdone + + + + + sync_fsm_rx + + + pipe_sync_fsm_rx + + + + + sync_fsm_tx + + + pipe_sync_fsm_tx + + + + + txdlysresetdone + + + pipe_txdlysresetdone + + + + + txinhibit + + + pipe_txinhibit + + + + + txphaligndone + + + pipe_txphaligndone + + + + + txphinitdone + + + pipe_txphinitdone + + + + + txprbsforceerr + + + pipe_txprbsforceerr + + + + + txprbssel + + + pipe_txprbssel + + + + + + + false + + + + + + pcie2_pl + pcie2_pl + pcie pl for gen2 + + + + + + + directed_change_done + + + pl_directed_change_done + + + + + directed_link_auton + + + pl_directed_link_auton + + + + + directed_link_change + + + pl_directed_link_change + + + + + directed_link_speed + + + pl_directed_link_speed + + + + + directed_link_width + + + pl_directed_link_width + + + + + downstream_deemph_source + + + pl_downstream_deemph_source + + + + + initial_link_width + + + pl_initial_link_width + + + + + lane_reversal_mode + + + pl_lane_reversal_mode + + + + + link_gen2_cap + + + pl_link_gen2_cap + + + + + link_partner_gen2_supported + + + pl_link_partner_gen2_supported + + + + + link_upcfg_cap + + + pl_link_upcfg_cap + + + + + ltssm_state + + + pl_ltssm_state + + + + + phy_lnk_up + + + pl_phy_lnk_up + + + + + received_hot_rst + + + pl_received_hot_rst + + + + + rx_pm_state + + + pl_rx_pm_state + + + + + sel_lnk_rate + + + pl_sel_lnk_rate + + + + + sel_lnk_width + + + pl_sel_lnk_width + + + + + transmit_hot_rst + + + pl_transmit_hot_rst + + + + + tx_pm_state + + + pl_tx_pm_state + + + + + upstream_prefer_deemph + + + pl_upstream_prefer_deemph + + + + + + + true + + + + + + pcie_ext_ch_gt + pcie_ext_ch_gt + pcie ext ch gt for gen2 + + + + + + + DADDR + + + ext_ch_gt_drpaddr + + + + + DEN + + + ext_ch_gt_drpen + + + + + DI + + + ext_ch_gt_drpdi + + + + + DO + + + ext_ch_gt_drpdo + + + + + DRDY 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Input_devices + Mass_storage_controller + Processors + Device_does_not_fit_in_any_defined_classes + Bridge_device + Network_controller + Base_system_peripherals + + + choice_pairs_26a64edf + 1_vector + 2_vectors + 4_vectors + 8_vectors + 16_vectors + 32_vectors + 256_vectors + + + choice_pairs_307ee298 + Maximum_of_64_ns + Maximum_of_128_ns + Maximum_of_256_ns + Maximum_of_512_ns + Maximum_of_1_us + Maximum_of_2_us + Maximum_of_4_us + No_limit + + + choice_pairs_395c7aad + 64_bit + 128_bit + + + choice_pairs_3f2631bf + 128_bytes + 256_bytes + 512_bytes + 1024_bytes + + + choice_pairs_49d248fb + BAR_0 + + + choice_pairs_4da2f4f7 + No_function_number_bits_used + First_MSB_of_function_number_used + First_2_MSBs_of_function_number_used + All_3_bits_of_function_number_used + + + choice_pairs_5a23eaa1 + None + Buffer_Write + Buffer_Write_and_Read + + + choice_pairs_6f377f25 + None + Enable_Pipe_Simulation + Enable_External_PIPE_Interface + + + choice_pairs_77d6f5f3 + dB: + -3.5 + 1 + + + choice_pairs_7b4ddf8d + Disabled + 16-bit_I/O_Addressing + 32-bit_I/O_Addressing + + + choice_pairs_817775ab + Disabled + 32-bit_Addressing + 64-bit_Addressing + + + choice_pairs_8d857fe8 + 64_byte + 128_byte + + + choice_pairs_b03f0655 + None + Tandem_PROM (Refer PG054) + + + choice_pairs_c7407e77 + Range_A + Range_B + Ranges_A_&_B + Ranges_B_&_C + Ranges_A,_B_&_C + Ranges_B,_C_&_D + Ranges_A,_B,_C_&_D + + + choice_pairs_c98117c0 + RAM + Other_memory_controller + Flash + + + choice_pairs_d06c0498 + 2.5_GT/s + 5.0_GT/s + + + choice_pairs_db58a2b2 + Initial_ES + GES_and_Production + + + choice_pairs_dbee2759 + Maximum_of_1_us + Maximum_of_2_us + Maximum_of_4_us + Maximum_of_8_us + Maximum_of_16_us + Maximum_of_32_us + Maximum_of_64_us + No_limit + + + choice_pairs_dc66c043 + PCI_Express_Endpoint_device + Legacy_PCI_Express_Endpoint_device + Root_Port_of_PCI_Express_Root_Complex + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + pcie_7x_0.vho + vhdlTemplate + + + pcie_7x_0.veo + verilogTemplate + + + + xilinx_verilogbehavioralsimulation_view_fileset + + source/pcie_7x_0_pipe_eq.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pipe_drp.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pipe_rate.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pipe_reset.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pipe_sync.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gtp_pipe_rate.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gtp_pipe_drp.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gtp_pipe_reset.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pipe_user.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pipe_wrapper.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_qpll_drp.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_qpll_reset.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_qpll_wrapper.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_rxeq_scan.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_top.v + verilogSource + pcie_7x_0_pcie2_top + + + sys_clk_gen_ps_v.txt + text + + + source/pcie_7x_0_core_top.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_rx_null_gen.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_rx_pipeline.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_rx.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_top.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_tx_pipeline.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_tx_thrtl_ctl.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_tx.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_7x.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_bram_7x.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_bram_top_7x.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_brams_7x.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_pipe_lane.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_pipe_misc.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_pipe_pipeline.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gt_top.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gt_common.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gtp_cpllpd_ovrd.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gtx_cpllpd_ovrd.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gt_rx_valid_filter_7x.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gt_wrapper.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie2_top.v + verilogSource + pcie_7x_0_pcie2_top + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/pcie_7x_0.v + verilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/pcie_7x_v3_3_changelog.txt + text + + + + xilinx_verilogsynthesis_view_fileset + + source/pcie_7x_0_pipe_eq.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pipe_drp.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pipe_rate.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pipe_reset.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pipe_sync.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gtp_pipe_rate.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gtp_pipe_drp.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gtp_pipe_reset.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pipe_user.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pipe_wrapper.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_qpll_drp.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_qpll_reset.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_qpll_wrapper.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_rxeq_scan.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_top.v + verilogSource + pcie_7x_0_pcie2_top + + + sys_clk_gen_ps_v.txt + text + + + source/pcie_7x_0_core_top.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_rx_null_gen.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_rx_pipeline.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_rx.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_top.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_tx_pipeline.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_tx_thrtl_ctl.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_axi_basic_tx.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_7x.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_bram_7x.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_bram_top_7x.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_brams_7x.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_pipe_lane.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_pipe_misc.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie_pipe_pipeline.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gt_top.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gt_common.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gtp_cpllpd_ovrd.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gtx_cpllpd_ovrd.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gt_rx_valid_filter_7x.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_gt_wrapper.v + verilogSource + pcie_7x_0_pcie2_top + + + source/pcie_7x_0-PCIE_X0Y0.xdc + xdc + pcie_7x_0_pcie2_top + + + synth/pcie_7x_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + pcie_7x_0_pcie2_top + + + source/pcie_7x_0_pcie2_top.v + verilogSource + pcie_7x_0_pcie2_top + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/pcie_7x_0.v + verilogSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + pcie_7x_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + pcie_7x_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + pcie_7x_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + pcie_7x_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + pcie_7x_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The Xilinx 7 Series Integrated Block for PCI Express (1-lane, 2-lane, 4-lane, and 8-lane) uses the 7-Series Integrated Hard IP Block for PCI Express in conjunction with flexible 7-Series architectural features to implement a PCI Express Base Specification v2.1 compliant PCI Express Endpoint or Root Port. Unique features of the LogiCORE Block for PCI Express are the high performance AXI Interface, optimal buffering for high bandwidth applications, and BAR checking and filtering. + + + mode_selection + Mode + Basic + + + Use_Class_Code_Lookup_Assistant + false + + + Component_Name + pcie_7x_0 + + + Device_Port_Type + PCI_Express_Endpoint_device + + + Maximum_Link_Width + X4 + + + Link_Speed + 5.0_GT/s + + + Interface_Width + 64_bit + + + User_Clk_Freq + 250 + + + Bar0_Enabled + true + + + Bar0_Type + Memory + + + Bar0_64bit + false + + + Bar0_Prefetchable + false + + + Bar0_Scale + Kilobytes + + + Bar0_Size + 64 + + + Bar1_Enabled + false + + + Bar1_Type + N/A + + + Bar1_64bit + false + + + Bar1_Prefetchable + false + + + Bar1_Scale + Megabytes + + + Bar1_Size + 1 + + + Bar2_Enabled + false + + + Bar2_Type + N/A + + + Bar2_64bit + false + + + Bar2_Prefetchable + false + + + Bar2_Scale + Kilobytes + + + Bar2_Size + 2 + + + Bar3_Enabled + false + + + Bar3_Type + N/A + + + Bar3_64bit + false + + + Bar3_Prefetchable + false + + + Bar3_Scale + Kilobytes + + + Bar3_Size + 2 + + + Bar4_Enabled + false + + + Bar4_Type + N/A + + + Bar4_64bit + false + + + Bar4_Prefetchable + false + + + Bar4_Scale + Kilobytes + + + Bar4_Size + 2 + + + Bar5_Enabled + false + + + Bar5_Type + N/A + + + Bar5_Prefetchable + false + + + Bar5_Scale + Kilobytes + + + Bar5_Size + 2 + + + Expansion_Rom_Enabled + false + + + Expansion_Rom_Scale + Kilobytes + + + Expansion_Rom_Size + 2 + + + IO_Base_Limit_Registers + Disabled + + + Prefetchable_Memory_Base_Limit_Registers + Disabled + + + Vendor_ID + 10EE + + + Device_ID + 7024 + + + Revision_ID + 00 + + + Subsystem_Vendor_ID + 10EE + + + Subsystem_ID + 0007 + + + Class_Code_Base + 05 + + + Class_Code_Sub + 00 + + + Class_Code_Interface + 00 + + + Base_Class_Menu + Memory_controller + + + Sub_Class_Interface_Menu + RAM + + + Cardbus_CIS_Pointer + 00000000 + + + PCIe_Cap_Slot_Implemented + false + + + Max_Payload_Size + 1024_bytes + + + Extended_Tag_Field + false + + + Extended_Tag_Default + false + + + Phantom_Functions + No_function_number_bits_used + + + Acceptable_L0s_Latency + Maximum_of_64_ns + + + Acceptable_L1_Latency + No_limit + + + Cpl_Finite + false + + + Cpl_Timeout_Disable_Sup + false + + + Cpl_Timeout_Range + Range_B + + + Buf_Opt_BMA + false + + + Perf_Level + High + + + Dll_Link_Active_Cap + false + + + RCB + 64_byte + + + Trgt_Link_Speed + 4'h2 + + + Hw_Auton_Spd_Disable + false + + + De_emph + -3.5 + + + Enable_Slot_Clock_Cfg + true + + + Root_Cap_CRS + false + + + Slot_Cap_Attn_Butn + false + + + Slot_Cap_Pwr_Ctrl + false + + + Slot_Cap_MRL + false + + + Slot_Cap_Attn_Ind + false + + + Slot_Cap_Pwr_Ind + false + + + Slot_Cap_HotPlug_Surprise + false + + + Slot_Cap_HotPlug_Cap + false + + + Slot_Cap_Elec_Interlock + false + + + Slot_Cap_No_Cmd_Comp_Sup + false + + + Slot_Cap_Pwr_Limit_Value + 0 + + + Slot_Cap_Pwr_Limit_Scale + 0 + + + Slot_Cap_Physical_Slot_Num + 0 + + + IntX_Generation + true + + + Legacy_Interrupt + INTA + + + MSI_Enabled + false + + + MSI_64b + true + + + Multiple_Message_Capable + 1_vector + + + MSI_Vec_Mask + false + + + MSIx_Enabled + false + + + MSIx_Table_Size + 1 + + + MSIx_Table_Offset + 0 + + + MSIx_Table_BIR + BAR_0 + + + MSIx_PBA_Offset + 0 + + + MSIx_PBA_BIR + BAR_0 + + + Device_Specific_Initialization + false + + + D1_Support + false + + + D2_Support + false + + + D0_PME_Support + true + + + D1_PME_Support + true + + + D2_PME_Support + true + + + D3hot_PME_Support + true + + + D3cold_PME_Support + false + + + No_Soft_Reset + true + + + D0_Power_Consumed + 0 + + + D0_Power_Consumed_Factor + 0 + + + D1_Power_Consumed + 0 + + + D1_Power_Consumed_Factor + 0 + + + D2_Power_Consumed + 0 + + + D2_Power_Consumed_Factor + 0 + + + D3_Power_Consumed + 0 + + + D3_Power_Consumed_Factor + 0 + + + D0_Power_Dissipated + 0 + + + D0_Power_Dissipated_Factor + 0 + + + D1_Power_Dissipated + 0 + + + D1_Power_Dissipated_Factor + 0 + + + D2_Power_Dissipated + 0 + + + D2_Power_Dissipated_Factor + 0 + + + D3_Power_Dissipated + 0 + + + D3_Power_Dissipated_Factor + 0 + + + DSN_Enabled + true + + + VC_Cap_Enabled + false + + + VC_Cap_Reject_Snoop + false + + + VSEC_Enabled + false + + + PCI_CFG_Space + false + + + PCI_CFG_Space_Addr + 3F + + + EXT_PCI_CFG_Space + false + + + EXT_PCI_CFG_Space_Addr + 3FF + + + Xlnx_Ref_Board + ZC706 + + + PCIe_Blk_Locn + X0Y0 + + + Trans_Buf_Pipeline + None + + + En_route_unlock + false + + + En_route_pme_to + false + + + En_route_err_cor + false + + + En_route_err_nfl + false + + + En_route_err_ftl + false + + + En_route_inta + false + + + En_route_intb + false + + + En_route_intc + false + + + En_route_intd + false + + + En_route_pm_pme + false + + + En_route_pme_to_ack + false + + + Receive_NP_Request + true + + + Enable_ACK_NAK_Timer + false + + + ACK_NAK_Timeout_Func + Absolute + + + ACK_NAK_Timeout_Value + 0000 + + + Enable_Replay_Timer + false + + + Replay_Timeout_Func + Add + + + Replay_Timeout_Value + 0000 + + + Enable_Lane_Reversal + false + + + Upconfigure_Capable + true + + + Force_No_Scrambling + false + + + Disable_Tx_ASPM_L0s + false + + + Downstream_Link_Num + 00 + + + UR_INV_REQ + true + + + UR_PRS_RESPONSE + true + + + Silicon_Rev + GES_and_Production + + + Pcie_fast_config + None + + + PCIe_Debug_Ports + true + + + Ref_Clk_Freq + 100_MHz + + + Cost_Table + 1 + + + UR_Atomic + false + + + ATOMICOP32_Completer_Supported + false + + + ATOMICOP64_Completer_Supported + false + + + CAS128_Completer_Supported + false + + + TPH_Completer_Supported + 00 + + + ARI_Forwarding_Supported + false + + + AtomicOp_Routing_Supported + false + + + ASPM_Optionality + false + + + AER_Enabled + false + + + AER_ECRC_Check_Capable + false + + + AER_ECRC_Gen_Capable + false + + + AER_Multiheader + false + + + AER_Permit_Root_Error_Update + false + + + AER_Correctable_Internal_Error + false + + + AER_Header_Log_Overflow + false + + + AER_Receiver_Error + false + + + AER_Surprise_Down + false + + + AER_Flow_Control_Protocol_Error + false + + + AER_Completion_Timeout + false + + + AER_Completer_Abort + false + + + AER_Receiver_Overflow + false + + + AER_ECRC_Error + false + + + AER_ACS_Violation + false + + + AER_Uncorrectable_Internal_Error + false + + + AER_MC_Blocked_TLP + false + + + AER_AtomicOp_Egress_Blocked + false + + + AER_TLP_Prefix_Blocked + false + + + Optional_Error_Support + 000000 + + + RBAR_Enabled + false + + + RBAR_Num + 0 + + + BAR_Index_Value0 + 0 + + + BAR0_Size_Vector + 1M + + + RBAR_Initial_Value0 + 0 + + + BAR_Index_Value1 + 0 + + + BAR1_Size_Vector + 1M + + + RBAR_Initial_Value1 + 0 + + + BAR_Index_Value2 + 0 + + + BAR2_Size_Vector + 1M + + + RBAR_Initial_Value2 + 0 + + + BAR_Index_Value3 + 0 + + + BAR3_Size_Vector + 1M + + + RBAR_Initial_Value3 + 0 + + + BAR_Index_Value4 + 0 + + + BAR4_Size_Vector + 1M + + + RBAR_Initial_Value4 + 0 + + + BAR_Index_Value5 + 0 + + + BAR5_Size_Vector + 1M + + + RBAR_Initial_Value5 + 0 + + + RECRC_Check + 0 + + + RECRC_Check_Trim + false + + + Disable_Rx_Poisoned_Resp + false + + + pipe_sim + false + + + en_ext_clk + true + + + en_ext_gt_common + false + + + en_ext_ch_gt_drp + false + + + en_transceiver_status_ports + false + + + shared_logic_in_core + false + + + pl_interface + true + + + cfg_mgmt_if + true + + + cfg_ctl_if + true + + + cfg_status_if + true + + + rcv_msg_if + true + + + cfg_fc_if + true + + + err_reporting_if + true + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + RESET_BOARD_INTERFACE + Custom + + + en_ext_pipe_interface + false + + + en_ext_startup + false + + + pipe_mode_sim + None + + + enable_jtag_dbg + false + + + reduce_oob_freq + false + + + + + 7 Series Integrated Block for PCI Express + + XPM_CDC + XPM_MEMORY + + 14 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_sim_netlist.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_sim_netlist.v new file mode 100644 index 0000000..9d1d801 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_sim_netlist.v @@ -0,0 +1,66137 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Wed Jul 20 13:38:01 2022 +// Host : DESKTOP-4NLVFC8 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top pcie_7x_0 -prefix +// pcie_7x_0_ pcie_7x_0_sim_netlist.v +// Design : pcie_7x_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z045ffg900-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module pcie_7x_0_BRAM_TDP_MACRO_viv_ + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [5:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [5:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_60 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_61 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_75 ; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [5:0]rdata; + wire [5:0]wdata; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],1'b0,1'b0,wdata}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,1'b0}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_60 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_61 ,rdata}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_75 }), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_tx_wen), + .ENBWREN(mim_tx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_11 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_tx_wen), + .ENBWREN(mim_tx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_12 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_tx_wen), + .ENBWREN(mim_tx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_13 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_tx_wen), + .ENBWREN(mim_tx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_14 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_tx_wen), + .ENBWREN(mim_tx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_15 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_tx_wen), + .ENBWREN(mim_tx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_16 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_tx_wen), + .ENBWREN(mim_tx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_17 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_tx_wen), + .ENBWREN(mim_tx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_26 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ); + output [4:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [4:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [4:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire [4:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_60 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_61 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_62 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_75 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 }), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,1'b0}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_60 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_61 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_62 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 }), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_75 }), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_rx_wen), + .ENBWREN(mim_rx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_27 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_rx_wen), + .ENBWREN(mim_rx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_28 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_rx_wen), + .ENBWREN(mim_rx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_29 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_rx_wen), + .ENBWREN(mim_rx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_30 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_rx_wen), + .ENBWREN(mim_rx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_31 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_rx_wen), + .ENBWREN(mim_rx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_32 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_rx_wen), + .ENBWREN(mim_rx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *) +module pcie_7x_0_BRAM_TDP_MACRO_33 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ; + wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ; + wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ; + wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("NO_CHANGE"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl + (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(pipe_userclk1_in), + .CLKBWRCLK(pipe_userclk1_in), + .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ), + .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}), + .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }), + .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}), + .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }), + .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}), + .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(mim_rx_wen), + .ENBWREN(mim_rx_ren), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b1), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ), + .WEA({1'b1,1'b1,1'b1,1'b1}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* CHECK_LICENSE_TYPE = "pcie_7x_0,pcie_7x_0_pcie2_top,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "pcie_7x_0_pcie2_top,Vivado 2020.2" *) +(* NotValidForBitStream *) +module pcie_7x_0 + (pci_exp_txp, + pci_exp_txn, + pci_exp_rxp, + pci_exp_rxn, + pipe_pclk_in, + pipe_rxusrclk_in, + pipe_rxoutclk_in, + pipe_dclk_in, + pipe_userclk1_in, + pipe_userclk2_in, + pipe_oobclk_in, + pipe_mmcm_lock_in, + pipe_txoutclk_out, + pipe_rxoutclk_out, + pipe_pclk_sel_out, + pipe_gen3_out, + user_clk_out, + user_reset_out, + user_lnk_up, + user_app_rdy, + tx_buf_av, + tx_cfg_req, + tx_err_drop, + s_axis_tx_tready, + s_axis_tx_tdata, + s_axis_tx_tkeep, + s_axis_tx_tlast, + s_axis_tx_tvalid, + s_axis_tx_tuser, + tx_cfg_gnt, + m_axis_rx_tdata, + m_axis_rx_tkeep, + m_axis_rx_tlast, + m_axis_rx_tvalid, + m_axis_rx_tready, + m_axis_rx_tuser, + rx_np_ok, + rx_np_req, + fc_cpld, + fc_cplh, + fc_npd, + fc_nph, + fc_pd, + fc_ph, + fc_sel, + cfg_mgmt_do, + cfg_mgmt_rd_wr_done, + cfg_status, + cfg_command, + cfg_dstatus, + cfg_dcommand, + cfg_lstatus, + cfg_lcommand, + cfg_dcommand2, + cfg_pcie_link_state, + cfg_pmcsr_pme_en, + cfg_pmcsr_powerstate, + cfg_pmcsr_pme_status, + cfg_received_func_lvl_rst, + cfg_mgmt_di, + cfg_mgmt_byte_en, + cfg_mgmt_dwaddr, + cfg_mgmt_wr_en, + cfg_mgmt_rd_en, + cfg_mgmt_wr_readonly, + cfg_err_ecrc, + cfg_err_ur, + cfg_err_cpl_timeout, + cfg_err_cpl_unexpect, + cfg_err_cpl_abort, + cfg_err_posted, + cfg_err_cor, + cfg_err_atomic_egress_blocked, + cfg_err_internal_cor, + cfg_err_malformed, + cfg_err_mc_blocked, + cfg_err_poisoned, + cfg_err_norecovery, + cfg_err_tlp_cpl_header, + cfg_err_cpl_rdy, + cfg_err_locked, + cfg_err_acs, + cfg_err_internal_uncor, + cfg_trn_pending, + cfg_pm_halt_aspm_l0s, + cfg_pm_halt_aspm_l1, + cfg_pm_force_state_en, + cfg_pm_force_state, + cfg_dsn, + cfg_interrupt, + cfg_interrupt_rdy, + cfg_interrupt_assert, + cfg_interrupt_di, + cfg_interrupt_do, + cfg_interrupt_mmenable, + cfg_interrupt_msienable, + cfg_interrupt_msixenable, + cfg_interrupt_msixfm, + cfg_interrupt_stat, + cfg_pciecap_interrupt_msgnum, + cfg_to_turnoff, + cfg_turnoff_ok, + cfg_bus_number, + cfg_device_number, + cfg_function_number, + cfg_pm_wake, + cfg_pm_send_pme_to, + cfg_ds_bus_number, + cfg_ds_device_number, + cfg_ds_function_number, + cfg_mgmt_wr_rw1c_as_rw, + cfg_msg_received, + cfg_msg_data, + cfg_bridge_serr_en, + cfg_slot_control_electromech_il_ctl_pulse, + cfg_root_control_syserr_corr_err_en, + cfg_root_control_syserr_non_fatal_err_en, + cfg_root_control_syserr_fatal_err_en, + cfg_root_control_pme_int_en, + cfg_aer_rooterr_corr_err_reporting_en, + cfg_aer_rooterr_non_fatal_err_reporting_en, + cfg_aer_rooterr_fatal_err_reporting_en, + cfg_aer_rooterr_corr_err_received, + cfg_aer_rooterr_non_fatal_err_received, + cfg_aer_rooterr_fatal_err_received, + cfg_msg_received_err_cor, + cfg_msg_received_err_non_fatal, + cfg_msg_received_err_fatal, + cfg_msg_received_pm_as_nak, + cfg_msg_received_pm_pme, + cfg_msg_received_pme_to_ack, + cfg_msg_received_assert_int_a, + cfg_msg_received_assert_int_b, + cfg_msg_received_assert_int_c, + cfg_msg_received_assert_int_d, + cfg_msg_received_deassert_int_a, + cfg_msg_received_deassert_int_b, + cfg_msg_received_deassert_int_c, + cfg_msg_received_deassert_int_d, + cfg_msg_received_setslotpowerlimit, + pl_directed_link_change, + pl_directed_link_width, + pl_directed_link_speed, + pl_directed_link_auton, + pl_upstream_prefer_deemph, + pl_sel_lnk_rate, + pl_sel_lnk_width, + pl_ltssm_state, + pl_lane_reversal_mode, + pl_phy_lnk_up, + pl_tx_pm_state, + pl_rx_pm_state, + pl_link_upcfg_cap, + pl_link_gen2_cap, + pl_link_partner_gen2_supported, + pl_initial_link_width, + pl_directed_change_done, + pl_received_hot_rst, + pl_transmit_hot_rst, + pl_downstream_deemph_source, + cfg_err_aer_headerlog, + cfg_aer_interrupt_msgnum, + cfg_err_aer_headerlog_set, + cfg_aer_ecrc_check_en, + cfg_aer_ecrc_gen_en, + cfg_vc_tcvc_map, + sys_clk, + sys_rst_n, + pipe_mmcm_rst_n, + pcie_drp_clk, + pcie_drp_en, + pcie_drp_we, + pcie_drp_addr, + pcie_drp_di, + pcie_drp_do, + pcie_drp_rdy); + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txp" *) output [3:0]pci_exp_txp; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txn" *) output [3:0]pci_exp_txn; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxp" *) input [3:0]pci_exp_rxp; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxn" *) input [3:0]pci_exp_rxn; + (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock pclk_in" *) input pipe_pclk_in; + (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxusrclk_in" *) input pipe_rxusrclk_in; + (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxoutclk_in" *) input [3:0]pipe_rxoutclk_in; + (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock dclk_in" *) input pipe_dclk_in; + (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock userclk1_in" *) input pipe_userclk1_in; + (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock userclk2_in" *) input pipe_userclk2_in; + (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock oobclk_in" *) input pipe_oobclk_in; + (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock mmcm_lock_in" *) input pipe_mmcm_lock_in; + (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock txoutclk_out" *) output pipe_txoutclk_out; + (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxoutclk_out" *) output [3:0]pipe_rxoutclk_out; + (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock pclk_sel_out" *) output [3:0]pipe_pclk_sel_out; + (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock gen3_out" *) output pipe_gen3_out; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.user_clk_out CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.user_clk_out, ASSOCIATED_BUSIF m_axis_rx:s_axis_tx, FREQ_HZ 125000000, ASSOCIATED_RESET user_reset_out, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) output user_clk_out; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.user_reset_out RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.user_reset_out, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) output user_reset_out; + output user_lnk_up; + output user_app_rdy; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_buf_av" *) output [5:0]tx_buf_av; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_cfg_req" *) output tx_cfg_req; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_err_drop" *) output tx_err_drop; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TREADY" *) output s_axis_tx_tready; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TDATA" *) input [63:0]s_axis_tx_tdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TKEEP" *) input [7:0]s_axis_tx_tkeep; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TLAST" *) input s_axis_tx_tlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TVALID" *) input s_axis_tx_tvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TUSER" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axis_tx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) input [3:0]s_axis_tx_tuser; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control tx_cfg_gnt" *) input tx_cfg_gnt; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TDATA" *) output [63:0]m_axis_rx_tdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TKEEP" *) output [7:0]m_axis_rx_tkeep; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TLAST" *) output m_axis_rx_tlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TVALID" *) output m_axis_rx_tvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TREADY" *) input m_axis_rx_tready; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TUSER" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis_rx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) output [21:0]m_axis_rx_tuser; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_ok" *) input rx_np_ok; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_req" *) input rx_np_req; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLD" *) output [11:0]fc_cpld; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLH" *) output [7:0]fc_cplh; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPD" *) output [11:0]fc_npd; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPH" *) output [7:0]fc_nph; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PD" *) output [11:0]fc_pd; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PH" *) output [7:0]fc_ph; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc SEL" *) input [2:0]fc_sel; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_DATA" *) output [31:0]cfg_mgmt_do; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_WRITE_DONE" *) output cfg_mgmt_rd_wr_done; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status status" *) output [15:0]cfg_status; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status command" *) output [15:0]cfg_command; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dstatus" *) output [15:0]cfg_dstatus; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand" *) output [15:0]cfg_dcommand; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lstatus" *) output [15:0]cfg_lstatus; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lcommand" *) output [15:0]cfg_lcommand; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand2" *) output [15:0]cfg_dcommand2; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pcie_link_state" *) output [2:0]cfg_pcie_link_state; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_en" *) output cfg_pmcsr_pme_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_powerstate" *) output [1:0]cfg_pmcsr_powerstate; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_status" *) output cfg_pmcsr_pme_status; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status received_func_lvl_rst" *) output cfg_received_func_lvl_rst; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_DATA" *) input [31:0]cfg_mgmt_di; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt BYTE_EN" *) input [3:0]cfg_mgmt_byte_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt ADDR" *) input [9:0]cfg_mgmt_dwaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_EN" *) input cfg_mgmt_wr_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_EN" *) input cfg_mgmt_rd_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READONLY" *) input cfg_mgmt_wr_readonly; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ecrc" *) input cfg_err_ecrc; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ur" *) input cfg_err_ur; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_timeout" *) input cfg_err_cpl_timeout; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_unexpect" *) input cfg_err_cpl_unexpect; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_abort" *) input cfg_err_cpl_abort; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err posted" *) input cfg_err_posted; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cor" *) input cfg_err_cor; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err atomic_egress_blocked" *) input cfg_err_atomic_egress_blocked; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_cor" *) input cfg_err_internal_cor; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err malformed" *) input cfg_err_malformed; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err mc_blocked" *) input cfg_err_mc_blocked; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err poisoned" *) input cfg_err_poisoned; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err norecovery" *) input cfg_err_norecovery; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err tlp_cpl_header" *) input [47:0]cfg_err_tlp_cpl_header; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_rdy" *) output cfg_err_cpl_rdy; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err locked" *) input cfg_err_locked; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err acs" *) input cfg_err_acs; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_uncor" *) input cfg_err_internal_uncor; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control trn_pending" *) input cfg_trn_pending; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l0s" *) input cfg_pm_halt_aspm_l0s; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l1" *) input cfg_pm_halt_aspm_l1; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state_en" *) input cfg_pm_force_state_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state" *) input [1:0]cfg_pm_force_state; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control dsn" *) input [63:0]cfg_dsn; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt interrupt" *) input cfg_interrupt; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt rdy" *) output cfg_interrupt_rdy; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt assert" *) input cfg_interrupt_assert; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt write_data" *) input [7:0]cfg_interrupt_di; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt read_data" *) output [7:0]cfg_interrupt_do; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt mmenable" *) output [2:0]cfg_interrupt_mmenable; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msienable" *) output cfg_interrupt_msienable; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixenable" *) output cfg_interrupt_msixenable; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixfm" *) output cfg_interrupt_msixfm; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt stat" *) input cfg_interrupt_stat; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt pciecap_interrupt_msgnum" *) input [4:0]cfg_pciecap_interrupt_msgnum; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status turnoff" *) output cfg_to_turnoff; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control turnoff_ok" *) input cfg_turnoff_ok; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bus_number" *) output [7:0]cfg_bus_number; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status device_number" *) output [4:0]cfg_device_number; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status function_number" *) output [2:0]cfg_function_number; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_wake" *) input cfg_pm_wake; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_send_pme_to" *) input cfg_pm_send_pme_to; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_bus_number" *) input [7:0]cfg_ds_bus_number; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_device_number" *) input [4:0]cfg_ds_device_number; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_function_number" *) input [2:0]cfg_ds_function_number; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt TYPE1_CFG_REG_ACCESS" *) input cfg_mgmt_wr_rw1c_as_rw; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received" *) output cfg_msg_received; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd data" *) output [15:0]cfg_msg_data; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bridge_serr_en" *) output cfg_bridge_serr_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status slot_control_electromech_il_ctl_pulse" *) output cfg_slot_control_electromech_il_ctl_pulse; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_corr_err_en" *) output cfg_root_control_syserr_corr_err_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_non_fatal_err_en" *) output cfg_root_control_syserr_non_fatal_err_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_fatal_err_en" *) output cfg_root_control_syserr_fatal_err_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_pme_int_en" *) output cfg_root_control_pme_int_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_reporting_en" *) output cfg_aer_rooterr_corr_err_reporting_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_reporting_en" *) output cfg_aer_rooterr_non_fatal_err_reporting_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_reporting_en" *) output cfg_aer_rooterr_fatal_err_reporting_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_received" *) output cfg_aer_rooterr_corr_err_received; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_received" *) output cfg_aer_rooterr_non_fatal_err_received; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_received" *) output cfg_aer_rooterr_fatal_err_received; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_cor" *) output cfg_msg_received_err_cor; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_non_fatal" *) output cfg_msg_received_err_non_fatal; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_fatal" *) output cfg_msg_received_err_fatal; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_pm_as_nak" *) output cfg_msg_received_pm_as_nak; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pm_pme" *) output cfg_msg_received_pm_pme; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pme_to_ack" *) output cfg_msg_received_pme_to_ack; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_a" *) output cfg_msg_received_assert_int_a; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_b" *) output cfg_msg_received_assert_int_b; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_c" *) output cfg_msg_received_assert_int_c; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_d" *) output cfg_msg_received_assert_int_d; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_a" *) output cfg_msg_received_deassert_int_a; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_b" *) output cfg_msg_received_deassert_int_b; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_c" *) output cfg_msg_received_deassert_int_c; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_d" *) output cfg_msg_received_deassert_int_d; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_setslotpowerlimit" *) output cfg_msg_received_setslotpowerlimit; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_change" *) input [1:0]pl_directed_link_change; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_width" *) input [1:0]pl_directed_link_width; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_speed" *) input pl_directed_link_speed; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_auton" *) input pl_directed_link_auton; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl upstream_prefer_deemph" *) input pl_upstream_prefer_deemph; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_rate" *) output pl_sel_lnk_rate; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_width" *) output [1:0]pl_sel_lnk_width; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl ltssm_state" *) output [5:0]pl_ltssm_state; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl lane_reversal_mode" *) output [1:0]pl_lane_reversal_mode; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl phy_lnk_up" *) output pl_phy_lnk_up; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl tx_pm_state" *) output [2:0]pl_tx_pm_state; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl rx_pm_state" *) output [1:0]pl_rx_pm_state; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_upcfg_cap" *) output pl_link_upcfg_cap; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_gen2_cap" *) output pl_link_gen2_cap; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_partner_gen2_supported" *) output pl_link_partner_gen2_supported; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl initial_link_width" *) output [2:0]pl_initial_link_width; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_change_done" *) output pl_directed_change_done; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl received_hot_rst" *) output pl_received_hot_rst; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl transmit_hot_rst" *) input pl_transmit_hot_rst; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl downstream_deemph_source" *) input pl_downstream_deemph_source; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog" *) input [127:0]cfg_err_aer_headerlog; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_interrupt_msgnum" *) input [4:0]cfg_aer_interrupt_msgnum; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog_set" *) output cfg_err_aer_headerlog_set; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_check_en" *) output cfg_aer_ecrc_check_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_gen_en" *) output cfg_aer_ecrc_gen_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status vc_tcvc_map" *) output [6:0]cfg_vc_tcvc_map; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.sys_clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.sys_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) input sys_clk; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.sys_rst_n RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.sys_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input sys_rst_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock mmcm_rst_n" *) input pipe_mmcm_rst_n; + input pcie_drp_clk; + (* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DEN" *) input pcie_drp_en; + (* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DWE" *) input pcie_drp_we; + (* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DADDR" *) input [8:0]pcie_drp_addr; + (* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DI" *) input [15:0]pcie_drp_di; + (* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DO" *) output [15:0]pcie_drp_do; + (* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DRDY" *) output pcie_drp_rdy; + + wire \ ; + wire \ ; + wire cfg_aer_ecrc_check_en; + wire cfg_aer_ecrc_gen_en; + wire [4:0]cfg_aer_interrupt_msgnum; + wire cfg_aer_rooterr_corr_err_received; + wire cfg_aer_rooterr_corr_err_reporting_en; + wire cfg_aer_rooterr_fatal_err_received; + wire cfg_aer_rooterr_fatal_err_reporting_en; + wire cfg_aer_rooterr_non_fatal_err_received; + wire cfg_aer_rooterr_non_fatal_err_reporting_en; + wire cfg_bridge_serr_en; + wire [7:0]cfg_bus_number; + wire [10:0]\^cfg_command ; + wire [14:0]\^cfg_dcommand ; + wire [11:0]\^cfg_dcommand2 ; + wire [4:0]cfg_device_number; + wire [7:0]cfg_ds_bus_number; + wire [4:0]cfg_ds_device_number; + wire [2:0]cfg_ds_function_number; + wire [63:0]cfg_dsn; + wire [5:0]\^cfg_dstatus ; + wire [127:0]cfg_err_aer_headerlog; + wire cfg_err_aer_headerlog_set; + wire cfg_err_atomic_egress_blocked; + wire cfg_err_cor; + wire cfg_err_cpl_abort; + wire cfg_err_cpl_rdy; + wire cfg_err_cpl_timeout; + wire cfg_err_cpl_unexpect; + wire cfg_err_ecrc; + wire cfg_err_internal_cor; + wire cfg_err_internal_uncor; + wire cfg_err_locked; + wire cfg_err_malformed; + wire cfg_err_mc_blocked; + wire cfg_err_norecovery; + wire cfg_err_poisoned; + wire cfg_err_posted; + wire [47:0]cfg_err_tlp_cpl_header; + wire cfg_err_ur; + wire [2:0]cfg_function_number; + wire cfg_interrupt; + wire cfg_interrupt_assert; + wire [7:0]cfg_interrupt_di; + wire [7:0]cfg_interrupt_do; + wire [2:0]cfg_interrupt_mmenable; + wire cfg_interrupt_msienable; + wire cfg_interrupt_msixenable; + wire cfg_interrupt_msixfm; + wire cfg_interrupt_rdy; + wire cfg_interrupt_stat; + wire [11:0]\^cfg_lcommand ; + wire [15:0]\^cfg_lstatus ; + wire [3:0]cfg_mgmt_byte_en; + wire [31:0]cfg_mgmt_di; + wire [31:0]cfg_mgmt_do; + wire [9:0]cfg_mgmt_dwaddr; + wire cfg_mgmt_rd_en; + wire cfg_mgmt_rd_wr_done; + wire cfg_mgmt_wr_en; + wire cfg_mgmt_wr_readonly; + wire cfg_mgmt_wr_rw1c_as_rw; + wire [15:0]cfg_msg_data; + wire cfg_msg_received; + wire cfg_msg_received_assert_int_a; + wire cfg_msg_received_assert_int_b; + wire cfg_msg_received_assert_int_c; + wire cfg_msg_received_assert_int_d; + wire cfg_msg_received_deassert_int_a; + wire cfg_msg_received_deassert_int_b; + wire cfg_msg_received_deassert_int_c; + wire cfg_msg_received_deassert_int_d; + wire cfg_msg_received_err_cor; + wire cfg_msg_received_err_fatal; + wire cfg_msg_received_err_non_fatal; + wire cfg_msg_received_pm_as_nak; + wire cfg_msg_received_pm_pme; + wire cfg_msg_received_pme_to_ack; + wire cfg_msg_received_setslotpowerlimit; + wire [2:0]cfg_pcie_link_state; + wire [4:0]cfg_pciecap_interrupt_msgnum; + wire [1:0]cfg_pm_force_state; + wire cfg_pm_force_state_en; + wire cfg_pm_halt_aspm_l0s; + wire cfg_pm_halt_aspm_l1; + wire cfg_pm_wake; + wire cfg_pmcsr_pme_en; + wire cfg_pmcsr_pme_status; + wire [1:0]cfg_pmcsr_powerstate; + wire cfg_received_func_lvl_rst; + wire cfg_root_control_pme_int_en; + wire cfg_root_control_syserr_corr_err_en; + wire cfg_root_control_syserr_fatal_err_en; + wire cfg_root_control_syserr_non_fatal_err_en; + wire cfg_slot_control_electromech_il_ctl_pulse; + wire cfg_to_turnoff; + wire cfg_trn_pending; + wire cfg_turnoff_ok; + wire [6:0]cfg_vc_tcvc_map; + wire [11:0]fc_cpld; + wire [7:0]fc_cplh; + wire [11:0]fc_npd; + wire [7:0]fc_nph; + wire [11:0]fc_pd; + wire [7:0]fc_ph; + wire [2:0]fc_sel; + wire [63:0]m_axis_rx_tdata; + wire [7:4]\^m_axis_rx_tkeep ; + wire m_axis_rx_tlast; + wire m_axis_rx_tready; + wire [21:0]\^m_axis_rx_tuser ; + wire m_axis_rx_tvalid; + wire [3:0]pci_exp_rxn; + wire [3:0]pci_exp_rxp; + wire [3:0]pci_exp_txn; + wire [3:0]pci_exp_txp; + wire [8:0]pcie_drp_addr; + wire pcie_drp_clk; + wire [15:0]pcie_drp_di; + wire [15:0]pcie_drp_do; + wire pcie_drp_en; + wire pcie_drp_rdy; + wire pcie_drp_we; + wire pipe_dclk_in; + wire pipe_gen3_out; + wire pipe_mmcm_lock_in; + wire pipe_oobclk_in; + wire pipe_pclk_in; + wire [3:0]pipe_pclk_sel_out; + wire [3:0]pipe_rxoutclk_out; + wire pipe_rxusrclk_in; + wire pipe_txoutclk_out; + wire pipe_userclk1_in; + wire pipe_userclk2_in; + wire pl_directed_change_done; + wire pl_directed_link_auton; + wire [1:0]pl_directed_link_change; + wire pl_directed_link_speed; + wire [1:0]pl_directed_link_width; + wire pl_downstream_deemph_source; + wire [2:0]pl_initial_link_width; + wire [1:0]pl_lane_reversal_mode; + wire pl_link_gen2_cap; + wire pl_link_partner_gen2_supported; + wire pl_link_upcfg_cap; + wire [5:0]pl_ltssm_state; + wire pl_phy_lnk_up; + wire pl_received_hot_rst; + wire [1:0]pl_rx_pm_state; + wire pl_sel_lnk_rate; + wire [1:0]pl_sel_lnk_width; + wire pl_transmit_hot_rst; + wire [2:0]pl_tx_pm_state; + wire pl_upstream_prefer_deemph; + wire rx_np_ok; + wire rx_np_req; + wire [63:0]s_axis_tx_tdata; + wire [7:0]s_axis_tx_tkeep; + wire s_axis_tx_tlast; + wire s_axis_tx_tready; + wire [3:0]s_axis_tx_tuser; + wire s_axis_tx_tvalid; + wire sys_clk; + wire sys_rst_n; + wire [5:0]tx_buf_av; + wire tx_cfg_gnt; + wire tx_cfg_req; + wire tx_err_drop; + wire user_clk_out; + wire user_lnk_up; + wire user_reset_out; + wire NLW_inst_ext_ch_gt_drpclk_UNCONNECTED; + wire NLW_inst_int_dclk_out_UNCONNECTED; + wire NLW_inst_int_mmcm_lock_out_UNCONNECTED; + wire NLW_inst_int_oobclk_out_UNCONNECTED; + wire NLW_inst_int_pclk_out_slave_UNCONNECTED; + wire NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED; + wire NLW_inst_int_userclk1_out_UNCONNECTED; + wire NLW_inst_int_userclk2_out_UNCONNECTED; + wire NLW_inst_pipe_qrst_idle_UNCONNECTED; + wire NLW_inst_pipe_rate_idle_UNCONNECTED; + wire NLW_inst_pipe_rst_idle_UNCONNECTED; + wire NLW_inst_qpll_drp_clk_UNCONNECTED; + wire NLW_inst_qpll_drp_gen3_UNCONNECTED; + wire NLW_inst_qpll_drp_ovrd_UNCONNECTED; + wire NLW_inst_qpll_drp_rst_n_UNCONNECTED; + wire NLW_inst_qpll_drp_start_UNCONNECTED; + wire NLW_inst_qpll_qplld_UNCONNECTED; + wire NLW_inst_startup_cfgclk_UNCONNECTED; + wire NLW_inst_startup_cfgmclk_UNCONNECTED; + wire NLW_inst_startup_eos_UNCONNECTED; + wire NLW_inst_startup_preq_UNCONNECTED; + wire NLW_inst_user_app_rdy_UNCONNECTED; + wire [15:3]NLW_inst_cfg_command_UNCONNECTED; + wire [15:15]NLW_inst_cfg_dcommand_UNCONNECTED; + wire [15:12]NLW_inst_cfg_dcommand2_UNCONNECTED; + wire [15:4]NLW_inst_cfg_dstatus_UNCONNECTED; + wire [15:2]NLW_inst_cfg_lcommand_UNCONNECTED; + wire [12:2]NLW_inst_cfg_lstatus_UNCONNECTED; + wire [15:0]NLW_inst_cfg_status_UNCONNECTED; + wire [11:0]NLW_inst_common_commands_out_UNCONNECTED; + wire [63:0]NLW_inst_ext_ch_gt_drpdo_UNCONNECTED; + wire [3:0]NLW_inst_ext_ch_gt_drprdy_UNCONNECTED; + wire [3:0]NLW_inst_gt_ch_drp_rdy_UNCONNECTED; + wire [31:0]NLW_inst_icap_o_UNCONNECTED; + wire [1:0]NLW_inst_int_qplllock_out_UNCONNECTED; + wire [1:0]NLW_inst_int_qplloutclk_out_UNCONNECTED; + wire [1:0]NLW_inst_int_qplloutrefclk_out_UNCONNECTED; + wire [3:0]NLW_inst_int_rxoutclk_out_UNCONNECTED; + wire [3:0]NLW_inst_m_axis_rx_tkeep_UNCONNECTED; + wire [20:9]NLW_inst_m_axis_rx_tuser_UNCONNECTED; + wire [3:0]NLW_inst_pipe_cpll_lock_UNCONNECTED; + wire [31:0]NLW_inst_pipe_debug_UNCONNECTED; + wire [3:0]NLW_inst_pipe_debug_0_UNCONNECTED; + wire [3:0]NLW_inst_pipe_debug_1_UNCONNECTED; + wire [3:0]NLW_inst_pipe_debug_2_UNCONNECTED; + wire [3:0]NLW_inst_pipe_debug_3_UNCONNECTED; + wire [3:0]NLW_inst_pipe_debug_4_UNCONNECTED; + wire [3:0]NLW_inst_pipe_debug_5_UNCONNECTED; + wire [3:0]NLW_inst_pipe_debug_6_UNCONNECTED; + wire [3:0]NLW_inst_pipe_debug_7_UNCONNECTED; + wire [3:0]NLW_inst_pipe_debug_8_UNCONNECTED; + wire [3:0]NLW_inst_pipe_debug_9_UNCONNECTED; + wire [59:0]NLW_inst_pipe_dmonitorout_UNCONNECTED; + wire [27:0]NLW_inst_pipe_drp_fsm_UNCONNECTED; + wire [3:0]NLW_inst_pipe_eyescandataerror_UNCONNECTED; + wire [0:0]NLW_inst_pipe_qpll_lock_UNCONNECTED; + wire [11:0]NLW_inst_pipe_qrst_fsm_UNCONNECTED; + wire [19:0]NLW_inst_pipe_rate_fsm_UNCONNECTED; + wire [4:0]NLW_inst_pipe_rst_fsm_UNCONNECTED; + wire [11:0]NLW_inst_pipe_rxbufstatus_UNCONNECTED; + wire [3:0]NLW_inst_pipe_rxcommadet_UNCONNECTED; + wire [31:0]NLW_inst_pipe_rxdisperr_UNCONNECTED; + wire [3:0]NLW_inst_pipe_rxdlysresetdone_UNCONNECTED; + wire [31:0]NLW_inst_pipe_rxnotintable_UNCONNECTED; + wire [3:0]NLW_inst_pipe_rxphaligndone_UNCONNECTED; + wire [3:0]NLW_inst_pipe_rxpmaresetdone_UNCONNECTED; + wire [3:0]NLW_inst_pipe_rxprbserr_UNCONNECTED; + wire [11:0]NLW_inst_pipe_rxstatus_UNCONNECTED; + wire [3:0]NLW_inst_pipe_rxsyncdone_UNCONNECTED; + wire [27:0]NLW_inst_pipe_sync_fsm_rx_UNCONNECTED; + wire [23:0]NLW_inst_pipe_sync_fsm_tx_UNCONNECTED; + wire [24:0]NLW_inst_pipe_tx_0_sigs_UNCONNECTED; + wire [24:0]NLW_inst_pipe_tx_1_sigs_UNCONNECTED; + wire [24:0]NLW_inst_pipe_tx_2_sigs_UNCONNECTED; + wire [24:0]NLW_inst_pipe_tx_3_sigs_UNCONNECTED; + wire [24:0]NLW_inst_pipe_tx_4_sigs_UNCONNECTED; + wire [24:0]NLW_inst_pipe_tx_5_sigs_UNCONNECTED; + wire [24:0]NLW_inst_pipe_tx_6_sigs_UNCONNECTED; + wire [24:0]NLW_inst_pipe_tx_7_sigs_UNCONNECTED; + wire [3:0]NLW_inst_pipe_txdlysresetdone_UNCONNECTED; + wire [3:0]NLW_inst_pipe_txphaligndone_UNCONNECTED; + wire [3:0]NLW_inst_pipe_txphinitdone_UNCONNECTED; + wire [1:0]NLW_inst_qpll_qpllreset_UNCONNECTED; + + assign cfg_command[15] = \ ; + assign cfg_command[14] = \ ; + assign cfg_command[13] = \ ; + assign cfg_command[12] = \ ; + assign cfg_command[11] = \ ; + assign cfg_command[10] = \^cfg_command [10]; + assign cfg_command[9] = \ ; + assign cfg_command[8] = \^cfg_command [8]; + assign cfg_command[7] = \ ; + assign cfg_command[6] = \ ; + assign cfg_command[5] = \ ; + assign cfg_command[4] = \ ; + assign cfg_command[3] = \ ; + assign cfg_command[2:0] = \^cfg_command [2:0]; + assign cfg_dcommand[15] = \ ; + assign cfg_dcommand[14:0] = \^cfg_dcommand [14:0]; + assign cfg_dcommand2[15] = \ ; + assign cfg_dcommand2[14] = \ ; + assign cfg_dcommand2[13] = \ ; + assign cfg_dcommand2[12] = \ ; + assign cfg_dcommand2[11:0] = \^cfg_dcommand2 [11:0]; + assign cfg_dstatus[15] = \ ; + assign cfg_dstatus[14] = \ ; + assign cfg_dstatus[13] = \ ; + assign cfg_dstatus[12] = \ ; + assign cfg_dstatus[11] = \ ; + assign cfg_dstatus[10] = \ ; + assign cfg_dstatus[9] = \ ; + assign cfg_dstatus[8] = \ ; + assign cfg_dstatus[7] = \ ; + assign cfg_dstatus[6] = \ ; + assign cfg_dstatus[5] = \^cfg_dstatus [5]; + assign cfg_dstatus[4] = \ ; + assign cfg_dstatus[3:0] = \^cfg_dstatus [3:0]; + assign cfg_lcommand[15] = \ ; + assign cfg_lcommand[14] = \ ; + assign cfg_lcommand[13] = \ ; + assign cfg_lcommand[12] = \ ; + assign cfg_lcommand[11:3] = \^cfg_lcommand [11:3]; + assign cfg_lcommand[2] = \ ; + assign cfg_lcommand[1:0] = \^cfg_lcommand [1:0]; + assign cfg_lstatus[15:13] = \^cfg_lstatus [15:13]; + assign cfg_lstatus[12] = \ ; + assign cfg_lstatus[11] = \^cfg_lstatus [11]; + assign cfg_lstatus[10] = \ ; + assign cfg_lstatus[9] = \ ; + assign cfg_lstatus[8] = \ ; + assign cfg_lstatus[7:4] = \^cfg_lstatus [7:4]; + assign cfg_lstatus[3] = \ ; + assign cfg_lstatus[2] = \ ; + assign cfg_lstatus[1:0] = \^cfg_lstatus [1:0]; + assign cfg_status[15] = \ ; + assign cfg_status[14] = \ ; + assign cfg_status[13] = \ ; + assign cfg_status[12] = \ ; + assign cfg_status[11] = \ ; + assign cfg_status[10] = \ ; + assign cfg_status[9] = \ ; + assign cfg_status[8] = \ ; + assign cfg_status[7] = \ ; + assign cfg_status[6] = \ ; + assign cfg_status[5] = \ ; + assign cfg_status[4] = \ ; + assign cfg_status[3] = \ ; + assign cfg_status[2] = \ ; + assign cfg_status[1] = \ ; + assign cfg_status[0] = \ ; + assign m_axis_rx_tkeep[7:4] = \^m_axis_rx_tkeep [7:4]; + assign m_axis_rx_tkeep[3] = \ ; + assign m_axis_rx_tkeep[2] = \ ; + assign m_axis_rx_tkeep[1] = \ ; + assign m_axis_rx_tkeep[0] = \ ; + assign m_axis_rx_tuser[21] = \^m_axis_rx_tuser [21]; + assign m_axis_rx_tuser[20] = \ ; + assign m_axis_rx_tuser[19:17] = \^m_axis_rx_tuser [19:17]; + assign m_axis_rx_tuser[16] = \ ; + assign m_axis_rx_tuser[15] = \ ; + assign m_axis_rx_tuser[14] = \^m_axis_rx_tuser [14]; + assign m_axis_rx_tuser[13] = \ ; + assign m_axis_rx_tuser[12] = \ ; + assign m_axis_rx_tuser[11] = \ ; + assign m_axis_rx_tuser[10] = \ ; + assign m_axis_rx_tuser[9] = \ ; + assign m_axis_rx_tuser[8:0] = \^m_axis_rx_tuser [8:0]; + assign user_app_rdy = \ ; + GND GND + (.G(\ )); + VCC VCC + (.P(\ )); + (* CFG_CTL_IF = "TRUE" *) + (* CFG_FC_IF = "TRUE" *) + (* CFG_MGMT_IF = "TRUE" *) + (* CFG_STATUS_IF = "TRUE" *) + (* CLASS_CODE = "050000" *) + (* C_DATA_WIDTH = "64" *) + (* DowngradeIPIdentifiedWarnings = "yes" *) + (* ENABLE_JTAG_DBG = "FALSE" *) + (* ERR_REPORTING_IF = "TRUE" *) + (* EXT_CH_GT_DRP = "FALSE" *) + (* EXT_PIPE_INTERFACE = "FALSE" *) + (* EXT_STARTUP_PRIMITIVE = "FALSE" *) + (* KEEP_WIDTH = "8" *) + (* LINK_CAP_MAX_LINK_WIDTH = "4" *) + (* PCIE_ASYNC_EN = "FALSE" *) + (* PCIE_EXT_CLK = "TRUE" *) + (* PCIE_EXT_GT_COMMON = "FALSE" *) + (* PIPE_SIM = "FALSE" *) + (* PL_INTERFACE = "TRUE" *) + (* RCV_MSG_IF = "TRUE" *) + (* REDUCE_OOB_FREQ = "FALSE" *) + (* SHARED_LOGIC_IN_CORE = "FALSE" *) + (* TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE" *) + (* bar_0 = "FFFF0000" *) + (* bar_1 = "00000000" *) + (* bar_2 = "00000000" *) + (* bar_3 = "00000000" *) + (* bar_4 = "00000000" *) + (* bar_5 = "00000000" *) + (* bram_lat = "0" *) + (* c_aer_base_ptr = "000" *) + (* c_aer_cap_ecrc_check_capable = "FALSE" *) + (* c_aer_cap_ecrc_gen_capable = "FALSE" *) + (* c_aer_cap_multiheader = "FALSE" *) + (* c_aer_cap_nextptr = "000" *) + (* c_aer_cap_on = "FALSE" *) + (* c_aer_cap_optional_err_support = "000000" *) + (* c_aer_cap_permit_rooterr_update = "FALSE" *) + (* c_buf_opt_bma = "TRUE" *) + (* c_component_name = "pcie_7x_0" *) + (* c_cpl_inf = "TRUE" *) + (* c_cpl_infinite = "TRUE" *) + (* c_cpl_timeout_disable_sup = "FALSE" *) + (* c_cpl_timeout_range = "0010" *) + (* c_cpl_timeout_ranges_sup = "2" *) + (* c_d1_support = "FALSE" *) + (* c_d2_support = "FALSE" *) + (* c_de_emph = "FALSE" *) + (* c_dev_cap2_ari_forwarding_supported = "FALSE" *) + (* c_dev_cap2_atomicop32_completer_supported = "FALSE" *) + (* c_dev_cap2_atomicop64_completer_supported = "FALSE" *) + (* c_dev_cap2_atomicop_routing_supported = "FALSE" *) + (* c_dev_cap2_cas128_completer_supported = "FALSE" *) + (* c_dev_cap2_tph_completer_supported = "00" *) + (* c_dev_control_ext_tag_default = "FALSE" *) + (* c_dev_port_type = "0" *) + (* c_dis_lane_reverse = "TRUE" *) + (* c_disable_rx_poisoned_resp = "FALSE" *) + (* c_disable_scrambling = "FALSE" *) + (* c_disable_tx_aspm_l0s = "FALSE" *) + (* c_dll_lnk_actv_cap = "FALSE" *) + (* c_dsi_bool = "FALSE" *) + (* c_dsn_base_ptr = "100" *) + (* c_dsn_cap_enabled = "TRUE" *) + (* c_dsn_next_ptr = "000" *) + (* c_enable_msg_route = "00000000000" *) + (* c_ep_l0s_accpt_lat = "0" *) + (* c_ep_l1_accpt_lat = "7" *) + (* c_ext_pci_cfg_space_addr = "3FF" *) + (* c_external_clocking = "TRUE" *) + (* c_fc_cpld = "973" *) + (* c_fc_cplh = "36" *) + (* c_fc_npd = "24" *) + (* c_fc_nph = "12" *) + (* c_fc_pd = "949" *) + (* c_fc_ph = "32" *) + (* c_gen1 = "1'b1" *) + (* c_header_type = "00" *) + (* c_hw_auton_spd_disable = "FALSE" *) + (* c_int_width = "64" *) + (* c_last_cfg_dw = "10C" *) + (* c_link_cap_aspm_optionality = "FALSE" *) + (* c_ll_ack_timeout = "0000" *) + (* c_ll_ack_timeout_enable = "FALSE" *) + (* c_ll_ack_timeout_function = "0" *) + (* c_ll_replay_timeout = "0000" *) + (* c_ll_replay_timeout_enable = "FALSE" *) + (* c_ll_replay_timeout_func = "1" *) + (* c_lnk_bndwdt_notif = "FALSE" *) + (* c_msi = "0" *) + (* c_msi_64b_addr = "TRUE" *) + (* c_msi_cap_on = "FALSE" *) + (* c_msi_mult_msg_extn = "0" *) + (* c_msi_per_vctr_mask_cap = "FALSE" *) + (* c_msix_cap_on = "FALSE" *) + (* c_msix_next_ptr = "00" *) + (* c_msix_pba_bir = "0" *) + (* c_msix_pba_offset = "0" *) + (* c_msix_table_bir = "0" *) + (* c_msix_table_offset = "0" *) + (* c_msix_table_size = "000" *) + (* c_pci_cfg_space_addr = "3F" *) + (* c_pcie_blk_locn = "0" *) + (* c_pcie_cap_next_ptr = "00" *) + (* c_pcie_cap_slot_implemented = "FALSE" *) + (* c_pcie_dbg_ports = "TRUE" *) + (* c_pcie_fast_config = "0" *) + (* c_perf_level_high = "TRUE" *) + (* c_phantom_functions = "0" *) + (* c_pm_cap_next_ptr = "60" *) + (* c_pme_support = "0F" *) + (* c_rbar_base_ptr = "000" *) + (* c_rbar_cap_control_encodedbar0 = "00" *) + (* c_rbar_cap_control_encodedbar1 = "00" *) + (* c_rbar_cap_control_encodedbar2 = "00" *) + (* c_rbar_cap_control_encodedbar3 = "00" *) + (* c_rbar_cap_control_encodedbar4 = "00" *) + (* c_rbar_cap_control_encodedbar5 = "00" *) + (* c_rbar_cap_index0 = "0" *) + (* c_rbar_cap_index1 = "0" *) + (* c_rbar_cap_index2 = "0" *) + (* c_rbar_cap_index3 = "0" *) + (* c_rbar_cap_index4 = "0" *) + (* c_rbar_cap_index5 = "0" *) + (* c_rbar_cap_nextptr = "000" *) + (* c_rbar_cap_on = "FALSE" *) + (* c_rbar_cap_sup0 = "00001" *) + (* c_rbar_cap_sup1 = "00001" *) + (* c_rbar_cap_sup2 = "00001" *) + (* c_rbar_cap_sup3 = "00001" *) + (* c_rbar_cap_sup4 = "00001" *) + (* c_rbar_cap_sup5 = "00001" *) + (* c_rbar_num = "0" *) + (* c_rcb = "0" *) + (* c_recrc_check = "0" *) + (* c_recrc_check_trim = "FALSE" *) + (* c_rev_gt_order = "FALSE" *) + (* c_root_cap_crs = "FALSE" *) + (* c_rx_raddr_lat = "0" *) + (* c_rx_ram_limit = "FFF" *) + (* c_rx_rdata_lat = "2" *) + (* c_rx_write_lat = "0" *) + (* c_silicon_rev = "2" *) + (* c_slot_cap_attn_butn = "FALSE" *) + (* c_slot_cap_attn_ind = "FALSE" *) + (* c_slot_cap_elec_interlock = "FALSE" *) + (* c_slot_cap_hotplug_cap = "FALSE" *) + (* c_slot_cap_hotplug_surprise = "FALSE" *) + (* c_slot_cap_mrl = "FALSE" *) + (* c_slot_cap_no_cmd_comp_sup = "FALSE" *) + (* c_slot_cap_physical_slot_num = "0" *) + (* c_slot_cap_pwr_ctrl = "FALSE" *) + (* c_slot_cap_pwr_ind = "FALSE" *) + (* c_slot_cap_pwr_limit_scale = "0" *) + (* c_slot_cap_pwr_limit_value = "0" *) + (* c_surprise_dn_err_cap = "FALSE" *) + (* c_trgt_lnk_spd = "2" *) + (* c_trn_np_fc = "TRUE" *) + (* c_tx_last_tlp = "30" *) + (* c_tx_raddr_lat = "0" *) + (* c_tx_rdata_lat = "2" *) + (* c_tx_write_lat = "0" *) + (* c_upconfig_capable = "TRUE" *) + (* c_upstream_facing = "TRUE" *) + (* c_ur_atomic = "FALSE" *) + (* c_ur_inv_req = "TRUE" *) + (* c_ur_prs_response = "TRUE" *) + (* c_vc_base_ptr = "000" *) + (* c_vc_cap_enabled = "FALSE" *) + (* c_vc_cap_reject_snoop = "FALSE" *) + (* c_vc_next_ptr = "000" *) + (* c_vsec_base_ptr = "000" *) + (* c_vsec_cap_enabled = "FALSE" *) + (* c_vsec_next_ptr = "000" *) + (* c_xlnx_ref_board = "ZC706" *) + (* cap_ver = "2" *) + (* cardbus_cis_ptr = "00000000" *) + (* cmps = "3" *) + (* con_scl_fctr_d0_state = "0" *) + (* con_scl_fctr_d1_state = "0" *) + (* con_scl_fctr_d2_state = "0" *) + (* con_scl_fctr_d3_state = "0" *) + (* cost_table = "1" *) + (* d1_sup = "0" *) + (* d2_sup = "0" *) + (* dev_id = "7024" *) + (* dev_port_type = "0000" *) + (* dis_scl_fctr_d0_state = "0" *) + (* dis_scl_fctr_d1_state = "0" *) + (* dis_scl_fctr_d2_state = "0" *) + (* dis_scl_fctr_d3_state = "0" *) + (* dsi = "0" *) + (* ep_l0s_accpt_lat = "000" *) + (* ep_l1_accpt_lat = "111" *) + (* ext_tag_fld_sup = "FALSE" *) + (* int_pin = "1" *) + (* intx = "TRUE" *) + (* max_lnk_spd = "2" *) + (* max_lnk_wdt = "000100" *) + (* mps = "011" *) + (* no_soft_rst = "TRUE" *) + (* pci_exp_int_freq = "3" *) + (* pci_exp_ref_freq = "0" *) + (* phantm_func_sup = "00" *) + (* pme_sup = "0F" *) + (* pwr_con_d0_state = "00" *) + (* pwr_con_d1_state = "00" *) + (* pwr_con_d2_state = "00" *) + (* pwr_con_d3_state = "00" *) + (* pwr_dis_d0_state = "00" *) + (* pwr_dis_d1_state = "00" *) + (* pwr_dis_d2_state = "00" *) + (* pwr_dis_d3_state = "00" *) + (* rev_id = "00" *) + (* slot_clk = "TRUE" *) + (* subsys_id = "0007" *) + (* subsys_ven_id = "10EE" *) + (* ven_id = "10EE" *) + (* xrom_bar = "00000000" *) + pcie_7x_0_pcie_7x_0_pcie2_top inst + (.cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en), + .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en), + .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum), + .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received), + .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en), + .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received), + .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en), + .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received), + .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en), + .cfg_bridge_serr_en(cfg_bridge_serr_en), + .cfg_bus_number(cfg_bus_number), + .cfg_command({NLW_inst_cfg_command_UNCONNECTED[15:11],\^cfg_command }), + .cfg_dcommand({NLW_inst_cfg_dcommand_UNCONNECTED[15],\^cfg_dcommand }), + .cfg_dcommand2({NLW_inst_cfg_dcommand2_UNCONNECTED[15:12],\^cfg_dcommand2 }), + .cfg_device_number(cfg_device_number), + .cfg_ds_bus_number(cfg_ds_bus_number), + .cfg_ds_device_number(cfg_ds_device_number), + .cfg_ds_function_number(cfg_ds_function_number), + .cfg_dsn(cfg_dsn), + .cfg_dstatus({NLW_inst_cfg_dstatus_UNCONNECTED[15:6],\^cfg_dstatus }), + .cfg_err_acs(1'b0), + .cfg_err_aer_headerlog(cfg_err_aer_headerlog), + .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set), + .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked), + .cfg_err_cor(cfg_err_cor), + .cfg_err_cpl_abort(cfg_err_cpl_abort), + .cfg_err_cpl_rdy(cfg_err_cpl_rdy), + .cfg_err_cpl_timeout(cfg_err_cpl_timeout), + .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect), + .cfg_err_ecrc(cfg_err_ecrc), + .cfg_err_internal_cor(cfg_err_internal_cor), + .cfg_err_internal_uncor(cfg_err_internal_uncor), + .cfg_err_locked(cfg_err_locked), + .cfg_err_malformed(cfg_err_malformed), + .cfg_err_mc_blocked(cfg_err_mc_blocked), + .cfg_err_norecovery(cfg_err_norecovery), + .cfg_err_poisoned(cfg_err_poisoned), + .cfg_err_posted(cfg_err_posted), + .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header), + .cfg_err_ur(cfg_err_ur), + .cfg_function_number(cfg_function_number), + .cfg_interrupt(cfg_interrupt), + .cfg_interrupt_assert(cfg_interrupt_assert), + .cfg_interrupt_di(cfg_interrupt_di), + .cfg_interrupt_do(cfg_interrupt_do), + .cfg_interrupt_mmenable(cfg_interrupt_mmenable), + .cfg_interrupt_msienable(cfg_interrupt_msienable), + .cfg_interrupt_msixenable(cfg_interrupt_msixenable), + .cfg_interrupt_msixfm(cfg_interrupt_msixfm), + .cfg_interrupt_rdy(cfg_interrupt_rdy), + .cfg_interrupt_stat(cfg_interrupt_stat), + .cfg_lcommand({NLW_inst_cfg_lcommand_UNCONNECTED[15:12],\^cfg_lcommand }), + .cfg_lstatus(\^cfg_lstatus ), + .cfg_mgmt_byte_en(cfg_mgmt_byte_en), + .cfg_mgmt_di(cfg_mgmt_di), + .cfg_mgmt_do(cfg_mgmt_do), + .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr), + .cfg_mgmt_rd_en(cfg_mgmt_rd_en), + .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done), + .cfg_mgmt_wr_en(cfg_mgmt_wr_en), + .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly), + .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw), + .cfg_msg_data(cfg_msg_data), + .cfg_msg_received(cfg_msg_received), + .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a), + .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b), + .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c), + .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d), + .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a), + .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b), + .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c), + .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d), + .cfg_msg_received_err_cor(cfg_msg_received_err_cor), + .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal), + .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal), + .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak), + .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme), + .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack), + .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit), + .cfg_pcie_link_state(cfg_pcie_link_state), + .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum), + .cfg_pm_force_state(cfg_pm_force_state), + .cfg_pm_force_state_en(cfg_pm_force_state_en), + .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s), + .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1), + .cfg_pm_send_pme_to(1'b0), + .cfg_pm_wake(cfg_pm_wake), + .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en), + .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status), + .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate), + .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst), + .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en), + .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en), + .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en), + .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en), + .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse), + .cfg_status(NLW_inst_cfg_status_UNCONNECTED[15:0]), + .cfg_to_turnoff(cfg_to_turnoff), + .cfg_trn_pending(cfg_trn_pending), + .cfg_turnoff_ok(cfg_turnoff_ok), + .cfg_vc_tcvc_map(cfg_vc_tcvc_map), + .common_commands_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .common_commands_out(NLW_inst_common_commands_out_UNCONNECTED[11:0]), + .ext_ch_gt_drpaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ext_ch_gt_drpclk(NLW_inst_ext_ch_gt_drpclk_UNCONNECTED), + .ext_ch_gt_drpdi({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ext_ch_gt_drpdo(NLW_inst_ext_ch_gt_drpdo_UNCONNECTED[63:0]), + .ext_ch_gt_drpen({1'b0,1'b0,1'b0,1'b0}), + .ext_ch_gt_drprdy(NLW_inst_ext_ch_gt_drprdy_UNCONNECTED[3:0]), + .ext_ch_gt_drpwe({1'b0,1'b0,1'b0,1'b0}), + .fc_cpld(fc_cpld), + .fc_cplh(fc_cplh), + .fc_npd(fc_npd), + .fc_nph(fc_nph), + .fc_pd(fc_pd), + .fc_ph(fc_ph), + .fc_sel(fc_sel), + .gt_ch_drp_rdy(NLW_inst_gt_ch_drp_rdy_UNCONNECTED[3:0]), + .icap_clk(1'b0), + .icap_csib(1'b0), + .icap_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .icap_o(NLW_inst_icap_o_UNCONNECTED[31:0]), + .icap_rdwrb(1'b0), + .int_dclk_out(NLW_inst_int_dclk_out_UNCONNECTED), + .int_mmcm_lock_out(NLW_inst_int_mmcm_lock_out_UNCONNECTED), + .int_oobclk_out(NLW_inst_int_oobclk_out_UNCONNECTED), + .int_pclk_out_slave(NLW_inst_int_pclk_out_slave_UNCONNECTED), + .int_pclk_sel_slave({1'b0,1'b0,1'b0,1'b0}), + .int_pipe_rxusrclk_out(NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED), + .int_qplllock_out(NLW_inst_int_qplllock_out_UNCONNECTED[1:0]), + .int_qplloutclk_out(NLW_inst_int_qplloutclk_out_UNCONNECTED[1:0]), + .int_qplloutrefclk_out(NLW_inst_int_qplloutrefclk_out_UNCONNECTED[1:0]), + .int_rxoutclk_out(NLW_inst_int_rxoutclk_out_UNCONNECTED[3:0]), + .int_userclk1_out(NLW_inst_int_userclk1_out_UNCONNECTED), + .int_userclk2_out(NLW_inst_int_userclk2_out_UNCONNECTED), + .m_axis_rx_tdata(m_axis_rx_tdata), + .m_axis_rx_tkeep({\^m_axis_rx_tkeep ,NLW_inst_m_axis_rx_tkeep_UNCONNECTED[3:0]}), + .m_axis_rx_tlast(m_axis_rx_tlast), + .m_axis_rx_tready(m_axis_rx_tready), + .m_axis_rx_tuser(\^m_axis_rx_tuser ), + .m_axis_rx_tvalid(m_axis_rx_tvalid), + .pci_exp_rxn(pci_exp_rxn), + .pci_exp_rxp(pci_exp_rxp), + .pci_exp_txn(pci_exp_txn), + .pci_exp_txp(pci_exp_txp), + .pcie_drp_addr(pcie_drp_addr), + .pcie_drp_clk(pcie_drp_clk), + .pcie_drp_di(pcie_drp_di), + .pcie_drp_do(pcie_drp_do), + .pcie_drp_en(pcie_drp_en), + .pcie_drp_rdy(pcie_drp_rdy), + .pcie_drp_we(pcie_drp_we), + .pipe_cpll_lock(NLW_inst_pipe_cpll_lock_UNCONNECTED[3:0]), + .pipe_dclk_in(pipe_dclk_in), + .pipe_debug(NLW_inst_pipe_debug_UNCONNECTED[31:0]), + .pipe_debug_0(NLW_inst_pipe_debug_0_UNCONNECTED[3:0]), + .pipe_debug_1(NLW_inst_pipe_debug_1_UNCONNECTED[3:0]), + .pipe_debug_2(NLW_inst_pipe_debug_2_UNCONNECTED[3:0]), + .pipe_debug_3(NLW_inst_pipe_debug_3_UNCONNECTED[3:0]), + .pipe_debug_4(NLW_inst_pipe_debug_4_UNCONNECTED[3:0]), + .pipe_debug_5(NLW_inst_pipe_debug_5_UNCONNECTED[3:0]), + .pipe_debug_6(NLW_inst_pipe_debug_6_UNCONNECTED[3:0]), + .pipe_debug_7(NLW_inst_pipe_debug_7_UNCONNECTED[3:0]), + .pipe_debug_8(NLW_inst_pipe_debug_8_UNCONNECTED[3:0]), + .pipe_debug_9(NLW_inst_pipe_debug_9_UNCONNECTED[3:0]), + .pipe_dmonitorout(NLW_inst_pipe_dmonitorout_UNCONNECTED[59:0]), + .pipe_drp_fsm(NLW_inst_pipe_drp_fsm_UNCONNECTED[27:0]), + .pipe_eyescandataerror(NLW_inst_pipe_eyescandataerror_UNCONNECTED[3:0]), + .pipe_gen3_out(pipe_gen3_out), + .pipe_loopback({1'b0,1'b0,1'b0}), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_mmcm_rst_n(1'b0), + .pipe_oobclk_in(pipe_oobclk_in), + .pipe_pclk_in(pipe_pclk_in), + .pipe_pclk_sel_out(pipe_pclk_sel_out), + .pipe_qpll_lock(NLW_inst_pipe_qpll_lock_UNCONNECTED[0]), + .pipe_qrst_fsm(NLW_inst_pipe_qrst_fsm_UNCONNECTED[11:0]), + .pipe_qrst_idle(NLW_inst_pipe_qrst_idle_UNCONNECTED), + .pipe_rate_fsm(NLW_inst_pipe_rate_fsm_UNCONNECTED[19:0]), + .pipe_rate_idle(NLW_inst_pipe_rate_idle_UNCONNECTED), + .pipe_rst_fsm(NLW_inst_pipe_rst_fsm_UNCONNECTED[4:0]), + .pipe_rst_idle(NLW_inst_pipe_rst_idle_UNCONNECTED), + .pipe_rx_0_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .pipe_rx_1_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .pipe_rx_2_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .pipe_rx_3_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .pipe_rx_4_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .pipe_rx_5_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .pipe_rx_6_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .pipe_rx_7_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .pipe_rxbufstatus(NLW_inst_pipe_rxbufstatus_UNCONNECTED[11:0]), + .pipe_rxcommadet(NLW_inst_pipe_rxcommadet_UNCONNECTED[3:0]), + .pipe_rxdisperr(NLW_inst_pipe_rxdisperr_UNCONNECTED[31:0]), + .pipe_rxdlysresetdone(NLW_inst_pipe_rxdlysresetdone_UNCONNECTED[3:0]), + .pipe_rxnotintable(NLW_inst_pipe_rxnotintable_UNCONNECTED[31:0]), + .pipe_rxoutclk_in({1'b0,1'b0,1'b0,1'b0}), + .pipe_rxoutclk_out(pipe_rxoutclk_out), + .pipe_rxphaligndone(NLW_inst_pipe_rxphaligndone_UNCONNECTED[3:0]), + .pipe_rxpmaresetdone(NLW_inst_pipe_rxpmaresetdone_UNCONNECTED[3:0]), + .pipe_rxprbscntreset(1'b0), + .pipe_rxprbserr(NLW_inst_pipe_rxprbserr_UNCONNECTED[3:0]), + .pipe_rxprbssel({1'b0,1'b0,1'b0}), + .pipe_rxstatus(NLW_inst_pipe_rxstatus_UNCONNECTED[11:0]), + .pipe_rxsyncdone(NLW_inst_pipe_rxsyncdone_UNCONNECTED[3:0]), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .pipe_sync_fsm_rx(NLW_inst_pipe_sync_fsm_rx_UNCONNECTED[27:0]), + .pipe_sync_fsm_tx(NLW_inst_pipe_sync_fsm_tx_UNCONNECTED[23:0]), + .pipe_tx_0_sigs(NLW_inst_pipe_tx_0_sigs_UNCONNECTED[24:0]), + .pipe_tx_1_sigs(NLW_inst_pipe_tx_1_sigs_UNCONNECTED[24:0]), + .pipe_tx_2_sigs(NLW_inst_pipe_tx_2_sigs_UNCONNECTED[24:0]), + .pipe_tx_3_sigs(NLW_inst_pipe_tx_3_sigs_UNCONNECTED[24:0]), + .pipe_tx_4_sigs(NLW_inst_pipe_tx_4_sigs_UNCONNECTED[24:0]), + .pipe_tx_5_sigs(NLW_inst_pipe_tx_5_sigs_UNCONNECTED[24:0]), + .pipe_tx_6_sigs(NLW_inst_pipe_tx_6_sigs_UNCONNECTED[24:0]), + .pipe_tx_7_sigs(NLW_inst_pipe_tx_7_sigs_UNCONNECTED[24:0]), + .pipe_txdlysresetdone(NLW_inst_pipe_txdlysresetdone_UNCONNECTED[3:0]), + .pipe_txinhibit({1'b0,1'b0,1'b0,1'b0}), + .pipe_txoutclk_out(pipe_txoutclk_out), + .pipe_txphaligndone(NLW_inst_pipe_txphaligndone_UNCONNECTED[3:0]), + .pipe_txphinitdone(NLW_inst_pipe_txphinitdone_UNCONNECTED[3:0]), + .pipe_txprbsforceerr(1'b0), + .pipe_txprbssel({1'b0,1'b0,1'b0}), + .pipe_userclk1_in(pipe_userclk1_in), + .pipe_userclk2_in(pipe_userclk2_in), + .pl_directed_change_done(pl_directed_change_done), + .pl_directed_link_auton(pl_directed_link_auton), + .pl_directed_link_change(pl_directed_link_change), + .pl_directed_link_speed(pl_directed_link_speed), + .pl_directed_link_width(pl_directed_link_width), + .pl_downstream_deemph_source(pl_downstream_deemph_source), + .pl_initial_link_width(pl_initial_link_width), + .pl_lane_reversal_mode(pl_lane_reversal_mode), + .pl_link_gen2_cap(pl_link_gen2_cap), + .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported), + .pl_link_upcfg_cap(pl_link_upcfg_cap), + .pl_ltssm_state(pl_ltssm_state), + .pl_phy_lnk_up(pl_phy_lnk_up), + .pl_received_hot_rst(pl_received_hot_rst), + .pl_rx_pm_state(pl_rx_pm_state), + .pl_sel_lnk_rate(pl_sel_lnk_rate), + .pl_sel_lnk_width(pl_sel_lnk_width), + .pl_transmit_hot_rst(pl_transmit_hot_rst), + .pl_tx_pm_state(pl_tx_pm_state), + .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph), + .qpll_drp_clk(NLW_inst_qpll_drp_clk_UNCONNECTED), + .qpll_drp_crscode({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .qpll_drp_done({1'b0,1'b0}), + .qpll_drp_fsm({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .qpll_drp_gen3(NLW_inst_qpll_drp_gen3_UNCONNECTED), + .qpll_drp_ovrd(NLW_inst_qpll_drp_ovrd_UNCONNECTED), + .qpll_drp_reset({1'b0,1'b0}), + .qpll_drp_rst_n(NLW_inst_qpll_drp_rst_n_UNCONNECTED), + .qpll_drp_start(NLW_inst_qpll_drp_start_UNCONNECTED), + .qpll_qplld(NLW_inst_qpll_qplld_UNCONNECTED), + .qpll_qplllock({1'b0,1'b0}), + .qpll_qplloutclk({1'b0,1'b0}), + .qpll_qplloutrefclk({1'b0,1'b0}), + .qpll_qpllreset(NLW_inst_qpll_qpllreset_UNCONNECTED[1:0]), + .rx_np_ok(rx_np_ok), + .rx_np_req(rx_np_req), + .s_axis_tx_tdata(s_axis_tx_tdata), + .s_axis_tx_tkeep({s_axis_tx_tkeep[7],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axis_tx_tlast(s_axis_tx_tlast), + .s_axis_tx_tready(s_axis_tx_tready), + .s_axis_tx_tuser(s_axis_tx_tuser), + .s_axis_tx_tvalid(s_axis_tx_tvalid), + .startup_cfgclk(NLW_inst_startup_cfgclk_UNCONNECTED), + .startup_cfgmclk(NLW_inst_startup_cfgmclk_UNCONNECTED), + .startup_clk(1'b0), + .startup_eos(NLW_inst_startup_eos_UNCONNECTED), + .startup_eos_in(1'b0), + .startup_gsr(1'b0), + .startup_gts(1'b0), + .startup_keyclearb(1'b1), + .startup_pack(1'b0), + .startup_preq(NLW_inst_startup_preq_UNCONNECTED), + .startup_usrcclko(1'b1), + .startup_usrcclkts(1'b0), + .startup_usrdoneo(1'b0), + .startup_usrdonets(1'b1), + .sys_clk(sys_clk), + .sys_rst_n(sys_rst_n), + .tx_buf_av(tx_buf_av), + .tx_cfg_gnt(tx_cfg_gnt), + .tx_cfg_req(tx_cfg_req), + .tx_err_drop(tx_err_drop), + .user_app_rdy(NLW_inst_user_app_rdy_UNCONNECTED), + .user_clk_out(user_clk_out), + .user_lnk_up(user_lnk_up), + .user_reset_out(user_reset_out)); +endmodule + +module pcie_7x_0_pcie_7x_0_axi_basic_rx + (E, + trn_rsrc_dsc_d, + m_axis_rx_tvalid_reg, + m_axis_rx_tkeep, + m_axis_rx_tlast, + trn_in_packet, + reg_dsc_detect_reg, + m_axis_rx_tuser, + Q, + \trn_rbar_hit_prev_reg[0] , + pipe_userclk2_in, + trn_rrem, + trn_rsrc_dsc, + rsrc_rdy_filtered, + trn_reof, + trn_rsrc_dsc_prev0, + trn_rsof, + trn_recrc_err, + trn_rerrfwd, + trn_in_packet_reg, + m_axis_rx_tready, + dsc_detect, + trn_rd, + trn_rbar_hit); + output [0:0]E; + output trn_rsrc_dsc_d; + output m_axis_rx_tvalid_reg; + output [0:0]m_axis_rx_tkeep; + output m_axis_rx_tlast; + output trn_in_packet; + output reg_dsc_detect_reg; + output [12:0]m_axis_rx_tuser; + output [63:0]Q; + input \trn_rbar_hit_prev_reg[0] ; + input pipe_userclk2_in; + input [0:0]trn_rrem; + input trn_rsrc_dsc; + input rsrc_rdy_filtered; + input trn_reof; + input trn_rsrc_dsc_prev0; + input trn_rsof; + input trn_recrc_err; + input trn_rerrfwd; + input trn_in_packet_reg; + input m_axis_rx_tready; + input dsc_detect; + input [63:0]trn_rd; + input [6:0]trn_rbar_hit; + + wire [0:0]E; + wire [63:0]Q; + wire dsc_detect; + wire [0:0]m_axis_rx_tkeep; + wire m_axis_rx_tlast; + wire m_axis_rx_tready; + wire [12:0]m_axis_rx_tuser; + wire m_axis_rx_tvalid_reg; + wire [10:0]new_pkt_len; + wire null_mux_sel; + wire pipe_userclk2_in; + wire reg_dsc_detect_reg; + wire rsrc_rdy_filtered; + wire rx_null_gen_inst_n_0; + wire rx_null_gen_inst_n_1; + wire rx_null_gen_inst_n_2; + wire rx_null_gen_inst_n_3; + wire rx_null_gen_inst_n_4; + wire rx_null_gen_inst_n_5; + wire rx_null_gen_inst_n_6; + wire rx_null_gen_inst_n_7; + wire rx_null_gen_inst_n_8; + wire rx_pipeline_inst_n_73; + wire rx_pipeline_inst_n_74; + wire rx_pipeline_inst_n_8; + wire trn_in_packet; + wire trn_in_packet_reg; + wire [6:0]trn_rbar_hit; + wire \trn_rbar_hit_prev_reg[0] ; + wire [63:0]trn_rd; + wire trn_recrc_err; + wire trn_reof; + wire trn_rerrfwd; + wire [0:0]trn_rrem; + wire trn_rsof; + wire trn_rsrc_dsc; + wire trn_rsrc_dsc_d; + wire trn_rsrc_dsc_prev0; + + pcie_7x_0_pcie_7x_0_axi_basic_rx_null_gen rx_null_gen_inst + (.D({rx_null_gen_inst_n_0,rx_null_gen_inst_n_1}), + .Q({Q[30:29],Q[15],Q[1:0]}), + .S({rx_null_gen_inst_n_7,rx_null_gen_inst_n_8}), + .cur_state_reg_0(\trn_rbar_hit_prev_reg[0] ), + .cur_state_reg_1(m_axis_rx_tvalid_reg), + .m_axis_rx_tready(m_axis_rx_tready), + .m_axis_rx_tuser(m_axis_rx_tuser[12]), + .\m_axis_rx_tuser_reg[19] (rx_pipeline_inst_n_74), + .\m_axis_rx_tuser_reg[21] (rx_pipeline_inst_n_73), + .new_pkt_len(new_pkt_len), + .null_mux_sel(null_mux_sel), + .null_mux_sel_reg(rx_null_gen_inst_n_5), + .null_mux_sel_reg_0(rx_null_gen_inst_n_6), + .null_mux_sel_reg_1(rx_pipeline_inst_n_8), + .pipe_userclk2_in(pipe_userclk2_in), + .\reg_pkt_len_counter_reg[0]_0 (rx_null_gen_inst_n_4), + .\reg_pkt_len_counter_reg[3]_0 (rx_null_gen_inst_n_3), + .\reg_tkeep[7]_i_7_0 (rx_null_gen_inst_n_2)); + pcie_7x_0_pcie_7x_0_axi_basic_rx_pipeline rx_pipeline_inst + (.D({rx_null_gen_inst_n_0,rx_null_gen_inst_n_1}), + .E(E), + .Q(Q), + .S({rx_null_gen_inst_n_7,rx_null_gen_inst_n_8}), + .data_prev_reg_0(rx_pipeline_inst_n_73), + .data_prev_reg_1(rx_pipeline_inst_n_74), + .dsc_detect(dsc_detect), + .m_axis_rx_tkeep(m_axis_rx_tkeep), + .m_axis_rx_tlast(m_axis_rx_tlast), + .m_axis_rx_tready(m_axis_rx_tready), + .m_axis_rx_tuser(m_axis_rx_tuser), + .m_axis_rx_tvalid_reg_0(m_axis_rx_tvalid_reg), + .new_pkt_len(new_pkt_len), + .null_mux_sel(null_mux_sel), + .null_mux_sel_reg_0(rx_null_gen_inst_n_5), + .pipe_userclk2_in(pipe_userclk2_in), + .reg_dsc_detect_reg_0(reg_dsc_detect_reg), + .\reg_tkeep_reg[7]_0 (rx_null_gen_inst_n_3), + .reg_tlast_reg_0(rx_null_gen_inst_n_6), + .rsrc_rdy_filtered(rsrc_rdy_filtered), + .trn_in_packet(trn_in_packet), + .trn_in_packet_reg_0(trn_in_packet_reg), + .trn_rbar_hit(trn_rbar_hit), + .\trn_rbar_hit_prev_reg[0]_0 (\trn_rbar_hit_prev_reg[0] ), + .trn_rd(trn_rd), + .trn_rdst_rdy_reg_0(rx_null_gen_inst_n_2), + .trn_rdst_rdy_reg_1(rx_null_gen_inst_n_4), + .trn_recrc_err(trn_recrc_err), + .trn_reof(trn_reof), + .trn_rerrfwd(trn_rerrfwd), + .trn_rrem(trn_rrem), + .trn_rsof(trn_rsof), + .trn_rsrc_dsc(trn_rsrc_dsc), + .trn_rsrc_dsc_d(trn_rsrc_dsc_d), + .trn_rsrc_dsc_prev0(trn_rsrc_dsc_prev0), + .user_reset_out_reg(rx_pipeline_inst_n_8)); +endmodule + +module pcie_7x_0_pcie_7x_0_axi_basic_rx_null_gen + (D, + \reg_tkeep[7]_i_7_0 , + \reg_pkt_len_counter_reg[3]_0 , + \reg_pkt_len_counter_reg[0]_0 , + null_mux_sel_reg, + null_mux_sel_reg_0, + S, + cur_state_reg_0, + pipe_userclk2_in, + null_mux_sel, + \m_axis_rx_tuser_reg[19] , + new_pkt_len, + m_axis_rx_tready, + null_mux_sel_reg_1, + cur_state_reg_1, + m_axis_rx_tuser, + \m_axis_rx_tuser_reg[21] , + Q); + output [1:0]D; + output \reg_tkeep[7]_i_7_0 ; + output \reg_pkt_len_counter_reg[3]_0 ; + output \reg_pkt_len_counter_reg[0]_0 ; + output null_mux_sel_reg; + output null_mux_sel_reg_0; + output [1:0]S; + input cur_state_reg_0; + input pipe_userclk2_in; + input null_mux_sel; + input \m_axis_rx_tuser_reg[19] ; + input [10:0]new_pkt_len; + input m_axis_rx_tready; + input null_mux_sel_reg_1; + input cur_state_reg_1; + input [0:0]m_axis_rx_tuser; + input \m_axis_rx_tuser_reg[21] ; + input [4:0]Q; + + wire [1:0]D; + wire [4:0]Q; + wire [1:0]S; + wire cur_state; + wire cur_state_reg_0; + wire cur_state_reg_1; + wire m_axis_rx_tready; + wire [0:0]m_axis_rx_tuser; + wire \m_axis_rx_tuser_reg[19] ; + wire \m_axis_rx_tuser_reg[21] ; + wire [10:0]new_pkt_len; + wire next_state; + wire null_mux_sel; + wire null_mux_sel_reg; + wire null_mux_sel_reg_0; + wire null_mux_sel_reg_1; + wire pipe_userclk2_in; + wire [11:1]pkt_len_counter; + wire [1:0]pkt_len_counter_0; + wire pkt_len_counter_dec__0_carry__0_i_1_n_0; + wire pkt_len_counter_dec__0_carry__0_i_2_n_0; + wire pkt_len_counter_dec__0_carry__0_i_3_n_0; + wire pkt_len_counter_dec__0_carry__0_i_4_n_0; + wire pkt_len_counter_dec__0_carry__0_n_0; + wire pkt_len_counter_dec__0_carry__0_n_1; + wire pkt_len_counter_dec__0_carry__0_n_2; + wire pkt_len_counter_dec__0_carry__0_n_3; + wire pkt_len_counter_dec__0_carry__1_i_1_n_0; + wire pkt_len_counter_dec__0_carry__1_i_2_n_0; + wire pkt_len_counter_dec__0_carry__1_i_3_n_0; + wire pkt_len_counter_dec__0_carry__1_n_2; + wire pkt_len_counter_dec__0_carry__1_n_3; + wire pkt_len_counter_dec__0_carry_i_1_n_0; + wire pkt_len_counter_dec__0_carry_i_2_n_0; + wire pkt_len_counter_dec__0_carry_i_3_n_0; + wire pkt_len_counter_dec__0_carry_i_4_n_0; + wire pkt_len_counter_dec__0_carry_i_5_n_0; + wire pkt_len_counter_dec__0_carry_n_0; + wire pkt_len_counter_dec__0_carry_n_1; + wire pkt_len_counter_dec__0_carry_n_2; + wire pkt_len_counter_dec__0_carry_n_3; + wire [11:0]reg_pkt_len_counter; + wire \reg_pkt_len_counter[11]_i_2_n_0 ; + wire \reg_pkt_len_counter[11]_i_3_n_0 ; + wire \reg_pkt_len_counter[11]_i_4_n_0 ; + wire \reg_pkt_len_counter_reg[0]_0 ; + wire \reg_pkt_len_counter_reg[3]_0 ; + wire \reg_tkeep[7]_i_4_n_0 ; + wire \reg_tkeep[7]_i_5_n_0 ; + wire \reg_tkeep[7]_i_6_n_0 ; + wire \reg_tkeep[7]_i_7_0 ; + wire \reg_tkeep[7]_i_7_n_0 ; + wire [11:2]sel0; + wire [3:2]NLW_pkt_len_counter_dec__0_carry__1_CO_UNCONNECTED; + wire [3:3]NLW_pkt_len_counter_dec__0_carry__1_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hAAAAAAEA)) + cur_state_i_1 + (.I0(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I1(m_axis_rx_tready), + .I2(cur_state_reg_1), + .I3(cur_state), + .I4(m_axis_rx_tuser), + .O(next_state)); + FDRE cur_state_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(next_state), + .Q(cur_state), + .R(cur_state_reg_0)); + LUT6 #( + .INIT(64'h5555555500000400)) + \m_axis_rx_tuser[19]_i_1 + (.I0(cur_state_reg_0), + .I1(\reg_tkeep[7]_i_7_0 ), + .I2(\reg_pkt_len_counter_reg[3]_0 ), + .I3(null_mux_sel), + .I4(pkt_len_counter_0[0]), + .I5(\m_axis_rx_tuser_reg[19] ), + .O(D[0])); + LUT6 #( + .INIT(64'h00000000FF80FF08)) + \m_axis_rx_tuser[21]_i_2 + (.I0(\reg_tkeep[7]_i_7_0 ), + .I1(null_mux_sel), + .I2(\reg_pkt_len_counter_reg[3]_0 ), + .I3(\m_axis_rx_tuser_reg[21] ), + .I4(pkt_len_counter_0[0]), + .I5(cur_state_reg_0), + .O(D[1])); + LUT6 #( + .INIT(64'h0000000077F7FFFF)) + null_mux_sel_i_1 + (.I0(\reg_tkeep[7]_i_7_0 ), + .I1(null_mux_sel), + .I2(pkt_len_counter_0[0]), + .I3(\reg_pkt_len_counter_reg[3]_0 ), + .I4(m_axis_rx_tready), + .I5(null_mux_sel_reg_1), + .O(null_mux_sel_reg)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 pkt_len_counter_dec__0_carry + (.CI(1'b0), + .CO({pkt_len_counter_dec__0_carry_n_0,pkt_len_counter_dec__0_carry_n_1,pkt_len_counter_dec__0_carry_n_2,pkt_len_counter_dec__0_carry_n_3}), + .CYINIT(1'b0), + .DI({reg_pkt_len_counter[3:2],pkt_len_counter_dec__0_carry_i_1_n_0,1'b0}), + .O(pkt_len_counter[4:1]), + .S({pkt_len_counter_dec__0_carry_i_2_n_0,pkt_len_counter_dec__0_carry_i_3_n_0,pkt_len_counter_dec__0_carry_i_4_n_0,pkt_len_counter_dec__0_carry_i_5_n_0})); + (* ADDER_THRESHOLD = "35" *) + CARRY4 pkt_len_counter_dec__0_carry__0 + (.CI(pkt_len_counter_dec__0_carry_n_0), + .CO({pkt_len_counter_dec__0_carry__0_n_0,pkt_len_counter_dec__0_carry__0_n_1,pkt_len_counter_dec__0_carry__0_n_2,pkt_len_counter_dec__0_carry__0_n_3}), + .CYINIT(1'b0), + .DI(reg_pkt_len_counter[7:4]), + .O(pkt_len_counter[8:5]), + .S({pkt_len_counter_dec__0_carry__0_i_1_n_0,pkt_len_counter_dec__0_carry__0_i_2_n_0,pkt_len_counter_dec__0_carry__0_i_3_n_0,pkt_len_counter_dec__0_carry__0_i_4_n_0})); + LUT2 #( + .INIT(4'h9)) + pkt_len_counter_dec__0_carry__0_i_1 + (.I0(reg_pkt_len_counter[7]), + .I1(reg_pkt_len_counter[8]), + .O(pkt_len_counter_dec__0_carry__0_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + pkt_len_counter_dec__0_carry__0_i_2 + (.I0(reg_pkt_len_counter[6]), + .I1(reg_pkt_len_counter[7]), + .O(pkt_len_counter_dec__0_carry__0_i_2_n_0)); + LUT2 #( + .INIT(4'h9)) + pkt_len_counter_dec__0_carry__0_i_3 + (.I0(reg_pkt_len_counter[5]), + .I1(reg_pkt_len_counter[6]), + .O(pkt_len_counter_dec__0_carry__0_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + pkt_len_counter_dec__0_carry__0_i_4 + (.I0(reg_pkt_len_counter[4]), + .I1(reg_pkt_len_counter[5]), + .O(pkt_len_counter_dec__0_carry__0_i_4_n_0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 pkt_len_counter_dec__0_carry__1 + (.CI(pkt_len_counter_dec__0_carry__0_n_0), + .CO({NLW_pkt_len_counter_dec__0_carry__1_CO_UNCONNECTED[3:2],pkt_len_counter_dec__0_carry__1_n_2,pkt_len_counter_dec__0_carry__1_n_3}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,reg_pkt_len_counter[9:8]}), + .O({NLW_pkt_len_counter_dec__0_carry__1_O_UNCONNECTED[3],pkt_len_counter[11:9]}), + .S({1'b0,pkt_len_counter_dec__0_carry__1_i_1_n_0,pkt_len_counter_dec__0_carry__1_i_2_n_0,pkt_len_counter_dec__0_carry__1_i_3_n_0})); + LUT2 #( + .INIT(4'h9)) + pkt_len_counter_dec__0_carry__1_i_1 + (.I0(reg_pkt_len_counter[10]), + .I1(reg_pkt_len_counter[11]), + .O(pkt_len_counter_dec__0_carry__1_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + pkt_len_counter_dec__0_carry__1_i_2 + (.I0(reg_pkt_len_counter[9]), + .I1(reg_pkt_len_counter[10]), + .O(pkt_len_counter_dec__0_carry__1_i_2_n_0)); + LUT2 #( + .INIT(4'h9)) + pkt_len_counter_dec__0_carry__1_i_3 + (.I0(reg_pkt_len_counter[8]), + .I1(reg_pkt_len_counter[9]), + .O(pkt_len_counter_dec__0_carry__1_i_3_n_0)); + LUT2 #( + .INIT(4'hB)) + pkt_len_counter_dec__0_carry_i_1 + (.I0(reg_pkt_len_counter[1]), + .I1(m_axis_rx_tready), + .O(pkt_len_counter_dec__0_carry_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + pkt_len_counter_dec__0_carry_i_2 + (.I0(reg_pkt_len_counter[3]), + .I1(reg_pkt_len_counter[4]), + .O(pkt_len_counter_dec__0_carry_i_2_n_0)); + LUT2 #( + .INIT(4'h9)) + pkt_len_counter_dec__0_carry_i_3 + (.I0(reg_pkt_len_counter[2]), + .I1(reg_pkt_len_counter[3]), + .O(pkt_len_counter_dec__0_carry_i_3_n_0)); + LUT3 #( + .INIT(8'hD2)) + pkt_len_counter_dec__0_carry_i_4 + (.I0(m_axis_rx_tready), + .I1(reg_pkt_len_counter[1]), + .I2(reg_pkt_len_counter[2]), + .O(pkt_len_counter_dec__0_carry_i_4_n_0)); + LUT2 #( + .INIT(4'h6)) + pkt_len_counter_dec__0_carry_i_5 + (.I0(reg_pkt_len_counter[1]), + .I1(m_axis_rx_tready), + .O(pkt_len_counter_dec__0_carry_i_5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair214" *) + LUT3 #( + .INIT(8'hB8)) + \reg_pkt_len_counter[0]_i_1 + (.I0(reg_pkt_len_counter[0]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I2(new_pkt_len[0]), + .O(pkt_len_counter_0[0])); + (* SOFT_HLUTNM = "soft_lutpair211" *) + LUT3 #( + .INIT(8'hB8)) + \reg_pkt_len_counter[10]_i_1 + (.I0(pkt_len_counter[10]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I2(new_pkt_len[10]), + .O(sel0[10])); + (* SOFT_HLUTNM = "soft_lutpair211" *) + LUT2 #( + .INIT(4'h8)) + \reg_pkt_len_counter[11]_i_1 + (.I0(pkt_len_counter[11]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .O(sel0[11])); + LUT6 #( + .INIT(64'hAAAAAAA8AAAAAAAA)) + \reg_pkt_len_counter[11]_i_2 + (.I0(cur_state), + .I1(reg_pkt_len_counter[3]), + .I2(reg_pkt_len_counter[8]), + .I3(reg_pkt_len_counter[7]), + .I4(\reg_pkt_len_counter[11]_i_3_n_0 ), + .I5(\reg_pkt_len_counter[11]_i_4_n_0 ), + .O(\reg_pkt_len_counter[11]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFFEF)) + \reg_pkt_len_counter[11]_i_3 + (.I0(reg_pkt_len_counter[5]), + .I1(reg_pkt_len_counter[4]), + .I2(m_axis_rx_tready), + .I3(reg_pkt_len_counter[9]), + .O(\reg_pkt_len_counter[11]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000000000000007)) + \reg_pkt_len_counter[11]_i_4 + (.I0(reg_pkt_len_counter[0]), + .I1(reg_pkt_len_counter[1]), + .I2(reg_pkt_len_counter[2]), + .I3(reg_pkt_len_counter[6]), + .I4(reg_pkt_len_counter[10]), + .I5(reg_pkt_len_counter[11]), + .O(\reg_pkt_len_counter[11]_i_4_n_0 )); + LUT3 #( + .INIT(8'hE2)) + \reg_pkt_len_counter[1]_i_1 + (.I0(new_pkt_len[1]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I2(pkt_len_counter[1]), + .O(pkt_len_counter_0[1])); + (* SOFT_HLUTNM = "soft_lutpair210" *) + LUT3 #( + .INIT(8'hB8)) + \reg_pkt_len_counter[2]_i_1 + (.I0(pkt_len_counter[2]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I2(new_pkt_len[2]), + .O(sel0[2])); + (* SOFT_HLUTNM = "soft_lutpair214" *) + LUT3 #( + .INIT(8'hB8)) + \reg_pkt_len_counter[3]_i_1 + (.I0(pkt_len_counter[3]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I2(new_pkt_len[3]), + .O(sel0[3])); + LUT4 #( + .INIT(16'h1EEE)) + \reg_pkt_len_counter[3]_i_7 + (.I0(Q[2]), + .I1(Q[3]), + .I2(Q[1]), + .I3(Q[4]), + .O(S[1])); + LUT4 #( + .INIT(16'h6999)) + \reg_pkt_len_counter[3]_i_8 + (.I0(Q[3]), + .I1(Q[2]), + .I2(Q[4]), + .I3(Q[0]), + .O(S[0])); + (* SOFT_HLUTNM = "soft_lutpair208" *) + LUT3 #( + .INIT(8'hB8)) + \reg_pkt_len_counter[4]_i_1 + (.I0(pkt_len_counter[4]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I2(new_pkt_len[4]), + .O(sel0[4])); + (* SOFT_HLUTNM = "soft_lutpair212" *) + LUT3 #( + .INIT(8'hB8)) + \reg_pkt_len_counter[5]_i_1 + (.I0(pkt_len_counter[5]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I2(new_pkt_len[5]), + .O(sel0[5])); + (* SOFT_HLUTNM = "soft_lutpair209" *) + LUT3 #( + .INIT(8'hB8)) + \reg_pkt_len_counter[6]_i_1 + (.I0(pkt_len_counter[6]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I2(new_pkt_len[6]), + .O(sel0[6])); + (* SOFT_HLUTNM = "soft_lutpair213" *) + LUT3 #( + .INIT(8'hB8)) + \reg_pkt_len_counter[7]_i_1 + (.I0(pkt_len_counter[7]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I2(new_pkt_len[7]), + .O(sel0[7])); + (* SOFT_HLUTNM = "soft_lutpair207" *) + LUT3 #( + .INIT(8'hB8)) + \reg_pkt_len_counter[8]_i_1 + (.I0(pkt_len_counter[8]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I2(new_pkt_len[8]), + .O(sel0[8])); + (* SOFT_HLUTNM = "soft_lutpair212" *) + LUT3 #( + .INIT(8'hB8)) + \reg_pkt_len_counter[9]_i_1 + (.I0(pkt_len_counter[9]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I2(new_pkt_len[9]), + .O(sel0[9])); + FDRE \reg_pkt_len_counter_reg[0] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(pkt_len_counter_0[0]), + .Q(reg_pkt_len_counter[0]), + .R(cur_state_reg_0)); + FDRE \reg_pkt_len_counter_reg[10] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(sel0[10]), + .Q(reg_pkt_len_counter[10]), + .R(cur_state_reg_0)); + FDRE \reg_pkt_len_counter_reg[11] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(sel0[11]), + .Q(reg_pkt_len_counter[11]), + .R(cur_state_reg_0)); + FDRE \reg_pkt_len_counter_reg[1] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(pkt_len_counter_0[1]), + .Q(reg_pkt_len_counter[1]), + .R(cur_state_reg_0)); + FDRE \reg_pkt_len_counter_reg[2] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(sel0[2]), + .Q(reg_pkt_len_counter[2]), + .R(cur_state_reg_0)); + FDRE \reg_pkt_len_counter_reg[3] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(sel0[3]), + .Q(reg_pkt_len_counter[3]), + .R(cur_state_reg_0)); + FDRE \reg_pkt_len_counter_reg[4] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(sel0[4]), + .Q(reg_pkt_len_counter[4]), + .R(cur_state_reg_0)); + FDRE \reg_pkt_len_counter_reg[5] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(sel0[5]), + .Q(reg_pkt_len_counter[5]), + .R(cur_state_reg_0)); + FDRE \reg_pkt_len_counter_reg[6] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(sel0[6]), + .Q(reg_pkt_len_counter[6]), + .R(cur_state_reg_0)); + FDRE \reg_pkt_len_counter_reg[7] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(sel0[7]), + .Q(reg_pkt_len_counter[7]), + .R(cur_state_reg_0)); + FDRE \reg_pkt_len_counter_reg[8] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(sel0[8]), + .Q(reg_pkt_len_counter[8]), + .R(cur_state_reg_0)); + FDRE \reg_pkt_len_counter_reg[9] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(sel0[9]), + .Q(reg_pkt_len_counter[9]), + .R(cur_state_reg_0)); + LUT6 #( + .INIT(64'h0000000000000001)) + \reg_tkeep[7]_i_2 + (.I0(sel0[11]), + .I1(sel0[10]), + .I2(\reg_tkeep[7]_i_4_n_0 ), + .I3(\reg_tkeep[7]_i_5_n_0 ), + .I4(\reg_tkeep[7]_i_6_n_0 ), + .I5(\reg_tkeep[7]_i_7_n_0 ), + .O(\reg_tkeep[7]_i_7_0 )); + (* SOFT_HLUTNM = "soft_lutpair213" *) + LUT3 #( + .INIT(8'h47)) + \reg_tkeep[7]_i_3 + (.I0(pkt_len_counter[1]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I2(new_pkt_len[1]), + .O(\reg_pkt_len_counter_reg[3]_0 )); + (* SOFT_HLUTNM = "soft_lutpair207" *) + LUT5 #( + .INIT(32'hFFFACCFA)) + \reg_tkeep[7]_i_4 + (.I0(new_pkt_len[8]), + .I1(pkt_len_counter[8]), + .I2(new_pkt_len[9]), + .I3(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I4(pkt_len_counter[9]), + .O(\reg_tkeep[7]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair209" *) + LUT5 #( + .INIT(32'hFFFACCFA)) + \reg_tkeep[7]_i_5 + (.I0(new_pkt_len[6]), + .I1(pkt_len_counter[6]), + .I2(new_pkt_len[7]), + .I3(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I4(pkt_len_counter[7]), + .O(\reg_tkeep[7]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair208" *) + LUT5 #( + .INIT(32'hFFFACCFA)) + \reg_tkeep[7]_i_6 + (.I0(new_pkt_len[4]), + .I1(pkt_len_counter[4]), + .I2(new_pkt_len[5]), + .I3(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I4(pkt_len_counter[5]), + .O(\reg_tkeep[7]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair210" *) + LUT5 #( + .INIT(32'hFFFACCFA)) + \reg_tkeep[7]_i_7 + (.I0(new_pkt_len[2]), + .I1(pkt_len_counter[2]), + .I2(new_pkt_len[3]), + .I3(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I4(pkt_len_counter[3]), + .O(\reg_tkeep[7]_i_7_n_0 )); + LUT5 #( + .INIT(32'hFFFFB000)) + reg_tlast_i_1 + (.I0(\reg_pkt_len_counter_reg[3]_0 ), + .I1(pkt_len_counter_0[0]), + .I2(null_mux_sel), + .I3(\reg_tkeep[7]_i_7_0 ), + .I4(\m_axis_rx_tuser_reg[21] ), + .O(null_mux_sel_reg_0)); + LUT6 #( + .INIT(64'hB8308800FFFFFFFF)) + trn_rdst_rdy_i_3 + (.I0(pkt_len_counter[1]), + .I1(\reg_pkt_len_counter[11]_i_2_n_0 ), + .I2(new_pkt_len[1]), + .I3(reg_pkt_len_counter[0]), + .I4(new_pkt_len[0]), + .I5(null_mux_sel), + .O(\reg_pkt_len_counter_reg[0]_0 )); +endmodule + +module pcie_7x_0_pcie_7x_0_axi_basic_rx_pipeline + (E, + trn_rsrc_dsc_d, + m_axis_rx_tvalid_reg_0, + m_axis_rx_tkeep, + m_axis_rx_tlast, + null_mux_sel, + trn_in_packet, + reg_dsc_detect_reg_0, + user_reset_out_reg, + Q, + data_prev_reg_0, + data_prev_reg_1, + new_pkt_len, + m_axis_rx_tuser, + \trn_rbar_hit_prev_reg[0]_0 , + pipe_userclk2_in, + trn_rrem, + trn_rsrc_dsc, + rsrc_rdy_filtered, + trn_reof, + reg_tlast_reg_0, + trn_rsrc_dsc_prev0, + trn_rsof, + trn_recrc_err, + trn_rerrfwd, + null_mux_sel_reg_0, + trn_in_packet_reg_0, + m_axis_rx_tready, + dsc_detect, + trn_rdst_rdy_reg_0, + trn_rdst_rdy_reg_1, + \reg_tkeep_reg[7]_0 , + trn_rd, + trn_rbar_hit, + S, + D); + output [0:0]E; + output trn_rsrc_dsc_d; + output m_axis_rx_tvalid_reg_0; + output [0:0]m_axis_rx_tkeep; + output m_axis_rx_tlast; + output null_mux_sel; + output trn_in_packet; + output reg_dsc_detect_reg_0; + output user_reset_out_reg; + output [63:0]Q; + output data_prev_reg_0; + output data_prev_reg_1; + output [10:0]new_pkt_len; + output [12:0]m_axis_rx_tuser; + input \trn_rbar_hit_prev_reg[0]_0 ; + input pipe_userclk2_in; + input [0:0]trn_rrem; + input trn_rsrc_dsc; + input rsrc_rdy_filtered; + input trn_reof; + input reg_tlast_reg_0; + input trn_rsrc_dsc_prev0; + input trn_rsof; + input trn_recrc_err; + input trn_rerrfwd; + input null_mux_sel_reg_0; + input trn_in_packet_reg_0; + input m_axis_rx_tready; + input dsc_detect; + input trn_rdst_rdy_reg_0; + input trn_rdst_rdy_reg_1; + input \reg_tkeep_reg[7]_0 ; + input [63:0]trn_rd; + input [6:0]trn_rbar_hit; + input [1:0]S; + input [1:0]D; + + wire [1:0]D; + wire [0:0]E; + wire [63:0]Q; + wire [1:0]S; + wire data_hold; + wire data_prev; + wire data_prev_reg_0; + wire data_prev_reg_1; + wire dsc_detect; + wire \m_axis_rx_tdata[63]_i_1_n_0 ; + wire [0:0]m_axis_rx_tkeep; + wire m_axis_rx_tlast; + wire m_axis_rx_tready; + wire [12:0]m_axis_rx_tuser; + wire \m_axis_rx_tuser[0]_i_1_n_0 ; + wire \m_axis_rx_tuser[14]_i_1_n_0 ; + wire \m_axis_rx_tuser[14]_i_2_n_0 ; + wire \m_axis_rx_tuser[18]_i_1_n_0 ; + wire \m_axis_rx_tuser[1]_i_1_n_0 ; + wire \m_axis_rx_tuser[21]_i_1_n_0 ; + wire \m_axis_rx_tuser[2]_i_1_n_0 ; + wire \m_axis_rx_tuser[3]_i_1_n_0 ; + wire \m_axis_rx_tuser[4]_i_1_n_0 ; + wire \m_axis_rx_tuser[5]_i_1_n_0 ; + wire \m_axis_rx_tuser[6]_i_1_n_0 ; + wire \m_axis_rx_tuser[7]_i_1_n_0 ; + wire \m_axis_rx_tuser[8]_i_1_n_0 ; + wire m_axis_rx_tvalid_i_1_n_0; + wire m_axis_rx_tvalid_reg_0; + wire [10:0]new_pkt_len; + wire null_mux_sel; + wire null_mux_sel_reg_0; + wire [63:0]p_1_in; + wire [1:0]packet_overhead; + wire pipe_userclk2_in; + wire reg_dsc_detect_i_1_n_0; + wire reg_dsc_detect_reg_0; + wire \reg_pkt_len_counter[10]_i_3_n_0 ; + wire \reg_pkt_len_counter[10]_i_4_n_0 ; + wire \reg_pkt_len_counter[3]_i_5_n_0 ; + wire \reg_pkt_len_counter[3]_i_6_n_0 ; + wire \reg_pkt_len_counter[7]_i_3_n_0 ; + wire \reg_pkt_len_counter[7]_i_4_n_0 ; + wire \reg_pkt_len_counter[7]_i_5_n_0 ; + wire \reg_pkt_len_counter[7]_i_6_n_0 ; + wire \reg_pkt_len_counter_reg[10]_i_2_n_3 ; + wire \reg_pkt_len_counter_reg[3]_i_2_n_0 ; + wire \reg_pkt_len_counter_reg[3]_i_2_n_1 ; + wire \reg_pkt_len_counter_reg[3]_i_2_n_2 ; + wire \reg_pkt_len_counter_reg[3]_i_2_n_3 ; + wire \reg_pkt_len_counter_reg[7]_i_2_n_0 ; + wire \reg_pkt_len_counter_reg[7]_i_2_n_1 ; + wire \reg_pkt_len_counter_reg[7]_i_2_n_2 ; + wire \reg_pkt_len_counter_reg[7]_i_2_n_3 ; + wire [7:7]reg_tkeep; + wire \reg_tkeep_reg[7]_0 ; + wire reg_tlast_reg_0; + wire rsrc_rdy_filtered; + wire trn_in_packet; + wire trn_in_packet_reg_0; + wire [6:0]trn_rbar_hit; + wire [6:0]trn_rbar_hit_prev; + wire \trn_rbar_hit_prev_reg[0]_0 ; + wire [63:0]trn_rd; + wire [63:0]trn_rd_prev; + wire trn_rdst_rdy_i_1_n_0; + wire trn_rdst_rdy_i_2_n_0; + wire trn_rdst_rdy_reg_0; + wire trn_rdst_rdy_reg_1; + wire trn_recrc_err; + wire trn_recrc_err_prev; + wire trn_reof; + wire trn_reof_prev; + wire trn_rerrfwd; + wire trn_rerrfwd_prev; + wire [0:0]trn_rrem; + wire trn_rrem_prev; + wire trn_rsof; + wire trn_rsof_prev; + wire trn_rsrc_dsc; + wire trn_rsrc_dsc_d; + wire trn_rsrc_dsc_prev; + wire trn_rsrc_dsc_prev0; + wire trn_rsrc_rdy_prev; + wire user_reset_out_reg; + wire [3:1]\NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED ; + wire [3:2]\NLW_reg_pkt_len_counter_reg[10]_i_2_O_UNCONNECTED ; + + LUT2 #( + .INIT(4'h2)) + data_prev_i_1 + (.I0(m_axis_rx_tvalid_reg_0), + .I1(m_axis_rx_tready), + .O(data_hold)); + FDRE data_prev_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(data_hold), + .Q(data_prev), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + (* SOFT_HLUTNM = "soft_lutpair243" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[0]_i_1 + (.I0(trn_rd_prev[0]), + .I1(data_prev), + .I2(trn_rd[32]), + .O(p_1_in[0])); + (* SOFT_HLUTNM = "soft_lutpair246" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[10]_i_1 + (.I0(trn_rd_prev[10]), + .I1(data_prev), + .I2(trn_rd[42]), + .O(p_1_in[10])); + (* SOFT_HLUTNM = "soft_lutpair244" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[11]_i_1 + (.I0(trn_rd_prev[11]), + .I1(data_prev), + .I2(trn_rd[43]), + .O(p_1_in[11])); + (* SOFT_HLUTNM = "soft_lutpair241" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[12]_i_1 + (.I0(trn_rd_prev[12]), + .I1(data_prev), + .I2(trn_rd[44]), + .O(p_1_in[12])); + (* SOFT_HLUTNM = "soft_lutpair239" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[13]_i_1 + (.I0(trn_rd_prev[13]), + .I1(data_prev), + .I2(trn_rd[45]), + .O(p_1_in[13])); + (* SOFT_HLUTNM = "soft_lutpair249" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[14]_i_1 + (.I0(trn_rd_prev[14]), + .I1(data_prev), + .I2(trn_rd[46]), + .O(p_1_in[14])); + (* SOFT_HLUTNM = "soft_lutpair242" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[15]_i_1 + (.I0(trn_rd_prev[15]), + .I1(data_prev), + .I2(trn_rd[47]), + .O(p_1_in[15])); + (* SOFT_HLUTNM = "soft_lutpair238" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[16]_i_1 + (.I0(trn_rd_prev[16]), + .I1(data_prev), + .I2(trn_rd[48]), + .O(p_1_in[16])); + (* SOFT_HLUTNM = "soft_lutpair234" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[17]_i_1 + (.I0(trn_rd_prev[17]), + .I1(data_prev), + .I2(trn_rd[49]), + .O(p_1_in[17])); + (* SOFT_HLUTNM = "soft_lutpair232" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[18]_i_1 + (.I0(trn_rd_prev[18]), + .I1(data_prev), + .I2(trn_rd[50]), + .O(p_1_in[18])); + (* SOFT_HLUTNM = "soft_lutpair246" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[19]_i_1 + (.I0(trn_rd_prev[19]), + .I1(data_prev), + .I2(trn_rd[51]), + .O(p_1_in[19])); + (* SOFT_HLUTNM = "soft_lutpair249" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[1]_i_1 + (.I0(trn_rd_prev[1]), + .I1(data_prev), + .I2(trn_rd[33]), + .O(p_1_in[1])); + (* SOFT_HLUTNM = "soft_lutpair242" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[20]_i_1 + (.I0(trn_rd_prev[20]), + .I1(data_prev), + .I2(trn_rd[52]), + .O(p_1_in[20])); + (* SOFT_HLUTNM = "soft_lutpair237" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[21]_i_1 + (.I0(trn_rd_prev[21]), + .I1(data_prev), + .I2(trn_rd[53]), + .O(p_1_in[21])); + (* SOFT_HLUTNM = "soft_lutpair245" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[22]_i_1 + (.I0(trn_rd_prev[22]), + .I1(data_prev), + .I2(trn_rd[54]), + .O(p_1_in[22])); + (* SOFT_HLUTNM = "soft_lutpair247" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[23]_i_1 + (.I0(trn_rd_prev[23]), + .I1(data_prev), + .I2(trn_rd[55]), + .O(p_1_in[23])); + (* SOFT_HLUTNM = "soft_lutpair240" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[24]_i_1 + (.I0(trn_rd_prev[24]), + .I1(data_prev), + .I2(trn_rd[56]), + .O(p_1_in[24])); + (* SOFT_HLUTNM = "soft_lutpair231" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[25]_i_1 + (.I0(trn_rd_prev[25]), + .I1(data_prev), + .I2(trn_rd[57]), + .O(p_1_in[25])); + (* SOFT_HLUTNM = "soft_lutpair229" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[26]_i_1 + (.I0(trn_rd_prev[26]), + .I1(data_prev), + .I2(trn_rd[58]), + .O(p_1_in[26])); + (* SOFT_HLUTNM = "soft_lutpair232" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[27]_i_1 + (.I0(trn_rd_prev[27]), + .I1(data_prev), + .I2(trn_rd[59]), + .O(p_1_in[27])); + (* SOFT_HLUTNM = "soft_lutpair236" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[28]_i_1 + (.I0(trn_rd_prev[28]), + .I1(data_prev), + .I2(trn_rd[60]), + .O(p_1_in[28])); + (* SOFT_HLUTNM = "soft_lutpair228" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[29]_i_1 + (.I0(trn_rd_prev[29]), + .I1(data_prev), + .I2(trn_rd[61]), + .O(p_1_in[29])); + (* SOFT_HLUTNM = "soft_lutpair240" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[2]_i_1 + (.I0(trn_rd_prev[2]), + .I1(data_prev), + .I2(trn_rd[34]), + .O(p_1_in[2])); + (* SOFT_HLUTNM = "soft_lutpair227" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[30]_i_1 + (.I0(trn_rd_prev[30]), + .I1(data_prev), + .I2(trn_rd[62]), + .O(p_1_in[30])); + (* SOFT_HLUTNM = "soft_lutpair222" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[31]_i_1 + (.I0(trn_rd_prev[31]), + .I1(data_prev), + .I2(trn_rd[63]), + .O(p_1_in[31])); + (* SOFT_HLUTNM = "soft_lutpair226" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[32]_i_1 + (.I0(trn_rd_prev[32]), + .I1(data_prev), + .I2(trn_rd[0]), + .O(p_1_in[32])); + (* SOFT_HLUTNM = "soft_lutpair218" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[33]_i_1 + (.I0(trn_rd_prev[33]), + .I1(data_prev), + .I2(trn_rd[1]), + .O(p_1_in[33])); + (* SOFT_HLUTNM = "soft_lutpair225" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[34]_i_1 + (.I0(trn_rd_prev[34]), + .I1(data_prev), + .I2(trn_rd[2]), + .O(p_1_in[34])); + (* SOFT_HLUTNM = "soft_lutpair219" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[35]_i_1 + (.I0(trn_rd_prev[35]), + .I1(data_prev), + .I2(trn_rd[3]), + .O(p_1_in[35])); + (* SOFT_HLUTNM = "soft_lutpair227" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[36]_i_1 + (.I0(trn_rd_prev[36]), + .I1(data_prev), + .I2(trn_rd[4]), + .O(p_1_in[36])); + (* SOFT_HLUTNM = "soft_lutpair218" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[37]_i_1 + (.I0(trn_rd_prev[37]), + .I1(data_prev), + .I2(trn_rd[5]), + .O(p_1_in[37])); + (* SOFT_HLUTNM = "soft_lutpair225" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[38]_i_1 + (.I0(trn_rd_prev[38]), + .I1(data_prev), + .I2(trn_rd[6]), + .O(p_1_in[38])); + (* SOFT_HLUTNM = "soft_lutpair221" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[39]_i_1 + (.I0(trn_rd_prev[39]), + .I1(data_prev), + .I2(trn_rd[7]), + .O(p_1_in[39])); + (* SOFT_HLUTNM = "soft_lutpair248" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[3]_i_1 + (.I0(trn_rd_prev[3]), + .I1(data_prev), + .I2(trn_rd[35]), + .O(p_1_in[3])); + (* SOFT_HLUTNM = "soft_lutpair223" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[40]_i_1 + (.I0(trn_rd_prev[40]), + .I1(data_prev), + .I2(trn_rd[8]), + .O(p_1_in[40])); + (* SOFT_HLUTNM = "soft_lutpair222" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[41]_i_1 + (.I0(trn_rd_prev[41]), + .I1(data_prev), + .I2(trn_rd[9]), + .O(p_1_in[41])); + (* SOFT_HLUTNM = "soft_lutpair221" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[42]_i_1 + (.I0(trn_rd_prev[42]), + .I1(data_prev), + .I2(trn_rd[10]), + .O(p_1_in[42])); + (* SOFT_HLUTNM = "soft_lutpair223" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[43]_i_1 + (.I0(trn_rd_prev[43]), + .I1(data_prev), + .I2(trn_rd[11]), + .O(p_1_in[43])); + (* SOFT_HLUTNM = "soft_lutpair229" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[44]_i_1 + (.I0(trn_rd_prev[44]), + .I1(data_prev), + .I2(trn_rd[12]), + .O(p_1_in[44])); + (* SOFT_HLUTNM = "soft_lutpair228" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[45]_i_1 + (.I0(trn_rd_prev[45]), + .I1(data_prev), + .I2(trn_rd[13]), + .O(p_1_in[45])); + (* SOFT_HLUTNM = "soft_lutpair220" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[46]_i_1 + (.I0(trn_rd_prev[46]), + .I1(data_prev), + .I2(trn_rd[14]), + .O(p_1_in[46])); + (* SOFT_HLUTNM = "soft_lutpair231" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[47]_i_1 + (.I0(trn_rd_prev[47]), + .I1(data_prev), + .I2(trn_rd[15]), + .O(p_1_in[47])); + (* SOFT_HLUTNM = "soft_lutpair220" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[48]_i_1 + (.I0(trn_rd_prev[48]), + .I1(data_prev), + .I2(trn_rd[16]), + .O(p_1_in[48])); + (* SOFT_HLUTNM = "soft_lutpair235" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[49]_i_1 + (.I0(trn_rd_prev[49]), + .I1(data_prev), + .I2(trn_rd[17]), + .O(p_1_in[49])); + (* SOFT_HLUTNM = "soft_lutpair248" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[4]_i_1 + (.I0(trn_rd_prev[4]), + .I1(data_prev), + .I2(trn_rd[36]), + .O(p_1_in[4])); + (* SOFT_HLUTNM = "soft_lutpair233" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[50]_i_1 + (.I0(trn_rd_prev[50]), + .I1(data_prev), + .I2(trn_rd[18]), + .O(p_1_in[50])); + (* SOFT_HLUTNM = "soft_lutpair230" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[51]_i_1 + (.I0(trn_rd_prev[51]), + .I1(data_prev), + .I2(trn_rd[19]), + .O(p_1_in[51])); + (* SOFT_HLUTNM = "soft_lutpair219" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[52]_i_1 + (.I0(trn_rd_prev[52]), + .I1(data_prev), + .I2(trn_rd[20]), + .O(p_1_in[52])); + (* SOFT_HLUTNM = "soft_lutpair226" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[53]_i_1 + (.I0(trn_rd_prev[53]), + .I1(data_prev), + .I2(trn_rd[21]), + .O(p_1_in[53])); + (* SOFT_HLUTNM = "soft_lutpair224" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[54]_i_1 + (.I0(trn_rd_prev[54]), + .I1(data_prev), + .I2(trn_rd[22]), + .O(p_1_in[54])); + (* SOFT_HLUTNM = "soft_lutpair224" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[55]_i_1 + (.I0(trn_rd_prev[55]), + .I1(data_prev), + .I2(trn_rd[23]), + .O(p_1_in[55])); + (* SOFT_HLUTNM = "soft_lutpair239" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[56]_i_1 + (.I0(trn_rd_prev[56]), + .I1(data_prev), + .I2(trn_rd[24]), + .O(p_1_in[56])); + (* SOFT_HLUTNM = "soft_lutpair236" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[57]_i_1 + (.I0(trn_rd_prev[57]), + .I1(data_prev), + .I2(trn_rd[25]), + .O(p_1_in[57])); + (* SOFT_HLUTNM = "soft_lutpair238" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[58]_i_1 + (.I0(trn_rd_prev[58]), + .I1(data_prev), + .I2(trn_rd[26]), + .O(p_1_in[58])); + (* SOFT_HLUTNM = "soft_lutpair230" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[59]_i_1 + (.I0(trn_rd_prev[59]), + .I1(data_prev), + .I2(trn_rd[27]), + .O(p_1_in[59])); + (* SOFT_HLUTNM = "soft_lutpair237" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[5]_i_1 + (.I0(trn_rd_prev[5]), + .I1(data_prev), + .I2(trn_rd[37]), + .O(p_1_in[5])); + (* SOFT_HLUTNM = "soft_lutpair233" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[60]_i_1 + (.I0(trn_rd_prev[60]), + .I1(data_prev), + .I2(trn_rd[28]), + .O(p_1_in[60])); + (* SOFT_HLUTNM = "soft_lutpair243" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[61]_i_1 + (.I0(trn_rd_prev[61]), + .I1(data_prev), + .I2(trn_rd[29]), + .O(p_1_in[61])); + (* SOFT_HLUTNM = "soft_lutpair234" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[62]_i_1 + (.I0(trn_rd_prev[62]), + .I1(data_prev), + .I2(trn_rd[30]), + .O(p_1_in[62])); + LUT2 #( + .INIT(4'hB)) + \m_axis_rx_tdata[63]_i_1 + (.I0(m_axis_rx_tready), + .I1(m_axis_rx_tvalid_reg_0), + .O(\m_axis_rx_tdata[63]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair247" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[63]_i_2 + (.I0(trn_rd_prev[63]), + .I1(data_prev), + .I2(trn_rd[31]), + .O(p_1_in[63])); + (* SOFT_HLUTNM = "soft_lutpair235" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[6]_i_1 + (.I0(trn_rd_prev[6]), + .I1(data_prev), + .I2(trn_rd[38]), + .O(p_1_in[6])); + (* SOFT_HLUTNM = "soft_lutpair245" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[7]_i_1 + (.I0(trn_rd_prev[7]), + .I1(data_prev), + .I2(trn_rd[39]), + .O(p_1_in[7])); + (* SOFT_HLUTNM = "soft_lutpair244" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[8]_i_1 + (.I0(trn_rd_prev[8]), + .I1(data_prev), + .I2(trn_rd[40]), + .O(p_1_in[8])); + (* SOFT_HLUTNM = "soft_lutpair241" *) + LUT3 #( + .INIT(8'hB8)) + \m_axis_rx_tdata[9]_i_1 + (.I0(trn_rd_prev[9]), + .I1(data_prev), + .I2(trn_rd[41]), + .O(p_1_in[9])); + FDRE \m_axis_rx_tdata_reg[0] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[0]), + .Q(Q[0]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[10] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[10]), + .Q(Q[10]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[11] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[11]), + .Q(Q[11]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[12] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[12]), + .Q(Q[12]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[13] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[13]), + .Q(Q[13]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[14] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[14]), + .Q(Q[14]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[15] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[15]), + .Q(Q[15]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[16] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[16]), + .Q(Q[16]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[17] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[17]), + .Q(Q[17]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[18] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[18]), + .Q(Q[18]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[19] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[19]), + .Q(Q[19]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[1] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[1]), + .Q(Q[1]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[20] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[20]), + .Q(Q[20]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[21] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[21]), + .Q(Q[21]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[22] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[22]), + .Q(Q[22]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[23] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[23]), + .Q(Q[23]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[24] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[24]), + .Q(Q[24]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[25] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[25]), + .Q(Q[25]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[26] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[26]), + .Q(Q[26]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[27] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[27]), + .Q(Q[27]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[28] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[28]), + .Q(Q[28]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[29] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[29]), + .Q(Q[29]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[2] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[2]), + .Q(Q[2]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[30] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[30]), + .Q(Q[30]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[31] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[31]), + .Q(Q[31]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[32] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[32]), + .Q(Q[32]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[33] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[33]), + .Q(Q[33]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[34] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[34]), + .Q(Q[34]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[35] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[35]), + .Q(Q[35]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[36] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[36]), + .Q(Q[36]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[37] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[37]), + .Q(Q[37]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[38] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[38]), + .Q(Q[38]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[39] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[39]), + .Q(Q[39]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[3] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[3]), + .Q(Q[3]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[40] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[40]), + .Q(Q[40]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[41] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[41]), + .Q(Q[41]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[42] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[42]), + .Q(Q[42]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[43] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[43]), + .Q(Q[43]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[44] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[44]), + .Q(Q[44]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[45] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[45]), + .Q(Q[45]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[46] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[46]), + .Q(Q[46]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[47] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[47]), + .Q(Q[47]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[48] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[48]), + .Q(Q[48]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[49] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[49]), + .Q(Q[49]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[4] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[4]), + .Q(Q[4]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[50] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[50]), + .Q(Q[50]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[51] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[51]), + .Q(Q[51]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[52] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[52]), + .Q(Q[52]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[53] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[53]), + .Q(Q[53]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[54] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[54]), + .Q(Q[54]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[55] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[55]), + .Q(Q[55]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[56] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[56]), + .Q(Q[56]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[57] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[57]), + .Q(Q[57]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[58] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[58]), + .Q(Q[58]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[59] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[59]), + .Q(Q[59]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[5] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[5]), + .Q(Q[5]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[60] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[60]), + .Q(Q[60]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[61] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[61]), + .Q(Q[61]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[62] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[62]), + .Q(Q[62]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[63] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[63]), + .Q(Q[63]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[6] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[6]), + .Q(Q[6]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[7] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[7]), + .Q(Q[7]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[8] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[8]), + .Q(Q[8]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \m_axis_rx_tdata_reg[9] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(p_1_in[9]), + .Q(Q[9]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + LUT5 #( + .INIT(32'h000000E2)) + \m_axis_rx_tuser[0]_i_1 + (.I0(trn_recrc_err), + .I1(data_prev), + .I2(trn_recrc_err_prev), + .I3(\trn_rbar_hit_prev_reg[0]_0 ), + .I4(null_mux_sel), + .O(\m_axis_rx_tuser[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000004F40404)) + \m_axis_rx_tuser[14]_i_1 + (.I0(trn_rsrc_dsc), + .I1(trn_rsof), + .I2(data_prev), + .I3(trn_rsrc_dsc_prev), + .I4(trn_rsof_prev), + .I5(\m_axis_rx_tuser[14]_i_2_n_0 ), + .O(\m_axis_rx_tuser[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair215" *) + LUT2 #( + .INIT(4'hE)) + \m_axis_rx_tuser[14]_i_2 + (.I0(\trn_rbar_hit_prev_reg[0]_0 ), + .I1(null_mux_sel), + .O(\m_axis_rx_tuser[14]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair216" *) + LUT1 #( + .INIT(2'h1)) + \m_axis_rx_tuser[18]_i_1 + (.I0(\trn_rbar_hit_prev_reg[0]_0 ), + .O(\m_axis_rx_tuser[18]_i_1_n_0 )); + LUT4 #( + .INIT(16'h00E2)) + \m_axis_rx_tuser[19]_i_2 + (.I0(trn_rrem), + .I1(data_prev), + .I2(trn_rrem_prev), + .I3(null_mux_sel), + .O(data_prev_reg_1)); + LUT5 #( + .INIT(32'h000000B8)) + \m_axis_rx_tuser[1]_i_1 + (.I0(trn_rerrfwd_prev), + .I1(data_prev), + .I2(trn_rerrfwd), + .I3(\trn_rbar_hit_prev_reg[0]_0 ), + .I4(null_mux_sel), + .O(\m_axis_rx_tuser[1]_i_1_n_0 )); + LUT3 #( + .INIT(8'hEF)) + \m_axis_rx_tuser[21]_i_1 + (.I0(\trn_rbar_hit_prev_reg[0]_0 ), + .I1(m_axis_rx_tready), + .I2(m_axis_rx_tvalid_reg_0), + .O(\m_axis_rx_tuser[21]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair216" *) + LUT5 #( + .INIT(32'h000000B8)) + \m_axis_rx_tuser[2]_i_1 + (.I0(trn_rbar_hit_prev[0]), + .I1(data_prev), + .I2(trn_rbar_hit[0]), + .I3(\trn_rbar_hit_prev_reg[0]_0 ), + .I4(null_mux_sel), + .O(\m_axis_rx_tuser[2]_i_1_n_0 )); + LUT5 #( + .INIT(32'h000000E2)) + \m_axis_rx_tuser[3]_i_1 + (.I0(trn_rbar_hit[1]), + .I1(data_prev), + .I2(trn_rbar_hit_prev[1]), + .I3(\trn_rbar_hit_prev_reg[0]_0 ), + .I4(null_mux_sel), + .O(\m_axis_rx_tuser[3]_i_1_n_0 )); + LUT5 #( + .INIT(32'h000000E2)) + \m_axis_rx_tuser[4]_i_1 + (.I0(trn_rbar_hit[2]), + .I1(data_prev), + .I2(trn_rbar_hit_prev[2]), + .I3(\trn_rbar_hit_prev_reg[0]_0 ), + .I4(null_mux_sel), + .O(\m_axis_rx_tuser[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'h000000B8)) + \m_axis_rx_tuser[5]_i_1 + (.I0(trn_rbar_hit_prev[3]), + .I1(data_prev), + .I2(trn_rbar_hit[3]), + .I3(\trn_rbar_hit_prev_reg[0]_0 ), + .I4(null_mux_sel), + .O(\m_axis_rx_tuser[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'h000000B8)) + \m_axis_rx_tuser[6]_i_1 + (.I0(trn_rbar_hit_prev[4]), + .I1(data_prev), + .I2(trn_rbar_hit[4]), + .I3(\trn_rbar_hit_prev_reg[0]_0 ), + .I4(null_mux_sel), + .O(\m_axis_rx_tuser[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair215" *) + LUT5 #( + .INIT(32'h000000E2)) + \m_axis_rx_tuser[7]_i_1 + (.I0(trn_rbar_hit[5]), + .I1(data_prev), + .I2(trn_rbar_hit_prev[5]), + .I3(\trn_rbar_hit_prev_reg[0]_0 ), + .I4(null_mux_sel), + .O(\m_axis_rx_tuser[7]_i_1_n_0 )); + LUT5 #( + .INIT(32'h000000E2)) + \m_axis_rx_tuser[8]_i_1 + (.I0(trn_rbar_hit[6]), + .I1(data_prev), + .I2(trn_rbar_hit_prev[6]), + .I3(\trn_rbar_hit_prev_reg[0]_0 ), + .I4(null_mux_sel), + .O(\m_axis_rx_tuser[8]_i_1_n_0 )); + FDRE \m_axis_rx_tuser_reg[0] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tuser[21]_i_1_n_0 ), + .D(\m_axis_rx_tuser[0]_i_1_n_0 ), + .Q(m_axis_rx_tuser[0]), + .R(1'b0)); + FDRE \m_axis_rx_tuser_reg[14] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tuser[21]_i_1_n_0 ), + .D(\m_axis_rx_tuser[14]_i_1_n_0 ), + .Q(m_axis_rx_tuser[9]), + .R(1'b0)); + FDRE \m_axis_rx_tuser_reg[18] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tuser[21]_i_1_n_0 ), + .D(\m_axis_rx_tuser[18]_i_1_n_0 ), + .Q(m_axis_rx_tuser[10]), + .R(1'b0)); + FDRE \m_axis_rx_tuser_reg[19] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tuser[21]_i_1_n_0 ), + .D(D[0]), + .Q(m_axis_rx_tuser[11]), + .R(1'b0)); + FDRE \m_axis_rx_tuser_reg[1] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tuser[21]_i_1_n_0 ), + .D(\m_axis_rx_tuser[1]_i_1_n_0 ), + .Q(m_axis_rx_tuser[1]), + .R(1'b0)); + FDRE \m_axis_rx_tuser_reg[21] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tuser[21]_i_1_n_0 ), + .D(D[1]), + .Q(m_axis_rx_tuser[12]), + .R(1'b0)); + FDRE \m_axis_rx_tuser_reg[2] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tuser[21]_i_1_n_0 ), + .D(\m_axis_rx_tuser[2]_i_1_n_0 ), + .Q(m_axis_rx_tuser[2]), + .R(1'b0)); + FDRE \m_axis_rx_tuser_reg[3] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tuser[21]_i_1_n_0 ), + .D(\m_axis_rx_tuser[3]_i_1_n_0 ), + .Q(m_axis_rx_tuser[3]), + .R(1'b0)); + FDRE \m_axis_rx_tuser_reg[4] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tuser[21]_i_1_n_0 ), + .D(\m_axis_rx_tuser[4]_i_1_n_0 ), + .Q(m_axis_rx_tuser[4]), + .R(1'b0)); + FDRE \m_axis_rx_tuser_reg[5] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tuser[21]_i_1_n_0 ), + .D(\m_axis_rx_tuser[5]_i_1_n_0 ), + .Q(m_axis_rx_tuser[5]), + .R(1'b0)); + FDRE \m_axis_rx_tuser_reg[6] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tuser[21]_i_1_n_0 ), + .D(\m_axis_rx_tuser[6]_i_1_n_0 ), + .Q(m_axis_rx_tuser[6]), + .R(1'b0)); + FDRE \m_axis_rx_tuser_reg[7] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tuser[21]_i_1_n_0 ), + .D(\m_axis_rx_tuser[7]_i_1_n_0 ), + .Q(m_axis_rx_tuser[7]), + .R(1'b0)); + FDRE \m_axis_rx_tuser_reg[8] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tuser[21]_i_1_n_0 ), + .D(\m_axis_rx_tuser[8]_i_1_n_0 ), + .Q(m_axis_rx_tuser[8]), + .R(1'b0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFECE)) + m_axis_rx_tvalid_i_1 + (.I0(rsrc_rdy_filtered), + .I1(null_mux_sel), + .I2(data_prev), + .I3(trn_rsrc_rdy_prev), + .I4(reg_dsc_detect_reg_0), + .I5(dsc_detect), + .O(m_axis_rx_tvalid_i_1_n_0)); + FDRE m_axis_rx_tvalid_reg + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(m_axis_rx_tvalid_i_1_n_0), + .Q(m_axis_rx_tvalid_reg_0), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + LUT6 #( + .INIT(64'hABAAABAAABAABBBB)) + null_mux_sel_i_2 + (.I0(\trn_rbar_hit_prev_reg[0]_0 ), + .I1(null_mux_sel), + .I2(m_axis_rx_tready), + .I3(m_axis_rx_tvalid_reg_0), + .I4(dsc_detect), + .I5(reg_dsc_detect_reg_0), + .O(user_reset_out_reg)); + FDRE null_mux_sel_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(null_mux_sel_reg_0), + .Q(null_mux_sel), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair217" *) + LUT3 #( + .INIT(8'hDC)) + reg_dsc_detect_i_1 + (.I0(null_mux_sel), + .I1(dsc_detect), + .I2(reg_dsc_detect_reg_0), + .O(reg_dsc_detect_i_1_n_0)); + FDRE reg_dsc_detect_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(reg_dsc_detect_i_1_n_0), + .Q(reg_dsc_detect_reg_0), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + LUT2 #( + .INIT(4'h8)) + \reg_pkt_len_counter[10]_i_3 + (.I0(Q[30]), + .I1(Q[9]), + .O(\reg_pkt_len_counter[10]_i_3_n_0 )); + LUT2 #( + .INIT(4'h8)) + \reg_pkt_len_counter[10]_i_4 + (.I0(Q[30]), + .I1(Q[8]), + .O(\reg_pkt_len_counter[10]_i_4_n_0 )); + LUT2 #( + .INIT(4'hE)) + \reg_pkt_len_counter[3]_i_3 + (.I0(Q[29]), + .I1(Q[15]), + .O(packet_overhead[1])); + LUT2 #( + .INIT(4'h9)) + \reg_pkt_len_counter[3]_i_4 + (.I0(Q[15]), + .I1(Q[29]), + .O(packet_overhead[0])); + LUT2 #( + .INIT(4'h8)) + \reg_pkt_len_counter[3]_i_5 + (.I0(Q[30]), + .I1(Q[3]), + .O(\reg_pkt_len_counter[3]_i_5_n_0 )); + LUT2 #( + .INIT(4'h8)) + \reg_pkt_len_counter[3]_i_6 + (.I0(Q[30]), + .I1(Q[2]), + .O(\reg_pkt_len_counter[3]_i_6_n_0 )); + LUT2 #( + .INIT(4'h8)) + \reg_pkt_len_counter[7]_i_3 + (.I0(Q[30]), + .I1(Q[7]), + .O(\reg_pkt_len_counter[7]_i_3_n_0 )); + LUT2 #( + .INIT(4'h8)) + \reg_pkt_len_counter[7]_i_4 + (.I0(Q[30]), + .I1(Q[6]), + .O(\reg_pkt_len_counter[7]_i_4_n_0 )); + LUT2 #( + .INIT(4'h8)) + \reg_pkt_len_counter[7]_i_5 + (.I0(Q[30]), + .I1(Q[5]), + .O(\reg_pkt_len_counter[7]_i_5_n_0 )); + LUT2 #( + .INIT(4'h8)) + \reg_pkt_len_counter[7]_i_6 + (.I0(Q[30]), + .I1(Q[4]), + .O(\reg_pkt_len_counter[7]_i_6_n_0 )); + CARRY4 \reg_pkt_len_counter_reg[10]_i_2 + (.CI(\reg_pkt_len_counter_reg[7]_i_2_n_0 ), + .CO({\NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED [3],new_pkt_len[10],\NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED [1],\reg_pkt_len_counter_reg[10]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_reg_pkt_len_counter_reg[10]_i_2_O_UNCONNECTED [3:2],new_pkt_len[9:8]}), + .S({1'b0,1'b1,\reg_pkt_len_counter[10]_i_3_n_0 ,\reg_pkt_len_counter[10]_i_4_n_0 })); + CARRY4 \reg_pkt_len_counter_reg[3]_i_2 + (.CI(1'b0), + .CO({\reg_pkt_len_counter_reg[3]_i_2_n_0 ,\reg_pkt_len_counter_reg[3]_i_2_n_1 ,\reg_pkt_len_counter_reg[3]_i_2_n_2 ,\reg_pkt_len_counter_reg[3]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,packet_overhead}), + .O(new_pkt_len[3:0]), + .S({\reg_pkt_len_counter[3]_i_5_n_0 ,\reg_pkt_len_counter[3]_i_6_n_0 ,S})); + CARRY4 \reg_pkt_len_counter_reg[7]_i_2 + (.CI(\reg_pkt_len_counter_reg[3]_i_2_n_0 ), + .CO({\reg_pkt_len_counter_reg[7]_i_2_n_0 ,\reg_pkt_len_counter_reg[7]_i_2_n_1 ,\reg_pkt_len_counter_reg[7]_i_2_n_2 ,\reg_pkt_len_counter_reg[7]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(new_pkt_len[7:4]), + .S({\reg_pkt_len_counter[7]_i_3_n_0 ,\reg_pkt_len_counter[7]_i_4_n_0 ,\reg_pkt_len_counter[7]_i_5_n_0 ,\reg_pkt_len_counter[7]_i_6_n_0 })); + LUT6 #( + .INIT(64'h7F7F7F7070707F70)) + \reg_tkeep[7]_i_1 + (.I0(trn_rdst_rdy_reg_0), + .I1(\reg_tkeep_reg[7]_0 ), + .I2(null_mux_sel), + .I3(trn_rrem), + .I4(data_prev), + .I5(trn_rrem_prev), + .O(reg_tkeep)); + FDSE \reg_tkeep_reg[7] + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(reg_tkeep), + .Q(m_axis_rx_tkeep), + .S(\trn_rbar_hit_prev_reg[0]_0 )); + LUT4 #( + .INIT(16'h00E2)) + reg_tlast_i_2 + (.I0(trn_reof), + .I1(data_prev), + .I2(trn_reof_prev), + .I3(null_mux_sel), + .O(data_prev_reg_0)); + FDRE reg_tlast_reg + (.C(pipe_userclk2_in), + .CE(\m_axis_rx_tdata[63]_i_1_n_0 ), + .D(reg_tlast_reg_0), + .Q(m_axis_rx_tlast), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE trn_in_packet_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(trn_in_packet_reg_0), + .Q(trn_in_packet), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rbar_hit_prev_reg[0] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rbar_hit[0]), + .Q(trn_rbar_hit_prev[0]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rbar_hit_prev_reg[1] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rbar_hit[1]), + .Q(trn_rbar_hit_prev[1]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rbar_hit_prev_reg[2] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rbar_hit[2]), + .Q(trn_rbar_hit_prev[2]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rbar_hit_prev_reg[3] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rbar_hit[3]), + .Q(trn_rbar_hit_prev[3]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rbar_hit_prev_reg[4] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rbar_hit[4]), + .Q(trn_rbar_hit_prev[4]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rbar_hit_prev_reg[5] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rbar_hit[5]), + .Q(trn_rbar_hit_prev[5]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rbar_hit_prev_reg[6] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rbar_hit[6]), + .Q(trn_rbar_hit_prev[6]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[0] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[32]), + .Q(trn_rd_prev[0]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[10] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[42]), + .Q(trn_rd_prev[10]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[11] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[43]), + .Q(trn_rd_prev[11]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[12] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[44]), + .Q(trn_rd_prev[12]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[13] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[45]), + .Q(trn_rd_prev[13]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[14] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[46]), + .Q(trn_rd_prev[14]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[15] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[47]), + .Q(trn_rd_prev[15]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[16] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[48]), + .Q(trn_rd_prev[16]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[17] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[49]), + .Q(trn_rd_prev[17]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[18] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[50]), + .Q(trn_rd_prev[18]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[19] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[51]), + .Q(trn_rd_prev[19]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[1] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[33]), + .Q(trn_rd_prev[1]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[20] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[52]), + .Q(trn_rd_prev[20]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[21] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[53]), + .Q(trn_rd_prev[21]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[22] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[54]), + .Q(trn_rd_prev[22]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[23] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[55]), + .Q(trn_rd_prev[23]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[24] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[56]), + .Q(trn_rd_prev[24]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[25] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[57]), + .Q(trn_rd_prev[25]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[26] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[58]), + .Q(trn_rd_prev[26]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[27] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[59]), + .Q(trn_rd_prev[27]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[28] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[60]), + .Q(trn_rd_prev[28]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[29] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[61]), + .Q(trn_rd_prev[29]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[2] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[34]), + .Q(trn_rd_prev[2]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[30] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[62]), + .Q(trn_rd_prev[30]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[31] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[63]), + .Q(trn_rd_prev[31]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[32] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[0]), + .Q(trn_rd_prev[32]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[33] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[1]), + .Q(trn_rd_prev[33]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[34] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[2]), + .Q(trn_rd_prev[34]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[35] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[3]), + .Q(trn_rd_prev[35]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[36] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[4]), + .Q(trn_rd_prev[36]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[37] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[5]), + .Q(trn_rd_prev[37]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[38] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[6]), + .Q(trn_rd_prev[38]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[39] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[7]), + .Q(trn_rd_prev[39]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[3] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[35]), + .Q(trn_rd_prev[3]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[40] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[8]), + .Q(trn_rd_prev[40]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[41] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[9]), + .Q(trn_rd_prev[41]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[42] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[10]), + .Q(trn_rd_prev[42]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[43] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[11]), + .Q(trn_rd_prev[43]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[44] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[12]), + .Q(trn_rd_prev[44]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[45] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[13]), + .Q(trn_rd_prev[45]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[46] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[14]), + .Q(trn_rd_prev[46]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[47] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[15]), + .Q(trn_rd_prev[47]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[48] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[16]), + .Q(trn_rd_prev[48]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[49] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[17]), + .Q(trn_rd_prev[49]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[4] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[36]), + .Q(trn_rd_prev[4]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[50] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[18]), + .Q(trn_rd_prev[50]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[51] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[19]), + .Q(trn_rd_prev[51]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[52] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[20]), + .Q(trn_rd_prev[52]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[53] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[21]), + .Q(trn_rd_prev[53]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[54] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[22]), + .Q(trn_rd_prev[54]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[55] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[23]), + .Q(trn_rd_prev[55]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[56] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[24]), + .Q(trn_rd_prev[56]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[57] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[25]), + .Q(trn_rd_prev[57]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[58] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[26]), + .Q(trn_rd_prev[58]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[59] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[27]), + .Q(trn_rd_prev[59]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[5] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[37]), + .Q(trn_rd_prev[5]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[60] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[28]), + .Q(trn_rd_prev[60]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[61] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[29]), + .Q(trn_rd_prev[61]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[62] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[30]), + .Q(trn_rd_prev[62]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[63] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[31]), + .Q(trn_rd_prev[63]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[6] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[38]), + .Q(trn_rd_prev[6]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[7] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[39]), + .Q(trn_rd_prev[7]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[8] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[40]), + .Q(trn_rd_prev[8]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rd_prev_reg[9] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rd[41]), + .Q(trn_rd_prev[9]), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + LUT6 #( + .INIT(64'h3030FF3050505050)) + trn_rdst_rdy_i_1 + (.I0(m_axis_rx_tvalid_reg_0), + .I1(null_mux_sel), + .I2(trn_rdst_rdy_i_2_n_0), + .I3(trn_rdst_rdy_reg_0), + .I4(trn_rdst_rdy_reg_1), + .I5(m_axis_rx_tready), + .O(trn_rdst_rdy_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair217" *) + LUT2 #( + .INIT(4'h1)) + trn_rdst_rdy_i_2 + (.I0(reg_dsc_detect_reg_0), + .I1(dsc_detect), + .O(trn_rdst_rdy_i_2_n_0)); + FDRE trn_rdst_rdy_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(trn_rdst_rdy_i_1_n_0), + .Q(E), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE trn_recrc_err_prev_reg + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_recrc_err), + .Q(trn_recrc_err_prev), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE trn_reof_prev_reg + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_reof), + .Q(trn_reof_prev), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE trn_rerrfwd_prev_reg + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rerrfwd), + .Q(trn_rerrfwd_prev), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE \trn_rrem_prev_reg[0] + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rrem), + .Q(trn_rrem_prev), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE trn_rsof_prev_reg + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rsof), + .Q(trn_rsof_prev), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE trn_rsrc_dsc_d_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(trn_rsrc_dsc), + .Q(trn_rsrc_dsc_d), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE trn_rsrc_dsc_prev_reg + (.C(pipe_userclk2_in), + .CE(E), + .D(trn_rsrc_dsc_prev0), + .Q(trn_rsrc_dsc_prev), + .R(\trn_rbar_hit_prev_reg[0]_0 )); + FDRE trn_rsrc_rdy_prev_reg + (.C(pipe_userclk2_in), + .CE(E), + .D(rsrc_rdy_filtered), + .Q(trn_rsrc_rdy_prev), + .R(\trn_rbar_hit_prev_reg[0]_0 )); +endmodule + +module pcie_7x_0_pcie_7x_0_axi_basic_top + (E, + trn_rsrc_dsc_d, + m_axis_rx_tvalid_reg, + m_axis_rx_tkeep, + m_axis_rx_tlast, + reg_tcfg_gnt, + tready_thrtl_reg, + trn_teof, + trn_tsrc_rdy, + trn_trem, + trn_in_packet, + reg_dsc_detect, + ppm_L1_thrtl, + lnk_up_thrtl, + m_axis_rx_tuser, + ppm_L1_trig, + cfg_pm_turnoff_ok_n, + trn_tcfg_gnt, + trn_tsof, + Q, + \throttle_ctl_pipeline.reg_tdata_reg[63] , + \throttle_ctl_pipeline.reg_tuser_reg[3] , + \throttle_ctl_pipeline.reg_tkeep_reg[7] , + pipe_userclk2_in, + trn_rrem, + trn_rsrc_dsc, + rsrc_rdy_filtered, + trn_reof, + trn_rsrc_dsc_prev0, + trn_rsof, + trn_recrc_err, + trn_rerrfwd, + tx_cfg_gnt, + trn_tcfg_req, + trn_tdst_rdy, + tbuf_av_min_trig, + cfg_turnoff_ok, + s_axis_tx_tlast, + s_axis_tx_tvalid, + s_axis_tx_tkeep, + trn_in_packet_reg, + ppm_L1_thrtl_reg, + lnk_up_thrtl_reg, + m_axis_rx_tready, + dsc_detect, + out, + tcfg_req_trig, + tready_thrtl_i_5, + cfg_pcie_link_state, + s_axis_tx_tdata, + s_axis_tx_tuser, + trn_tbuf_av, + trn_rd, + trn_rbar_hit, + cfg_to_turnoff); + output [0:0]E; + output trn_rsrc_dsc_d; + output m_axis_rx_tvalid_reg; + output [0:0]m_axis_rx_tkeep; + output m_axis_rx_tlast; + output reg_tcfg_gnt; + output tready_thrtl_reg; + output trn_teof; + output trn_tsrc_rdy; + output [0:0]trn_trem; + output trn_in_packet; + output reg_dsc_detect; + output ppm_L1_thrtl; + output lnk_up_thrtl; + output [12:0]m_axis_rx_tuser; + output ppm_L1_trig; + output cfg_pm_turnoff_ok_n; + output trn_tcfg_gnt; + output trn_tsof; + output [63:0]Q; + output [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63] ; + output [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3] ; + input \throttle_ctl_pipeline.reg_tkeep_reg[7] ; + input pipe_userclk2_in; + input [0:0]trn_rrem; + input trn_rsrc_dsc; + input rsrc_rdy_filtered; + input trn_reof; + input trn_rsrc_dsc_prev0; + input trn_rsof; + input trn_recrc_err; + input trn_rerrfwd; + input tx_cfg_gnt; + input trn_tcfg_req; + input trn_tdst_rdy; + input tbuf_av_min_trig; + input cfg_turnoff_ok; + input s_axis_tx_tlast; + input s_axis_tx_tvalid; + input [0:0]s_axis_tx_tkeep; + input trn_in_packet_reg; + input ppm_L1_thrtl_reg; + input lnk_up_thrtl_reg; + input m_axis_rx_tready; + input dsc_detect; + input out; + input tcfg_req_trig; + input tready_thrtl_i_5; + input [2:0]cfg_pcie_link_state; + input [63:0]s_axis_tx_tdata; + input [3:0]s_axis_tx_tuser; + input [5:0]trn_tbuf_av; + input [63:0]trn_rd; + input [6:0]trn_rbar_hit; + input cfg_to_turnoff; + + wire [0:0]E; + wire [63:0]Q; + wire [2:0]cfg_pcie_link_state; + wire cfg_pm_turnoff_ok_n; + wire cfg_to_turnoff; + wire cfg_turnoff_ok; + wire dsc_detect; + wire lnk_up_thrtl; + wire lnk_up_thrtl_reg; + wire [0:0]m_axis_rx_tkeep; + wire m_axis_rx_tlast; + wire m_axis_rx_tready; + wire [12:0]m_axis_rx_tuser; + wire m_axis_rx_tvalid_reg; + wire out; + wire pipe_userclk2_in; + wire ppm_L1_thrtl; + wire ppm_L1_thrtl_reg; + wire ppm_L1_trig; + wire reg_dsc_detect; + wire reg_tcfg_gnt; + wire rsrc_rdy_filtered; + wire [63:0]s_axis_tx_tdata; + wire [0:0]s_axis_tx_tkeep; + wire s_axis_tx_tlast; + wire [3:0]s_axis_tx_tuser; + wire s_axis_tx_tvalid; + wire tbuf_av_min_trig; + wire tcfg_req_trig; + wire [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63] ; + wire \throttle_ctl_pipeline.reg_tkeep_reg[7] ; + wire [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3] ; + wire tready_thrtl_i_5; + wire tready_thrtl_reg; + wire trn_in_packet; + wire trn_in_packet_reg; + wire [6:0]trn_rbar_hit; + wire [63:0]trn_rd; + wire trn_recrc_err; + wire trn_reof; + wire trn_rerrfwd; + wire [0:0]trn_rrem; + wire trn_rsof; + wire trn_rsrc_dsc; + wire trn_rsrc_dsc_d; + wire trn_rsrc_dsc_prev0; + wire [5:0]trn_tbuf_av; + wire trn_tcfg_gnt; + wire trn_tcfg_req; + wire trn_tdst_rdy; + wire trn_teof; + wire [0:0]trn_trem; + wire trn_tsof; + wire trn_tsrc_rdy; + wire tx_cfg_gnt; + + pcie_7x_0_pcie_7x_0_axi_basic_rx rx_inst + (.E(E), + .Q(Q), + .dsc_detect(dsc_detect), + .m_axis_rx_tkeep(m_axis_rx_tkeep), + .m_axis_rx_tlast(m_axis_rx_tlast), + .m_axis_rx_tready(m_axis_rx_tready), + .m_axis_rx_tuser(m_axis_rx_tuser), + .m_axis_rx_tvalid_reg(m_axis_rx_tvalid_reg), + .pipe_userclk2_in(pipe_userclk2_in), + .reg_dsc_detect_reg(reg_dsc_detect), + .rsrc_rdy_filtered(rsrc_rdy_filtered), + .trn_in_packet(trn_in_packet), + .trn_in_packet_reg(trn_in_packet_reg), + .trn_rbar_hit(trn_rbar_hit), + .\trn_rbar_hit_prev_reg[0] (\throttle_ctl_pipeline.reg_tkeep_reg[7] ), + .trn_rd(trn_rd), + .trn_recrc_err(trn_recrc_err), + .trn_reof(trn_reof), + .trn_rerrfwd(trn_rerrfwd), + .trn_rrem(trn_rrem), + .trn_rsof(trn_rsof), + .trn_rsrc_dsc(trn_rsrc_dsc), + .trn_rsrc_dsc_d(trn_rsrc_dsc_d), + .trn_rsrc_dsc_prev0(trn_rsrc_dsc_prev0)); + pcie_7x_0_pcie_7x_0_axi_basic_tx tx_inst + (.cfg_pcie_link_state(cfg_pcie_link_state), + .cfg_pm_turnoff_ok_n(cfg_pm_turnoff_ok_n), + .cfg_to_turnoff(cfg_to_turnoff), + .cfg_turnoff_ok(cfg_turnoff_ok), + .lnk_up_thrtl(lnk_up_thrtl), + .lnk_up_thrtl_reg(lnk_up_thrtl_reg), + .out(out), + .pipe_userclk2_in(pipe_userclk2_in), + .ppm_L1_thrtl(ppm_L1_thrtl), + .ppm_L1_thrtl_reg(ppm_L1_thrtl_reg), + .ppm_L1_trig(ppm_L1_trig), + .reg_tcfg_gnt(reg_tcfg_gnt), + .s_axis_tx_tdata(s_axis_tx_tdata), + .s_axis_tx_tkeep(s_axis_tx_tkeep), + .s_axis_tx_tlast(s_axis_tx_tlast), + .s_axis_tx_tuser(s_axis_tx_tuser), + .s_axis_tx_tvalid(s_axis_tx_tvalid), + .tbuf_av_min_trig(tbuf_av_min_trig), + .tcfg_req_trig(tcfg_req_trig), + .\throttle_ctl_pipeline.reg_tdata_reg[63] (\throttle_ctl_pipeline.reg_tdata_reg[63] ), + .\throttle_ctl_pipeline.reg_tkeep_reg[7] (\throttle_ctl_pipeline.reg_tkeep_reg[7] ), + .\throttle_ctl_pipeline.reg_tuser_reg[3] (\throttle_ctl_pipeline.reg_tuser_reg[3] ), + .tready_thrtl_i_5(tready_thrtl_i_5), + .tready_thrtl_reg(tready_thrtl_reg), + .trn_tbuf_av(trn_tbuf_av), + .trn_tcfg_gnt(trn_tcfg_gnt), + .trn_tcfg_req(trn_tcfg_req), + .trn_tdst_rdy(trn_tdst_rdy), + .trn_teof(trn_teof), + .trn_trem(trn_trem), + .trn_tsof(trn_tsof), + .trn_tsrc_rdy(trn_tsrc_rdy), + .tx_cfg_gnt(tx_cfg_gnt)); +endmodule + +module pcie_7x_0_pcie_7x_0_axi_basic_tx + (reg_tcfg_gnt, + tready_thrtl_reg, + trn_teof, + trn_tsrc_rdy, + trn_trem, + ppm_L1_thrtl, + lnk_up_thrtl, + ppm_L1_trig, + cfg_pm_turnoff_ok_n, + trn_tcfg_gnt, + trn_tsof, + \throttle_ctl_pipeline.reg_tdata_reg[63] , + \throttle_ctl_pipeline.reg_tuser_reg[3] , + \throttle_ctl_pipeline.reg_tkeep_reg[7] , + tx_cfg_gnt, + pipe_userclk2_in, + trn_tcfg_req, + trn_tdst_rdy, + tbuf_av_min_trig, + cfg_turnoff_ok, + s_axis_tx_tlast, + s_axis_tx_tvalid, + s_axis_tx_tkeep, + ppm_L1_thrtl_reg, + lnk_up_thrtl_reg, + out, + tcfg_req_trig, + tready_thrtl_i_5, + cfg_pcie_link_state, + s_axis_tx_tdata, + s_axis_tx_tuser, + trn_tbuf_av, + cfg_to_turnoff); + output reg_tcfg_gnt; + output tready_thrtl_reg; + output trn_teof; + output trn_tsrc_rdy; + output [0:0]trn_trem; + output ppm_L1_thrtl; + output lnk_up_thrtl; + output ppm_L1_trig; + output cfg_pm_turnoff_ok_n; + output trn_tcfg_gnt; + output trn_tsof; + output [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63] ; + output [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3] ; + input \throttle_ctl_pipeline.reg_tkeep_reg[7] ; + input tx_cfg_gnt; + input pipe_userclk2_in; + input trn_tcfg_req; + input trn_tdst_rdy; + input tbuf_av_min_trig; + input cfg_turnoff_ok; + input s_axis_tx_tlast; + input s_axis_tx_tvalid; + input [0:0]s_axis_tx_tkeep; + input ppm_L1_thrtl_reg; + input lnk_up_thrtl_reg; + input out; + input tcfg_req_trig; + input tready_thrtl_i_5; + input [2:0]cfg_pcie_link_state; + input [63:0]s_axis_tx_tdata; + input [3:0]s_axis_tx_tuser; + input [5:0]trn_tbuf_av; + input cfg_to_turnoff; + + wire axi_in_packet; + wire [2:0]cfg_pcie_link_state; + wire cfg_pm_turnoff_ok_n; + wire cfg_to_turnoff; + wire cfg_turnoff_ok; + wire lnk_up_thrtl; + wire lnk_up_thrtl_reg; + wire out; + wire pipe_userclk2_in; + wire ppm_L1_thrtl; + wire ppm_L1_thrtl_reg; + wire ppm_L1_trig; + wire reg_disable_trn; + wire reg_tcfg_gnt; + wire reg_tsrc_rdy0; + wire [63:0]s_axis_tx_tdata; + wire [0:0]s_axis_tx_tkeep; + wire s_axis_tx_tlast; + wire [3:0]s_axis_tx_tuser; + wire s_axis_tx_tvalid; + wire tbuf_av_min_trig; + wire tcfg_req_trig; + wire [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63] ; + wire \throttle_ctl_pipeline.reg_tkeep_reg[7] ; + wire [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3] ; + wire \thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4 ; + wire tready_thrtl_i_5; + wire tready_thrtl_reg; + wire [5:0]trn_tbuf_av; + wire trn_tcfg_gnt; + wire trn_tcfg_req; + wire trn_tdst_rdy; + wire trn_teof; + wire [0:0]trn_trem; + wire trn_tsof; + wire trn_tsrc_rdy; + wire tx_cfg_gnt; + + pcie_7x_0_pcie_7x_0_axi_basic_tx_thrtl_ctl \thrtl_ctl_enabled.tx_thrl_ctl_inst + (.axi_in_packet(axi_in_packet), + .cfg_pcie_link_state(cfg_pcie_link_state), + .cfg_pm_turnoff_ok_n(cfg_pm_turnoff_ok_n), + .cfg_to_turnoff(cfg_to_turnoff), + .cfg_turnoff_ok(cfg_turnoff_ok), + .lnk_up_thrtl(lnk_up_thrtl), + .lnk_up_thrtl_reg_0(lnk_up_thrtl_reg), + .out(out), + .pipe_userclk2_in(pipe_userclk2_in), + .ppm_L1_thrtl(ppm_L1_thrtl), + .ppm_L1_thrtl_reg_0(ppm_L1_thrtl_reg), + .ppm_L1_trig(ppm_L1_trig), + .reg_disable_trn(reg_disable_trn), + .reg_tcfg_gnt(reg_tcfg_gnt), + .reg_tsrc_rdy0(reg_tsrc_rdy0), + .s_axis_tx_tdata({s_axis_tx_tdata[30:29],s_axis_tx_tdata[15],s_axis_tx_tdata[0]}), + .s_axis_tx_tlast(s_axis_tx_tlast), + .s_axis_tx_tlast_0(\thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4 ), + .s_axis_tx_tuser(s_axis_tx_tuser[0]), + .s_axis_tx_tvalid(s_axis_tx_tvalid), + .tbuf_av_min_trig(tbuf_av_min_trig), + .\tbuf_gap_cnt_reg[0]_0 (\throttle_ctl_pipeline.reg_tkeep_reg[7] ), + .tcfg_req_trig(tcfg_req_trig), + .tready_thrtl_i_5_0(tready_thrtl_i_5), + .tready_thrtl_reg_0(tready_thrtl_reg), + .trn_tbuf_av(trn_tbuf_av), + .trn_tcfg_gnt(trn_tcfg_gnt), + .trn_tcfg_req(trn_tcfg_req), + .trn_tdst_rdy(trn_tdst_rdy), + .tx_cfg_gnt(tx_cfg_gnt)); + pcie_7x_0_pcie_7x_0_axi_basic_tx_pipeline tx_pipeline_inst + (.axi_in_packet(axi_in_packet), + .axi_in_packet_reg_0(\thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4 ), + .out(out), + .pipe_userclk2_in(pipe_userclk2_in), + .reg_disable_trn(reg_disable_trn), + .reg_tsrc_rdy0(reg_tsrc_rdy0), + .s_axis_tx_tdata(s_axis_tx_tdata), + .s_axis_tx_tkeep(s_axis_tx_tkeep), + .s_axis_tx_tlast(s_axis_tx_tlast), + .s_axis_tx_tuser(s_axis_tx_tuser), + .s_axis_tx_tvalid(s_axis_tx_tvalid), + .\throttle_ctl_pipeline.reg_tdata_reg[63]_0 (\throttle_ctl_pipeline.reg_tdata_reg[63] ), + .\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 (\throttle_ctl_pipeline.reg_tkeep_reg[7] ), + .\throttle_ctl_pipeline.reg_tuser_reg[3]_0 (\throttle_ctl_pipeline.reg_tuser_reg[3] ), + .\thrtl_ctl_trn_flush.reg_disable_trn_reg_0 (tready_thrtl_reg), + .trn_tdst_rdy(trn_tdst_rdy), + .trn_teof(trn_teof), + .trn_trem(trn_trem), + .trn_tsof(trn_tsof), + .trn_tsrc_rdy(trn_tsrc_rdy)); +endmodule + +module pcie_7x_0_pcie_7x_0_axi_basic_tx_pipeline + (trn_teof, + trn_tsrc_rdy, + trn_trem, + axi_in_packet, + reg_disable_trn, + trn_tsof, + \throttle_ctl_pipeline.reg_tdata_reg[63]_0 , + \throttle_ctl_pipeline.reg_tuser_reg[3]_0 , + \throttle_ctl_pipeline.reg_tkeep_reg[7]_0 , + s_axis_tx_tlast, + pipe_userclk2_in, + reg_tsrc_rdy0, + s_axis_tx_tvalid, + s_axis_tx_tkeep, + axi_in_packet_reg_0, + out, + \thrtl_ctl_trn_flush.reg_disable_trn_reg_0 , + trn_tdst_rdy, + s_axis_tx_tdata, + s_axis_tx_tuser); + output trn_teof; + output trn_tsrc_rdy; + output [0:0]trn_trem; + output axi_in_packet; + output reg_disable_trn; + output trn_tsof; + output [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63]_0 ; + output [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3]_0 ; + input \throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ; + input s_axis_tx_tlast; + input pipe_userclk2_in; + input reg_tsrc_rdy0; + input s_axis_tx_tvalid; + input [0:0]s_axis_tx_tkeep; + input axi_in_packet_reg_0; + input out; + input \thrtl_ctl_trn_flush.reg_disable_trn_reg_0 ; + input trn_tdst_rdy; + input [63:0]s_axis_tx_tdata; + input [3:0]s_axis_tx_tuser; + + wire axi_in_packet; + wire axi_in_packet_reg_0; + wire out; + wire pipe_userclk2_in; + wire reg_disable_trn; + wire reg_tsrc_rdy0; + wire reg_tvalid; + wire [63:0]s_axis_tx_tdata; + wire [0:0]s_axis_tx_tkeep; + wire s_axis_tx_tlast; + wire [3:0]s_axis_tx_tuser; + wire s_axis_tx_tvalid; + wire [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63]_0 ; + wire \throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ; + wire [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3]_0 ; + wire \thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0 ; + wire \thrtl_ctl_trn_flush.reg_disable_trn_reg_0 ; + wire trn_in_packet; + wire trn_in_packet_i_1__0_n_0; + wire trn_tdst_rdy; + wire trn_teof; + wire [0:0]trn_trem; + wire trn_tsof; + wire trn_tsrc_rdy; + + FDRE axi_in_packet_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(axi_in_packet_reg_0), + .Q(axi_in_packet), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + LUT2 #( + .INIT(4'h2)) + pcie_block_i_i_31 + (.I0(reg_tvalid), + .I1(trn_in_packet), + .O(trn_tsof)); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[0] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[0]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [0]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[10] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[10]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [10]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[11] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[11]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [11]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[12] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[12]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [12]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[13] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[13]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [13]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[14] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[14]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [14]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[15] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[15]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [15]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[16] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[16]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [16]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[17] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[17]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [17]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[18] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[18]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [18]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[19] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[19]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [19]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[1] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[1]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [1]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[20] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[20]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [20]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[21] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[21]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [21]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[22] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[22]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [22]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[23] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[23]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [23]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[24] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[24]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [24]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[25] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[25]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [25]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[26] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[26]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [26]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[27] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[27]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [27]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[28] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[28]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [28]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[29] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[29]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [29]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[2] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[2]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [2]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[30] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[30]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [30]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[31] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[31]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [31]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[32] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[32]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [32]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[33] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[33]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [33]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[34] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[34]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [34]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[35] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[35]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [35]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[36] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[36]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [36]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[37] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[37]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [37]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[38] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[38]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [38]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[39] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[39]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [39]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[3] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[3]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [3]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[40] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[40]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [40]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[41] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[41]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [41]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[42] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[42]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [42]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[43] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[43]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [43]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[44] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[44]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [44]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[45] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[45]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [45]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[46] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[46]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [46]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[47] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[47]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [47]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[48] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[48]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [48]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[49] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[49]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [49]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[4] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[4]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [4]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[50] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[50]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [50]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[51] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[51]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [51]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[52] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[52]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [52]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[53] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[53]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [53]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[54] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[54]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [54]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[55] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[55]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [55]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[56] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[56]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [56]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[57] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[57]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [57]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[58] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[58]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [58]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[59] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[59]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [59]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[5] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[5]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [5]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[60] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[60]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [60]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[61] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[61]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [61]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[62] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[62]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [62]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[63] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[63]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [63]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[6] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[6]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [6]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[7] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[7]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [7]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[8] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[8]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [8]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tdata_reg[9] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tdata[9]), + .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [9]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tkeep_reg[7] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tkeep), + .Q(trn_trem), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tlast_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tlast), + .Q(trn_teof), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tsrc_rdy_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(reg_tsrc_rdy0), + .Q(trn_tsrc_rdy), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tuser_reg[0] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tuser[0]), + .Q(\throttle_ctl_pipeline.reg_tuser_reg[3]_0 [0]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tuser_reg[1] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tuser[1]), + .Q(\throttle_ctl_pipeline.reg_tuser_reg[3]_0 [1]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tuser_reg[2] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tuser[2]), + .Q(\throttle_ctl_pipeline.reg_tuser_reg[3]_0 [2]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tuser_reg[3] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tuser[3]), + .Q(\throttle_ctl_pipeline.reg_tuser_reg[3]_0 [3]), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + FDRE \throttle_ctl_pipeline.reg_tvalid_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(s_axis_tx_tvalid), + .Q(reg_tvalid), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + LUT6 #( + .INIT(64'h0FFFFFFF04444444)) + \thrtl_ctl_trn_flush.reg_disable_trn_i_1 + (.I0(out), + .I1(axi_in_packet), + .I2(\thrtl_ctl_trn_flush.reg_disable_trn_reg_0 ), + .I3(s_axis_tx_tvalid), + .I4(s_axis_tx_tlast), + .I5(reg_disable_trn), + .O(\thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0 )); + FDRE \thrtl_ctl_trn_flush.reg_disable_trn_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(\thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0 ), + .Q(reg_disable_trn), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); + LUT6 #( + .INIT(64'h0000F088F000F000)) + trn_in_packet_i_1__0 + (.I0(trn_tdst_rdy), + .I1(reg_tvalid), + .I2(out), + .I3(trn_in_packet), + .I4(trn_teof), + .I5(trn_tsrc_rdy), + .O(trn_in_packet_i_1__0_n_0)); + FDRE trn_in_packet_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(trn_in_packet_i_1__0_n_0), + .Q(trn_in_packet), + .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 )); +endmodule + +module pcie_7x_0_pcie_7x_0_axi_basic_tx_thrtl_ctl + (reg_tcfg_gnt, + tready_thrtl_reg_0, + ppm_L1_thrtl, + lnk_up_thrtl, + s_axis_tx_tlast_0, + ppm_L1_trig, + cfg_pm_turnoff_ok_n, + trn_tcfg_gnt, + reg_tsrc_rdy0, + \tbuf_gap_cnt_reg[0]_0 , + tx_cfg_gnt, + pipe_userclk2_in, + trn_tcfg_req, + trn_tdst_rdy, + tbuf_av_min_trig, + cfg_turnoff_ok, + ppm_L1_thrtl_reg_0, + lnk_up_thrtl_reg_0, + s_axis_tx_tlast, + s_axis_tx_tvalid, + axi_in_packet, + out, + tcfg_req_trig, + tready_thrtl_i_5_0, + cfg_pcie_link_state, + s_axis_tx_tdata, + s_axis_tx_tuser, + reg_disable_trn, + trn_tbuf_av, + cfg_to_turnoff); + output reg_tcfg_gnt; + output tready_thrtl_reg_0; + output ppm_L1_thrtl; + output lnk_up_thrtl; + output s_axis_tx_tlast_0; + output ppm_L1_trig; + output cfg_pm_turnoff_ok_n; + output trn_tcfg_gnt; + output reg_tsrc_rdy0; + input \tbuf_gap_cnt_reg[0]_0 ; + input tx_cfg_gnt; + input pipe_userclk2_in; + input trn_tcfg_req; + input trn_tdst_rdy; + input tbuf_av_min_trig; + input cfg_turnoff_ok; + input ppm_L1_thrtl_reg_0; + input lnk_up_thrtl_reg_0; + input s_axis_tx_tlast; + input s_axis_tx_tvalid; + input axi_in_packet; + input out; + input tcfg_req_trig; + input tready_thrtl_i_5_0; + input [2:0]cfg_pcie_link_state; + input [3:0]s_axis_tx_tdata; + input [0:0]s_axis_tx_tuser; + input reg_disable_trn; + input [5:0]trn_tbuf_av; + input cfg_to_turnoff; + + wire \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ; + wire \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1_n_0 ; + wire axi_in_packet; + wire [2:0]cfg_pcie_link_state; + wire [2:0]cfg_pcie_link_state_d; + wire cfg_pm_turnoff_ok_n; + wire cfg_to_turnoff; + wire cfg_turnoff_ok; + wire cfg_turnoff_ok_pending; + wire cfg_turnoff_ok_pending_i_1_n_0; + wire cur_state; + wire cur_state_i_2_n_0; + wire \ecrc_pause_enabled.reg_tx_ecrc_pkt ; + wire \ecrc_pause_enabled.reg_tx_ecrc_pkt021_out ; + wire \ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1_n_0 ; + wire lnk_up_thrtl; + wire lnk_up_thrtl_reg_0; + wire next_state; + wire out; + wire p_2_in; + wire pcie_block_i_i_36_n_0; + wire pipe_userclk2_in; + wire ppm_L1_thrtl; + wire ppm_L1_thrtl_reg_0; + wire ppm_L1_trig; + wire ppm_L23_thrtl; + wire ppm_L23_thrtl_i_1_n_0; + wire ppm_L23_trig; + wire reg_axi_in_pkt; + wire reg_axi_in_pkt_i_1_n_0; + wire reg_disable_trn; + wire reg_tcfg_gnt; + wire reg_tsrc_rdy0; + wire reg_turnoff_ok; + wire [3:0]s_axis_tx_tdata; + wire s_axis_tx_tlast; + wire s_axis_tx_tlast_0; + wire [0:0]s_axis_tx_tuser; + wire s_axis_tx_tvalid; + wire [5:0]tbuf_av_d; + wire tbuf_av_gap_thrtl; + wire tbuf_av_gap_thrtl_i_1_n_0; + wire tbuf_av_gap_trig; + wire tbuf_av_min_thrtl; + wire tbuf_av_min_trig; + wire \tbuf_gap_cnt[0]_i_1_n_0 ; + wire \tbuf_gap_cnt_reg[0]_0 ; + wire \tbuf_gap_cnt_reg_n_0_[0] ; + wire tcfg_gnt_pending; + wire tcfg_gnt_pending_i_1_n_0; + wire [1:0]tcfg_req_cnt; + wire \tcfg_req_cnt[0]_i_1_n_0 ; + wire \tcfg_req_cnt[1]_i_1_n_0 ; + wire tcfg_req_thrtl; + wire tcfg_req_thrtl_i_1_n_0; + wire tcfg_req_trig; + wire tready_thrtl0; + wire tready_thrtl_i_10_n_0; + wire tready_thrtl_i_12_n_0; + wire tready_thrtl_i_2_n_0; + wire tready_thrtl_i_3_n_0; + wire tready_thrtl_i_4_n_0; + wire tready_thrtl_i_5_0; + wire tready_thrtl_i_6_n_0; + wire tready_thrtl_i_7_n_0; + wire tready_thrtl_reg_0; + wire [5:0]trn_tbuf_av; + wire trn_tcfg_gnt; + wire trn_tcfg_req; + wire trn_tcfg_req_d; + wire trn_tdst_rdy; + wire trn_tdst_rdy_d; + wire tx_cfg_gnt; + + FDRE \L23_thrtl_ep.reg_turnoff_ok_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(cfg_turnoff_ok), + .Q(reg_turnoff_ok), + .R(\tbuf_gap_cnt_reg[0]_0 )); + (* SOFT_HLUTNM = "soft_lutpair255" *) + LUT2 #( + .INIT(4'hE)) + \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1 + (.I0(cfg_to_turnoff), + .I1(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ), + .O(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1_n_0 )); + FDRE \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1_n_0 ), + .Q(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ), + .R(\tbuf_gap_cnt_reg[0]_0 )); + LUT4 #( + .INIT(16'h7F40)) + axi_in_packet_i_1 + (.I0(s_axis_tx_tlast), + .I1(s_axis_tx_tvalid), + .I2(tready_thrtl_reg_0), + .I3(axi_in_packet), + .O(s_axis_tx_tlast_0)); + FDRE \cfg_pcie_link_state_d_reg[0] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(cfg_pcie_link_state[0]), + .Q(cfg_pcie_link_state_d[0]), + .R(\tbuf_gap_cnt_reg[0]_0 )); + FDRE \cfg_pcie_link_state_d_reg[1] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(cfg_pcie_link_state[1]), + .Q(cfg_pcie_link_state_d[1]), + .R(\tbuf_gap_cnt_reg[0]_0 )); + FDRE \cfg_pcie_link_state_d_reg[2] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(cfg_pcie_link_state[2]), + .Q(cfg_pcie_link_state_d[2]), + .R(\tbuf_gap_cnt_reg[0]_0 )); + (* SOFT_HLUTNM = "soft_lutpair252" *) + LUT5 #( + .INIT(32'h75553000)) + cfg_turnoff_ok_pending_i_1 + (.I0(cfg_pm_turnoff_ok_n), + .I1(ppm_L23_thrtl), + .I2(reg_turnoff_ok), + .I3(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ), + .I4(cfg_turnoff_ok_pending), + .O(cfg_turnoff_ok_pending_i_1_n_0)); + FDRE cfg_turnoff_ok_pending_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(cfg_turnoff_ok_pending_i_1_n_0), + .Q(cfg_turnoff_ok_pending), + .R(\tbuf_gap_cnt_reg[0]_0 )); + LUT6 #( + .INIT(64'h5455445554555555)) + cur_state_i_1__0 + (.I0(cur_state_i_2_n_0), + .I1(cur_state), + .I2(s_axis_tx_tlast), + .I3(tready_thrtl_reg_0), + .I4(s_axis_tx_tvalid), + .I5(reg_axi_in_pkt), + .O(next_state)); + LUT6 #( + .INIT(64'h0000000000000001)) + cur_state_i_2 + (.I0(ppm_L1_thrtl), + .I1(lnk_up_thrtl), + .I2(tcfg_req_thrtl), + .I3(ppm_L23_thrtl), + .I4(tbuf_av_gap_thrtl), + .I5(tbuf_av_min_thrtl), + .O(cur_state_i_2_n_0)); + FDSE cur_state_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(next_state), + .Q(cur_state), + .S(\tbuf_gap_cnt_reg[0]_0 )); + LUT5 #( + .INIT(32'hBFFFAAAA)) + \ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1 + (.I0(\ecrc_pause_enabled.reg_tx_ecrc_pkt021_out ), + .I1(tready_thrtl_reg_0), + .I2(s_axis_tx_tvalid), + .I3(s_axis_tx_tlast), + .I4(\ecrc_pause_enabled.reg_tx_ecrc_pkt ), + .O(\ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair253" *) + LUT5 #( + .INIT(32'h00001444)) + \ecrc_pause_enabled.reg_tx_ecrc_pkt_i_2 + (.I0(tready_thrtl_i_7_n_0), + .I1(s_axis_tx_tdata[2]), + .I2(s_axis_tx_tdata[3]), + .I3(s_axis_tx_tdata[0]), + .I4(s_axis_tx_tlast), + .O(\ecrc_pause_enabled.reg_tx_ecrc_pkt021_out )); + FDRE \ecrc_pause_enabled.reg_tx_ecrc_pkt_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(\ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1_n_0 ), + .Q(\ecrc_pause_enabled.reg_tx_ecrc_pkt ), + .R(\tbuf_gap_cnt_reg[0]_0 )); + FDSE lnk_up_thrtl_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(lnk_up_thrtl_reg_0), + .Q(lnk_up_thrtl), + .S(\tbuf_gap_cnt_reg[0]_0 )); + LUT6 #( + .INIT(64'h20202020A0AFA0A0)) + pcie_block_i_i_26 + (.I0(cfg_turnoff_ok_pending), + .I1(tcfg_gnt_pending), + .I2(cur_state), + .I3(pcie_block_i_i_36_n_0), + .I4(ppm_L23_thrtl), + .I5(tcfg_req_thrtl), + .O(cfg_pm_turnoff_ok_n)); + (* SOFT_HLUTNM = "soft_lutpair254" *) + LUT4 #( + .INIT(16'hA202)) + pcie_block_i_i_30 + (.I0(tcfg_req_thrtl), + .I1(pcie_block_i_i_36_n_0), + .I2(cur_state), + .I3(tcfg_gnt_pending), + .O(trn_tcfg_gnt)); + (* SOFT_HLUTNM = "soft_lutpair250" *) + LUT5 #( + .INIT(32'hFFFF20E0)) + pcie_block_i_i_36 + (.I0(reg_axi_in_pkt), + .I1(s_axis_tx_tvalid), + .I2(tready_thrtl_reg_0), + .I3(s_axis_tx_tlast), + .I4(cur_state_i_2_n_0), + .O(pcie_block_i_i_36_n_0)); + LUT6 #( + .INIT(64'h0000010000000000)) + ppm_L1_thrtl_i_2 + (.I0(cfg_pcie_link_state_d[1]), + .I1(cfg_pcie_link_state_d[2]), + .I2(cfg_pcie_link_state_d[0]), + .I3(cfg_pcie_link_state[0]), + .I4(cfg_pcie_link_state[1]), + .I5(cfg_pcie_link_state[2]), + .O(ppm_L1_trig)); + FDRE ppm_L1_thrtl_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(ppm_L1_thrtl_reg_0), + .Q(ppm_L1_thrtl), + .R(\tbuf_gap_cnt_reg[0]_0 )); + (* SOFT_HLUTNM = "soft_lutpair252" *) + LUT3 #( + .INIT(8'hF8)) + ppm_L23_thrtl_i_1 + (.I0(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ), + .I1(reg_turnoff_ok), + .I2(ppm_L23_thrtl), + .O(ppm_L23_thrtl_i_1_n_0)); + FDRE ppm_L23_thrtl_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(ppm_L23_thrtl_i_1_n_0), + .Q(ppm_L23_thrtl), + .R(\tbuf_gap_cnt_reg[0]_0 )); + LUT5 #( + .INIT(32'h00005F40)) + reg_axi_in_pkt_i_1 + (.I0(s_axis_tx_tlast), + .I1(tready_thrtl_reg_0), + .I2(s_axis_tx_tvalid), + .I3(reg_axi_in_pkt), + .I4(\tbuf_gap_cnt_reg[0]_0 ), + .O(reg_axi_in_pkt_i_1_n_0)); + FDRE reg_axi_in_pkt_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(reg_axi_in_pkt_i_1_n_0), + .Q(reg_axi_in_pkt), + .R(1'b0)); + FDRE reg_tcfg_gnt_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(tx_cfg_gnt), + .Q(reg_tcfg_gnt), + .R(\tbuf_gap_cnt_reg[0]_0 )); + FDRE \tbuf_av_d_reg[0] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(trn_tbuf_av[0]), + .Q(tbuf_av_d[0]), + .R(\tbuf_gap_cnt_reg[0]_0 )); + FDRE \tbuf_av_d_reg[1] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(trn_tbuf_av[1]), + .Q(tbuf_av_d[1]), + .R(\tbuf_gap_cnt_reg[0]_0 )); + FDRE \tbuf_av_d_reg[2] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(trn_tbuf_av[2]), + .Q(tbuf_av_d[2]), + .R(\tbuf_gap_cnt_reg[0]_0 )); + FDRE \tbuf_av_d_reg[3] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(trn_tbuf_av[3]), + .Q(tbuf_av_d[3]), + .R(\tbuf_gap_cnt_reg[0]_0 )); + FDRE \tbuf_av_d_reg[4] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(trn_tbuf_av[4]), + .Q(tbuf_av_d[4]), + .R(\tbuf_gap_cnt_reg[0]_0 )); + FDRE \tbuf_av_d_reg[5] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(trn_tbuf_av[5]), + .Q(tbuf_av_d[5]), + .R(\tbuf_gap_cnt_reg[0]_0 )); + LUT3 #( + .INIT(8'hEA)) + tbuf_av_gap_thrtl_i_1 + (.I0(tbuf_av_gap_trig), + .I1(\tbuf_gap_cnt_reg_n_0_[0] ), + .I2(tbuf_av_gap_thrtl), + .O(tbuf_av_gap_thrtl_i_1_n_0)); + FDRE tbuf_av_gap_thrtl_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(tbuf_av_gap_thrtl_i_1_n_0), + .Q(tbuf_av_gap_thrtl), + .R(\tbuf_gap_cnt_reg[0]_0 )); + FDRE tbuf_av_min_thrtl_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(tbuf_av_min_trig), + .Q(tbuf_av_min_thrtl), + .R(\tbuf_gap_cnt_reg[0]_0 )); + (* SOFT_HLUTNM = "soft_lutpair254" *) + LUT2 #( + .INIT(4'h7)) + \tbuf_gap_cnt[0]_i_1 + (.I0(tbuf_av_gap_thrtl), + .I1(cur_state), + .O(\tbuf_gap_cnt[0]_i_1_n_0 )); + FDRE \tbuf_gap_cnt_reg[0] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(\tbuf_gap_cnt[0]_i_1_n_0 ), + .Q(\tbuf_gap_cnt_reg_n_0_[0] ), + .R(\tbuf_gap_cnt_reg[0]_0 )); + LUT6 #( + .INIT(64'h44F44444F4F4F4F4)) + tcfg_gnt_pending_i_1 + (.I0(trn_tcfg_req_d), + .I1(trn_tcfg_req), + .I2(tcfg_gnt_pending), + .I3(cur_state), + .I4(pcie_block_i_i_36_n_0), + .I5(tcfg_req_thrtl), + .O(tcfg_gnt_pending_i_1_n_0)); + FDRE tcfg_gnt_pending_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(tcfg_gnt_pending_i_1_n_0), + .Q(tcfg_gnt_pending), + .R(\tbuf_gap_cnt_reg[0]_0 )); + LUT6 #( + .INIT(64'h0000000000000D00)) + \tcfg_req_cnt[0]_i_1 + (.I0(trn_tcfg_req), + .I1(trn_tcfg_req_d), + .I2(tcfg_gnt_pending), + .I3(tcfg_req_cnt[1]), + .I4(tcfg_req_cnt[0]), + .I5(\tbuf_gap_cnt_reg[0]_0 ), + .O(\tcfg_req_cnt[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair251" *) + LUT5 #( + .INIT(32'hFFFF88F8)) + \tcfg_req_cnt[1]_i_1 + (.I0(tcfg_req_cnt[0]), + .I1(tcfg_req_cnt[1]), + .I2(trn_tcfg_req), + .I3(trn_tcfg_req_d), + .I4(tcfg_gnt_pending), + .O(\tcfg_req_cnt[1]_i_1_n_0 )); + FDRE \tcfg_req_cnt_reg[0] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(\tcfg_req_cnt[0]_i_1_n_0 ), + .Q(tcfg_req_cnt[0]), + .R(1'b0)); + FDRE \tcfg_req_cnt_reg[1] + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(\tcfg_req_cnt[1]_i_1_n_0 ), + .Q(tcfg_req_cnt[1]), + .R(\tbuf_gap_cnt_reg[0]_0 )); + LUT6 #( + .INIT(64'hFFFFF8FF88888888)) + tcfg_req_thrtl_i_1 + (.I0(reg_tcfg_gnt), + .I1(trn_tcfg_req), + .I2(trn_tdst_rdy_d), + .I3(trn_tdst_rdy), + .I4(p_2_in), + .I5(tcfg_req_thrtl), + .O(tcfg_req_thrtl_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair251" *) + LUT2 #( + .INIT(4'hE)) + tcfg_req_thrtl_i_2 + (.I0(tcfg_req_cnt[1]), + .I1(tcfg_req_cnt[0]), + .O(p_2_in)); + FDRE tcfg_req_thrtl_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(tcfg_req_thrtl_i_1_n_0), + .Q(tcfg_req_thrtl), + .R(\tbuf_gap_cnt_reg[0]_0 )); + LUT4 #( + .INIT(16'h0080)) + \throttle_ctl_pipeline.reg_tsrc_rdy_i_1 + (.I0(tready_thrtl_reg_0), + .I1(s_axis_tx_tvalid), + .I2(out), + .I3(reg_disable_trn), + .O(reg_tsrc_rdy0)); + LUT6 #( + .INIT(64'hF1F1F1F10000F100)) + tready_thrtl_i_1 + (.I0(\ecrc_pause_enabled.reg_tx_ecrc_pkt ), + .I1(tready_thrtl_i_2_n_0), + .I2(tready_thrtl_i_3_n_0), + .I3(tready_thrtl_i_4_n_0), + .I4(tbuf_av_gap_trig), + .I5(tready_thrtl_i_6_n_0), + .O(tready_thrtl0)); + LUT6 #( + .INIT(64'h00002000AAAAAAAA)) + tready_thrtl_i_10 + (.I0(tready_thrtl_i_5_0), + .I1(tbuf_av_d[4]), + .I2(tbuf_av_d[0]), + .I3(tbuf_av_d[1]), + .I4(tready_thrtl_i_12_n_0), + .I5(tready_thrtl_i_3_n_0), + .O(tready_thrtl_i_10_n_0)); + LUT4 #( + .INIT(16'hFFEF)) + tready_thrtl_i_12 + (.I0(tbuf_av_d[5]), + .I1(tbuf_av_d[2]), + .I2(trn_tbuf_av[1]), + .I3(tbuf_av_d[3]), + .O(tready_thrtl_i_12_n_0)); + (* SOFT_HLUTNM = "soft_lutpair253" *) + LUT4 #( + .INIT(16'h0078)) + tready_thrtl_i_2 + (.I0(s_axis_tx_tdata[0]), + .I1(s_axis_tx_tdata[3]), + .I2(s_axis_tx_tdata[2]), + .I3(tready_thrtl_i_7_n_0), + .O(tready_thrtl_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair250" *) + LUT3 #( + .INIT(8'h7F)) + tready_thrtl_i_3 + (.I0(s_axis_tx_tlast), + .I1(s_axis_tx_tvalid), + .I2(tready_thrtl_reg_0), + .O(tready_thrtl_i_3_n_0)); + LUT6 #( + .INIT(64'h0000000000040000)) + tready_thrtl_i_4 + (.I0(ppm_L23_trig), + .I1(out), + .I2(tcfg_req_trig), + .I3(ppm_L1_trig), + .I4(cur_state_i_2_n_0), + .I5(tbuf_av_min_trig), + .O(tready_thrtl_i_4_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFF00100000)) + tready_thrtl_i_5 + (.I0(tcfg_req_cnt[0]), + .I1(tcfg_req_cnt[1]), + .I2(trn_tdst_rdy), + .I3(trn_tdst_rdy_d), + .I4(tcfg_req_thrtl), + .I5(tready_thrtl_i_10_n_0), + .O(tbuf_av_gap_trig)); + LUT5 #( + .INIT(32'h000020E0)) + tready_thrtl_i_6 + (.I0(reg_axi_in_pkt), + .I1(s_axis_tx_tvalid), + .I2(tready_thrtl_reg_0), + .I3(s_axis_tx_tlast), + .I4(cur_state), + .O(tready_thrtl_i_6_n_0)); + LUT5 #( + .INIT(32'hFFFFDFFF)) + tready_thrtl_i_7 + (.I0(s_axis_tx_tuser), + .I1(s_axis_tx_tdata[1]), + .I2(s_axis_tx_tvalid), + .I3(tready_thrtl_reg_0), + .I4(reg_axi_in_pkt), + .O(tready_thrtl_i_7_n_0)); + (* SOFT_HLUTNM = "soft_lutpair255" *) + LUT2 #( + .INIT(4'h8)) + tready_thrtl_i_8 + (.I0(reg_turnoff_ok), + .I1(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ), + .O(ppm_L23_trig)); + FDRE tready_thrtl_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(tready_thrtl0), + .Q(tready_thrtl_reg_0), + .R(\tbuf_gap_cnt_reg[0]_0 )); + FDRE trn_tcfg_req_d_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(trn_tcfg_req), + .Q(trn_tcfg_req_d), + .R(\tbuf_gap_cnt_reg[0]_0 )); + FDSE trn_tdst_rdy_d_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(trn_tdst_rdy), + .Q(trn_tdst_rdy_d), + .S(\tbuf_gap_cnt_reg[0]_0 )); +endmodule + +module pcie_7x_0_pcie_7x_0_core_top + (pl_ltssm_state, + pl_phy_lnk_up, + user_reset_out, + m_axis_rx_tvalid, + s_axis_tx_tready, + cfg_aer_ecrc_check_en, + cfg_aer_ecrc_gen_en, + cfg_aer_rooterr_corr_err_received, + cfg_aer_rooterr_corr_err_reporting_en, + cfg_aer_rooterr_fatal_err_received, + cfg_aer_rooterr_fatal_err_reporting_en, + cfg_aer_rooterr_non_fatal_err_received, + cfg_aer_rooterr_non_fatal_err_reporting_en, + cfg_bridge_serr_en, + cfg_command, + cfg_dcommand2, + cfg_dcommand, + cfg_dstatus, + cfg_interrupt_msienable, + cfg_interrupt_msixenable, + cfg_interrupt_msixfm, + cfg_lcommand, + cfg_lstatus, + cfg_msg_received, + cfg_msg_received_assert_int_a, + cfg_msg_received_assert_int_b, + cfg_msg_received_assert_int_c, + cfg_msg_received_assert_int_d, + cfg_msg_received_deassert_int_a, + cfg_msg_received_deassert_int_b, + cfg_msg_received_deassert_int_c, + cfg_msg_received_deassert_int_d, + cfg_msg_received_err_cor, + cfg_msg_received_err_fatal, + cfg_msg_received_err_non_fatal, + cfg_msg_received_pm_as_nak, + cfg_to_turnoff, + cfg_msg_received_pme_to_ack, + cfg_msg_received_pm_pme, + cfg_msg_received_setslotpowerlimit, + cfg_pmcsr_pme_en, + cfg_pmcsr_pme_status, + cfg_root_control_pme_int_en, + cfg_root_control_syserr_corr_err_en, + cfg_root_control_syserr_fatal_err_en, + cfg_root_control_syserr_non_fatal_err_en, + cfg_slot_control_electromech_il_ctl_pulse, + pcie_drp_rdy, + pl_directed_change_done, + pl_link_gen2_cap, + pl_link_partner_gen2_supported, + pl_link_upcfg_cap, + pl_sel_lnk_rate, + tx_cfg_req, + tx_err_drop, + fc_cpld, + fc_npd, + fc_pd, + cfg_msg_data, + pcie_drp_do, + cfg_pmcsr_powerstate, + pl_lane_reversal_mode, + pl_rx_pm_state, + pl_sel_lnk_width, + cfg_interrupt_mmenable, + cfg_pcie_link_state, + pl_initial_link_width, + pl_tx_pm_state, + cfg_mgmt_do, + tx_buf_av, + cfg_vc_tcvc_map, + cfg_interrupt_do, + fc_cplh, + fc_nph, + fc_ph, + pipe_pclk_sel_out, + gen3_reg, + pci_exp_txn, + pci_exp_txp, + pipe_rxoutclk_out, + pipe_txoutclk_out, + user_lnk_up, + m_axis_rx_tdata, + m_axis_rx_tkeep, + m_axis_rx_tlast, + m_axis_rx_tuser, + cfg_bus_number, + cfg_device_number, + cfg_function_number, + pl_received_hot_rst, + cfg_mgmt_rd_wr_done, + cfg_err_aer_headerlog_set, + cfg_err_cpl_rdy, + cfg_interrupt_rdy, + cfg_received_func_lvl_rst, + pipe_pclk_in, + m_axis_rx_tready, + s_axis_tx_tlast, + s_axis_tx_tvalid, + pipe_userclk2_in, + pipe_userclk1_in, + pcie_drp_clk, + pcie_drp_en, + pcie_drp_we, + pl_directed_link_auton, + pl_directed_link_speed, + pl_downstream_deemph_source, + pl_transmit_hot_rst, + pl_upstream_prefer_deemph, + rx_np_ok, + rx_np_req, + cfg_err_aer_headerlog, + pcie_drp_di, + cfg_pm_force_state, + pl_directed_link_change, + pl_directed_link_width, + cfg_ds_function_number, + fc_sel, + cfg_mgmt_di, + cfg_err_tlp_cpl_header, + cfg_aer_interrupt_msgnum, + cfg_ds_device_number, + cfg_pciecap_interrupt_msgnum, + cfg_dsn, + cfg_ds_bus_number, + cfg_interrupt_di, + pcie_drp_addr, + cfg_mgmt_dwaddr, + pipe_mmcm_lock_in, + pipe_rxusrclk_in, + pipe_dclk_in, + sys_clk, + pipe_oobclk_in, + pci_exp_rxn, + pci_exp_rxp, + sys_rst_n, + tx_cfg_gnt, + cfg_turnoff_ok, + s_axis_tx_tdata, + s_axis_tx_tuser, + s_axis_tx_tkeep, + cfg_mgmt_byte_en, + cfg_trn_pending, + cfg_mgmt_wr_rw1c_as_rw, + cfg_mgmt_wr_readonly, + cfg_mgmt_wr_en, + cfg_mgmt_rd_en, + cfg_err_malformed, + cfg_err_cor, + cfg_err_ur, + cfg_err_ecrc, + cfg_err_cpl_timeout, + cfg_err_cpl_abort, + cfg_err_cpl_unexpect, + cfg_err_poisoned, + cfg_err_atomic_egress_blocked, + cfg_err_mc_blocked, + cfg_err_internal_uncor, + cfg_err_internal_cor, + cfg_err_posted, + cfg_err_locked, + cfg_err_norecovery, + cfg_interrupt, + cfg_interrupt_assert, + cfg_interrupt_stat, + cfg_pm_halt_aspm_l0s, + cfg_pm_halt_aspm_l1, + cfg_pm_force_state_en, + cfg_pm_wake); + output [5:0]pl_ltssm_state; + output pl_phy_lnk_up; + output user_reset_out; + output m_axis_rx_tvalid; + output s_axis_tx_tready; + output cfg_aer_ecrc_check_en; + output cfg_aer_ecrc_gen_en; + output cfg_aer_rooterr_corr_err_received; + output cfg_aer_rooterr_corr_err_reporting_en; + output cfg_aer_rooterr_fatal_err_received; + output cfg_aer_rooterr_fatal_err_reporting_en; + output cfg_aer_rooterr_non_fatal_err_received; + output cfg_aer_rooterr_non_fatal_err_reporting_en; + output cfg_bridge_serr_en; + output [4:0]cfg_command; + output [11:0]cfg_dcommand2; + output [14:0]cfg_dcommand; + output [3:0]cfg_dstatus; + output cfg_interrupt_msienable; + output cfg_interrupt_msixenable; + output cfg_interrupt_msixfm; + output [10:0]cfg_lcommand; + output [9:0]cfg_lstatus; + output cfg_msg_received; + output cfg_msg_received_assert_int_a; + output cfg_msg_received_assert_int_b; + output cfg_msg_received_assert_int_c; + output cfg_msg_received_assert_int_d; + output cfg_msg_received_deassert_int_a; + output cfg_msg_received_deassert_int_b; + output cfg_msg_received_deassert_int_c; + output cfg_msg_received_deassert_int_d; + output cfg_msg_received_err_cor; + output cfg_msg_received_err_fatal; + output cfg_msg_received_err_non_fatal; + output cfg_msg_received_pm_as_nak; + output cfg_to_turnoff; + output cfg_msg_received_pme_to_ack; + output cfg_msg_received_pm_pme; + output cfg_msg_received_setslotpowerlimit; + output cfg_pmcsr_pme_en; + output cfg_pmcsr_pme_status; + output cfg_root_control_pme_int_en; + output cfg_root_control_syserr_corr_err_en; + output cfg_root_control_syserr_fatal_err_en; + output cfg_root_control_syserr_non_fatal_err_en; + output cfg_slot_control_electromech_il_ctl_pulse; + output pcie_drp_rdy; + output pl_directed_change_done; + output pl_link_gen2_cap; + output pl_link_partner_gen2_supported; + output pl_link_upcfg_cap; + output pl_sel_lnk_rate; + output tx_cfg_req; + output tx_err_drop; + output [11:0]fc_cpld; + output [11:0]fc_npd; + output [11:0]fc_pd; + output [15:0]cfg_msg_data; + output [15:0]pcie_drp_do; + output [1:0]cfg_pmcsr_powerstate; + output [1:0]pl_lane_reversal_mode; + output [1:0]pl_rx_pm_state; + output [1:0]pl_sel_lnk_width; + output [2:0]cfg_interrupt_mmenable; + output [2:0]cfg_pcie_link_state; + output [2:0]pl_initial_link_width; + output [2:0]pl_tx_pm_state; + output [31:0]cfg_mgmt_do; + output [5:0]tx_buf_av; + output [6:0]cfg_vc_tcvc_map; + output [7:0]cfg_interrupt_do; + output [7:0]fc_cplh; + output [7:0]fc_nph; + output [7:0]fc_ph; + output [3:0]pipe_pclk_sel_out; + output gen3_reg; + output [3:0]pci_exp_txn; + output [3:0]pci_exp_txp; + output [3:0]pipe_rxoutclk_out; + output pipe_txoutclk_out; + output user_lnk_up; + output [63:0]m_axis_rx_tdata; + output [0:0]m_axis_rx_tkeep; + output m_axis_rx_tlast; + output [12:0]m_axis_rx_tuser; + output [7:0]cfg_bus_number; + output [4:0]cfg_device_number; + output [2:0]cfg_function_number; + output pl_received_hot_rst; + output cfg_mgmt_rd_wr_done; + output cfg_err_aer_headerlog_set; + output cfg_err_cpl_rdy; + output cfg_interrupt_rdy; + output cfg_received_func_lvl_rst; + input pipe_pclk_in; + input m_axis_rx_tready; + input s_axis_tx_tlast; + input s_axis_tx_tvalid; + input pipe_userclk2_in; + input pipe_userclk1_in; + input pcie_drp_clk; + input pcie_drp_en; + input pcie_drp_we; + input pl_directed_link_auton; + input pl_directed_link_speed; + input pl_downstream_deemph_source; + input pl_transmit_hot_rst; + input pl_upstream_prefer_deemph; + input rx_np_ok; + input rx_np_req; + input [127:0]cfg_err_aer_headerlog; + input [15:0]pcie_drp_di; + input [1:0]cfg_pm_force_state; + input [1:0]pl_directed_link_change; + input [1:0]pl_directed_link_width; + input [2:0]cfg_ds_function_number; + input [2:0]fc_sel; + input [31:0]cfg_mgmt_di; + input [47:0]cfg_err_tlp_cpl_header; + input [4:0]cfg_aer_interrupt_msgnum; + input [4:0]cfg_ds_device_number; + input [4:0]cfg_pciecap_interrupt_msgnum; + input [63:0]cfg_dsn; + input [7:0]cfg_ds_bus_number; + input [7:0]cfg_interrupt_di; + input [8:0]pcie_drp_addr; + input [9:0]cfg_mgmt_dwaddr; + input pipe_mmcm_lock_in; + input pipe_rxusrclk_in; + input pipe_dclk_in; + input sys_clk; + input pipe_oobclk_in; + input [3:0]pci_exp_rxn; + input [3:0]pci_exp_rxp; + input sys_rst_n; + input tx_cfg_gnt; + input cfg_turnoff_ok; + input [63:0]s_axis_tx_tdata; + input [3:0]s_axis_tx_tuser; + input [0:0]s_axis_tx_tkeep; + input [3:0]cfg_mgmt_byte_en; + input cfg_trn_pending; + input cfg_mgmt_wr_rw1c_as_rw; + input cfg_mgmt_wr_readonly; + input cfg_mgmt_wr_en; + input cfg_mgmt_rd_en; + input cfg_err_malformed; + input cfg_err_cor; + input cfg_err_ur; + input cfg_err_ecrc; + input cfg_err_cpl_timeout; + input cfg_err_cpl_abort; + input cfg_err_cpl_unexpect; + input cfg_err_poisoned; + input cfg_err_atomic_egress_blocked; + input cfg_err_mc_blocked; + input cfg_err_internal_uncor; + input cfg_err_internal_cor; + input cfg_err_posted; + input cfg_err_locked; + input cfg_err_norecovery; + input cfg_interrupt; + input cfg_interrupt_assert; + input cfg_interrupt_stat; + input cfg_pm_halt_aspm_l0s; + input cfg_pm_halt_aspm_l1; + input cfg_pm_force_state_en; + input cfg_pm_wake; + + wire \_inferred__0/store_ltssm_inferred_i_2_n_0 ; + wire \_inferred__0/store_ltssm_inferred_i_3_n_0 ; + wire bridge_reset_int; + wire cfg_aer_ecrc_check_en; + wire cfg_aer_ecrc_gen_en; + wire [4:0]cfg_aer_interrupt_msgnum; + wire cfg_aer_rooterr_corr_err_received; + wire cfg_aer_rooterr_corr_err_reporting_en; + wire cfg_aer_rooterr_fatal_err_received; + wire cfg_aer_rooterr_fatal_err_reporting_en; + wire cfg_aer_rooterr_non_fatal_err_received; + wire cfg_aer_rooterr_non_fatal_err_reporting_en; + wire cfg_bridge_serr_en; + wire [7:0]cfg_bus_number; + wire [4:0]cfg_command; + wire [14:0]cfg_dcommand; + wire [11:0]cfg_dcommand2; + wire [4:0]cfg_device_number; + wire [7:0]cfg_ds_bus_number; + wire [4:0]cfg_ds_device_number; + wire [2:0]cfg_ds_function_number; + wire [63:0]cfg_dsn; + wire [3:0]cfg_dstatus; + wire [127:0]cfg_err_aer_headerlog; + wire cfg_err_aer_headerlog_set; + wire cfg_err_atomic_egress_blocked; + wire cfg_err_cor; + wire cfg_err_cpl_abort; + wire cfg_err_cpl_rdy; + wire cfg_err_cpl_timeout; + wire cfg_err_cpl_unexpect; + wire cfg_err_ecrc; + wire cfg_err_internal_cor; + wire cfg_err_internal_uncor; + wire cfg_err_locked; + wire cfg_err_malformed; + wire cfg_err_mc_blocked; + wire cfg_err_norecovery; + wire cfg_err_poisoned; + wire cfg_err_posted; + wire [47:0]cfg_err_tlp_cpl_header; + wire cfg_err_ur; + wire [2:0]cfg_function_number; + wire cfg_interrupt; + wire cfg_interrupt_assert; + wire [7:0]cfg_interrupt_di; + wire [7:0]cfg_interrupt_do; + wire [2:0]cfg_interrupt_mmenable; + wire cfg_interrupt_msienable; + wire cfg_interrupt_msixenable; + wire cfg_interrupt_msixfm; + wire cfg_interrupt_rdy; + wire cfg_interrupt_stat; + wire [10:0]cfg_lcommand; + wire [9:0]cfg_lstatus; + wire [3:0]cfg_mgmt_byte_en; + wire [31:0]cfg_mgmt_di; + wire [31:0]cfg_mgmt_do; + wire [9:0]cfg_mgmt_dwaddr; + wire cfg_mgmt_rd_en; + wire cfg_mgmt_rd_wr_done; + wire cfg_mgmt_wr_en; + wire cfg_mgmt_wr_readonly; + wire cfg_mgmt_wr_rw1c_as_rw; + wire [15:0]cfg_msg_data; + wire cfg_msg_received; + wire cfg_msg_received_assert_int_a; + wire cfg_msg_received_assert_int_b; + wire cfg_msg_received_assert_int_c; + wire cfg_msg_received_assert_int_d; + wire cfg_msg_received_deassert_int_a; + wire cfg_msg_received_deassert_int_b; + wire cfg_msg_received_deassert_int_c; + wire cfg_msg_received_deassert_int_d; + wire cfg_msg_received_err_cor; + wire cfg_msg_received_err_fatal; + wire cfg_msg_received_err_non_fatal; + wire cfg_msg_received_pm_as_nak; + wire cfg_msg_received_pm_pme; + wire cfg_msg_received_pme_to_ack; + wire cfg_msg_received_setslotpowerlimit; + wire [2:0]cfg_pcie_link_state; + wire [4:0]cfg_pciecap_interrupt_msgnum; + wire [1:0]cfg_pm_force_state; + wire cfg_pm_force_state_en; + wire cfg_pm_halt_aspm_l0s; + wire cfg_pm_halt_aspm_l1; + wire cfg_pm_wake; + wire cfg_pmcsr_pme_en; + wire cfg_pmcsr_pme_status; + wire [1:0]cfg_pmcsr_powerstate; + wire cfg_received_func_lvl_rst; + wire cfg_root_control_pme_int_en; + wire cfg_root_control_syserr_corr_err_en; + wire cfg_root_control_syserr_fatal_err_en; + wire cfg_root_control_syserr_non_fatal_err_en; + wire cfg_slot_control_electromech_il_ctl_pulse; + wire cfg_to_turnoff; + wire cfg_trn_pending; + wire cfg_turnoff_ok; + wire [6:0]cfg_vc_tcvc_map; + wire [11:0]fc_cpld; + wire [7:0]fc_cplh; + wire [11:0]fc_npd; + wire [7:0]fc_nph; + wire [11:0]fc_pd; + wire [7:0]fc_ph; + wire [2:0]fc_sel; + wire gen3_reg; + wire gt_rx_phy_status_q; + wire gt_rxelecidle_q; + wire gt_top_i_n_10; + wire gt_top_i_n_120; + wire gt_top_i_n_13; + wire gt_top_i_n_5; + wire gt_top_i_n_6; + wire gt_top_i_n_7; + wire gt_top_i_n_78; + wire gt_top_i_n_79; + wire gt_top_i_n_8; + wire gt_top_i_n_80; + wire gt_top_i_n_81; + wire gt_top_i_n_82; + wire gt_top_i_n_83; + wire gt_top_i_n_84; + wire gt_top_i_n_85; + wire gt_top_i_n_86; + wire gt_top_i_n_87; + wire gt_top_i_n_88; + wire gt_top_i_n_89; + wire gt_top_i_n_9; + wire \ltssm_reg1_reg[0]_srl2_n_0 ; + wire \ltssm_reg1_reg[1]_srl2_n_0 ; + wire \ltssm_reg1_reg[2]_srl2_n_0 ; + wire \ltssm_reg1_reg[3]_srl2_n_0 ; + wire \ltssm_reg1_reg[4]_srl2_n_0 ; + wire \ltssm_reg1_reg[5]_srl2_n_0 ; + wire [5:0]ltssm_reg2; + wire [63:0]m_axis_rx_tdata; + wire [0:0]m_axis_rx_tkeep; + wire m_axis_rx_tlast; + wire m_axis_rx_tready; + wire [12:0]m_axis_rx_tuser; + wire m_axis_rx_tvalid; + wire [3:0]pci_exp_rxn; + wire [3:0]pci_exp_rxp; + wire [3:0]pci_exp_txn; + wire [3:0]pci_exp_txp; + wire pcie_block_i_i_32_n_0; + wire pcie_block_i_i_33_n_0; + wire pcie_block_i_i_34_n_0; + wire pcie_block_i_i_35_n_0; + wire [8:0]pcie_drp_addr; + wire pcie_drp_clk; + wire [15:0]pcie_drp_di; + wire [15:0]pcie_drp_do; + wire pcie_drp_en; + wire pcie_drp_rdy; + wire pcie_drp_we; + wire pcie_top_i_n_20; + wire phy_rdy_n; + wire pipe_dclk_in; + wire pipe_mmcm_lock_in; + wire pipe_oobclk_in; + wire pipe_pclk_in; + wire [3:0]pipe_pclk_sel_out; + wire pipe_rx0_chanisaligned_gt; + wire [1:0]pipe_rx0_char_is_k_gt; + wire [15:0]pipe_rx0_data_gt; + wire pipe_rx0_polarity_gt; + wire pipe_rx0_valid_gt; + wire pipe_rx1_chanisaligned_gt; + wire [1:0]pipe_rx1_char_is_k_gt; + wire [15:0]pipe_rx1_data_gt; + wire pipe_rx1_polarity_gt; + wire pipe_rx1_valid_gt; + wire pipe_rx2_chanisaligned_gt; + wire [1:0]pipe_rx2_char_is_k_gt; + wire [15:0]pipe_rx2_data_gt; + wire pipe_rx2_polarity_gt; + wire pipe_rx2_valid_gt; + wire pipe_rx3_chanisaligned_gt; + wire [1:0]pipe_rx3_char_is_k_gt; + wire [15:0]pipe_rx3_data_gt; + wire pipe_rx3_polarity_gt; + wire pipe_rx3_valid_gt; + wire [3:0]pipe_rxoutclk_out; + wire pipe_rxusrclk_in; + wire [1:0]pipe_tx0_char_is_k_gt; + wire pipe_tx0_compliance_gt; + wire [15:0]pipe_tx0_data_gt; + wire pipe_tx0_elec_idle_gt; + wire [1:0]pipe_tx0_powerdown_gt; + wire [1:0]pipe_tx1_char_is_k_gt; + wire pipe_tx1_compliance_gt; + wire [15:0]pipe_tx1_data_gt; + wire pipe_tx1_elec_idle_gt; + wire [1:0]pipe_tx1_powerdown_gt; + wire [1:0]pipe_tx2_char_is_k_gt; + wire pipe_tx2_compliance_gt; + wire [15:0]pipe_tx2_data_gt; + wire pipe_tx2_elec_idle_gt; + wire [1:0]pipe_tx2_powerdown_gt; + wire [1:0]pipe_tx3_char_is_k_gt; + wire pipe_tx3_compliance_gt; + wire [15:0]pipe_tx3_data_gt; + wire pipe_tx3_elec_idle_gt; + wire [1:0]pipe_tx3_powerdown_gt; + wire pipe_tx_deemph_gt; + wire [2:0]pipe_tx_margin_gt; + wire pipe_tx_rate_gt; + wire pipe_tx_rcvr_det_gt; + wire pipe_txoutclk_out; + wire pipe_userclk1_in; + wire pipe_userclk2_in; + wire pl_directed_change_done; + wire pl_directed_link_auton; + wire [1:0]pl_directed_link_change; + wire pl_directed_link_speed; + wire [1:0]pl_directed_link_width; + wire pl_downstream_deemph_source; + wire [2:0]pl_initial_link_width; + wire [1:0]pl_lane_reversal_mode; + wire pl_link_gen2_cap; + wire pl_link_partner_gen2_supported; + wire pl_link_upcfg_cap; + wire [5:0]pl_ltssm_state; + wire pl_phy_lnk_up; + wire pl_phy_lnk_up_sync; + wire pl_phy_lnk_up_wire; + wire pl_received_hot_rst; + wire pl_received_hot_rst_sync; + wire pl_received_hot_rst_wire; + wire [1:0]pl_rx_pm_state; + wire pl_sel_lnk_rate; + wire [1:0]pl_sel_lnk_width; + wire pl_transmit_hot_rst; + wire [2:0]pl_tx_pm_state; + wire pl_upstream_prefer_deemph; + wire rx_np_ok; + wire rx_np_req; + wire [63:0]s_axis_tx_tdata; + wire [0:0]s_axis_tx_tkeep; + wire s_axis_tx_tlast; + wire s_axis_tx_tready; + wire [3:0]s_axis_tx_tuser; + wire s_axis_tx_tvalid; + (* DONT_TOUCH *) wire store_ltssm; + wire sys_clk; + wire sys_or_hot_rst; + wire sys_rst_n; + wire trn_lnk_up; + wire [5:0]tx_buf_av; + wire tx_cfg_gnt; + wire tx_cfg_req; + wire tx_err_drop; + (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire user_lnk_up_int; + (* async_reg = "true" *) wire user_lnk_up_mux; + wire user_reset_out; + + assign user_lnk_up = user_lnk_up_int; + LUT2 #( + .INIT(4'hE)) + \_inferred__0/store_ltssm_inferred_i_1 + (.I0(\_inferred__0/store_ltssm_inferred_i_2_n_0 ), + .I1(\_inferred__0/store_ltssm_inferred_i_3_n_0 ), + .O(store_ltssm)); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + \_inferred__0/store_ltssm_inferred_i_2 + (.I0(ltssm_reg2[0]), + .I1(pl_ltssm_state[0]), + .I2(pl_ltssm_state[2]), + .I3(ltssm_reg2[2]), + .I4(pl_ltssm_state[1]), + .I5(ltssm_reg2[1]), + .O(\_inferred__0/store_ltssm_inferred_i_2_n_0 )); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + \_inferred__0/store_ltssm_inferred_i_3 + (.I0(ltssm_reg2[3]), + .I1(pl_ltssm_state[3]), + .I2(pl_ltssm_state[5]), + .I3(ltssm_reg2[5]), + .I4(pl_ltssm_state[4]), + .I5(ltssm_reg2[4]), + .O(\_inferred__0/store_ltssm_inferred_i_3_n_0 )); + pcie_7x_0_pcie_7x_0_gt_top gt_top_i + (.D(pipe_rx0_char_is_k_gt), + .PIPE_POWERDOWN({pipe_tx3_powerdown_gt,pipe_tx2_powerdown_gt,pipe_tx1_powerdown_gt,pipe_tx0_powerdown_gt}), + .PIPE_RXCHANISALIGNED({pipe_rx3_chanisaligned_gt,pipe_rx2_chanisaligned_gt,pipe_rx1_chanisaligned_gt,pipe_rx0_chanisaligned_gt}), + .PIPE_RXPOLARITY({pipe_rx3_polarity_gt,pipe_rx2_polarity_gt,pipe_rx1_polarity_gt,pipe_rx0_polarity_gt}), + .PIPE_TXCOMPLIANCE({pipe_tx3_compliance_gt,pipe_tx2_compliance_gt,pipe_tx1_compliance_gt,pipe_tx0_compliance_gt}), + .PIPE_TXDATA({pipe_tx3_data_gt,pipe_tx2_data_gt,pipe_tx1_data_gt,pipe_tx0_data_gt}), + .PIPE_TXDATAK({pipe_tx3_char_is_k_gt,pipe_tx2_char_is_k_gt,pipe_tx1_char_is_k_gt,pipe_tx0_char_is_k_gt}), + .PIPE_TXELECIDLE({pipe_tx3_elec_idle_gt,pipe_tx2_elec_idle_gt,pipe_tx1_elec_idle_gt,pipe_tx0_elec_idle_gt}), + .Q(pipe_rx0_data_gt), + .USER_RATE_GEN3(gen3_reg), + .\cplllock_reg1_reg[3] (pipe_tx_margin_gt), + .gt_rx_phy_status_q(gt_rx_phy_status_q), + .gt_rx_phy_status_q_reg(gt_top_i_n_5), + .gt_rx_phy_status_q_reg_0(gt_top_i_n_7), + .gt_rx_phy_status_q_reg_1(gt_top_i_n_9), + .\gt_rx_status_q_reg[2] ({gt_top_i_n_78,gt_top_i_n_79,gt_top_i_n_80}), + .\gt_rx_status_q_reg[2]_0 ({gt_top_i_n_81,gt_top_i_n_82,gt_top_i_n_83}), + .\gt_rx_status_q_reg[2]_1 ({gt_top_i_n_84,gt_top_i_n_85,gt_top_i_n_86}), + .\gt_rx_status_q_reg[2]_2 ({gt_top_i_n_87,gt_top_i_n_88,gt_top_i_n_89}), + .\gt_rxdata_q_reg[15] (pipe_rx1_data_gt), + .\gt_rxdata_q_reg[15]_0 (pipe_rx2_data_gt), + .\gt_rxdata_q_reg[15]_1 (pipe_rx3_data_gt), + .gt_rxelecidle_q(gt_rxelecidle_q), + .gt_rxelecidle_q_reg(gt_top_i_n_6), + .gt_rxelecidle_q_reg_0(gt_top_i_n_8), + .gt_rxelecidle_q_reg_1(gt_top_i_n_10), + .gt_rxvalid_q_reg(pipe_rx1_char_is_k_gt), + .gt_rxvalid_q_reg_0(pipe_rx2_char_is_k_gt), + .gt_rxvalid_q_reg_1(pipe_rx3_char_is_k_gt), + .pci_exp_rxn(pci_exp_rxn), + .pci_exp_rxp(pci_exp_rxp), + .pci_exp_txn(pci_exp_txn), + .pci_exp_txp(pci_exp_txp), + .phy_rdy_n(phy_rdy_n), + .pipe_dclk_in(pipe_dclk_in), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_oobclk_in(pipe_oobclk_in), + .pipe_pclk_in(pipe_pclk_in), + .pipe_pclk_sel_out(pipe_pclk_sel_out), + .pipe_rx0_valid_gt(pipe_rx0_valid_gt), + .pipe_rx1_valid_gt(pipe_rx1_valid_gt), + .pipe_rx2_valid_gt(pipe_rx2_valid_gt), + .pipe_rx3_valid_gt(pipe_rx3_valid_gt), + .pipe_rxoutclk_out(pipe_rxoutclk_out), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .pipe_tx_deemph_gt(pipe_tx_deemph_gt), + .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt), + .pipe_txoutclk_out(pipe_txoutclk_out), + .pl_ltssm_state(pl_ltssm_state), + .\rate_reg1_reg[0] (pipe_tx_rate_gt), + .reset_n_reg1_reg(sys_rst_n), + .sys_clk(sys_clk), + .sys_rst_n(gt_top_i_n_13), + .sys_rst_n_0(gt_top_i_n_120)); + (* srl_bus_name = "inst/\inst/ltssm_reg1_reg " *) + (* srl_name = "inst/\inst/ltssm_reg1_reg[0]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \ltssm_reg1_reg[0]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(1'b1), + .CLK(pipe_pclk_in), + .D(pl_ltssm_state[0]), + .Q(\ltssm_reg1_reg[0]_srl2_n_0 )); + (* srl_bus_name = "inst/\inst/ltssm_reg1_reg " *) + (* srl_name = "inst/\inst/ltssm_reg1_reg[1]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \ltssm_reg1_reg[1]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(1'b1), + .CLK(pipe_pclk_in), + .D(pl_ltssm_state[1]), + .Q(\ltssm_reg1_reg[1]_srl2_n_0 )); + (* srl_bus_name = "inst/\inst/ltssm_reg1_reg " *) + (* srl_name = "inst/\inst/ltssm_reg1_reg[2]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \ltssm_reg1_reg[2]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(1'b1), + .CLK(pipe_pclk_in), + .D(pl_ltssm_state[2]), + .Q(\ltssm_reg1_reg[2]_srl2_n_0 )); + (* srl_bus_name = "inst/\inst/ltssm_reg1_reg " *) + (* srl_name = "inst/\inst/ltssm_reg1_reg[3]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \ltssm_reg1_reg[3]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(1'b1), + .CLK(pipe_pclk_in), + .D(pl_ltssm_state[3]), + .Q(\ltssm_reg1_reg[3]_srl2_n_0 )); + (* srl_bus_name = "inst/\inst/ltssm_reg1_reg " *) + (* srl_name = "inst/\inst/ltssm_reg1_reg[4]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \ltssm_reg1_reg[4]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(1'b1), + .CLK(pipe_pclk_in), + .D(pl_ltssm_state[4]), + .Q(\ltssm_reg1_reg[4]_srl2_n_0 )); + (* srl_bus_name = "inst/\inst/ltssm_reg1_reg " *) + (* srl_name = "inst/\inst/ltssm_reg1_reg[5]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \ltssm_reg1_reg[5]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(1'b1), + .CLK(pipe_pclk_in), + .D(pl_ltssm_state[5]), + .Q(\ltssm_reg1_reg[5]_srl2_n_0 )); + FDRE #( + .INIT(1'b0)) + \ltssm_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\ltssm_reg1_reg[0]_srl2_n_0 ), + .Q(ltssm_reg2[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \ltssm_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\ltssm_reg1_reg[1]_srl2_n_0 ), + .Q(ltssm_reg2[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \ltssm_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\ltssm_reg1_reg[2]_srl2_n_0 ), + .Q(ltssm_reg2[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \ltssm_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\ltssm_reg1_reg[3]_srl2_n_0 ), + .Q(ltssm_reg2[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \ltssm_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\ltssm_reg1_reg[4]_srl2_n_0 ), + .Q(ltssm_reg2[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \ltssm_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\ltssm_reg1_reg[5]_srl2_n_0 ), + .Q(ltssm_reg2[5]), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_32 + (.I0(cfg_mgmt_byte_en[3]), + .O(pcie_block_i_i_32_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_33 + (.I0(cfg_mgmt_byte_en[2]), + .O(pcie_block_i_i_33_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_34 + (.I0(cfg_mgmt_byte_en[1]), + .O(pcie_block_i_i_34_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_35 + (.I0(cfg_mgmt_byte_en[0]), + .O(pcie_block_i_i_35_n_0)); + pcie_7x_0_pcie_7x_0_pcie_top pcie_top_i + (.D(pipe_rx1_char_is_k_gt), + .PIPE_POWERDOWN({pipe_tx3_powerdown_gt,pipe_tx2_powerdown_gt,pipe_tx1_powerdown_gt,pipe_tx0_powerdown_gt}), + .PIPE_RXCHANISALIGNED({pipe_rx3_chanisaligned_gt,pipe_rx2_chanisaligned_gt,pipe_rx1_chanisaligned_gt,pipe_rx0_chanisaligned_gt}), + .PIPE_RXPOLARITY({pipe_rx3_polarity_gt,pipe_rx2_polarity_gt,pipe_rx1_polarity_gt,pipe_rx0_polarity_gt}), + .PIPE_TXCOMPLIANCE({pipe_tx3_compliance_gt,pipe_tx2_compliance_gt,pipe_tx1_compliance_gt,pipe_tx0_compliance_gt}), + .PIPE_TXDATA({pipe_tx3_data_gt,pipe_tx2_data_gt,pipe_tx1_data_gt,pipe_tx0_data_gt}), + .PIPE_TXDATAK({pipe_tx3_char_is_k_gt,pipe_tx2_char_is_k_gt,pipe_tx1_char_is_k_gt,pipe_tx0_char_is_k_gt}), + .PIPE_TXELECIDLE({pipe_tx3_elec_idle_gt,pipe_tx2_elec_idle_gt,pipe_tx1_elec_idle_gt,pipe_tx0_elec_idle_gt}), + .Q(pipe_tx_margin_gt), + .SR(phy_rdy_n), + .bridge_reset_int(bridge_reset_int), + .cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en), + .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en), + .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum), + .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received), + .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en), + .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received), + .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en), + .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received), + .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en), + .cfg_bridge_serr_en(cfg_bridge_serr_en), + .cfg_bus_number(cfg_bus_number), + .cfg_command(cfg_command), + .cfg_dcommand(cfg_dcommand), + .cfg_dcommand2(cfg_dcommand2), + .cfg_device_number(cfg_device_number), + .cfg_ds_bus_number(cfg_ds_bus_number), + .cfg_ds_device_number(cfg_ds_device_number), + .cfg_ds_function_number(cfg_ds_function_number), + .cfg_dsn(cfg_dsn), + .cfg_dstatus(cfg_dstatus), + .cfg_err_aer_headerlog(cfg_err_aer_headerlog), + .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set), + .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked), + .cfg_err_cor(cfg_err_cor), + .cfg_err_cpl_abort(cfg_err_cpl_abort), + .cfg_err_cpl_rdy(cfg_err_cpl_rdy), + .cfg_err_cpl_timeout(cfg_err_cpl_timeout), + .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect), + .cfg_err_ecrc(cfg_err_ecrc), + .cfg_err_internal_cor(cfg_err_internal_cor), + .cfg_err_internal_uncor(cfg_err_internal_uncor), + .cfg_err_locked(cfg_err_locked), + .cfg_err_malformed(cfg_err_malformed), + .cfg_err_mc_blocked(cfg_err_mc_blocked), + .cfg_err_norecovery(cfg_err_norecovery), + .cfg_err_poisoned(cfg_err_poisoned), + .cfg_err_posted(cfg_err_posted), + .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header), + .cfg_err_ur(cfg_err_ur), + .cfg_function_number(cfg_function_number), + .cfg_interrupt(cfg_interrupt), + .cfg_interrupt_assert(cfg_interrupt_assert), + .cfg_interrupt_di(cfg_interrupt_di), + .cfg_interrupt_do(cfg_interrupt_do), + .cfg_interrupt_mmenable(cfg_interrupt_mmenable), + .cfg_interrupt_msienable(cfg_interrupt_msienable), + .cfg_interrupt_msixenable(cfg_interrupt_msixenable), + .cfg_interrupt_msixfm(cfg_interrupt_msixfm), + .cfg_interrupt_rdy(cfg_interrupt_rdy), + .cfg_interrupt_stat(cfg_interrupt_stat), + .cfg_lcommand(cfg_lcommand), + .cfg_lstatus(cfg_lstatus), + .cfg_mgmt_byte_en_n({pcie_block_i_i_32_n_0,pcie_block_i_i_33_n_0,pcie_block_i_i_34_n_0,pcie_block_i_i_35_n_0}), + .cfg_mgmt_di(cfg_mgmt_di), + .cfg_mgmt_do(cfg_mgmt_do), + .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr), + .cfg_mgmt_rd_en(cfg_mgmt_rd_en), + .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done), + .cfg_mgmt_wr_en(cfg_mgmt_wr_en), + .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly), + .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw), + .cfg_msg_data(cfg_msg_data), + .cfg_msg_received(cfg_msg_received), + .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a), + .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b), + .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c), + .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d), + .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a), + .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b), + .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c), + .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d), + .cfg_msg_received_err_cor(cfg_msg_received_err_cor), + .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal), + .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal), + .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak), + .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme), + .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack), + .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit), + .cfg_pcie_link_state(cfg_pcie_link_state), + .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum), + .cfg_pm_force_state(cfg_pm_force_state), + .cfg_pm_force_state_en(cfg_pm_force_state_en), + .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s), + .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1), + .cfg_pm_wake(cfg_pm_wake), + .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en), + .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status), + .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate), + .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst), + .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en), + .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en), + .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en), + .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en), + .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse), + .cfg_to_turnoff(cfg_to_turnoff), + .cfg_trn_pending(cfg_trn_pending), + .cfg_turnoff_ok(cfg_turnoff_ok), + .cfg_vc_tcvc_map(cfg_vc_tcvc_map), + .fc_cpld(fc_cpld), + .fc_cplh(fc_cplh), + .fc_npd(fc_npd), + .fc_nph(fc_nph), + .fc_pd(fc_pd), + .fc_ph(fc_ph), + .fc_sel(fc_sel), + .gt_rx_phy_status_q(gt_rx_phy_status_q), + .gt_rxelecidle_q(gt_rxelecidle_q), + .m_axis_rx_tdata(m_axis_rx_tdata), + .m_axis_rx_tkeep(m_axis_rx_tkeep), + .m_axis_rx_tlast(m_axis_rx_tlast), + .m_axis_rx_tready(m_axis_rx_tready), + .m_axis_rx_tuser(m_axis_rx_tuser), + .m_axis_rx_tvalid_reg(m_axis_rx_tvalid), + .out(user_lnk_up_int), + .pcie_drp_addr(pcie_drp_addr), + .pcie_drp_clk(pcie_drp_clk), + .pcie_drp_di(pcie_drp_di), + .pcie_drp_do(pcie_drp_do), + .pcie_drp_en(pcie_drp_en), + .pcie_drp_rdy(pcie_drp_rdy), + .pcie_drp_we(pcie_drp_we), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rx0_valid_gt(pipe_rx0_valid_gt), + .pipe_rx1_valid_gt(pipe_rx1_valid_gt), + .pipe_rx2_valid_gt(pipe_rx2_valid_gt), + .pipe_rx3_valid_gt(pipe_rx3_valid_gt), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (pipe_rx2_char_is_k_gt), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 (pipe_rx3_char_is_k_gt), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 (pipe_rx0_char_is_k_gt), + .\pipe_stages_1.pipe_rx_data_q_reg[15] (pipe_rx1_data_gt), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_0 (pipe_rx2_data_gt), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_1 (pipe_rx3_data_gt), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_2 (pipe_rx0_data_gt), + .\pipe_stages_1.pipe_rx_elec_idle_q_reg (gt_top_i_n_6), + .\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 (gt_top_i_n_8), + .\pipe_stages_1.pipe_rx_elec_idle_q_reg_1 (gt_top_i_n_10), + .\pipe_stages_1.pipe_rx_phy_status_q_reg (gt_top_i_n_5), + .\pipe_stages_1.pipe_rx_phy_status_q_reg_0 (gt_top_i_n_7), + .\pipe_stages_1.pipe_rx_phy_status_q_reg_1 (gt_top_i_n_9), + .\pipe_stages_1.pipe_rx_status_q_reg[2] ({gt_top_i_n_78,gt_top_i_n_79,gt_top_i_n_80}), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ({gt_top_i_n_81,gt_top_i_n_82,gt_top_i_n_83}), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ({gt_top_i_n_84,gt_top_i_n_85,gt_top_i_n_86}), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ({gt_top_i_n_87,gt_top_i_n_88,gt_top_i_n_89}), + .\pipe_stages_1.pipe_tx_rate_q_reg (pipe_tx_rate_gt), + .pipe_tx_deemph_gt(pipe_tx_deemph_gt), + .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt), + .pipe_userclk1_in(pipe_userclk1_in), + .pipe_userclk2_in(pipe_userclk2_in), + .pl_directed_change_done(pl_directed_change_done), + .pl_directed_link_auton(pl_directed_link_auton), + .pl_directed_link_change(pl_directed_link_change), + .pl_directed_link_speed(pl_directed_link_speed), + .pl_directed_link_width(pl_directed_link_width), + .pl_downstream_deemph_source(pl_downstream_deemph_source), + .pl_initial_link_width(pl_initial_link_width), + .pl_lane_reversal_mode(pl_lane_reversal_mode), + .pl_link_gen2_cap(pl_link_gen2_cap), + .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported), + .pl_link_upcfg_cap(pl_link_upcfg_cap), + .pl_ltssm_state(pl_ltssm_state), + .pl_phy_lnk_up(pl_phy_lnk_up), + .pl_received_hot_rst(pl_received_hot_rst_wire), + .pl_rx_pm_state(pl_rx_pm_state), + .pl_sel_lnk_rate(pl_sel_lnk_rate), + .pl_sel_lnk_width(pl_sel_lnk_width), + .pl_transmit_hot_rst(pl_transmit_hot_rst), + .pl_tx_pm_state(pl_tx_pm_state), + .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph), + .rx_np_ok(rx_np_ok), + .rx_np_req(rx_np_req), + .s_axis_tx_tdata(s_axis_tx_tdata), + .s_axis_tx_tkeep(s_axis_tx_tkeep), + .s_axis_tx_tlast(s_axis_tx_tlast), + .s_axis_tx_tuser(s_axis_tx_tuser), + .s_axis_tx_tvalid(s_axis_tx_tvalid), + .src_in(pl_phy_lnk_up_wire), + .sys_rst_n(gt_top_i_n_13), + .\throttle_ctl_pipeline.reg_tkeep_reg[7] (user_reset_out), + .tready_thrtl_reg(s_axis_tx_tready), + .trn_lnk_up(trn_lnk_up), + .trn_tbuf_av(tx_buf_av), + .trn_tcfg_req(tx_cfg_req), + .tx_cfg_gnt(tx_cfg_gnt), + .tx_err_drop(tx_err_drop), + .user_reset_int_reg(pcie_top_i_n_20)); + (* DEST_SYNC_FF = "2" *) + (* INIT_SYNC_FF = "0" *) + (* SIM_ASSERT_CHK = "0" *) + (* SRC_INPUT_REG = "0" *) + (* VERSION = "0" *) + (* XPM_CDC = "SINGLE" *) + (* XPM_MODULE = "TRUE" *) + pcie_7x_0_xpm_cdc_single__2 phy_lnk_up_cdc + (.dest_clk(pipe_userclk2_in), + .dest_out(pl_phy_lnk_up_sync), + .src_clk(1'b0), + .src_in(pl_phy_lnk_up_wire)); + FDRE pl_phy_lnk_up_q_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(pl_phy_lnk_up_sync), + .Q(pl_phy_lnk_up), + .R(gt_top_i_n_120)); + (* DEST_SYNC_FF = "2" *) + (* INIT_SYNC_FF = "0" *) + (* SIM_ASSERT_CHK = "0" *) + (* SRC_INPUT_REG = "0" *) + (* VERSION = "0" *) + (* XPM_CDC = "SINGLE" *) + (* XPM_MODULE = "TRUE" *) + pcie_7x_0_xpm_cdc_single pl_received_hot_rst_cdc + (.dest_clk(pipe_userclk2_in), + .dest_out(pl_received_hot_rst_sync), + .src_clk(1'b0), + .src_in(pl_received_hot_rst_wire)); + FDRE pl_received_hot_rst_q_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(pl_received_hot_rst_sync), + .Q(pl_received_hot_rst), + .R(gt_top_i_n_120)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE user_lnk_up_int_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(trn_lnk_up), + .Q(user_lnk_up_int), + .R(gt_top_i_n_120)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE user_lnk_up_mux_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(user_lnk_up_int), + .Q(user_lnk_up_mux), + .R(gt_top_i_n_120)); + FDPE user_reset_int_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(pcie_top_i_n_20), + .PRE(sys_or_hot_rst), + .Q(bridge_reset_int)); + LUT2 #( + .INIT(4'hB)) + user_reset_out_i_1 + (.I0(pl_received_hot_rst), + .I1(sys_rst_n), + .O(sys_or_hot_rst)); + FDPE user_reset_out_reg + (.C(pipe_userclk2_in), + .CE(1'b1), + .D(bridge_reset_int), + .PRE(sys_or_hot_rst), + .Q(user_reset_out)); +endmodule + +module pcie_7x_0_pcie_7x_0_gt_common + (QPLL_QPLLLOCK, + QPLL_QPLLOUTCLK, + QPLL_QPLLOUTREFCLK, + QPLL_DRP_DONE, + RST_DCLK_RESET, + pipe_dclk_in, + sys_clk, + QPLL_QPLLPD, + QPLL_QPLLRESET, + QRST_DRP_START, + QPLL_DRP_GEN3); + output QPLL_QPLLLOCK; + output QPLL_QPLLOUTCLK; + output QPLL_QPLLOUTREFCLK; + output QPLL_DRP_DONE; + input RST_DCLK_RESET; + input pipe_dclk_in; + input sys_clk; + input QPLL_QPLLPD; + input QPLL_QPLLRESET; + input QRST_DRP_START; + input QPLL_DRP_GEN3; + + wire QPLL_DRP_DONE; + wire QPLL_DRP_GEN3; + wire QPLL_QPLLLOCK; + wire QPLL_QPLLOUTCLK; + wire QPLL_QPLLOUTREFCLK; + wire QPLL_QPLLPD; + wire QPLL_QPLLRESET; + wire QRST_DRP_START; + wire RST_DCLK_RESET; + wire pipe_dclk_in; + wire [7:0]qpll_drp_addr; + wire [15:0]qpll_drp_di; + wire [15:0]qpll_drp_do; + wire qpll_drp_en; + wire qpll_drp_rdy; + wire qpll_drp_we; + wire sys_clk; + + pcie_7x_0_pcie_7x_0_qpll_drp qpll_drp_i + (.D(qpll_drp_do), + .Q({qpll_drp_addr[7],qpll_drp_addr[5],qpll_drp_addr[2:0]}), + .QPLL_DRP_DONE(QPLL_DRP_DONE), + .QPLL_DRP_GEN3(QPLL_DRP_GEN3), + .QPLL_QPLLLOCK(QPLL_QPLLLOCK), + .QRST_DRP_START(QRST_DRP_START), + .RST_DCLK_RESET(RST_DCLK_RESET), + .\di_reg[15]_0 (qpll_drp_di), + .pipe_dclk_in(pipe_dclk_in), + .qpll_drp_en(qpll_drp_en), + .qpll_drp_rdy(qpll_drp_rdy), + .qpll_drp_we(qpll_drp_we)); + pcie_7x_0_pcie_7x_0_qpll_wrapper qpll_wrapper_i + (.D(qpll_drp_do), + .Q({qpll_drp_addr[7],qpll_drp_addr[5],qpll_drp_addr[2:0]}), + .QPLL_QPLLLOCK(QPLL_QPLLLOCK), + .QPLL_QPLLOUTCLK(QPLL_QPLLOUTCLK), + .QPLL_QPLLOUTREFCLK(QPLL_QPLLOUTREFCLK), + .QPLL_QPLLPD(QPLL_QPLLPD), + .QPLL_QPLLRESET(QPLL_QPLLRESET), + .pipe_dclk_in(pipe_dclk_in), + .qpll_drp_en(qpll_drp_en), + .qpll_drp_rdy(qpll_drp_rdy), + .qpll_drp_we(qpll_drp_we), + .rdy_reg1_reg(qpll_drp_di), + .sys_clk(sys_clk)); +endmodule + +module pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x + (gt_rxvalid_q_reg_0, + gt_rx_phy_status_q, + gt_rxelecidle_q, + \pl_ltssm_state_q_reg[5] , + Q, + D, + \gt_rx_status_q_reg[2]_0 , + SR, + pipe_pclk_in, + gt_rx_phy_status_wire_filter, + PIPE_RXELECIDLE, + gt_rxvalid_q_reg_1, + PIPE_RXSTATUS, + \gt_rx_status_q_reg[0]_0 , + PIPE_RXDATAK, + PIPE_RXDATA); + output gt_rxvalid_q_reg_0; + output gt_rx_phy_status_q; + output gt_rxelecidle_q; + output \pl_ltssm_state_q_reg[5] ; + output [15:0]Q; + output [1:0]D; + output [2:0]\gt_rx_status_q_reg[2]_0 ; + input [0:0]SR; + input pipe_pclk_in; + input [0:0]gt_rx_phy_status_wire_filter; + input [0:0]PIPE_RXELECIDLE; + input gt_rxvalid_q_reg_1; + input [2:0]PIPE_RXSTATUS; + input [5:0]\gt_rx_status_q_reg[0]_0 ; + input [1:0]PIPE_RXDATAK; + input [15:0]PIPE_RXDATA; + + wire [1:0]D; + wire [15:0]PIPE_RXDATA; + wire [1:0]PIPE_RXDATAK; + wire [0:0]PIPE_RXELECIDLE; + wire [2:0]PIPE_RXSTATUS; + wire [15:0]Q; + wire [0:0]SR; + wire gt_rx_phy_status_q; + wire [0:0]gt_rx_phy_status_wire_filter; + wire \gt_rx_status_q[0]_i_1__2_n_0 ; + wire \gt_rx_status_q[1]_i_1__2_n_0 ; + wire \gt_rx_status_q[2]_i_1__2_n_0 ; + wire [5:0]\gt_rx_status_q_reg[0]_0 ; + wire [2:0]\gt_rx_status_q_reg[2]_0 ; + wire \gt_rxcharisk_q_reg_n_0_[0] ; + wire gt_rxelecidle_q; + wire gt_rxvalid_q__0; + wire gt_rxvalid_q_i_2_n_0; + wire gt_rxvalid_q_n_0; + wire gt_rxvalid_q_reg_0; + wire gt_rxvalid_q_reg_1; + wire p_1_in; + wire [4:0]p_1_in__0; + wire pipe_pclk_in; + wire \pl_ltssm_state_q_reg[5] ; + wire \reg_state_eios_det[0]_i_2_n_0 ; + wire \reg_state_eios_det[0]_i_3_n_0 ; + wire \reg_state_eios_det[0]_i_4_n_0 ; + wire \reg_state_eios_det[0]_i_5_n_0 ; + wire \reg_state_eios_det[1]_i_2_n_0 ; + wire \reg_state_eios_det[1]_i_3_n_0 ; + wire \reg_state_eios_det[2]_i_2_n_0 ; + wire \reg_state_eios_det[2]_i_3_n_0 ; + wire \reg_state_eios_det[3]_i_2_n_0 ; + wire \reg_state_eios_det[4]_i_1_n_0 ; + wire \reg_state_eios_det[4]_i_3_n_0 ; + wire reg_symbol_after_eios; + wire reg_symbol_after_eios_i_2_n_0; + wire [4:0]state_eios_det; + wire symbol_after_eios; + + FDRE gt_rx_phy_status_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rx_phy_status_wire_filter), + .Q(gt_rx_phy_status_q), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'hE0)) + \gt_rx_status_q[0]_i_1__2 + (.I0(gt_rxvalid_q_reg_0), + .I1(\pl_ltssm_state_q_reg[5] ), + .I2(PIPE_RXSTATUS[0]), + .O(\gt_rx_status_q[0]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'hE0)) + \gt_rx_status_q[1]_i_1__2 + (.I0(gt_rxvalid_q_reg_0), + .I1(\pl_ltssm_state_q_reg[5] ), + .I2(PIPE_RXSTATUS[1]), + .O(\gt_rx_status_q[1]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'hE0)) + \gt_rx_status_q[2]_i_1__2 + (.I0(gt_rxvalid_q_reg_0), + .I1(\pl_ltssm_state_q_reg[5] ), + .I2(PIPE_RXSTATUS[2]), + .O(\gt_rx_status_q[2]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFBFFFFFF)) + \gt_rx_status_q[2]_i_2 + (.I0(\gt_rx_status_q_reg[0]_0 [5]), + .I1(\gt_rx_status_q_reg[0]_0 [4]), + .I2(\gt_rx_status_q_reg[0]_0 [3]), + .I3(\gt_rx_status_q_reg[0]_0 [2]), + .I4(\gt_rx_status_q_reg[0]_0 [1]), + .I5(\gt_rx_status_q_reg[0]_0 [0]), + .O(\pl_ltssm_state_q_reg[5] )); + FDRE \gt_rx_status_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\gt_rx_status_q[0]_i_1__2_n_0 ), + .Q(\gt_rx_status_q_reg[2]_0 [0]), + .R(SR)); + FDRE \gt_rx_status_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\gt_rx_status_q[1]_i_1__2_n_0 ), + .Q(\gt_rx_status_q_reg[2]_0 [1]), + .R(SR)); + FDRE \gt_rx_status_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\gt_rx_status_q[2]_i_1__2_n_0 ), + .Q(\gt_rx_status_q_reg[2]_0 [2]), + .R(SR)); + FDRE \gt_rxcharisk_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATAK[0]), + .Q(\gt_rxcharisk_q_reg_n_0_[0] ), + .R(SR)); + FDRE \gt_rxcharisk_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATAK[1]), + .Q(p_1_in), + .R(SR)); + FDRE \gt_rxdata_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[0]), + .Q(Q[0]), + .R(SR)); + FDRE \gt_rxdata_q_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[10]), + .Q(Q[10]), + .R(SR)); + FDRE \gt_rxdata_q_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[11]), + .Q(Q[11]), + .R(SR)); + FDRE \gt_rxdata_q_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[12]), + .Q(Q[12]), + .R(SR)); + FDRE \gt_rxdata_q_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[13]), + .Q(Q[13]), + .R(SR)); + FDRE \gt_rxdata_q_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[14]), + .Q(Q[14]), + .R(SR)); + FDRE \gt_rxdata_q_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[15]), + .Q(Q[15]), + .R(SR)); + FDRE \gt_rxdata_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[1]), + .Q(Q[1]), + .R(SR)); + FDRE \gt_rxdata_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[2]), + .Q(Q[2]), + .R(SR)); + FDRE \gt_rxdata_q_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[3]), + .Q(Q[3]), + .R(SR)); + FDRE \gt_rxdata_q_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[4]), + .Q(Q[4]), + .R(SR)); + FDRE \gt_rxdata_q_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[5]), + .Q(Q[5]), + .R(SR)); + FDRE \gt_rxdata_q_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[6]), + .Q(Q[6]), + .R(SR)); + FDRE \gt_rxdata_q_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[7]), + .Q(Q[7]), + .R(SR)); + FDRE \gt_rxdata_q_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[8]), + .Q(Q[8]), + .R(SR)); + FDRE \gt_rxdata_q_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[9]), + .Q(Q[9]), + .R(SR)); + FDRE gt_rxelecidle_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXELECIDLE), + .Q(gt_rxelecidle_q), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h00010116)) + gt_rxvalid_q + (.I0(state_eios_det[0]), + .I1(state_eios_det[1]), + .I2(state_eios_det[2]), + .I3(state_eios_det[3]), + .I4(state_eios_det[4]), + .O(gt_rxvalid_q_n_0)); + LUT5 #( + .INIT(32'hFFAAEAAA)) + gt_rxvalid_q_i_1 + (.I0(gt_rxvalid_q_i_2_n_0), + .I1(state_eios_det[2]), + .I2(\reg_state_eios_det[3]_i_2_n_0 ), + .I3(gt_rxvalid_q_reg_1), + .I4(state_eios_det[0]), + .O(gt_rxvalid_q__0)); + LUT6 #( + .INIT(64'hFFF50000CC550000)) + gt_rxvalid_q_i_2 + (.I0(gt_rxvalid_q_n_0), + .I1(\pl_ltssm_state_q_reg[5] ), + .I2(\reg_state_eios_det[4]_i_3_n_0 ), + .I3(state_eios_det[4]), + .I4(gt_rxvalid_q_reg_1), + .I5(\reg_state_eios_det[0]_i_3_n_0 ), + .O(gt_rxvalid_q_i_2_n_0)); + FDRE gt_rxvalid_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rxvalid_q__0), + .Q(gt_rxvalid_q_reg_0), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h8)) + \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1 + (.I0(gt_rxvalid_q_reg_0), + .I1(\gt_rxcharisk_q_reg_n_0_[0] ), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h08)) + \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1 + (.I0(gt_rxvalid_q_reg_0), + .I1(p_1_in), + .I2(symbol_after_eios), + .O(D[1])); + LUT6 #( + .INIT(64'hFFFFFFFFFEFEFEEE)) + \reg_state_eios_det[0]_i_1 + (.I0(state_eios_det[4]), + .I1(\reg_state_eios_det[0]_i_2_n_0 ), + .I2(\reg_state_eios_det[1]_i_2_n_0 ), + .I3(\reg_state_eios_det[0]_i_3_n_0 ), + .I4(\reg_state_eios_det[0]_i_4_n_0 ), + .I5(\reg_state_eios_det[0]_i_5_n_0 ), + .O(p_1_in__0[0])); + LUT6 #( + .INIT(64'hFFF3AAFFAA00AAAA)) + \reg_state_eios_det[0]_i_2 + (.I0(state_eios_det[2]), + .I1(Q[7]), + .I2(Q[6]), + .I3(Q[15]), + .I4(Q[14]), + .I5(state_eios_det[0]), + .O(\reg_state_eios_det[0]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'hFE)) + \reg_state_eios_det[0]_i_3 + (.I0(state_eios_det[3]), + .I1(state_eios_det[1]), + .I2(state_eios_det[2]), + .O(\reg_state_eios_det[0]_i_3_n_0 )); + LUT2 #( + .INIT(4'h8)) + \reg_state_eios_det[0]_i_4 + (.I0(Q[14]), + .I1(state_eios_det[0]), + .O(\reg_state_eios_det[0]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFE0E0E0FFE0FFE0)) + \reg_state_eios_det[0]_i_5 + (.I0(state_eios_det[0]), + .I1(state_eios_det[2]), + .I2(\reg_state_eios_det[2]_i_2_n_0 ), + .I3(\reg_state_eios_det[0]_i_3_n_0 ), + .I4(Q[7]), + .I5(Q[6]), + .O(\reg_state_eios_det[0]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00000040)) + \reg_state_eios_det[1]_i_1 + (.I0(\reg_state_eios_det[1]_i_2_n_0 ), + .I1(state_eios_det[0]), + .I2(Q[7]), + .I3(Q[6]), + .I4(\reg_state_eios_det[3]_i_2_n_0 ), + .O(p_1_in__0[1])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'hBFFF)) + \reg_state_eios_det[1]_i_2 + (.I0(\reg_state_eios_det[1]_i_3_n_0 ), + .I1(\gt_rxcharisk_q_reg_n_0_[0] ), + .I2(Q[4]), + .I3(Q[5]), + .O(\reg_state_eios_det[1]_i_2_n_0 )); + LUT4 #( + .INIT(16'hEFFF)) + \reg_state_eios_det[1]_i_3 + (.I0(Q[1]), + .I1(Q[0]), + .I2(Q[3]), + .I3(Q[2]), + .O(\reg_state_eios_det[1]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h0040)) + \reg_state_eios_det[2]_i_1 + (.I0(Q[14]), + .I1(Q[15]), + .I2(state_eios_det[0]), + .I3(\reg_state_eios_det[2]_i_2_n_0 ), + .O(p_1_in__0[2])); + LUT4 #( + .INIT(16'hBFFF)) + \reg_state_eios_det[2]_i_2 + (.I0(\reg_state_eios_det[2]_i_3_n_0 ), + .I1(p_1_in), + .I2(Q[12]), + .I3(Q[13]), + .O(\reg_state_eios_det[2]_i_2_n_0 )); + LUT4 #( + .INIT(16'hEFFF)) + \reg_state_eios_det[2]_i_3 + (.I0(Q[9]), + .I1(Q[8]), + .I2(Q[11]), + .I3(Q[10]), + .O(\reg_state_eios_det[2]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT3 #( + .INIT(8'h04)) + \reg_state_eios_det[3]_i_1 + (.I0(\reg_state_eios_det[3]_i_2_n_0 ), + .I1(state_eios_det[2]), + .I2(\reg_state_eios_det[4]_i_3_n_0 ), + .O(p_1_in__0[3])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT3 #( + .INIT(8'hFD)) + \reg_state_eios_det[3]_i_2 + (.I0(Q[14]), + .I1(Q[15]), + .I2(\reg_state_eios_det[2]_i_2_n_0 ), + .O(\reg_state_eios_det[3]_i_2_n_0 )); + LUT5 #( + .INIT(32'h00010116)) + \reg_state_eios_det[4]_i_1 + (.I0(state_eios_det[0]), + .I1(state_eios_det[4]), + .I2(state_eios_det[2]), + .I3(state_eios_det[1]), + .I4(state_eios_det[3]), + .O(\reg_state_eios_det[4]_i_1_n_0 )); + LUT3 #( + .INIT(8'h0E)) + \reg_state_eios_det[4]_i_2 + (.I0(state_eios_det[3]), + .I1(state_eios_det[1]), + .I2(\reg_state_eios_det[4]_i_3_n_0 ), + .O(p_1_in__0[4])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT3 #( + .INIT(8'hFD)) + \reg_state_eios_det[4]_i_3 + (.I0(Q[6]), + .I1(Q[7]), + .I2(\reg_state_eios_det[1]_i_2_n_0 ), + .O(\reg_state_eios_det[4]_i_3_n_0 )); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDSE \reg_state_eios_det_reg[0] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1_n_0 ), + .D(p_1_in__0[0]), + .Q(state_eios_det[0]), + .S(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[1] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1_n_0 ), + .D(p_1_in__0[1]), + .Q(state_eios_det[1]), + .R(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[2] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1_n_0 ), + .D(p_1_in__0[2]), + .Q(state_eios_det[2]), + .R(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[3] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1_n_0 ), + .D(p_1_in__0[3]), + .Q(state_eios_det[3]), + .R(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[4] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1_n_0 ), + .D(p_1_in__0[4]), + .Q(state_eios_det[4]), + .R(SR)); + LUT6 #( + .INIT(64'h0000000000000010)) + reg_symbol_after_eios_i_1 + (.I0(\reg_state_eios_det[3]_i_2_n_0 ), + .I1(state_eios_det[0]), + .I2(state_eios_det[2]), + .I3(state_eios_det[3]), + .I4(state_eios_det[1]), + .I5(reg_symbol_after_eios_i_2_n_0), + .O(reg_symbol_after_eios)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'hE)) + reg_symbol_after_eios_i_2 + (.I0(\reg_state_eios_det[4]_i_3_n_0 ), + .I1(state_eios_det[4]), + .O(reg_symbol_after_eios_i_2_n_0)); + FDRE reg_symbol_after_eios_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(reg_symbol_after_eios), + .Q(symbol_after_eios), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_gt_rx_valid_filter_7x" *) +module pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_34 + (gt_rxvalid_q_reg_0, + gt_rx_phy_status_q_reg_0, + gt_rxelecidle_q_reg_0, + Q, + gt_rxvalid_q_reg_1, + \gt_rx_status_q_reg[2]_0 , + SR, + pipe_pclk_in, + gt_rx_phy_status_wire_filter, + PIPE_RXELECIDLE, + gt_rxvalid_q_reg_2, + \gt_rx_status_q_reg[0]_0 , + PIPE_RXSTATUS, + PIPE_RXDATAK, + PIPE_RXDATA); + output gt_rxvalid_q_reg_0; + output gt_rx_phy_status_q_reg_0; + output gt_rxelecidle_q_reg_0; + output [15:0]Q; + output [1:0]gt_rxvalid_q_reg_1; + output [2:0]\gt_rx_status_q_reg[2]_0 ; + input [0:0]SR; + input pipe_pclk_in; + input [0:0]gt_rx_phy_status_wire_filter; + input [0:0]PIPE_RXELECIDLE; + input gt_rxvalid_q_reg_2; + input \gt_rx_status_q_reg[0]_0 ; + input [2:0]PIPE_RXSTATUS; + input [1:0]PIPE_RXDATAK; + input [15:0]PIPE_RXDATA; + + wire [15:0]PIPE_RXDATA; + wire [1:0]PIPE_RXDATAK; + wire [0:0]PIPE_RXELECIDLE; + wire [2:0]PIPE_RXSTATUS; + wire [15:0]Q; + wire [0:0]SR; + wire gt_rx_phy_status_q_reg_0; + wire [0:0]gt_rx_phy_status_wire_filter; + wire \gt_rx_status_q[0]_i_1__1_n_0 ; + wire \gt_rx_status_q[1]_i_1__1_n_0 ; + wire \gt_rx_status_q[2]_i_1__1_n_0 ; + wire \gt_rx_status_q_reg[0]_0 ; + wire [2:0]\gt_rx_status_q_reg[2]_0 ; + wire \gt_rxcharisk_q_reg_n_0_[0] ; + wire gt_rxelecidle_q_reg_0; + wire gt_rxvalid_q__0; + wire gt_rxvalid_q_i_2__0_n_0; + wire gt_rxvalid_q_n_0; + wire gt_rxvalid_q_reg_0; + wire [1:0]gt_rxvalid_q_reg_1; + wire gt_rxvalid_q_reg_2; + wire p_1_in; + wire [4:0]p_1_in__0; + wire pipe_pclk_in; + wire \reg_state_eios_det[0]_i_2__0_n_0 ; + wire \reg_state_eios_det[0]_i_3__0_n_0 ; + wire \reg_state_eios_det[0]_i_4__0_n_0 ; + wire \reg_state_eios_det[0]_i_5__0_n_0 ; + wire \reg_state_eios_det[1]_i_2__0_n_0 ; + wire \reg_state_eios_det[1]_i_3__0_n_0 ; + wire \reg_state_eios_det[2]_i_2__0_n_0 ; + wire \reg_state_eios_det[2]_i_3__0_n_0 ; + wire \reg_state_eios_det[3]_i_2__0_n_0 ; + wire \reg_state_eios_det[4]_i_1__0_n_0 ; + wire \reg_state_eios_det[4]_i_3__0_n_0 ; + wire reg_symbol_after_eios; + wire reg_symbol_after_eios_i_2__0_n_0; + wire [4:0]state_eios_det; + wire symbol_after_eios; + + FDRE gt_rx_phy_status_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rx_phy_status_wire_filter), + .Q(gt_rx_phy_status_q_reg_0), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT3 #( + .INIT(8'hE0)) + \gt_rx_status_q[0]_i_1__1 + (.I0(gt_rxvalid_q_reg_0), + .I1(\gt_rx_status_q_reg[0]_0 ), + .I2(PIPE_RXSTATUS[0]), + .O(\gt_rx_status_q[0]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT3 #( + .INIT(8'hE0)) + \gt_rx_status_q[1]_i_1__1 + (.I0(gt_rxvalid_q_reg_0), + .I1(\gt_rx_status_q_reg[0]_0 ), + .I2(PIPE_RXSTATUS[1]), + .O(\gt_rx_status_q[1]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'hE0)) + \gt_rx_status_q[2]_i_1__1 + (.I0(gt_rxvalid_q_reg_0), + .I1(\gt_rx_status_q_reg[0]_0 ), + .I2(PIPE_RXSTATUS[2]), + .O(\gt_rx_status_q[2]_i_1__1_n_0 )); + FDRE \gt_rx_status_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\gt_rx_status_q[0]_i_1__1_n_0 ), + .Q(\gt_rx_status_q_reg[2]_0 [0]), + .R(SR)); + FDRE \gt_rx_status_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\gt_rx_status_q[1]_i_1__1_n_0 ), + .Q(\gt_rx_status_q_reg[2]_0 [1]), + .R(SR)); + FDRE \gt_rx_status_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\gt_rx_status_q[2]_i_1__1_n_0 ), + .Q(\gt_rx_status_q_reg[2]_0 [2]), + .R(SR)); + FDRE \gt_rxcharisk_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATAK[0]), + .Q(\gt_rxcharisk_q_reg_n_0_[0] ), + .R(SR)); + FDRE \gt_rxcharisk_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATAK[1]), + .Q(p_1_in), + .R(SR)); + FDRE \gt_rxdata_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[0]), + .Q(Q[0]), + .R(SR)); + FDRE \gt_rxdata_q_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[10]), + .Q(Q[10]), + .R(SR)); + FDRE \gt_rxdata_q_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[11]), + .Q(Q[11]), + .R(SR)); + FDRE \gt_rxdata_q_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[12]), + .Q(Q[12]), + .R(SR)); + FDRE \gt_rxdata_q_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[13]), + .Q(Q[13]), + .R(SR)); + FDRE \gt_rxdata_q_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[14]), + .Q(Q[14]), + .R(SR)); + FDRE \gt_rxdata_q_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[15]), + .Q(Q[15]), + .R(SR)); + FDRE \gt_rxdata_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[1]), + .Q(Q[1]), + .R(SR)); + FDRE \gt_rxdata_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[2]), + .Q(Q[2]), + .R(SR)); + FDRE \gt_rxdata_q_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[3]), + .Q(Q[3]), + .R(SR)); + FDRE \gt_rxdata_q_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[4]), + .Q(Q[4]), + .R(SR)); + FDRE \gt_rxdata_q_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[5]), + .Q(Q[5]), + .R(SR)); + FDRE \gt_rxdata_q_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[6]), + .Q(Q[6]), + .R(SR)); + FDRE \gt_rxdata_q_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[7]), + .Q(Q[7]), + .R(SR)); + FDRE \gt_rxdata_q_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[8]), + .Q(Q[8]), + .R(SR)); + FDRE \gt_rxdata_q_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[9]), + .Q(Q[9]), + .R(SR)); + FDRE gt_rxelecidle_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXELECIDLE), + .Q(gt_rxelecidle_q_reg_0), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT5 #( + .INIT(32'h00010116)) + gt_rxvalid_q + (.I0(state_eios_det[0]), + .I1(state_eios_det[1]), + .I2(state_eios_det[2]), + .I3(state_eios_det[3]), + .I4(state_eios_det[4]), + .O(gt_rxvalid_q_n_0)); + LUT5 #( + .INIT(32'hFFAAEAAA)) + gt_rxvalid_q_i_1__0 + (.I0(gt_rxvalid_q_i_2__0_n_0), + .I1(state_eios_det[2]), + .I2(\reg_state_eios_det[3]_i_2__0_n_0 ), + .I3(gt_rxvalid_q_reg_2), + .I4(state_eios_det[0]), + .O(gt_rxvalid_q__0)); + LUT6 #( + .INIT(64'hFFF50000CC550000)) + gt_rxvalid_q_i_2__0 + (.I0(gt_rxvalid_q_n_0), + .I1(\gt_rx_status_q_reg[0]_0 ), + .I2(\reg_state_eios_det[4]_i_3__0_n_0 ), + .I3(state_eios_det[4]), + .I4(gt_rxvalid_q_reg_2), + .I5(\reg_state_eios_det[0]_i_3__0_n_0 ), + .O(gt_rxvalid_q_i_2__0_n_0)); + FDRE gt_rxvalid_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rxvalid_q__0), + .Q(gt_rxvalid_q_reg_0), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h8)) + \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__0 + (.I0(gt_rxvalid_q_reg_0), + .I1(\gt_rxcharisk_q_reg_n_0_[0] ), + .O(gt_rxvalid_q_reg_1[0])); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'h08)) + \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__0 + (.I0(gt_rxvalid_q_reg_0), + .I1(p_1_in), + .I2(symbol_after_eios), + .O(gt_rxvalid_q_reg_1[1])); + LUT6 #( + .INIT(64'hFFFFFFFFFEFEFEEE)) + \reg_state_eios_det[0]_i_1__0 + (.I0(state_eios_det[4]), + .I1(\reg_state_eios_det[0]_i_2__0_n_0 ), + .I2(\reg_state_eios_det[1]_i_2__0_n_0 ), + .I3(\reg_state_eios_det[0]_i_3__0_n_0 ), + .I4(\reg_state_eios_det[0]_i_4__0_n_0 ), + .I5(\reg_state_eios_det[0]_i_5__0_n_0 ), + .O(p_1_in__0[0])); + LUT6 #( + .INIT(64'hFFF3AAFFAA00AAAA)) + \reg_state_eios_det[0]_i_2__0 + (.I0(state_eios_det[2]), + .I1(Q[7]), + .I2(Q[6]), + .I3(Q[15]), + .I4(Q[14]), + .I5(state_eios_det[0]), + .O(\reg_state_eios_det[0]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'hFE)) + \reg_state_eios_det[0]_i_3__0 + (.I0(state_eios_det[3]), + .I1(state_eios_det[1]), + .I2(state_eios_det[2]), + .O(\reg_state_eios_det[0]_i_3__0_n_0 )); + LUT2 #( + .INIT(4'h8)) + \reg_state_eios_det[0]_i_4__0 + (.I0(Q[14]), + .I1(state_eios_det[0]), + .O(\reg_state_eios_det[0]_i_4__0_n_0 )); + LUT6 #( + .INIT(64'hFFE0E0E0FFE0FFE0)) + \reg_state_eios_det[0]_i_5__0 + (.I0(state_eios_det[0]), + .I1(state_eios_det[2]), + .I2(\reg_state_eios_det[2]_i_2__0_n_0 ), + .I3(\reg_state_eios_det[0]_i_3__0_n_0 ), + .I4(Q[7]), + .I5(Q[6]), + .O(\reg_state_eios_det[0]_i_5__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'h00000040)) + \reg_state_eios_det[1]_i_1__0 + (.I0(\reg_state_eios_det[1]_i_2__0_n_0 ), + .I1(state_eios_det[0]), + .I2(Q[7]), + .I3(Q[6]), + .I4(\reg_state_eios_det[3]_i_2__0_n_0 ), + .O(p_1_in__0[1])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT4 #( + .INIT(16'hBFFF)) + \reg_state_eios_det[1]_i_2__0 + (.I0(\reg_state_eios_det[1]_i_3__0_n_0 ), + .I1(\gt_rxcharisk_q_reg_n_0_[0] ), + .I2(Q[4]), + .I3(Q[5]), + .O(\reg_state_eios_det[1]_i_2__0_n_0 )); + LUT4 #( + .INIT(16'hEFFF)) + \reg_state_eios_det[1]_i_3__0 + (.I0(Q[1]), + .I1(Q[0]), + .I2(Q[3]), + .I3(Q[2]), + .O(\reg_state_eios_det[1]_i_3__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'h0040)) + \reg_state_eios_det[2]_i_1__0 + (.I0(Q[14]), + .I1(Q[15]), + .I2(state_eios_det[0]), + .I3(\reg_state_eios_det[2]_i_2__0_n_0 ), + .O(p_1_in__0[2])); + LUT4 #( + .INIT(16'hBFFF)) + \reg_state_eios_det[2]_i_2__0 + (.I0(\reg_state_eios_det[2]_i_3__0_n_0 ), + .I1(p_1_in), + .I2(Q[12]), + .I3(Q[13]), + .O(\reg_state_eios_det[2]_i_2__0_n_0 )); + LUT4 #( + .INIT(16'hEFFF)) + \reg_state_eios_det[2]_i_3__0 + (.I0(Q[9]), + .I1(Q[8]), + .I2(Q[11]), + .I3(Q[10]), + .O(\reg_state_eios_det[2]_i_3__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'h04)) + \reg_state_eios_det[3]_i_1__0 + (.I0(\reg_state_eios_det[3]_i_2__0_n_0 ), + .I1(state_eios_det[2]), + .I2(\reg_state_eios_det[4]_i_3__0_n_0 ), + .O(p_1_in__0[3])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT3 #( + .INIT(8'hFD)) + \reg_state_eios_det[3]_i_2__0 + (.I0(Q[14]), + .I1(Q[15]), + .I2(\reg_state_eios_det[2]_i_2__0_n_0 ), + .O(\reg_state_eios_det[3]_i_2__0_n_0 )); + LUT5 #( + .INIT(32'h00010116)) + \reg_state_eios_det[4]_i_1__0 + (.I0(state_eios_det[0]), + .I1(state_eios_det[4]), + .I2(state_eios_det[2]), + .I3(state_eios_det[1]), + .I4(state_eios_det[3]), + .O(\reg_state_eios_det[4]_i_1__0_n_0 )); + LUT3 #( + .INIT(8'h0E)) + \reg_state_eios_det[4]_i_2__0 + (.I0(state_eios_det[3]), + .I1(state_eios_det[1]), + .I2(\reg_state_eios_det[4]_i_3__0_n_0 ), + .O(p_1_in__0[4])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT3 #( + .INIT(8'hFD)) + \reg_state_eios_det[4]_i_3__0 + (.I0(Q[6]), + .I1(Q[7]), + .I2(\reg_state_eios_det[1]_i_2__0_n_0 ), + .O(\reg_state_eios_det[4]_i_3__0_n_0 )); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDSE \reg_state_eios_det_reg[0] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__0_n_0 ), + .D(p_1_in__0[0]), + .Q(state_eios_det[0]), + .S(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[1] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__0_n_0 ), + .D(p_1_in__0[1]), + .Q(state_eios_det[1]), + .R(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[2] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__0_n_0 ), + .D(p_1_in__0[2]), + .Q(state_eios_det[2]), + .R(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[3] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__0_n_0 ), + .D(p_1_in__0[3]), + .Q(state_eios_det[3]), + .R(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[4] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__0_n_0 ), + .D(p_1_in__0[4]), + .Q(state_eios_det[4]), + .R(SR)); + LUT6 #( + .INIT(64'h0000000000000010)) + reg_symbol_after_eios_i_1__0 + (.I0(\reg_state_eios_det[3]_i_2__0_n_0 ), + .I1(state_eios_det[0]), + .I2(state_eios_det[2]), + .I3(state_eios_det[3]), + .I4(state_eios_det[1]), + .I5(reg_symbol_after_eios_i_2__0_n_0), + .O(reg_symbol_after_eios)); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT2 #( + .INIT(4'hE)) + reg_symbol_after_eios_i_2__0 + (.I0(\reg_state_eios_det[4]_i_3__0_n_0 ), + .I1(state_eios_det[4]), + .O(reg_symbol_after_eios_i_2__0_n_0)); + FDRE reg_symbol_after_eios_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(reg_symbol_after_eios), + .Q(symbol_after_eios), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_gt_rx_valid_filter_7x" *) +module pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_35 + (gt_rxvalid_q_reg_0, + gt_rx_phy_status_q_reg_0, + gt_rxelecidle_q_reg_0, + Q, + gt_rxvalid_q_reg_1, + \gt_rx_status_q_reg[2]_0 , + SR, + pipe_pclk_in, + gt_rx_phy_status_wire_filter, + PIPE_RXELECIDLE, + gt_rxvalid_q_reg_2, + \gt_rx_status_q_reg[0]_0 , + PIPE_RXSTATUS, + PIPE_RXDATAK, + PIPE_RXDATA); + output gt_rxvalid_q_reg_0; + output gt_rx_phy_status_q_reg_0; + output gt_rxelecidle_q_reg_0; + output [15:0]Q; + output [1:0]gt_rxvalid_q_reg_1; + output [2:0]\gt_rx_status_q_reg[2]_0 ; + input [0:0]SR; + input pipe_pclk_in; + input [0:0]gt_rx_phy_status_wire_filter; + input [0:0]PIPE_RXELECIDLE; + input gt_rxvalid_q_reg_2; + input \gt_rx_status_q_reg[0]_0 ; + input [2:0]PIPE_RXSTATUS; + input [1:0]PIPE_RXDATAK; + input [15:0]PIPE_RXDATA; + + wire [15:0]PIPE_RXDATA; + wire [1:0]PIPE_RXDATAK; + wire [0:0]PIPE_RXELECIDLE; + wire [2:0]PIPE_RXSTATUS; + wire [15:0]Q; + wire [0:0]SR; + wire gt_rx_phy_status_q_reg_0; + wire [0:0]gt_rx_phy_status_wire_filter; + wire \gt_rx_status_q[0]_i_1__0_n_0 ; + wire \gt_rx_status_q[1]_i_1__0_n_0 ; + wire \gt_rx_status_q[2]_i_1__0_n_0 ; + wire \gt_rx_status_q_reg[0]_0 ; + wire [2:0]\gt_rx_status_q_reg[2]_0 ; + wire \gt_rxcharisk_q_reg_n_0_[0] ; + wire gt_rxelecidle_q_reg_0; + wire gt_rxvalid_q__0; + wire gt_rxvalid_q_i_2__1_n_0; + wire gt_rxvalid_q_n_0; + wire gt_rxvalid_q_reg_0; + wire [1:0]gt_rxvalid_q_reg_1; + wire gt_rxvalid_q_reg_2; + wire p_1_in; + wire [4:0]p_1_in__0; + wire pipe_pclk_in; + wire \reg_state_eios_det[0]_i_2__1_n_0 ; + wire \reg_state_eios_det[0]_i_3__1_n_0 ; + wire \reg_state_eios_det[0]_i_4__1_n_0 ; + wire \reg_state_eios_det[0]_i_5__1_n_0 ; + wire \reg_state_eios_det[1]_i_2__1_n_0 ; + wire \reg_state_eios_det[1]_i_3__1_n_0 ; + wire \reg_state_eios_det[2]_i_2__1_n_0 ; + wire \reg_state_eios_det[2]_i_3__1_n_0 ; + wire \reg_state_eios_det[3]_i_2__1_n_0 ; + wire \reg_state_eios_det[4]_i_1__1_n_0 ; + wire \reg_state_eios_det[4]_i_3__1_n_0 ; + wire reg_symbol_after_eios; + wire reg_symbol_after_eios_i_2__1_n_0; + wire [4:0]state_eios_det; + wire symbol_after_eios; + + FDRE gt_rx_phy_status_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rx_phy_status_wire_filter), + .Q(gt_rx_phy_status_q_reg_0), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hE0)) + \gt_rx_status_q[0]_i_1__0 + (.I0(gt_rxvalid_q_reg_0), + .I1(\gt_rx_status_q_reg[0]_0 ), + .I2(PIPE_RXSTATUS[0]), + .O(\gt_rx_status_q[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hE0)) + \gt_rx_status_q[1]_i_1__0 + (.I0(gt_rxvalid_q_reg_0), + .I1(\gt_rx_status_q_reg[0]_0 ), + .I2(PIPE_RXSTATUS[1]), + .O(\gt_rx_status_q[1]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'hE0)) + \gt_rx_status_q[2]_i_1__0 + (.I0(gt_rxvalid_q_reg_0), + .I1(\gt_rx_status_q_reg[0]_0 ), + .I2(PIPE_RXSTATUS[2]), + .O(\gt_rx_status_q[2]_i_1__0_n_0 )); + FDRE \gt_rx_status_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\gt_rx_status_q[0]_i_1__0_n_0 ), + .Q(\gt_rx_status_q_reg[2]_0 [0]), + .R(SR)); + FDRE \gt_rx_status_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\gt_rx_status_q[1]_i_1__0_n_0 ), + .Q(\gt_rx_status_q_reg[2]_0 [1]), + .R(SR)); + FDRE \gt_rx_status_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\gt_rx_status_q[2]_i_1__0_n_0 ), + .Q(\gt_rx_status_q_reg[2]_0 [2]), + .R(SR)); + FDRE \gt_rxcharisk_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATAK[0]), + .Q(\gt_rxcharisk_q_reg_n_0_[0] ), + .R(SR)); + FDRE \gt_rxcharisk_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATAK[1]), + .Q(p_1_in), + .R(SR)); + FDRE \gt_rxdata_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[0]), + .Q(Q[0]), + .R(SR)); + FDRE \gt_rxdata_q_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[10]), + .Q(Q[10]), + .R(SR)); + FDRE \gt_rxdata_q_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[11]), + .Q(Q[11]), + .R(SR)); + FDRE \gt_rxdata_q_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[12]), + .Q(Q[12]), + .R(SR)); + FDRE \gt_rxdata_q_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[13]), + .Q(Q[13]), + .R(SR)); + FDRE \gt_rxdata_q_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[14]), + .Q(Q[14]), + .R(SR)); + FDRE \gt_rxdata_q_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[15]), + .Q(Q[15]), + .R(SR)); + FDRE \gt_rxdata_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[1]), + .Q(Q[1]), + .R(SR)); + FDRE \gt_rxdata_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[2]), + .Q(Q[2]), + .R(SR)); + FDRE \gt_rxdata_q_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[3]), + .Q(Q[3]), + .R(SR)); + FDRE \gt_rxdata_q_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[4]), + .Q(Q[4]), + .R(SR)); + FDRE \gt_rxdata_q_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[5]), + .Q(Q[5]), + .R(SR)); + FDRE \gt_rxdata_q_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[6]), + .Q(Q[6]), + .R(SR)); + FDRE \gt_rxdata_q_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[7]), + .Q(Q[7]), + .R(SR)); + FDRE \gt_rxdata_q_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[8]), + .Q(Q[8]), + .R(SR)); + FDRE \gt_rxdata_q_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[9]), + .Q(Q[9]), + .R(SR)); + FDRE gt_rxelecidle_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXELECIDLE), + .Q(gt_rxelecidle_q_reg_0), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT5 #( + .INIT(32'h00010116)) + gt_rxvalid_q + (.I0(state_eios_det[0]), + .I1(state_eios_det[1]), + .I2(state_eios_det[2]), + .I3(state_eios_det[3]), + .I4(state_eios_det[4]), + .O(gt_rxvalid_q_n_0)); + LUT5 #( + .INIT(32'hFFAAEAAA)) + gt_rxvalid_q_i_1__1 + (.I0(gt_rxvalid_q_i_2__1_n_0), + .I1(state_eios_det[2]), + .I2(\reg_state_eios_det[3]_i_2__1_n_0 ), + .I3(gt_rxvalid_q_reg_2), + .I4(state_eios_det[0]), + .O(gt_rxvalid_q__0)); + LUT6 #( + .INIT(64'hFFF50000CC550000)) + gt_rxvalid_q_i_2__1 + (.I0(gt_rxvalid_q_n_0), + .I1(\gt_rx_status_q_reg[0]_0 ), + .I2(\reg_state_eios_det[4]_i_3__1_n_0 ), + .I3(state_eios_det[4]), + .I4(gt_rxvalid_q_reg_2), + .I5(\reg_state_eios_det[0]_i_3__1_n_0 ), + .O(gt_rxvalid_q_i_2__1_n_0)); + FDRE gt_rxvalid_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rxvalid_q__0), + .Q(gt_rxvalid_q_reg_0), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT2 #( + .INIT(4'h8)) + \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__1 + (.I0(gt_rxvalid_q_reg_0), + .I1(\gt_rxcharisk_q_reg_n_0_[0] ), + .O(gt_rxvalid_q_reg_1[0])); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'h08)) + \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__1 + (.I0(gt_rxvalid_q_reg_0), + .I1(p_1_in), + .I2(symbol_after_eios), + .O(gt_rxvalid_q_reg_1[1])); + LUT6 #( + .INIT(64'hFFFFFFFFFEFEFEEE)) + \reg_state_eios_det[0]_i_1__1 + (.I0(state_eios_det[4]), + .I1(\reg_state_eios_det[0]_i_2__1_n_0 ), + .I2(\reg_state_eios_det[1]_i_2__1_n_0 ), + .I3(\reg_state_eios_det[0]_i_3__1_n_0 ), + .I4(\reg_state_eios_det[0]_i_4__1_n_0 ), + .I5(\reg_state_eios_det[0]_i_5__1_n_0 ), + .O(p_1_in__0[0])); + LUT6 #( + .INIT(64'hFFF3AAFFAA00AAAA)) + \reg_state_eios_det[0]_i_2__1 + (.I0(state_eios_det[2]), + .I1(Q[7]), + .I2(Q[6]), + .I3(Q[15]), + .I4(Q[14]), + .I5(state_eios_det[0]), + .O(\reg_state_eios_det[0]_i_2__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'hFE)) + \reg_state_eios_det[0]_i_3__1 + (.I0(state_eios_det[3]), + .I1(state_eios_det[1]), + .I2(state_eios_det[2]), + .O(\reg_state_eios_det[0]_i_3__1_n_0 )); + LUT2 #( + .INIT(4'h8)) + \reg_state_eios_det[0]_i_4__1 + (.I0(Q[14]), + .I1(state_eios_det[0]), + .O(\reg_state_eios_det[0]_i_4__1_n_0 )); + LUT6 #( + .INIT(64'hFFE0E0E0FFE0FFE0)) + \reg_state_eios_det[0]_i_5__1 + (.I0(state_eios_det[0]), + .I1(state_eios_det[2]), + .I2(\reg_state_eios_det[2]_i_2__1_n_0 ), + .I3(\reg_state_eios_det[0]_i_3__1_n_0 ), + .I4(Q[7]), + .I5(Q[6]), + .O(\reg_state_eios_det[0]_i_5__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT5 #( + .INIT(32'h00000040)) + \reg_state_eios_det[1]_i_1__1 + (.I0(\reg_state_eios_det[1]_i_2__1_n_0 ), + .I1(state_eios_det[0]), + .I2(Q[7]), + .I3(Q[6]), + .I4(\reg_state_eios_det[3]_i_2__1_n_0 ), + .O(p_1_in__0[1])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'hBFFF)) + \reg_state_eios_det[1]_i_2__1 + (.I0(\reg_state_eios_det[1]_i_3__1_n_0 ), + .I1(\gt_rxcharisk_q_reg_n_0_[0] ), + .I2(Q[4]), + .I3(Q[5]), + .O(\reg_state_eios_det[1]_i_2__1_n_0 )); + LUT4 #( + .INIT(16'hEFFF)) + \reg_state_eios_det[1]_i_3__1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(Q[3]), + .I3(Q[2]), + .O(\reg_state_eios_det[1]_i_3__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h0040)) + \reg_state_eios_det[2]_i_1__1 + (.I0(Q[14]), + .I1(Q[15]), + .I2(state_eios_det[0]), + .I3(\reg_state_eios_det[2]_i_2__1_n_0 ), + .O(p_1_in__0[2])); + LUT4 #( + .INIT(16'hBFFF)) + \reg_state_eios_det[2]_i_2__1 + (.I0(\reg_state_eios_det[2]_i_3__1_n_0 ), + .I1(p_1_in), + .I2(Q[12]), + .I3(Q[13]), + .O(\reg_state_eios_det[2]_i_2__1_n_0 )); + LUT4 #( + .INIT(16'hEFFF)) + \reg_state_eios_det[2]_i_3__1 + (.I0(Q[9]), + .I1(Q[8]), + .I2(Q[11]), + .I3(Q[10]), + .O(\reg_state_eios_det[2]_i_3__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'h04)) + \reg_state_eios_det[3]_i_1__1 + (.I0(\reg_state_eios_det[3]_i_2__1_n_0 ), + .I1(state_eios_det[2]), + .I2(\reg_state_eios_det[4]_i_3__1_n_0 ), + .O(p_1_in__0[3])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'hFD)) + \reg_state_eios_det[3]_i_2__1 + (.I0(Q[14]), + .I1(Q[15]), + .I2(\reg_state_eios_det[2]_i_2__1_n_0 ), + .O(\reg_state_eios_det[3]_i_2__1_n_0 )); + LUT5 #( + .INIT(32'h00010116)) + \reg_state_eios_det[4]_i_1__1 + (.I0(state_eios_det[0]), + .I1(state_eios_det[4]), + .I2(state_eios_det[2]), + .I3(state_eios_det[1]), + .I4(state_eios_det[3]), + .O(\reg_state_eios_det[4]_i_1__1_n_0 )); + LUT3 #( + .INIT(8'h0E)) + \reg_state_eios_det[4]_i_2__1 + (.I0(state_eios_det[3]), + .I1(state_eios_det[1]), + .I2(\reg_state_eios_det[4]_i_3__1_n_0 ), + .O(p_1_in__0[4])); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hFD)) + \reg_state_eios_det[4]_i_3__1 + (.I0(Q[6]), + .I1(Q[7]), + .I2(\reg_state_eios_det[1]_i_2__1_n_0 ), + .O(\reg_state_eios_det[4]_i_3__1_n_0 )); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDSE \reg_state_eios_det_reg[0] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__1_n_0 ), + .D(p_1_in__0[0]), + .Q(state_eios_det[0]), + .S(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[1] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__1_n_0 ), + .D(p_1_in__0[1]), + .Q(state_eios_det[1]), + .R(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[2] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__1_n_0 ), + .D(p_1_in__0[2]), + .Q(state_eios_det[2]), + .R(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[3] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__1_n_0 ), + .D(p_1_in__0[3]), + .Q(state_eios_det[3]), + .R(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[4] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__1_n_0 ), + .D(p_1_in__0[4]), + .Q(state_eios_det[4]), + .R(SR)); + LUT6 #( + .INIT(64'h0000000000000010)) + reg_symbol_after_eios_i_1__1 + (.I0(\reg_state_eios_det[3]_i_2__1_n_0 ), + .I1(state_eios_det[0]), + .I2(state_eios_det[2]), + .I3(state_eios_det[3]), + .I4(state_eios_det[1]), + .I5(reg_symbol_after_eios_i_2__1_n_0), + .O(reg_symbol_after_eios)); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT2 #( + .INIT(4'hE)) + reg_symbol_after_eios_i_2__1 + (.I0(\reg_state_eios_det[4]_i_3__1_n_0 ), + .I1(state_eios_det[4]), + .O(reg_symbol_after_eios_i_2__1_n_0)); + FDRE reg_symbol_after_eios_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(reg_symbol_after_eios), + .Q(symbol_after_eios), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_gt_rx_valid_filter_7x" *) +module pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_36 + (gt_rxvalid_q_reg_0, + gt_rx_phy_status_q_reg_0, + gt_rxelecidle_q_reg_0, + Q, + gt_rxvalid_q_reg_1, + \gt_rx_status_q_reg[2]_0 , + SR, + pipe_pclk_in, + gt_rx_phy_status_wire_filter, + PIPE_RXELECIDLE, + gt_rxvalid_q_reg_2, + \gt_rx_status_q_reg[0]_0 , + PIPE_RXSTATUS, + PIPE_RXDATAK, + PIPE_RXDATA); + output gt_rxvalid_q_reg_0; + output gt_rx_phy_status_q_reg_0; + output gt_rxelecidle_q_reg_0; + output [15:0]Q; + output [1:0]gt_rxvalid_q_reg_1; + output [2:0]\gt_rx_status_q_reg[2]_0 ; + input [0:0]SR; + input pipe_pclk_in; + input [0:0]gt_rx_phy_status_wire_filter; + input [0:0]PIPE_RXELECIDLE; + input gt_rxvalid_q_reg_2; + input \gt_rx_status_q_reg[0]_0 ; + input [2:0]PIPE_RXSTATUS; + input [1:0]PIPE_RXDATAK; + input [15:0]PIPE_RXDATA; + + wire [15:0]PIPE_RXDATA; + wire [1:0]PIPE_RXDATAK; + wire [0:0]PIPE_RXELECIDLE; + wire [2:0]PIPE_RXSTATUS; + wire [15:0]Q; + wire [0:0]SR; + wire gt_rx_phy_status_q_reg_0; + wire [0:0]gt_rx_phy_status_wire_filter; + wire \gt_rx_status_q[0]_i_1_n_0 ; + wire \gt_rx_status_q[1]_i_1_n_0 ; + wire \gt_rx_status_q[2]_i_1_n_0 ; + wire \gt_rx_status_q_reg[0]_0 ; + wire [2:0]\gt_rx_status_q_reg[2]_0 ; + wire \gt_rxcharisk_q_reg_n_0_[0] ; + wire gt_rxelecidle_q_reg_0; + wire gt_rxvalid_q__0; + wire gt_rxvalid_q_i_2__2_n_0; + wire gt_rxvalid_q_n_0; + wire gt_rxvalid_q_reg_0; + wire [1:0]gt_rxvalid_q_reg_1; + wire gt_rxvalid_q_reg_2; + wire p_1_in; + wire [4:0]p_1_in__0; + wire pipe_pclk_in; + wire \reg_state_eios_det[0]_i_2__2_n_0 ; + wire \reg_state_eios_det[0]_i_3__2_n_0 ; + wire \reg_state_eios_det[0]_i_4__2_n_0 ; + wire \reg_state_eios_det[0]_i_5__2_n_0 ; + wire \reg_state_eios_det[1]_i_2__2_n_0 ; + wire \reg_state_eios_det[1]_i_3__2_n_0 ; + wire \reg_state_eios_det[2]_i_2__2_n_0 ; + wire \reg_state_eios_det[2]_i_3__2_n_0 ; + wire \reg_state_eios_det[3]_i_2__2_n_0 ; + wire \reg_state_eios_det[4]_i_1__2_n_0 ; + wire \reg_state_eios_det[4]_i_3__2_n_0 ; + wire reg_symbol_after_eios; + wire reg_symbol_after_eios_i_2__2_n_0; + wire [4:0]state_eios_det; + wire symbol_after_eios; + + FDRE gt_rx_phy_status_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rx_phy_status_wire_filter), + .Q(gt_rx_phy_status_q_reg_0), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'hE0)) + \gt_rx_status_q[0]_i_1 + (.I0(gt_rxvalid_q_reg_0), + .I1(\gt_rx_status_q_reg[0]_0 ), + .I2(PIPE_RXSTATUS[0]), + .O(\gt_rx_status_q[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'hE0)) + \gt_rx_status_q[1]_i_1 + (.I0(gt_rxvalid_q_reg_0), + .I1(\gt_rx_status_q_reg[0]_0 ), + .I2(PIPE_RXSTATUS[1]), + .O(\gt_rx_status_q[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hE0)) + \gt_rx_status_q[2]_i_1 + (.I0(gt_rxvalid_q_reg_0), + .I1(\gt_rx_status_q_reg[0]_0 ), + .I2(PIPE_RXSTATUS[2]), + .O(\gt_rx_status_q[2]_i_1_n_0 )); + FDRE \gt_rx_status_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\gt_rx_status_q[0]_i_1_n_0 ), + .Q(\gt_rx_status_q_reg[2]_0 [0]), + .R(SR)); + FDRE \gt_rx_status_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\gt_rx_status_q[1]_i_1_n_0 ), + .Q(\gt_rx_status_q_reg[2]_0 [1]), + .R(SR)); + FDRE \gt_rx_status_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\gt_rx_status_q[2]_i_1_n_0 ), + .Q(\gt_rx_status_q_reg[2]_0 [2]), + .R(SR)); + FDRE \gt_rxcharisk_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATAK[0]), + .Q(\gt_rxcharisk_q_reg_n_0_[0] ), + .R(SR)); + FDRE \gt_rxcharisk_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATAK[1]), + .Q(p_1_in), + .R(SR)); + FDRE \gt_rxdata_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[0]), + .Q(Q[0]), + .R(SR)); + FDRE \gt_rxdata_q_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[10]), + .Q(Q[10]), + .R(SR)); + FDRE \gt_rxdata_q_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[11]), + .Q(Q[11]), + .R(SR)); + FDRE \gt_rxdata_q_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[12]), + .Q(Q[12]), + .R(SR)); + FDRE \gt_rxdata_q_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[13]), + .Q(Q[13]), + .R(SR)); + FDRE \gt_rxdata_q_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[14]), + .Q(Q[14]), + .R(SR)); + FDRE \gt_rxdata_q_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[15]), + .Q(Q[15]), + .R(SR)); + FDRE \gt_rxdata_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[1]), + .Q(Q[1]), + .R(SR)); + FDRE \gt_rxdata_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[2]), + .Q(Q[2]), + .R(SR)); + FDRE \gt_rxdata_q_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[3]), + .Q(Q[3]), + .R(SR)); + FDRE \gt_rxdata_q_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[4]), + .Q(Q[4]), + .R(SR)); + FDRE \gt_rxdata_q_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[5]), + .Q(Q[5]), + .R(SR)); + FDRE \gt_rxdata_q_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[6]), + .Q(Q[6]), + .R(SR)); + FDRE \gt_rxdata_q_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[7]), + .Q(Q[7]), + .R(SR)); + FDRE \gt_rxdata_q_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[8]), + .Q(Q[8]), + .R(SR)); + FDRE \gt_rxdata_q_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXDATA[9]), + .Q(Q[9]), + .R(SR)); + FDRE gt_rxelecidle_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXELECIDLE), + .Q(gt_rxelecidle_q_reg_0), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT5 #( + .INIT(32'h00010116)) + gt_rxvalid_q + (.I0(state_eios_det[0]), + .I1(state_eios_det[1]), + .I2(state_eios_det[2]), + .I3(state_eios_det[3]), + .I4(state_eios_det[4]), + .O(gt_rxvalid_q_n_0)); + LUT5 #( + .INIT(32'hFFAAEAAA)) + gt_rxvalid_q_i_1__2 + (.I0(gt_rxvalid_q_i_2__2_n_0), + .I1(state_eios_det[2]), + .I2(\reg_state_eios_det[3]_i_2__2_n_0 ), + .I3(gt_rxvalid_q_reg_2), + .I4(state_eios_det[0]), + .O(gt_rxvalid_q__0)); + LUT6 #( + .INIT(64'hFFF50000CC550000)) + gt_rxvalid_q_i_2__2 + (.I0(gt_rxvalid_q_n_0), + .I1(\gt_rx_status_q_reg[0]_0 ), + .I2(\reg_state_eios_det[4]_i_3__2_n_0 ), + .I3(state_eios_det[4]), + .I4(gt_rxvalid_q_reg_2), + .I5(\reg_state_eios_det[0]_i_3__2_n_0 ), + .O(gt_rxvalid_q_i_2__2_n_0)); + FDRE gt_rxvalid_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rxvalid_q__0), + .Q(gt_rxvalid_q_reg_0), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'h8)) + \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__2 + (.I0(gt_rxvalid_q_reg_0), + .I1(\gt_rxcharisk_q_reg_n_0_[0] ), + .O(gt_rxvalid_q_reg_1[0])); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'h08)) + \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__2 + (.I0(gt_rxvalid_q_reg_0), + .I1(p_1_in), + .I2(symbol_after_eios), + .O(gt_rxvalid_q_reg_1[1])); + LUT6 #( + .INIT(64'hFFFFFFFFFEFEFEEE)) + \reg_state_eios_det[0]_i_1__2 + (.I0(state_eios_det[4]), + .I1(\reg_state_eios_det[0]_i_2__2_n_0 ), + .I2(\reg_state_eios_det[1]_i_2__2_n_0 ), + .I3(\reg_state_eios_det[0]_i_3__2_n_0 ), + .I4(\reg_state_eios_det[0]_i_4__2_n_0 ), + .I5(\reg_state_eios_det[0]_i_5__2_n_0 ), + .O(p_1_in__0[0])); + LUT6 #( + .INIT(64'hFFAA8A8AFF00FFAA)) + \reg_state_eios_det[0]_i_2__2 + (.I0(state_eios_det[0]), + .I1(Q[6]), + .I2(Q[7]), + .I3(state_eios_det[2]), + .I4(Q[15]), + .I5(Q[14]), + .O(\reg_state_eios_det[0]_i_2__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'hFE)) + \reg_state_eios_det[0]_i_3__2 + (.I0(state_eios_det[3]), + .I1(state_eios_det[1]), + .I2(state_eios_det[2]), + .O(\reg_state_eios_det[0]_i_3__2_n_0 )); + LUT2 #( + .INIT(4'h2)) + \reg_state_eios_det[0]_i_4__2 + (.I0(state_eios_det[0]), + .I1(Q[15]), + .O(\reg_state_eios_det[0]_i_4__2_n_0 )); + LUT6 #( + .INIT(64'hFFE0E0E0FFE0FFE0)) + \reg_state_eios_det[0]_i_5__2 + (.I0(state_eios_det[0]), + .I1(state_eios_det[2]), + .I2(\reg_state_eios_det[2]_i_2__2_n_0 ), + .I3(\reg_state_eios_det[0]_i_3__2_n_0 ), + .I4(Q[7]), + .I5(Q[6]), + .O(\reg_state_eios_det[0]_i_5__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT5 #( + .INIT(32'h00000040)) + \reg_state_eios_det[1]_i_1__2 + (.I0(\reg_state_eios_det[1]_i_2__2_n_0 ), + .I1(state_eios_det[0]), + .I2(Q[7]), + .I3(Q[6]), + .I4(\reg_state_eios_det[3]_i_2__2_n_0 ), + .O(p_1_in__0[1])); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT4 #( + .INIT(16'hBFFF)) + \reg_state_eios_det[1]_i_2__2 + (.I0(\reg_state_eios_det[1]_i_3__2_n_0 ), + .I1(\gt_rxcharisk_q_reg_n_0_[0] ), + .I2(Q[4]), + .I3(Q[5]), + .O(\reg_state_eios_det[1]_i_2__2_n_0 )); + LUT4 #( + .INIT(16'hEFFF)) + \reg_state_eios_det[1]_i_3__2 + (.I0(Q[1]), + .I1(Q[0]), + .I2(Q[3]), + .I3(Q[2]), + .O(\reg_state_eios_det[1]_i_3__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT4 #( + .INIT(16'h0040)) + \reg_state_eios_det[2]_i_1__2 + (.I0(Q[14]), + .I1(Q[15]), + .I2(state_eios_det[0]), + .I3(\reg_state_eios_det[2]_i_2__2_n_0 ), + .O(p_1_in__0[2])); + LUT4 #( + .INIT(16'hBFFF)) + \reg_state_eios_det[2]_i_2__2 + (.I0(\reg_state_eios_det[2]_i_3__2_n_0 ), + .I1(p_1_in), + .I2(Q[12]), + .I3(Q[13]), + .O(\reg_state_eios_det[2]_i_2__2_n_0 )); + LUT4 #( + .INIT(16'hEFFF)) + \reg_state_eios_det[2]_i_3__2 + (.I0(Q[9]), + .I1(Q[8]), + .I2(Q[11]), + .I3(Q[10]), + .O(\reg_state_eios_det[2]_i_3__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'h04)) + \reg_state_eios_det[3]_i_1__2 + (.I0(\reg_state_eios_det[3]_i_2__2_n_0 ), + .I1(state_eios_det[2]), + .I2(\reg_state_eios_det[4]_i_3__2_n_0 ), + .O(p_1_in__0[3])); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hFD)) + \reg_state_eios_det[3]_i_2__2 + (.I0(Q[14]), + .I1(Q[15]), + .I2(\reg_state_eios_det[2]_i_2__2_n_0 ), + .O(\reg_state_eios_det[3]_i_2__2_n_0 )); + LUT5 #( + .INIT(32'h00010116)) + \reg_state_eios_det[4]_i_1__2 + (.I0(state_eios_det[0]), + .I1(state_eios_det[4]), + .I2(state_eios_det[2]), + .I3(state_eios_det[1]), + .I4(state_eios_det[3]), + .O(\reg_state_eios_det[4]_i_1__2_n_0 )); + LUT3 #( + .INIT(8'h0E)) + \reg_state_eios_det[4]_i_2__2 + (.I0(state_eios_det[3]), + .I1(state_eios_det[1]), + .I2(\reg_state_eios_det[4]_i_3__2_n_0 ), + .O(p_1_in__0[4])); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT3 #( + .INIT(8'hFD)) + \reg_state_eios_det[4]_i_3__2 + (.I0(Q[6]), + .I1(Q[7]), + .I2(\reg_state_eios_det[1]_i_2__2_n_0 ), + .O(\reg_state_eios_det[4]_i_3__2_n_0 )); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDSE \reg_state_eios_det_reg[0] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__2_n_0 ), + .D(p_1_in__0[0]), + .Q(state_eios_det[0]), + .S(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[1] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__2_n_0 ), + .D(p_1_in__0[1]), + .Q(state_eios_det[1]), + .R(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[2] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__2_n_0 ), + .D(p_1_in__0[2]), + .Q(state_eios_det[2]), + .R(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[3] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__2_n_0 ), + .D(p_1_in__0[3]), + .Q(state_eios_det[3]), + .R(SR)); + (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) + FDRE \reg_state_eios_det_reg[4] + (.C(pipe_pclk_in), + .CE(\reg_state_eios_det[4]_i_1__2_n_0 ), + .D(p_1_in__0[4]), + .Q(state_eios_det[4]), + .R(SR)); + LUT6 #( + .INIT(64'h0000000000000010)) + reg_symbol_after_eios_i_1__2 + (.I0(\reg_state_eios_det[3]_i_2__2_n_0 ), + .I1(state_eios_det[0]), + .I2(state_eios_det[2]), + .I3(state_eios_det[3]), + .I4(state_eios_det[1]), + .I5(reg_symbol_after_eios_i_2__2_n_0), + .O(reg_symbol_after_eios)); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT2 #( + .INIT(4'hE)) + reg_symbol_after_eios_i_2__2 + (.I0(\reg_state_eios_det[4]_i_3__2_n_0 ), + .I1(state_eios_det[4]), + .O(reg_symbol_after_eios_i_2__2_n_0)); + FDRE reg_symbol_after_eios_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(reg_symbol_after_eios), + .Q(symbol_after_eios), + .R(SR)); +endmodule + +module pcie_7x_0_pcie_7x_0_gt_top + (pipe_rx0_valid_gt, + phy_rdy_n, + pipe_rx1_valid_gt, + pipe_rx2_valid_gt, + pipe_rx3_valid_gt, + gt_rx_phy_status_q_reg, + gt_rxelecidle_q_reg, + gt_rx_phy_status_q_reg_0, + gt_rxelecidle_q_reg_0, + gt_rx_phy_status_q_reg_1, + gt_rxelecidle_q_reg_1, + gt_rx_phy_status_q, + gt_rxelecidle_q, + sys_rst_n, + Q, + \gt_rxdata_q_reg[15] , + \gt_rxdata_q_reg[15]_0 , + \gt_rxdata_q_reg[15]_1 , + \gt_rx_status_q_reg[2] , + \gt_rx_status_q_reg[2]_0 , + \gt_rx_status_q_reg[2]_1 , + \gt_rx_status_q_reg[2]_2 , + D, + gt_rxvalid_q_reg, + gt_rxvalid_q_reg_0, + gt_rxvalid_q_reg_1, + pipe_pclk_sel_out, + USER_RATE_GEN3, + pci_exp_txn, + pci_exp_txp, + PIPE_RXCHANISALIGNED, + pipe_rxoutclk_out, + pipe_txoutclk_out, + sys_rst_n_0, + pipe_pclk_in, + pipe_mmcm_lock_in, + pl_ltssm_state, + pipe_rxusrclk_in, + pipe_dclk_in, + \rate_reg1_reg[0] , + sys_clk, + pipe_oobclk_in, + PIPE_TXELECIDLE, + PIPE_TXCOMPLIANCE, + pci_exp_rxn, + pci_exp_rxp, + PIPE_RXPOLARITY, + pipe_tx_deemph_gt, + pipe_tx_rcvr_det_gt, + PIPE_POWERDOWN, + \cplllock_reg1_reg[3] , + PIPE_TXDATA, + PIPE_TXDATAK, + reset_n_reg1_reg); + output pipe_rx0_valid_gt; + output phy_rdy_n; + output pipe_rx1_valid_gt; + output pipe_rx2_valid_gt; + output pipe_rx3_valid_gt; + output gt_rx_phy_status_q_reg; + output gt_rxelecidle_q_reg; + output gt_rx_phy_status_q_reg_0; + output gt_rxelecidle_q_reg_0; + output gt_rx_phy_status_q_reg_1; + output gt_rxelecidle_q_reg_1; + output gt_rx_phy_status_q; + output gt_rxelecidle_q; + output sys_rst_n; + output [15:0]Q; + output [15:0]\gt_rxdata_q_reg[15] ; + output [15:0]\gt_rxdata_q_reg[15]_0 ; + output [15:0]\gt_rxdata_q_reg[15]_1 ; + output [2:0]\gt_rx_status_q_reg[2] ; + output [2:0]\gt_rx_status_q_reg[2]_0 ; + output [2:0]\gt_rx_status_q_reg[2]_1 ; + output [2:0]\gt_rx_status_q_reg[2]_2 ; + output [1:0]D; + output [1:0]gt_rxvalid_q_reg; + output [1:0]gt_rxvalid_q_reg_0; + output [1:0]gt_rxvalid_q_reg_1; + output [3:0]pipe_pclk_sel_out; + output USER_RATE_GEN3; + output [3:0]pci_exp_txn; + output [3:0]pci_exp_txp; + output [3:0]PIPE_RXCHANISALIGNED; + output [3:0]pipe_rxoutclk_out; + output pipe_txoutclk_out; + output sys_rst_n_0; + input pipe_pclk_in; + input pipe_mmcm_lock_in; + input [5:0]pl_ltssm_state; + input pipe_rxusrclk_in; + input pipe_dclk_in; + input [0:0]\rate_reg1_reg[0] ; + input sys_clk; + input pipe_oobclk_in; + input [3:0]PIPE_TXELECIDLE; + input [3:0]PIPE_TXCOMPLIANCE; + input [3:0]pci_exp_rxn; + input [3:0]pci_exp_rxp; + input [3:0]PIPE_RXPOLARITY; + input pipe_tx_deemph_gt; + input pipe_tx_rcvr_det_gt; + input [7:0]PIPE_POWERDOWN; + input [2:0]\cplllock_reg1_reg[3] ; + input [63:0]PIPE_TXDATA; + input [7:0]PIPE_TXDATAK; + input reset_n_reg1_reg; + + wire [1:0]D; + wire [7:0]PIPE_POWERDOWN; + wire [3:0]PIPE_RXCHANISALIGNED; + wire [3:0]PIPE_RXPOLARITY; + wire [3:0]PIPE_TXCOMPLIANCE; + wire [63:0]PIPE_TXDATA; + wire [7:0]PIPE_TXDATAK; + wire [3:0]PIPE_TXELECIDLE; + wire [15:0]Q; + wire USER_RATE_GEN3; + wire [2:0]\cplllock_reg1_reg[3] ; + wire [13:0]gt_rx_data_k_wire_filter; + wire [111:0]gt_rx_data_wire_filter; + wire [3:0]gt_rx_elec_idle_wire_filter; + wire gt_rx_phy_status_q; + wire gt_rx_phy_status_q_reg; + wire gt_rx_phy_status_q_reg_0; + wire gt_rx_phy_status_q_reg_1; + wire [3:0]gt_rx_phy_status_wire_filter; + wire [2:0]\gt_rx_status_q_reg[2] ; + wire [2:0]\gt_rx_status_q_reg[2]_0 ; + wire [2:0]\gt_rx_status_q_reg[2]_1 ; + wire [2:0]\gt_rx_status_q_reg[2]_2 ; + wire \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ; + wire [15:0]\gt_rxdata_q_reg[15] ; + wire [15:0]\gt_rxdata_q_reg[15]_0 ; + wire [15:0]\gt_rxdata_q_reg[15]_1 ; + wire gt_rxelecidle_q; + wire gt_rxelecidle_q_reg; + wire gt_rxelecidle_q_reg_0; + wire gt_rxelecidle_q_reg_1; + wire [1:0]gt_rxvalid_q_reg; + wire [1:0]gt_rxvalid_q_reg_0; + wire [1:0]gt_rxvalid_q_reg_1; + wire [3:0]pci_exp_rxn; + wire [3:0]pci_exp_rxp; + wire [3:0]pci_exp_txn; + wire [3:0]pci_exp_txp; + wire phy_rdy_n; + wire pipe_dclk_in; + wire \pipe_lane[0].gt_wrapper_i/CPLLPD0 ; + wire \pipe_lane[0].gt_wrapper_i/cpllpd ; + wire \pipe_lane[1].gt_wrapper_i/CPLLPD0 ; + wire \pipe_lane[1].gt_wrapper_i/cpllpd ; + wire \pipe_lane[2].gt_wrapper_i/CPLLPD0 ; + wire \pipe_lane[2].gt_wrapper_i/cpllpd ; + wire \pipe_lane[3].gt_wrapper_i/CPLLPD0 ; + wire \pipe_lane[3].gt_wrapper_i/cpllpd ; + wire pipe_mmcm_lock_in; + wire pipe_oobclk_in; + wire pipe_pclk_in; + wire [3:0]pipe_pclk_sel_out; + wire pipe_rx0_valid_gt; + wire pipe_rx1_valid_gt; + wire pipe_rx2_valid_gt; + wire pipe_rx3_valid_gt; + wire [3:0]pipe_rxoutclk_out; + wire pipe_rxusrclk_in; + wire pipe_tx_deemph_gt; + wire pipe_tx_rcvr_det_gt; + wire pipe_txoutclk_out; + wire pipe_wrapper_i_n_100; + wire pipe_wrapper_i_n_101; + wire pipe_wrapper_i_n_102; + wire pipe_wrapper_i_n_103; + wire pipe_wrapper_i_n_104; + wire pipe_wrapper_i_n_105; + wire pipe_wrapper_i_n_106; + wire pipe_wrapper_i_n_107; + wire pipe_wrapper_i_n_108; + wire pipe_wrapper_i_n_109; + wire pipe_wrapper_i_n_110; + wire pipe_wrapper_i_n_111; + wire pipe_wrapper_i_n_112; + wire pipe_wrapper_i_n_113; + wire pipe_wrapper_i_n_25; + wire pipe_wrapper_i_n_26; + wire pipe_wrapper_i_n_27; + wire [5:0]pl_ltssm_state; + wire [5:0]pl_ltssm_state_q; + wire rate_cpllpd_0; + wire rate_cpllpd_1; + wire rate_cpllpd_2; + wire rate_cpllpd_3; + wire [0:0]\rate_reg1_reg[0] ; + wire reg_clock_locked; + wire reg_clock_locked_i_1_n_0; + wire reset_n_reg1_reg; + wire sys_clk; + wire sys_rst_n; + wire sys_rst_n_0; + + pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst + (.D(D), + .PIPE_RXDATA(gt_rx_data_wire_filter[15:0]), + .PIPE_RXDATAK(gt_rx_data_k_wire_filter[1:0]), + .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[0]), + .PIPE_RXSTATUS({pipe_wrapper_i_n_25,pipe_wrapper_i_n_26,pipe_wrapper_i_n_27}), + .Q(Q), + .SR(phy_rdy_n), + .gt_rx_phy_status_q(gt_rx_phy_status_q), + .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[0]), + .\gt_rx_status_q_reg[0]_0 (pl_ltssm_state_q), + .\gt_rx_status_q_reg[2]_0 (\gt_rx_status_q_reg[2]_2 ), + .gt_rxelecidle_q(gt_rxelecidle_q), + .gt_rxvalid_q_reg_0(pipe_rx0_valid_gt), + .gt_rxvalid_q_reg_1(pipe_wrapper_i_n_110), + .pipe_pclk_in(pipe_pclk_in), + .\pl_ltssm_state_q_reg[5] (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 )); + pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_34 \gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst + (.PIPE_RXDATA(gt_rx_data_wire_filter[47:32]), + .PIPE_RXDATAK(gt_rx_data_k_wire_filter[5:4]), + .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[1]), + .PIPE_RXSTATUS({pipe_wrapper_i_n_100,pipe_wrapper_i_n_101,pipe_wrapper_i_n_102}), + .Q(\gt_rxdata_q_reg[15] ), + .SR(phy_rdy_n), + .gt_rx_phy_status_q_reg_0(gt_rx_phy_status_q_reg), + .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[1]), + .\gt_rx_status_q_reg[0]_0 (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ), + .\gt_rx_status_q_reg[2]_0 (\gt_rx_status_q_reg[2] ), + .gt_rxelecidle_q_reg_0(gt_rxelecidle_q_reg), + .gt_rxvalid_q_reg_0(pipe_rx1_valid_gt), + .gt_rxvalid_q_reg_1(gt_rxvalid_q_reg), + .gt_rxvalid_q_reg_2(pipe_wrapper_i_n_111), + .pipe_pclk_in(pipe_pclk_in)); + pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_35 \gt_rx_valid_filter[2].GT_RX_VALID_FILTER_7x_inst + (.PIPE_RXDATA(gt_rx_data_wire_filter[79:64]), + .PIPE_RXDATAK(gt_rx_data_k_wire_filter[9:8]), + .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[2]), + .PIPE_RXSTATUS({pipe_wrapper_i_n_103,pipe_wrapper_i_n_104,pipe_wrapper_i_n_105}), + .Q(\gt_rxdata_q_reg[15]_0 ), + .SR(phy_rdy_n), + .gt_rx_phy_status_q_reg_0(gt_rx_phy_status_q_reg_0), + .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[2]), + .\gt_rx_status_q_reg[0]_0 (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ), + .\gt_rx_status_q_reg[2]_0 (\gt_rx_status_q_reg[2]_0 ), + .gt_rxelecidle_q_reg_0(gt_rxelecidle_q_reg_0), + .gt_rxvalid_q_reg_0(pipe_rx2_valid_gt), + .gt_rxvalid_q_reg_1(gt_rxvalid_q_reg_0), + .gt_rxvalid_q_reg_2(pipe_wrapper_i_n_112), + .pipe_pclk_in(pipe_pclk_in)); + pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_36 \gt_rx_valid_filter[3].GT_RX_VALID_FILTER_7x_inst + (.PIPE_RXDATA(gt_rx_data_wire_filter[111:96]), + .PIPE_RXDATAK(gt_rx_data_k_wire_filter[13:12]), + .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[3]), + .PIPE_RXSTATUS({pipe_wrapper_i_n_106,pipe_wrapper_i_n_107,pipe_wrapper_i_n_108}), + .Q(\gt_rxdata_q_reg[15]_1 ), + .SR(phy_rdy_n), + .gt_rx_phy_status_q_reg_0(gt_rx_phy_status_q_reg_1), + .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[3]), + .\gt_rx_status_q_reg[0]_0 (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ), + .\gt_rx_status_q_reg[2]_0 (\gt_rx_status_q_reg[2]_1 ), + .gt_rxelecidle_q_reg_0(gt_rxelecidle_q_reg_1), + .gt_rxvalid_q_reg_0(pipe_rx3_valid_gt), + .gt_rxvalid_q_reg_1(gt_rxvalid_q_reg_1), + .gt_rxvalid_q_reg_2(pipe_wrapper_i_n_113), + .pipe_pclk_in(pipe_pclk_in)); + LUT2 #( + .INIT(4'hE)) + \gtx_channel.gtxe2_channel_i_i_1 + (.I0(\pipe_lane[0].gt_wrapper_i/cpllpd ), + .I1(rate_cpllpd_0), + .O(\pipe_lane[0].gt_wrapper_i/CPLLPD0 )); + LUT2 #( + .INIT(4'hE)) + \gtx_channel.gtxe2_channel_i_i_1__0 + (.I0(\pipe_lane[1].gt_wrapper_i/cpllpd ), + .I1(rate_cpllpd_1), + .O(\pipe_lane[1].gt_wrapper_i/CPLLPD0 )); + LUT2 #( + .INIT(4'hE)) + \gtx_channel.gtxe2_channel_i_i_1__1 + (.I0(\pipe_lane[2].gt_wrapper_i/cpllpd ), + .I1(rate_cpllpd_2), + .O(\pipe_lane[2].gt_wrapper_i/CPLLPD0 )); + LUT2 #( + .INIT(4'hE)) + \gtx_channel.gtxe2_channel_i_i_1__2 + (.I0(\pipe_lane[3].gt_wrapper_i/cpllpd ), + .I1(rate_cpllpd_3), + .O(\pipe_lane[3].gt_wrapper_i/CPLLPD0 )); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_29 + (.I0(phy_rdy_n), + .O(sys_rst_n)); + FDRE phy_rdy_n_int_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_wrapper_i_n_109), + .Q(phy_rdy_n), + .R(1'b0)); + pcie_7x_0_pcie_7x_0_pipe_wrapper pipe_wrapper_i + (.CPLLPD0(\pipe_lane[0].gt_wrapper_i/CPLLPD0 ), + .CPLLPD0_3(\pipe_lane[1].gt_wrapper_i/CPLLPD0 ), + .CPLLPD0_4(\pipe_lane[2].gt_wrapper_i/CPLLPD0 ), + .CPLLPD0_5(\pipe_lane[3].gt_wrapper_i/CPLLPD0 ), + .PIPE_POWERDOWN(PIPE_POWERDOWN), + .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED), + .PIPE_RXPOLARITY(PIPE_RXPOLARITY), + .PIPE_RXSTATUS({pipe_wrapper_i_n_25,pipe_wrapper_i_n_26,pipe_wrapper_i_n_27}), + .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE), + .PIPE_TXDATA(PIPE_TXDATA), + .PIPE_TXDATAK(PIPE_TXDATAK), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE), + .\cplllock_reg1_reg[3] (\cplllock_reg1_reg[3] ), + .cpllpd(\pipe_lane[0].gt_wrapper_i/cpllpd ), + .cpllpd_0(\pipe_lane[1].gt_wrapper_i/cpllpd ), + .cpllpd_1(\pipe_lane[2].gt_wrapper_i/cpllpd ), + .cpllpd_2(\pipe_lane[3].gt_wrapper_i/cpllpd ), + .gen3_reg(USER_RATE_GEN3), + .gt_rx_data_k_wire_filter({gt_rx_data_k_wire_filter[13:12],gt_rx_data_k_wire_filter[9:8],gt_rx_data_k_wire_filter[5:4],gt_rx_data_k_wire_filter[1:0]}), + .gt_rx_data_wire_filter({gt_rx_data_wire_filter[111:96],gt_rx_data_wire_filter[79:64],gt_rx_data_wire_filter[47:32],gt_rx_data_wire_filter[15:0]}), + .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter), + .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter), + .gt_rxvalid_q_reg(pipe_wrapper_i_n_110), + .gt_rxvalid_q_reg_0(pipe_wrapper_i_n_111), + .gt_rxvalid_q_reg_1(pipe_wrapper_i_n_112), + .gt_rxvalid_q_reg_2(pipe_wrapper_i_n_113), + .pci_exp_rxn(pci_exp_rxn), + .pci_exp_rxp(pci_exp_rxp), + .pci_exp_txn(pci_exp_txn), + .pci_exp_txp(pci_exp_txp), + .pipe_dclk_in(pipe_dclk_in), + .pipe_dclk_in_0({pipe_wrapper_i_n_100,pipe_wrapper_i_n_101,pipe_wrapper_i_n_102}), + .pipe_dclk_in_1({pipe_wrapper_i_n_103,pipe_wrapper_i_n_104,pipe_wrapper_i_n_105}), + .pipe_dclk_in_2({pipe_wrapper_i_n_106,pipe_wrapper_i_n_107,pipe_wrapper_i_n_108}), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_oobclk_in(pipe_oobclk_in), + .pipe_pclk_in(pipe_pclk_in), + .pipe_pclk_sel_out(pipe_pclk_sel_out), + .pipe_rx0_valid_gt(pipe_rx0_valid_gt), + .pipe_rx1_valid_gt(pipe_rx1_valid_gt), + .pipe_rx2_valid_gt(pipe_rx2_valid_gt), + .pipe_rx3_valid_gt(pipe_rx3_valid_gt), + .pipe_rxoutclk_out(pipe_rxoutclk_out), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .pipe_tx_deemph_gt(pipe_tx_deemph_gt), + .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt), + .pipe_txoutclk_out(pipe_txoutclk_out), + .rate_cpllpd_0(rate_cpllpd_0), + .rate_cpllpd_1(rate_cpllpd_1), + .rate_cpllpd_2(rate_cpllpd_2), + .rate_cpllpd_3(rate_cpllpd_3), + .\rate_reg1_reg[0] (\rate_reg1_reg[0] ), + .reg_clock_locked(reg_clock_locked), + .reg_clock_locked_reg(pipe_wrapper_i_n_109), + .reset_n_reg1_reg_0(sys_rst_n_0), + .sys_clk(sys_clk)); + FDCE \pl_ltssm_state_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .CLR(reg_clock_locked_i_1_n_0), + .D(pl_ltssm_state[0]), + .Q(pl_ltssm_state_q[0])); + FDCE \pl_ltssm_state_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .CLR(reg_clock_locked_i_1_n_0), + .D(pl_ltssm_state[1]), + .Q(pl_ltssm_state_q[1])); + FDCE \pl_ltssm_state_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .CLR(reg_clock_locked_i_1_n_0), + .D(pl_ltssm_state[2]), + .Q(pl_ltssm_state_q[2])); + FDCE \pl_ltssm_state_q_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .CLR(reg_clock_locked_i_1_n_0), + .D(pl_ltssm_state[3]), + .Q(pl_ltssm_state_q[3])); + FDCE \pl_ltssm_state_q_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .CLR(reg_clock_locked_i_1_n_0), + .D(pl_ltssm_state[4]), + .Q(pl_ltssm_state_q[4])); + FDCE \pl_ltssm_state_q_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .CLR(reg_clock_locked_i_1_n_0), + .D(pl_ltssm_state[5]), + .Q(pl_ltssm_state_q[5])); + LUT1 #( + .INIT(2'h1)) + pl_phy_lnk_up_q_i_1 + (.I0(reset_n_reg1_reg), + .O(sys_rst_n_0)); + LUT1 #( + .INIT(2'h1)) + reg_clock_locked_i_1 + (.I0(pipe_mmcm_lock_in), + .O(reg_clock_locked_i_1_n_0)); + FDCE reg_clock_locked_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .CLR(reg_clock_locked_i_1_n_0), + .D(1'b1), + .Q(reg_clock_locked)); +endmodule + +module pcie_7x_0_pcie_7x_0_gt_wrapper + (cpllpd, + QRST_CPLLLOCK, + DRP_RDY, + pci_exp_txn, + pci_exp_txp, + RATE_PHYSTATUS, + gt_rxcdrlock_0, + PIPE_RXCHANISALIGNED, + pipe_dclk_in_0, + gt_rx_elec_idle_wire_filter, + pipe_rxoutclk_out, + SYNC_RXPHALIGNDONE_M, + RATE_RXRATEDONE, + USER_RXRESETDONE, + gt_rxvalid_0, + pipe_dclk_in_1, + pipe_txoutclk_out, + pipe_dclk_in_2, + pipe_dclk_in_3, + RATE_TXRATEDONE, + USER_TXRESETDONE, + DRP_DO, + PIPE_RXSTATUS, + RXCHBONDO, + gt_rx_data_wire_filter, + gt_rx_data_k_wire_filter, + gt_cpllpdrefclk, + CPLLPD0, + pipe_dclk_in, + \cplllock_reg1_reg[0] , + \cplllock_reg1_reg[0]_0 , + sys_clk, + DRP_GTXRESET, + pci_exp_rxn, + pci_exp_rxp, + QPLL_QPLLOUTCLK, + QPLL_QPLLOUTREFCLK, + rxchbonden_0, + \cplllock_reg1_reg[0]_1 , + rate_txpmareset_0, + PIPE_RXPOLARITY, + rst_userrdy, + pipe_rxusrclk_in, + pipe_tx_deemph_gt, + pipe_tx_rcvr_det_gt, + sync_txdlyen_0, + SYNC_TXDLYSRESET, + PIPE_TXELECIDLE, + SYNC_TXPHALIGN, + SYNC_TXPHINIT, + pipe_pclk_in, + DRPDI, + PIPE_POWERDOWN, + RXSYSCLKSEL, + RXRATE, + \cplllock_reg1_reg[0]_2 , + USER_OOBCLK, + TXPOSTCURSOR, + TXPRECURSOR, + PIPE_TXDATA, + TXMAINCURSOR, + PIPE_TXCOMPLIANCE, + PIPE_TXDATAK, + DRPADDR, + rate_cpllreset_0, + RST_CPLLRESET); + output cpllpd; + output [0:0]QRST_CPLLLOCK; + output DRP_RDY; + output [0:0]pci_exp_txn; + output [0:0]pci_exp_txp; + output RATE_PHYSTATUS; + output gt_rxcdrlock_0; + output [0:0]PIPE_RXCHANISALIGNED; + output pipe_dclk_in_0; + output [0:0]gt_rx_elec_idle_wire_filter; + output [0:0]pipe_rxoutclk_out; + output SYNC_RXPHALIGNDONE_M; + output RATE_RXRATEDONE; + output USER_RXRESETDONE; + output gt_rxvalid_0; + output pipe_dclk_in_1; + output pipe_txoutclk_out; + output pipe_dclk_in_2; + output pipe_dclk_in_3; + output RATE_TXRATEDONE; + output USER_TXRESETDONE; + output [15:0]DRP_DO; + output [2:0]PIPE_RXSTATUS; + output [4:0]RXCHBONDO; + output [15:0]gt_rx_data_wire_filter; + output [1:0]gt_rx_data_k_wire_filter; + input gt_cpllpdrefclk; + input CPLLPD0; + input pipe_dclk_in; + input \cplllock_reg1_reg[0] ; + input \cplllock_reg1_reg[0]_0 ; + input sys_clk; + input DRP_GTXRESET; + input [0:0]pci_exp_rxn; + input [0:0]pci_exp_rxp; + input QPLL_QPLLOUTCLK; + input QPLL_QPLLOUTREFCLK; + input rxchbonden_0; + input \cplllock_reg1_reg[0]_1 ; + input rate_txpmareset_0; + input [0:0]PIPE_RXPOLARITY; + input rst_userrdy; + input pipe_rxusrclk_in; + input pipe_tx_deemph_gt; + input pipe_tx_rcvr_det_gt; + input sync_txdlyen_0; + input SYNC_TXDLYSRESET; + input [0:0]PIPE_TXELECIDLE; + input SYNC_TXPHALIGN; + input SYNC_TXPHINIT; + input pipe_pclk_in; + input [15:0]DRPDI; + input [1:0]PIPE_POWERDOWN; + input [0:0]RXSYSCLKSEL; + input [0:0]RXRATE; + input [2:0]\cplllock_reg1_reg[0]_2 ; + input USER_OOBCLK; + input [4:0]TXPOSTCURSOR; + input [4:0]TXPRECURSOR; + input [15:0]PIPE_TXDATA; + input [6:0]TXMAINCURSOR; + input [0:0]PIPE_TXCOMPLIANCE; + input [1:0]PIPE_TXDATAK; + input [7:0]DRPADDR; + input rate_cpllreset_0; + input RST_CPLLRESET; + + wire CPLLPD0; + wire CPLLRESET0; + wire [7:0]DRPADDR; + wire [15:0]DRPDI; + wire [15:0]DRP_DO; + wire DRP_GTXRESET; + wire DRP_RDY; + wire [1:0]PIPE_POWERDOWN; + wire [0:0]PIPE_RXCHANISALIGNED; + wire [0:0]PIPE_RXPOLARITY; + wire [2:0]PIPE_RXSTATUS; + wire [0:0]PIPE_TXCOMPLIANCE; + wire [15:0]PIPE_TXDATA; + wire [1:0]PIPE_TXDATAK; + wire [0:0]PIPE_TXELECIDLE; + wire QPLL_QPLLOUTCLK; + wire QPLL_QPLLOUTREFCLK; + wire [0:0]QRST_CPLLLOCK; + wire RATE_PHYSTATUS; + wire RATE_RXRATEDONE; + wire RATE_TXRATEDONE; + wire RST_CPLLRESET; + wire [4:0]RXCHBONDO; + wire [0:0]RXRATE; + wire [0:0]RXSYSCLKSEL; + wire SYNC_RXPHALIGNDONE_M; + wire SYNC_TXDLYSRESET; + wire SYNC_TXPHALIGN; + wire SYNC_TXPHINIT; + wire [6:0]TXMAINCURSOR; + wire [4:0]TXPOSTCURSOR; + wire [4:0]TXPRECURSOR; + wire USER_OOBCLK; + wire USER_RXRESETDONE; + wire USER_TXRESETDONE; + wire \cplllock_reg1_reg[0] ; + wire \cplllock_reg1_reg[0]_0 ; + wire \cplllock_reg1_reg[0]_1 ; + wire [2:0]\cplllock_reg1_reg[0]_2 ; + wire cpllpd; + wire gt_cpllpdrefclk; + wire [1:0]gt_rx_data_k_wire_filter; + wire [15:0]gt_rx_data_wire_filter; + wire [0:0]gt_rx_elec_idle_wire_filter; + wire gt_rxcdrlock_0; + wire gt_rxvalid_0; + wire \gtx_channel.gtxe2_channel_i_n_10 ; + wire \gtx_channel.gtxe2_channel_i_n_138 ; + wire \gtx_channel.gtxe2_channel_i_n_139 ; + wire \gtx_channel.gtxe2_channel_i_n_140 ; + wire \gtx_channel.gtxe2_channel_i_n_141 ; + wire \gtx_channel.gtxe2_channel_i_n_142 ; + wire \gtx_channel.gtxe2_channel_i_n_143 ; + wire \gtx_channel.gtxe2_channel_i_n_144 ; + wire \gtx_channel.gtxe2_channel_i_n_145 ; + wire \gtx_channel.gtxe2_channel_i_n_146 ; + wire \gtx_channel.gtxe2_channel_i_n_147 ; + wire \gtx_channel.gtxe2_channel_i_n_148 ; + wire \gtx_channel.gtxe2_channel_i_n_149 ; + wire \gtx_channel.gtxe2_channel_i_n_150 ; + wire \gtx_channel.gtxe2_channel_i_n_151 ; + wire \gtx_channel.gtxe2_channel_i_n_152 ; + wire \gtx_channel.gtxe2_channel_i_n_153 ; + wire \gtx_channel.gtxe2_channel_i_n_16 ; + wire \gtx_channel.gtxe2_channel_i_n_177 ; + wire \gtx_channel.gtxe2_channel_i_n_178 ; + wire \gtx_channel.gtxe2_channel_i_n_179 ; + wire \gtx_channel.gtxe2_channel_i_n_180 ; + wire \gtx_channel.gtxe2_channel_i_n_181 ; + wire \gtx_channel.gtxe2_channel_i_n_182 ; + wire \gtx_channel.gtxe2_channel_i_n_183 ; + wire \gtx_channel.gtxe2_channel_i_n_184 ; + wire \gtx_channel.gtxe2_channel_i_n_189 ; + wire \gtx_channel.gtxe2_channel_i_n_190 ; + wire \gtx_channel.gtxe2_channel_i_n_191 ; + wire \gtx_channel.gtxe2_channel_i_n_192 ; + wire \gtx_channel.gtxe2_channel_i_n_197 ; + wire \gtx_channel.gtxe2_channel_i_n_198 ; + wire \gtx_channel.gtxe2_channel_i_n_201 ; + wire \gtx_channel.gtxe2_channel_i_n_202 ; + wire \gtx_channel.gtxe2_channel_i_n_203 ; + wire \gtx_channel.gtxe2_channel_i_n_204 ; + wire \gtx_channel.gtxe2_channel_i_n_205 ; + wire \gtx_channel.gtxe2_channel_i_n_206 ; + wire \gtx_channel.gtxe2_channel_i_n_207 ; + wire \gtx_channel.gtxe2_channel_i_n_208 ; + wire \gtx_channel.gtxe2_channel_i_n_209 ; + wire \gtx_channel.gtxe2_channel_i_n_210 ; + wire \gtx_channel.gtxe2_channel_i_n_211 ; + wire \gtx_channel.gtxe2_channel_i_n_212 ; + wire \gtx_channel.gtxe2_channel_i_n_213 ; + wire \gtx_channel.gtxe2_channel_i_n_214 ; + wire \gtx_channel.gtxe2_channel_i_n_215 ; + wire \gtx_channel.gtxe2_channel_i_n_216 ; + wire \gtx_channel.gtxe2_channel_i_n_27 ; + wire \gtx_channel.gtxe2_channel_i_n_4 ; + wire \gtx_channel.gtxe2_channel_i_n_82 ; + wire \gtx_channel.gtxe2_channel_i_n_83 ; + wire \gtx_channel.gtxe2_channel_i_n_84 ; + wire \gtx_channel.gtxe2_channel_i_n_9 ; + wire [0:0]pci_exp_rxn; + wire [0:0]pci_exp_rxp; + wire [0:0]pci_exp_txn; + wire [0:0]pci_exp_txp; + wire pipe_dclk_in; + wire pipe_dclk_in_0; + wire pipe_dclk_in_1; + wire pipe_dclk_in_2; + wire pipe_dclk_in_3; + wire pipe_pclk_in; + wire [0:0]pipe_rxoutclk_out; + wire pipe_rxusrclk_in; + wire pipe_tx_deemph_gt; + wire pipe_tx_rcvr_det_gt; + wire pipe_txoutclk_out; + wire rate_cpllreset_0; + wire rate_txpmareset_0; + wire rst_userrdy; + wire rxchbonden_0; + wire sync_txdlyen_0; + wire sys_clk; + wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ; + wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ; + wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ; + wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ; + wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ; + wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ; + wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ; + wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ; + wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ; + wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ; + wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ; + wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ; + + pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_60 cpllPDInst + (.CPLLRESET0(CPLLRESET0), + .RST_CPLLRESET(RST_CPLLRESET), + .cpllpd(cpllpd), + .gt_cpllpdrefclk(gt_cpllpdrefclk), + .rate_cpllreset_0(rate_cpllreset_0)); + (* BOX_TYPE = "PRIMITIVE" *) + GTXE2_CHANNEL #( + .ALIGN_COMMA_DOUBLE("FALSE"), + .ALIGN_COMMA_ENABLE(10'b1111111111), + .ALIGN_COMMA_WORD(1), + .ALIGN_MCOMMA_DET("TRUE"), + .ALIGN_MCOMMA_VALUE(10'b1010000011), + .ALIGN_PCOMMA_DET("TRUE"), + .ALIGN_PCOMMA_VALUE(10'b0101111100), + .CBCC_DATA_SOURCE_SEL("DECODED"), + .CHAN_BOND_KEEP_ALIGN("TRUE"), + .CHAN_BOND_MAX_SKEW(7), + .CHAN_BOND_SEQ_1_1(10'b0001001010), + .CHAN_BOND_SEQ_1_2(10'b0001001010), + .CHAN_BOND_SEQ_1_3(10'b0001001010), + .CHAN_BOND_SEQ_1_4(10'b0110111100), + .CHAN_BOND_SEQ_1_ENABLE(4'b1111), + .CHAN_BOND_SEQ_2_1(10'b0001000101), + .CHAN_BOND_SEQ_2_2(10'b0001000101), + .CHAN_BOND_SEQ_2_3(10'b0001000101), + .CHAN_BOND_SEQ_2_4(10'b0110111100), + .CHAN_BOND_SEQ_2_ENABLE(4'b1111), + .CHAN_BOND_SEQ_2_USE("TRUE"), + .CHAN_BOND_SEQ_LEN(4), + .CLK_CORRECT_USE("TRUE"), + .CLK_COR_KEEP_IDLE("TRUE"), + .CLK_COR_MAX_LAT(20), + .CLK_COR_MIN_LAT(18), + .CLK_COR_PRECEDENCE("TRUE"), + .CLK_COR_REPEAT_WAIT(0), + .CLK_COR_SEQ_1_1(10'b0100011100), + .CLK_COR_SEQ_1_2(10'b0000000000), + .CLK_COR_SEQ_1_3(10'b0000000000), + .CLK_COR_SEQ_1_4(10'b0000000000), + .CLK_COR_SEQ_1_ENABLE(4'b1111), + .CLK_COR_SEQ_2_1(10'b0000000000), + .CLK_COR_SEQ_2_2(10'b0000000000), + .CLK_COR_SEQ_2_3(10'b0000000000), + .CLK_COR_SEQ_2_4(10'b0000000000), + .CLK_COR_SEQ_2_ENABLE(4'b0000), + .CLK_COR_SEQ_2_USE("FALSE"), + .CLK_COR_SEQ_LEN(1), + .CPLL_CFG(24'hA407CC), + .CPLL_FBDIV(5), + .CPLL_FBDIV_45(5), + .CPLL_INIT_CFG(24'h00001E), + .CPLL_LOCK_CFG(16'h01E8), + .CPLL_REFCLK_DIV(1), + .DEC_MCOMMA_DETECT("TRUE"), + .DEC_PCOMMA_DETECT("TRUE"), + .DEC_VALID_COMMA_ONLY("FALSE"), + .DMONITOR_CFG(24'h000B01), + .ES_CONTROL(6'b000000), + .ES_ERRDET_EN("FALSE"), + .ES_EYE_SCAN_EN("FALSE"), + .ES_HORZ_OFFSET(12'h000), + .ES_PMA_CFG(10'b0000000000), + .ES_PRESCALE(5'b00000), + .ES_QUALIFIER(80'h00000000000000000000), + .ES_QUAL_MASK(80'h00000000000000000000), + .ES_SDATA_MASK(80'h00000000000000000000), + .ES_VERT_OFFSET(9'b000000000), + .FTS_DESKEW_SEQ_ENABLE(4'b1111), + .FTS_LANE_DESKEW_CFG(4'b1111), + .FTS_LANE_DESKEW_EN("TRUE"), + .GEARBOX_MODE(3'b000), + .IS_CPLLLOCKDETCLK_INVERTED(1'b0), + .IS_DRPCLK_INVERTED(1'b0), + .IS_GTGREFCLK_INVERTED(1'b0), + .IS_RXUSRCLK2_INVERTED(1'b0), + .IS_RXUSRCLK_INVERTED(1'b0), + .IS_TXPHDLYTSTCLK_INVERTED(1'b0), + .IS_TXUSRCLK2_INVERTED(1'b0), + .IS_TXUSRCLK_INVERTED(1'b0), + .OUTREFCLK_SEL_INV(2'b11), + .PCS_PCIE_EN("TRUE"), + .PCS_RSVD_ATTR(48'h0000000001CF), + .PD_TRANS_TIME_FROM_P2(12'h03C), + .PD_TRANS_TIME_NONE_P2(8'h09), + .PD_TRANS_TIME_TO_P2(8'h64), + .PMA_RSV(32'h00018480), + .PMA_RSV2(16'h2050), + .PMA_RSV3(2'b00), + .PMA_RSV4(32'h00000000), + .RXBUFRESET_TIME(5'b00001), + .RXBUF_ADDR_MODE("FULL"), + .RXBUF_EIDLE_HI_CNT(4'b0100), + .RXBUF_EIDLE_LO_CNT(4'b0000), + .RXBUF_EN("TRUE"), + .RXBUF_RESET_ON_CB_CHANGE("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN("FALSE"), + .RXBUF_RESET_ON_EIDLE("TRUE"), + .RXBUF_RESET_ON_RATE_CHANGE("TRUE"), + .RXBUF_THRESH_OVFLW(61), + .RXBUF_THRESH_OVRD("FALSE"), + .RXBUF_THRESH_UNDFLW(4), + .RXCDRFREQRESET_TIME(5'b00001), + .RXCDRPHRESET_TIME(5'b00001), + .RXCDR_CFG(72'h03000023FF10200020), + .RXCDR_FR_RESET_ON_EIDLE(1'b0), + .RXCDR_HOLD_DURING_EIDLE(1'b1), + .RXCDR_LOCK_CFG(6'b010101), + .RXCDR_PH_RESET_ON_EIDLE(1'b0), + .RXDFELPMRESET_TIME(7'b0001111), + .RXDLY_CFG(16'h001F), + .RXDLY_LCFG(9'h030), + .RXDLY_TAP_CFG(16'h0000), + .RXGEARBOX_EN("FALSE"), + .RXISCANRESET_TIME(5'b00001), + .RXLPM_HF_CFG(14'b00000011110000), + .RXLPM_LF_CFG(14'b00000011110000), + .RXOOB_CFG(7'b0000110), + .RXOUT_DIV(2), + .RXPCSRESET_TIME(5'b00001), + .RXPHDLY_CFG(24'h004020), + .RXPH_CFG(24'h000000), + .RXPH_MONITOR_SEL(5'b00000), + .RXPMARESET_TIME(5'b00011), + .RXPRBS_ERR_LOOPBACK(1'b0), + .RXSLIDE_AUTO_WAIT(7), + .RXSLIDE_MODE("PMA"), + .RX_BIAS_CFG(12'b000000000100), + .RX_BUFFER_CFG(6'b000000), + .RX_CLK25_DIV(4), + .RX_CLKMUX_PD(1'b1), + .RX_CM_SEL(2'b11), + .RX_CM_TRIM(3'b010), + .RX_DATA_WIDTH(20), + .RX_DDI_SEL(6'b000000), + .RX_DEBUG_CFG(12'b000000000000), + .RX_DEFER_RESET_BUF_EN("TRUE"), + .RX_DFE_GAIN_CFG(23'h020FEA), + .RX_DFE_H2_CFG(12'b000000000000), + .RX_DFE_H3_CFG(12'b000001000000), + .RX_DFE_H4_CFG(11'b00011110000), + .RX_DFE_H5_CFG(11'b00011100000), + .RX_DFE_KL_CFG(13'b0000011111110), + .RX_DFE_KL_CFG2(32'h3290D86C), + .RX_DFE_LPM_CFG(16'h0954), + .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1), + .RX_DFE_UT_CFG(17'b10001111000000000), + .RX_DFE_VP_CFG(17'b00011111100000011), + .RX_DFE_XYD_CFG(13'b0000000000000), + .RX_DISPERR_SEQ_MATCH("TRUE"), + .RX_INT_DATAWIDTH(0), + .RX_OS_CFG(13'b0000010000000), + .RX_SIG_VALID_DLY(4), + .RX_XCLK_SEL("RXREC"), + .SAS_MAX_COM(64), + .SAS_MIN_COM(36), + .SATA_BURST_SEQ_LEN(4'b1111), + .SATA_BURST_VAL(3'b100), + .SATA_CPLL_CFG("VCO_3000MHZ"), + .SATA_EIDLE_VAL(3'b100), + .SATA_MAX_BURST(8), + .SATA_MAX_INIT(21), + .SATA_MAX_WAKE(7), + .SATA_MIN_BURST(4), + .SATA_MIN_INIT(12), + .SATA_MIN_WAKE(4), + .SHOW_REALIGN_COMMA("FALSE"), + .SIM_CPLLREFCLK_SEL(3'b001), + .SIM_RECEIVER_DETECT_PASS("TRUE"), + .SIM_RESET_SPEEDUP("FALSE"), + .SIM_TX_EIDLE_DRIVE_LEVEL("1"), + .SIM_VERSION("3.0"), + .TERM_RCAL_CFG(5'b10000), + .TERM_RCAL_OVRD(1'b0), + .TRANS_TIME_RATE(8'h0E), + .TST_RSV(32'h00000000), + .TXBUF_EN("FALSE"), + .TXBUF_RESET_ON_RATE_CHANGE("TRUE"), + .TXDLY_CFG(16'h001F), + .TXDLY_LCFG(9'h030), + .TXDLY_TAP_CFG(16'h0000), + .TXGEARBOX_EN("FALSE"), + .TXOUT_DIV(2), + .TXPCSRESET_TIME(5'b00001), + .TXPHDLY_CFG(24'h084020), + .TXPH_CFG(16'h0780), + .TXPH_MONITOR_SEL(5'b00000), + .TXPMARESET_TIME(5'b00011), + .TX_CLK25_DIV(4), + .TX_CLKMUX_PD(1'b1), + .TX_DATA_WIDTH(20), + .TX_DEEMPH0(5'b10100), + .TX_DEEMPH1(5'b01011), + .TX_DRIVE_MODE("PIPE"), + .TX_EIDLE_ASSERT_DELAY(3'b010), + .TX_EIDLE_DEASSERT_DELAY(3'b100), + .TX_INT_DATAWIDTH(0), + .TX_LOOPBACK_DRIVE_HIZ("FALSE"), + .TX_MAINCURSOR_SEL(1'b0), + .TX_MARGIN_FULL_0(7'b1001111), + .TX_MARGIN_FULL_1(7'b1001110), + .TX_MARGIN_FULL_2(7'b1001101), + .TX_MARGIN_FULL_3(7'b1001100), + .TX_MARGIN_FULL_4(7'b1000011), + .TX_MARGIN_LOW_0(7'b1000101), + .TX_MARGIN_LOW_1(7'b1000110), + .TX_MARGIN_LOW_2(7'b1000011), + .TX_MARGIN_LOW_3(7'b1000010), + .TX_MARGIN_LOW_4(7'b1000000), + .TX_PREDRIVER_MODE(1'b0), + .TX_QPI_STATUS_EN(1'b0), + .TX_RXDETECT_CFG(14'h0064), + .TX_RXDETECT_REF(3'b011), + .TX_XCLK_SEL("TXUSR"), + .UCODEER_CLR(1'b0)) + \gtx_channel.gtxe2_channel_i + (.CFGRESET(1'b0), + .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}), + .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ), + .CPLLLOCK(QRST_CPLLLOCK), + .CPLLLOCKDETCLK(1'b0), + .CPLLLOCKEN(1'b1), + .CPLLPD(CPLLPD0), + .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ), + .CPLLREFCLKSEL({1'b0,1'b0,1'b1}), + .CPLLRESET(CPLLRESET0), + .DMONITOROUT({\gtx_channel.gtxe2_channel_i_n_177 ,\gtx_channel.gtxe2_channel_i_n_178 ,\gtx_channel.gtxe2_channel_i_n_179 ,\gtx_channel.gtxe2_channel_i_n_180 ,\gtx_channel.gtxe2_channel_i_n_181 ,\gtx_channel.gtxe2_channel_i_n_182 ,\gtx_channel.gtxe2_channel_i_n_183 ,\gtx_channel.gtxe2_channel_i_n_184 }), + .DRPADDR({1'b0,DRPADDR}), + .DRPCLK(pipe_dclk_in), + .DRPDI(DRPDI), + .DRPDO(DRP_DO), + .DRPEN(\cplllock_reg1_reg[0] ), + .DRPRDY(DRP_RDY), + .DRPWE(\cplllock_reg1_reg[0]_0 ), + .EYESCANDATAERROR(\gtx_channel.gtxe2_channel_i_n_4 ), + .EYESCANMODE(1'b0), + .EYESCANRESET(1'b0), + .EYESCANTRIGGER(1'b0), + .GTGREFCLK(1'b0), + .GTNORTHREFCLK0(1'b0), + .GTNORTHREFCLK1(1'b0), + .GTREFCLK0(sys_clk), + .GTREFCLK1(1'b0), + .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ), + .GTRESETSEL(1'b0), + .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .GTRXRESET(DRP_GTXRESET), + .GTSOUTHREFCLK0(1'b0), + .GTSOUTHREFCLK1(1'b0), + .GTTXRESET(DRP_GTXRESET), + .GTXRXN(pci_exp_rxn), + .GTXRXP(pci_exp_rxp), + .GTXTXN(pci_exp_txn), + .GTXTXP(pci_exp_txp), + .LOOPBACK({1'b0,1'b0,1'b0}), + .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), + .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]), + .PHYSTATUS(RATE_PHYSTATUS), + .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}), + .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), + .QPLLCLK(QPLL_QPLLOUTCLK), + .QPLLREFCLK(QPLL_QPLLOUTREFCLK), + .RESETOVRD(1'b0), + .RX8B10BEN(rxchbonden_0), + .RXBUFRESET(1'b0), + .RXBUFSTATUS({\gtx_channel.gtxe2_channel_i_n_82 ,\gtx_channel.gtxe2_channel_i_n_83 ,\gtx_channel.gtxe2_channel_i_n_84 }), + .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ), + .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ), + .RXCDRFREQRESET(1'b0), + .RXCDRHOLD(1'b0), + .RXCDRLOCK(gt_rxcdrlock_0), + .RXCDROVRDEN(1'b0), + .RXCDRRESET(1'b0), + .RXCDRRESETRSV(1'b0), + .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ), + .RXCHANISALIGNED(PIPE_RXCHANISALIGNED), + .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ), + .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }), + .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,gt_rx_data_k_wire_filter}), + .RXCHBONDEN(rxchbonden_0), + .RXCHBONDI({1'b0,1'b0,1'b0,1'b0,1'b0}), + .RXCHBONDLEVEL({1'b0,1'b0,1'b1}), + .RXCHBONDMASTER(rxchbonden_0), + .RXCHBONDO(RXCHBONDO), + .RXCHBONDSLAVE(1'b0), + .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]), + .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ), + .RXCOMMADET(\gtx_channel.gtxe2_channel_i_n_16 ), + .RXCOMMADETEN(1'b1), + .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ), + .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ), + .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,gt_rx_data_wire_filter}), + .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ), + .RXDDIEN(1'b0), + .RXDFEAGCHOLD(\cplllock_reg1_reg[0]_1 ), + .RXDFEAGCOVRDEN(1'b0), + .RXDFECM1EN(1'b0), + .RXDFELFHOLD(1'b0), + .RXDFELFOVRDEN(1'b1), + .RXDFELPMRESET(1'b0), + .RXDFETAP2HOLD(1'b0), + .RXDFETAP2OVRDEN(1'b0), + .RXDFETAP3HOLD(1'b0), + .RXDFETAP3OVRDEN(1'b0), + .RXDFETAP4HOLD(1'b0), + .RXDFETAP4OVRDEN(1'b0), + .RXDFETAP5HOLD(1'b0), + .RXDFETAP5OVRDEN(1'b0), + .RXDFEUTHOLD(1'b0), + .RXDFEUTOVRDEN(1'b0), + .RXDFEVPHOLD(1'b0), + .RXDFEVPOVRDEN(1'b0), + .RXDFEVSEN(1'b0), + .RXDFEXYDEN(1'b0), + .RXDFEXYDHOLD(1'b0), + .RXDFEXYDOVRDEN(1'b0), + .RXDISPERR({\gtx_channel.gtxe2_channel_i_n_201 ,\gtx_channel.gtxe2_channel_i_n_202 ,\gtx_channel.gtxe2_channel_i_n_203 ,\gtx_channel.gtxe2_channel_i_n_204 ,\gtx_channel.gtxe2_channel_i_n_205 ,\gtx_channel.gtxe2_channel_i_n_206 ,\gtx_channel.gtxe2_channel_i_n_207 ,\gtx_channel.gtxe2_channel_i_n_208 }), + .RXDLYBYPASS(1'b1), + .RXDLYEN(1'b0), + .RXDLYOVRDEN(1'b0), + .RXDLYSRESET(1'b0), + .RXDLYSRESETDONE(pipe_dclk_in_0), + .RXELECIDLE(gt_rx_elec_idle_wire_filter), + .RXELECIDLEMODE({1'b0,1'b0}), + .RXGEARBOXSLIP(1'b0), + .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]), + .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ), + .RXLPMEN(rxchbonden_0), + .RXLPMHFHOLD(1'b0), + .RXLPMHFOVRDEN(1'b0), + .RXLPMLFHOLD(1'b0), + .RXLPMLFKLOVRDEN(1'b0), + .RXMCOMMAALIGNEN(rxchbonden_0), + .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]), + .RXMONITORSEL({1'b0,1'b0}), + .RXNOTINTABLE({\gtx_channel.gtxe2_channel_i_n_209 ,\gtx_channel.gtxe2_channel_i_n_210 ,\gtx_channel.gtxe2_channel_i_n_211 ,\gtx_channel.gtxe2_channel_i_n_212 ,\gtx_channel.gtxe2_channel_i_n_213 ,\gtx_channel.gtxe2_channel_i_n_214 ,\gtx_channel.gtxe2_channel_i_n_215 ,\gtx_channel.gtxe2_channel_i_n_216 }), + .RXOOBRESET(1'b0), + .RXOSHOLD(1'b0), + .RXOSOVRDEN(1'b0), + .RXOUTCLK(pipe_rxoutclk_out), + .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ), + .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ), + .RXOUTCLKSEL({1'b0,1'b0,1'b0}), + .RXPCOMMAALIGNEN(rxchbonden_0), + .RXPCSRESET(1'b0), + .RXPD(PIPE_POWERDOWN), + .RXPHALIGN(1'b0), + .RXPHALIGNDONE(SYNC_RXPHALIGNDONE_M), + .RXPHALIGNEN(1'b0), + .RXPHDLYPD(1'b0), + .RXPHDLYRESET(1'b0), + .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]), + .RXPHOVRDEN(1'b0), + .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]), + .RXPMARESET(rate_txpmareset_0), + .RXPOLARITY(PIPE_RXPOLARITY), + .RXPRBSCNTRESET(1'b0), + .RXPRBSERR(\gtx_channel.gtxe2_channel_i_n_27 ), + .RXPRBSSEL({1'b0,1'b0,1'b0}), + .RXQPIEN(1'b0), + .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ), + .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ), + .RXRATE({1'b0,1'b0,RXRATE}), + .RXRATEDONE(RATE_RXRATEDONE), + .RXRESETDONE(USER_RXRESETDONE), + .RXSLIDE(1'b0), + .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ), + .RXSTATUS(PIPE_RXSTATUS), + .RXSYSCLKSEL({1'b0,RXSYSCLKSEL}), + .RXUSERRDY(rst_userrdy), + .RXUSRCLK(pipe_rxusrclk_in), + .RXUSRCLK2(pipe_rxusrclk_in), + .RXVALID(gt_rxvalid_0), + .SETERRSTATUS(1'b0), + .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]), + .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .TX8B10BEN(rxchbonden_0), + .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}), + .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]), + .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}), + .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}), + .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ), + .TXCOMINIT(1'b0), + .TXCOMSAS(1'b0), + .TXCOMWAKE(1'b0), + .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}), + .TXDEEMPH(pipe_tx_deemph_gt), + .TXDETECTRX(pipe_tx_rcvr_det_gt), + .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}), + .TXDIFFPD(1'b0), + .TXDLYBYPASS(1'b0), + .TXDLYEN(sync_txdlyen_0), + .TXDLYHOLD(1'b0), + .TXDLYOVRDEN(1'b0), + .TXDLYSRESET(SYNC_TXDLYSRESET), + .TXDLYSRESETDONE(pipe_dclk_in_1), + .TXDLYUPDOWN(1'b0), + .TXELECIDLE(PIPE_TXELECIDLE), + .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ), + .TXHEADER({1'b0,1'b0,1'b0}), + .TXINHIBIT(1'b0), + .TXMAINCURSOR(TXMAINCURSOR), + .TXMARGIN(\cplllock_reg1_reg[0]_2 ), + .TXOUTCLK(pipe_txoutclk_out), + .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ), + .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ), + .TXOUTCLKSEL({1'b0,1'b1,1'b1}), + .TXPCSRESET(1'b0), + .TXPD(PIPE_POWERDOWN), + .TXPDELECIDLEMODE(1'b0), + .TXPHALIGN(SYNC_TXPHALIGN), + .TXPHALIGNDONE(pipe_dclk_in_2), + .TXPHALIGNEN(1'b1), + .TXPHDLYPD(1'b0), + .TXPHDLYRESET(1'b0), + .TXPHDLYTSTCLK(1'b0), + .TXPHINIT(SYNC_TXPHINIT), + .TXPHINITDONE(pipe_dclk_in_3), + .TXPHOVRDEN(1'b0), + .TXPISOPD(1'b0), + .TXPMARESET(rate_txpmareset_0), + .TXPOLARITY(1'b0), + .TXPOSTCURSOR(TXPOSTCURSOR), + .TXPOSTCURSORINV(1'b0), + .TXPRBSFORCEERR(1'b0), + .TXPRBSSEL({1'b0,1'b0,1'b0}), + .TXPRECURSOR(TXPRECURSOR), + .TXPRECURSORINV(1'b0), + .TXQPIBIASEN(1'b0), + .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ), + .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ), + .TXQPISTRONGPDOWN(1'b0), + .TXQPIWEAKPUP(1'b0), + .TXRATE({1'b0,1'b0,RXRATE}), + .TXRATEDONE(RATE_TXRATEDONE), + .TXRESETDONE(USER_TXRESETDONE), + .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .TXSTARTSEQ(1'b0), + .TXSWING(1'b0), + .TXSYSCLKSEL({1'b0,RXSYSCLKSEL}), + .TXUSERRDY(rst_userrdy), + .TXUSRCLK(pipe_pclk_in), + .TXUSRCLK2(pipe_pclk_in)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_gt_wrapper" *) +module pcie_7x_0_pcie_7x_0_gt_wrapper_37 + (cpllpd_0, + QRST_CPLLLOCK, + DRP_RDY, + pci_exp_txn, + pci_exp_txp, + RATE_PHYSTATUS, + gt_rxcdrlock_1, + PIPE_RXCHANISALIGNED, + pipe_dclk_in_0, + gt_rx_elec_idle_wire_filter, + pipe_rxoutclk_out, + pipe_dclk_in_1, + RATE_RXRATEDONE, + USER_RXRESETDONE, + gt_rxvalid_1, + pipe_dclk_in_2, + pipe_dclk_in_3, + pipe_dclk_in_4, + RATE_TXRATEDONE, + USER_TXRESETDONE, + DRP_DO, + pipe_dclk_in_5, + gt_rx_data_wire_filter, + gt_rx_data_k_wire_filter, + gt_cpllpdrefclk, + CPLLPD0_3, + pipe_dclk_in, + \cplllock_reg1_reg[1] , + \cplllock_reg1_reg[1]_0 , + sys_clk, + DRP_GTXRESET, + pci_exp_rxn, + pci_exp_rxp, + QPLL_QPLLOUTCLK, + QPLL_QPLLOUTREFCLK, + rxchbonden_1, + \cplllock_reg1_reg[1]_1 , + rate_txpmareset_1, + PIPE_RXPOLARITY, + rst_userrdy, + pipe_rxusrclk_in, + pipe_tx_deemph_gt, + pipe_tx_rcvr_det_gt, + SYNC_TXDLYSRESET, + PIPE_TXELECIDLE, + SYNC_TXPHALIGN, + SYNC_TXPHINIT, + pipe_pclk_in, + DRPDI, + PIPE_POWERDOWN, + RXSYSCLKSEL, + RXRATE, + \cplllock_reg1_reg[1]_2 , + USER_OOBCLK, + RXCHBONDO, + TXPOSTCURSOR, + TXPRECURSOR, + PIPE_TXDATA, + TXMAINCURSOR, + PIPE_TXCOMPLIANCE, + PIPE_TXDATAK, + DRPADDR, + rate_cpllreset_1, + RST_CPLLRESET); + output cpllpd_0; + output [0:0]QRST_CPLLLOCK; + output DRP_RDY; + output [0:0]pci_exp_txn; + output [0:0]pci_exp_txp; + output RATE_PHYSTATUS; + output gt_rxcdrlock_1; + output [0:0]PIPE_RXCHANISALIGNED; + output pipe_dclk_in_0; + output [0:0]gt_rx_elec_idle_wire_filter; + output [0:0]pipe_rxoutclk_out; + output pipe_dclk_in_1; + output RATE_RXRATEDONE; + output USER_RXRESETDONE; + output gt_rxvalid_1; + output pipe_dclk_in_2; + output pipe_dclk_in_3; + output pipe_dclk_in_4; + output RATE_TXRATEDONE; + output USER_TXRESETDONE; + output [15:0]DRP_DO; + output [2:0]pipe_dclk_in_5; + output [15:0]gt_rx_data_wire_filter; + output [1:0]gt_rx_data_k_wire_filter; + input gt_cpllpdrefclk; + input CPLLPD0_3; + input pipe_dclk_in; + input \cplllock_reg1_reg[1] ; + input \cplllock_reg1_reg[1]_0 ; + input sys_clk; + input DRP_GTXRESET; + input [0:0]pci_exp_rxn; + input [0:0]pci_exp_rxp; + input QPLL_QPLLOUTCLK; + input QPLL_QPLLOUTREFCLK; + input rxchbonden_1; + input \cplllock_reg1_reg[1]_1 ; + input rate_txpmareset_1; + input [0:0]PIPE_RXPOLARITY; + input rst_userrdy; + input pipe_rxusrclk_in; + input pipe_tx_deemph_gt; + input pipe_tx_rcvr_det_gt; + input SYNC_TXDLYSRESET; + input [0:0]PIPE_TXELECIDLE; + input SYNC_TXPHALIGN; + input SYNC_TXPHINIT; + input pipe_pclk_in; + input [15:0]DRPDI; + input [1:0]PIPE_POWERDOWN; + input [0:0]RXSYSCLKSEL; + input [0:0]RXRATE; + input [2:0]\cplllock_reg1_reg[1]_2 ; + input USER_OOBCLK; + input [4:0]RXCHBONDO; + input [4:0]TXPOSTCURSOR; + input [4:0]TXPRECURSOR; + input [15:0]PIPE_TXDATA; + input [6:0]TXMAINCURSOR; + input [0:0]PIPE_TXCOMPLIANCE; + input [1:0]PIPE_TXDATAK; + input [7:0]DRPADDR; + input rate_cpllreset_1; + input RST_CPLLRESET; + + wire CPLLPD0_3; + wire CPLLRESET0; + wire [7:0]DRPADDR; + wire [15:0]DRPDI; + wire [15:0]DRP_DO; + wire DRP_GTXRESET; + wire DRP_RDY; + wire [1:0]PIPE_POWERDOWN; + wire [0:0]PIPE_RXCHANISALIGNED; + wire [0:0]PIPE_RXPOLARITY; + wire [0:0]PIPE_TXCOMPLIANCE; + wire [15:0]PIPE_TXDATA; + wire [1:0]PIPE_TXDATAK; + wire [0:0]PIPE_TXELECIDLE; + wire QPLL_QPLLOUTCLK; + wire QPLL_QPLLOUTREFCLK; + wire [0:0]QRST_CPLLLOCK; + wire RATE_PHYSTATUS; + wire RATE_RXRATEDONE; + wire RATE_TXRATEDONE; + wire RST_CPLLRESET; + wire [4:0]RXCHBONDO; + wire [0:0]RXRATE; + wire [0:0]RXSYSCLKSEL; + wire SYNC_TXDLYSRESET; + wire SYNC_TXPHALIGN; + wire SYNC_TXPHINIT; + wire [6:0]TXMAINCURSOR; + wire [4:0]TXPOSTCURSOR; + wire [4:0]TXPRECURSOR; + wire USER_OOBCLK; + wire USER_RXRESETDONE; + wire USER_TXRESETDONE; + wire \cplllock_reg1_reg[1] ; + wire \cplllock_reg1_reg[1]_0 ; + wire \cplllock_reg1_reg[1]_1 ; + wire [2:0]\cplllock_reg1_reg[1]_2 ; + wire cpllpd_0; + wire gt_cpllpdrefclk; + wire [1:0]gt_rx_data_k_wire_filter; + wire [15:0]gt_rx_data_wire_filter; + wire [0:0]gt_rx_elec_idle_wire_filter; + wire gt_rxcdrlock_1; + wire gt_rxvalid_1; + wire \gtx_channel.gtxe2_channel_i_n_10 ; + wire \gtx_channel.gtxe2_channel_i_n_138 ; + wire \gtx_channel.gtxe2_channel_i_n_139 ; + wire \gtx_channel.gtxe2_channel_i_n_140 ; + wire \gtx_channel.gtxe2_channel_i_n_141 ; + wire \gtx_channel.gtxe2_channel_i_n_142 ; + wire \gtx_channel.gtxe2_channel_i_n_143 ; + wire \gtx_channel.gtxe2_channel_i_n_144 ; + wire \gtx_channel.gtxe2_channel_i_n_145 ; + wire \gtx_channel.gtxe2_channel_i_n_146 ; + wire \gtx_channel.gtxe2_channel_i_n_147 ; + wire \gtx_channel.gtxe2_channel_i_n_148 ; + wire \gtx_channel.gtxe2_channel_i_n_149 ; + wire \gtx_channel.gtxe2_channel_i_n_150 ; + wire \gtx_channel.gtxe2_channel_i_n_151 ; + wire \gtx_channel.gtxe2_channel_i_n_152 ; + wire \gtx_channel.gtxe2_channel_i_n_153 ; + wire \gtx_channel.gtxe2_channel_i_n_16 ; + wire \gtx_channel.gtxe2_channel_i_n_177 ; + wire \gtx_channel.gtxe2_channel_i_n_178 ; + wire \gtx_channel.gtxe2_channel_i_n_179 ; + wire \gtx_channel.gtxe2_channel_i_n_180 ; + wire \gtx_channel.gtxe2_channel_i_n_181 ; + wire \gtx_channel.gtxe2_channel_i_n_182 ; + wire \gtx_channel.gtxe2_channel_i_n_183 ; + wire \gtx_channel.gtxe2_channel_i_n_184 ; + wire \gtx_channel.gtxe2_channel_i_n_189 ; + wire \gtx_channel.gtxe2_channel_i_n_190 ; + wire \gtx_channel.gtxe2_channel_i_n_191 ; + wire \gtx_channel.gtxe2_channel_i_n_192 ; + wire \gtx_channel.gtxe2_channel_i_n_197 ; + wire \gtx_channel.gtxe2_channel_i_n_198 ; + wire \gtx_channel.gtxe2_channel_i_n_201 ; + wire \gtx_channel.gtxe2_channel_i_n_202 ; + wire \gtx_channel.gtxe2_channel_i_n_203 ; + wire \gtx_channel.gtxe2_channel_i_n_204 ; + wire \gtx_channel.gtxe2_channel_i_n_205 ; + wire \gtx_channel.gtxe2_channel_i_n_206 ; + wire \gtx_channel.gtxe2_channel_i_n_207 ; + wire \gtx_channel.gtxe2_channel_i_n_208 ; + wire \gtx_channel.gtxe2_channel_i_n_209 ; + wire \gtx_channel.gtxe2_channel_i_n_210 ; + wire \gtx_channel.gtxe2_channel_i_n_211 ; + wire \gtx_channel.gtxe2_channel_i_n_212 ; + wire \gtx_channel.gtxe2_channel_i_n_213 ; + wire \gtx_channel.gtxe2_channel_i_n_214 ; + wire \gtx_channel.gtxe2_channel_i_n_215 ; + wire \gtx_channel.gtxe2_channel_i_n_216 ; + wire \gtx_channel.gtxe2_channel_i_n_27 ; + wire \gtx_channel.gtxe2_channel_i_n_37 ; + wire \gtx_channel.gtxe2_channel_i_n_4 ; + wire \gtx_channel.gtxe2_channel_i_n_82 ; + wire \gtx_channel.gtxe2_channel_i_n_83 ; + wire \gtx_channel.gtxe2_channel_i_n_84 ; + wire \gtx_channel.gtxe2_channel_i_n_9 ; + wire \gtx_channel.gtxe2_channel_i_n_91 ; + wire \gtx_channel.gtxe2_channel_i_n_92 ; + wire \gtx_channel.gtxe2_channel_i_n_93 ; + wire \gtx_channel.gtxe2_channel_i_n_94 ; + wire \gtx_channel.gtxe2_channel_i_n_95 ; + wire [0:0]pci_exp_rxn; + wire [0:0]pci_exp_rxp; + wire [0:0]pci_exp_txn; + wire [0:0]pci_exp_txp; + wire pipe_dclk_in; + wire pipe_dclk_in_0; + wire pipe_dclk_in_1; + wire pipe_dclk_in_2; + wire pipe_dclk_in_3; + wire pipe_dclk_in_4; + wire [2:0]pipe_dclk_in_5; + wire pipe_pclk_in; + wire [0:0]pipe_rxoutclk_out; + wire pipe_rxusrclk_in; + wire pipe_tx_deemph_gt; + wire pipe_tx_rcvr_det_gt; + wire rate_cpllreset_1; + wire rate_txpmareset_1; + wire rst_userrdy; + wire rxchbonden_1; + wire sys_clk; + wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ; + wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ; + wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ; + wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ; + wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ; + wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ; + wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ; + wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ; + wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ; + wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ; + wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ; + wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ; + + pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_58 cpllPDInst + (.CPLLRESET0(CPLLRESET0), + .RST_CPLLRESET(RST_CPLLRESET), + .cpllpd_0(cpllpd_0), + .gt_cpllpdrefclk(gt_cpllpdrefclk), + .rate_cpllreset_1(rate_cpllreset_1)); + (* BOX_TYPE = "PRIMITIVE" *) + GTXE2_CHANNEL #( + .ALIGN_COMMA_DOUBLE("FALSE"), + .ALIGN_COMMA_ENABLE(10'b1111111111), + .ALIGN_COMMA_WORD(1), + .ALIGN_MCOMMA_DET("TRUE"), + .ALIGN_MCOMMA_VALUE(10'b1010000011), + .ALIGN_PCOMMA_DET("TRUE"), + .ALIGN_PCOMMA_VALUE(10'b0101111100), + .CBCC_DATA_SOURCE_SEL("DECODED"), + .CHAN_BOND_KEEP_ALIGN("TRUE"), + .CHAN_BOND_MAX_SKEW(7), + .CHAN_BOND_SEQ_1_1(10'b0001001010), + .CHAN_BOND_SEQ_1_2(10'b0001001010), + .CHAN_BOND_SEQ_1_3(10'b0001001010), + .CHAN_BOND_SEQ_1_4(10'b0110111100), + .CHAN_BOND_SEQ_1_ENABLE(4'b1111), + .CHAN_BOND_SEQ_2_1(10'b0001000101), + .CHAN_BOND_SEQ_2_2(10'b0001000101), + .CHAN_BOND_SEQ_2_3(10'b0001000101), + .CHAN_BOND_SEQ_2_4(10'b0110111100), + .CHAN_BOND_SEQ_2_ENABLE(4'b1111), + .CHAN_BOND_SEQ_2_USE("TRUE"), + .CHAN_BOND_SEQ_LEN(4), + .CLK_CORRECT_USE("TRUE"), + .CLK_COR_KEEP_IDLE("TRUE"), + .CLK_COR_MAX_LAT(20), + .CLK_COR_MIN_LAT(18), + .CLK_COR_PRECEDENCE("TRUE"), + .CLK_COR_REPEAT_WAIT(0), + .CLK_COR_SEQ_1_1(10'b0100011100), + .CLK_COR_SEQ_1_2(10'b0000000000), + .CLK_COR_SEQ_1_3(10'b0000000000), + .CLK_COR_SEQ_1_4(10'b0000000000), + .CLK_COR_SEQ_1_ENABLE(4'b1111), + .CLK_COR_SEQ_2_1(10'b0000000000), + .CLK_COR_SEQ_2_2(10'b0000000000), + .CLK_COR_SEQ_2_3(10'b0000000000), + .CLK_COR_SEQ_2_4(10'b0000000000), + .CLK_COR_SEQ_2_ENABLE(4'b0000), + .CLK_COR_SEQ_2_USE("FALSE"), + .CLK_COR_SEQ_LEN(1), + .CPLL_CFG(24'hA407CC), + .CPLL_FBDIV(5), + .CPLL_FBDIV_45(5), + .CPLL_INIT_CFG(24'h00001E), + .CPLL_LOCK_CFG(16'h01E8), + .CPLL_REFCLK_DIV(1), + .DEC_MCOMMA_DETECT("TRUE"), + .DEC_PCOMMA_DETECT("TRUE"), + .DEC_VALID_COMMA_ONLY("FALSE"), + .DMONITOR_CFG(24'h000B01), + .ES_CONTROL(6'b000000), + .ES_ERRDET_EN("FALSE"), + .ES_EYE_SCAN_EN("FALSE"), + .ES_HORZ_OFFSET(12'h000), + .ES_PMA_CFG(10'b0000000000), + .ES_PRESCALE(5'b00000), + .ES_QUALIFIER(80'h00000000000000000000), + .ES_QUAL_MASK(80'h00000000000000000000), + .ES_SDATA_MASK(80'h00000000000000000000), + .ES_VERT_OFFSET(9'b000000000), + .FTS_DESKEW_SEQ_ENABLE(4'b1111), + .FTS_LANE_DESKEW_CFG(4'b1111), + .FTS_LANE_DESKEW_EN("TRUE"), + .GEARBOX_MODE(3'b000), + .IS_CPLLLOCKDETCLK_INVERTED(1'b0), + .IS_DRPCLK_INVERTED(1'b0), + .IS_GTGREFCLK_INVERTED(1'b0), + .IS_RXUSRCLK2_INVERTED(1'b0), + .IS_RXUSRCLK_INVERTED(1'b0), + .IS_TXPHDLYTSTCLK_INVERTED(1'b0), + .IS_TXUSRCLK2_INVERTED(1'b0), + .IS_TXUSRCLK_INVERTED(1'b0), + .OUTREFCLK_SEL_INV(2'b11), + .PCS_PCIE_EN("TRUE"), + .PCS_RSVD_ATTR(48'h0000000001CF), + .PD_TRANS_TIME_FROM_P2(12'h03C), + .PD_TRANS_TIME_NONE_P2(8'h09), + .PD_TRANS_TIME_TO_P2(8'h64), + .PMA_RSV(32'h00018480), + .PMA_RSV2(16'h2050), + .PMA_RSV3(2'b00), + .PMA_RSV4(32'h00000000), + .RXBUFRESET_TIME(5'b00001), + .RXBUF_ADDR_MODE("FULL"), + .RXBUF_EIDLE_HI_CNT(4'b0100), + .RXBUF_EIDLE_LO_CNT(4'b0000), + .RXBUF_EN("TRUE"), + .RXBUF_RESET_ON_CB_CHANGE("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN("FALSE"), + .RXBUF_RESET_ON_EIDLE("TRUE"), + .RXBUF_RESET_ON_RATE_CHANGE("TRUE"), + .RXBUF_THRESH_OVFLW(61), + .RXBUF_THRESH_OVRD("FALSE"), + .RXBUF_THRESH_UNDFLW(4), + .RXCDRFREQRESET_TIME(5'b00001), + .RXCDRPHRESET_TIME(5'b00001), + .RXCDR_CFG(72'h03000023FF10200020), + .RXCDR_FR_RESET_ON_EIDLE(1'b0), + .RXCDR_HOLD_DURING_EIDLE(1'b1), + .RXCDR_LOCK_CFG(6'b010101), + .RXCDR_PH_RESET_ON_EIDLE(1'b0), + .RXDFELPMRESET_TIME(7'b0001111), + .RXDLY_CFG(16'h001F), + .RXDLY_LCFG(9'h030), + .RXDLY_TAP_CFG(16'h0000), + .RXGEARBOX_EN("FALSE"), + .RXISCANRESET_TIME(5'b00001), + .RXLPM_HF_CFG(14'b00000011110000), + .RXLPM_LF_CFG(14'b00000011110000), + .RXOOB_CFG(7'b0000110), + .RXOUT_DIV(2), + .RXPCSRESET_TIME(5'b00001), + .RXPHDLY_CFG(24'h004020), + .RXPH_CFG(24'h000000), + .RXPH_MONITOR_SEL(5'b00000), + .RXPMARESET_TIME(5'b00011), + .RXPRBS_ERR_LOOPBACK(1'b0), + .RXSLIDE_AUTO_WAIT(7), + .RXSLIDE_MODE("PMA"), + .RX_BIAS_CFG(12'b000000000100), + .RX_BUFFER_CFG(6'b000000), + .RX_CLK25_DIV(4), + .RX_CLKMUX_PD(1'b1), + .RX_CM_SEL(2'b11), + .RX_CM_TRIM(3'b010), + .RX_DATA_WIDTH(20), + .RX_DDI_SEL(6'b000000), + .RX_DEBUG_CFG(12'b000000000000), + .RX_DEFER_RESET_BUF_EN("TRUE"), + .RX_DFE_GAIN_CFG(23'h020FEA), + .RX_DFE_H2_CFG(12'b000000000000), + .RX_DFE_H3_CFG(12'b000001000000), + .RX_DFE_H4_CFG(11'b00011110000), + .RX_DFE_H5_CFG(11'b00011100000), + .RX_DFE_KL_CFG(13'b0000011111110), + .RX_DFE_KL_CFG2(32'h3290D86C), + .RX_DFE_LPM_CFG(16'h0954), + .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1), + .RX_DFE_UT_CFG(17'b10001111000000000), + .RX_DFE_VP_CFG(17'b00011111100000011), + .RX_DFE_XYD_CFG(13'b0000000000000), + .RX_DISPERR_SEQ_MATCH("TRUE"), + .RX_INT_DATAWIDTH(0), + .RX_OS_CFG(13'b0000010000000), + .RX_SIG_VALID_DLY(4), + .RX_XCLK_SEL("RXREC"), + .SAS_MAX_COM(64), + .SAS_MIN_COM(36), + .SATA_BURST_SEQ_LEN(4'b1111), + .SATA_BURST_VAL(3'b100), + .SATA_CPLL_CFG("VCO_3000MHZ"), + .SATA_EIDLE_VAL(3'b100), + .SATA_MAX_BURST(8), + .SATA_MAX_INIT(21), + .SATA_MAX_WAKE(7), + .SATA_MIN_BURST(4), + .SATA_MIN_INIT(12), + .SATA_MIN_WAKE(4), + .SHOW_REALIGN_COMMA("FALSE"), + .SIM_CPLLREFCLK_SEL(3'b001), + .SIM_RECEIVER_DETECT_PASS("TRUE"), + .SIM_RESET_SPEEDUP("FALSE"), + .SIM_TX_EIDLE_DRIVE_LEVEL("1"), + .SIM_VERSION("3.0"), + .TERM_RCAL_CFG(5'b10000), + .TERM_RCAL_OVRD(1'b0), + .TRANS_TIME_RATE(8'h0E), + .TST_RSV(32'h00000000), + .TXBUF_EN("FALSE"), + .TXBUF_RESET_ON_RATE_CHANGE("TRUE"), + .TXDLY_CFG(16'h001F), + .TXDLY_LCFG(9'h030), + .TXDLY_TAP_CFG(16'h0000), + .TXGEARBOX_EN("FALSE"), + .TXOUT_DIV(2), + .TXPCSRESET_TIME(5'b00001), + .TXPHDLY_CFG(24'h084020), + .TXPH_CFG(16'h0780), + .TXPH_MONITOR_SEL(5'b00000), + .TXPMARESET_TIME(5'b00011), + .TX_CLK25_DIV(4), + .TX_CLKMUX_PD(1'b1), + .TX_DATA_WIDTH(20), + .TX_DEEMPH0(5'b10100), + .TX_DEEMPH1(5'b01011), + .TX_DRIVE_MODE("PIPE"), + .TX_EIDLE_ASSERT_DELAY(3'b010), + .TX_EIDLE_DEASSERT_DELAY(3'b100), + .TX_INT_DATAWIDTH(0), + .TX_LOOPBACK_DRIVE_HIZ("FALSE"), + .TX_MAINCURSOR_SEL(1'b0), + .TX_MARGIN_FULL_0(7'b1001111), + .TX_MARGIN_FULL_1(7'b1001110), + .TX_MARGIN_FULL_2(7'b1001101), + .TX_MARGIN_FULL_3(7'b1001100), + .TX_MARGIN_FULL_4(7'b1000011), + .TX_MARGIN_LOW_0(7'b1000101), + .TX_MARGIN_LOW_1(7'b1000110), + .TX_MARGIN_LOW_2(7'b1000011), + .TX_MARGIN_LOW_3(7'b1000010), + .TX_MARGIN_LOW_4(7'b1000000), + .TX_PREDRIVER_MODE(1'b0), + .TX_QPI_STATUS_EN(1'b0), + .TX_RXDETECT_CFG(14'h0064), + .TX_RXDETECT_REF(3'b011), + .TX_XCLK_SEL("TXUSR"), + .UCODEER_CLR(1'b0)) + \gtx_channel.gtxe2_channel_i + (.CFGRESET(1'b0), + .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}), + .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ), + .CPLLLOCK(QRST_CPLLLOCK), + .CPLLLOCKDETCLK(1'b0), + .CPLLLOCKEN(1'b1), + .CPLLPD(CPLLPD0_3), + .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ), + .CPLLREFCLKSEL({1'b0,1'b0,1'b1}), + .CPLLRESET(CPLLRESET0), + .DMONITOROUT({\gtx_channel.gtxe2_channel_i_n_177 ,\gtx_channel.gtxe2_channel_i_n_178 ,\gtx_channel.gtxe2_channel_i_n_179 ,\gtx_channel.gtxe2_channel_i_n_180 ,\gtx_channel.gtxe2_channel_i_n_181 ,\gtx_channel.gtxe2_channel_i_n_182 ,\gtx_channel.gtxe2_channel_i_n_183 ,\gtx_channel.gtxe2_channel_i_n_184 }), + .DRPADDR({1'b0,DRPADDR}), + .DRPCLK(pipe_dclk_in), + .DRPDI(DRPDI), + .DRPDO(DRP_DO), + .DRPEN(\cplllock_reg1_reg[1] ), + .DRPRDY(DRP_RDY), + .DRPWE(\cplllock_reg1_reg[1]_0 ), + .EYESCANDATAERROR(\gtx_channel.gtxe2_channel_i_n_4 ), + .EYESCANMODE(1'b0), + .EYESCANRESET(1'b0), + .EYESCANTRIGGER(1'b0), + .GTGREFCLK(1'b0), + .GTNORTHREFCLK0(1'b0), + .GTNORTHREFCLK1(1'b0), + .GTREFCLK0(sys_clk), + .GTREFCLK1(1'b0), + .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ), + .GTRESETSEL(1'b0), + .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .GTRXRESET(DRP_GTXRESET), + .GTSOUTHREFCLK0(1'b0), + .GTSOUTHREFCLK1(1'b0), + .GTTXRESET(DRP_GTXRESET), + .GTXRXN(pci_exp_rxn), + .GTXRXP(pci_exp_rxp), + .GTXTXN(pci_exp_txn), + .GTXTXP(pci_exp_txp), + .LOOPBACK({1'b0,1'b0,1'b0}), + .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), + .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]), + .PHYSTATUS(RATE_PHYSTATUS), + .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}), + .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), + .QPLLCLK(QPLL_QPLLOUTCLK), + .QPLLREFCLK(QPLL_QPLLOUTREFCLK), + .RESETOVRD(1'b0), + .RX8B10BEN(rxchbonden_1), + .RXBUFRESET(1'b0), + .RXBUFSTATUS({\gtx_channel.gtxe2_channel_i_n_82 ,\gtx_channel.gtxe2_channel_i_n_83 ,\gtx_channel.gtxe2_channel_i_n_84 }), + .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ), + .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ), + .RXCDRFREQRESET(1'b0), + .RXCDRHOLD(1'b0), + .RXCDRLOCK(gt_rxcdrlock_1), + .RXCDROVRDEN(1'b0), + .RXCDRRESET(1'b0), + .RXCDRRESETRSV(1'b0), + .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ), + .RXCHANISALIGNED(PIPE_RXCHANISALIGNED), + .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ), + .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }), + .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,gt_rx_data_k_wire_filter}), + .RXCHBONDEN(rxchbonden_1), + .RXCHBONDI(RXCHBONDO), + .RXCHBONDLEVEL({1'b0,1'b0,1'b0}), + .RXCHBONDMASTER(1'b0), + .RXCHBONDO({\gtx_channel.gtxe2_channel_i_n_91 ,\gtx_channel.gtxe2_channel_i_n_92 ,\gtx_channel.gtxe2_channel_i_n_93 ,\gtx_channel.gtxe2_channel_i_n_94 ,\gtx_channel.gtxe2_channel_i_n_95 }), + .RXCHBONDSLAVE(rxchbonden_1), + .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]), + .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ), + .RXCOMMADET(\gtx_channel.gtxe2_channel_i_n_16 ), + .RXCOMMADETEN(1'b1), + .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ), + .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ), + .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,gt_rx_data_wire_filter}), + .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ), + .RXDDIEN(1'b0), + .RXDFEAGCHOLD(\cplllock_reg1_reg[1]_1 ), + .RXDFEAGCOVRDEN(1'b0), + .RXDFECM1EN(1'b0), + .RXDFELFHOLD(1'b0), + .RXDFELFOVRDEN(1'b1), + .RXDFELPMRESET(1'b0), + .RXDFETAP2HOLD(1'b0), + .RXDFETAP2OVRDEN(1'b0), + .RXDFETAP3HOLD(1'b0), + .RXDFETAP3OVRDEN(1'b0), + .RXDFETAP4HOLD(1'b0), + .RXDFETAP4OVRDEN(1'b0), + .RXDFETAP5HOLD(1'b0), + .RXDFETAP5OVRDEN(1'b0), + .RXDFEUTHOLD(1'b0), + .RXDFEUTOVRDEN(1'b0), + .RXDFEVPHOLD(1'b0), + .RXDFEVPOVRDEN(1'b0), + .RXDFEVSEN(1'b0), + .RXDFEXYDEN(1'b0), + .RXDFEXYDHOLD(1'b0), + .RXDFEXYDOVRDEN(1'b0), + .RXDISPERR({\gtx_channel.gtxe2_channel_i_n_201 ,\gtx_channel.gtxe2_channel_i_n_202 ,\gtx_channel.gtxe2_channel_i_n_203 ,\gtx_channel.gtxe2_channel_i_n_204 ,\gtx_channel.gtxe2_channel_i_n_205 ,\gtx_channel.gtxe2_channel_i_n_206 ,\gtx_channel.gtxe2_channel_i_n_207 ,\gtx_channel.gtxe2_channel_i_n_208 }), + .RXDLYBYPASS(1'b1), + .RXDLYEN(1'b0), + .RXDLYOVRDEN(1'b0), + .RXDLYSRESET(1'b0), + .RXDLYSRESETDONE(pipe_dclk_in_0), + .RXELECIDLE(gt_rx_elec_idle_wire_filter), + .RXELECIDLEMODE({1'b0,1'b0}), + .RXGEARBOXSLIP(1'b0), + .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]), + .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ), + .RXLPMEN(rxchbonden_1), + .RXLPMHFHOLD(1'b0), + .RXLPMHFOVRDEN(1'b0), + .RXLPMLFHOLD(1'b0), + .RXLPMLFKLOVRDEN(1'b0), + .RXMCOMMAALIGNEN(rxchbonden_1), + .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]), + .RXMONITORSEL({1'b0,1'b0}), + .RXNOTINTABLE({\gtx_channel.gtxe2_channel_i_n_209 ,\gtx_channel.gtxe2_channel_i_n_210 ,\gtx_channel.gtxe2_channel_i_n_211 ,\gtx_channel.gtxe2_channel_i_n_212 ,\gtx_channel.gtxe2_channel_i_n_213 ,\gtx_channel.gtxe2_channel_i_n_214 ,\gtx_channel.gtxe2_channel_i_n_215 ,\gtx_channel.gtxe2_channel_i_n_216 }), + .RXOOBRESET(1'b0), + .RXOSHOLD(1'b0), + .RXOSOVRDEN(1'b0), + .RXOUTCLK(pipe_rxoutclk_out), + .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ), + .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ), + .RXOUTCLKSEL({1'b0,1'b0,1'b0}), + .RXPCOMMAALIGNEN(rxchbonden_1), + .RXPCSRESET(1'b0), + .RXPD(PIPE_POWERDOWN), + .RXPHALIGN(1'b0), + .RXPHALIGNDONE(pipe_dclk_in_1), + .RXPHALIGNEN(1'b0), + .RXPHDLYPD(1'b0), + .RXPHDLYRESET(1'b0), + .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]), + .RXPHOVRDEN(1'b0), + .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]), + .RXPMARESET(rate_txpmareset_1), + .RXPOLARITY(PIPE_RXPOLARITY), + .RXPRBSCNTRESET(1'b0), + .RXPRBSERR(\gtx_channel.gtxe2_channel_i_n_27 ), + .RXPRBSSEL({1'b0,1'b0,1'b0}), + .RXQPIEN(1'b0), + .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ), + .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ), + .RXRATE({1'b0,1'b0,RXRATE}), + .RXRATEDONE(RATE_RXRATEDONE), + .RXRESETDONE(USER_RXRESETDONE), + .RXSLIDE(1'b0), + .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ), + .RXSTATUS(pipe_dclk_in_5), + .RXSYSCLKSEL({1'b0,RXSYSCLKSEL}), + .RXUSERRDY(rst_userrdy), + .RXUSRCLK(pipe_rxusrclk_in), + .RXUSRCLK2(pipe_rxusrclk_in), + .RXVALID(gt_rxvalid_1), + .SETERRSTATUS(1'b0), + .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]), + .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .TX8B10BEN(rxchbonden_1), + .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}), + .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]), + .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}), + .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}), + .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ), + .TXCOMINIT(1'b0), + .TXCOMSAS(1'b0), + .TXCOMWAKE(1'b0), + .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}), + .TXDEEMPH(pipe_tx_deemph_gt), + .TXDETECTRX(pipe_tx_rcvr_det_gt), + .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}), + .TXDIFFPD(1'b0), + .TXDLYBYPASS(1'b0), + .TXDLYEN(1'b0), + .TXDLYHOLD(1'b0), + .TXDLYOVRDEN(1'b0), + .TXDLYSRESET(SYNC_TXDLYSRESET), + .TXDLYSRESETDONE(pipe_dclk_in_2), + .TXDLYUPDOWN(1'b0), + .TXELECIDLE(PIPE_TXELECIDLE), + .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ), + .TXHEADER({1'b0,1'b0,1'b0}), + .TXINHIBIT(1'b0), + .TXMAINCURSOR(TXMAINCURSOR), + .TXMARGIN(\cplllock_reg1_reg[1]_2 ), + .TXOUTCLK(\gtx_channel.gtxe2_channel_i_n_37 ), + .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ), + .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ), + .TXOUTCLKSEL({1'b0,1'b0,1'b0}), + .TXPCSRESET(1'b0), + .TXPD(PIPE_POWERDOWN), + .TXPDELECIDLEMODE(1'b0), + .TXPHALIGN(SYNC_TXPHALIGN), + .TXPHALIGNDONE(pipe_dclk_in_3), + .TXPHALIGNEN(1'b1), + .TXPHDLYPD(1'b0), + .TXPHDLYRESET(1'b0), + .TXPHDLYTSTCLK(1'b0), + .TXPHINIT(SYNC_TXPHINIT), + .TXPHINITDONE(pipe_dclk_in_4), + .TXPHOVRDEN(1'b0), + .TXPISOPD(1'b0), + .TXPMARESET(rate_txpmareset_1), + .TXPOLARITY(1'b0), + .TXPOSTCURSOR(TXPOSTCURSOR), + .TXPOSTCURSORINV(1'b0), + .TXPRBSFORCEERR(1'b0), + .TXPRBSSEL({1'b0,1'b0,1'b0}), + .TXPRECURSOR(TXPRECURSOR), + .TXPRECURSORINV(1'b0), + .TXQPIBIASEN(1'b0), + .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ), + .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ), + .TXQPISTRONGPDOWN(1'b0), + .TXQPIWEAKPUP(1'b0), + .TXRATE({1'b0,1'b0,RXRATE}), + .TXRATEDONE(RATE_TXRATEDONE), + .TXRESETDONE(USER_TXRESETDONE), + .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .TXSTARTSEQ(1'b0), + .TXSWING(1'b0), + .TXSYSCLKSEL({1'b0,RXSYSCLKSEL}), + .TXUSERRDY(rst_userrdy), + .TXUSRCLK(pipe_pclk_in), + .TXUSRCLK2(pipe_pclk_in)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_gt_wrapper" *) +module pcie_7x_0_pcie_7x_0_gt_wrapper_43 + (cpllpd_1, + QRST_CPLLLOCK, + DRP_RDY, + pci_exp_txn, + pci_exp_txp, + RATE_PHYSTATUS, + gt_rxcdrlock_2, + PIPE_RXCHANISALIGNED, + pipe_dclk_in_0, + gt_rx_elec_idle_wire_filter, + pipe_rxoutclk_out, + pipe_dclk_in_1, + RATE_RXRATEDONE, + USER_RXRESETDONE, + gt_rxvalid_2, + pipe_dclk_in_2, + pipe_dclk_in_3, + pipe_dclk_in_4, + RATE_TXRATEDONE, + USER_TXRESETDONE, + DRP_DO, + pipe_dclk_in_5, + gt_rx_data_wire_filter, + gt_rx_data_k_wire_filter, + gt_cpllpdrefclk, + CPLLPD0_4, + pipe_dclk_in, + \cplllock_reg1_reg[2] , + \cplllock_reg1_reg[2]_0 , + sys_clk, + DRP_GTXRESET, + pci_exp_rxn, + pci_exp_rxp, + QPLL_QPLLOUTCLK, + QPLL_QPLLOUTREFCLK, + rxchbonden_2, + \cplllock_reg1_reg[2]_1 , + rate_txpmareset_2, + PIPE_RXPOLARITY, + rst_userrdy, + pipe_rxusrclk_in, + pipe_tx_deemph_gt, + pipe_tx_rcvr_det_gt, + SYNC_TXDLYSRESET, + PIPE_TXELECIDLE, + SYNC_TXPHALIGN, + SYNC_TXPHINIT, + pipe_pclk_in, + DRPDI, + PIPE_POWERDOWN, + RXSYSCLKSEL, + RXRATE, + \cplllock_reg1_reg[2]_2 , + USER_OOBCLK, + RXCHBONDO, + TXPOSTCURSOR, + TXPRECURSOR, + PIPE_TXDATA, + TXMAINCURSOR, + PIPE_TXCOMPLIANCE, + PIPE_TXDATAK, + DRPADDR, + rate_cpllreset_2, + RST_CPLLRESET); + output cpllpd_1; + output [0:0]QRST_CPLLLOCK; + output DRP_RDY; + output [0:0]pci_exp_txn; + output [0:0]pci_exp_txp; + output RATE_PHYSTATUS; + output gt_rxcdrlock_2; + output [0:0]PIPE_RXCHANISALIGNED; + output pipe_dclk_in_0; + output [0:0]gt_rx_elec_idle_wire_filter; + output [0:0]pipe_rxoutclk_out; + output pipe_dclk_in_1; + output RATE_RXRATEDONE; + output USER_RXRESETDONE; + output gt_rxvalid_2; + output pipe_dclk_in_2; + output pipe_dclk_in_3; + output pipe_dclk_in_4; + output RATE_TXRATEDONE; + output USER_TXRESETDONE; + output [15:0]DRP_DO; + output [2:0]pipe_dclk_in_5; + output [15:0]gt_rx_data_wire_filter; + output [1:0]gt_rx_data_k_wire_filter; + input gt_cpllpdrefclk; + input CPLLPD0_4; + input pipe_dclk_in; + input \cplllock_reg1_reg[2] ; + input \cplllock_reg1_reg[2]_0 ; + input sys_clk; + input DRP_GTXRESET; + input [0:0]pci_exp_rxn; + input [0:0]pci_exp_rxp; + input QPLL_QPLLOUTCLK; + input QPLL_QPLLOUTREFCLK; + input rxchbonden_2; + input \cplllock_reg1_reg[2]_1 ; + input rate_txpmareset_2; + input [0:0]PIPE_RXPOLARITY; + input rst_userrdy; + input pipe_rxusrclk_in; + input pipe_tx_deemph_gt; + input pipe_tx_rcvr_det_gt; + input SYNC_TXDLYSRESET; + input [0:0]PIPE_TXELECIDLE; + input SYNC_TXPHALIGN; + input SYNC_TXPHINIT; + input pipe_pclk_in; + input [15:0]DRPDI; + input [1:0]PIPE_POWERDOWN; + input [0:0]RXSYSCLKSEL; + input [0:0]RXRATE; + input [2:0]\cplllock_reg1_reg[2]_2 ; + input USER_OOBCLK; + input [4:0]RXCHBONDO; + input [4:0]TXPOSTCURSOR; + input [4:0]TXPRECURSOR; + input [15:0]PIPE_TXDATA; + input [6:0]TXMAINCURSOR; + input [0:0]PIPE_TXCOMPLIANCE; + input [1:0]PIPE_TXDATAK; + input [7:0]DRPADDR; + input rate_cpllreset_2; + input RST_CPLLRESET; + + wire CPLLPD0_4; + wire CPLLRESET0; + wire [7:0]DRPADDR; + wire [15:0]DRPDI; + wire [15:0]DRP_DO; + wire DRP_GTXRESET; + wire DRP_RDY; + wire [1:0]PIPE_POWERDOWN; + wire [0:0]PIPE_RXCHANISALIGNED; + wire [0:0]PIPE_RXPOLARITY; + wire [0:0]PIPE_TXCOMPLIANCE; + wire [15:0]PIPE_TXDATA; + wire [1:0]PIPE_TXDATAK; + wire [0:0]PIPE_TXELECIDLE; + wire QPLL_QPLLOUTCLK; + wire QPLL_QPLLOUTREFCLK; + wire [0:0]QRST_CPLLLOCK; + wire RATE_PHYSTATUS; + wire RATE_RXRATEDONE; + wire RATE_TXRATEDONE; + wire RST_CPLLRESET; + wire [4:0]RXCHBONDO; + wire [0:0]RXRATE; + wire [0:0]RXSYSCLKSEL; + wire SYNC_TXDLYSRESET; + wire SYNC_TXPHALIGN; + wire SYNC_TXPHINIT; + wire [6:0]TXMAINCURSOR; + wire [4:0]TXPOSTCURSOR; + wire [4:0]TXPRECURSOR; + wire USER_OOBCLK; + wire USER_RXRESETDONE; + wire USER_TXRESETDONE; + wire \cplllock_reg1_reg[2] ; + wire \cplllock_reg1_reg[2]_0 ; + wire \cplllock_reg1_reg[2]_1 ; + wire [2:0]\cplllock_reg1_reg[2]_2 ; + wire cpllpd_1; + wire gt_cpllpdrefclk; + wire [1:0]gt_rx_data_k_wire_filter; + wire [15:0]gt_rx_data_wire_filter; + wire [0:0]gt_rx_elec_idle_wire_filter; + wire gt_rxcdrlock_2; + wire gt_rxvalid_2; + wire \gtx_channel.gtxe2_channel_i_n_10 ; + wire \gtx_channel.gtxe2_channel_i_n_138 ; + wire \gtx_channel.gtxe2_channel_i_n_139 ; + wire \gtx_channel.gtxe2_channel_i_n_140 ; + wire \gtx_channel.gtxe2_channel_i_n_141 ; + wire \gtx_channel.gtxe2_channel_i_n_142 ; + wire \gtx_channel.gtxe2_channel_i_n_143 ; + wire \gtx_channel.gtxe2_channel_i_n_144 ; + wire \gtx_channel.gtxe2_channel_i_n_145 ; + wire \gtx_channel.gtxe2_channel_i_n_146 ; + wire \gtx_channel.gtxe2_channel_i_n_147 ; + wire \gtx_channel.gtxe2_channel_i_n_148 ; + wire \gtx_channel.gtxe2_channel_i_n_149 ; + wire \gtx_channel.gtxe2_channel_i_n_150 ; + wire \gtx_channel.gtxe2_channel_i_n_151 ; + wire \gtx_channel.gtxe2_channel_i_n_152 ; + wire \gtx_channel.gtxe2_channel_i_n_153 ; + wire \gtx_channel.gtxe2_channel_i_n_16 ; + wire \gtx_channel.gtxe2_channel_i_n_177 ; + wire \gtx_channel.gtxe2_channel_i_n_178 ; + wire \gtx_channel.gtxe2_channel_i_n_179 ; + wire \gtx_channel.gtxe2_channel_i_n_180 ; + wire \gtx_channel.gtxe2_channel_i_n_181 ; + wire \gtx_channel.gtxe2_channel_i_n_182 ; + wire \gtx_channel.gtxe2_channel_i_n_183 ; + wire \gtx_channel.gtxe2_channel_i_n_184 ; + wire \gtx_channel.gtxe2_channel_i_n_189 ; + wire \gtx_channel.gtxe2_channel_i_n_190 ; + wire \gtx_channel.gtxe2_channel_i_n_191 ; + wire \gtx_channel.gtxe2_channel_i_n_192 ; + wire \gtx_channel.gtxe2_channel_i_n_197 ; + wire \gtx_channel.gtxe2_channel_i_n_198 ; + wire \gtx_channel.gtxe2_channel_i_n_201 ; + wire \gtx_channel.gtxe2_channel_i_n_202 ; + wire \gtx_channel.gtxe2_channel_i_n_203 ; + wire \gtx_channel.gtxe2_channel_i_n_204 ; + wire \gtx_channel.gtxe2_channel_i_n_205 ; + wire \gtx_channel.gtxe2_channel_i_n_206 ; + wire \gtx_channel.gtxe2_channel_i_n_207 ; + wire \gtx_channel.gtxe2_channel_i_n_208 ; + wire \gtx_channel.gtxe2_channel_i_n_209 ; + wire \gtx_channel.gtxe2_channel_i_n_210 ; + wire \gtx_channel.gtxe2_channel_i_n_211 ; + wire \gtx_channel.gtxe2_channel_i_n_212 ; + wire \gtx_channel.gtxe2_channel_i_n_213 ; + wire \gtx_channel.gtxe2_channel_i_n_214 ; + wire \gtx_channel.gtxe2_channel_i_n_215 ; + wire \gtx_channel.gtxe2_channel_i_n_216 ; + wire \gtx_channel.gtxe2_channel_i_n_27 ; + wire \gtx_channel.gtxe2_channel_i_n_37 ; + wire \gtx_channel.gtxe2_channel_i_n_4 ; + wire \gtx_channel.gtxe2_channel_i_n_82 ; + wire \gtx_channel.gtxe2_channel_i_n_83 ; + wire \gtx_channel.gtxe2_channel_i_n_84 ; + wire \gtx_channel.gtxe2_channel_i_n_9 ; + wire \gtx_channel.gtxe2_channel_i_n_91 ; + wire \gtx_channel.gtxe2_channel_i_n_92 ; + wire \gtx_channel.gtxe2_channel_i_n_93 ; + wire \gtx_channel.gtxe2_channel_i_n_94 ; + wire \gtx_channel.gtxe2_channel_i_n_95 ; + wire [0:0]pci_exp_rxn; + wire [0:0]pci_exp_rxp; + wire [0:0]pci_exp_txn; + wire [0:0]pci_exp_txp; + wire pipe_dclk_in; + wire pipe_dclk_in_0; + wire pipe_dclk_in_1; + wire pipe_dclk_in_2; + wire pipe_dclk_in_3; + wire pipe_dclk_in_4; + wire [2:0]pipe_dclk_in_5; + wire pipe_pclk_in; + wire [0:0]pipe_rxoutclk_out; + wire pipe_rxusrclk_in; + wire pipe_tx_deemph_gt; + wire pipe_tx_rcvr_det_gt; + wire rate_cpllreset_2; + wire rate_txpmareset_2; + wire rst_userrdy; + wire rxchbonden_2; + wire sys_clk; + wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ; + wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ; + wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ; + wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ; + wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ; + wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ; + wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ; + wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ; + wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ; + wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ; + wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ; + wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ; + + pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_56 cpllPDInst + (.CPLLRESET0(CPLLRESET0), + .RST_CPLLRESET(RST_CPLLRESET), + .cpllpd_1(cpllpd_1), + .gt_cpllpdrefclk(gt_cpllpdrefclk), + .rate_cpllreset_2(rate_cpllreset_2)); + (* BOX_TYPE = "PRIMITIVE" *) + GTXE2_CHANNEL #( + .ALIGN_COMMA_DOUBLE("FALSE"), + .ALIGN_COMMA_ENABLE(10'b1111111111), + .ALIGN_COMMA_WORD(1), + .ALIGN_MCOMMA_DET("TRUE"), + .ALIGN_MCOMMA_VALUE(10'b1010000011), + .ALIGN_PCOMMA_DET("TRUE"), + .ALIGN_PCOMMA_VALUE(10'b0101111100), + .CBCC_DATA_SOURCE_SEL("DECODED"), + .CHAN_BOND_KEEP_ALIGN("TRUE"), + .CHAN_BOND_MAX_SKEW(7), + .CHAN_BOND_SEQ_1_1(10'b0001001010), + .CHAN_BOND_SEQ_1_2(10'b0001001010), + .CHAN_BOND_SEQ_1_3(10'b0001001010), + .CHAN_BOND_SEQ_1_4(10'b0110111100), + .CHAN_BOND_SEQ_1_ENABLE(4'b1111), + .CHAN_BOND_SEQ_2_1(10'b0001000101), + .CHAN_BOND_SEQ_2_2(10'b0001000101), + .CHAN_BOND_SEQ_2_3(10'b0001000101), + .CHAN_BOND_SEQ_2_4(10'b0110111100), + .CHAN_BOND_SEQ_2_ENABLE(4'b1111), + .CHAN_BOND_SEQ_2_USE("TRUE"), + .CHAN_BOND_SEQ_LEN(4), + .CLK_CORRECT_USE("TRUE"), + .CLK_COR_KEEP_IDLE("TRUE"), + .CLK_COR_MAX_LAT(20), + .CLK_COR_MIN_LAT(18), + .CLK_COR_PRECEDENCE("TRUE"), + .CLK_COR_REPEAT_WAIT(0), + .CLK_COR_SEQ_1_1(10'b0100011100), + .CLK_COR_SEQ_1_2(10'b0000000000), + .CLK_COR_SEQ_1_3(10'b0000000000), + .CLK_COR_SEQ_1_4(10'b0000000000), + .CLK_COR_SEQ_1_ENABLE(4'b1111), + .CLK_COR_SEQ_2_1(10'b0000000000), + .CLK_COR_SEQ_2_2(10'b0000000000), + .CLK_COR_SEQ_2_3(10'b0000000000), + .CLK_COR_SEQ_2_4(10'b0000000000), + .CLK_COR_SEQ_2_ENABLE(4'b0000), + .CLK_COR_SEQ_2_USE("FALSE"), + .CLK_COR_SEQ_LEN(1), + .CPLL_CFG(24'hA407CC), + .CPLL_FBDIV(5), + .CPLL_FBDIV_45(5), + .CPLL_INIT_CFG(24'h00001E), + .CPLL_LOCK_CFG(16'h01E8), + .CPLL_REFCLK_DIV(1), + .DEC_MCOMMA_DETECT("TRUE"), + .DEC_PCOMMA_DETECT("TRUE"), + .DEC_VALID_COMMA_ONLY("FALSE"), + .DMONITOR_CFG(24'h000B01), + .ES_CONTROL(6'b000000), + .ES_ERRDET_EN("FALSE"), + .ES_EYE_SCAN_EN("FALSE"), + .ES_HORZ_OFFSET(12'h000), + .ES_PMA_CFG(10'b0000000000), + .ES_PRESCALE(5'b00000), + .ES_QUALIFIER(80'h00000000000000000000), + .ES_QUAL_MASK(80'h00000000000000000000), + .ES_SDATA_MASK(80'h00000000000000000000), + .ES_VERT_OFFSET(9'b000000000), + .FTS_DESKEW_SEQ_ENABLE(4'b1111), + .FTS_LANE_DESKEW_CFG(4'b1111), + .FTS_LANE_DESKEW_EN("TRUE"), + .GEARBOX_MODE(3'b000), + .IS_CPLLLOCKDETCLK_INVERTED(1'b0), + .IS_DRPCLK_INVERTED(1'b0), + .IS_GTGREFCLK_INVERTED(1'b0), + .IS_RXUSRCLK2_INVERTED(1'b0), + .IS_RXUSRCLK_INVERTED(1'b0), + .IS_TXPHDLYTSTCLK_INVERTED(1'b0), + .IS_TXUSRCLK2_INVERTED(1'b0), + .IS_TXUSRCLK_INVERTED(1'b0), + .OUTREFCLK_SEL_INV(2'b11), + .PCS_PCIE_EN("TRUE"), + .PCS_RSVD_ATTR(48'h0000000001CF), + .PD_TRANS_TIME_FROM_P2(12'h03C), + .PD_TRANS_TIME_NONE_P2(8'h09), + .PD_TRANS_TIME_TO_P2(8'h64), + .PMA_RSV(32'h00018480), + .PMA_RSV2(16'h2050), + .PMA_RSV3(2'b00), + .PMA_RSV4(32'h00000000), + .RXBUFRESET_TIME(5'b00001), + .RXBUF_ADDR_MODE("FULL"), + .RXBUF_EIDLE_HI_CNT(4'b0100), + .RXBUF_EIDLE_LO_CNT(4'b0000), + .RXBUF_EN("TRUE"), + .RXBUF_RESET_ON_CB_CHANGE("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN("FALSE"), + .RXBUF_RESET_ON_EIDLE("TRUE"), + .RXBUF_RESET_ON_RATE_CHANGE("TRUE"), + .RXBUF_THRESH_OVFLW(61), + .RXBUF_THRESH_OVRD("FALSE"), + .RXBUF_THRESH_UNDFLW(4), + .RXCDRFREQRESET_TIME(5'b00001), + .RXCDRPHRESET_TIME(5'b00001), + .RXCDR_CFG(72'h03000023FF10200020), + .RXCDR_FR_RESET_ON_EIDLE(1'b0), + .RXCDR_HOLD_DURING_EIDLE(1'b1), + .RXCDR_LOCK_CFG(6'b010101), + .RXCDR_PH_RESET_ON_EIDLE(1'b0), + .RXDFELPMRESET_TIME(7'b0001111), + .RXDLY_CFG(16'h001F), + .RXDLY_LCFG(9'h030), + .RXDLY_TAP_CFG(16'h0000), + .RXGEARBOX_EN("FALSE"), + .RXISCANRESET_TIME(5'b00001), + .RXLPM_HF_CFG(14'b00000011110000), + .RXLPM_LF_CFG(14'b00000011110000), + .RXOOB_CFG(7'b0000110), + .RXOUT_DIV(2), + .RXPCSRESET_TIME(5'b00001), + .RXPHDLY_CFG(24'h004020), + .RXPH_CFG(24'h000000), + .RXPH_MONITOR_SEL(5'b00000), + .RXPMARESET_TIME(5'b00011), + .RXPRBS_ERR_LOOPBACK(1'b0), + .RXSLIDE_AUTO_WAIT(7), + .RXSLIDE_MODE("PMA"), + .RX_BIAS_CFG(12'b000000000100), + .RX_BUFFER_CFG(6'b000000), + .RX_CLK25_DIV(4), + .RX_CLKMUX_PD(1'b1), + .RX_CM_SEL(2'b11), + .RX_CM_TRIM(3'b010), + .RX_DATA_WIDTH(20), + .RX_DDI_SEL(6'b000000), + .RX_DEBUG_CFG(12'b000000000000), + .RX_DEFER_RESET_BUF_EN("TRUE"), + .RX_DFE_GAIN_CFG(23'h020FEA), + .RX_DFE_H2_CFG(12'b000000000000), + .RX_DFE_H3_CFG(12'b000001000000), + .RX_DFE_H4_CFG(11'b00011110000), + .RX_DFE_H5_CFG(11'b00011100000), + .RX_DFE_KL_CFG(13'b0000011111110), + .RX_DFE_KL_CFG2(32'h3290D86C), + .RX_DFE_LPM_CFG(16'h0954), + .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1), + .RX_DFE_UT_CFG(17'b10001111000000000), + .RX_DFE_VP_CFG(17'b00011111100000011), + .RX_DFE_XYD_CFG(13'b0000000000000), + .RX_DISPERR_SEQ_MATCH("TRUE"), + .RX_INT_DATAWIDTH(0), + .RX_OS_CFG(13'b0000010000000), + .RX_SIG_VALID_DLY(4), + .RX_XCLK_SEL("RXREC"), + .SAS_MAX_COM(64), + .SAS_MIN_COM(36), + .SATA_BURST_SEQ_LEN(4'b1111), + .SATA_BURST_VAL(3'b100), + .SATA_CPLL_CFG("VCO_3000MHZ"), + .SATA_EIDLE_VAL(3'b100), + .SATA_MAX_BURST(8), + .SATA_MAX_INIT(21), + .SATA_MAX_WAKE(7), + .SATA_MIN_BURST(4), + .SATA_MIN_INIT(12), + .SATA_MIN_WAKE(4), + .SHOW_REALIGN_COMMA("FALSE"), + .SIM_CPLLREFCLK_SEL(3'b001), + .SIM_RECEIVER_DETECT_PASS("TRUE"), + .SIM_RESET_SPEEDUP("FALSE"), + .SIM_TX_EIDLE_DRIVE_LEVEL("1"), + .SIM_VERSION("3.0"), + .TERM_RCAL_CFG(5'b10000), + .TERM_RCAL_OVRD(1'b0), + .TRANS_TIME_RATE(8'h0E), + .TST_RSV(32'h00000000), + .TXBUF_EN("FALSE"), + .TXBUF_RESET_ON_RATE_CHANGE("TRUE"), + .TXDLY_CFG(16'h001F), + .TXDLY_LCFG(9'h030), + .TXDLY_TAP_CFG(16'h0000), + .TXGEARBOX_EN("FALSE"), + .TXOUT_DIV(2), + .TXPCSRESET_TIME(5'b00001), + .TXPHDLY_CFG(24'h084020), + .TXPH_CFG(16'h0780), + .TXPH_MONITOR_SEL(5'b00000), + .TXPMARESET_TIME(5'b00011), + .TX_CLK25_DIV(4), + .TX_CLKMUX_PD(1'b1), + .TX_DATA_WIDTH(20), + .TX_DEEMPH0(5'b10100), + .TX_DEEMPH1(5'b01011), + .TX_DRIVE_MODE("PIPE"), + .TX_EIDLE_ASSERT_DELAY(3'b010), + .TX_EIDLE_DEASSERT_DELAY(3'b100), + .TX_INT_DATAWIDTH(0), + .TX_LOOPBACK_DRIVE_HIZ("FALSE"), + .TX_MAINCURSOR_SEL(1'b0), + .TX_MARGIN_FULL_0(7'b1001111), + .TX_MARGIN_FULL_1(7'b1001110), + .TX_MARGIN_FULL_2(7'b1001101), + .TX_MARGIN_FULL_3(7'b1001100), + .TX_MARGIN_FULL_4(7'b1000011), + .TX_MARGIN_LOW_0(7'b1000101), + .TX_MARGIN_LOW_1(7'b1000110), + .TX_MARGIN_LOW_2(7'b1000011), + .TX_MARGIN_LOW_3(7'b1000010), + .TX_MARGIN_LOW_4(7'b1000000), + .TX_PREDRIVER_MODE(1'b0), + .TX_QPI_STATUS_EN(1'b0), + .TX_RXDETECT_CFG(14'h0064), + .TX_RXDETECT_REF(3'b011), + .TX_XCLK_SEL("TXUSR"), + .UCODEER_CLR(1'b0)) + \gtx_channel.gtxe2_channel_i + (.CFGRESET(1'b0), + .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}), + .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ), + .CPLLLOCK(QRST_CPLLLOCK), + .CPLLLOCKDETCLK(1'b0), + .CPLLLOCKEN(1'b1), + .CPLLPD(CPLLPD0_4), + .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ), + .CPLLREFCLKSEL({1'b0,1'b0,1'b1}), + .CPLLRESET(CPLLRESET0), + .DMONITOROUT({\gtx_channel.gtxe2_channel_i_n_177 ,\gtx_channel.gtxe2_channel_i_n_178 ,\gtx_channel.gtxe2_channel_i_n_179 ,\gtx_channel.gtxe2_channel_i_n_180 ,\gtx_channel.gtxe2_channel_i_n_181 ,\gtx_channel.gtxe2_channel_i_n_182 ,\gtx_channel.gtxe2_channel_i_n_183 ,\gtx_channel.gtxe2_channel_i_n_184 }), + .DRPADDR({1'b0,DRPADDR}), + .DRPCLK(pipe_dclk_in), + .DRPDI(DRPDI), + .DRPDO(DRP_DO), + .DRPEN(\cplllock_reg1_reg[2] ), + .DRPRDY(DRP_RDY), + .DRPWE(\cplllock_reg1_reg[2]_0 ), + .EYESCANDATAERROR(\gtx_channel.gtxe2_channel_i_n_4 ), + .EYESCANMODE(1'b0), + .EYESCANRESET(1'b0), + .EYESCANTRIGGER(1'b0), + .GTGREFCLK(1'b0), + .GTNORTHREFCLK0(1'b0), + .GTNORTHREFCLK1(1'b0), + .GTREFCLK0(sys_clk), + .GTREFCLK1(1'b0), + .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ), + .GTRESETSEL(1'b0), + .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .GTRXRESET(DRP_GTXRESET), + .GTSOUTHREFCLK0(1'b0), + .GTSOUTHREFCLK1(1'b0), + .GTTXRESET(DRP_GTXRESET), + .GTXRXN(pci_exp_rxn), + .GTXRXP(pci_exp_rxp), + .GTXTXN(pci_exp_txn), + .GTXTXP(pci_exp_txp), + .LOOPBACK({1'b0,1'b0,1'b0}), + .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), + .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]), + .PHYSTATUS(RATE_PHYSTATUS), + .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}), + .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), + .QPLLCLK(QPLL_QPLLOUTCLK), + .QPLLREFCLK(QPLL_QPLLOUTREFCLK), + .RESETOVRD(1'b0), + .RX8B10BEN(rxchbonden_2), + .RXBUFRESET(1'b0), + .RXBUFSTATUS({\gtx_channel.gtxe2_channel_i_n_82 ,\gtx_channel.gtxe2_channel_i_n_83 ,\gtx_channel.gtxe2_channel_i_n_84 }), + .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ), + .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ), + .RXCDRFREQRESET(1'b0), + .RXCDRHOLD(1'b0), + .RXCDRLOCK(gt_rxcdrlock_2), + .RXCDROVRDEN(1'b0), + .RXCDRRESET(1'b0), + .RXCDRRESETRSV(1'b0), + .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ), + .RXCHANISALIGNED(PIPE_RXCHANISALIGNED), + .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ), + .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }), + .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,gt_rx_data_k_wire_filter}), + .RXCHBONDEN(rxchbonden_2), + .RXCHBONDI(RXCHBONDO), + .RXCHBONDLEVEL({1'b0,1'b0,1'b0}), + .RXCHBONDMASTER(1'b0), + .RXCHBONDO({\gtx_channel.gtxe2_channel_i_n_91 ,\gtx_channel.gtxe2_channel_i_n_92 ,\gtx_channel.gtxe2_channel_i_n_93 ,\gtx_channel.gtxe2_channel_i_n_94 ,\gtx_channel.gtxe2_channel_i_n_95 }), + .RXCHBONDSLAVE(rxchbonden_2), + .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]), + .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ), + .RXCOMMADET(\gtx_channel.gtxe2_channel_i_n_16 ), + .RXCOMMADETEN(1'b1), + .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ), + .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ), + .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,gt_rx_data_wire_filter}), + .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ), + .RXDDIEN(1'b0), + .RXDFEAGCHOLD(\cplllock_reg1_reg[2]_1 ), + .RXDFEAGCOVRDEN(1'b0), + .RXDFECM1EN(1'b0), + .RXDFELFHOLD(1'b0), + .RXDFELFOVRDEN(1'b1), + .RXDFELPMRESET(1'b0), + .RXDFETAP2HOLD(1'b0), + .RXDFETAP2OVRDEN(1'b0), + .RXDFETAP3HOLD(1'b0), + .RXDFETAP3OVRDEN(1'b0), + .RXDFETAP4HOLD(1'b0), + .RXDFETAP4OVRDEN(1'b0), + .RXDFETAP5HOLD(1'b0), + .RXDFETAP5OVRDEN(1'b0), + .RXDFEUTHOLD(1'b0), + .RXDFEUTOVRDEN(1'b0), + .RXDFEVPHOLD(1'b0), + .RXDFEVPOVRDEN(1'b0), + .RXDFEVSEN(1'b0), + .RXDFEXYDEN(1'b0), + .RXDFEXYDHOLD(1'b0), + .RXDFEXYDOVRDEN(1'b0), + .RXDISPERR({\gtx_channel.gtxe2_channel_i_n_201 ,\gtx_channel.gtxe2_channel_i_n_202 ,\gtx_channel.gtxe2_channel_i_n_203 ,\gtx_channel.gtxe2_channel_i_n_204 ,\gtx_channel.gtxe2_channel_i_n_205 ,\gtx_channel.gtxe2_channel_i_n_206 ,\gtx_channel.gtxe2_channel_i_n_207 ,\gtx_channel.gtxe2_channel_i_n_208 }), + .RXDLYBYPASS(1'b1), + .RXDLYEN(1'b0), + .RXDLYOVRDEN(1'b0), + .RXDLYSRESET(1'b0), + .RXDLYSRESETDONE(pipe_dclk_in_0), + .RXELECIDLE(gt_rx_elec_idle_wire_filter), + .RXELECIDLEMODE({1'b0,1'b0}), + .RXGEARBOXSLIP(1'b0), + .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]), + .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ), + .RXLPMEN(rxchbonden_2), + .RXLPMHFHOLD(1'b0), + .RXLPMHFOVRDEN(1'b0), + .RXLPMLFHOLD(1'b0), + .RXLPMLFKLOVRDEN(1'b0), + .RXMCOMMAALIGNEN(rxchbonden_2), + .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]), + .RXMONITORSEL({1'b0,1'b0}), + .RXNOTINTABLE({\gtx_channel.gtxe2_channel_i_n_209 ,\gtx_channel.gtxe2_channel_i_n_210 ,\gtx_channel.gtxe2_channel_i_n_211 ,\gtx_channel.gtxe2_channel_i_n_212 ,\gtx_channel.gtxe2_channel_i_n_213 ,\gtx_channel.gtxe2_channel_i_n_214 ,\gtx_channel.gtxe2_channel_i_n_215 ,\gtx_channel.gtxe2_channel_i_n_216 }), + .RXOOBRESET(1'b0), + .RXOSHOLD(1'b0), + .RXOSOVRDEN(1'b0), + .RXOUTCLK(pipe_rxoutclk_out), + .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ), + .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ), + .RXOUTCLKSEL({1'b0,1'b0,1'b0}), + .RXPCOMMAALIGNEN(rxchbonden_2), + .RXPCSRESET(1'b0), + .RXPD(PIPE_POWERDOWN), + .RXPHALIGN(1'b0), + .RXPHALIGNDONE(pipe_dclk_in_1), + .RXPHALIGNEN(1'b0), + .RXPHDLYPD(1'b0), + .RXPHDLYRESET(1'b0), + .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]), + .RXPHOVRDEN(1'b0), + .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]), + .RXPMARESET(rate_txpmareset_2), + .RXPOLARITY(PIPE_RXPOLARITY), + .RXPRBSCNTRESET(1'b0), + .RXPRBSERR(\gtx_channel.gtxe2_channel_i_n_27 ), + .RXPRBSSEL({1'b0,1'b0,1'b0}), + .RXQPIEN(1'b0), + .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ), + .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ), + .RXRATE({1'b0,1'b0,RXRATE}), + .RXRATEDONE(RATE_RXRATEDONE), + .RXRESETDONE(USER_RXRESETDONE), + .RXSLIDE(1'b0), + .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ), + .RXSTATUS(pipe_dclk_in_5), + .RXSYSCLKSEL({1'b0,RXSYSCLKSEL}), + .RXUSERRDY(rst_userrdy), + .RXUSRCLK(pipe_rxusrclk_in), + .RXUSRCLK2(pipe_rxusrclk_in), + .RXVALID(gt_rxvalid_2), + .SETERRSTATUS(1'b0), + .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]), + .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .TX8B10BEN(rxchbonden_2), + .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}), + .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]), + .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}), + .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}), + .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ), + .TXCOMINIT(1'b0), + .TXCOMSAS(1'b0), + .TXCOMWAKE(1'b0), + .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}), + .TXDEEMPH(pipe_tx_deemph_gt), + .TXDETECTRX(pipe_tx_rcvr_det_gt), + .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}), + .TXDIFFPD(1'b0), + .TXDLYBYPASS(1'b0), + .TXDLYEN(1'b0), + .TXDLYHOLD(1'b0), + .TXDLYOVRDEN(1'b0), + .TXDLYSRESET(SYNC_TXDLYSRESET), + .TXDLYSRESETDONE(pipe_dclk_in_2), + .TXDLYUPDOWN(1'b0), + .TXELECIDLE(PIPE_TXELECIDLE), + .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ), + .TXHEADER({1'b0,1'b0,1'b0}), + .TXINHIBIT(1'b0), + .TXMAINCURSOR(TXMAINCURSOR), + .TXMARGIN(\cplllock_reg1_reg[2]_2 ), + .TXOUTCLK(\gtx_channel.gtxe2_channel_i_n_37 ), + .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ), + .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ), + .TXOUTCLKSEL({1'b0,1'b0,1'b0}), + .TXPCSRESET(1'b0), + .TXPD(PIPE_POWERDOWN), + .TXPDELECIDLEMODE(1'b0), + .TXPHALIGN(SYNC_TXPHALIGN), + .TXPHALIGNDONE(pipe_dclk_in_3), + .TXPHALIGNEN(1'b1), + .TXPHDLYPD(1'b0), + .TXPHDLYRESET(1'b0), + .TXPHDLYTSTCLK(1'b0), + .TXPHINIT(SYNC_TXPHINIT), + .TXPHINITDONE(pipe_dclk_in_4), + .TXPHOVRDEN(1'b0), + .TXPISOPD(1'b0), + .TXPMARESET(rate_txpmareset_2), + .TXPOLARITY(1'b0), + .TXPOSTCURSOR(TXPOSTCURSOR), + .TXPOSTCURSORINV(1'b0), + .TXPRBSFORCEERR(1'b0), + .TXPRBSSEL({1'b0,1'b0,1'b0}), + .TXPRECURSOR(TXPRECURSOR), + .TXPRECURSORINV(1'b0), + .TXQPIBIASEN(1'b0), + .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ), + .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ), + .TXQPISTRONGPDOWN(1'b0), + .TXQPIWEAKPUP(1'b0), + .TXRATE({1'b0,1'b0,RXRATE}), + .TXRATEDONE(RATE_TXRATEDONE), + .TXRESETDONE(USER_TXRESETDONE), + .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .TXSTARTSEQ(1'b0), + .TXSWING(1'b0), + .TXSYSCLKSEL({1'b0,RXSYSCLKSEL}), + .TXUSERRDY(rst_userrdy), + .TXUSRCLK(pipe_pclk_in), + .TXUSRCLK2(pipe_pclk_in)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_gt_wrapper" *) +module pcie_7x_0_pcie_7x_0_gt_wrapper_49 + (cpllpd_2, + QRST_CPLLLOCK, + DRP_RDY, + pci_exp_txn, + pci_exp_txp, + RATE_PHYSTATUS, + gt_rxcdrlock_3, + PIPE_RXCHANISALIGNED, + pipe_dclk_in_0, + gt_rx_elec_idle_wire_filter, + pipe_rxoutclk_out, + pipe_dclk_in_1, + RATE_RXRATEDONE, + USER_RXRESETDONE, + gt_rxvalid_3, + pipe_dclk_in_2, + pipe_dclk_in_3, + pipe_dclk_in_4, + RATE_TXRATEDONE, + USER_TXRESETDONE, + DRP_DO, + pipe_dclk_in_5, + gt_rx_data_wire_filter, + gt_rx_data_k_wire_filter, + gt_cpllpdrefclk, + CPLLPD0_5, + pipe_dclk_in, + \cplllock_reg1_reg[3] , + \cplllock_reg1_reg[3]_0 , + sys_clk, + DRP_GTXRESET, + pci_exp_rxn, + pci_exp_rxp, + QPLL_QPLLOUTCLK, + QPLL_QPLLOUTREFCLK, + rxchbonden_3, + \cplllock_reg1_reg[3]_1 , + rate_txpmareset_3, + PIPE_RXPOLARITY, + rst_userrdy, + pipe_rxusrclk_in, + pipe_tx_deemph_gt, + pipe_tx_rcvr_det_gt, + SYNC_TXDLYSRESET, + PIPE_TXELECIDLE, + SYNC_TXPHALIGN, + SYNC_TXPHINIT, + pipe_pclk_in, + DRPDI, + PIPE_POWERDOWN, + RXSYSCLKSEL, + RXRATE, + \cplllock_reg1_reg[3]_2 , + USER_OOBCLK, + RXCHBONDO, + TXPOSTCURSOR, + TXPRECURSOR, + PIPE_TXDATA, + TXMAINCURSOR, + PIPE_TXCOMPLIANCE, + PIPE_TXDATAK, + DRPADDR, + rate_cpllreset_3, + RST_CPLLRESET); + output cpllpd_2; + output [0:0]QRST_CPLLLOCK; + output DRP_RDY; + output [0:0]pci_exp_txn; + output [0:0]pci_exp_txp; + output RATE_PHYSTATUS; + output gt_rxcdrlock_3; + output [0:0]PIPE_RXCHANISALIGNED; + output pipe_dclk_in_0; + output [0:0]gt_rx_elec_idle_wire_filter; + output [0:0]pipe_rxoutclk_out; + output pipe_dclk_in_1; + output RATE_RXRATEDONE; + output USER_RXRESETDONE; + output gt_rxvalid_3; + output pipe_dclk_in_2; + output pipe_dclk_in_3; + output pipe_dclk_in_4; + output RATE_TXRATEDONE; + output USER_TXRESETDONE; + output [15:0]DRP_DO; + output [2:0]pipe_dclk_in_5; + output [15:0]gt_rx_data_wire_filter; + output [1:0]gt_rx_data_k_wire_filter; + input gt_cpllpdrefclk; + input CPLLPD0_5; + input pipe_dclk_in; + input \cplllock_reg1_reg[3] ; + input \cplllock_reg1_reg[3]_0 ; + input sys_clk; + input DRP_GTXRESET; + input [0:0]pci_exp_rxn; + input [0:0]pci_exp_rxp; + input QPLL_QPLLOUTCLK; + input QPLL_QPLLOUTREFCLK; + input rxchbonden_3; + input \cplllock_reg1_reg[3]_1 ; + input rate_txpmareset_3; + input [0:0]PIPE_RXPOLARITY; + input rst_userrdy; + input pipe_rxusrclk_in; + input pipe_tx_deemph_gt; + input pipe_tx_rcvr_det_gt; + input SYNC_TXDLYSRESET; + input [0:0]PIPE_TXELECIDLE; + input SYNC_TXPHALIGN; + input SYNC_TXPHINIT; + input pipe_pclk_in; + input [15:0]DRPDI; + input [1:0]PIPE_POWERDOWN; + input [0:0]RXSYSCLKSEL; + input [0:0]RXRATE; + input [2:0]\cplllock_reg1_reg[3]_2 ; + input USER_OOBCLK; + input [4:0]RXCHBONDO; + input [4:0]TXPOSTCURSOR; + input [4:0]TXPRECURSOR; + input [15:0]PIPE_TXDATA; + input [6:0]TXMAINCURSOR; + input [0:0]PIPE_TXCOMPLIANCE; + input [1:0]PIPE_TXDATAK; + input [7:0]DRPADDR; + input rate_cpllreset_3; + input RST_CPLLRESET; + + wire CPLLPD0_5; + wire CPLLRESET0; + wire [7:0]DRPADDR; + wire [15:0]DRPDI; + wire [15:0]DRP_DO; + wire DRP_GTXRESET; + wire DRP_RDY; + wire [1:0]PIPE_POWERDOWN; + wire [0:0]PIPE_RXCHANISALIGNED; + wire [0:0]PIPE_RXPOLARITY; + wire [0:0]PIPE_TXCOMPLIANCE; + wire [15:0]PIPE_TXDATA; + wire [1:0]PIPE_TXDATAK; + wire [0:0]PIPE_TXELECIDLE; + wire QPLL_QPLLOUTCLK; + wire QPLL_QPLLOUTREFCLK; + wire [0:0]QRST_CPLLLOCK; + wire RATE_PHYSTATUS; + wire RATE_RXRATEDONE; + wire RATE_TXRATEDONE; + wire RST_CPLLRESET; + wire [4:0]RXCHBONDO; + wire [0:0]RXRATE; + wire [0:0]RXSYSCLKSEL; + wire SYNC_TXDLYSRESET; + wire SYNC_TXPHALIGN; + wire SYNC_TXPHINIT; + wire [6:0]TXMAINCURSOR; + wire [4:0]TXPOSTCURSOR; + wire [4:0]TXPRECURSOR; + wire USER_OOBCLK; + wire USER_RXRESETDONE; + wire USER_TXRESETDONE; + wire \cplllock_reg1_reg[3] ; + wire \cplllock_reg1_reg[3]_0 ; + wire \cplllock_reg1_reg[3]_1 ; + wire [2:0]\cplllock_reg1_reg[3]_2 ; + wire cpllpd_2; + wire gt_cpllpdrefclk; + wire [1:0]gt_rx_data_k_wire_filter; + wire [15:0]gt_rx_data_wire_filter; + wire [0:0]gt_rx_elec_idle_wire_filter; + wire gt_rxcdrlock_3; + wire gt_rxvalid_3; + wire \gtx_channel.gtxe2_channel_i_n_10 ; + wire \gtx_channel.gtxe2_channel_i_n_138 ; + wire \gtx_channel.gtxe2_channel_i_n_139 ; + wire \gtx_channel.gtxe2_channel_i_n_140 ; + wire \gtx_channel.gtxe2_channel_i_n_141 ; + wire \gtx_channel.gtxe2_channel_i_n_142 ; + wire \gtx_channel.gtxe2_channel_i_n_143 ; + wire \gtx_channel.gtxe2_channel_i_n_144 ; + wire \gtx_channel.gtxe2_channel_i_n_145 ; + wire \gtx_channel.gtxe2_channel_i_n_146 ; + wire \gtx_channel.gtxe2_channel_i_n_147 ; + wire \gtx_channel.gtxe2_channel_i_n_148 ; + wire \gtx_channel.gtxe2_channel_i_n_149 ; + wire \gtx_channel.gtxe2_channel_i_n_150 ; + wire \gtx_channel.gtxe2_channel_i_n_151 ; + wire \gtx_channel.gtxe2_channel_i_n_152 ; + wire \gtx_channel.gtxe2_channel_i_n_153 ; + wire \gtx_channel.gtxe2_channel_i_n_16 ; + wire \gtx_channel.gtxe2_channel_i_n_177 ; + wire \gtx_channel.gtxe2_channel_i_n_178 ; + wire \gtx_channel.gtxe2_channel_i_n_179 ; + wire \gtx_channel.gtxe2_channel_i_n_180 ; + wire \gtx_channel.gtxe2_channel_i_n_181 ; + wire \gtx_channel.gtxe2_channel_i_n_182 ; + wire \gtx_channel.gtxe2_channel_i_n_183 ; + wire \gtx_channel.gtxe2_channel_i_n_184 ; + wire \gtx_channel.gtxe2_channel_i_n_189 ; + wire \gtx_channel.gtxe2_channel_i_n_190 ; + wire \gtx_channel.gtxe2_channel_i_n_191 ; + wire \gtx_channel.gtxe2_channel_i_n_192 ; + wire \gtx_channel.gtxe2_channel_i_n_197 ; + wire \gtx_channel.gtxe2_channel_i_n_198 ; + wire \gtx_channel.gtxe2_channel_i_n_201 ; + wire \gtx_channel.gtxe2_channel_i_n_202 ; + wire \gtx_channel.gtxe2_channel_i_n_203 ; + wire \gtx_channel.gtxe2_channel_i_n_204 ; + wire \gtx_channel.gtxe2_channel_i_n_205 ; + wire \gtx_channel.gtxe2_channel_i_n_206 ; + wire \gtx_channel.gtxe2_channel_i_n_207 ; + wire \gtx_channel.gtxe2_channel_i_n_208 ; + wire \gtx_channel.gtxe2_channel_i_n_209 ; + wire \gtx_channel.gtxe2_channel_i_n_210 ; + wire \gtx_channel.gtxe2_channel_i_n_211 ; + wire \gtx_channel.gtxe2_channel_i_n_212 ; + wire \gtx_channel.gtxe2_channel_i_n_213 ; + wire \gtx_channel.gtxe2_channel_i_n_214 ; + wire \gtx_channel.gtxe2_channel_i_n_215 ; + wire \gtx_channel.gtxe2_channel_i_n_216 ; + wire \gtx_channel.gtxe2_channel_i_n_27 ; + wire \gtx_channel.gtxe2_channel_i_n_37 ; + wire \gtx_channel.gtxe2_channel_i_n_4 ; + wire \gtx_channel.gtxe2_channel_i_n_82 ; + wire \gtx_channel.gtxe2_channel_i_n_83 ; + wire \gtx_channel.gtxe2_channel_i_n_84 ; + wire \gtx_channel.gtxe2_channel_i_n_9 ; + wire \gtx_channel.gtxe2_channel_i_n_91 ; + wire \gtx_channel.gtxe2_channel_i_n_92 ; + wire \gtx_channel.gtxe2_channel_i_n_93 ; + wire \gtx_channel.gtxe2_channel_i_n_94 ; + wire \gtx_channel.gtxe2_channel_i_n_95 ; + wire [0:0]pci_exp_rxn; + wire [0:0]pci_exp_rxp; + wire [0:0]pci_exp_txn; + wire [0:0]pci_exp_txp; + wire pipe_dclk_in; + wire pipe_dclk_in_0; + wire pipe_dclk_in_1; + wire pipe_dclk_in_2; + wire pipe_dclk_in_3; + wire pipe_dclk_in_4; + wire [2:0]pipe_dclk_in_5; + wire pipe_pclk_in; + wire [0:0]pipe_rxoutclk_out; + wire pipe_rxusrclk_in; + wire pipe_tx_deemph_gt; + wire pipe_tx_rcvr_det_gt; + wire rate_cpllreset_3; + wire rate_txpmareset_3; + wire rst_userrdy; + wire rxchbonden_3; + wire sys_clk; + wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ; + wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ; + wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ; + wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ; + wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ; + wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ; + wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ; + wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ; + wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ; + wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ; + wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ; + wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ; + wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ; + + pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd cpllPDInst + (.CPLLRESET0(CPLLRESET0), + .RST_CPLLRESET(RST_CPLLRESET), + .cpllpd_2(cpllpd_2), + .gt_cpllpdrefclk(gt_cpllpdrefclk), + .rate_cpllreset_3(rate_cpllreset_3)); + (* BOX_TYPE = "PRIMITIVE" *) + GTXE2_CHANNEL #( + .ALIGN_COMMA_DOUBLE("FALSE"), + .ALIGN_COMMA_ENABLE(10'b1111111111), + .ALIGN_COMMA_WORD(1), + .ALIGN_MCOMMA_DET("TRUE"), + .ALIGN_MCOMMA_VALUE(10'b1010000011), + .ALIGN_PCOMMA_DET("TRUE"), + .ALIGN_PCOMMA_VALUE(10'b0101111100), + .CBCC_DATA_SOURCE_SEL("DECODED"), + .CHAN_BOND_KEEP_ALIGN("TRUE"), + .CHAN_BOND_MAX_SKEW(7), + .CHAN_BOND_SEQ_1_1(10'b0001001010), + .CHAN_BOND_SEQ_1_2(10'b0001001010), + .CHAN_BOND_SEQ_1_3(10'b0001001010), + .CHAN_BOND_SEQ_1_4(10'b0110111100), + .CHAN_BOND_SEQ_1_ENABLE(4'b1111), + .CHAN_BOND_SEQ_2_1(10'b0001000101), + .CHAN_BOND_SEQ_2_2(10'b0001000101), + .CHAN_BOND_SEQ_2_3(10'b0001000101), + .CHAN_BOND_SEQ_2_4(10'b0110111100), + .CHAN_BOND_SEQ_2_ENABLE(4'b1111), + .CHAN_BOND_SEQ_2_USE("TRUE"), + .CHAN_BOND_SEQ_LEN(4), + .CLK_CORRECT_USE("TRUE"), + .CLK_COR_KEEP_IDLE("TRUE"), + .CLK_COR_MAX_LAT(20), + .CLK_COR_MIN_LAT(18), + .CLK_COR_PRECEDENCE("TRUE"), + .CLK_COR_REPEAT_WAIT(0), + .CLK_COR_SEQ_1_1(10'b0100011100), + .CLK_COR_SEQ_1_2(10'b0000000000), + .CLK_COR_SEQ_1_3(10'b0000000000), + .CLK_COR_SEQ_1_4(10'b0000000000), + .CLK_COR_SEQ_1_ENABLE(4'b1111), + .CLK_COR_SEQ_2_1(10'b0000000000), + .CLK_COR_SEQ_2_2(10'b0000000000), + .CLK_COR_SEQ_2_3(10'b0000000000), + .CLK_COR_SEQ_2_4(10'b0000000000), + .CLK_COR_SEQ_2_ENABLE(4'b0000), + .CLK_COR_SEQ_2_USE("FALSE"), + .CLK_COR_SEQ_LEN(1), + .CPLL_CFG(24'hA407CC), + .CPLL_FBDIV(5), + .CPLL_FBDIV_45(5), + .CPLL_INIT_CFG(24'h00001E), + .CPLL_LOCK_CFG(16'h01E8), + .CPLL_REFCLK_DIV(1), + .DEC_MCOMMA_DETECT("TRUE"), + .DEC_PCOMMA_DETECT("TRUE"), + .DEC_VALID_COMMA_ONLY("FALSE"), + .DMONITOR_CFG(24'h000B01), + .ES_CONTROL(6'b000000), + .ES_ERRDET_EN("FALSE"), + .ES_EYE_SCAN_EN("FALSE"), + .ES_HORZ_OFFSET(12'h000), + .ES_PMA_CFG(10'b0000000000), + .ES_PRESCALE(5'b00000), + .ES_QUALIFIER(80'h00000000000000000000), + .ES_QUAL_MASK(80'h00000000000000000000), + .ES_SDATA_MASK(80'h00000000000000000000), + .ES_VERT_OFFSET(9'b000000000), + .FTS_DESKEW_SEQ_ENABLE(4'b1111), + .FTS_LANE_DESKEW_CFG(4'b1111), + .FTS_LANE_DESKEW_EN("TRUE"), + .GEARBOX_MODE(3'b000), + .IS_CPLLLOCKDETCLK_INVERTED(1'b0), + .IS_DRPCLK_INVERTED(1'b0), + .IS_GTGREFCLK_INVERTED(1'b0), + .IS_RXUSRCLK2_INVERTED(1'b0), + .IS_RXUSRCLK_INVERTED(1'b0), + .IS_TXPHDLYTSTCLK_INVERTED(1'b0), + .IS_TXUSRCLK2_INVERTED(1'b0), + .IS_TXUSRCLK_INVERTED(1'b0), + .OUTREFCLK_SEL_INV(2'b11), + .PCS_PCIE_EN("TRUE"), + .PCS_RSVD_ATTR(48'h0000000001CF), + .PD_TRANS_TIME_FROM_P2(12'h03C), + .PD_TRANS_TIME_NONE_P2(8'h09), + .PD_TRANS_TIME_TO_P2(8'h64), + .PMA_RSV(32'h00018480), + .PMA_RSV2(16'h2050), + .PMA_RSV3(2'b00), + .PMA_RSV4(32'h00000000), + .RXBUFRESET_TIME(5'b00001), + .RXBUF_ADDR_MODE("FULL"), + .RXBUF_EIDLE_HI_CNT(4'b0100), + .RXBUF_EIDLE_LO_CNT(4'b0000), + .RXBUF_EN("TRUE"), + .RXBUF_RESET_ON_CB_CHANGE("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN("FALSE"), + .RXBUF_RESET_ON_EIDLE("TRUE"), + .RXBUF_RESET_ON_RATE_CHANGE("TRUE"), + .RXBUF_THRESH_OVFLW(61), + .RXBUF_THRESH_OVRD("FALSE"), + .RXBUF_THRESH_UNDFLW(4), + .RXCDRFREQRESET_TIME(5'b00001), + .RXCDRPHRESET_TIME(5'b00001), + .RXCDR_CFG(72'h03000023FF10200020), + .RXCDR_FR_RESET_ON_EIDLE(1'b0), + .RXCDR_HOLD_DURING_EIDLE(1'b1), + .RXCDR_LOCK_CFG(6'b010101), + .RXCDR_PH_RESET_ON_EIDLE(1'b0), + .RXDFELPMRESET_TIME(7'b0001111), + .RXDLY_CFG(16'h001F), + .RXDLY_LCFG(9'h030), + .RXDLY_TAP_CFG(16'h0000), + .RXGEARBOX_EN("FALSE"), + .RXISCANRESET_TIME(5'b00001), + .RXLPM_HF_CFG(14'b00000011110000), + .RXLPM_LF_CFG(14'b00000011110000), + .RXOOB_CFG(7'b0000110), + .RXOUT_DIV(2), + .RXPCSRESET_TIME(5'b00001), + .RXPHDLY_CFG(24'h004020), + .RXPH_CFG(24'h000000), + .RXPH_MONITOR_SEL(5'b00000), + .RXPMARESET_TIME(5'b00011), + .RXPRBS_ERR_LOOPBACK(1'b0), + .RXSLIDE_AUTO_WAIT(7), + .RXSLIDE_MODE("PMA"), + .RX_BIAS_CFG(12'b000000000100), + .RX_BUFFER_CFG(6'b000000), + .RX_CLK25_DIV(4), + .RX_CLKMUX_PD(1'b1), + .RX_CM_SEL(2'b11), + .RX_CM_TRIM(3'b010), + .RX_DATA_WIDTH(20), + .RX_DDI_SEL(6'b000000), + .RX_DEBUG_CFG(12'b000000000000), + .RX_DEFER_RESET_BUF_EN("TRUE"), + .RX_DFE_GAIN_CFG(23'h020FEA), + .RX_DFE_H2_CFG(12'b000000000000), + .RX_DFE_H3_CFG(12'b000001000000), + .RX_DFE_H4_CFG(11'b00011110000), + .RX_DFE_H5_CFG(11'b00011100000), + .RX_DFE_KL_CFG(13'b0000011111110), + .RX_DFE_KL_CFG2(32'h3290D86C), + .RX_DFE_LPM_CFG(16'h0954), + .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1), + .RX_DFE_UT_CFG(17'b10001111000000000), + .RX_DFE_VP_CFG(17'b00011111100000011), + .RX_DFE_XYD_CFG(13'b0000000000000), + .RX_DISPERR_SEQ_MATCH("TRUE"), + .RX_INT_DATAWIDTH(0), + .RX_OS_CFG(13'b0000010000000), + .RX_SIG_VALID_DLY(4), + .RX_XCLK_SEL("RXREC"), + .SAS_MAX_COM(64), + .SAS_MIN_COM(36), + .SATA_BURST_SEQ_LEN(4'b1111), + .SATA_BURST_VAL(3'b100), + .SATA_CPLL_CFG("VCO_3000MHZ"), + .SATA_EIDLE_VAL(3'b100), + .SATA_MAX_BURST(8), + .SATA_MAX_INIT(21), + .SATA_MAX_WAKE(7), + .SATA_MIN_BURST(4), + .SATA_MIN_INIT(12), + .SATA_MIN_WAKE(4), + .SHOW_REALIGN_COMMA("FALSE"), + .SIM_CPLLREFCLK_SEL(3'b001), + .SIM_RECEIVER_DETECT_PASS("TRUE"), + .SIM_RESET_SPEEDUP("FALSE"), + .SIM_TX_EIDLE_DRIVE_LEVEL("1"), + .SIM_VERSION("3.0"), + .TERM_RCAL_CFG(5'b10000), + .TERM_RCAL_OVRD(1'b0), + .TRANS_TIME_RATE(8'h0E), + .TST_RSV(32'h00000000), + .TXBUF_EN("FALSE"), + .TXBUF_RESET_ON_RATE_CHANGE("TRUE"), + .TXDLY_CFG(16'h001F), + .TXDLY_LCFG(9'h030), + .TXDLY_TAP_CFG(16'h0000), + .TXGEARBOX_EN("FALSE"), + .TXOUT_DIV(2), + .TXPCSRESET_TIME(5'b00001), + .TXPHDLY_CFG(24'h084020), + .TXPH_CFG(16'h0780), + .TXPH_MONITOR_SEL(5'b00000), + .TXPMARESET_TIME(5'b00011), + .TX_CLK25_DIV(4), + .TX_CLKMUX_PD(1'b1), + .TX_DATA_WIDTH(20), + .TX_DEEMPH0(5'b10100), + .TX_DEEMPH1(5'b01011), + .TX_DRIVE_MODE("PIPE"), + .TX_EIDLE_ASSERT_DELAY(3'b010), + .TX_EIDLE_DEASSERT_DELAY(3'b100), + .TX_INT_DATAWIDTH(0), + .TX_LOOPBACK_DRIVE_HIZ("FALSE"), + .TX_MAINCURSOR_SEL(1'b0), + .TX_MARGIN_FULL_0(7'b1001111), + .TX_MARGIN_FULL_1(7'b1001110), + .TX_MARGIN_FULL_2(7'b1001101), + .TX_MARGIN_FULL_3(7'b1001100), + .TX_MARGIN_FULL_4(7'b1000011), + .TX_MARGIN_LOW_0(7'b1000101), + .TX_MARGIN_LOW_1(7'b1000110), + .TX_MARGIN_LOW_2(7'b1000011), + .TX_MARGIN_LOW_3(7'b1000010), + .TX_MARGIN_LOW_4(7'b1000000), + .TX_PREDRIVER_MODE(1'b0), + .TX_QPI_STATUS_EN(1'b0), + .TX_RXDETECT_CFG(14'h0064), + .TX_RXDETECT_REF(3'b011), + .TX_XCLK_SEL("TXUSR"), + .UCODEER_CLR(1'b0)) + \gtx_channel.gtxe2_channel_i + (.CFGRESET(1'b0), + .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}), + .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ), + .CPLLLOCK(QRST_CPLLLOCK), + .CPLLLOCKDETCLK(1'b0), + .CPLLLOCKEN(1'b1), + .CPLLPD(CPLLPD0_5), + .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ), + .CPLLREFCLKSEL({1'b0,1'b0,1'b1}), + .CPLLRESET(CPLLRESET0), + .DMONITOROUT({\gtx_channel.gtxe2_channel_i_n_177 ,\gtx_channel.gtxe2_channel_i_n_178 ,\gtx_channel.gtxe2_channel_i_n_179 ,\gtx_channel.gtxe2_channel_i_n_180 ,\gtx_channel.gtxe2_channel_i_n_181 ,\gtx_channel.gtxe2_channel_i_n_182 ,\gtx_channel.gtxe2_channel_i_n_183 ,\gtx_channel.gtxe2_channel_i_n_184 }), + .DRPADDR({1'b0,DRPADDR}), + .DRPCLK(pipe_dclk_in), + .DRPDI(DRPDI), + .DRPDO(DRP_DO), + .DRPEN(\cplllock_reg1_reg[3] ), + .DRPRDY(DRP_RDY), + .DRPWE(\cplllock_reg1_reg[3]_0 ), + .EYESCANDATAERROR(\gtx_channel.gtxe2_channel_i_n_4 ), + .EYESCANMODE(1'b0), + .EYESCANRESET(1'b0), + .EYESCANTRIGGER(1'b0), + .GTGREFCLK(1'b0), + .GTNORTHREFCLK0(1'b0), + .GTNORTHREFCLK1(1'b0), + .GTREFCLK0(sys_clk), + .GTREFCLK1(1'b0), + .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ), + .GTRESETSEL(1'b0), + .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .GTRXRESET(DRP_GTXRESET), + .GTSOUTHREFCLK0(1'b0), + .GTSOUTHREFCLK1(1'b0), + .GTTXRESET(DRP_GTXRESET), + .GTXRXN(pci_exp_rxn), + .GTXRXP(pci_exp_rxp), + .GTXTXN(pci_exp_txn), + .GTXTXP(pci_exp_txp), + .LOOPBACK({1'b0,1'b0,1'b0}), + .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), + .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]), + .PHYSTATUS(RATE_PHYSTATUS), + .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}), + .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), + .QPLLCLK(QPLL_QPLLOUTCLK), + .QPLLREFCLK(QPLL_QPLLOUTREFCLK), + .RESETOVRD(1'b0), + .RX8B10BEN(rxchbonden_3), + .RXBUFRESET(1'b0), + .RXBUFSTATUS({\gtx_channel.gtxe2_channel_i_n_82 ,\gtx_channel.gtxe2_channel_i_n_83 ,\gtx_channel.gtxe2_channel_i_n_84 }), + .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ), + .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ), + .RXCDRFREQRESET(1'b0), + .RXCDRHOLD(1'b0), + .RXCDRLOCK(gt_rxcdrlock_3), + .RXCDROVRDEN(1'b0), + .RXCDRRESET(1'b0), + .RXCDRRESETRSV(1'b0), + .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ), + .RXCHANISALIGNED(PIPE_RXCHANISALIGNED), + .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ), + .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }), + .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,gt_rx_data_k_wire_filter}), + .RXCHBONDEN(rxchbonden_3), + .RXCHBONDI(RXCHBONDO), + .RXCHBONDLEVEL({1'b0,1'b0,1'b0}), + .RXCHBONDMASTER(1'b0), + .RXCHBONDO({\gtx_channel.gtxe2_channel_i_n_91 ,\gtx_channel.gtxe2_channel_i_n_92 ,\gtx_channel.gtxe2_channel_i_n_93 ,\gtx_channel.gtxe2_channel_i_n_94 ,\gtx_channel.gtxe2_channel_i_n_95 }), + .RXCHBONDSLAVE(rxchbonden_3), + .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]), + .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ), + .RXCOMMADET(\gtx_channel.gtxe2_channel_i_n_16 ), + .RXCOMMADETEN(1'b1), + .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ), + .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ), + .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,gt_rx_data_wire_filter}), + .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ), + .RXDDIEN(1'b0), + .RXDFEAGCHOLD(\cplllock_reg1_reg[3]_1 ), + .RXDFEAGCOVRDEN(1'b0), + .RXDFECM1EN(1'b0), + .RXDFELFHOLD(1'b0), + .RXDFELFOVRDEN(1'b1), + .RXDFELPMRESET(1'b0), + .RXDFETAP2HOLD(1'b0), + .RXDFETAP2OVRDEN(1'b0), + .RXDFETAP3HOLD(1'b0), + .RXDFETAP3OVRDEN(1'b0), + .RXDFETAP4HOLD(1'b0), + .RXDFETAP4OVRDEN(1'b0), + .RXDFETAP5HOLD(1'b0), + .RXDFETAP5OVRDEN(1'b0), + .RXDFEUTHOLD(1'b0), + .RXDFEUTOVRDEN(1'b0), + .RXDFEVPHOLD(1'b0), + .RXDFEVPOVRDEN(1'b0), + .RXDFEVSEN(1'b0), + .RXDFEXYDEN(1'b0), + .RXDFEXYDHOLD(1'b0), + .RXDFEXYDOVRDEN(1'b0), + .RXDISPERR({\gtx_channel.gtxe2_channel_i_n_201 ,\gtx_channel.gtxe2_channel_i_n_202 ,\gtx_channel.gtxe2_channel_i_n_203 ,\gtx_channel.gtxe2_channel_i_n_204 ,\gtx_channel.gtxe2_channel_i_n_205 ,\gtx_channel.gtxe2_channel_i_n_206 ,\gtx_channel.gtxe2_channel_i_n_207 ,\gtx_channel.gtxe2_channel_i_n_208 }), + .RXDLYBYPASS(1'b1), + .RXDLYEN(1'b0), + .RXDLYOVRDEN(1'b0), + .RXDLYSRESET(1'b0), + .RXDLYSRESETDONE(pipe_dclk_in_0), + .RXELECIDLE(gt_rx_elec_idle_wire_filter), + .RXELECIDLEMODE({1'b0,1'b0}), + .RXGEARBOXSLIP(1'b0), + .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]), + .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ), + .RXLPMEN(rxchbonden_3), + .RXLPMHFHOLD(1'b0), + .RXLPMHFOVRDEN(1'b0), + .RXLPMLFHOLD(1'b0), + .RXLPMLFKLOVRDEN(1'b0), + .RXMCOMMAALIGNEN(rxchbonden_3), + .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]), + .RXMONITORSEL({1'b0,1'b0}), + .RXNOTINTABLE({\gtx_channel.gtxe2_channel_i_n_209 ,\gtx_channel.gtxe2_channel_i_n_210 ,\gtx_channel.gtxe2_channel_i_n_211 ,\gtx_channel.gtxe2_channel_i_n_212 ,\gtx_channel.gtxe2_channel_i_n_213 ,\gtx_channel.gtxe2_channel_i_n_214 ,\gtx_channel.gtxe2_channel_i_n_215 ,\gtx_channel.gtxe2_channel_i_n_216 }), + .RXOOBRESET(1'b0), + .RXOSHOLD(1'b0), + .RXOSOVRDEN(1'b0), + .RXOUTCLK(pipe_rxoutclk_out), + .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ), + .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ), + .RXOUTCLKSEL({1'b0,1'b0,1'b0}), + .RXPCOMMAALIGNEN(rxchbonden_3), + .RXPCSRESET(1'b0), + .RXPD(PIPE_POWERDOWN), + .RXPHALIGN(1'b0), + .RXPHALIGNDONE(pipe_dclk_in_1), + .RXPHALIGNEN(1'b0), + .RXPHDLYPD(1'b0), + .RXPHDLYRESET(1'b0), + .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]), + .RXPHOVRDEN(1'b0), + .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]), + .RXPMARESET(rate_txpmareset_3), + .RXPOLARITY(PIPE_RXPOLARITY), + .RXPRBSCNTRESET(1'b0), + .RXPRBSERR(\gtx_channel.gtxe2_channel_i_n_27 ), + .RXPRBSSEL({1'b0,1'b0,1'b0}), + .RXQPIEN(1'b0), + .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ), + .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ), + .RXRATE({1'b0,1'b0,RXRATE}), + .RXRATEDONE(RATE_RXRATEDONE), + .RXRESETDONE(USER_RXRESETDONE), + .RXSLIDE(1'b0), + .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ), + .RXSTATUS(pipe_dclk_in_5), + .RXSYSCLKSEL({1'b0,RXSYSCLKSEL}), + .RXUSERRDY(rst_userrdy), + .RXUSRCLK(pipe_rxusrclk_in), + .RXUSRCLK2(pipe_rxusrclk_in), + .RXVALID(gt_rxvalid_3), + .SETERRSTATUS(1'b0), + .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]), + .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .TX8B10BEN(rxchbonden_3), + .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}), + .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]), + .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}), + .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}), + .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ), + .TXCOMINIT(1'b0), + .TXCOMSAS(1'b0), + .TXCOMWAKE(1'b0), + .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}), + .TXDEEMPH(pipe_tx_deemph_gt), + .TXDETECTRX(pipe_tx_rcvr_det_gt), + .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}), + .TXDIFFPD(1'b0), + .TXDLYBYPASS(1'b0), + .TXDLYEN(1'b0), + .TXDLYHOLD(1'b0), + .TXDLYOVRDEN(1'b0), + .TXDLYSRESET(SYNC_TXDLYSRESET), + .TXDLYSRESETDONE(pipe_dclk_in_2), + .TXDLYUPDOWN(1'b0), + .TXELECIDLE(PIPE_TXELECIDLE), + .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ), + .TXHEADER({1'b0,1'b0,1'b0}), + .TXINHIBIT(1'b0), + .TXMAINCURSOR(TXMAINCURSOR), + .TXMARGIN(\cplllock_reg1_reg[3]_2 ), + .TXOUTCLK(\gtx_channel.gtxe2_channel_i_n_37 ), + .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ), + .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ), + .TXOUTCLKSEL({1'b0,1'b0,1'b0}), + .TXPCSRESET(1'b0), + .TXPD(PIPE_POWERDOWN), + .TXPDELECIDLEMODE(1'b0), + .TXPHALIGN(SYNC_TXPHALIGN), + .TXPHALIGNDONE(pipe_dclk_in_3), + .TXPHALIGNEN(1'b1), + .TXPHDLYPD(1'b0), + .TXPHDLYRESET(1'b0), + .TXPHDLYTSTCLK(1'b0), + .TXPHINIT(SYNC_TXPHINIT), + .TXPHINITDONE(pipe_dclk_in_4), + .TXPHOVRDEN(1'b0), + .TXPISOPD(1'b0), + .TXPMARESET(rate_txpmareset_3), + .TXPOLARITY(1'b0), + .TXPOSTCURSOR(TXPOSTCURSOR), + .TXPOSTCURSORINV(1'b0), + .TXPRBSFORCEERR(1'b0), + .TXPRBSSEL({1'b0,1'b0,1'b0}), + .TXPRECURSOR(TXPRECURSOR), + .TXPRECURSORINV(1'b0), + .TXQPIBIASEN(1'b0), + .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ), + .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ), + .TXQPISTRONGPDOWN(1'b0), + .TXQPIWEAKPUP(1'b0), + .TXRATE({1'b0,1'b0,RXRATE}), + .TXRATEDONE(RATE_TXRATEDONE), + .TXRESETDONE(USER_TXRESETDONE), + .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .TXSTARTSEQ(1'b0), + .TXSWING(1'b0), + .TXSYSCLKSEL({1'b0,RXSYSCLKSEL}), + .TXUSERRDY(rst_userrdy), + .TXUSRCLK(pipe_pclk_in), + .TXUSRCLK2(pipe_pclk_in)); +endmodule + +module pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd + (cpllpd_2, + CPLLRESET0, + gt_cpllpdrefclk, + rate_cpllreset_3, + RST_CPLLRESET); + output cpllpd_2; + output CPLLRESET0; + input gt_cpllpdrefclk; + input rate_cpllreset_3; + input RST_CPLLRESET; + + wire CPLLRESET0; + wire RST_CPLLRESET; + wire cpllpd_2; + wire \cpllpd_wait_reg[31]_srl32_n_1 ; + wire \cpllpd_wait_reg[63]_srl32_n_1 ; + wire \cpllpd_wait_reg[94]_srl31_n_0 ; + wire \cpllreset_wait_reg[126]_srl31_n_0 ; + wire \cpllreset_wait_reg[31]_srl32_n_1 ; + wire \cpllreset_wait_reg[63]_srl32_n_1 ; + wire \cpllreset_wait_reg[95]_srl32_n_1 ; + wire cpllrst; + wire gt_cpllpdrefclk; + wire rate_cpllreset_3; + wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ; + + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *) + SRLC32E #( + .INIT(32'hFFFFFFFF)) + \cpllpd_wait_reg[31]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(1'b0), + .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ), + .Q31(\cpllpd_wait_reg[31]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *) + SRLC32E #( + .INIT(32'hFFFFFFFF)) + \cpllpd_wait_reg[63]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllpd_wait_reg[31]_srl32_n_1 ), + .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ), + .Q31(\cpllpd_wait_reg[63]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *) + SRLC32E #( + .INIT(32'h7FFFFFFF)) + \cpllpd_wait_reg[94]_srl31 + (.A({1'b1,1'b1,1'b1,1'b1,1'b0}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllpd_wait_reg[63]_srl32_n_1 ), + .Q(\cpllpd_wait_reg[94]_srl31_n_0 ), + .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED )); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + \cpllpd_wait_reg[95] + (.C(gt_cpllpdrefclk), + .CE(1'b1), + .D(\cpllpd_wait_reg[94]_srl31_n_0 ), + .Q(cpllpd_2), + .R(1'b0)); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *) + SRLC32E #( + .INIT(32'h00000000)) + \cpllreset_wait_reg[126]_srl31 + (.A({1'b1,1'b1,1'b1,1'b1,1'b0}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllreset_wait_reg[95]_srl32_n_1 ), + .Q(\cpllreset_wait_reg[126]_srl31_n_0 ), + .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED )); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \cpllreset_wait_reg[127] + (.C(gt_cpllpdrefclk), + .CE(1'b1), + .D(\cpllreset_wait_reg[126]_srl31_n_0 ), + .Q(cpllrst), + .R(1'b0)); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *) + SRLC32E #( + .INIT(32'h000000FF)) + \cpllreset_wait_reg[31]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(1'b0), + .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ), + .Q31(\cpllreset_wait_reg[31]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \cpllreset_wait_reg[63]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllreset_wait_reg[31]_srl32_n_1 ), + .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ), + .Q31(\cpllreset_wait_reg[63]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \cpllreset_wait_reg[95]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllreset_wait_reg[63]_srl32_n_1 ), + .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ), + .Q31(\cpllreset_wait_reg[95]_srl32_n_1 )); + LUT3 #( + .INIT(8'hFE)) + \gtx_channel.gtxe2_channel_i_i_2__2 + (.I0(cpllrst), + .I1(rate_cpllreset_3), + .I2(RST_CPLLRESET), + .O(CPLLRESET0)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_gtx_cpllpd_ovrd" *) +module pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_56 + (cpllpd_1, + CPLLRESET0, + gt_cpllpdrefclk, + rate_cpllreset_2, + RST_CPLLRESET); + output cpllpd_1; + output CPLLRESET0; + input gt_cpllpdrefclk; + input rate_cpllreset_2; + input RST_CPLLRESET; + + wire CPLLRESET0; + wire RST_CPLLRESET; + wire cpllpd_1; + wire \cpllpd_wait_reg[31]_srl32_n_1 ; + wire \cpllpd_wait_reg[63]_srl32_n_1 ; + wire \cpllpd_wait_reg[94]_srl31_n_0 ; + wire \cpllreset_wait_reg[126]_srl31_n_0 ; + wire \cpllreset_wait_reg[31]_srl32_n_1 ; + wire \cpllreset_wait_reg[63]_srl32_n_1 ; + wire \cpllreset_wait_reg[95]_srl32_n_1 ; + wire cpllrst; + wire gt_cpllpdrefclk; + wire rate_cpllreset_2; + wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ; + + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *) + SRLC32E #( + .INIT(32'hFFFFFFFF)) + \cpllpd_wait_reg[31]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(1'b0), + .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ), + .Q31(\cpllpd_wait_reg[31]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *) + SRLC32E #( + .INIT(32'hFFFFFFFF)) + \cpllpd_wait_reg[63]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllpd_wait_reg[31]_srl32_n_1 ), + .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ), + .Q31(\cpllpd_wait_reg[63]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *) + SRLC32E #( + .INIT(32'h7FFFFFFF)) + \cpllpd_wait_reg[94]_srl31 + (.A({1'b1,1'b1,1'b1,1'b1,1'b0}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllpd_wait_reg[63]_srl32_n_1 ), + .Q(\cpllpd_wait_reg[94]_srl31_n_0 ), + .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED )); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + \cpllpd_wait_reg[95] + (.C(gt_cpllpdrefclk), + .CE(1'b1), + .D(\cpllpd_wait_reg[94]_srl31_n_0 ), + .Q(cpllpd_1), + .R(1'b0)); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *) + SRLC32E #( + .INIT(32'h00000000)) + \cpllreset_wait_reg[126]_srl31 + (.A({1'b1,1'b1,1'b1,1'b1,1'b0}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllreset_wait_reg[95]_srl32_n_1 ), + .Q(\cpllreset_wait_reg[126]_srl31_n_0 ), + .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED )); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \cpllreset_wait_reg[127] + (.C(gt_cpllpdrefclk), + .CE(1'b1), + .D(\cpllreset_wait_reg[126]_srl31_n_0 ), + .Q(cpllrst), + .R(1'b0)); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *) + SRLC32E #( + .INIT(32'h000000FF)) + \cpllreset_wait_reg[31]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(1'b0), + .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ), + .Q31(\cpllreset_wait_reg[31]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \cpllreset_wait_reg[63]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllreset_wait_reg[31]_srl32_n_1 ), + .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ), + .Q31(\cpllreset_wait_reg[63]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \cpllreset_wait_reg[95]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllreset_wait_reg[63]_srl32_n_1 ), + .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ), + .Q31(\cpllreset_wait_reg[95]_srl32_n_1 )); + LUT3 #( + .INIT(8'hFE)) + \gtx_channel.gtxe2_channel_i_i_2__1 + (.I0(cpllrst), + .I1(rate_cpllreset_2), + .I2(RST_CPLLRESET), + .O(CPLLRESET0)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_gtx_cpllpd_ovrd" *) +module pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_58 + (cpllpd_0, + CPLLRESET0, + gt_cpllpdrefclk, + rate_cpllreset_1, + RST_CPLLRESET); + output cpllpd_0; + output CPLLRESET0; + input gt_cpllpdrefclk; + input rate_cpllreset_1; + input RST_CPLLRESET; + + wire CPLLRESET0; + wire RST_CPLLRESET; + wire cpllpd_0; + wire \cpllpd_wait_reg[31]_srl32_n_1 ; + wire \cpllpd_wait_reg[63]_srl32_n_1 ; + wire \cpllpd_wait_reg[94]_srl31_n_0 ; + wire \cpllreset_wait_reg[126]_srl31_n_0 ; + wire \cpllreset_wait_reg[31]_srl32_n_1 ; + wire \cpllreset_wait_reg[63]_srl32_n_1 ; + wire \cpllreset_wait_reg[95]_srl32_n_1 ; + wire cpllrst; + wire gt_cpllpdrefclk; + wire rate_cpllreset_1; + wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ; + + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *) + SRLC32E #( + .INIT(32'hFFFFFFFF)) + \cpllpd_wait_reg[31]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(1'b0), + .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ), + .Q31(\cpllpd_wait_reg[31]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *) + SRLC32E #( + .INIT(32'hFFFFFFFF)) + \cpllpd_wait_reg[63]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllpd_wait_reg[31]_srl32_n_1 ), + .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ), + .Q31(\cpllpd_wait_reg[63]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *) + SRLC32E #( + .INIT(32'h7FFFFFFF)) + \cpllpd_wait_reg[94]_srl31 + (.A({1'b1,1'b1,1'b1,1'b1,1'b0}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllpd_wait_reg[63]_srl32_n_1 ), + .Q(\cpllpd_wait_reg[94]_srl31_n_0 ), + .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED )); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + \cpllpd_wait_reg[95] + (.C(gt_cpllpdrefclk), + .CE(1'b1), + .D(\cpllpd_wait_reg[94]_srl31_n_0 ), + .Q(cpllpd_0), + .R(1'b0)); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *) + SRLC32E #( + .INIT(32'h00000000)) + \cpllreset_wait_reg[126]_srl31 + (.A({1'b1,1'b1,1'b1,1'b1,1'b0}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllreset_wait_reg[95]_srl32_n_1 ), + .Q(\cpllreset_wait_reg[126]_srl31_n_0 ), + .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED )); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \cpllreset_wait_reg[127] + (.C(gt_cpllpdrefclk), + .CE(1'b1), + .D(\cpllreset_wait_reg[126]_srl31_n_0 ), + .Q(cpllrst), + .R(1'b0)); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *) + SRLC32E #( + .INIT(32'h000000FF)) + \cpllreset_wait_reg[31]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(1'b0), + .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ), + .Q31(\cpllreset_wait_reg[31]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \cpllreset_wait_reg[63]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllreset_wait_reg[31]_srl32_n_1 ), + .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ), + .Q31(\cpllreset_wait_reg[63]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \cpllreset_wait_reg[95]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllreset_wait_reg[63]_srl32_n_1 ), + .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ), + .Q31(\cpllreset_wait_reg[95]_srl32_n_1 )); + LUT3 #( + .INIT(8'hFE)) + \gtx_channel.gtxe2_channel_i_i_2__0 + (.I0(cpllrst), + .I1(rate_cpllreset_1), + .I2(RST_CPLLRESET), + .O(CPLLRESET0)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_gtx_cpllpd_ovrd" *) +module pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_60 + (cpllpd, + CPLLRESET0, + gt_cpllpdrefclk, + rate_cpllreset_0, + RST_CPLLRESET); + output cpllpd; + output CPLLRESET0; + input gt_cpllpdrefclk; + input rate_cpllreset_0; + input RST_CPLLRESET; + + wire CPLLRESET0; + wire RST_CPLLRESET; + wire cpllpd; + wire \cpllpd_wait_reg[31]_srl32_n_1 ; + wire \cpllpd_wait_reg[63]_srl32_n_1 ; + wire \cpllpd_wait_reg[94]_srl31_n_0 ; + wire \cpllreset_wait_reg[126]_srl31_n_0 ; + wire \cpllreset_wait_reg[31]_srl32_n_1 ; + wire \cpllreset_wait_reg[63]_srl32_n_1 ; + wire \cpllreset_wait_reg[95]_srl32_n_1 ; + wire cpllrst; + wire gt_cpllpdrefclk; + wire rate_cpllreset_0; + wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ; + wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ; + + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *) + SRLC32E #( + .INIT(32'hFFFFFFFF)) + \cpllpd_wait_reg[31]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(1'b0), + .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ), + .Q31(\cpllpd_wait_reg[31]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *) + SRLC32E #( + .INIT(32'hFFFFFFFF)) + \cpllpd_wait_reg[63]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllpd_wait_reg[31]_srl32_n_1 ), + .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ), + .Q31(\cpllpd_wait_reg[63]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *) + SRLC32E #( + .INIT(32'h7FFFFFFF)) + \cpllpd_wait_reg[94]_srl31 + (.A({1'b1,1'b1,1'b1,1'b1,1'b0}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllpd_wait_reg[63]_srl32_n_1 ), + .Q(\cpllpd_wait_reg[94]_srl31_n_0 ), + .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED )); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + \cpllpd_wait_reg[95] + (.C(gt_cpllpdrefclk), + .CE(1'b1), + .D(\cpllpd_wait_reg[94]_srl31_n_0 ), + .Q(cpllpd), + .R(1'b0)); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *) + SRLC32E #( + .INIT(32'h00000000)) + \cpllreset_wait_reg[126]_srl31 + (.A({1'b1,1'b1,1'b1,1'b1,1'b0}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllreset_wait_reg[95]_srl32_n_1 ), + .Q(\cpllreset_wait_reg[126]_srl31_n_0 ), + .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED )); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \cpllreset_wait_reg[127] + (.C(gt_cpllpdrefclk), + .CE(1'b1), + .D(\cpllreset_wait_reg[126]_srl31_n_0 ), + .Q(cpllrst), + .R(1'b0)); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *) + SRLC32E #( + .INIT(32'h000000FF)) + \cpllreset_wait_reg[31]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(1'b0), + .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ), + .Q31(\cpllreset_wait_reg[31]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \cpllreset_wait_reg[63]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllreset_wait_reg[31]_srl32_n_1 ), + .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ), + .Q31(\cpllreset_wait_reg[63]_srl32_n_1 )); + (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) + (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *) + SRLC32E #( + .INIT(32'h00000000)) + \cpllreset_wait_reg[95]_srl32 + (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), + .CE(1'b1), + .CLK(gt_cpllpdrefclk), + .D(\cpllreset_wait_reg[63]_srl32_n_1 ), + .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ), + .Q31(\cpllreset_wait_reg[95]_srl32_n_1 )); + LUT3 #( + .INIT(8'hFE)) + \gtx_channel.gtxe2_channel_i_i_2 + (.I0(cpllrst), + .I1(rate_cpllreset_0), + .I2(RST_CPLLRESET), + .O(CPLLRESET0)); +endmodule + +(* CFG_CTL_IF = "TRUE" *) (* CFG_FC_IF = "TRUE" *) (* CFG_MGMT_IF = "TRUE" *) +(* CFG_STATUS_IF = "TRUE" *) (* C_DATA_WIDTH = "64" *) (* DowngradeIPIdentifiedWarnings = "yes" *) +(* ENABLE_JTAG_DBG = "FALSE" *) (* ERR_REPORTING_IF = "TRUE" *) (* EXT_CH_GT_DRP = "FALSE" *) +(* EXT_PIPE_INTERFACE = "FALSE" *) (* EXT_STARTUP_PRIMITIVE = "FALSE" *) (* KEEP_WIDTH = "8" *) +(* LINK_CAP_MAX_LINK_WIDTH = "4" *) (* PCIE_ASYNC_EN = "FALSE" *) (* PCIE_EXT_CLK = "TRUE" *) +(* PCIE_EXT_GT_COMMON = "FALSE" *) (* PIPE_SIM = "FALSE" *) (* PL_INTERFACE = "TRUE" *) +(* RCV_MSG_IF = "TRUE" *) (* REDUCE_OOB_FREQ = "FALSE" *) (* SHARED_LOGIC_IN_CORE = "FALSE" *) +(* TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE" *) (* bar_0 = "FFFF0000" *) (* bar_1 = "00000000" *) +(* bar_2 = "00000000" *) (* bar_3 = "00000000" *) (* bar_4 = "00000000" *) +(* bar_5 = "00000000" *) (* bram_lat = "0" *) (* c_aer_base_ptr = "000" *) +(* c_aer_cap_ecrc_check_capable = "FALSE" *) (* c_aer_cap_ecrc_gen_capable = "FALSE" *) (* c_aer_cap_multiheader = "FALSE" *) +(* c_aer_cap_nextptr = "000" *) (* c_aer_cap_on = "FALSE" *) (* c_aer_cap_optional_err_support = "000000" *) +(* c_aer_cap_permit_rooterr_update = "FALSE" *) (* c_buf_opt_bma = "TRUE" *) (* c_component_name = "pcie_7x_0" *) +(* c_cpl_inf = "TRUE" *) (* c_cpl_infinite = "TRUE" *) (* c_cpl_timeout_disable_sup = "FALSE" *) +(* c_cpl_timeout_range = "0010" *) (* c_cpl_timeout_ranges_sup = "2" *) (* c_d1_support = "FALSE" *) +(* c_d2_support = "FALSE" *) (* c_de_emph = "FALSE" *) (* c_dev_cap2_ari_forwarding_supported = "FALSE" *) +(* c_dev_cap2_atomicop32_completer_supported = "FALSE" *) (* c_dev_cap2_atomicop64_completer_supported = "FALSE" *) (* c_dev_cap2_atomicop_routing_supported = "FALSE" *) +(* c_dev_cap2_cas128_completer_supported = "FALSE" *) (* c_dev_cap2_tph_completer_supported = "00" *) (* c_dev_control_ext_tag_default = "FALSE" *) +(* c_dev_port_type = "0" *) (* c_dis_lane_reverse = "TRUE" *) (* c_disable_rx_poisoned_resp = "FALSE" *) +(* c_disable_scrambling = "FALSE" *) (* c_disable_tx_aspm_l0s = "FALSE" *) (* c_dll_lnk_actv_cap = "FALSE" *) +(* c_dsi_bool = "FALSE" *) (* c_dsn_base_ptr = "100" *) (* c_dsn_cap_enabled = "TRUE" *) +(* c_dsn_next_ptr = "000" *) (* c_enable_msg_route = "00000000000" *) (* c_ep_l0s_accpt_lat = "0" *) +(* c_ep_l1_accpt_lat = "7" *) (* c_ext_pci_cfg_space_addr = "3FF" *) (* c_external_clocking = "TRUE" *) +(* c_fc_cpld = "973" *) (* c_fc_cplh = "36" *) (* c_fc_npd = "24" *) +(* c_fc_nph = "12" *) (* c_fc_pd = "949" *) (* c_fc_ph = "32" *) +(* c_gen1 = "1'b1" *) (* c_header_type = "00" *) (* c_hw_auton_spd_disable = "FALSE" *) +(* c_int_width = "64" *) (* c_last_cfg_dw = "10C" *) (* c_link_cap_aspm_optionality = "FALSE" *) +(* c_ll_ack_timeout = "0000" *) (* c_ll_ack_timeout_enable = "FALSE" *) (* c_ll_ack_timeout_function = "0" *) +(* c_ll_replay_timeout = "0000" *) (* c_ll_replay_timeout_enable = "FALSE" *) (* c_ll_replay_timeout_func = "1" *) +(* c_lnk_bndwdt_notif = "FALSE" *) (* c_msi = "0" *) (* c_msi_64b_addr = "TRUE" *) +(* c_msi_cap_on = "FALSE" *) (* c_msi_mult_msg_extn = "0" *) (* c_msi_per_vctr_mask_cap = "FALSE" *) +(* c_msix_cap_on = "FALSE" *) (* c_msix_next_ptr = "00" *) (* c_msix_pba_bir = "0" *) +(* c_msix_pba_offset = "0" *) (* c_msix_table_bir = "0" *) (* c_msix_table_offset = "0" *) +(* c_msix_table_size = "000" *) (* c_pci_cfg_space_addr = "3F" *) (* c_pcie_blk_locn = "0" *) +(* c_pcie_cap_next_ptr = "00" *) (* c_pcie_cap_slot_implemented = "FALSE" *) (* c_pcie_dbg_ports = "TRUE" *) +(* c_pcie_fast_config = "0" *) (* c_perf_level_high = "TRUE" *) (* c_phantom_functions = "0" *) +(* c_pm_cap_next_ptr = "60" *) (* c_pme_support = "0F" *) (* c_rbar_base_ptr = "000" *) +(* c_rbar_cap_control_encodedbar0 = "00" *) (* c_rbar_cap_control_encodedbar1 = "00" *) (* c_rbar_cap_control_encodedbar2 = "00" *) +(* c_rbar_cap_control_encodedbar3 = "00" *) (* c_rbar_cap_control_encodedbar4 = "00" *) (* c_rbar_cap_control_encodedbar5 = "00" *) +(* c_rbar_cap_index0 = "0" *) (* c_rbar_cap_index1 = "0" *) (* c_rbar_cap_index2 = "0" *) +(* c_rbar_cap_index3 = "0" *) (* c_rbar_cap_index4 = "0" *) (* c_rbar_cap_index5 = "0" *) +(* c_rbar_cap_nextptr = "000" *) (* c_rbar_cap_on = "FALSE" *) (* c_rbar_cap_sup0 = "00001" *) +(* c_rbar_cap_sup1 = "00001" *) (* c_rbar_cap_sup2 = "00001" *) (* c_rbar_cap_sup3 = "00001" *) +(* c_rbar_cap_sup4 = "00001" *) (* c_rbar_cap_sup5 = "00001" *) (* c_rbar_num = "0" *) +(* c_rcb = "0" *) (* c_recrc_check = "0" *) (* c_recrc_check_trim = "FALSE" *) +(* c_rev_gt_order = "FALSE" *) (* c_root_cap_crs = "FALSE" *) (* c_rx_raddr_lat = "0" *) +(* c_rx_ram_limit = "FFF" *) (* c_rx_rdata_lat = "2" *) (* c_rx_write_lat = "0" *) +(* c_silicon_rev = "2" *) (* c_slot_cap_attn_butn = "FALSE" *) (* c_slot_cap_attn_ind = "FALSE" *) +(* c_slot_cap_elec_interlock = "FALSE" *) (* c_slot_cap_hotplug_cap = "FALSE" *) (* c_slot_cap_hotplug_surprise = "FALSE" *) +(* c_slot_cap_mrl = "FALSE" *) (* c_slot_cap_no_cmd_comp_sup = "FALSE" *) (* c_slot_cap_physical_slot_num = "0" *) +(* c_slot_cap_pwr_ctrl = "FALSE" *) (* c_slot_cap_pwr_ind = "FALSE" *) (* c_slot_cap_pwr_limit_scale = "0" *) +(* c_slot_cap_pwr_limit_value = "0" *) (* c_surprise_dn_err_cap = "FALSE" *) (* c_trgt_lnk_spd = "2" *) +(* c_trn_np_fc = "TRUE" *) (* c_tx_last_tlp = "30" *) (* c_tx_raddr_lat = "0" *) +(* c_tx_rdata_lat = "2" *) (* c_tx_write_lat = "0" *) (* c_upconfig_capable = "TRUE" *) +(* c_upstream_facing = "TRUE" *) (* c_ur_atomic = "FALSE" *) (* c_ur_inv_req = "TRUE" *) +(* c_ur_prs_response = "TRUE" *) (* c_vc_base_ptr = "000" *) (* c_vc_cap_enabled = "FALSE" *) +(* c_vc_cap_reject_snoop = "FALSE" *) (* c_vc_next_ptr = "000" *) (* c_vsec_base_ptr = "000" *) +(* c_vsec_cap_enabled = "FALSE" *) (* c_vsec_next_ptr = "000" *) (* c_xlnx_ref_board = "ZC706" *) +(* cap_ver = "2" *) (* cardbus_cis_ptr = "00000000" *) (* class_code = "050000" *) +(* cmps = "3" *) (* con_scl_fctr_d0_state = "0" *) (* con_scl_fctr_d1_state = "0" *) +(* con_scl_fctr_d2_state = "0" *) (* con_scl_fctr_d3_state = "0" *) (* cost_table = "1" *) +(* d1_sup = "0" *) (* d2_sup = "0" *) (* dev_id = "7024" *) +(* dev_port_type = "0000" *) (* dis_scl_fctr_d0_state = "0" *) (* dis_scl_fctr_d1_state = "0" *) +(* dis_scl_fctr_d2_state = "0" *) (* dis_scl_fctr_d3_state = "0" *) (* dsi = "0" *) +(* ep_l0s_accpt_lat = "000" *) (* ep_l1_accpt_lat = "111" *) (* ext_tag_fld_sup = "FALSE" *) +(* int_pin = "1" *) (* intx = "TRUE" *) (* max_lnk_spd = "2" *) +(* max_lnk_wdt = "000100" *) (* mps = "011" *) (* no_soft_rst = "TRUE" *) +(* pci_exp_int_freq = "3" *) (* pci_exp_ref_freq = "0" *) (* phantm_func_sup = "00" *) +(* pme_sup = "0F" *) (* pwr_con_d0_state = "00" *) (* pwr_con_d1_state = "00" *) +(* pwr_con_d2_state = "00" *) (* pwr_con_d3_state = "00" *) (* pwr_dis_d0_state = "00" *) +(* pwr_dis_d1_state = "00" *) (* pwr_dis_d2_state = "00" *) (* pwr_dis_d3_state = "00" *) +(* rev_id = "00" *) (* slot_clk = "TRUE" *) (* subsys_id = "0007" *) +(* subsys_ven_id = "10EE" *) (* ven_id = "10EE" *) (* xrom_bar = "00000000" *) +module pcie_7x_0_pcie_7x_0_pcie2_top + (pci_exp_txn, + pci_exp_txp, + pci_exp_rxn, + pci_exp_rxp, + int_pclk_out_slave, + int_pipe_rxusrclk_out, + int_rxoutclk_out, + int_dclk_out, + int_userclk1_out, + int_userclk2_out, + int_oobclk_out, + int_mmcm_lock_out, + int_qplllock_out, + int_qplloutclk_out, + int_qplloutrefclk_out, + int_pclk_sel_slave, + pipe_pclk_in, + pipe_rxusrclk_in, + pipe_rxoutclk_in, + pipe_dclk_in, + pipe_userclk1_in, + pipe_userclk2_in, + pipe_oobclk_in, + pipe_mmcm_lock_in, + pipe_txoutclk_out, + pipe_rxoutclk_out, + pipe_pclk_sel_out, + pipe_gen3_out, + qpll_drp_crscode, + qpll_drp_fsm, + qpll_drp_done, + qpll_drp_reset, + qpll_qplllock, + qpll_qplloutclk, + qpll_qplloutrefclk, + qpll_qplld, + qpll_qpllreset, + qpll_drp_clk, + qpll_drp_rst_n, + qpll_drp_ovrd, + qpll_drp_gen3, + qpll_drp_start, + user_clk_out, + user_reset_out, + user_lnk_up, + user_app_rdy, + tx_buf_av, + tx_err_drop, + tx_cfg_req, + s_axis_tx_tdata, + s_axis_tx_tvalid, + s_axis_tx_tready, + s_axis_tx_tkeep, + s_axis_tx_tlast, + s_axis_tx_tuser, + tx_cfg_gnt, + m_axis_rx_tdata, + m_axis_rx_tvalid, + m_axis_rx_tready, + m_axis_rx_tkeep, + m_axis_rx_tlast, + m_axis_rx_tuser, + rx_np_ok, + rx_np_req, + fc_cpld, + fc_cplh, + fc_npd, + fc_nph, + fc_pd, + fc_ph, + fc_sel, + cfg_mgmt_do, + cfg_mgmt_rd_wr_done, + cfg_status, + cfg_command, + cfg_dstatus, + cfg_dcommand, + cfg_lstatus, + cfg_lcommand, + cfg_dcommand2, + cfg_pcie_link_state, + cfg_pmcsr_pme_en, + cfg_pmcsr_powerstate, + cfg_pmcsr_pme_status, + cfg_received_func_lvl_rst, + cfg_mgmt_di, + cfg_mgmt_byte_en, + cfg_mgmt_dwaddr, + cfg_mgmt_wr_en, + cfg_mgmt_rd_en, + cfg_mgmt_wr_readonly, + cfg_err_ecrc, + cfg_err_ur, + cfg_err_cpl_timeout, + cfg_err_cpl_unexpect, + cfg_err_cpl_abort, + cfg_err_posted, + cfg_err_cor, + cfg_err_atomic_egress_blocked, + cfg_err_internal_cor, + cfg_err_malformed, + cfg_err_mc_blocked, + cfg_err_poisoned, + cfg_err_norecovery, + cfg_err_tlp_cpl_header, + cfg_err_cpl_rdy, + cfg_err_locked, + cfg_err_acs, + cfg_err_internal_uncor, + cfg_trn_pending, + cfg_pm_halt_aspm_l0s, + cfg_pm_halt_aspm_l1, + cfg_pm_force_state_en, + cfg_pm_force_state, + cfg_dsn, + cfg_msg_received, + cfg_msg_data, + cfg_interrupt, + cfg_interrupt_rdy, + cfg_interrupt_assert, + cfg_interrupt_di, + cfg_interrupt_do, + cfg_interrupt_mmenable, + cfg_interrupt_msienable, + cfg_interrupt_msixenable, + cfg_interrupt_msixfm, + cfg_interrupt_stat, + cfg_pciecap_interrupt_msgnum, + cfg_to_turnoff, + cfg_turnoff_ok, + cfg_bus_number, + cfg_device_number, + cfg_function_number, + cfg_pm_wake, + cfg_msg_received_pm_as_nak, + cfg_msg_received_setslotpowerlimit, + cfg_pm_send_pme_to, + cfg_ds_bus_number, + cfg_ds_device_number, + cfg_ds_function_number, + cfg_mgmt_wr_rw1c_as_rw, + cfg_bridge_serr_en, + cfg_slot_control_electromech_il_ctl_pulse, + cfg_root_control_syserr_corr_err_en, + cfg_root_control_syserr_non_fatal_err_en, + cfg_root_control_syserr_fatal_err_en, + cfg_root_control_pme_int_en, + cfg_aer_rooterr_corr_err_reporting_en, + cfg_aer_rooterr_non_fatal_err_reporting_en, + cfg_aer_rooterr_fatal_err_reporting_en, + cfg_aer_rooterr_corr_err_received, + cfg_aer_rooterr_non_fatal_err_received, + cfg_aer_rooterr_fatal_err_received, + cfg_msg_received_err_cor, + cfg_msg_received_err_non_fatal, + cfg_msg_received_err_fatal, + cfg_msg_received_pm_pme, + cfg_msg_received_pme_to_ack, + cfg_msg_received_assert_int_a, + cfg_msg_received_assert_int_b, + cfg_msg_received_assert_int_c, + cfg_msg_received_assert_int_d, + cfg_msg_received_deassert_int_a, + cfg_msg_received_deassert_int_b, + cfg_msg_received_deassert_int_c, + cfg_msg_received_deassert_int_d, + pl_directed_link_change, + pl_directed_link_width, + pl_directed_link_speed, + pl_directed_link_auton, + pl_upstream_prefer_deemph, + pl_sel_lnk_rate, + pl_sel_lnk_width, + pl_ltssm_state, + pl_lane_reversal_mode, + pl_phy_lnk_up, + pl_tx_pm_state, + pl_rx_pm_state, + pl_link_upcfg_cap, + pl_link_gen2_cap, + pl_link_partner_gen2_supported, + pl_initial_link_width, + pl_directed_change_done, + pl_received_hot_rst, + pl_transmit_hot_rst, + pl_downstream_deemph_source, + cfg_err_aer_headerlog, + cfg_aer_interrupt_msgnum, + cfg_err_aer_headerlog_set, + cfg_aer_ecrc_check_en, + cfg_aer_ecrc_gen_en, + cfg_vc_tcvc_map, + pcie_drp_clk, + pcie_drp_en, + pcie_drp_we, + pcie_drp_addr, + pcie_drp_di, + pcie_drp_rdy, + pcie_drp_do, + startup_eos_in, + startup_cfgclk, + startup_cfgmclk, + startup_eos, + startup_preq, + startup_clk, + startup_gsr, + startup_gts, + startup_keyclearb, + startup_pack, + startup_usrcclko, + startup_usrcclkts, + startup_usrdoneo, + startup_usrdonets, + icap_clk, + icap_csib, + icap_rdwrb, + icap_i, + icap_o, + pipe_txprbssel, + pipe_rxprbssel, + pipe_txprbsforceerr, + pipe_rxprbscntreset, + pipe_loopback, + pipe_rxprbserr, + pipe_txinhibit, + pipe_rst_fsm, + pipe_qrst_fsm, + pipe_rate_fsm, + pipe_sync_fsm_tx, + pipe_sync_fsm_rx, + pipe_drp_fsm, + pipe_rst_idle, + pipe_qrst_idle, + pipe_rate_idle, + pipe_eyescandataerror, + pipe_rxstatus, + pipe_dmonitorout, + pipe_cpll_lock, + pipe_qpll_lock, + pipe_rxpmaresetdone, + pipe_rxbufstatus, + pipe_txphaligndone, + pipe_txphinitdone, + pipe_txdlysresetdone, + pipe_rxphaligndone, + pipe_rxdlysresetdone, + pipe_rxsyncdone, + pipe_rxdisperr, + pipe_rxnotintable, + pipe_rxcommadet, + gt_ch_drp_rdy, + pipe_debug_0, + pipe_debug_1, + pipe_debug_2, + pipe_debug_3, + pipe_debug_4, + pipe_debug_5, + pipe_debug_6, + pipe_debug_7, + pipe_debug_8, + pipe_debug_9, + pipe_debug, + ext_ch_gt_drpclk, + ext_ch_gt_drpaddr, + ext_ch_gt_drpen, + ext_ch_gt_drpdi, + ext_ch_gt_drpwe, + ext_ch_gt_drpdo, + ext_ch_gt_drprdy, + common_commands_in, + pipe_rx_0_sigs, + pipe_rx_1_sigs, + pipe_rx_2_sigs, + pipe_rx_3_sigs, + pipe_rx_4_sigs, + pipe_rx_5_sigs, + pipe_rx_6_sigs, + pipe_rx_7_sigs, + common_commands_out, + pipe_tx_0_sigs, + pipe_tx_1_sigs, + pipe_tx_2_sigs, + pipe_tx_3_sigs, + pipe_tx_4_sigs, + pipe_tx_5_sigs, + pipe_tx_6_sigs, + pipe_tx_7_sigs, + pipe_mmcm_rst_n, + sys_clk, + sys_rst_n); + output [3:0]pci_exp_txn; + output [3:0]pci_exp_txp; + input [3:0]pci_exp_rxn; + input [3:0]pci_exp_rxp; + output int_pclk_out_slave; + output int_pipe_rxusrclk_out; + output [3:0]int_rxoutclk_out; + output int_dclk_out; + output int_userclk1_out; + output int_userclk2_out; + output int_oobclk_out; + output int_mmcm_lock_out; + output [1:0]int_qplllock_out; + output [1:0]int_qplloutclk_out; + output [1:0]int_qplloutrefclk_out; + input [3:0]int_pclk_sel_slave; + input pipe_pclk_in; + input pipe_rxusrclk_in; + input [3:0]pipe_rxoutclk_in; + input pipe_dclk_in; + input pipe_userclk1_in; + input pipe_userclk2_in; + input pipe_oobclk_in; + input pipe_mmcm_lock_in; + output pipe_txoutclk_out; + output [3:0]pipe_rxoutclk_out; + output [3:0]pipe_pclk_sel_out; + output pipe_gen3_out; + input [11:0]qpll_drp_crscode; + input [17:0]qpll_drp_fsm; + input [1:0]qpll_drp_done; + input [1:0]qpll_drp_reset; + input [1:0]qpll_qplllock; + input [1:0]qpll_qplloutclk; + input [1:0]qpll_qplloutrefclk; + output qpll_qplld; + output [1:0]qpll_qpllreset; + output qpll_drp_clk; + output qpll_drp_rst_n; + output qpll_drp_ovrd; + output qpll_drp_gen3; + output qpll_drp_start; + output user_clk_out; + output user_reset_out; + output user_lnk_up; + output user_app_rdy; + output [5:0]tx_buf_av; + output tx_err_drop; + output tx_cfg_req; + input [63:0]s_axis_tx_tdata; + input s_axis_tx_tvalid; + output s_axis_tx_tready; + input [7:0]s_axis_tx_tkeep; + input s_axis_tx_tlast; + input [3:0]s_axis_tx_tuser; + input tx_cfg_gnt; + output [63:0]m_axis_rx_tdata; + output m_axis_rx_tvalid; + input m_axis_rx_tready; + output [7:0]m_axis_rx_tkeep; + output m_axis_rx_tlast; + output [21:0]m_axis_rx_tuser; + input rx_np_ok; + input rx_np_req; + output [11:0]fc_cpld; + output [7:0]fc_cplh; + output [11:0]fc_npd; + output [7:0]fc_nph; + output [11:0]fc_pd; + output [7:0]fc_ph; + input [2:0]fc_sel; + output [31:0]cfg_mgmt_do; + output cfg_mgmt_rd_wr_done; + output [15:0]cfg_status; + output [15:0]cfg_command; + output [15:0]cfg_dstatus; + output [15:0]cfg_dcommand; + output [15:0]cfg_lstatus; + output [15:0]cfg_lcommand; + output [15:0]cfg_dcommand2; + output [2:0]cfg_pcie_link_state; + output cfg_pmcsr_pme_en; + output [1:0]cfg_pmcsr_powerstate; + output cfg_pmcsr_pme_status; + output cfg_received_func_lvl_rst; + input [31:0]cfg_mgmt_di; + input [3:0]cfg_mgmt_byte_en; + input [9:0]cfg_mgmt_dwaddr; + input cfg_mgmt_wr_en; + input cfg_mgmt_rd_en; + input cfg_mgmt_wr_readonly; + input cfg_err_ecrc; + input cfg_err_ur; + input cfg_err_cpl_timeout; + input cfg_err_cpl_unexpect; + input cfg_err_cpl_abort; + input cfg_err_posted; + input cfg_err_cor; + input cfg_err_atomic_egress_blocked; + input cfg_err_internal_cor; + input cfg_err_malformed; + input cfg_err_mc_blocked; + input cfg_err_poisoned; + input cfg_err_norecovery; + input [47:0]cfg_err_tlp_cpl_header; + output cfg_err_cpl_rdy; + input cfg_err_locked; + input cfg_err_acs; + input cfg_err_internal_uncor; + input cfg_trn_pending; + input cfg_pm_halt_aspm_l0s; + input cfg_pm_halt_aspm_l1; + input cfg_pm_force_state_en; + input [1:0]cfg_pm_force_state; + input [63:0]cfg_dsn; + output cfg_msg_received; + output [15:0]cfg_msg_data; + input cfg_interrupt; + output cfg_interrupt_rdy; + input cfg_interrupt_assert; + input [7:0]cfg_interrupt_di; + output [7:0]cfg_interrupt_do; + output [2:0]cfg_interrupt_mmenable; + output cfg_interrupt_msienable; + output cfg_interrupt_msixenable; + output cfg_interrupt_msixfm; + input cfg_interrupt_stat; + input [4:0]cfg_pciecap_interrupt_msgnum; + output cfg_to_turnoff; + input cfg_turnoff_ok; + output [7:0]cfg_bus_number; + output [4:0]cfg_device_number; + output [2:0]cfg_function_number; + input cfg_pm_wake; + output cfg_msg_received_pm_as_nak; + output cfg_msg_received_setslotpowerlimit; + input cfg_pm_send_pme_to; + input [7:0]cfg_ds_bus_number; + input [4:0]cfg_ds_device_number; + input [2:0]cfg_ds_function_number; + input cfg_mgmt_wr_rw1c_as_rw; + output cfg_bridge_serr_en; + output cfg_slot_control_electromech_il_ctl_pulse; + output cfg_root_control_syserr_corr_err_en; + output cfg_root_control_syserr_non_fatal_err_en; + output cfg_root_control_syserr_fatal_err_en; + output cfg_root_control_pme_int_en; + output cfg_aer_rooterr_corr_err_reporting_en; + output cfg_aer_rooterr_non_fatal_err_reporting_en; + output cfg_aer_rooterr_fatal_err_reporting_en; + output cfg_aer_rooterr_corr_err_received; + output cfg_aer_rooterr_non_fatal_err_received; + output cfg_aer_rooterr_fatal_err_received; + output cfg_msg_received_err_cor; + output cfg_msg_received_err_non_fatal; + output cfg_msg_received_err_fatal; + output cfg_msg_received_pm_pme; + output cfg_msg_received_pme_to_ack; + output cfg_msg_received_assert_int_a; + output cfg_msg_received_assert_int_b; + output cfg_msg_received_assert_int_c; + output cfg_msg_received_assert_int_d; + output cfg_msg_received_deassert_int_a; + output cfg_msg_received_deassert_int_b; + output cfg_msg_received_deassert_int_c; + output cfg_msg_received_deassert_int_d; + input [1:0]pl_directed_link_change; + input [1:0]pl_directed_link_width; + input pl_directed_link_speed; + input pl_directed_link_auton; + input pl_upstream_prefer_deemph; + output pl_sel_lnk_rate; + output [1:0]pl_sel_lnk_width; + output [5:0]pl_ltssm_state; + output [1:0]pl_lane_reversal_mode; + output pl_phy_lnk_up; + output [2:0]pl_tx_pm_state; + output [1:0]pl_rx_pm_state; + output pl_link_upcfg_cap; + output pl_link_gen2_cap; + output pl_link_partner_gen2_supported; + output [2:0]pl_initial_link_width; + output pl_directed_change_done; + output pl_received_hot_rst; + input pl_transmit_hot_rst; + input pl_downstream_deemph_source; + input [127:0]cfg_err_aer_headerlog; + input [4:0]cfg_aer_interrupt_msgnum; + output cfg_err_aer_headerlog_set; + output cfg_aer_ecrc_check_en; + output cfg_aer_ecrc_gen_en; + output [6:0]cfg_vc_tcvc_map; + input pcie_drp_clk; + input pcie_drp_en; + input pcie_drp_we; + input [8:0]pcie_drp_addr; + input [15:0]pcie_drp_di; + output pcie_drp_rdy; + output [15:0]pcie_drp_do; + input startup_eos_in; + output startup_cfgclk; + output startup_cfgmclk; + output startup_eos; + output startup_preq; + input startup_clk; + input startup_gsr; + input startup_gts; + input startup_keyclearb; + input startup_pack; + input startup_usrcclko; + input startup_usrcclkts; + input startup_usrdoneo; + input startup_usrdonets; + input icap_clk; + input icap_csib; + input icap_rdwrb; + input [31:0]icap_i; + output [31:0]icap_o; + input [2:0]pipe_txprbssel; + input [2:0]pipe_rxprbssel; + input pipe_txprbsforceerr; + input pipe_rxprbscntreset; + input [2:0]pipe_loopback; + output [3:0]pipe_rxprbserr; + input [3:0]pipe_txinhibit; + output [4:0]pipe_rst_fsm; + output [11:0]pipe_qrst_fsm; + output [19:0]pipe_rate_fsm; + output [23:0]pipe_sync_fsm_tx; + output [27:0]pipe_sync_fsm_rx; + output [27:0]pipe_drp_fsm; + output pipe_rst_idle; + output pipe_qrst_idle; + output pipe_rate_idle; + output [3:0]pipe_eyescandataerror; + output [11:0]pipe_rxstatus; + output [59:0]pipe_dmonitorout; + output [3:0]pipe_cpll_lock; + output [0:0]pipe_qpll_lock; + output [3:0]pipe_rxpmaresetdone; + output [11:0]pipe_rxbufstatus; + output [3:0]pipe_txphaligndone; + output [3:0]pipe_txphinitdone; + output [3:0]pipe_txdlysresetdone; + output [3:0]pipe_rxphaligndone; + output [3:0]pipe_rxdlysresetdone; + output [3:0]pipe_rxsyncdone; + output [31:0]pipe_rxdisperr; + output [31:0]pipe_rxnotintable; + output [3:0]pipe_rxcommadet; + output [3:0]gt_ch_drp_rdy; + output [3:0]pipe_debug_0; + output [3:0]pipe_debug_1; + output [3:0]pipe_debug_2; + output [3:0]pipe_debug_3; + output [3:0]pipe_debug_4; + output [3:0]pipe_debug_5; + output [3:0]pipe_debug_6; + output [3:0]pipe_debug_7; + output [3:0]pipe_debug_8; + output [3:0]pipe_debug_9; + output [31:0]pipe_debug; + output ext_ch_gt_drpclk; + input [35:0]ext_ch_gt_drpaddr; + input [3:0]ext_ch_gt_drpen; + input [63:0]ext_ch_gt_drpdi; + input [3:0]ext_ch_gt_drpwe; + output [63:0]ext_ch_gt_drpdo; + output [3:0]ext_ch_gt_drprdy; + input [11:0]common_commands_in; + input [24:0]pipe_rx_0_sigs; + input [24:0]pipe_rx_1_sigs; + input [24:0]pipe_rx_2_sigs; + input [24:0]pipe_rx_3_sigs; + input [24:0]pipe_rx_4_sigs; + input [24:0]pipe_rx_5_sigs; + input [24:0]pipe_rx_6_sigs; + input [24:0]pipe_rx_7_sigs; + output [11:0]common_commands_out; + output [24:0]pipe_tx_0_sigs; + output [24:0]pipe_tx_1_sigs; + output [24:0]pipe_tx_2_sigs; + output [24:0]pipe_tx_3_sigs; + output [24:0]pipe_tx_4_sigs; + output [24:0]pipe_tx_5_sigs; + output [24:0]pipe_tx_6_sigs; + output [24:0]pipe_tx_7_sigs; + input pipe_mmcm_rst_n; + input sys_clk; + input sys_rst_n; + + wire \ ; + wire cfg_aer_ecrc_check_en; + wire cfg_aer_ecrc_gen_en; + wire [4:0]cfg_aer_interrupt_msgnum; + wire cfg_aer_rooterr_corr_err_received; + wire cfg_aer_rooterr_corr_err_reporting_en; + wire cfg_aer_rooterr_fatal_err_received; + wire cfg_aer_rooterr_fatal_err_reporting_en; + wire cfg_aer_rooterr_non_fatal_err_received; + wire cfg_aer_rooterr_non_fatal_err_reporting_en; + wire cfg_bridge_serr_en; + wire [7:0]cfg_bus_number; + wire [10:0]\^cfg_command ; + wire [14:0]\^cfg_dcommand ; + wire [11:0]\^cfg_dcommand2 ; + wire [4:0]cfg_device_number; + wire [7:0]cfg_ds_bus_number; + wire [4:0]cfg_ds_device_number; + wire [2:0]cfg_ds_function_number; + wire [63:0]cfg_dsn; + wire [3:0]\^cfg_dstatus ; + wire [127:0]cfg_err_aer_headerlog; + wire cfg_err_aer_headerlog_set; + wire cfg_err_atomic_egress_blocked; + wire cfg_err_cor; + wire cfg_err_cpl_abort; + wire cfg_err_cpl_rdy; + wire cfg_err_cpl_timeout; + wire cfg_err_cpl_unexpect; + wire cfg_err_ecrc; + wire cfg_err_internal_cor; + wire cfg_err_internal_uncor; + wire cfg_err_locked; + wire cfg_err_malformed; + wire cfg_err_mc_blocked; + wire cfg_err_norecovery; + wire cfg_err_poisoned; + wire cfg_err_posted; + wire [47:0]cfg_err_tlp_cpl_header; + wire cfg_err_ur; + wire [2:0]cfg_function_number; + wire cfg_interrupt; + wire cfg_interrupt_assert; + wire [7:0]cfg_interrupt_di; + wire [7:0]cfg_interrupt_do; + wire [2:0]cfg_interrupt_mmenable; + wire cfg_interrupt_msienable; + wire cfg_interrupt_msixenable; + wire cfg_interrupt_msixfm; + wire cfg_interrupt_rdy; + wire cfg_interrupt_stat; + wire [11:0]\^cfg_lcommand ; + wire [15:0]\^cfg_lstatus ; + wire [3:0]cfg_mgmt_byte_en; + wire [31:0]cfg_mgmt_di; + wire [31:0]cfg_mgmt_do; + wire [9:0]cfg_mgmt_dwaddr; + wire cfg_mgmt_rd_en; + wire cfg_mgmt_rd_wr_done; + wire cfg_mgmt_wr_en; + wire cfg_mgmt_wr_readonly; + wire cfg_mgmt_wr_rw1c_as_rw; + wire [15:0]cfg_msg_data; + wire cfg_msg_received; + wire cfg_msg_received_assert_int_a; + wire cfg_msg_received_assert_int_b; + wire cfg_msg_received_assert_int_c; + wire cfg_msg_received_assert_int_d; + wire cfg_msg_received_deassert_int_a; + wire cfg_msg_received_deassert_int_b; + wire cfg_msg_received_deassert_int_c; + wire cfg_msg_received_deassert_int_d; + wire cfg_msg_received_err_cor; + wire cfg_msg_received_err_fatal; + wire cfg_msg_received_err_non_fatal; + wire cfg_msg_received_pm_as_nak; + wire cfg_msg_received_pm_pme; + wire cfg_msg_received_pme_to_ack; + wire cfg_msg_received_setslotpowerlimit; + wire [2:0]cfg_pcie_link_state; + wire [4:0]cfg_pciecap_interrupt_msgnum; + wire [1:0]cfg_pm_force_state; + wire cfg_pm_force_state_en; + wire cfg_pm_halt_aspm_l0s; + wire cfg_pm_halt_aspm_l1; + wire cfg_pm_wake; + wire cfg_pmcsr_pme_en; + wire cfg_pmcsr_pme_status; + wire [1:0]cfg_pmcsr_powerstate; + wire cfg_received_func_lvl_rst; + wire cfg_root_control_pme_int_en; + wire cfg_root_control_syserr_corr_err_en; + wire cfg_root_control_syserr_fatal_err_en; + wire cfg_root_control_syserr_non_fatal_err_en; + wire cfg_slot_control_electromech_il_ctl_pulse; + wire cfg_to_turnoff; + wire cfg_trn_pending; + wire cfg_turnoff_ok; + wire [6:0]cfg_vc_tcvc_map; + wire [11:0]fc_cpld; + wire [7:0]fc_cplh; + wire [11:0]fc_npd; + wire [7:0]fc_nph; + wire [11:0]fc_pd; + wire [7:0]fc_ph; + wire [2:0]fc_sel; + wire [63:0]m_axis_rx_tdata; + wire [6:6]\^m_axis_rx_tkeep ; + wire m_axis_rx_tlast; + wire m_axis_rx_tready; + wire [21:0]\^m_axis_rx_tuser ; + wire m_axis_rx_tvalid; + wire [3:0]pci_exp_rxn; + wire [3:0]pci_exp_rxp; + wire [3:0]pci_exp_txn; + wire [3:0]pci_exp_txp; + wire [8:0]pcie_drp_addr; + wire pcie_drp_clk; + wire [15:0]pcie_drp_di; + wire [15:0]pcie_drp_do; + wire pcie_drp_en; + wire pcie_drp_rdy; + wire pcie_drp_we; + wire pipe_dclk_in; + wire pipe_gen3_out; + wire pipe_mmcm_lock_in; + wire pipe_oobclk_in; + wire pipe_pclk_in; + wire [3:0]pipe_pclk_sel_out; + wire [3:0]pipe_rxoutclk_out; + wire pipe_rxusrclk_in; + wire pipe_txoutclk_out; + wire pipe_userclk1_in; + wire pipe_userclk2_in; + wire pl_directed_change_done; + wire pl_directed_link_auton; + wire [1:0]pl_directed_link_change; + wire pl_directed_link_speed; + wire [1:0]pl_directed_link_width; + wire pl_downstream_deemph_source; + wire [2:0]pl_initial_link_width; + wire [1:0]pl_lane_reversal_mode; + wire pl_link_gen2_cap; + wire pl_link_partner_gen2_supported; + wire pl_link_upcfg_cap; + wire [5:0]pl_ltssm_state; + wire pl_phy_lnk_up; + wire pl_received_hot_rst; + wire [1:0]pl_rx_pm_state; + wire pl_sel_lnk_rate; + wire [1:0]pl_sel_lnk_width; + wire pl_transmit_hot_rst; + wire [2:0]pl_tx_pm_state; + wire pl_upstream_prefer_deemph; + wire rx_np_ok; + wire rx_np_req; + wire [63:0]s_axis_tx_tdata; + wire [7:0]s_axis_tx_tkeep; + wire s_axis_tx_tlast; + wire s_axis_tx_tready; + wire [3:0]s_axis_tx_tuser; + wire s_axis_tx_tvalid; + wire sys_clk; + wire sys_rst_n; + wire [5:0]tx_buf_av; + wire tx_cfg_gnt; + wire tx_cfg_req; + wire tx_err_drop; + wire user_lnk_up; + wire user_reset_out; + + assign cfg_command[15] = \ ; + assign cfg_command[14] = \ ; + assign cfg_command[13] = \ ; + assign cfg_command[12] = \ ; + assign cfg_command[11] = \ ; + assign cfg_command[10] = \^cfg_command [10]; + assign cfg_command[9] = \ ; + assign cfg_command[8] = \^cfg_command [8]; + assign cfg_command[7] = \ ; + assign cfg_command[6] = \ ; + assign cfg_command[5] = \ ; + assign cfg_command[4] = \ ; + assign cfg_command[3] = \ ; + assign cfg_command[2:0] = \^cfg_command [2:0]; + assign cfg_dcommand[15] = \ ; + assign cfg_dcommand[14:0] = \^cfg_dcommand [14:0]; + assign cfg_dcommand2[15] = \ ; + assign cfg_dcommand2[14] = \ ; + assign cfg_dcommand2[13] = \ ; + assign cfg_dcommand2[12] = \ ; + assign cfg_dcommand2[11:0] = \^cfg_dcommand2 [11:0]; + assign cfg_dstatus[15] = \ ; + assign cfg_dstatus[14] = \ ; + assign cfg_dstatus[13] = \ ; + assign cfg_dstatus[12] = \ ; + assign cfg_dstatus[11] = \ ; + assign cfg_dstatus[10] = \ ; + assign cfg_dstatus[9] = \ ; + assign cfg_dstatus[8] = \ ; + assign cfg_dstatus[7] = \ ; + assign cfg_dstatus[6] = \ ; + assign cfg_dstatus[5] = cfg_trn_pending; + assign cfg_dstatus[4] = \ ; + assign cfg_dstatus[3:0] = \^cfg_dstatus [3:0]; + assign cfg_lcommand[15] = \ ; + assign cfg_lcommand[14] = \ ; + assign cfg_lcommand[13] = \ ; + assign cfg_lcommand[12] = \ ; + assign cfg_lcommand[11:3] = \^cfg_lcommand [11:3]; + assign cfg_lcommand[2] = \ ; + assign cfg_lcommand[1:0] = \^cfg_lcommand [1:0]; + assign cfg_lstatus[15:13] = \^cfg_lstatus [15:13]; + assign cfg_lstatus[12] = \ ; + assign cfg_lstatus[11] = \^cfg_lstatus [11]; + assign cfg_lstatus[10] = \ ; + assign cfg_lstatus[9] = \ ; + assign cfg_lstatus[8] = \ ; + assign cfg_lstatus[7:4] = \^cfg_lstatus [7:4]; + assign cfg_lstatus[3] = \ ; + assign cfg_lstatus[2] = \ ; + assign cfg_lstatus[1:0] = \^cfg_lstatus [1:0]; + assign cfg_status[15] = \ ; + assign cfg_status[14] = \ ; + assign cfg_status[13] = \ ; + assign cfg_status[12] = \ ; + assign cfg_status[11] = \ ; + assign cfg_status[10] = \ ; + assign cfg_status[9] = \ ; + assign cfg_status[8] = \ ; + assign cfg_status[7] = \ ; + assign cfg_status[6] = \ ; + assign cfg_status[5] = \ ; + assign cfg_status[4] = \ ; + assign cfg_status[3] = \ ; + assign cfg_status[2] = \ ; + assign cfg_status[1] = \ ; + assign cfg_status[0] = \ ; + assign common_commands_out[11] = \ ; + assign common_commands_out[10] = \ ; + assign common_commands_out[9] = \ ; + assign common_commands_out[8] = \ ; + assign common_commands_out[7] = \ ; + assign common_commands_out[6] = \ ; + assign common_commands_out[5] = \ ; + assign common_commands_out[4] = \ ; + assign common_commands_out[3] = \ ; + assign common_commands_out[2] = \ ; + assign common_commands_out[1] = \ ; + assign common_commands_out[0] = \ ; + assign ext_ch_gt_drpclk = \ ; + assign ext_ch_gt_drpdo[63] = \ ; + assign ext_ch_gt_drpdo[62] = \ ; + assign ext_ch_gt_drpdo[61] = \ ; + assign ext_ch_gt_drpdo[60] = \ ; + assign ext_ch_gt_drpdo[59] = \ ; + assign ext_ch_gt_drpdo[58] = \ ; + assign ext_ch_gt_drpdo[57] = \ ; + assign ext_ch_gt_drpdo[56] = \ ; + assign ext_ch_gt_drpdo[55] = \ ; + assign ext_ch_gt_drpdo[54] = \ ; + assign ext_ch_gt_drpdo[53] = \ ; + assign ext_ch_gt_drpdo[52] = \ ; + assign ext_ch_gt_drpdo[51] = \ ; + assign ext_ch_gt_drpdo[50] = \ ; + assign ext_ch_gt_drpdo[49] = \ ; + assign ext_ch_gt_drpdo[48] = \ ; + assign ext_ch_gt_drpdo[47] = \ ; + assign ext_ch_gt_drpdo[46] = \ ; + assign ext_ch_gt_drpdo[45] = \ ; + assign ext_ch_gt_drpdo[44] = \ ; + assign ext_ch_gt_drpdo[43] = \ ; + assign ext_ch_gt_drpdo[42] = \ ; + assign ext_ch_gt_drpdo[41] = \ ; + assign ext_ch_gt_drpdo[40] = \ ; + assign ext_ch_gt_drpdo[39] = \ ; + assign ext_ch_gt_drpdo[38] = \ ; + assign ext_ch_gt_drpdo[37] = \ ; + assign ext_ch_gt_drpdo[36] = \ ; + assign ext_ch_gt_drpdo[35] = \ ; + assign ext_ch_gt_drpdo[34] = \ ; + assign ext_ch_gt_drpdo[33] = \ ; + assign ext_ch_gt_drpdo[32] = \ ; + assign ext_ch_gt_drpdo[31] = \ ; + assign ext_ch_gt_drpdo[30] = \ ; + assign ext_ch_gt_drpdo[29] = \ ; + assign ext_ch_gt_drpdo[28] = \ ; + assign ext_ch_gt_drpdo[27] = \ ; + assign ext_ch_gt_drpdo[26] = \ ; + assign ext_ch_gt_drpdo[25] = \ ; + assign ext_ch_gt_drpdo[24] = \ ; + assign ext_ch_gt_drpdo[23] = \ ; + assign ext_ch_gt_drpdo[22] = \ ; + assign ext_ch_gt_drpdo[21] = \ ; + assign ext_ch_gt_drpdo[20] = \ ; + assign ext_ch_gt_drpdo[19] = \ ; + assign ext_ch_gt_drpdo[18] = \ ; + assign ext_ch_gt_drpdo[17] = \ ; + assign ext_ch_gt_drpdo[16] = \ ; + assign ext_ch_gt_drpdo[15] = \ ; + assign ext_ch_gt_drpdo[14] = \ ; + assign ext_ch_gt_drpdo[13] = \ ; + assign ext_ch_gt_drpdo[12] = \ ; + assign ext_ch_gt_drpdo[11] = \ ; + assign ext_ch_gt_drpdo[10] = \ ; + assign ext_ch_gt_drpdo[9] = \ ; + assign ext_ch_gt_drpdo[8] = \ ; + assign ext_ch_gt_drpdo[7] = \ ; + assign ext_ch_gt_drpdo[6] = \ ; + assign ext_ch_gt_drpdo[5] = \ ; + assign ext_ch_gt_drpdo[4] = \ ; + assign ext_ch_gt_drpdo[3] = \ ; + assign ext_ch_gt_drpdo[2] = \ ; + assign ext_ch_gt_drpdo[1] = \ ; + assign ext_ch_gt_drpdo[0] = \ ; + assign ext_ch_gt_drprdy[3] = \ ; + assign ext_ch_gt_drprdy[2] = \ ; + assign ext_ch_gt_drprdy[1] = \ ; + assign ext_ch_gt_drprdy[0] = \ ; + assign gt_ch_drp_rdy[3] = \ ; + assign gt_ch_drp_rdy[2] = \ ; + assign gt_ch_drp_rdy[1] = \ ; + assign gt_ch_drp_rdy[0] = \ ; + assign icap_o[31] = \ ; + assign icap_o[30] = \ ; + assign icap_o[29] = \ ; + assign icap_o[28] = \ ; + assign icap_o[27] = \ ; + assign icap_o[26] = \ ; + assign icap_o[25] = \ ; + assign icap_o[24] = \ ; + assign icap_o[23] = \ ; + assign icap_o[22] = \ ; + assign icap_o[21] = \ ; + assign icap_o[20] = \ ; + assign icap_o[19] = \ ; + assign icap_o[18] = \ ; + assign icap_o[17] = \ ; + assign icap_o[16] = \ ; + assign icap_o[15] = \ ; + assign icap_o[14] = \ ; + assign icap_o[13] = \ ; + assign icap_o[12] = \ ; + assign icap_o[11] = \ ; + assign icap_o[10] = \ ; + assign icap_o[9] = \ ; + assign icap_o[8] = \ ; + assign icap_o[7] = \ ; + assign icap_o[6] = \ ; + assign icap_o[5] = \ ; + assign icap_o[4] = \ ; + assign icap_o[3] = \ ; + assign icap_o[2] = \ ; + assign icap_o[1] = \ ; + assign icap_o[0] = \ ; + assign int_dclk_out = \ ; + assign int_mmcm_lock_out = \ ; + assign int_oobclk_out = \ ; + assign int_pclk_out_slave = \ ; + assign int_pipe_rxusrclk_out = \ ; + assign int_qplllock_out[1] = \ ; + assign int_qplllock_out[0] = \ ; + assign int_qplloutclk_out[1] = \ ; + assign int_qplloutclk_out[0] = \ ; + assign int_qplloutrefclk_out[1] = \ ; + assign int_qplloutrefclk_out[0] = \ ; + assign int_rxoutclk_out[3] = \ ; + assign int_rxoutclk_out[2] = \ ; + assign int_rxoutclk_out[1] = \ ; + assign int_rxoutclk_out[0] = \ ; + assign int_userclk1_out = \ ; + assign int_userclk2_out = \ ; + assign m_axis_rx_tkeep[7] = \^m_axis_rx_tkeep [6]; + assign m_axis_rx_tkeep[6] = \^m_axis_rx_tkeep [6]; + assign m_axis_rx_tkeep[5] = \^m_axis_rx_tkeep [6]; + assign m_axis_rx_tkeep[4] = \^m_axis_rx_tkeep [6]; + assign m_axis_rx_tkeep[3] = \ ; + assign m_axis_rx_tkeep[2] = \ ; + assign m_axis_rx_tkeep[1] = \ ; + assign m_axis_rx_tkeep[0] = \ ; + assign m_axis_rx_tuser[21] = \^m_axis_rx_tuser [21]; + assign m_axis_rx_tuser[20] = \ ; + assign m_axis_rx_tuser[19] = \^m_axis_rx_tuser [19]; + assign m_axis_rx_tuser[18] = \^m_axis_rx_tuser [17]; + assign m_axis_rx_tuser[17] = \^m_axis_rx_tuser [17]; + assign m_axis_rx_tuser[16] = \ ; + assign m_axis_rx_tuser[15] = \ ; + assign m_axis_rx_tuser[14] = \^m_axis_rx_tuser [14]; + assign m_axis_rx_tuser[13] = \ ; + assign m_axis_rx_tuser[12] = \ ; + assign m_axis_rx_tuser[11] = \ ; + assign m_axis_rx_tuser[10] = \ ; + assign m_axis_rx_tuser[9] = \ ; + assign m_axis_rx_tuser[8:0] = \^m_axis_rx_tuser [8:0]; + assign pipe_cpll_lock[3] = \ ; + assign pipe_cpll_lock[2] = \ ; + assign pipe_cpll_lock[1] = \ ; + assign pipe_cpll_lock[0] = \ ; + assign pipe_debug[31] = \ ; + assign pipe_debug[30] = \ ; + assign pipe_debug[29] = \ ; + assign pipe_debug[28] = \ ; + assign pipe_debug[27] = \ ; + assign pipe_debug[26] = \ ; + assign pipe_debug[25] = \ ; + assign pipe_debug[24] = \ ; + assign pipe_debug[23] = \ ; + assign pipe_debug[22] = \ ; + assign pipe_debug[21] = \ ; + assign pipe_debug[20] = \ ; + assign pipe_debug[19] = \ ; + assign pipe_debug[18] = \ ; + assign pipe_debug[17] = \ ; + assign pipe_debug[16] = \ ; + assign pipe_debug[15] = \ ; + assign pipe_debug[14] = \ ; + assign pipe_debug[13] = \ ; + assign pipe_debug[12] = \ ; + assign pipe_debug[11] = \ ; + assign pipe_debug[10] = \ ; + assign pipe_debug[9] = \ ; + assign pipe_debug[8] = \ ; + assign pipe_debug[7] = \ ; + assign pipe_debug[6] = \ ; + assign pipe_debug[5] = \ ; + assign pipe_debug[4] = \ ; + assign pipe_debug[3] = \ ; + assign pipe_debug[2] = \ ; + assign pipe_debug[1] = \ ; + assign pipe_debug[0] = \ ; + assign pipe_debug_0[3] = \ ; + assign pipe_debug_0[2] = \ ; + assign pipe_debug_0[1] = \ ; + assign pipe_debug_0[0] = \ ; + assign pipe_debug_1[3] = \ ; + assign pipe_debug_1[2] = \ ; + assign pipe_debug_1[1] = \ ; + assign pipe_debug_1[0] = \ ; + assign pipe_debug_2[3] = \ ; + assign pipe_debug_2[2] = \ ; + assign pipe_debug_2[1] = \ ; + assign pipe_debug_2[0] = \ ; + assign pipe_debug_3[3] = \ ; + assign pipe_debug_3[2] = \ ; + assign pipe_debug_3[1] = \ ; + assign pipe_debug_3[0] = \ ; + assign pipe_debug_4[3] = \ ; + assign pipe_debug_4[2] = \ ; + assign pipe_debug_4[1] = \ ; + assign pipe_debug_4[0] = \ ; + assign pipe_debug_5[3] = \ ; + assign pipe_debug_5[2] = \ ; + assign pipe_debug_5[1] = \ ; + assign pipe_debug_5[0] = \ ; + assign pipe_debug_6[3] = \ ; + assign pipe_debug_6[2] = \ ; + assign pipe_debug_6[1] = \ ; + assign pipe_debug_6[0] = \ ; + assign pipe_debug_7[3] = \ ; + assign pipe_debug_7[2] = \ ; + assign pipe_debug_7[1] = \ ; + assign pipe_debug_7[0] = \ ; + assign pipe_debug_8[3] = \ ; + assign pipe_debug_8[2] = \ ; + assign pipe_debug_8[1] = \ ; + assign pipe_debug_8[0] = \ ; + assign pipe_debug_9[3] = \ ; + assign pipe_debug_9[2] = \ ; + assign pipe_debug_9[1] = \ ; + assign pipe_debug_9[0] = \ ; + assign pipe_dmonitorout[59] = \ ; + assign pipe_dmonitorout[58] = \ ; + assign pipe_dmonitorout[57] = \ ; + assign pipe_dmonitorout[56] = \ ; + assign pipe_dmonitorout[55] = \ ; + assign pipe_dmonitorout[54] = \ ; + assign pipe_dmonitorout[53] = \ ; + assign pipe_dmonitorout[52] = \ ; + assign pipe_dmonitorout[51] = \ ; + assign pipe_dmonitorout[50] = \ ; + assign pipe_dmonitorout[49] = \ ; + assign pipe_dmonitorout[48] = \ ; + assign pipe_dmonitorout[47] = \ ; + assign pipe_dmonitorout[46] = \ ; + assign pipe_dmonitorout[45] = \ ; + assign pipe_dmonitorout[44] = \ ; + assign pipe_dmonitorout[43] = \ ; + assign pipe_dmonitorout[42] = \ ; + assign pipe_dmonitorout[41] = \ ; + assign pipe_dmonitorout[40] = \ ; + assign pipe_dmonitorout[39] = \ ; + assign pipe_dmonitorout[38] = \ ; + assign pipe_dmonitorout[37] = \ ; + assign pipe_dmonitorout[36] = \ ; + assign pipe_dmonitorout[35] = \ ; + assign pipe_dmonitorout[34] = \ ; + assign pipe_dmonitorout[33] = \ ; + assign pipe_dmonitorout[32] = \ ; + assign pipe_dmonitorout[31] = \ ; + assign pipe_dmonitorout[30] = \ ; + assign pipe_dmonitorout[29] = \ ; + assign pipe_dmonitorout[28] = \ ; + assign pipe_dmonitorout[27] = \ ; + assign pipe_dmonitorout[26] = \ ; + assign pipe_dmonitorout[25] = \ ; + assign pipe_dmonitorout[24] = \ ; + assign pipe_dmonitorout[23] = \ ; + assign pipe_dmonitorout[22] = \ ; + assign pipe_dmonitorout[21] = \ ; + assign pipe_dmonitorout[20] = \ ; + assign pipe_dmonitorout[19] = \ ; + assign pipe_dmonitorout[18] = \ ; + assign pipe_dmonitorout[17] = \ ; + assign pipe_dmonitorout[16] = \ ; + assign pipe_dmonitorout[15] = \ ; + assign pipe_dmonitorout[14] = \ ; + assign pipe_dmonitorout[13] = \ ; + assign pipe_dmonitorout[12] = \ ; + assign pipe_dmonitorout[11] = \ ; + assign pipe_dmonitorout[10] = \ ; + assign pipe_dmonitorout[9] = \ ; + assign pipe_dmonitorout[8] = \ ; + assign pipe_dmonitorout[7] = \ ; + assign pipe_dmonitorout[6] = \ ; + assign pipe_dmonitorout[5] = \ ; + assign pipe_dmonitorout[4] = \ ; + assign pipe_dmonitorout[3] = \ ; + assign pipe_dmonitorout[2] = \ ; + assign pipe_dmonitorout[1] = \ ; + assign pipe_dmonitorout[0] = \ ; + assign pipe_drp_fsm[27] = \ ; + assign pipe_drp_fsm[26] = \ ; + assign pipe_drp_fsm[25] = \ ; + assign pipe_drp_fsm[24] = \ ; + assign pipe_drp_fsm[23] = \ ; + assign pipe_drp_fsm[22] = \ ; + assign pipe_drp_fsm[21] = \ ; + assign pipe_drp_fsm[20] = \ ; + assign pipe_drp_fsm[19] = \ ; + assign pipe_drp_fsm[18] = \ ; + assign pipe_drp_fsm[17] = \ ; + assign pipe_drp_fsm[16] = \ ; + assign pipe_drp_fsm[15] = \ ; + assign pipe_drp_fsm[14] = \ ; + assign pipe_drp_fsm[13] = \ ; + assign pipe_drp_fsm[12] = \ ; + assign pipe_drp_fsm[11] = \ ; + assign pipe_drp_fsm[10] = \ ; + assign pipe_drp_fsm[9] = \ ; + assign pipe_drp_fsm[8] = \ ; + assign pipe_drp_fsm[7] = \ ; + assign pipe_drp_fsm[6] = \ ; + assign pipe_drp_fsm[5] = \ ; + assign pipe_drp_fsm[4] = \ ; + assign pipe_drp_fsm[3] = \ ; + assign pipe_drp_fsm[2] = \ ; + assign pipe_drp_fsm[1] = \ ; + assign pipe_drp_fsm[0] = \ ; + assign pipe_eyescandataerror[3] = \ ; + assign pipe_eyescandataerror[2] = \ ; + assign pipe_eyescandataerror[1] = \ ; + assign pipe_eyescandataerror[0] = \ ; + assign pipe_qpll_lock[0] = \ ; + assign pipe_qrst_fsm[11] = \ ; + assign pipe_qrst_fsm[10] = \ ; + assign pipe_qrst_fsm[9] = \ ; + assign pipe_qrst_fsm[8] = \ ; + assign pipe_qrst_fsm[7] = \ ; + assign pipe_qrst_fsm[6] = \ ; + assign pipe_qrst_fsm[5] = \ ; + assign pipe_qrst_fsm[4] = \ ; + assign pipe_qrst_fsm[3] = \ ; + assign pipe_qrst_fsm[2] = \ ; + assign pipe_qrst_fsm[1] = \ ; + assign pipe_qrst_fsm[0] = \ ; + assign pipe_qrst_idle = \ ; + assign pipe_rate_fsm[19] = \ ; + assign pipe_rate_fsm[18] = \ ; + assign pipe_rate_fsm[17] = \ ; + assign pipe_rate_fsm[16] = \ ; + assign pipe_rate_fsm[15] = \ ; + assign pipe_rate_fsm[14] = \ ; + assign pipe_rate_fsm[13] = \ ; + assign pipe_rate_fsm[12] = \ ; + assign pipe_rate_fsm[11] = \ ; + assign pipe_rate_fsm[10] = \ ; + assign pipe_rate_fsm[9] = \ ; + assign pipe_rate_fsm[8] = \ ; + assign pipe_rate_fsm[7] = \ ; + assign pipe_rate_fsm[6] = \ ; + assign pipe_rate_fsm[5] = \ ; + assign pipe_rate_fsm[4] = \ ; + assign pipe_rate_fsm[3] = \ ; + assign pipe_rate_fsm[2] = \ ; + assign pipe_rate_fsm[1] = \ ; + assign pipe_rate_fsm[0] = \ ; + assign pipe_rate_idle = \ ; + assign pipe_rst_fsm[4] = \ ; + assign pipe_rst_fsm[3] = \ ; + assign pipe_rst_fsm[2] = \ ; + assign pipe_rst_fsm[1] = \ ; + assign pipe_rst_fsm[0] = \ ; + assign pipe_rst_idle = \ ; + assign pipe_rxbufstatus[11] = \ ; + assign pipe_rxbufstatus[10] = \ ; + assign pipe_rxbufstatus[9] = \ ; + assign pipe_rxbufstatus[8] = \ ; + assign pipe_rxbufstatus[7] = \ ; + assign pipe_rxbufstatus[6] = \ ; + assign pipe_rxbufstatus[5] = \ ; + assign pipe_rxbufstatus[4] = \ ; + assign pipe_rxbufstatus[3] = \ ; + assign pipe_rxbufstatus[2] = \ ; + assign pipe_rxbufstatus[1] = \ ; + assign pipe_rxbufstatus[0] = \ ; + assign pipe_rxcommadet[3] = \ ; + assign pipe_rxcommadet[2] = \ ; + assign pipe_rxcommadet[1] = \ ; + assign pipe_rxcommadet[0] = \ ; + assign pipe_rxdisperr[31] = \ ; + assign pipe_rxdisperr[30] = \ ; + assign pipe_rxdisperr[29] = \ ; + assign pipe_rxdisperr[28] = \ ; + assign pipe_rxdisperr[27] = \ ; + assign pipe_rxdisperr[26] = \ ; + assign pipe_rxdisperr[25] = \ ; + assign pipe_rxdisperr[24] = \ ; + assign pipe_rxdisperr[23] = \ ; + assign pipe_rxdisperr[22] = \ ; + assign pipe_rxdisperr[21] = \ ; + assign pipe_rxdisperr[20] = \ ; + assign pipe_rxdisperr[19] = \ ; + assign pipe_rxdisperr[18] = \ ; + assign pipe_rxdisperr[17] = \ ; + assign pipe_rxdisperr[16] = \ ; + assign pipe_rxdisperr[15] = \ ; + assign pipe_rxdisperr[14] = \ ; + assign pipe_rxdisperr[13] = \ ; + assign pipe_rxdisperr[12] = \ ; + assign pipe_rxdisperr[11] = \ ; + assign pipe_rxdisperr[10] = \ ; + assign pipe_rxdisperr[9] = \ ; + assign pipe_rxdisperr[8] = \ ; + assign pipe_rxdisperr[7] = \ ; + assign pipe_rxdisperr[6] = \ ; + assign pipe_rxdisperr[5] = \ ; + assign pipe_rxdisperr[4] = \ ; + assign pipe_rxdisperr[3] = \ ; + assign pipe_rxdisperr[2] = \ ; + assign pipe_rxdisperr[1] = \ ; + assign pipe_rxdisperr[0] = \ ; + assign pipe_rxdlysresetdone[3] = \ ; + assign pipe_rxdlysresetdone[2] = \ ; + assign pipe_rxdlysresetdone[1] = \ ; + assign pipe_rxdlysresetdone[0] = \ ; + assign pipe_rxnotintable[31] = \ ; + assign pipe_rxnotintable[30] = \ ; + assign pipe_rxnotintable[29] = \ ; + assign pipe_rxnotintable[28] = \ ; + assign pipe_rxnotintable[27] = \ ; + assign pipe_rxnotintable[26] = \ ; + assign pipe_rxnotintable[25] = \ ; + assign pipe_rxnotintable[24] = \ ; + assign pipe_rxnotintable[23] = \ ; + assign pipe_rxnotintable[22] = \ ; + assign pipe_rxnotintable[21] = \ ; + assign pipe_rxnotintable[20] = \ ; + assign pipe_rxnotintable[19] = \ ; + assign pipe_rxnotintable[18] = \ ; + assign pipe_rxnotintable[17] = \ ; + assign pipe_rxnotintable[16] = \ ; + assign pipe_rxnotintable[15] = \ ; + assign pipe_rxnotintable[14] = \ ; + assign pipe_rxnotintable[13] = \ ; + assign pipe_rxnotintable[12] = \ ; + assign pipe_rxnotintable[11] = \ ; + assign pipe_rxnotintable[10] = \ ; + assign pipe_rxnotintable[9] = \ ; + assign pipe_rxnotintable[8] = \ ; + assign pipe_rxnotintable[7] = \ ; + assign pipe_rxnotintable[6] = \ ; + assign pipe_rxnotintable[5] = \ ; + assign pipe_rxnotintable[4] = \ ; + assign pipe_rxnotintable[3] = \ ; + assign pipe_rxnotintable[2] = \ ; + assign pipe_rxnotintable[1] = \ ; + assign pipe_rxnotintable[0] = \ ; + assign pipe_rxphaligndone[3] = \ ; + assign pipe_rxphaligndone[2] = \ ; + assign pipe_rxphaligndone[1] = \ ; + assign pipe_rxphaligndone[0] = \ ; + assign pipe_rxpmaresetdone[3] = \ ; + assign pipe_rxpmaresetdone[2] = \ ; + assign pipe_rxpmaresetdone[1] = \ ; + assign pipe_rxpmaresetdone[0] = \ ; + assign pipe_rxprbserr[3] = \ ; + assign pipe_rxprbserr[2] = \ ; + assign pipe_rxprbserr[1] = \ ; + assign pipe_rxprbserr[0] = \ ; + assign pipe_rxstatus[11] = \ ; + assign pipe_rxstatus[10] = \ ; + assign pipe_rxstatus[9] = \ ; + assign pipe_rxstatus[8] = \ ; + assign pipe_rxstatus[7] = \ ; + assign pipe_rxstatus[6] = \ ; + assign pipe_rxstatus[5] = \ ; + assign pipe_rxstatus[4] = \ ; + assign pipe_rxstatus[3] = \ ; + assign pipe_rxstatus[2] = \ ; + assign pipe_rxstatus[1] = \ ; + assign pipe_rxstatus[0] = \ ; + assign pipe_rxsyncdone[3] = \ ; + assign pipe_rxsyncdone[2] = \ ; + assign pipe_rxsyncdone[1] = \ ; + assign pipe_rxsyncdone[0] = \ ; + assign pipe_sync_fsm_rx[27] = \ ; + assign pipe_sync_fsm_rx[26] = \ ; + assign pipe_sync_fsm_rx[25] = \ ; + assign pipe_sync_fsm_rx[24] = \ ; + assign pipe_sync_fsm_rx[23] = \ ; + assign pipe_sync_fsm_rx[22] = \ ; + assign pipe_sync_fsm_rx[21] = \ ; + assign pipe_sync_fsm_rx[20] = \ ; + assign pipe_sync_fsm_rx[19] = \ ; + assign pipe_sync_fsm_rx[18] = \ ; + assign pipe_sync_fsm_rx[17] = \ ; + assign pipe_sync_fsm_rx[16] = \ ; + assign pipe_sync_fsm_rx[15] = \ ; + assign pipe_sync_fsm_rx[14] = \ ; + assign pipe_sync_fsm_rx[13] = \ ; + assign pipe_sync_fsm_rx[12] = \ ; + assign pipe_sync_fsm_rx[11] = \ ; + assign pipe_sync_fsm_rx[10] = \ ; + assign pipe_sync_fsm_rx[9] = \ ; + assign pipe_sync_fsm_rx[8] = \ ; + assign pipe_sync_fsm_rx[7] = \ ; + assign pipe_sync_fsm_rx[6] = \ ; + assign pipe_sync_fsm_rx[5] = \ ; + assign pipe_sync_fsm_rx[4] = \ ; + assign pipe_sync_fsm_rx[3] = \ ; + assign pipe_sync_fsm_rx[2] = \ ; + assign pipe_sync_fsm_rx[1] = \ ; + assign pipe_sync_fsm_rx[0] = \ ; + assign pipe_sync_fsm_tx[23] = \ ; + assign pipe_sync_fsm_tx[22] = \ ; + assign pipe_sync_fsm_tx[21] = \ ; + assign pipe_sync_fsm_tx[20] = \ ; + assign pipe_sync_fsm_tx[19] = \ ; + assign pipe_sync_fsm_tx[18] = \ ; + assign pipe_sync_fsm_tx[17] = \ ; + assign pipe_sync_fsm_tx[16] = \ ; + assign pipe_sync_fsm_tx[15] = \ ; + assign pipe_sync_fsm_tx[14] = \ ; + assign pipe_sync_fsm_tx[13] = \ ; + assign pipe_sync_fsm_tx[12] = \ ; + assign pipe_sync_fsm_tx[11] = \ ; + assign pipe_sync_fsm_tx[10] = \ ; + assign pipe_sync_fsm_tx[9] = \ ; + assign pipe_sync_fsm_tx[8] = \ ; + assign pipe_sync_fsm_tx[7] = \ ; + assign pipe_sync_fsm_tx[6] = \ ; + assign pipe_sync_fsm_tx[5] = \ ; + assign pipe_sync_fsm_tx[4] = \ ; + assign pipe_sync_fsm_tx[3] = \ ; + assign pipe_sync_fsm_tx[2] = \ ; + assign pipe_sync_fsm_tx[1] = \ ; + assign pipe_sync_fsm_tx[0] = \ ; + assign pipe_tx_0_sigs[24] = \ ; + assign pipe_tx_0_sigs[23] = \ ; + assign pipe_tx_0_sigs[22] = \ ; + assign pipe_tx_0_sigs[21] = \ ; + assign pipe_tx_0_sigs[20] = \ ; + assign pipe_tx_0_sigs[19] = \ ; + assign pipe_tx_0_sigs[18] = \ ; + assign pipe_tx_0_sigs[17] = \ ; + assign pipe_tx_0_sigs[16] = \ ; + assign pipe_tx_0_sigs[15] = \ ; + assign pipe_tx_0_sigs[14] = \ ; + assign pipe_tx_0_sigs[13] = \ ; + assign pipe_tx_0_sigs[12] = \ ; + assign pipe_tx_0_sigs[11] = \ ; + assign pipe_tx_0_sigs[10] = \ ; + assign pipe_tx_0_sigs[9] = \ ; + assign pipe_tx_0_sigs[8] = \ ; + assign pipe_tx_0_sigs[7] = \ ; + assign pipe_tx_0_sigs[6] = \ ; + assign pipe_tx_0_sigs[5] = \ ; + assign pipe_tx_0_sigs[4] = \ ; + assign pipe_tx_0_sigs[3] = \ ; + assign pipe_tx_0_sigs[2] = \ ; + assign pipe_tx_0_sigs[1] = \ ; + assign pipe_tx_0_sigs[0] = \ ; + assign pipe_tx_1_sigs[24] = \ ; + assign pipe_tx_1_sigs[23] = \ ; + assign pipe_tx_1_sigs[22] = \ ; + assign pipe_tx_1_sigs[21] = \ ; + assign pipe_tx_1_sigs[20] = \ ; + assign pipe_tx_1_sigs[19] = \ ; + assign pipe_tx_1_sigs[18] = \ ; + assign pipe_tx_1_sigs[17] = \ ; + assign pipe_tx_1_sigs[16] = \ ; + assign pipe_tx_1_sigs[15] = \ ; + assign pipe_tx_1_sigs[14] = \ ; + assign pipe_tx_1_sigs[13] = \ ; + assign pipe_tx_1_sigs[12] = \ ; + assign pipe_tx_1_sigs[11] = \ ; + assign pipe_tx_1_sigs[10] = \ ; + assign pipe_tx_1_sigs[9] = \ ; + assign pipe_tx_1_sigs[8] = \ ; + assign pipe_tx_1_sigs[7] = \ ; + assign pipe_tx_1_sigs[6] = \ ; + assign pipe_tx_1_sigs[5] = \ ; + assign pipe_tx_1_sigs[4] = \ ; + assign pipe_tx_1_sigs[3] = \ ; + assign pipe_tx_1_sigs[2] = \ ; + assign pipe_tx_1_sigs[1] = \ ; + assign pipe_tx_1_sigs[0] = \ ; + assign pipe_tx_2_sigs[24] = \ ; + assign pipe_tx_2_sigs[23] = \ ; + assign pipe_tx_2_sigs[22] = \ ; + assign pipe_tx_2_sigs[21] = \ ; + assign pipe_tx_2_sigs[20] = \ ; + assign pipe_tx_2_sigs[19] = \ ; + assign pipe_tx_2_sigs[18] = \ ; + assign pipe_tx_2_sigs[17] = \ ; + assign pipe_tx_2_sigs[16] = \ ; + assign pipe_tx_2_sigs[15] = \ ; + assign pipe_tx_2_sigs[14] = \ ; + assign pipe_tx_2_sigs[13] = \ ; + assign pipe_tx_2_sigs[12] = \ ; + assign pipe_tx_2_sigs[11] = \ ; + assign pipe_tx_2_sigs[10] = \ ; + assign pipe_tx_2_sigs[9] = \ ; + assign pipe_tx_2_sigs[8] = \ ; + assign pipe_tx_2_sigs[7] = \ ; + assign pipe_tx_2_sigs[6] = \ ; + assign pipe_tx_2_sigs[5] = \ ; + assign pipe_tx_2_sigs[4] = \ ; + assign pipe_tx_2_sigs[3] = \ ; + assign pipe_tx_2_sigs[2] = \ ; + assign pipe_tx_2_sigs[1] = \ ; + assign pipe_tx_2_sigs[0] = \ ; + assign pipe_tx_3_sigs[24] = \ ; + assign pipe_tx_3_sigs[23] = \ ; + assign pipe_tx_3_sigs[22] = \ ; + assign pipe_tx_3_sigs[21] = \ ; + assign pipe_tx_3_sigs[20] = \ ; + assign pipe_tx_3_sigs[19] = \ ; + assign pipe_tx_3_sigs[18] = \ ; + assign pipe_tx_3_sigs[17] = \ ; + assign pipe_tx_3_sigs[16] = \ ; + assign pipe_tx_3_sigs[15] = \ ; + assign pipe_tx_3_sigs[14] = \ ; + assign pipe_tx_3_sigs[13] = \ ; + assign pipe_tx_3_sigs[12] = \ ; + assign pipe_tx_3_sigs[11] = \ ; + assign pipe_tx_3_sigs[10] = \ ; + assign pipe_tx_3_sigs[9] = \ ; + assign pipe_tx_3_sigs[8] = \ ; + assign pipe_tx_3_sigs[7] = \ ; + assign pipe_tx_3_sigs[6] = \ ; + assign pipe_tx_3_sigs[5] = \ ; + assign pipe_tx_3_sigs[4] = \ ; + assign pipe_tx_3_sigs[3] = \ ; + assign pipe_tx_3_sigs[2] = \ ; + assign pipe_tx_3_sigs[1] = \ ; + assign pipe_tx_3_sigs[0] = \ ; + assign pipe_tx_4_sigs[24] = \ ; + assign pipe_tx_4_sigs[23] = \ ; + assign pipe_tx_4_sigs[22] = \ ; + assign pipe_tx_4_sigs[21] = \ ; + assign pipe_tx_4_sigs[20] = \ ; + assign pipe_tx_4_sigs[19] = \ ; + assign pipe_tx_4_sigs[18] = \ ; + assign pipe_tx_4_sigs[17] = \ ; + assign pipe_tx_4_sigs[16] = \ ; + assign pipe_tx_4_sigs[15] = \ ; + assign pipe_tx_4_sigs[14] = \ ; + assign pipe_tx_4_sigs[13] = \ ; + assign pipe_tx_4_sigs[12] = \ ; + assign pipe_tx_4_sigs[11] = \ ; + assign pipe_tx_4_sigs[10] = \ ; + assign pipe_tx_4_sigs[9] = \ ; + assign pipe_tx_4_sigs[8] = \ ; + assign pipe_tx_4_sigs[7] = \ ; + assign pipe_tx_4_sigs[6] = \ ; + assign pipe_tx_4_sigs[5] = \ ; + assign pipe_tx_4_sigs[4] = \ ; + assign pipe_tx_4_sigs[3] = \ ; + assign pipe_tx_4_sigs[2] = \ ; + assign pipe_tx_4_sigs[1] = \ ; + assign pipe_tx_4_sigs[0] = \ ; + assign pipe_tx_5_sigs[24] = \ ; + assign pipe_tx_5_sigs[23] = \ ; + assign pipe_tx_5_sigs[22] = \ ; + assign pipe_tx_5_sigs[21] = \ ; + assign pipe_tx_5_sigs[20] = \ ; + assign pipe_tx_5_sigs[19] = \ ; + assign pipe_tx_5_sigs[18] = \ ; + assign pipe_tx_5_sigs[17] = \ ; + assign pipe_tx_5_sigs[16] = \ ; + assign pipe_tx_5_sigs[15] = \ ; + assign pipe_tx_5_sigs[14] = \ ; + assign pipe_tx_5_sigs[13] = \ ; + assign pipe_tx_5_sigs[12] = \ ; + assign pipe_tx_5_sigs[11] = \ ; + assign pipe_tx_5_sigs[10] = \ ; + assign pipe_tx_5_sigs[9] = \ ; + assign pipe_tx_5_sigs[8] = \ ; + assign pipe_tx_5_sigs[7] = \ ; + assign pipe_tx_5_sigs[6] = \ ; + assign pipe_tx_5_sigs[5] = \ ; + assign pipe_tx_5_sigs[4] = \ ; + assign pipe_tx_5_sigs[3] = \ ; + assign pipe_tx_5_sigs[2] = \ ; + assign pipe_tx_5_sigs[1] = \ ; + assign pipe_tx_5_sigs[0] = \ ; + assign pipe_tx_6_sigs[24] = \ ; + assign pipe_tx_6_sigs[23] = \ ; + assign pipe_tx_6_sigs[22] = \ ; + assign pipe_tx_6_sigs[21] = \ ; + assign pipe_tx_6_sigs[20] = \ ; + assign pipe_tx_6_sigs[19] = \ ; + assign pipe_tx_6_sigs[18] = \ ; + assign pipe_tx_6_sigs[17] = \ ; + assign pipe_tx_6_sigs[16] = \ ; + assign pipe_tx_6_sigs[15] = \ ; + assign pipe_tx_6_sigs[14] = \ ; + assign pipe_tx_6_sigs[13] = \ ; + assign pipe_tx_6_sigs[12] = \ ; + assign pipe_tx_6_sigs[11] = \ ; + assign pipe_tx_6_sigs[10] = \ ; + assign pipe_tx_6_sigs[9] = \ ; + assign pipe_tx_6_sigs[8] = \ ; + assign pipe_tx_6_sigs[7] = \ ; + assign pipe_tx_6_sigs[6] = \ ; + assign pipe_tx_6_sigs[5] = \ ; + assign pipe_tx_6_sigs[4] = \ ; + assign pipe_tx_6_sigs[3] = \ ; + assign pipe_tx_6_sigs[2] = \ ; + assign pipe_tx_6_sigs[1] = \ ; + assign pipe_tx_6_sigs[0] = \ ; + assign pipe_tx_7_sigs[24] = \ ; + assign pipe_tx_7_sigs[23] = \ ; + assign pipe_tx_7_sigs[22] = \ ; + assign pipe_tx_7_sigs[21] = \ ; + assign pipe_tx_7_sigs[20] = \ ; + assign pipe_tx_7_sigs[19] = \ ; + assign pipe_tx_7_sigs[18] = \ ; + assign pipe_tx_7_sigs[17] = \ ; + assign pipe_tx_7_sigs[16] = \ ; + assign pipe_tx_7_sigs[15] = \ ; + assign pipe_tx_7_sigs[14] = \ ; + assign pipe_tx_7_sigs[13] = \ ; + assign pipe_tx_7_sigs[12] = \ ; + assign pipe_tx_7_sigs[11] = \ ; + assign pipe_tx_7_sigs[10] = \ ; + assign pipe_tx_7_sigs[9] = \ ; + assign pipe_tx_7_sigs[8] = \ ; + assign pipe_tx_7_sigs[7] = \ ; + assign pipe_tx_7_sigs[6] = \ ; + assign pipe_tx_7_sigs[5] = \ ; + assign pipe_tx_7_sigs[4] = \ ; + assign pipe_tx_7_sigs[3] = \ ; + assign pipe_tx_7_sigs[2] = \ ; + assign pipe_tx_7_sigs[1] = \ ; + assign pipe_tx_7_sigs[0] = \ ; + assign pipe_txdlysresetdone[3] = \ ; + assign pipe_txdlysresetdone[2] = \ ; + assign pipe_txdlysresetdone[1] = \ ; + assign pipe_txdlysresetdone[0] = \ ; + assign pipe_txphaligndone[3] = \ ; + assign pipe_txphaligndone[2] = \ ; + assign pipe_txphaligndone[1] = \ ; + assign pipe_txphaligndone[0] = \ ; + assign pipe_txphinitdone[3] = \ ; + assign pipe_txphinitdone[2] = \ ; + assign pipe_txphinitdone[1] = \ ; + assign pipe_txphinitdone[0] = \ ; + assign qpll_drp_clk = \ ; + assign qpll_drp_gen3 = \ ; + assign qpll_drp_ovrd = \ ; + assign qpll_drp_rst_n = \ ; + assign qpll_drp_start = \ ; + assign qpll_qplld = \ ; + assign qpll_qpllreset[1] = \ ; + assign qpll_qpllreset[0] = \ ; + assign startup_cfgclk = \ ; + assign startup_cfgmclk = \ ; + assign startup_eos = \ ; + assign startup_preq = \ ; + assign user_app_rdy = \ ; + assign user_clk_out = pipe_userclk2_in; + GND GND + (.G(\ )); + pcie_7x_0_pcie_7x_0_core_top inst + (.cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en), + .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en), + .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum), + .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received), + .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en), + .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received), + .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en), + .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received), + .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en), + .cfg_bridge_serr_en(cfg_bridge_serr_en), + .cfg_bus_number(cfg_bus_number), + .cfg_command({\^cfg_command [10],\^cfg_command [8],\^cfg_command [2:0]}), + .cfg_dcommand(\^cfg_dcommand ), + .cfg_dcommand2(\^cfg_dcommand2 ), + .cfg_device_number(cfg_device_number), + .cfg_ds_bus_number(cfg_ds_bus_number), + .cfg_ds_device_number(cfg_ds_device_number), + .cfg_ds_function_number(cfg_ds_function_number), + .cfg_dsn(cfg_dsn), + .cfg_dstatus(\^cfg_dstatus ), + .cfg_err_aer_headerlog(cfg_err_aer_headerlog), + .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set), + .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked), + .cfg_err_cor(cfg_err_cor), + .cfg_err_cpl_abort(cfg_err_cpl_abort), + .cfg_err_cpl_rdy(cfg_err_cpl_rdy), + .cfg_err_cpl_timeout(cfg_err_cpl_timeout), + .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect), + .cfg_err_ecrc(cfg_err_ecrc), + .cfg_err_internal_cor(cfg_err_internal_cor), + .cfg_err_internal_uncor(cfg_err_internal_uncor), + .cfg_err_locked(cfg_err_locked), + .cfg_err_malformed(cfg_err_malformed), + .cfg_err_mc_blocked(cfg_err_mc_blocked), + .cfg_err_norecovery(cfg_err_norecovery), + .cfg_err_poisoned(cfg_err_poisoned), + .cfg_err_posted(cfg_err_posted), + .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header), + .cfg_err_ur(cfg_err_ur), + .cfg_function_number(cfg_function_number), + .cfg_interrupt(cfg_interrupt), + .cfg_interrupt_assert(cfg_interrupt_assert), + .cfg_interrupt_di(cfg_interrupt_di), + .cfg_interrupt_do(cfg_interrupt_do), + .cfg_interrupt_mmenable(cfg_interrupt_mmenable), + .cfg_interrupt_msienable(cfg_interrupt_msienable), + .cfg_interrupt_msixenable(cfg_interrupt_msixenable), + .cfg_interrupt_msixfm(cfg_interrupt_msixfm), + .cfg_interrupt_rdy(cfg_interrupt_rdy), + .cfg_interrupt_stat(cfg_interrupt_stat), + .cfg_lcommand({\^cfg_lcommand [11:3],\^cfg_lcommand [1:0]}), + .cfg_lstatus({\^cfg_lstatus [15:13],\^cfg_lstatus [11],\^cfg_lstatus [7:4],\^cfg_lstatus [1:0]}), + .cfg_mgmt_byte_en(cfg_mgmt_byte_en), + .cfg_mgmt_di(cfg_mgmt_di), + .cfg_mgmt_do(cfg_mgmt_do), + .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr), + .cfg_mgmt_rd_en(cfg_mgmt_rd_en), + .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done), + .cfg_mgmt_wr_en(cfg_mgmt_wr_en), + .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly), + .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw), + .cfg_msg_data(cfg_msg_data), + .cfg_msg_received(cfg_msg_received), + .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a), + .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b), + .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c), + .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d), + .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a), + .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b), + .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c), + .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d), + .cfg_msg_received_err_cor(cfg_msg_received_err_cor), + .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal), + .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal), + .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak), + .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme), + .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack), + .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit), + .cfg_pcie_link_state(cfg_pcie_link_state), + .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum), + .cfg_pm_force_state(cfg_pm_force_state), + .cfg_pm_force_state_en(cfg_pm_force_state_en), + .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s), + .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1), + .cfg_pm_wake(cfg_pm_wake), + .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en), + .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status), + .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate), + .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst), + .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en), + .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en), + .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en), + .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en), + .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse), + .cfg_to_turnoff(cfg_to_turnoff), + .cfg_trn_pending(cfg_trn_pending), + .cfg_turnoff_ok(cfg_turnoff_ok), + .cfg_vc_tcvc_map(cfg_vc_tcvc_map), + .fc_cpld(fc_cpld), + .fc_cplh(fc_cplh), + .fc_npd(fc_npd), + .fc_nph(fc_nph), + .fc_pd(fc_pd), + .fc_ph(fc_ph), + .fc_sel(fc_sel), + .gen3_reg(pipe_gen3_out), + .m_axis_rx_tdata(m_axis_rx_tdata), + .m_axis_rx_tkeep(\^m_axis_rx_tkeep ), + .m_axis_rx_tlast(m_axis_rx_tlast), + .m_axis_rx_tready(m_axis_rx_tready), + .m_axis_rx_tuser({\^m_axis_rx_tuser [21],\^m_axis_rx_tuser [19],\^m_axis_rx_tuser [17],\^m_axis_rx_tuser [14],\^m_axis_rx_tuser [8:0]}), + .m_axis_rx_tvalid(m_axis_rx_tvalid), + .pci_exp_rxn(pci_exp_rxn), + .pci_exp_rxp(pci_exp_rxp), + .pci_exp_txn(pci_exp_txn), + .pci_exp_txp(pci_exp_txp), + .pcie_drp_addr(pcie_drp_addr), + .pcie_drp_clk(pcie_drp_clk), + .pcie_drp_di(pcie_drp_di), + .pcie_drp_do(pcie_drp_do), + .pcie_drp_en(pcie_drp_en), + .pcie_drp_rdy(pcie_drp_rdy), + .pcie_drp_we(pcie_drp_we), + .pipe_dclk_in(pipe_dclk_in), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_oobclk_in(pipe_oobclk_in), + .pipe_pclk_in(pipe_pclk_in), + .pipe_pclk_sel_out(pipe_pclk_sel_out), + .pipe_rxoutclk_out(pipe_rxoutclk_out), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .pipe_txoutclk_out(pipe_txoutclk_out), + .pipe_userclk1_in(pipe_userclk1_in), + .pipe_userclk2_in(pipe_userclk2_in), + .pl_directed_change_done(pl_directed_change_done), + .pl_directed_link_auton(pl_directed_link_auton), + .pl_directed_link_change(pl_directed_link_change), + .pl_directed_link_speed(pl_directed_link_speed), + .pl_directed_link_width(pl_directed_link_width), + .pl_downstream_deemph_source(pl_downstream_deemph_source), + .pl_initial_link_width(pl_initial_link_width), + .pl_lane_reversal_mode(pl_lane_reversal_mode), + .pl_link_gen2_cap(pl_link_gen2_cap), + .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported), + .pl_link_upcfg_cap(pl_link_upcfg_cap), + .pl_ltssm_state(pl_ltssm_state), + .pl_phy_lnk_up(pl_phy_lnk_up), + .pl_received_hot_rst(pl_received_hot_rst), + .pl_rx_pm_state(pl_rx_pm_state), + .pl_sel_lnk_rate(pl_sel_lnk_rate), + .pl_sel_lnk_width(pl_sel_lnk_width), + .pl_transmit_hot_rst(pl_transmit_hot_rst), + .pl_tx_pm_state(pl_tx_pm_state), + .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph), + .rx_np_ok(rx_np_ok), + .rx_np_req(rx_np_req), + .s_axis_tx_tdata(s_axis_tx_tdata), + .s_axis_tx_tkeep(s_axis_tx_tkeep[7]), + .s_axis_tx_tlast(s_axis_tx_tlast), + .s_axis_tx_tready(s_axis_tx_tready), + .s_axis_tx_tuser(s_axis_tx_tuser), + .s_axis_tx_tvalid(s_axis_tx_tvalid), + .sys_clk(sys_clk), + .sys_rst_n(sys_rst_n), + .tx_buf_av(tx_buf_av), + .tx_cfg_gnt(tx_cfg_gnt), + .tx_cfg_req(tx_cfg_req), + .tx_err_drop(tx_err_drop), + .user_lnk_up(user_lnk_up), + .user_reset_out(user_reset_out)); +endmodule + +module pcie_7x_0_pcie_7x_0_pcie_7x + (user_reset_int_reg, + src_in, + cfg_mgmt_rd_wr_done, + cfg_err_aer_headerlog_set, + cfg_err_cpl_rdy, + cfg_interrupt_rdy, + E, + cfg_msg_received, + cfg_received_func_lvl_rst, + trn_in_packet_reg, + trn_reof, + trn_rsof, + trn_rsrc_dsc, + ppm_L1_thrtl_reg, + cfg_pcie_link_state, + dsc_detect, + rsrc_rdy_filtered, + trn_rsrc_dsc_prev0, + tcfg_req_trig, + trn_tcfg_req, + pcie_drp_clk_0, + trn_tbuf_av, + tbuf_av_min_trig, + lnk_up_thrtl_reg, + trn_tdst_rdy, + cfg_aer_ecrc_check_en, + cfg_aer_ecrc_gen_en, + cfg_aer_rooterr_corr_err_received, + cfg_aer_rooterr_corr_err_reporting_en, + cfg_aer_rooterr_fatal_err_received, + cfg_aer_rooterr_fatal_err_reporting_en, + cfg_aer_rooterr_non_fatal_err_received, + cfg_aer_rooterr_non_fatal_err_reporting_en, + cfg_bridge_serr_en, + cfg_command, + cfg_dcommand2, + cfg_dcommand, + cfg_dstatus, + cfg_interrupt_msienable, + cfg_interrupt_msixenable, + cfg_interrupt_msixfm, + cfg_lcommand, + cfg_lstatus, + cfg_msg_received_assert_int_a, + cfg_msg_received_assert_int_b, + cfg_msg_received_assert_int_c, + cfg_msg_received_assert_int_d, + cfg_msg_received_deassert_int_a, + cfg_msg_received_deassert_int_b, + cfg_msg_received_deassert_int_c, + cfg_msg_received_deassert_int_d, + cfg_msg_received_err_cor, + cfg_msg_received_err_fatal, + cfg_msg_received_err_non_fatal, + cfg_msg_received_pm_as_nak, + cfg_to_turnoff, + cfg_msg_received_pme_to_ack, + cfg_msg_received_pm_pme, + cfg_msg_received_setslotpowerlimit, + cfg_pmcsr_pme_en, + cfg_pmcsr_pme_status, + cfg_root_control_pme_int_en, + cfg_root_control_syserr_corr_err_en, + cfg_root_control_syserr_fatal_err_en, + cfg_root_control_syserr_non_fatal_err_en, + cfg_slot_control_electromech_il_ctl_pulse, + pcie_drp_rdy, + pipe_rx0_polarity, + pipe_rx1_polarity, + pipe_rx2_polarity, + pipe_rx3_polarity, + pipe_tx0_compliance, + pipe_tx0_elec_idle, + pipe_tx1_compliance, + pipe_tx1_elec_idle, + pipe_tx2_compliance, + pipe_tx2_elec_idle, + pipe_tx3_compliance, + pipe_tx3_elec_idle, + pipe_tx_deemph, + pipe_tx_rate, + pipe_tx_rcvr_det, + pl_directed_change_done, + pl_link_gen2_cap, + pl_link_partner_gen2_supported, + pl_link_upcfg_cap, + pl_received_hot_rst, + pl_sel_lnk_rate, + trn_lnk_up, + trn_recrc_err, + trn_rerrfwd, + tx_err_drop, + fc_cpld, + fc_npd, + fc_pd, + pcie_drp_clk_1, + cfg_msg_data, + pcie_drp_do, + pipe_tx0_data, + pipe_tx1_data, + pipe_tx2_data, + pipe_tx3_data, + cfg_pmcsr_powerstate, + pipe_tx0_char_is_k, + pipe_tx0_powerdown, + pipe_tx1_char_is_k, + pipe_tx1_powerdown, + pipe_tx2_char_is_k, + pipe_tx2_powerdown, + pipe_tx3_char_is_k, + pipe_tx3_powerdown, + pl_lane_reversal_mode, + pl_rx_pm_state, + pl_sel_lnk_width, + pcie_drp_clk_2, + cfg_interrupt_mmenable, + pipe_tx_margin, + pl_initial_link_width, + pl_tx_pm_state, + cfg_mgmt_do, + pl_ltssm_state, + cfg_vc_tcvc_map, + cfg_interrupt_do, + fc_cplh, + fc_nph, + fc_ph, + trn_rbar_hit, + bridge_reset_int, + pl_phy_lnk_up, + cfg_trn_pending, + cfg_mgmt_wr_rw1c_as_rw, + cfg_mgmt_wr_readonly, + cfg_mgmt_wr_en, + cfg_mgmt_rd_en, + cfg_err_malformed, + cfg_err_cor, + cfg_err_ur, + cfg_err_ecrc, + cfg_err_cpl_timeout, + cfg_err_cpl_abort, + cfg_err_cpl_unexpect, + cfg_err_poisoned, + cfg_err_atomic_egress_blocked, + cfg_err_mc_blocked, + cfg_err_internal_uncor, + cfg_err_internal_cor, + cfg_err_posted, + cfg_err_locked, + cfg_err_norecovery, + cfg_interrupt, + cfg_interrupt_assert, + cfg_interrupt_stat, + cfg_pm_halt_aspm_l0s, + cfg_pm_halt_aspm_l1, + cfg_pm_force_state_en, + cfg_pm_wake, + trn_in_packet, + trn_rdst_rdy, + ppm_L1_trig, + ppm_L1_thrtl, + trn_rsrc_dsc_d, + reg_dsc_detect, + reg_tcfg_gnt, + lnk_up_thrtl, + out, + pipe_userclk1_in, + cfg_pm_turnoff_ok_n, + pcie_drp_clk, + pcie_drp_en, + pcie_drp_we, + pipe_pclk_in, + pipe_rx0_chanisaligned, + pipe_rx0_elec_idle, + pipe_rx0_phy_status, + pipe_rx0_valid, + pipe_rx1_chanisaligned, + pipe_rx1_elec_idle, + pipe_rx1_phy_status, + pipe_rx1_valid, + pipe_rx2_chanisaligned, + pipe_rx2_elec_idle, + pipe_rx2_phy_status, + pipe_rx2_valid, + pipe_rx3_chanisaligned, + pipe_rx3_elec_idle, + pipe_rx3_phy_status, + pipe_rx3_valid, + pl_directed_link_auton, + pl_directed_link_speed, + pl_downstream_deemph_source, + pl_transmit_hot_rst, + pl_upstream_prefer_deemph, + sys_rst_n, + rx_np_ok, + rx_np_req, + trn_tcfg_gnt, + cfg_aer_ecrc_check_en_0, + trn_teof, + trn_tsof, + trn_tsrc_rdy, + pipe_userclk2_in, + cfg_err_aer_headerlog, + trn_td, + pcie_drp_di, + Q, + cfg_aer_ecrc_check_en_1, + cfg_aer_ecrc_check_en_2, + cfg_aer_ecrc_check_en_3, + cfg_pm_force_state, + cfg_aer_ecrc_check_en_4, + cfg_aer_ecrc_check_en_5, + cfg_aer_ecrc_check_en_6, + cfg_aer_ecrc_check_en_7, + pl_directed_link_change, + pl_directed_link_width, + trn_trem, + cfg_ds_function_number, + cfg_aer_ecrc_check_en_8, + cfg_aer_ecrc_check_en_9, + cfg_aer_ecrc_check_en_10, + cfg_aer_ecrc_check_en_11, + fc_sel, + cfg_mgmt_di, + cfg_mgmt_byte_en_n, + cfg_err_tlp_cpl_header, + cfg_aer_interrupt_msgnum, + cfg_ds_device_number, + cfg_pciecap_interrupt_msgnum, + cfg_dsn, + cfg_ds_bus_number, + cfg_interrupt_di, + pcie_drp_addr, + cfg_mgmt_dwaddr); + output user_reset_int_reg; + output src_in; + output cfg_mgmt_rd_wr_done; + output cfg_err_aer_headerlog_set; + output cfg_err_cpl_rdy; + output cfg_interrupt_rdy; + output [0:0]E; + output cfg_msg_received; + output cfg_received_func_lvl_rst; + output trn_in_packet_reg; + output trn_reof; + output trn_rsof; + output trn_rsrc_dsc; + output ppm_L1_thrtl_reg; + output [2:0]cfg_pcie_link_state; + output dsc_detect; + output rsrc_rdy_filtered; + output trn_rsrc_dsc_prev0; + output tcfg_req_trig; + output trn_tcfg_req; + output pcie_drp_clk_0; + output [5:0]trn_tbuf_av; + output tbuf_av_min_trig; + output lnk_up_thrtl_reg; + output trn_tdst_rdy; + output cfg_aer_ecrc_check_en; + output cfg_aer_ecrc_gen_en; + output cfg_aer_rooterr_corr_err_received; + output cfg_aer_rooterr_corr_err_reporting_en; + output cfg_aer_rooterr_fatal_err_received; + output cfg_aer_rooterr_fatal_err_reporting_en; + output cfg_aer_rooterr_non_fatal_err_received; + output cfg_aer_rooterr_non_fatal_err_reporting_en; + output cfg_bridge_serr_en; + output [4:0]cfg_command; + output [11:0]cfg_dcommand2; + output [14:0]cfg_dcommand; + output [3:0]cfg_dstatus; + output cfg_interrupt_msienable; + output cfg_interrupt_msixenable; + output cfg_interrupt_msixfm; + output [10:0]cfg_lcommand; + output [9:0]cfg_lstatus; + output cfg_msg_received_assert_int_a; + output cfg_msg_received_assert_int_b; + output cfg_msg_received_assert_int_c; + output cfg_msg_received_assert_int_d; + output cfg_msg_received_deassert_int_a; + output cfg_msg_received_deassert_int_b; + output cfg_msg_received_deassert_int_c; + output cfg_msg_received_deassert_int_d; + output cfg_msg_received_err_cor; + output cfg_msg_received_err_fatal; + output cfg_msg_received_err_non_fatal; + output cfg_msg_received_pm_as_nak; + output cfg_to_turnoff; + output cfg_msg_received_pme_to_ack; + output cfg_msg_received_pm_pme; + output cfg_msg_received_setslotpowerlimit; + output cfg_pmcsr_pme_en; + output cfg_pmcsr_pme_status; + output cfg_root_control_pme_int_en; + output cfg_root_control_syserr_corr_err_en; + output cfg_root_control_syserr_fatal_err_en; + output cfg_root_control_syserr_non_fatal_err_en; + output cfg_slot_control_electromech_il_ctl_pulse; + output pcie_drp_rdy; + output pipe_rx0_polarity; + output pipe_rx1_polarity; + output pipe_rx2_polarity; + output pipe_rx3_polarity; + output pipe_tx0_compliance; + output pipe_tx0_elec_idle; + output pipe_tx1_compliance; + output pipe_tx1_elec_idle; + output pipe_tx2_compliance; + output pipe_tx2_elec_idle; + output pipe_tx3_compliance; + output pipe_tx3_elec_idle; + output pipe_tx_deemph; + output pipe_tx_rate; + output pipe_tx_rcvr_det; + output pl_directed_change_done; + output pl_link_gen2_cap; + output pl_link_partner_gen2_supported; + output pl_link_upcfg_cap; + output pl_received_hot_rst; + output pl_sel_lnk_rate; + output trn_lnk_up; + output trn_recrc_err; + output trn_rerrfwd; + output tx_err_drop; + output [11:0]fc_cpld; + output [11:0]fc_npd; + output [11:0]fc_pd; + output [63:0]pcie_drp_clk_1; + output [15:0]cfg_msg_data; + output [15:0]pcie_drp_do; + output [15:0]pipe_tx0_data; + output [15:0]pipe_tx1_data; + output [15:0]pipe_tx2_data; + output [15:0]pipe_tx3_data; + output [1:0]cfg_pmcsr_powerstate; + output [1:0]pipe_tx0_char_is_k; + output [1:0]pipe_tx0_powerdown; + output [1:0]pipe_tx1_char_is_k; + output [1:0]pipe_tx1_powerdown; + output [1:0]pipe_tx2_char_is_k; + output [1:0]pipe_tx2_powerdown; + output [1:0]pipe_tx3_char_is_k; + output [1:0]pipe_tx3_powerdown; + output [1:0]pl_lane_reversal_mode; + output [1:0]pl_rx_pm_state; + output [1:0]pl_sel_lnk_width; + output [0:0]pcie_drp_clk_2; + output [2:0]cfg_interrupt_mmenable; + output [2:0]pipe_tx_margin; + output [2:0]pl_initial_link_width; + output [2:0]pl_tx_pm_state; + output [31:0]cfg_mgmt_do; + output [5:0]pl_ltssm_state; + output [6:0]cfg_vc_tcvc_map; + output [7:0]cfg_interrupt_do; + output [7:0]fc_cplh; + output [7:0]fc_nph; + output [7:0]fc_ph; + output [6:0]trn_rbar_hit; + input bridge_reset_int; + input pl_phy_lnk_up; + input cfg_trn_pending; + input cfg_mgmt_wr_rw1c_as_rw; + input cfg_mgmt_wr_readonly; + input cfg_mgmt_wr_en; + input cfg_mgmt_rd_en; + input cfg_err_malformed; + input cfg_err_cor; + input cfg_err_ur; + input cfg_err_ecrc; + input cfg_err_cpl_timeout; + input cfg_err_cpl_abort; + input cfg_err_cpl_unexpect; + input cfg_err_poisoned; + input cfg_err_atomic_egress_blocked; + input cfg_err_mc_blocked; + input cfg_err_internal_uncor; + input cfg_err_internal_cor; + input cfg_err_posted; + input cfg_err_locked; + input cfg_err_norecovery; + input cfg_interrupt; + input cfg_interrupt_assert; + input cfg_interrupt_stat; + input cfg_pm_halt_aspm_l0s; + input cfg_pm_halt_aspm_l1; + input cfg_pm_force_state_en; + input cfg_pm_wake; + input trn_in_packet; + input trn_rdst_rdy; + input ppm_L1_trig; + input ppm_L1_thrtl; + input trn_rsrc_dsc_d; + input reg_dsc_detect; + input reg_tcfg_gnt; + input lnk_up_thrtl; + input out; + input pipe_userclk1_in; + input cfg_pm_turnoff_ok_n; + input pcie_drp_clk; + input pcie_drp_en; + input pcie_drp_we; + input pipe_pclk_in; + input pipe_rx0_chanisaligned; + input pipe_rx0_elec_idle; + input pipe_rx0_phy_status; + input pipe_rx0_valid; + input pipe_rx1_chanisaligned; + input pipe_rx1_elec_idle; + input pipe_rx1_phy_status; + input pipe_rx1_valid; + input pipe_rx2_chanisaligned; + input pipe_rx2_elec_idle; + input pipe_rx2_phy_status; + input pipe_rx2_valid; + input pipe_rx3_chanisaligned; + input pipe_rx3_elec_idle; + input pipe_rx3_phy_status; + input pipe_rx3_valid; + input pl_directed_link_auton; + input pl_directed_link_speed; + input pl_downstream_deemph_source; + input pl_transmit_hot_rst; + input pl_upstream_prefer_deemph; + input sys_rst_n; + input rx_np_ok; + input rx_np_req; + input trn_tcfg_gnt; + input [3:0]cfg_aer_ecrc_check_en_0; + input trn_teof; + input trn_tsof; + input trn_tsrc_rdy; + input pipe_userclk2_in; + input [127:0]cfg_err_aer_headerlog; + input [63:0]trn_td; + input [15:0]pcie_drp_di; + input [15:0]Q; + input [15:0]cfg_aer_ecrc_check_en_1; + input [15:0]cfg_aer_ecrc_check_en_2; + input [15:0]cfg_aer_ecrc_check_en_3; + input [1:0]cfg_pm_force_state; + input [1:0]cfg_aer_ecrc_check_en_4; + input [1:0]cfg_aer_ecrc_check_en_5; + input [1:0]cfg_aer_ecrc_check_en_6; + input [1:0]cfg_aer_ecrc_check_en_7; + input [1:0]pl_directed_link_change; + input [1:0]pl_directed_link_width; + input [0:0]trn_trem; + input [2:0]cfg_ds_function_number; + input [2:0]cfg_aer_ecrc_check_en_8; + input [2:0]cfg_aer_ecrc_check_en_9; + input [2:0]cfg_aer_ecrc_check_en_10; + input [2:0]cfg_aer_ecrc_check_en_11; + input [2:0]fc_sel; + input [31:0]cfg_mgmt_di; + input [3:0]cfg_mgmt_byte_en_n; + input [47:0]cfg_err_tlp_cpl_header; + input [4:0]cfg_aer_interrupt_msgnum; + input [4:0]cfg_ds_device_number; + input [4:0]cfg_pciecap_interrupt_msgnum; + input [63:0]cfg_dsn; + input [7:0]cfg_ds_bus_number; + input [7:0]cfg_interrupt_di; + input [8:0]pcie_drp_addr; + input [9:0]cfg_mgmt_dwaddr; + + wire [0:0]E; + wire [15:0]Q; + wire bridge_reset_int; + wire cfg_aer_ecrc_check_en; + wire [3:0]cfg_aer_ecrc_check_en_0; + wire [15:0]cfg_aer_ecrc_check_en_1; + wire [2:0]cfg_aer_ecrc_check_en_10; + wire [2:0]cfg_aer_ecrc_check_en_11; + wire [15:0]cfg_aer_ecrc_check_en_2; + wire [15:0]cfg_aer_ecrc_check_en_3; + wire [1:0]cfg_aer_ecrc_check_en_4; + wire [1:0]cfg_aer_ecrc_check_en_5; + wire [1:0]cfg_aer_ecrc_check_en_6; + wire [1:0]cfg_aer_ecrc_check_en_7; + wire [2:0]cfg_aer_ecrc_check_en_8; + wire [2:0]cfg_aer_ecrc_check_en_9; + wire cfg_aer_ecrc_gen_en; + wire [4:0]cfg_aer_interrupt_msgnum; + wire cfg_aer_rooterr_corr_err_received; + wire cfg_aer_rooterr_corr_err_reporting_en; + wire cfg_aer_rooterr_fatal_err_received; + wire cfg_aer_rooterr_fatal_err_reporting_en; + wire cfg_aer_rooterr_non_fatal_err_received; + wire cfg_aer_rooterr_non_fatal_err_reporting_en; + wire cfg_bridge_serr_en; + wire [4:0]cfg_command; + wire [14:0]cfg_dcommand; + wire [11:0]cfg_dcommand2; + wire [7:0]cfg_ds_bus_number; + wire [4:0]cfg_ds_device_number; + wire [2:0]cfg_ds_function_number; + wire [63:0]cfg_dsn; + wire [3:0]cfg_dstatus; + wire [127:0]cfg_err_aer_headerlog; + wire cfg_err_aer_headerlog_set; + wire cfg_err_aer_headerlog_set_n; + wire cfg_err_atomic_egress_blocked; + wire cfg_err_cor; + wire cfg_err_cpl_abort; + wire cfg_err_cpl_rdy; + wire cfg_err_cpl_rdy_n; + wire cfg_err_cpl_timeout; + wire cfg_err_cpl_unexpect; + wire cfg_err_ecrc; + wire cfg_err_internal_cor; + wire cfg_err_internal_uncor; + wire cfg_err_locked; + wire cfg_err_malformed; + wire cfg_err_mc_blocked; + wire cfg_err_norecovery; + wire cfg_err_poisoned; + wire cfg_err_posted; + wire [47:0]cfg_err_tlp_cpl_header; + wire cfg_err_ur; + wire cfg_interrupt; + wire cfg_interrupt_assert; + wire [7:0]cfg_interrupt_di; + wire [7:0]cfg_interrupt_do; + wire [2:0]cfg_interrupt_mmenable; + wire cfg_interrupt_msienable; + wire cfg_interrupt_msixenable; + wire cfg_interrupt_msixfm; + wire cfg_interrupt_rdy; + wire cfg_interrupt_rdy_n; + wire cfg_interrupt_stat; + wire [10:0]cfg_lcommand; + wire [9:0]cfg_lstatus; + wire [3:0]cfg_mgmt_byte_en_n; + wire [31:0]cfg_mgmt_di; + wire [31:0]cfg_mgmt_do; + wire [9:0]cfg_mgmt_dwaddr; + wire cfg_mgmt_rd_en; + wire cfg_mgmt_rd_wr_done; + wire cfg_mgmt_rd_wr_done_n; + wire cfg_mgmt_wr_en; + wire cfg_mgmt_wr_readonly; + wire cfg_mgmt_wr_rw1c_as_rw; + wire [15:0]cfg_msg_data; + wire cfg_msg_received; + wire cfg_msg_received_assert_int_a; + wire cfg_msg_received_assert_int_b; + wire cfg_msg_received_assert_int_c; + wire cfg_msg_received_assert_int_d; + wire cfg_msg_received_deassert_int_a; + wire cfg_msg_received_deassert_int_b; + wire cfg_msg_received_deassert_int_c; + wire cfg_msg_received_deassert_int_d; + wire cfg_msg_received_err_cor; + wire cfg_msg_received_err_fatal; + wire cfg_msg_received_err_non_fatal; + wire cfg_msg_received_pm_as_nak; + wire cfg_msg_received_pm_pme; + wire cfg_msg_received_pme_to_ack; + wire cfg_msg_received_setslotpowerlimit; + wire [2:0]cfg_pcie_link_state; + wire [4:0]cfg_pciecap_interrupt_msgnum; + wire [1:0]cfg_pm_force_state; + wire cfg_pm_force_state_en; + wire cfg_pm_halt_aspm_l0s; + wire cfg_pm_halt_aspm_l1; + wire cfg_pm_turnoff_ok_n; + wire cfg_pm_wake; + wire cfg_pmcsr_pme_en; + wire cfg_pmcsr_pme_status; + wire [1:0]cfg_pmcsr_powerstate; + wire cfg_received_func_lvl_rst; + wire cfg_received_func_lvl_rst_n; + wire cfg_root_control_pme_int_en; + wire cfg_root_control_syserr_corr_err_en; + wire cfg_root_control_syserr_fatal_err_en; + wire cfg_root_control_syserr_non_fatal_err_en; + wire cfg_slot_control_electromech_il_ctl_pulse; + wire cfg_to_turnoff; + wire cfg_trn_pending; + wire [6:0]cfg_vc_tcvc_map; + wire dsc_detect; + wire [11:0]fc_cpld; + wire [7:0]fc_cplh; + wire [11:0]fc_npd; + wire [7:0]fc_nph; + wire [11:0]fc_pd; + wire [7:0]fc_ph; + wire [2:0]fc_sel; + wire lnk_up_thrtl; + wire lnk_up_thrtl_reg; + wire [12:0]mim_rx_raddr; + wire [67:0]mim_rx_rdata; + wire mim_rx_ren; + wire [12:0]mim_rx_waddr; + wire [67:0]mim_rx_wdata; + wire mim_rx_wen; + wire [12:0]mim_tx_raddr; + wire [68:0]mim_tx_rdata; + wire mim_tx_ren; + wire [12:0]mim_tx_waddr; + wire [68:0]mim_tx_wdata; + wire mim_tx_wen; + wire out; + wire pcie_block_i_i_10_n_0; + wire pcie_block_i_i_11_n_0; + wire pcie_block_i_i_12_n_0; + wire pcie_block_i_i_13_n_0; + wire pcie_block_i_i_14_n_0; + wire pcie_block_i_i_15_n_0; + wire pcie_block_i_i_16_n_0; + wire pcie_block_i_i_17_n_0; + wire pcie_block_i_i_18_n_0; + wire pcie_block_i_i_19_n_0; + wire pcie_block_i_i_1_n_0; + wire pcie_block_i_i_20_n_0; + wire pcie_block_i_i_21_n_0; + wire pcie_block_i_i_22_n_0; + wire pcie_block_i_i_23_n_0; + wire pcie_block_i_i_24_n_0; + wire pcie_block_i_i_25_n_0; + wire pcie_block_i_i_27_n_0; + wire pcie_block_i_i_28_n_0; + wire pcie_block_i_i_2_n_0; + wire pcie_block_i_i_3_n_0; + wire pcie_block_i_i_4_n_0; + wire pcie_block_i_i_5_n_0; + wire pcie_block_i_i_6_n_0; + wire pcie_block_i_i_7_n_0; + wire pcie_block_i_i_8_n_0; + wire pcie_block_i_i_9_n_0; + wire pcie_block_i_n_100; + wire pcie_block_i_n_101; + wire pcie_block_i_n_102; + wire pcie_block_i_n_103; + wire pcie_block_i_n_104; + wire pcie_block_i_n_105; + wire pcie_block_i_n_106; + wire pcie_block_i_n_107; + wire pcie_block_i_n_108; + wire pcie_block_i_n_1097; + wire pcie_block_i_n_1098; + wire pcie_block_i_n_1099; + wire pcie_block_i_n_1100; + wire pcie_block_i_n_1101; + wire pcie_block_i_n_1102; + wire pcie_block_i_n_1103; + wire pcie_block_i_n_1143; + wire pcie_block_i_n_140; + wire pcie_block_i_n_141; + wire pcie_block_i_n_142; + wire pcie_block_i_n_143; + wire pcie_block_i_n_144; + wire pcie_block_i_n_145; + wire pcie_block_i_n_146; + wire pcie_block_i_n_155; + wire pcie_block_i_n_156; + wire pcie_block_i_n_157; + wire pcie_block_i_n_158; + wire pcie_block_i_n_159; + wire pcie_block_i_n_160; + wire pcie_block_i_n_169; + wire pcie_block_i_n_172; + wire pcie_block_i_n_173; + wire pcie_block_i_n_174; + wire pcie_block_i_n_175; + wire pcie_block_i_n_176; + wire pcie_block_i_n_177; + wire pcie_block_i_n_178; + wire pcie_block_i_n_179; + wire pcie_block_i_n_180; + wire pcie_block_i_n_181; + wire pcie_block_i_n_182; + wire pcie_block_i_n_183; + wire pcie_block_i_n_184; + wire pcie_block_i_n_185; + wire pcie_block_i_n_186; + wire pcie_block_i_n_187; + wire pcie_block_i_n_188; + wire pcie_block_i_n_189; + wire pcie_block_i_n_190; + wire pcie_block_i_n_191; + wire pcie_block_i_n_192; + wire pcie_block_i_n_193; + wire pcie_block_i_n_194; + wire pcie_block_i_n_195; + wire pcie_block_i_n_610; + wire pcie_block_i_n_611; + wire pcie_block_i_n_618; + wire pcie_block_i_n_619; + wire pcie_block_i_n_687; + wire pcie_block_i_n_688; + wire pcie_block_i_n_689; + wire pcie_block_i_n_690; + wire pcie_block_i_n_691; + wire pcie_block_i_n_704; + wire pcie_block_i_n_705; + wire pcie_block_i_n_706; + wire pcie_block_i_n_707; + wire pcie_block_i_n_708; + wire pcie_block_i_n_709; + wire pcie_block_i_n_710; + wire pcie_block_i_n_711; + wire pcie_block_i_n_712; + wire pcie_block_i_n_713; + wire pcie_block_i_n_714; + wire pcie_block_i_n_715; + wire pcie_block_i_n_716; + wire pcie_block_i_n_717; + wire pcie_block_i_n_718; + wire pcie_block_i_n_719; + wire pcie_block_i_n_72; + wire pcie_block_i_n_720; + wire pcie_block_i_n_721; + wire pcie_block_i_n_722; + wire pcie_block_i_n_723; + wire pcie_block_i_n_724; + wire pcie_block_i_n_725; + wire pcie_block_i_n_726; + wire pcie_block_i_n_727; + wire pcie_block_i_n_728; + wire pcie_block_i_n_729; + wire pcie_block_i_n_730; + wire pcie_block_i_n_731; + wire pcie_block_i_n_732; + wire pcie_block_i_n_733; + wire pcie_block_i_n_734; + wire pcie_block_i_n_735; + wire pcie_block_i_n_736; + wire pcie_block_i_n_737; + wire pcie_block_i_n_738; + wire pcie_block_i_n_739; + wire pcie_block_i_n_740; + wire pcie_block_i_n_741; + wire pcie_block_i_n_742; + wire pcie_block_i_n_743; + wire pcie_block_i_n_744; + wire pcie_block_i_n_745; + wire pcie_block_i_n_746; + wire pcie_block_i_n_747; + wire pcie_block_i_n_748; + wire pcie_block_i_n_749; + wire pcie_block_i_n_75; + wire pcie_block_i_n_750; + wire pcie_block_i_n_751; + wire pcie_block_i_n_752; + wire pcie_block_i_n_753; + wire pcie_block_i_n_754; + wire pcie_block_i_n_755; + wire pcie_block_i_n_756; + wire pcie_block_i_n_757; + wire pcie_block_i_n_758; + wire pcie_block_i_n_759; + wire pcie_block_i_n_76; + wire pcie_block_i_n_760; + wire pcie_block_i_n_761; + wire pcie_block_i_n_762; + wire pcie_block_i_n_763; + wire pcie_block_i_n_764; + wire pcie_block_i_n_765; + wire pcie_block_i_n_766; + wire pcie_block_i_n_767; + wire pcie_block_i_n_768; + wire pcie_block_i_n_769; + wire pcie_block_i_n_77; + wire pcie_block_i_n_770; + wire pcie_block_i_n_771; + wire pcie_block_i_n_772; + wire pcie_block_i_n_773; + wire pcie_block_i_n_774; + wire pcie_block_i_n_775; + wire pcie_block_i_n_776; + wire pcie_block_i_n_777; + wire pcie_block_i_n_778; + wire pcie_block_i_n_779; + wire pcie_block_i_n_78; + wire pcie_block_i_n_780; + wire pcie_block_i_n_781; + wire pcie_block_i_n_782; + wire pcie_block_i_n_783; + wire pcie_block_i_n_784; + wire pcie_block_i_n_785; + wire pcie_block_i_n_786; + wire pcie_block_i_n_787; + wire pcie_block_i_n_788; + wire pcie_block_i_n_789; + wire pcie_block_i_n_790; + wire pcie_block_i_n_791; + wire pcie_block_i_n_792; + wire pcie_block_i_n_793; + wire pcie_block_i_n_794; + wire pcie_block_i_n_795; + wire pcie_block_i_n_796; + wire pcie_block_i_n_797; + wire pcie_block_i_n_798; + wire pcie_block_i_n_799; + wire pcie_block_i_n_800; + wire pcie_block_i_n_801; + wire pcie_block_i_n_802; + wire pcie_block_i_n_803; + wire pcie_block_i_n_804; + wire pcie_block_i_n_805; + wire pcie_block_i_n_806; + wire pcie_block_i_n_807; + wire pcie_block_i_n_808; + wire pcie_block_i_n_809; + wire pcie_block_i_n_810; + wire pcie_block_i_n_811; + wire pcie_block_i_n_812; + wire pcie_block_i_n_813; + wire pcie_block_i_n_814; + wire pcie_block_i_n_815; + wire pcie_block_i_n_816; + wire pcie_block_i_n_817; + wire pcie_block_i_n_818; + wire pcie_block_i_n_819; + wire pcie_block_i_n_820; + wire pcie_block_i_n_821; + wire pcie_block_i_n_822; + wire pcie_block_i_n_823; + wire pcie_block_i_n_824; + wire pcie_block_i_n_825; + wire pcie_block_i_n_826; + wire pcie_block_i_n_827; + wire pcie_block_i_n_828; + wire pcie_block_i_n_829; + wire pcie_block_i_n_830; + wire pcie_block_i_n_831; + wire pcie_block_i_n_832; + wire pcie_block_i_n_833; + wire pcie_block_i_n_834; + wire pcie_block_i_n_835; + wire pcie_block_i_n_836; + wire pcie_block_i_n_837; + wire pcie_block_i_n_838; + wire pcie_block_i_n_839; + wire pcie_block_i_n_84; + wire pcie_block_i_n_840; + wire pcie_block_i_n_841; + wire pcie_block_i_n_842; + wire pcie_block_i_n_843; + wire pcie_block_i_n_844; + wire pcie_block_i_n_845; + wire pcie_block_i_n_846; + wire pcie_block_i_n_847; + wire pcie_block_i_n_848; + wire pcie_block_i_n_849; + wire pcie_block_i_n_85; + wire pcie_block_i_n_850; + wire pcie_block_i_n_851; + wire pcie_block_i_n_852; + wire pcie_block_i_n_853; + wire pcie_block_i_n_854; + wire pcie_block_i_n_855; + wire pcie_block_i_n_856; + wire pcie_block_i_n_857; + wire pcie_block_i_n_858; + wire pcie_block_i_n_859; + wire pcie_block_i_n_86; + wire pcie_block_i_n_860; + wire pcie_block_i_n_861; + wire pcie_block_i_n_862; + wire pcie_block_i_n_863; + wire pcie_block_i_n_864; + wire pcie_block_i_n_865; + wire pcie_block_i_n_866; + wire pcie_block_i_n_867; + wire pcie_block_i_n_868; + wire pcie_block_i_n_869; + wire pcie_block_i_n_87; + wire pcie_block_i_n_870; + wire pcie_block_i_n_871; + wire pcie_block_i_n_872; + wire pcie_block_i_n_873; + wire pcie_block_i_n_874; + wire pcie_block_i_n_875; + wire pcie_block_i_n_876; + wire pcie_block_i_n_877; + wire pcie_block_i_n_878; + wire pcie_block_i_n_879; + wire pcie_block_i_n_88; + wire pcie_block_i_n_880; + wire pcie_block_i_n_881; + wire pcie_block_i_n_882; + wire pcie_block_i_n_883; + wire pcie_block_i_n_884; + wire pcie_block_i_n_885; + wire pcie_block_i_n_886; + wire pcie_block_i_n_887; + wire pcie_block_i_n_888; + wire pcie_block_i_n_889; + wire pcie_block_i_n_89; + wire pcie_block_i_n_890; + wire pcie_block_i_n_891; + wire pcie_block_i_n_892; + wire pcie_block_i_n_893; + wire pcie_block_i_n_894; + wire pcie_block_i_n_895; + wire pcie_block_i_n_896; + wire pcie_block_i_n_897; + wire pcie_block_i_n_898; + wire pcie_block_i_n_899; + wire pcie_block_i_n_90; + wire pcie_block_i_n_900; + wire pcie_block_i_n_901; + wire pcie_block_i_n_902; + wire pcie_block_i_n_903; + wire pcie_block_i_n_904; + wire pcie_block_i_n_905; + wire pcie_block_i_n_906; + wire pcie_block_i_n_907; + wire pcie_block_i_n_908; + wire pcie_block_i_n_909; + wire pcie_block_i_n_91; + wire pcie_block_i_n_910; + wire pcie_block_i_n_911; + wire pcie_block_i_n_912; + wire pcie_block_i_n_913; + wire pcie_block_i_n_914; + wire pcie_block_i_n_915; + wire pcie_block_i_n_916; + wire pcie_block_i_n_917; + wire pcie_block_i_n_918; + wire pcie_block_i_n_919; + wire pcie_block_i_n_92; + wire pcie_block_i_n_920; + wire pcie_block_i_n_921; + wire pcie_block_i_n_922; + wire pcie_block_i_n_923; + wire pcie_block_i_n_924; + wire pcie_block_i_n_925; + wire pcie_block_i_n_926; + wire pcie_block_i_n_927; + wire pcie_block_i_n_928; + wire pcie_block_i_n_929; + wire pcie_block_i_n_93; + wire pcie_block_i_n_930; + wire pcie_block_i_n_931; + wire pcie_block_i_n_932; + wire pcie_block_i_n_933; + wire pcie_block_i_n_934; + wire pcie_block_i_n_935; + wire pcie_block_i_n_936; + wire pcie_block_i_n_937; + wire pcie_block_i_n_938; + wire pcie_block_i_n_939; + wire pcie_block_i_n_94; + wire pcie_block_i_n_940; + wire pcie_block_i_n_941; + wire pcie_block_i_n_942; + wire pcie_block_i_n_943; + wire pcie_block_i_n_944; + wire pcie_block_i_n_945; + wire pcie_block_i_n_946; + wire pcie_block_i_n_947; + wire pcie_block_i_n_948; + wire pcie_block_i_n_949; + wire pcie_block_i_n_95; + wire pcie_block_i_n_950; + wire pcie_block_i_n_951; + wire pcie_block_i_n_952; + wire pcie_block_i_n_953; + wire pcie_block_i_n_954; + wire pcie_block_i_n_955; + wire pcie_block_i_n_956; + wire pcie_block_i_n_957; + wire pcie_block_i_n_958; + wire pcie_block_i_n_959; + wire pcie_block_i_n_96; + wire pcie_block_i_n_98; + wire pcie_block_i_n_99; + wire [8:0]pcie_drp_addr; + wire pcie_drp_clk; + wire pcie_drp_clk_0; + wire [63:0]pcie_drp_clk_1; + wire [0:0]pcie_drp_clk_2; + wire [15:0]pcie_drp_di; + wire [15:0]pcie_drp_do; + wire pcie_drp_en; + wire pcie_drp_rdy; + wire pcie_drp_we; + wire pipe_pclk_in; + wire pipe_rx0_chanisaligned; + wire pipe_rx0_elec_idle; + wire pipe_rx0_phy_status; + wire pipe_rx0_polarity; + wire pipe_rx0_valid; + wire pipe_rx1_chanisaligned; + wire pipe_rx1_elec_idle; + wire pipe_rx1_phy_status; + wire pipe_rx1_polarity; + wire pipe_rx1_valid; + wire pipe_rx2_chanisaligned; + wire pipe_rx2_elec_idle; + wire pipe_rx2_phy_status; + wire pipe_rx2_polarity; + wire pipe_rx2_valid; + wire pipe_rx3_chanisaligned; + wire pipe_rx3_elec_idle; + wire pipe_rx3_phy_status; + wire pipe_rx3_polarity; + wire pipe_rx3_valid; + wire pipe_rx4_polarity; + wire pipe_rx5_polarity; + wire pipe_rx6_polarity; + wire pipe_rx7_polarity; + wire [1:0]pipe_tx0_char_is_k; + wire pipe_tx0_compliance; + wire [15:0]pipe_tx0_data; + wire pipe_tx0_elec_idle; + wire [1:0]pipe_tx0_powerdown; + wire [1:0]pipe_tx1_char_is_k; + wire pipe_tx1_compliance; + wire [15:0]pipe_tx1_data; + wire pipe_tx1_elec_idle; + wire [1:0]pipe_tx1_powerdown; + wire [1:0]pipe_tx2_char_is_k; + wire pipe_tx2_compliance; + wire [15:0]pipe_tx2_data; + wire pipe_tx2_elec_idle; + wire [1:0]pipe_tx2_powerdown; + wire [1:0]pipe_tx3_char_is_k; + wire pipe_tx3_compliance; + wire [15:0]pipe_tx3_data; + wire pipe_tx3_elec_idle; + wire [1:0]pipe_tx3_powerdown; + wire [1:0]pipe_tx4_char_is_k; + wire pipe_tx4_compliance; + wire [15:0]pipe_tx4_data; + wire pipe_tx4_elec_idle; + wire [1:0]pipe_tx4_powerdown; + wire [1:0]pipe_tx5_char_is_k; + wire pipe_tx5_compliance; + wire [15:0]pipe_tx5_data; + wire pipe_tx5_elec_idle; + wire [1:0]pipe_tx5_powerdown; + wire [1:0]pipe_tx6_char_is_k; + wire pipe_tx6_compliance; + wire [15:0]pipe_tx6_data; + wire pipe_tx6_elec_idle; + wire [1:0]pipe_tx6_powerdown; + wire [1:0]pipe_tx7_char_is_k; + wire pipe_tx7_compliance; + wire [15:0]pipe_tx7_data; + wire pipe_tx7_elec_idle; + wire [1:0]pipe_tx7_powerdown; + wire pipe_tx_deemph; + wire [2:0]pipe_tx_margin; + wire pipe_tx_rate; + wire pipe_tx_rcvr_det; + wire pipe_userclk1_in; + wire pipe_userclk2_in; + wire pl_directed_change_done; + wire pl_directed_link_auton; + wire [1:0]pl_directed_link_change; + wire pl_directed_link_speed; + wire [1:0]pl_directed_link_width; + wire pl_downstream_deemph_source; + wire [2:0]pl_initial_link_width; + wire [1:0]pl_lane_reversal_mode; + wire pl_link_gen2_cap; + wire pl_link_partner_gen2_supported; + wire pl_link_upcfg_cap; + wire [5:0]pl_ltssm_state; + wire pl_phy_lnk_up; + wire pl_phy_lnk_up_n; + wire pl_received_hot_rst; + wire [1:0]pl_rx_pm_state; + wire pl_sel_lnk_rate; + wire [1:0]pl_sel_lnk_width; + wire pl_transmit_hot_rst; + wire [2:0]pl_tx_pm_state; + wire pl_upstream_prefer_deemph; + wire ppm_L1_thrtl; + wire ppm_L1_thrtl_reg; + wire ppm_L1_trig; + wire reg_dsc_detect; + wire reg_tcfg_gnt; + wire rsrc_rdy_filtered; + wire rx_np_ok; + wire rx_np_req; + wire src_in; + wire sys_rst_n; + wire tbuf_av_min_trig; + wire tcfg_req_trig; + wire trn_in_packet; + wire trn_in_packet_reg; + wire trn_lnk_up; + wire [6:0]trn_rbar_hit; + wire [127:64]trn_rd; + wire trn_rdst_rdy; + wire trn_recrc_err; + wire trn_reof; + wire trn_rerrfwd; + wire [1:1]trn_rrem; + wire trn_rsof; + wire trn_rsrc_dsc; + wire trn_rsrc_dsc_d; + wire trn_rsrc_dsc_prev0; + wire trn_rsrc_rdy; + wire [5:0]trn_tbuf_av; + wire trn_tcfg_gnt; + wire trn_tcfg_req; + wire [63:0]trn_td; + wire trn_tdst_rdy; + wire trn_teof; + wire [0:0]trn_trem; + wire trn_tsof; + wire trn_tsrc_rdy; + wire tx_err_drop; + wire user_reset_int_reg; + wire user_rst_n; + wire [3:1]NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED; + + LUT1 #( + .INIT(2'h1)) + \cfg_bus_number_d[7]_i_2 + (.I0(cfg_msg_received), + .O(E)); + LUT1 #( + .INIT(2'h1)) + cfg_err_aer_headerlog_set_INST_0 + (.I0(cfg_err_aer_headerlog_set_n), + .O(cfg_err_aer_headerlog_set)); + LUT1 #( + .INIT(2'h1)) + cfg_err_cpl_rdy_INST_0 + (.I0(cfg_err_cpl_rdy_n), + .O(cfg_err_cpl_rdy)); + LUT1 #( + .INIT(2'h1)) + cfg_interrupt_rdy_INST_0 + (.I0(cfg_interrupt_rdy_n), + .O(cfg_interrupt_rdy)); + LUT1 #( + .INIT(2'h1)) + cfg_mgmt_rd_wr_done_INST_0 + (.I0(cfg_mgmt_rd_wr_done_n), + .O(cfg_mgmt_rd_wr_done)); + LUT1 #( + .INIT(2'h1)) + cfg_received_func_lvl_rst_INST_0 + (.I0(cfg_received_func_lvl_rst_n), + .O(cfg_received_func_lvl_rst)); + LUT3 #( + .INIT(8'h4F)) + lnk_up_thrtl_i_1 + (.I0(trn_tdst_rdy), + .I1(lnk_up_thrtl), + .I2(out), + .O(lnk_up_thrtl_reg)); + LUT6 #( + .INIT(64'h0000000027000000)) + m_axis_rx_tvalid_i_2 + (.I0(trn_reof), + .I1(trn_rdst_rdy), + .I2(trn_rsof), + .I3(trn_rsrc_dsc), + .I4(trn_in_packet), + .I5(trn_rsrc_dsc_d), + .O(dsc_detect)); + (* BOX_TYPE = "PRIMITIVE" *) + PCIE_2_1 #( + .AER_BASE_PTR(12'h000), + .AER_CAP_ECRC_CHECK_CAPABLE("FALSE"), + .AER_CAP_ECRC_GEN_CAPABLE("FALSE"), + .AER_CAP_ID(16'h0001), + .AER_CAP_MULTIHEADER("FALSE"), + .AER_CAP_NEXTPTR(12'h000), + .AER_CAP_ON("FALSE"), + .AER_CAP_OPTIONAL_ERR_SUPPORT(24'h000000), + .AER_CAP_PERMIT_ROOTERR_UPDATE("FALSE"), + .AER_CAP_VERSION(4'h1), + .ALLOW_X8_GEN2("FALSE"), + .BAR0(32'hFFFF0000), + .BAR1(32'h00000000), + .BAR2(32'h00000000), + .BAR3(32'h00000000), + .BAR4(32'h00000000), + .BAR5(32'h00000000), + .CAPABILITIES_PTR(8'h40), + .CARDBUS_CIS_POINTER(32'h00000000), + .CFG_ECRC_ERR_CPLSTAT(0), + .CLASS_CODE(24'h050000), + .CMD_INTX_IMPLEMENTED("TRUE"), + .CPL_TIMEOUT_DISABLE_SUPPORTED("FALSE"), + .CPL_TIMEOUT_RANGES_SUPPORTED(4'h2), + .CRM_MODULE_RSTS(7'h00), + .DEV_CAP2_ARI_FORWARDING_SUPPORTED("FALSE"), + .DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED("FALSE"), + .DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED("FALSE"), + .DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED("FALSE"), + .DEV_CAP2_CAS128_COMPLETER_SUPPORTED("FALSE"), + .DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED("FALSE"), + .DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED("FALSE"), + .DEV_CAP2_LTR_MECHANISM_SUPPORTED("FALSE"), + .DEV_CAP2_MAX_ENDEND_TLP_PREFIXES(2'h0), + .DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING("FALSE"), + .DEV_CAP2_TPH_COMPLETER_SUPPORTED(2'h0), + .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE("TRUE"), + .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE("TRUE"), + .DEV_CAP_ENDPOINT_L0S_LATENCY(0), + .DEV_CAP_ENDPOINT_L1_LATENCY(7), + .DEV_CAP_EXT_TAG_SUPPORTED("FALSE"), + .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE("FALSE"), + .DEV_CAP_MAX_PAYLOAD_SUPPORTED(3), + .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT(0), + .DEV_CAP_ROLE_BASED_ERROR("TRUE"), + .DEV_CAP_RSVD_14_12(0), + .DEV_CAP_RSVD_17_16(0), + .DEV_CAP_RSVD_31_29(0), + .DEV_CONTROL_AUX_POWER_SUPPORTED("FALSE"), + .DEV_CONTROL_EXT_TAG_DEFAULT("FALSE"), + .DISABLE_ASPM_L1_TIMER("FALSE"), + .DISABLE_BAR_FILTERING("FALSE"), + .DISABLE_ERR_MSG("FALSE"), + .DISABLE_ID_CHECK("FALSE"), + .DISABLE_LANE_REVERSAL("TRUE"), + .DISABLE_LOCKED_FILTER("FALSE"), + .DISABLE_PPM_FILTER("FALSE"), + .DISABLE_RX_POISONED_RESP("FALSE"), + .DISABLE_RX_TC_FILTER("FALSE"), + .DISABLE_SCRAMBLING("FALSE"), + .DNSTREAM_LINK_NUM(8'h00), + .DSN_BASE_PTR(12'h100), + .DSN_CAP_ID(16'h0003), + .DSN_CAP_NEXTPTR(12'h000), + .DSN_CAP_ON("TRUE"), + .DSN_CAP_VERSION(4'h1), + .ENABLE_MSG_ROUTE(11'h000), + .ENABLE_RX_TD_ECRC_TRIM("FALSE"), + .ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED("FALSE"), + .ENTER_RVRY_EI_L0("TRUE"), + .EXIT_LOOPBACK_ON_EI("TRUE"), + .EXPANSION_ROM(32'h00000000), + .EXT_CFG_CAP_PTR(6'h3F), + .EXT_CFG_XP_CAP_PTR(10'h3FF), + .HEADER_TYPE(8'h00), + .INFER_EI(5'h00), + .INTERRUPT_PIN(8'h01), + .INTERRUPT_STAT_AUTO("TRUE"), + .IS_SWITCH("FALSE"), + .LAST_CONFIG_DWORD(10'h3FF), + .LINK_CAP_ASPM_OPTIONALITY("FALSE"), + .LINK_CAP_ASPM_SUPPORT(1), + .LINK_CAP_CLOCK_POWER_MANAGEMENT("FALSE"), + .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP("FALSE"), + .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1(7), + .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2(7), + .LINK_CAP_L0S_EXIT_LATENCY_GEN1(7), + .LINK_CAP_L0S_EXIT_LATENCY_GEN2(7), + .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1(7), + .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2(7), + .LINK_CAP_L1_EXIT_LATENCY_GEN1(7), + .LINK_CAP_L1_EXIT_LATENCY_GEN2(7), + .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP("FALSE"), + .LINK_CAP_MAX_LINK_SPEED(4'h2), + .LINK_CAP_MAX_LINK_WIDTH(6'h04), + .LINK_CAP_RSVD_23(0), + .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE("FALSE"), + .LINK_CONTROL_RCB(0), + .LINK_CTRL2_DEEMPHASIS("FALSE"), + .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE("FALSE"), + .LINK_CTRL2_TARGET_LINK_SPEED(4'h2), + .LINK_STATUS_SLOT_CLOCK_CONFIG("TRUE"), + .LL_ACK_TIMEOUT(15'h0000), + .LL_ACK_TIMEOUT_EN("FALSE"), + .LL_ACK_TIMEOUT_FUNC(0), + .LL_REPLAY_TIMEOUT(15'h0000), + .LL_REPLAY_TIMEOUT_EN("FALSE"), + .LL_REPLAY_TIMEOUT_FUNC(1), + .LTSSM_MAX_LINK_WIDTH(6'h04), + .MPS_FORCE("FALSE"), + .MSIX_BASE_PTR(8'h9C), + .MSIX_CAP_ID(8'h11), + .MSIX_CAP_NEXTPTR(8'h00), + .MSIX_CAP_ON("FALSE"), + .MSIX_CAP_PBA_BIR(0), + .MSIX_CAP_PBA_OFFSET(29'h00000000), + .MSIX_CAP_TABLE_BIR(0), + .MSIX_CAP_TABLE_OFFSET(29'h00000000), + .MSIX_CAP_TABLE_SIZE(11'h000), + .MSI_BASE_PTR(8'h48), + .MSI_CAP_64_BIT_ADDR_CAPABLE("TRUE"), + .MSI_CAP_ID(8'h05), + .MSI_CAP_MULTIMSGCAP(0), + .MSI_CAP_MULTIMSG_EXTENSION(0), + .MSI_CAP_NEXTPTR(8'h60), + .MSI_CAP_ON("FALSE"), + .MSI_CAP_PER_VECTOR_MASKING_CAPABLE("FALSE"), + .N_FTS_COMCLK_GEN1(255), + .N_FTS_COMCLK_GEN2(255), + .N_FTS_GEN1(255), + .N_FTS_GEN2(255), + .PCIE_BASE_PTR(8'h60), + .PCIE_CAP_CAPABILITY_ID(8'h10), + .PCIE_CAP_CAPABILITY_VERSION(4'h2), + .PCIE_CAP_DEVICE_PORT_TYPE(4'h0), + .PCIE_CAP_NEXTPTR(8'h00), + .PCIE_CAP_ON("TRUE"), + .PCIE_CAP_RSVD_15_14(0), + .PCIE_CAP_SLOT_IMPLEMENTED("FALSE"), + .PCIE_REVISION(2), + .PL_AUTO_CONFIG(0), + .PL_FAST_TRAIN("TRUE"), + .PM_ASPML0S_TIMEOUT(15'h0000), + .PM_ASPML0S_TIMEOUT_EN("FALSE"), + .PM_ASPML0S_TIMEOUT_FUNC(0), + .PM_ASPM_FASTEXIT("FALSE"), + .PM_BASE_PTR(8'h40), + .PM_CAP_AUXCURRENT(0), + .PM_CAP_D1SUPPORT("FALSE"), + .PM_CAP_D2SUPPORT("FALSE"), + .PM_CAP_DSI("FALSE"), + .PM_CAP_ID(8'h01), + .PM_CAP_NEXTPTR(8'h60), + .PM_CAP_ON("TRUE"), + .PM_CAP_PMESUPPORT(5'h0F), + .PM_CAP_PME_CLOCK("FALSE"), + .PM_CAP_RSVD_04(0), + .PM_CAP_VERSION(3), + .PM_CSR_B2B3("FALSE"), + .PM_CSR_BPCCEN("FALSE"), + .PM_CSR_NOSOFTRST("TRUE"), + .PM_DATA0(8'h00), + .PM_DATA1(8'h00), + .PM_DATA2(8'h00), + .PM_DATA3(8'h00), + .PM_DATA4(8'h00), + .PM_DATA5(8'h00), + .PM_DATA6(8'h00), + .PM_DATA7(8'h00), + .PM_DATA_SCALE0(2'h0), + .PM_DATA_SCALE1(2'h0), + .PM_DATA_SCALE2(2'h0), + .PM_DATA_SCALE3(2'h0), + .PM_DATA_SCALE4(2'h0), + .PM_DATA_SCALE5(2'h0), + .PM_DATA_SCALE6(2'h0), + .PM_DATA_SCALE7(2'h0), + .PM_MF("FALSE"), + .RBAR_BASE_PTR(12'h000), + .RBAR_CAP_CONTROL_ENCODEDBAR0(5'h00), + .RBAR_CAP_CONTROL_ENCODEDBAR1(5'h00), + .RBAR_CAP_CONTROL_ENCODEDBAR2(5'h00), + .RBAR_CAP_CONTROL_ENCODEDBAR3(5'h00), + .RBAR_CAP_CONTROL_ENCODEDBAR4(5'h00), + .RBAR_CAP_CONTROL_ENCODEDBAR5(5'h00), + .RBAR_CAP_ID(16'h0015), + .RBAR_CAP_INDEX0(3'h0), + .RBAR_CAP_INDEX1(3'h0), + .RBAR_CAP_INDEX2(3'h0), + .RBAR_CAP_INDEX3(3'h0), + .RBAR_CAP_INDEX4(3'h0), + .RBAR_CAP_INDEX5(3'h0), + .RBAR_CAP_NEXTPTR(12'h000), + .RBAR_CAP_ON("FALSE"), + .RBAR_CAP_SUP0(32'h00000001), + .RBAR_CAP_SUP1(32'h00000001), + .RBAR_CAP_SUP2(32'h00000001), + .RBAR_CAP_SUP3(32'h00000001), + .RBAR_CAP_SUP4(32'h00000001), + .RBAR_CAP_SUP5(32'h00000001), + .RBAR_CAP_VERSION(4'h1), + .RBAR_NUM(3'h0), + .RECRC_CHK(0), + .RECRC_CHK_TRIM("FALSE"), + .ROOT_CAP_CRS_SW_VISIBILITY("FALSE"), + .RP_AUTO_SPD(2'h1), + .RP_AUTO_SPD_LOOPCNT(5'h1F), + .SELECT_DLL_IF("FALSE"), + .SIM_VERSION("1.0"), + .SLOT_CAP_ATT_BUTTON_PRESENT("FALSE"), + .SLOT_CAP_ATT_INDICATOR_PRESENT("FALSE"), + .SLOT_CAP_ELEC_INTERLOCK_PRESENT("FALSE"), + .SLOT_CAP_HOTPLUG_CAPABLE("FALSE"), + .SLOT_CAP_HOTPLUG_SURPRISE("FALSE"), + .SLOT_CAP_MRL_SENSOR_PRESENT("FALSE"), + .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT("FALSE"), + .SLOT_CAP_PHYSICAL_SLOT_NUM(13'h0000), + .SLOT_CAP_POWER_CONTROLLER_PRESENT("FALSE"), + .SLOT_CAP_POWER_INDICATOR_PRESENT("FALSE"), + .SLOT_CAP_SLOT_POWER_LIMIT_SCALE(0), + .SLOT_CAP_SLOT_POWER_LIMIT_VALUE(8'h00), + .SPARE_BIT0(0), + .SPARE_BIT1(0), + .SPARE_BIT2(0), + .SPARE_BIT3(0), + .SPARE_BIT4(0), + .SPARE_BIT5(0), + .SPARE_BIT6(0), + .SPARE_BIT7(0), + .SPARE_BIT8(0), + .SPARE_BYTE0(8'h00), + .SPARE_BYTE1(8'h00), + .SPARE_BYTE2(8'h00), + .SPARE_BYTE3(8'h00), + .SPARE_WORD0(32'h00000000), + .SPARE_WORD1(32'h00000000), + .SPARE_WORD2(32'h00000000), + .SPARE_WORD3(32'h00000000), + .SSL_MESSAGE_AUTO("FALSE"), + .TECRC_EP_INV("FALSE"), + .TL_RBYPASS("FALSE"), + .TL_RX_RAM_RADDR_LATENCY(0), + .TL_RX_RAM_RDATA_LATENCY(2), + .TL_RX_RAM_WRITE_LATENCY(0), + .TL_TFC_DISABLE("FALSE"), + .TL_TX_CHECKS_DISABLE("FALSE"), + .TL_TX_RAM_RADDR_LATENCY(0), + .TL_TX_RAM_RDATA_LATENCY(2), + .TL_TX_RAM_WRITE_LATENCY(0), + .TRN_DW("FALSE"), + .TRN_NP_FC("TRUE"), + .UPCONFIG_CAPABLE("TRUE"), + .UPSTREAM_FACING("TRUE"), + .UR_ATOMIC("FALSE"), + .UR_CFG1("TRUE"), + .UR_INV_REQ("TRUE"), + .UR_PRS_RESPONSE("TRUE"), + .USER_CLK2_DIV2("FALSE"), + .USER_CLK_FREQ(3), + .USE_RID_PINS("FALSE"), + .VC0_CPL_INFINITE("TRUE"), + .VC0_RX_RAM_LIMIT(13'h0FFF), + .VC0_TOTAL_CREDITS_CD(973), + .VC0_TOTAL_CREDITS_CH(36), + .VC0_TOTAL_CREDITS_NPD(24), + .VC0_TOTAL_CREDITS_NPH(12), + .VC0_TOTAL_CREDITS_PD(949), + .VC0_TOTAL_CREDITS_PH(32), + .VC0_TX_LASTPACKET(30), + .VC_BASE_PTR(12'h000), + .VC_CAP_ID(16'h0002), + .VC_CAP_NEXTPTR(12'h000), + .VC_CAP_ON("FALSE"), + .VC_CAP_REJECT_SNOOP_TRANSACTIONS("FALSE"), + .VC_CAP_VERSION(4'h1), + .VSEC_BASE_PTR(12'h000), + .VSEC_CAP_HDR_ID(16'h1234), + .VSEC_CAP_HDR_LENGTH(12'h018), + .VSEC_CAP_HDR_REVISION(4'h1), + .VSEC_CAP_ID(16'h000B), + .VSEC_CAP_IS_LINK_VISIBLE("TRUE"), + .VSEC_CAP_NEXTPTR(12'h000), + .VSEC_CAP_ON("FALSE"), + .VSEC_CAP_VERSION(4'h1)) + pcie_block_i + (.CFGAERECRCCHECKEN(cfg_aer_ecrc_check_en), + .CFGAERECRCGENEN(cfg_aer_ecrc_gen_en), + .CFGAERINTERRUPTMSGNUM(cfg_aer_interrupt_msgnum), + .CFGAERROOTERRCORRERRRECEIVED(cfg_aer_rooterr_corr_err_received), + .CFGAERROOTERRCORRERRREPORTINGEN(cfg_aer_rooterr_corr_err_reporting_en), + .CFGAERROOTERRFATALERRRECEIVED(cfg_aer_rooterr_fatal_err_received), + .CFGAERROOTERRFATALERRREPORTINGEN(cfg_aer_rooterr_fatal_err_reporting_en), + .CFGAERROOTERRNONFATALERRRECEIVED(cfg_aer_rooterr_non_fatal_err_received), + .CFGAERROOTERRNONFATALERRREPORTINGEN(cfg_aer_rooterr_non_fatal_err_reporting_en), + .CFGBRIDGESERREN(cfg_bridge_serr_en), + .CFGCOMMANDBUSMASTERENABLE(cfg_command[2]), + .CFGCOMMANDINTERRUPTDISABLE(cfg_command[4]), + .CFGCOMMANDIOENABLE(cfg_command[0]), + .CFGCOMMANDMEMENABLE(cfg_command[1]), + .CFGCOMMANDSERREN(cfg_command[3]), + .CFGDEVCONTROL2ARIFORWARDEN(cfg_dcommand2[5]), + .CFGDEVCONTROL2ATOMICEGRESSBLOCK(cfg_dcommand2[7]), + .CFGDEVCONTROL2ATOMICREQUESTEREN(cfg_dcommand2[6]), + .CFGDEVCONTROL2CPLTIMEOUTDIS(cfg_dcommand2[4]), + .CFGDEVCONTROL2CPLTIMEOUTVAL(cfg_dcommand2[3:0]), + .CFGDEVCONTROL2IDOCPLEN(cfg_dcommand2[9]), + .CFGDEVCONTROL2IDOREQEN(cfg_dcommand2[8]), + .CFGDEVCONTROL2LTREN(cfg_dcommand2[10]), + .CFGDEVCONTROL2TLPPREFIXBLOCK(cfg_dcommand2[11]), + .CFGDEVCONTROLAUXPOWEREN(cfg_dcommand[10]), + .CFGDEVCONTROLCORRERRREPORTINGEN(cfg_dcommand[0]), + .CFGDEVCONTROLENABLERO(cfg_dcommand[4]), + .CFGDEVCONTROLEXTTAGEN(cfg_dcommand[8]), + .CFGDEVCONTROLFATALERRREPORTINGEN(cfg_dcommand[2]), + .CFGDEVCONTROLMAXPAYLOAD(cfg_dcommand[7:5]), + .CFGDEVCONTROLMAXREADREQ(cfg_dcommand[14:12]), + .CFGDEVCONTROLNONFATALREPORTINGEN(cfg_dcommand[1]), + .CFGDEVCONTROLNOSNOOPEN(cfg_dcommand[11]), + .CFGDEVCONTROLPHANTOMEN(cfg_dcommand[9]), + .CFGDEVCONTROLURERRREPORTINGEN(cfg_dcommand[3]), + .CFGDEVID({1'b0,1'b1,1'b1,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b1,1'b0,1'b0}), + .CFGDEVSTATUSCORRERRDETECTED(cfg_dstatus[0]), + .CFGDEVSTATUSFATALERRDETECTED(cfg_dstatus[2]), + .CFGDEVSTATUSNONFATALERRDETECTED(cfg_dstatus[1]), + .CFGDEVSTATUSURDETECTED(cfg_dstatus[3]), + .CFGDSBUSNUMBER(cfg_ds_bus_number), + .CFGDSDEVICENUMBER(cfg_ds_device_number), + .CFGDSFUNCTIONNUMBER(cfg_ds_function_number), + .CFGDSN(cfg_dsn), + .CFGERRACSN(1'b1), + .CFGERRAERHEADERLOG(cfg_err_aer_headerlog), + .CFGERRAERHEADERLOGSETN(cfg_err_aer_headerlog_set_n), + .CFGERRATOMICEGRESSBLOCKEDN(pcie_block_i_i_1_n_0), + .CFGERRCORN(pcie_block_i_i_2_n_0), + .CFGERRCPLABORTN(pcie_block_i_i_3_n_0), + .CFGERRCPLRDYN(cfg_err_cpl_rdy_n), + .CFGERRCPLTIMEOUTN(pcie_block_i_i_4_n_0), + .CFGERRCPLUNEXPECTN(pcie_block_i_i_5_n_0), + .CFGERRECRCN(pcie_block_i_i_6_n_0), + .CFGERRINTERNALCORN(pcie_block_i_i_7_n_0), + .CFGERRINTERNALUNCORN(pcie_block_i_i_8_n_0), + .CFGERRLOCKEDN(pcie_block_i_i_9_n_0), + .CFGERRMALFORMEDN(pcie_block_i_i_10_n_0), + .CFGERRMCBLOCKEDN(pcie_block_i_i_11_n_0), + .CFGERRNORECOVERYN(pcie_block_i_i_12_n_0), + .CFGERRPOISONEDN(pcie_block_i_i_13_n_0), + .CFGERRPOSTEDN(pcie_block_i_i_14_n_0), + .CFGERRTLPCPLHEADER(cfg_err_tlp_cpl_header), + .CFGERRURN(pcie_block_i_i_15_n_0), + .CFGFORCECOMMONCLOCKOFF(1'b0), + .CFGFORCEEXTENDEDSYNCON(1'b0), + .CFGFORCEMPS({1'b0,1'b0,1'b0}), + .CFGINTERRUPTASSERTN(pcie_block_i_i_16_n_0), + .CFGINTERRUPTDI(cfg_interrupt_di), + .CFGINTERRUPTDO(cfg_interrupt_do), + .CFGINTERRUPTMMENABLE(cfg_interrupt_mmenable), + .CFGINTERRUPTMSIENABLE(cfg_interrupt_msienable), + .CFGINTERRUPTMSIXENABLE(cfg_interrupt_msixenable), + .CFGINTERRUPTMSIXFM(cfg_interrupt_msixfm), + .CFGINTERRUPTN(pcie_block_i_i_17_n_0), + .CFGINTERRUPTRDYN(cfg_interrupt_rdy_n), + .CFGINTERRUPTSTATN(pcie_block_i_i_18_n_0), + .CFGLINKCONTROLASPMCONTROL(cfg_lcommand[1:0]), + .CFGLINKCONTROLAUTOBANDWIDTHINTEN(cfg_lcommand[10]), + .CFGLINKCONTROLBANDWIDTHINTEN(cfg_lcommand[9]), + .CFGLINKCONTROLCLOCKPMEN(cfg_lcommand[7]), + .CFGLINKCONTROLCOMMONCLOCK(cfg_lcommand[5]), + .CFGLINKCONTROLEXTENDEDSYNC(cfg_lcommand[6]), + .CFGLINKCONTROLHWAUTOWIDTHDIS(cfg_lcommand[8]), + .CFGLINKCONTROLLINKDISABLE(cfg_lcommand[3]), + .CFGLINKCONTROLRCB(cfg_lcommand[2]), + .CFGLINKCONTROLRETRAINLINK(cfg_lcommand[4]), + .CFGLINKSTATUSAUTOBANDWIDTHSTATUS(cfg_lstatus[9]), + .CFGLINKSTATUSBANDWIDTHSTATUS(cfg_lstatus[8]), + .CFGLINKSTATUSCURRENTSPEED(cfg_lstatus[1:0]), + .CFGLINKSTATUSDLLACTIVE(cfg_lstatus[7]), + .CFGLINKSTATUSLINKTRAINING(cfg_lstatus[6]), + .CFGLINKSTATUSNEGOTIATEDWIDTH(cfg_lstatus[5:2]), + .CFGMGMTBYTEENN(cfg_mgmt_byte_en_n), + .CFGMGMTDI(cfg_mgmt_di), + .CFGMGMTDO(cfg_mgmt_do), + .CFGMGMTDWADDR(cfg_mgmt_dwaddr), + .CFGMGMTRDENN(pcie_block_i_i_19_n_0), + .CFGMGMTRDWRDONEN(cfg_mgmt_rd_wr_done_n), + .CFGMGMTWRENN(pcie_block_i_i_20_n_0), + .CFGMGMTWRREADONLYN(pcie_block_i_i_21_n_0), + .CFGMGMTWRRW1CASRWN(pcie_block_i_i_22_n_0), + .CFGMSGDATA(cfg_msg_data), + .CFGMSGRECEIVED(cfg_msg_received), + .CFGMSGRECEIVEDASSERTINTA(cfg_msg_received_assert_int_a), + .CFGMSGRECEIVEDASSERTINTB(cfg_msg_received_assert_int_b), + .CFGMSGRECEIVEDASSERTINTC(cfg_msg_received_assert_int_c), + .CFGMSGRECEIVEDASSERTINTD(cfg_msg_received_assert_int_d), + .CFGMSGRECEIVEDDEASSERTINTA(cfg_msg_received_deassert_int_a), + .CFGMSGRECEIVEDDEASSERTINTB(cfg_msg_received_deassert_int_b), + .CFGMSGRECEIVEDDEASSERTINTC(cfg_msg_received_deassert_int_c), + .CFGMSGRECEIVEDDEASSERTINTD(cfg_msg_received_deassert_int_d), + .CFGMSGRECEIVEDERRCOR(cfg_msg_received_err_cor), + .CFGMSGRECEIVEDERRFATAL(cfg_msg_received_err_fatal), + .CFGMSGRECEIVEDERRNONFATAL(cfg_msg_received_err_non_fatal), + .CFGMSGRECEIVEDPMASNAK(cfg_msg_received_pm_as_nak), + .CFGMSGRECEIVEDPMETO(cfg_to_turnoff), + .CFGMSGRECEIVEDPMETOACK(cfg_msg_received_pme_to_ack), + .CFGMSGRECEIVEDPMPME(cfg_msg_received_pm_pme), + .CFGMSGRECEIVEDSETSLOTPOWERLIMIT(cfg_msg_received_setslotpowerlimit), + .CFGMSGRECEIVEDUNLOCK(pcie_block_i_n_72), + .CFGPCIECAPINTERRUPTMSGNUM(cfg_pciecap_interrupt_msgnum), + .CFGPCIELINKSTATE(cfg_pcie_link_state), + .CFGPMCSRPMEEN(cfg_pmcsr_pme_en), + .CFGPMCSRPMESTATUS(cfg_pmcsr_pme_status), + .CFGPMCSRPOWERSTATE(cfg_pmcsr_powerstate), + .CFGPMFORCESTATE(cfg_pm_force_state), + .CFGPMFORCESTATEENN(pcie_block_i_i_23_n_0), + .CFGPMHALTASPML0SN(pcie_block_i_i_24_n_0), + .CFGPMHALTASPML1N(pcie_block_i_i_25_n_0), + .CFGPMRCVASREQL1N(pcie_block_i_n_75), + .CFGPMRCVENTERL1N(pcie_block_i_n_76), + .CFGPMRCVENTERL23N(pcie_block_i_n_77), + .CFGPMRCVREQACKN(pcie_block_i_n_78), + .CFGPMSENDPMETON(1'b1), + .CFGPMTURNOFFOKN(cfg_pm_turnoff_ok_n), + .CFGPMWAKEN(pcie_block_i_i_27_n_0), + .CFGPORTNUMBER({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .CFGREVID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .CFGROOTCONTROLPMEINTEN(cfg_root_control_pme_int_en), + .CFGROOTCONTROLSYSERRCORRERREN(cfg_root_control_syserr_corr_err_en), + .CFGROOTCONTROLSYSERRFATALERREN(cfg_root_control_syserr_fatal_err_en), + .CFGROOTCONTROLSYSERRNONFATALERREN(cfg_root_control_syserr_non_fatal_err_en), + .CFGSLOTCONTROLELECTROMECHILCTLPULSE(cfg_slot_control_electromech_il_ctl_pulse), + .CFGSUBSYSID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1}), + .CFGSUBSYSVENDID({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0,1'b1,1'b1,1'b1,1'b0}), + .CFGTRANSACTION(pcie_block_i_n_84), + .CFGTRANSACTIONADDR({pcie_block_i_n_1097,pcie_block_i_n_1098,pcie_block_i_n_1099,pcie_block_i_n_1100,pcie_block_i_n_1101,pcie_block_i_n_1102,pcie_block_i_n_1103}), + .CFGTRANSACTIONTYPE(pcie_block_i_n_85), + .CFGTRNPENDINGN(pcie_block_i_i_28_n_0), + .CFGVCTCVCMAP(cfg_vc_tcvc_map), + .CFGVENDID({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0,1'b1,1'b1,1'b1,1'b0}), + .CMRSTN(1'b1), + .CMSTICKYRSTN(1'b1), + .DBGMODE({1'b0,1'b0}), + .DBGSCLRA(pcie_block_i_n_86), + .DBGSCLRB(pcie_block_i_n_87), + .DBGSCLRC(pcie_block_i_n_88), + .DBGSCLRD(pcie_block_i_n_89), + .DBGSCLRE(pcie_block_i_n_90), + .DBGSCLRF(pcie_block_i_n_91), + .DBGSCLRG(pcie_block_i_n_92), + .DBGSCLRH(pcie_block_i_n_93), + .DBGSCLRI(pcie_block_i_n_94), + .DBGSCLRJ(pcie_block_i_n_95), + .DBGSCLRK(pcie_block_i_n_96), + .DBGSUBMODE(1'b0), + .DBGVECA({pcie_block_i_n_704,pcie_block_i_n_705,pcie_block_i_n_706,pcie_block_i_n_707,pcie_block_i_n_708,pcie_block_i_n_709,pcie_block_i_n_710,pcie_block_i_n_711,pcie_block_i_n_712,pcie_block_i_n_713,pcie_block_i_n_714,pcie_block_i_n_715,pcie_block_i_n_716,pcie_block_i_n_717,pcie_block_i_n_718,pcie_block_i_n_719,pcie_block_i_n_720,pcie_block_i_n_721,pcie_block_i_n_722,pcie_block_i_n_723,pcie_block_i_n_724,pcie_block_i_n_725,pcie_block_i_n_726,pcie_block_i_n_727,pcie_block_i_n_728,pcie_block_i_n_729,pcie_block_i_n_730,pcie_block_i_n_731,pcie_block_i_n_732,pcie_block_i_n_733,pcie_block_i_n_734,pcie_block_i_n_735,pcie_block_i_n_736,pcie_block_i_n_737,pcie_block_i_n_738,pcie_block_i_n_739,pcie_block_i_n_740,pcie_block_i_n_741,pcie_block_i_n_742,pcie_block_i_n_743,pcie_block_i_n_744,pcie_block_i_n_745,pcie_block_i_n_746,pcie_block_i_n_747,pcie_block_i_n_748,pcie_block_i_n_749,pcie_block_i_n_750,pcie_block_i_n_751,pcie_block_i_n_752,pcie_block_i_n_753,pcie_block_i_n_754,pcie_block_i_n_755,pcie_block_i_n_756,pcie_block_i_n_757,pcie_block_i_n_758,pcie_block_i_n_759,pcie_block_i_n_760,pcie_block_i_n_761,pcie_block_i_n_762,pcie_block_i_n_763,pcie_block_i_n_764,pcie_block_i_n_765,pcie_block_i_n_766,pcie_block_i_n_767}), + .DBGVECB({pcie_block_i_n_768,pcie_block_i_n_769,pcie_block_i_n_770,pcie_block_i_n_771,pcie_block_i_n_772,pcie_block_i_n_773,pcie_block_i_n_774,pcie_block_i_n_775,pcie_block_i_n_776,pcie_block_i_n_777,pcie_block_i_n_778,pcie_block_i_n_779,pcie_block_i_n_780,pcie_block_i_n_781,pcie_block_i_n_782,pcie_block_i_n_783,pcie_block_i_n_784,pcie_block_i_n_785,pcie_block_i_n_786,pcie_block_i_n_787,pcie_block_i_n_788,pcie_block_i_n_789,pcie_block_i_n_790,pcie_block_i_n_791,pcie_block_i_n_792,pcie_block_i_n_793,pcie_block_i_n_794,pcie_block_i_n_795,pcie_block_i_n_796,pcie_block_i_n_797,pcie_block_i_n_798,pcie_block_i_n_799,pcie_block_i_n_800,pcie_block_i_n_801,pcie_block_i_n_802,pcie_block_i_n_803,pcie_block_i_n_804,pcie_block_i_n_805,pcie_block_i_n_806,pcie_block_i_n_807,pcie_block_i_n_808,pcie_block_i_n_809,pcie_block_i_n_810,pcie_block_i_n_811,pcie_block_i_n_812,pcie_block_i_n_813,pcie_block_i_n_814,pcie_block_i_n_815,pcie_block_i_n_816,pcie_block_i_n_817,pcie_block_i_n_818,pcie_block_i_n_819,pcie_block_i_n_820,pcie_block_i_n_821,pcie_block_i_n_822,pcie_block_i_n_823,pcie_block_i_n_824,pcie_block_i_n_825,pcie_block_i_n_826,pcie_block_i_n_827,pcie_block_i_n_828,pcie_block_i_n_829,pcie_block_i_n_830,pcie_block_i_n_831}), + .DBGVECC({pcie_block_i_n_172,pcie_block_i_n_173,pcie_block_i_n_174,pcie_block_i_n_175,pcie_block_i_n_176,pcie_block_i_n_177,pcie_block_i_n_178,pcie_block_i_n_179,pcie_block_i_n_180,pcie_block_i_n_181,pcie_block_i_n_182,pcie_block_i_n_183}), + .DLRSTN(1'b1), + .DRPADDR(pcie_drp_addr), + .DRPCLK(pcie_drp_clk), + .DRPDI(pcie_drp_di), + .DRPDO(pcie_drp_do), + .DRPEN(pcie_drp_en), + .DRPRDY(pcie_drp_rdy), + .DRPWE(pcie_drp_we), + .FUNCLVLRSTN(1'b1), + .LL2BADDLLPERR(pcie_block_i_n_98), + .LL2BADTLPERR(pcie_block_i_n_99), + .LL2LINKSTATUS({pcie_block_i_n_687,pcie_block_i_n_688,pcie_block_i_n_689,pcie_block_i_n_690,pcie_block_i_n_691}), + .LL2PROTOCOLERR(pcie_block_i_n_100), + .LL2RECEIVERERR(pcie_block_i_n_101), + .LL2REPLAYROERR(pcie_block_i_n_102), + .LL2REPLAYTOERR(pcie_block_i_n_103), + .LL2SENDASREQL1(1'b0), + .LL2SENDENTERL1(1'b0), + .LL2SENDENTERL23(1'b0), + .LL2SENDPMACK(1'b0), + .LL2SUSPENDNOW(1'b0), + .LL2SUSPENDOK(pcie_block_i_n_104), + .LL2TFCINIT1SEQ(pcie_block_i_n_105), + .LL2TFCINIT2SEQ(pcie_block_i_n_106), + .LL2TLPRCV(1'b0), + .LL2TXIDLE(pcie_block_i_n_107), + .LNKCLKEN(pcie_block_i_n_108), + .MIMRXRADDR(mim_rx_raddr), + .MIMRXRDATA(mim_rx_rdata), + .MIMRXREN(mim_rx_ren), + .MIMRXWADDR(mim_rx_waddr), + .MIMRXWDATA(mim_rx_wdata), + .MIMRXWEN(mim_rx_wen), + .MIMTXRADDR(mim_tx_raddr), + .MIMTXRDATA(mim_tx_rdata), + .MIMTXREN(mim_tx_ren), + .MIMTXWADDR(mim_tx_waddr), + .MIMTXWDATA(mim_tx_wdata), + .MIMTXWEN(mim_tx_wen), + .PIPECLK(pipe_pclk_in), + .PIPERX0CHANISALIGNED(pipe_rx0_chanisaligned), + .PIPERX0CHARISK(cfg_aer_ecrc_check_en_4), + .PIPERX0DATA(Q), + .PIPERX0ELECIDLE(pipe_rx0_elec_idle), + .PIPERX0PHYSTATUS(pipe_rx0_phy_status), + .PIPERX0POLARITY(pipe_rx0_polarity), + .PIPERX0STATUS(cfg_aer_ecrc_check_en_8), + .PIPERX0VALID(pipe_rx0_valid), + .PIPERX1CHANISALIGNED(pipe_rx1_chanisaligned), + .PIPERX1CHARISK(cfg_aer_ecrc_check_en_5), + .PIPERX1DATA(cfg_aer_ecrc_check_en_1), + .PIPERX1ELECIDLE(pipe_rx1_elec_idle), + .PIPERX1PHYSTATUS(pipe_rx1_phy_status), + .PIPERX1POLARITY(pipe_rx1_polarity), + .PIPERX1STATUS(cfg_aer_ecrc_check_en_9), + .PIPERX1VALID(pipe_rx1_valid), + .PIPERX2CHANISALIGNED(pipe_rx2_chanisaligned), + .PIPERX2CHARISK(cfg_aer_ecrc_check_en_6), + .PIPERX2DATA(cfg_aer_ecrc_check_en_2), + .PIPERX2ELECIDLE(pipe_rx2_elec_idle), + .PIPERX2PHYSTATUS(pipe_rx2_phy_status), + .PIPERX2POLARITY(pipe_rx2_polarity), + .PIPERX2STATUS(cfg_aer_ecrc_check_en_10), + .PIPERX2VALID(pipe_rx2_valid), + .PIPERX3CHANISALIGNED(pipe_rx3_chanisaligned), + .PIPERX3CHARISK(cfg_aer_ecrc_check_en_7), + .PIPERX3DATA(cfg_aer_ecrc_check_en_3), + .PIPERX3ELECIDLE(pipe_rx3_elec_idle), + .PIPERX3PHYSTATUS(pipe_rx3_phy_status), + .PIPERX3POLARITY(pipe_rx3_polarity), + .PIPERX3STATUS(cfg_aer_ecrc_check_en_11), + .PIPERX3VALID(pipe_rx3_valid), + .PIPERX4CHANISALIGNED(1'b0), + .PIPERX4CHARISK({1'b0,1'b0}), + .PIPERX4DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .PIPERX4ELECIDLE(1'b1), + .PIPERX4PHYSTATUS(1'b0), + .PIPERX4POLARITY(pipe_rx4_polarity), + .PIPERX4STATUS({1'b0,1'b0,1'b0}), + .PIPERX4VALID(1'b0), + .PIPERX5CHANISALIGNED(1'b0), + .PIPERX5CHARISK({1'b0,1'b0}), + .PIPERX5DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .PIPERX5ELECIDLE(1'b1), + .PIPERX5PHYSTATUS(1'b0), + .PIPERX5POLARITY(pipe_rx5_polarity), + .PIPERX5STATUS({1'b0,1'b0,1'b0}), + .PIPERX5VALID(1'b0), + .PIPERX6CHANISALIGNED(1'b0), + .PIPERX6CHARISK({1'b0,1'b0}), + .PIPERX6DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .PIPERX6ELECIDLE(1'b1), + .PIPERX6PHYSTATUS(1'b0), + .PIPERX6POLARITY(pipe_rx6_polarity), + .PIPERX6STATUS({1'b0,1'b0,1'b0}), + .PIPERX6VALID(1'b0), + .PIPERX7CHANISALIGNED(1'b0), + .PIPERX7CHARISK({1'b0,1'b0}), + .PIPERX7DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .PIPERX7ELECIDLE(1'b1), + .PIPERX7PHYSTATUS(1'b0), + .PIPERX7POLARITY(pipe_rx7_polarity), + .PIPERX7STATUS({1'b0,1'b0,1'b0}), + .PIPERX7VALID(1'b0), + .PIPETX0CHARISK(pipe_tx0_char_is_k), + .PIPETX0COMPLIANCE(pipe_tx0_compliance), + .PIPETX0DATA(pipe_tx0_data), + .PIPETX0ELECIDLE(pipe_tx0_elec_idle), + .PIPETX0POWERDOWN(pipe_tx0_powerdown), + .PIPETX1CHARISK(pipe_tx1_char_is_k), + .PIPETX1COMPLIANCE(pipe_tx1_compliance), + .PIPETX1DATA(pipe_tx1_data), + .PIPETX1ELECIDLE(pipe_tx1_elec_idle), + .PIPETX1POWERDOWN(pipe_tx1_powerdown), + .PIPETX2CHARISK(pipe_tx2_char_is_k), + .PIPETX2COMPLIANCE(pipe_tx2_compliance), + .PIPETX2DATA(pipe_tx2_data), + .PIPETX2ELECIDLE(pipe_tx2_elec_idle), + .PIPETX2POWERDOWN(pipe_tx2_powerdown), + .PIPETX3CHARISK(pipe_tx3_char_is_k), + .PIPETX3COMPLIANCE(pipe_tx3_compliance), + .PIPETX3DATA(pipe_tx3_data), + .PIPETX3ELECIDLE(pipe_tx3_elec_idle), + .PIPETX3POWERDOWN(pipe_tx3_powerdown), + .PIPETX4CHARISK(pipe_tx4_char_is_k), + .PIPETX4COMPLIANCE(pipe_tx4_compliance), + .PIPETX4DATA(pipe_tx4_data), + .PIPETX4ELECIDLE(pipe_tx4_elec_idle), + .PIPETX4POWERDOWN(pipe_tx4_powerdown), + .PIPETX5CHARISK(pipe_tx5_char_is_k), + .PIPETX5COMPLIANCE(pipe_tx5_compliance), + .PIPETX5DATA(pipe_tx5_data), + .PIPETX5ELECIDLE(pipe_tx5_elec_idle), + .PIPETX5POWERDOWN(pipe_tx5_powerdown), + .PIPETX6CHARISK(pipe_tx6_char_is_k), + .PIPETX6COMPLIANCE(pipe_tx6_compliance), + .PIPETX6DATA(pipe_tx6_data), + .PIPETX6ELECIDLE(pipe_tx6_elec_idle), + .PIPETX6POWERDOWN(pipe_tx6_powerdown), + .PIPETX7CHARISK(pipe_tx7_char_is_k), + .PIPETX7COMPLIANCE(pipe_tx7_compliance), + .PIPETX7DATA(pipe_tx7_data), + .PIPETX7ELECIDLE(pipe_tx7_elec_idle), + .PIPETX7POWERDOWN(pipe_tx7_powerdown), + .PIPETXDEEMPH(pipe_tx_deemph), + .PIPETXMARGIN(pipe_tx_margin), + .PIPETXRATE(pipe_tx_rate), + .PIPETXRCVRDET(pipe_tx_rcvr_det), + .PIPETXRESET(pcie_block_i_n_140), + .PL2DIRECTEDLSTATE({1'b0,1'b0,1'b0,1'b0,1'b0}), + .PL2L0REQ(pcie_block_i_n_141), + .PL2LINKUP(pcie_block_i_n_142), + .PL2RECEIVERERR(pcie_block_i_n_143), + .PL2RECOVERY(pcie_block_i_n_144), + .PL2RXELECIDLE(pcie_block_i_n_145), + .PL2RXPMSTATE({pcie_block_i_n_610,pcie_block_i_n_611}), + .PL2SUSPENDOK(pcie_block_i_n_146), + .PLDBGMODE({1'b0,1'b0,1'b0}), + .PLDBGVEC({pcie_block_i_n_184,pcie_block_i_n_185,pcie_block_i_n_186,pcie_block_i_n_187,pcie_block_i_n_188,pcie_block_i_n_189,pcie_block_i_n_190,pcie_block_i_n_191,pcie_block_i_n_192,pcie_block_i_n_193,pcie_block_i_n_194,pcie_block_i_n_195}), + .PLDIRECTEDCHANGEDONE(pl_directed_change_done), + .PLDIRECTEDLINKAUTON(pl_directed_link_auton), + .PLDIRECTEDLINKCHANGE(pl_directed_link_change), + .PLDIRECTEDLINKSPEED(pl_directed_link_speed), + .PLDIRECTEDLINKWIDTH(pl_directed_link_width), + .PLDIRECTEDLTSSMNEW({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .PLDIRECTEDLTSSMNEWVLD(1'b0), + .PLDIRECTEDLTSSMSTALL(1'b0), + .PLDOWNSTREAMDEEMPHSOURCE(pl_downstream_deemph_source), + .PLINITIALLINKWIDTH(pl_initial_link_width), + .PLLANEREVERSALMODE(pl_lane_reversal_mode), + .PLLINKGEN2CAP(pl_link_gen2_cap), + .PLLINKPARTNERGEN2SUPPORTED(pl_link_partner_gen2_supported), + .PLLINKUPCFGCAP(pl_link_upcfg_cap), + .PLLTSSMSTATE(pl_ltssm_state), + .PLPHYLNKUPN(pl_phy_lnk_up_n), + .PLRECEIVEDHOTRST(pl_received_hot_rst), + .PLRSTN(1'b1), + .PLRXPMSTATE(pl_rx_pm_state), + .PLSELLNKRATE(pl_sel_lnk_rate), + .PLSELLNKWIDTH(pl_sel_lnk_width), + .PLTRANSMITHOTRST(pl_transmit_hot_rst), + .PLTXPMSTATE(pl_tx_pm_state), + .PLUPSTREAMPREFERDEEMPH(pl_upstream_prefer_deemph), + .RECEIVEDFUNCLVLRSTN(cfg_received_func_lvl_rst_n), + .SYSRSTN(sys_rst_n), + .TL2ASPMSUSPENDCREDITCHECK(1'b0), + .TL2ASPMSUSPENDCREDITCHECKOK(pcie_block_i_n_155), + .TL2ASPMSUSPENDREQ(pcie_block_i_n_156), + .TL2ERRFCPE(pcie_block_i_n_157), + .TL2ERRHDR({pcie_block_i_n_832,pcie_block_i_n_833,pcie_block_i_n_834,pcie_block_i_n_835,pcie_block_i_n_836,pcie_block_i_n_837,pcie_block_i_n_838,pcie_block_i_n_839,pcie_block_i_n_840,pcie_block_i_n_841,pcie_block_i_n_842,pcie_block_i_n_843,pcie_block_i_n_844,pcie_block_i_n_845,pcie_block_i_n_846,pcie_block_i_n_847,pcie_block_i_n_848,pcie_block_i_n_849,pcie_block_i_n_850,pcie_block_i_n_851,pcie_block_i_n_852,pcie_block_i_n_853,pcie_block_i_n_854,pcie_block_i_n_855,pcie_block_i_n_856,pcie_block_i_n_857,pcie_block_i_n_858,pcie_block_i_n_859,pcie_block_i_n_860,pcie_block_i_n_861,pcie_block_i_n_862,pcie_block_i_n_863,pcie_block_i_n_864,pcie_block_i_n_865,pcie_block_i_n_866,pcie_block_i_n_867,pcie_block_i_n_868,pcie_block_i_n_869,pcie_block_i_n_870,pcie_block_i_n_871,pcie_block_i_n_872,pcie_block_i_n_873,pcie_block_i_n_874,pcie_block_i_n_875,pcie_block_i_n_876,pcie_block_i_n_877,pcie_block_i_n_878,pcie_block_i_n_879,pcie_block_i_n_880,pcie_block_i_n_881,pcie_block_i_n_882,pcie_block_i_n_883,pcie_block_i_n_884,pcie_block_i_n_885,pcie_block_i_n_886,pcie_block_i_n_887,pcie_block_i_n_888,pcie_block_i_n_889,pcie_block_i_n_890,pcie_block_i_n_891,pcie_block_i_n_892,pcie_block_i_n_893,pcie_block_i_n_894,pcie_block_i_n_895}), + .TL2ERRMALFORMED(pcie_block_i_n_158), + .TL2ERRRXOVERFLOW(pcie_block_i_n_159), + .TL2PPMSUSPENDOK(pcie_block_i_n_160), + .TL2PPMSUSPENDREQ(1'b0), + .TLRSTN(1'b1), + .TRNFCCPLD(fc_cpld), + .TRNFCCPLH(fc_cplh), + .TRNFCNPD(fc_npd), + .TRNFCNPH(fc_nph), + .TRNFCPD(fc_pd), + .TRNFCPH(fc_ph), + .TRNFCSEL(fc_sel), + .TRNLNKUP(trn_lnk_up), + .TRNRBARHIT({pcie_block_i_n_1143,trn_rbar_hit}), + .TRNRD({trn_rd,pcie_drp_clk_1}), + .TRNRDLLPDATA({pcie_block_i_n_896,pcie_block_i_n_897,pcie_block_i_n_898,pcie_block_i_n_899,pcie_block_i_n_900,pcie_block_i_n_901,pcie_block_i_n_902,pcie_block_i_n_903,pcie_block_i_n_904,pcie_block_i_n_905,pcie_block_i_n_906,pcie_block_i_n_907,pcie_block_i_n_908,pcie_block_i_n_909,pcie_block_i_n_910,pcie_block_i_n_911,pcie_block_i_n_912,pcie_block_i_n_913,pcie_block_i_n_914,pcie_block_i_n_915,pcie_block_i_n_916,pcie_block_i_n_917,pcie_block_i_n_918,pcie_block_i_n_919,pcie_block_i_n_920,pcie_block_i_n_921,pcie_block_i_n_922,pcie_block_i_n_923,pcie_block_i_n_924,pcie_block_i_n_925,pcie_block_i_n_926,pcie_block_i_n_927,pcie_block_i_n_928,pcie_block_i_n_929,pcie_block_i_n_930,pcie_block_i_n_931,pcie_block_i_n_932,pcie_block_i_n_933,pcie_block_i_n_934,pcie_block_i_n_935,pcie_block_i_n_936,pcie_block_i_n_937,pcie_block_i_n_938,pcie_block_i_n_939,pcie_block_i_n_940,pcie_block_i_n_941,pcie_block_i_n_942,pcie_block_i_n_943,pcie_block_i_n_944,pcie_block_i_n_945,pcie_block_i_n_946,pcie_block_i_n_947,pcie_block_i_n_948,pcie_block_i_n_949,pcie_block_i_n_950,pcie_block_i_n_951,pcie_block_i_n_952,pcie_block_i_n_953,pcie_block_i_n_954,pcie_block_i_n_955,pcie_block_i_n_956,pcie_block_i_n_957,pcie_block_i_n_958,pcie_block_i_n_959}), + .TRNRDLLPSRCRDY({pcie_block_i_n_618,pcie_block_i_n_619}), + .TRNRDSTRDY(trn_rdst_rdy), + .TRNRECRCERR(trn_recrc_err), + .TRNREOF(trn_reof), + .TRNRERRFWD(trn_rerrfwd), + .TRNRFCPRET(1'b1), + .TRNRNPOK(rx_np_ok), + .TRNRNPREQ(rx_np_req), + .TRNRREM({trn_rrem,pcie_drp_clk_2}), + .TRNRSOF(trn_rsof), + .TRNRSRCDSC(trn_rsrc_dsc), + .TRNRSRCRDY(trn_rsrc_rdy), + .TRNTBUFAV(trn_tbuf_av), + .TRNTCFGGNT(trn_tcfg_gnt), + .TRNTCFGREQ(trn_tcfg_req), + .TRNTD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,trn_td}), + .TRNTDLLPDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .TRNTDLLPDSTRDY(pcie_block_i_n_169), + .TRNTDLLPSRCRDY(1'b0), + .TRNTDSTRDY({NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED[3:1],trn_tdst_rdy}), + .TRNTECRCGEN(cfg_aer_ecrc_check_en_0[0]), + .TRNTEOF(trn_teof), + .TRNTERRDROP(tx_err_drop), + .TRNTERRFWD(cfg_aer_ecrc_check_en_0[1]), + .TRNTREM({1'b0,trn_trem}), + .TRNTSOF(trn_tsof), + .TRNTSRCDSC(cfg_aer_ecrc_check_en_0[3]), + .TRNTSRCRDY(trn_tsrc_rdy), + .TRNTSTR(cfg_aer_ecrc_check_en_0[2]), + .USERCLK(pipe_userclk1_in), + .USERCLK2(pipe_userclk2_in), + .USERRSTN(user_rst_n)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_1 + (.I0(cfg_err_atomic_egress_blocked), + .O(pcie_block_i_i_1_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_10 + (.I0(cfg_err_malformed), + .O(pcie_block_i_i_10_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_11 + (.I0(cfg_err_mc_blocked), + .O(pcie_block_i_i_11_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_12 + (.I0(cfg_err_norecovery), + .O(pcie_block_i_i_12_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_13 + (.I0(cfg_err_poisoned), + .O(pcie_block_i_i_13_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_14 + (.I0(cfg_err_posted), + .O(pcie_block_i_i_14_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_15 + (.I0(cfg_err_ur), + .O(pcie_block_i_i_15_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_16 + (.I0(cfg_interrupt_assert), + .O(pcie_block_i_i_16_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_17 + (.I0(cfg_interrupt), + .O(pcie_block_i_i_17_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_18 + (.I0(cfg_interrupt_stat), + .O(pcie_block_i_i_18_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_19 + (.I0(cfg_mgmt_rd_en), + .O(pcie_block_i_i_19_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_2 + (.I0(cfg_err_cor), + .O(pcie_block_i_i_2_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_20 + (.I0(cfg_mgmt_wr_en), + .O(pcie_block_i_i_20_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_21 + (.I0(cfg_mgmt_wr_readonly), + .O(pcie_block_i_i_21_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_22 + (.I0(cfg_mgmt_wr_rw1c_as_rw), + .O(pcie_block_i_i_22_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_23 + (.I0(cfg_pm_force_state_en), + .O(pcie_block_i_i_23_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_24 + (.I0(cfg_pm_halt_aspm_l0s), + .O(pcie_block_i_i_24_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_25 + (.I0(cfg_pm_halt_aspm_l1), + .O(pcie_block_i_i_25_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_27 + (.I0(cfg_pm_wake), + .O(pcie_block_i_i_27_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_28 + (.I0(cfg_trn_pending), + .O(pcie_block_i_i_28_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_3 + (.I0(cfg_err_cpl_abort), + .O(pcie_block_i_i_3_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_4 + (.I0(cfg_err_cpl_timeout), + .O(pcie_block_i_i_4_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_5 + (.I0(cfg_err_cpl_unexpect), + .O(pcie_block_i_i_5_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_6 + (.I0(cfg_err_ecrc), + .O(pcie_block_i_i_6_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_7 + (.I0(cfg_err_internal_cor), + .O(pcie_block_i_i_7_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_8 + (.I0(cfg_err_internal_uncor), + .O(pcie_block_i_i_8_n_0)); + LUT1 #( + .INIT(2'h1)) + pcie_block_i_i_9 + (.I0(cfg_err_locked), + .O(pcie_block_i_i_9_n_0)); + pcie_7x_0_pcie_7x_0_pcie_bram_top_7x pcie_bram_top + (.MIMRXRADDR(mim_rx_raddr[11:0]), + .MIMRXWADDR(mim_rx_waddr[11:0]), + .MIMTXRADDR(mim_tx_raddr[11:0]), + .MIMTXWADDR(mim_tx_waddr[11:0]), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (mim_rx_rdata), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (mim_rx_wdata), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(mim_tx_rdata), + .wdata(mim_tx_wdata)); + LUT1 #( + .INIT(2'h1)) + phy_lnk_up_cdc_i_1 + (.I0(pl_phy_lnk_up_n), + .O(src_in)); + LUT5 #( + .INIT(32'hFFFEAAAA)) + ppm_L1_thrtl_i_1 + (.I0(ppm_L1_trig), + .I1(cfg_pcie_link_state[0]), + .I2(cfg_pcie_link_state[2]), + .I3(cfg_pcie_link_state[1]), + .I4(ppm_L1_thrtl), + .O(ppm_L1_thrtl_reg)); + LUT5 #( + .INIT(32'h00000001)) + tbuf_av_min_thrtl_i_1 + (.I0(trn_tbuf_av[5]), + .I1(trn_tbuf_av[4]), + .I2(trn_tbuf_av[3]), + .I3(trn_tbuf_av[2]), + .I4(trn_tbuf_av[1]), + .O(tbuf_av_min_trig)); + LUT6 #( + .INIT(64'h0000000100010001)) + tready_thrtl_i_11 + (.I0(trn_tbuf_av[5]), + .I1(trn_tbuf_av[4]), + .I2(trn_tbuf_av[3]), + .I3(trn_tbuf_av[2]), + .I4(trn_tbuf_av[0]), + .I5(trn_tbuf_av[1]), + .O(pcie_drp_clk_0)); + LUT2 #( + .INIT(4'h8)) + tready_thrtl_i_9 + (.I0(trn_tcfg_req), + .I1(reg_tcfg_gnt), + .O(tcfg_req_trig)); + LUT6 #( + .INIT(64'h08000000AEAA2AAA)) + trn_in_packet_i_1 + (.I0(trn_in_packet), + .I1(trn_rdst_rdy), + .I2(trn_reof), + .I3(trn_rsrc_rdy), + .I4(trn_rsof), + .I5(trn_rsrc_dsc), + .O(trn_in_packet_reg)); + (* SOFT_HLUTNM = "soft_lutpair256" *) + LUT2 #( + .INIT(4'hE)) + trn_rsrc_dsc_prev_i_1 + (.I0(trn_rsrc_dsc), + .I1(reg_dsc_detect), + .O(trn_rsrc_dsc_prev0)); + (* SOFT_HLUTNM = "soft_lutpair256" *) + LUT4 #( + .INIT(16'hAA08)) + trn_rsrc_rdy_prev_i_1 + (.I0(trn_rsrc_rdy), + .I1(trn_rsof), + .I2(trn_rsrc_dsc), + .I3(trn_in_packet), + .O(rsrc_rdy_filtered)); + LUT3 #( + .INIT(8'h2A)) + user_reset_int_i_1 + (.I0(bridge_reset_int), + .I1(pl_phy_lnk_up), + .I2(user_rst_n), + .O(user_reset_int_reg)); +endmodule + +module pcie_7x_0_pcie_7x_0_pcie_bram_7x + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + + pcie_7x_0_BRAM_TDP_MACRO_17 \use_tdp.ramb36 + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata), + .wdata(wdata)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_10 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [5:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [5:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [5:0]rdata; + wire [5:0]wdata; + + pcie_7x_0_BRAM_TDP_MACRO_viv_ \use_tdp.ramb36 + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata), + .wdata(wdata)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_18 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + + pcie_7x_0_BRAM_TDP_MACRO_33 \use_tdp.ramb36 + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_19 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + + pcie_7x_0_BRAM_TDP_MACRO_32 \use_tdp.ramb36 + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_20 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + + pcie_7x_0_BRAM_TDP_MACRO_31 \use_tdp.ramb36 + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_21 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + + pcie_7x_0_BRAM_TDP_MACRO_30 \use_tdp.ramb36 + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_22 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + + pcie_7x_0_BRAM_TDP_MACRO_29 \use_tdp.ramb36 + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_23 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + + pcie_7x_0_BRAM_TDP_MACRO_28 \use_tdp.ramb36 + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_24 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ); + output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + + pcie_7x_0_BRAM_TDP_MACRO_27 \use_tdp.ramb36 + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_25 + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ); + output [4:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [4:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [4:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + wire [4:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + + pcie_7x_0_BRAM_TDP_MACRO_26 \use_tdp.ramb36 + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_4 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + + pcie_7x_0_BRAM_TDP_MACRO_16 \use_tdp.ramb36 + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata), + .wdata(wdata)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_5 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + + pcie_7x_0_BRAM_TDP_MACRO_15 \use_tdp.ramb36 + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata), + .wdata(wdata)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_6 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + + pcie_7x_0_BRAM_TDP_MACRO_14 \use_tdp.ramb36 + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata), + .wdata(wdata)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_7 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + + pcie_7x_0_BRAM_TDP_MACRO_13 \use_tdp.ramb36 + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata), + .wdata(wdata)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_8 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + + pcie_7x_0_BRAM_TDP_MACRO_12 \use_tdp.ramb36 + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata), + .wdata(wdata)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_bram_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_bram_7x_9 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [8:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [8:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [8:0]rdata; + wire [8:0]wdata; + + pcie_7x_0_BRAM_TDP_MACRO_11 \use_tdp.ramb36 + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata), + .wdata(wdata)); +endmodule + +module pcie_7x_0_pcie_7x_0_pcie_bram_top_7x + (rdata, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl , + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ); + output [68:0]rdata; + output [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [68:0]wdata; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + wire [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [68:0]rdata; + wire [68:0]wdata; + + pcie_7x_0_pcie_7x_0_pcie_brams_7x pcie_brams_rx + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); + pcie_7x_0_pcie_7x_0_pcie_brams_7x_3 pcie_brams_tx + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata), + .wdata(wdata)); +endmodule + +module pcie_7x_0_pcie_7x_0_pcie_brams_7x + (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl , + pipe_userclk1_in, + mim_rx_wen, + mim_rx_ren, + MIMRXWADDR, + MIMRXRADDR, + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ); + output [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + input pipe_userclk1_in; + input mim_rx_wen; + input mim_rx_ren; + input [11:0]MIMRXWADDR; + input [11:0]MIMRXRADDR; + input [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + + wire [11:0]MIMRXRADDR; + wire [11:0]MIMRXWADDR; + wire [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ; + wire [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ; + wire mim_rx_ren; + wire mim_rx_wen; + wire pipe_userclk1_in; + + pcie_7x_0_pcie_7x_0_pcie_bram_7x_18 \brams[0].ram + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl [8:0]), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8:0]), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_19 \brams[1].ram + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl [17:9]), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [17:9]), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_20 \brams[2].ram + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl [26:18]), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [26:18]), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_21 \brams[3].ram + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl [35:27]), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [35:27]), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_22 \brams[4].ram + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl [44:36]), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [44:36]), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_23 \brams[5].ram + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl [53:45]), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [53:45]), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_24 \brams[6].ram + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl [62:54]), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [62:54]), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_25 \brams[7].ram + (.MIMRXRADDR(MIMRXRADDR), + .MIMRXWADDR(MIMRXWADDR), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl [67:63]), + .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [67:63]), + .mim_rx_ren(mim_rx_ren), + .mim_rx_wen(mim_rx_wen), + .pipe_userclk1_in(pipe_userclk1_in)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_brams_7x" *) +module pcie_7x_0_pcie_7x_0_pcie_brams_7x_3 + (rdata, + pipe_userclk1_in, + mim_tx_wen, + mim_tx_ren, + MIMTXWADDR, + MIMTXRADDR, + wdata); + output [68:0]rdata; + input pipe_userclk1_in; + input mim_tx_wen; + input mim_tx_ren; + input [11:0]MIMTXWADDR; + input [11:0]MIMTXRADDR; + input [68:0]wdata; + + wire [11:0]MIMTXRADDR; + wire [11:0]MIMTXWADDR; + wire mim_tx_ren; + wire mim_tx_wen; + wire pipe_userclk1_in; + wire [68:0]rdata; + wire [68:0]wdata; + + pcie_7x_0_pcie_7x_0_pcie_bram_7x \brams[0].ram + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata[8:0]), + .wdata(wdata[8:0])); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_4 \brams[1].ram + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata[17:9]), + .wdata(wdata[17:9])); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_5 \brams[2].ram + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata[26:18]), + .wdata(wdata[26:18])); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_6 \brams[3].ram + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata[35:27]), + .wdata(wdata[35:27])); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_7 \brams[4].ram + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata[44:36]), + .wdata(wdata[44:36])); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_8 \brams[5].ram + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata[53:45]), + .wdata(wdata[53:45])); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_9 \brams[6].ram + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata[62:54]), + .wdata(wdata[62:54])); + pcie_7x_0_pcie_7x_0_pcie_bram_7x_10 \brams[7].ram + (.MIMTXRADDR(MIMTXRADDR), + .MIMTXWADDR(MIMTXWADDR), + .mim_tx_ren(mim_tx_ren), + .mim_tx_wen(mim_tx_wen), + .pipe_userclk1_in(pipe_userclk1_in), + .rdata(rdata[68:63]), + .wdata(wdata[68:63])); +endmodule + +module pcie_7x_0_pcie_7x_0_pcie_pipe_lane + (pipe_rx1_valid, + pipe_rx1_chanisaligned, + pipe_rx1_phy_status, + pipe_rx1_elec_idle, + PIPE_RXPOLARITY, + PIPE_TXCOMPLIANCE, + PIPE_TXELECIDLE, + Q, + \pipe_stages_1.pipe_rx_data_q_reg[15]_0 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_0 , + PIPE_TXDATAK, + PIPE_TXDATA, + PIPE_POWERDOWN, + SR, + pipe_rx1_valid_gt, + pipe_pclk_in, + PIPE_RXCHANISALIGNED, + \pipe_stages_1.pipe_rx_phy_status_q_reg_0 , + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 , + pipe_rx1_polarity, + pipe_tx1_compliance, + pipe_tx1_elec_idle, + D, + \pipe_stages_1.pipe_rx_data_q_reg[15]_1 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_1 , + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 , + \pipe_stages_1.pipe_tx_data_q_reg[15]_0 , + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ); + output pipe_rx1_valid; + output pipe_rx1_chanisaligned; + output pipe_rx1_phy_status; + output pipe_rx1_elec_idle; + output [0:0]PIPE_RXPOLARITY; + output [0:0]PIPE_TXCOMPLIANCE; + output [0:0]PIPE_TXELECIDLE; + output [1:0]Q; + output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ; + output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ; + output [1:0]PIPE_TXDATAK; + output [15:0]PIPE_TXDATA; + output [1:0]PIPE_POWERDOWN; + input [0:0]SR; + input pipe_rx1_valid_gt; + input pipe_pclk_in; + input [0:0]PIPE_RXCHANISALIGNED; + input \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ; + input \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ; + input pipe_rx1_polarity; + input pipe_tx1_compliance; + input pipe_tx1_elec_idle; + input [1:0]D; + input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ; + input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ; + input [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ; + input [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ; + input [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ; + + wire [1:0]D; + wire [1:0]PIPE_POWERDOWN; + wire [0:0]PIPE_RXCHANISALIGNED; + wire [0:0]PIPE_RXPOLARITY; + wire [0:0]PIPE_TXCOMPLIANCE; + wire [15:0]PIPE_TXDATA; + wire [1:0]PIPE_TXDATAK; + wire [0:0]PIPE_TXELECIDLE; + wire [1:0]Q; + wire [0:0]SR; + wire pipe_pclk_in; + wire pipe_rx1_chanisaligned; + wire pipe_rx1_elec_idle; + wire pipe_rx1_phy_status; + wire pipe_rx1_polarity; + wire pipe_rx1_valid; + wire pipe_rx1_valid_gt; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ; + wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ; + wire \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ; + wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ; + wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ; + wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ; + wire pipe_tx1_compliance; + wire pipe_tx1_elec_idle; + + FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXCHANISALIGNED), + .Q(pipe_rx1_chanisaligned), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(D[0]), + .Q(Q[0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(D[1]), + .Q(Q[1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [0]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [10]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [10]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [11]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [11]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [12]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [12]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [13]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [13]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [14]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [14]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [15]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [15]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [1]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [2]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [2]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [3]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [3]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [4]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [4]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [5]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [5]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [6]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [6]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [7]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [7]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [8]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [8]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [9]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [9]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ), + .Q(pipe_rx1_elec_idle), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_phy_status_q_reg_0 ), + .Q(pipe_rx1_phy_status), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_polarity_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_rx1_polarity), + .Q(PIPE_RXPOLARITY), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [0]), + .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [1]), + .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [2]), + .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [2]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_valid_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_rx1_valid_gt), + .Q(pipe_rx1_valid), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 [0]), + .Q(PIPE_TXDATAK[0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 [1]), + .Q(PIPE_TXDATAK[1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_compliance_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_tx1_compliance), + .Q(PIPE_TXCOMPLIANCE), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [0]), + .Q(PIPE_TXDATA[0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [10]), + .Q(PIPE_TXDATA[10]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [11]), + .Q(PIPE_TXDATA[11]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [12]), + .Q(PIPE_TXDATA[12]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [13]), + .Q(PIPE_TXDATA[13]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [14]), + .Q(PIPE_TXDATA[14]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [15]), + .Q(PIPE_TXDATA[15]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [1]), + .Q(PIPE_TXDATA[1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [2]), + .Q(PIPE_TXDATA[2]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [3]), + .Q(PIPE_TXDATA[3]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [4]), + .Q(PIPE_TXDATA[4]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [5]), + .Q(PIPE_TXDATA[5]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [6]), + .Q(PIPE_TXDATA[6]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [7]), + .Q(PIPE_TXDATA[7]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [8]), + .Q(PIPE_TXDATA[8]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [9]), + .Q(PIPE_TXDATA[9]), + .R(SR)); + FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_tx1_elec_idle), + .Q(PIPE_TXELECIDLE), + .S(SR)); + FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 [0]), + .Q(PIPE_POWERDOWN[0]), + .R(SR)); + FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 [1]), + .Q(PIPE_POWERDOWN[1]), + .S(SR)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_pipe_lane" *) +module pcie_7x_0_pcie_7x_0_pcie_pipe_lane_0 + (PIPE_RXPOLARITY, + PIPE_TXCOMPLIANCE, + PIPE_TXELECIDLE, + pipe_rx2_valid, + pipe_rx2_chanisaligned, + pipe_rx2_phy_status, + pipe_rx2_elec_idle, + PIPE_TXDATAK, + PIPE_TXDATA, + PIPE_POWERDOWN, + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 , + \pipe_stages_1.pipe_rx_data_q_reg[15]_0 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_0 , + SR, + pipe_rx2_polarity, + pipe_pclk_in, + pipe_tx2_compliance, + pipe_tx2_elec_idle, + pipe_rx2_valid_gt, + PIPE_RXCHANISALIGNED, + \pipe_stages_1.pipe_rx_phy_status_q_reg_0 , + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 , + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 , + \pipe_stages_1.pipe_tx_data_q_reg[15]_0 , + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 , + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 , + \pipe_stages_1.pipe_rx_data_q_reg[15]_1 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_1 ); + output [0:0]PIPE_RXPOLARITY; + output [0:0]PIPE_TXCOMPLIANCE; + output [0:0]PIPE_TXELECIDLE; + output pipe_rx2_valid; + output pipe_rx2_chanisaligned; + output pipe_rx2_phy_status; + output pipe_rx2_elec_idle; + output [1:0]PIPE_TXDATAK; + output [15:0]PIPE_TXDATA; + output [1:0]PIPE_POWERDOWN; + output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ; + output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ; + output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ; + input [0:0]SR; + input pipe_rx2_polarity; + input pipe_pclk_in; + input pipe_tx2_compliance; + input pipe_tx2_elec_idle; + input pipe_rx2_valid_gt; + input [0:0]PIPE_RXCHANISALIGNED; + input \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ; + input \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ; + input [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ; + input [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ; + input [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ; + input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ; + input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ; + input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ; + + wire [1:0]PIPE_POWERDOWN; + wire [0:0]PIPE_RXCHANISALIGNED; + wire [0:0]PIPE_RXPOLARITY; + wire [0:0]PIPE_TXCOMPLIANCE; + wire [15:0]PIPE_TXDATA; + wire [1:0]PIPE_TXDATAK; + wire [0:0]PIPE_TXELECIDLE; + wire [0:0]SR; + wire pipe_pclk_in; + wire pipe_rx2_chanisaligned; + wire pipe_rx2_elec_idle; + wire pipe_rx2_phy_status; + wire pipe_rx2_polarity; + wire pipe_rx2_valid; + wire pipe_rx2_valid_gt; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ; + wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ; + wire \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ; + wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ; + wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ; + wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ; + wire pipe_tx2_compliance; + wire pipe_tx2_elec_idle; + + FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXCHANISALIGNED), + .Q(pipe_rx2_chanisaligned), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 [0]), + .Q(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 [0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 [1]), + .Q(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 [1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [0]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [10]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [10]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [11]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [11]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [12]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [12]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [13]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [13]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [14]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [14]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [15]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [15]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [1]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [2]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [2]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [3]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [3]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [4]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [4]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [5]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [5]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [6]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [6]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [7]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [7]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [8]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [8]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [9]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [9]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ), + .Q(pipe_rx2_elec_idle), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_phy_status_q_reg_0 ), + .Q(pipe_rx2_phy_status), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_polarity_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_rx2_polarity), + .Q(PIPE_RXPOLARITY), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [0]), + .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [1]), + .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [2]), + .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [2]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_valid_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_rx2_valid_gt), + .Q(pipe_rx2_valid), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 [0]), + .Q(PIPE_TXDATAK[0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 [1]), + .Q(PIPE_TXDATAK[1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_compliance_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_tx2_compliance), + .Q(PIPE_TXCOMPLIANCE), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [0]), + .Q(PIPE_TXDATA[0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [10]), + .Q(PIPE_TXDATA[10]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [11]), + .Q(PIPE_TXDATA[11]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [12]), + .Q(PIPE_TXDATA[12]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [13]), + .Q(PIPE_TXDATA[13]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [14]), + .Q(PIPE_TXDATA[14]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [15]), + .Q(PIPE_TXDATA[15]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [1]), + .Q(PIPE_TXDATA[1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [2]), + .Q(PIPE_TXDATA[2]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [3]), + .Q(PIPE_TXDATA[3]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [4]), + .Q(PIPE_TXDATA[4]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [5]), + .Q(PIPE_TXDATA[5]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [6]), + .Q(PIPE_TXDATA[6]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [7]), + .Q(PIPE_TXDATA[7]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [8]), + .Q(PIPE_TXDATA[8]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [9]), + .Q(PIPE_TXDATA[9]), + .R(SR)); + FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_tx2_elec_idle), + .Q(PIPE_TXELECIDLE), + .S(SR)); + FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 [0]), + .Q(PIPE_POWERDOWN[0]), + .R(SR)); + FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 [1]), + .Q(PIPE_POWERDOWN[1]), + .S(SR)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_pipe_lane" *) +module pcie_7x_0_pcie_7x_0_pcie_pipe_lane_1 + (PIPE_RXPOLARITY, + PIPE_TXCOMPLIANCE, + PIPE_TXELECIDLE, + pipe_rx3_valid, + pipe_rx3_chanisaligned, + pipe_rx3_phy_status, + pipe_rx3_elec_idle, + PIPE_TXDATAK, + PIPE_TXDATA, + PIPE_POWERDOWN, + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 , + \pipe_stages_1.pipe_rx_data_q_reg[15]_0 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_0 , + SR, + pipe_rx3_polarity, + pipe_pclk_in, + pipe_tx3_compliance, + pipe_tx3_elec_idle, + pipe_rx3_valid_gt, + PIPE_RXCHANISALIGNED, + \pipe_stages_1.pipe_rx_phy_status_q_reg_0 , + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 , + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 , + \pipe_stages_1.pipe_tx_data_q_reg[15]_0 , + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 , + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 , + \pipe_stages_1.pipe_rx_data_q_reg[15]_1 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_1 ); + output [0:0]PIPE_RXPOLARITY; + output [0:0]PIPE_TXCOMPLIANCE; + output [0:0]PIPE_TXELECIDLE; + output pipe_rx3_valid; + output pipe_rx3_chanisaligned; + output pipe_rx3_phy_status; + output pipe_rx3_elec_idle; + output [1:0]PIPE_TXDATAK; + output [15:0]PIPE_TXDATA; + output [1:0]PIPE_POWERDOWN; + output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ; + output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ; + output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ; + input [0:0]SR; + input pipe_rx3_polarity; + input pipe_pclk_in; + input pipe_tx3_compliance; + input pipe_tx3_elec_idle; + input pipe_rx3_valid_gt; + input [0:0]PIPE_RXCHANISALIGNED; + input \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ; + input \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ; + input [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ; + input [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ; + input [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ; + input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ; + input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ; + input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ; + + wire [1:0]PIPE_POWERDOWN; + wire [0:0]PIPE_RXCHANISALIGNED; + wire [0:0]PIPE_RXPOLARITY; + wire [0:0]PIPE_TXCOMPLIANCE; + wire [15:0]PIPE_TXDATA; + wire [1:0]PIPE_TXDATAK; + wire [0:0]PIPE_TXELECIDLE; + wire [0:0]SR; + wire pipe_pclk_in; + wire pipe_rx3_chanisaligned; + wire pipe_rx3_elec_idle; + wire pipe_rx3_phy_status; + wire pipe_rx3_polarity; + wire pipe_rx3_valid; + wire pipe_rx3_valid_gt; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ; + wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ; + wire \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ; + wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ; + wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ; + wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ; + wire pipe_tx3_compliance; + wire pipe_tx3_elec_idle; + + FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXCHANISALIGNED), + .Q(pipe_rx3_chanisaligned), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 [0]), + .Q(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 [0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 [1]), + .Q(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 [1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [0]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [10]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [10]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [11]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [11]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [12]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [12]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [13]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [13]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [14]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [14]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [15]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [15]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [1]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [2]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [2]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [3]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [3]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [4]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [4]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [5]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [5]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [6]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [6]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [7]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [7]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [8]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [8]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [9]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [9]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ), + .Q(pipe_rx3_elec_idle), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_phy_status_q_reg_0 ), + .Q(pipe_rx3_phy_status), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_polarity_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_rx3_polarity), + .Q(PIPE_RXPOLARITY), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [0]), + .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [1]), + .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [2]), + .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [2]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_valid_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_rx3_valid_gt), + .Q(pipe_rx3_valid), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 [0]), + .Q(PIPE_TXDATAK[0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 [1]), + .Q(PIPE_TXDATAK[1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_compliance_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_tx3_compliance), + .Q(PIPE_TXCOMPLIANCE), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [0]), + .Q(PIPE_TXDATA[0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [10]), + .Q(PIPE_TXDATA[10]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [11]), + .Q(PIPE_TXDATA[11]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [12]), + .Q(PIPE_TXDATA[12]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [13]), + .Q(PIPE_TXDATA[13]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [14]), + .Q(PIPE_TXDATA[14]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [15]), + .Q(PIPE_TXDATA[15]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [1]), + .Q(PIPE_TXDATA[1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [2]), + .Q(PIPE_TXDATA[2]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [3]), + .Q(PIPE_TXDATA[3]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [4]), + .Q(PIPE_TXDATA[4]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [5]), + .Q(PIPE_TXDATA[5]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [6]), + .Q(PIPE_TXDATA[6]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [7]), + .Q(PIPE_TXDATA[7]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [8]), + .Q(PIPE_TXDATA[8]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [9]), + .Q(PIPE_TXDATA[9]), + .R(SR)); + FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_tx3_elec_idle), + .Q(PIPE_TXELECIDLE), + .S(SR)); + FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 [0]), + .Q(PIPE_POWERDOWN[0]), + .R(SR)); + FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 [1]), + .Q(PIPE_POWERDOWN[1]), + .S(SR)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pcie_pipe_lane" *) +module pcie_7x_0_pcie_7x_0_pcie_pipe_lane_2 + (PIPE_RXPOLARITY, + PIPE_TXCOMPLIANCE, + PIPE_TXELECIDLE, + pipe_rx0_valid, + pipe_rx0_chanisaligned, + pipe_rx0_phy_status, + pipe_rx0_elec_idle, + PIPE_TXDATAK, + PIPE_TXDATA, + PIPE_POWERDOWN, + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 , + \pipe_stages_1.pipe_rx_data_q_reg[15]_0 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_0 , + SR, + pipe_rx0_polarity, + pipe_pclk_in, + pipe_tx0_compliance, + pipe_tx0_elec_idle, + pipe_rx0_valid_gt, + PIPE_RXCHANISALIGNED, + gt_rx_phy_status_q, + gt_rxelecidle_q, + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 , + \pipe_stages_1.pipe_tx_data_q_reg[15]_0 , + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 , + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 , + \pipe_stages_1.pipe_rx_data_q_reg[15]_1 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_1 ); + output [0:0]PIPE_RXPOLARITY; + output [0:0]PIPE_TXCOMPLIANCE; + output [0:0]PIPE_TXELECIDLE; + output pipe_rx0_valid; + output pipe_rx0_chanisaligned; + output pipe_rx0_phy_status; + output pipe_rx0_elec_idle; + output [1:0]PIPE_TXDATAK; + output [15:0]PIPE_TXDATA; + output [1:0]PIPE_POWERDOWN; + output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ; + output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ; + output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ; + input [0:0]SR; + input pipe_rx0_polarity; + input pipe_pclk_in; + input pipe_tx0_compliance; + input pipe_tx0_elec_idle; + input pipe_rx0_valid_gt; + input [0:0]PIPE_RXCHANISALIGNED; + input gt_rx_phy_status_q; + input gt_rxelecidle_q; + input [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ; + input [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ; + input [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ; + input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ; + input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ; + input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ; + + wire [1:0]PIPE_POWERDOWN; + wire [0:0]PIPE_RXCHANISALIGNED; + wire [0:0]PIPE_RXPOLARITY; + wire [0:0]PIPE_TXCOMPLIANCE; + wire [15:0]PIPE_TXDATA; + wire [1:0]PIPE_TXDATAK; + wire [0:0]PIPE_TXELECIDLE; + wire [0:0]SR; + wire gt_rx_phy_status_q; + wire gt_rxelecidle_q; + wire pipe_pclk_in; + wire pipe_rx0_chanisaligned; + wire pipe_rx0_elec_idle; + wire pipe_rx0_phy_status; + wire pipe_rx0_polarity; + wire pipe_rx0_valid; + wire pipe_rx0_valid_gt; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ; + wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ; + wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ; + wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ; + wire pipe_tx0_compliance; + wire pipe_tx0_elec_idle; + + FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_RXCHANISALIGNED), + .Q(pipe_rx0_chanisaligned), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 [0]), + .Q(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 [0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 [1]), + .Q(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 [1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [0]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [10]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [10]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [11]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [11]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [12]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [12]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [13]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [13]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [14]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [14]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [15]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [15]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [1]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [2]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [2]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [3]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [3]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [4]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [4]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [5]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [5]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [6]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [6]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [7]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [7]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [8]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [8]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [9]), + .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [9]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rxelecidle_q), + .Q(pipe_rx0_elec_idle), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rx_phy_status_q), + .Q(pipe_rx0_phy_status), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_polarity_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_rx0_polarity), + .Q(PIPE_RXPOLARITY), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [0]), + .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [1]), + .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [2]), + .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [2]), + .R(SR)); + FDRE \pipe_stages_1.pipe_rx_valid_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_rx0_valid_gt), + .Q(pipe_rx0_valid), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 [0]), + .Q(PIPE_TXDATAK[0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 [1]), + .Q(PIPE_TXDATAK[1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_compliance_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_tx0_compliance), + .Q(PIPE_TXCOMPLIANCE), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [0]), + .Q(PIPE_TXDATA[0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [10]), + .Q(PIPE_TXDATA[10]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [11]), + .Q(PIPE_TXDATA[11]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [12]), + .Q(PIPE_TXDATA[12]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [13]), + .Q(PIPE_TXDATA[13]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [14]), + .Q(PIPE_TXDATA[14]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [15]), + .Q(PIPE_TXDATA[15]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [1]), + .Q(PIPE_TXDATA[1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [2]), + .Q(PIPE_TXDATA[2]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [3]), + .Q(PIPE_TXDATA[3]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [4]), + .Q(PIPE_TXDATA[4]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [5]), + .Q(PIPE_TXDATA[5]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [6]), + .Q(PIPE_TXDATA[6]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [7]), + .Q(PIPE_TXDATA[7]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [8]), + .Q(PIPE_TXDATA[8]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [9]), + .Q(PIPE_TXDATA[9]), + .R(SR)); + FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_tx0_elec_idle), + .Q(PIPE_TXELECIDLE), + .S(SR)); + FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 [0]), + .Q(PIPE_POWERDOWN[0]), + .R(SR)); + FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 [1]), + .Q(PIPE_POWERDOWN[1]), + .S(SR)); +endmodule + +module pcie_7x_0_pcie_7x_0_pcie_pipe_misc + (pipe_tx_rcvr_det_gt, + \pipe_stages_1.pipe_tx_rate_q_reg_0 , + pipe_tx_deemph_gt, + \pipe_stages_1.pipe_tx_margin_q_reg[2]_0 , + SR, + pipe_tx_rcvr_det, + pipe_pclk_in, + pipe_tx_rate, + pipe_tx_deemph, + \pipe_stages_1.pipe_tx_margin_q_reg[2]_1 ); + output pipe_tx_rcvr_det_gt; + output [0:0]\pipe_stages_1.pipe_tx_rate_q_reg_0 ; + output pipe_tx_deemph_gt; + output [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 ; + input [0:0]SR; + input pipe_tx_rcvr_det; + input pipe_pclk_in; + input pipe_tx_rate; + input pipe_tx_deemph; + input [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_1 ; + + wire [0:0]SR; + wire pipe_pclk_in; + wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 ; + wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_1 ; + wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg_0 ; + wire pipe_tx_deemph; + wire pipe_tx_deemph_gt; + wire pipe_tx_rate; + wire pipe_tx_rcvr_det; + wire pipe_tx_rcvr_det_gt; + + FDSE \pipe_stages_1.pipe_tx_deemph_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_tx_deemph), + .Q(pipe_tx_deemph_gt), + .S(SR)); + FDRE \pipe_stages_1.pipe_tx_margin_q_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_margin_q_reg[2]_1 [0]), + .Q(\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 [0]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_margin_q_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_margin_q_reg[2]_1 [1]), + .Q(\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 [1]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_margin_q_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\pipe_stages_1.pipe_tx_margin_q_reg[2]_1 [2]), + .Q(\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 [2]), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_rate_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_tx_rate), + .Q(\pipe_stages_1.pipe_tx_rate_q_reg_0 ), + .R(SR)); + FDRE \pipe_stages_1.pipe_tx_rcvr_det_q_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_tx_rcvr_det), + .Q(pipe_tx_rcvr_det_gt), + .R(SR)); +endmodule + +module pcie_7x_0_pcie_7x_0_pcie_pipe_pipeline + (pipe_rx1_valid, + pipe_rx1_chanisaligned, + pipe_rx1_phy_status, + pipe_rx1_elec_idle, + PIPE_RXPOLARITY, + PIPE_TXCOMPLIANCE, + PIPE_TXELECIDLE, + pipe_rx2_valid, + pipe_rx2_chanisaligned, + pipe_rx2_phy_status, + pipe_rx2_elec_idle, + pipe_rx3_valid, + pipe_rx3_chanisaligned, + pipe_rx3_phy_status, + pipe_rx3_elec_idle, + pipe_tx_rcvr_det_gt, + \pipe_stages_1.pipe_tx_rate_q_reg , + pipe_tx_deemph_gt, + pipe_rx0_valid, + pipe_rx0_chanisaligned, + pipe_rx0_phy_status, + pipe_rx0_elec_idle, + Q, + \pipe_stages_1.pipe_rx_data_q_reg[15] , + \pipe_stages_1.pipe_rx_status_q_reg[2] , + PIPE_TXDATAK, + PIPE_TXDATA, + PIPE_POWERDOWN, + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] , + \pipe_stages_1.pipe_rx_data_q_reg[15]_0 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_0 , + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 , + \pipe_stages_1.pipe_rx_data_q_reg[15]_1 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_1 , + \pipe_stages_1.pipe_tx_margin_q_reg[2] , + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 , + \pipe_stages_1.pipe_rx_data_q_reg[15]_2 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_2 , + SR, + pipe_rx1_valid_gt, + pipe_pclk_in, + PIPE_RXCHANISALIGNED, + \pipe_stages_1.pipe_rx_phy_status_q_reg , + \pipe_stages_1.pipe_rx_elec_idle_q_reg , + pipe_rx0_polarity, + pipe_rx1_polarity, + pipe_rx2_polarity, + pipe_rx3_polarity, + pipe_tx0_compliance, + pipe_tx1_compliance, + pipe_tx2_compliance, + pipe_tx3_compliance, + pipe_tx0_elec_idle, + pipe_tx1_elec_idle, + pipe_tx2_elec_idle, + pipe_tx3_elec_idle, + pipe_rx2_valid_gt, + \pipe_stages_1.pipe_rx_phy_status_q_reg_0 , + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 , + pipe_rx3_valid_gt, + \pipe_stages_1.pipe_rx_phy_status_q_reg_1 , + \pipe_stages_1.pipe_rx_elec_idle_q_reg_1 , + pipe_tx_rcvr_det, + pipe_tx_rate, + pipe_tx_deemph, + pipe_rx0_valid_gt, + gt_rx_phy_status_q, + gt_rxelecidle_q, + D, + \pipe_stages_1.pipe_rx_data_q_reg[15]_3 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_3 , + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] , + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 , + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 , + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2 , + \pipe_stages_1.pipe_tx_data_q_reg[15] , + \pipe_stages_1.pipe_tx_data_q_reg[15]_0 , + \pipe_stages_1.pipe_tx_data_q_reg[15]_1 , + \pipe_stages_1.pipe_tx_data_q_reg[15]_2 , + \pipe_stages_1.pipe_tx_powerdown_q_reg[1] , + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 , + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 , + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2 , + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 , + \pipe_stages_1.pipe_rx_data_q_reg[15]_4 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_4 , + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 , + \pipe_stages_1.pipe_rx_data_q_reg[15]_5 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_5 , + \pipe_stages_1.pipe_tx_margin_q_reg[2]_0 , + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 , + \pipe_stages_1.pipe_rx_data_q_reg[15]_6 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_6 ); + output pipe_rx1_valid; + output pipe_rx1_chanisaligned; + output pipe_rx1_phy_status; + output pipe_rx1_elec_idle; + output [3:0]PIPE_RXPOLARITY; + output [3:0]PIPE_TXCOMPLIANCE; + output [3:0]PIPE_TXELECIDLE; + output pipe_rx2_valid; + output pipe_rx2_chanisaligned; + output pipe_rx2_phy_status; + output pipe_rx2_elec_idle; + output pipe_rx3_valid; + output pipe_rx3_chanisaligned; + output pipe_rx3_phy_status; + output pipe_rx3_elec_idle; + output pipe_tx_rcvr_det_gt; + output [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ; + output pipe_tx_deemph_gt; + output pipe_rx0_valid; + output pipe_rx0_chanisaligned; + output pipe_rx0_phy_status; + output pipe_rx0_elec_idle; + output [1:0]Q; + output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ; + output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ; + output [7:0]PIPE_TXDATAK; + output [63:0]PIPE_TXDATA; + output [7:0]PIPE_POWERDOWN; + output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ; + output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ; + output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ; + output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ; + output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ; + output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ; + output [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ; + output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ; + output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ; + output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ; + input [0:0]SR; + input pipe_rx1_valid_gt; + input pipe_pclk_in; + input [3:0]PIPE_RXCHANISALIGNED; + input \pipe_stages_1.pipe_rx_phy_status_q_reg ; + input \pipe_stages_1.pipe_rx_elec_idle_q_reg ; + input pipe_rx0_polarity; + input pipe_rx1_polarity; + input pipe_rx2_polarity; + input pipe_rx3_polarity; + input pipe_tx0_compliance; + input pipe_tx1_compliance; + input pipe_tx2_compliance; + input pipe_tx3_compliance; + input pipe_tx0_elec_idle; + input pipe_tx1_elec_idle; + input pipe_tx2_elec_idle; + input pipe_tx3_elec_idle; + input pipe_rx2_valid_gt; + input \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ; + input \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ; + input pipe_rx3_valid_gt; + input \pipe_stages_1.pipe_rx_phy_status_q_reg_1 ; + input \pipe_stages_1.pipe_rx_elec_idle_q_reg_1 ; + input pipe_tx_rcvr_det; + input pipe_tx_rate; + input pipe_tx_deemph; + input pipe_rx0_valid_gt; + input gt_rx_phy_status_q; + input gt_rxelecidle_q; + input [1:0]D; + input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_3 ; + input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_3 ; + input [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1] ; + input [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ; + input [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 ; + input [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2 ; + input [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15] ; + input [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ; + input [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_1 ; + input [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_2 ; + input [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1] ; + input [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ; + input [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 ; + input [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2 ; + input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 ; + input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_4 ; + input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_4 ; + input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 ; + input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_5 ; + input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_5 ; + input [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 ; + input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 ; + input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_6 ; + input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_6 ; + + wire [1:0]D; + wire [7:0]PIPE_POWERDOWN; + wire [3:0]PIPE_RXCHANISALIGNED; + wire [3:0]PIPE_RXPOLARITY; + wire [3:0]PIPE_TXCOMPLIANCE; + wire [63:0]PIPE_TXDATA; + wire [7:0]PIPE_TXDATAK; + wire [3:0]PIPE_TXELECIDLE; + wire [1:0]Q; + wire [0:0]SR; + wire gt_rx_phy_status_q; + wire gt_rxelecidle_q; + wire pipe_pclk_in; + wire pipe_rx0_chanisaligned; + wire pipe_rx0_elec_idle; + wire pipe_rx0_phy_status; + wire pipe_rx0_polarity; + wire pipe_rx0_valid; + wire pipe_rx0_valid_gt; + wire pipe_rx1_chanisaligned; + wire pipe_rx1_elec_idle; + wire pipe_rx1_phy_status; + wire pipe_rx1_polarity; + wire pipe_rx1_valid; + wire pipe_rx1_valid_gt; + wire pipe_rx2_chanisaligned; + wire pipe_rx2_elec_idle; + wire pipe_rx2_phy_status; + wire pipe_rx2_polarity; + wire pipe_rx2_valid; + wire pipe_rx2_valid_gt; + wire pipe_rx3_chanisaligned; + wire pipe_rx3_elec_idle; + wire pipe_rx3_phy_status; + wire pipe_rx3_polarity; + wire pipe_rx3_valid; + wire pipe_rx3_valid_gt; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 ; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 ; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_3 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_4 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_5 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_6 ; + wire \pipe_stages_1.pipe_rx_elec_idle_q_reg ; + wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ; + wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_1 ; + wire \pipe_stages_1.pipe_rx_phy_status_q_reg ; + wire \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ; + wire \pipe_stages_1.pipe_rx_phy_status_q_reg_1 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_3 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_4 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_5 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_6 ; + wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1] ; + wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ; + wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 ; + wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2 ; + wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15] ; + wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ; + wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_1 ; + wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_2 ; + wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ; + wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 ; + wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1] ; + wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ; + wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 ; + wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2 ; + wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ; + wire pipe_tx0_compliance; + wire pipe_tx0_elec_idle; + wire pipe_tx1_compliance; + wire pipe_tx1_elec_idle; + wire pipe_tx2_compliance; + wire pipe_tx2_elec_idle; + wire pipe_tx3_compliance; + wire pipe_tx3_elec_idle; + wire pipe_tx_deemph; + wire pipe_tx_deemph_gt; + wire pipe_tx_rate; + wire pipe_tx_rcvr_det; + wire pipe_tx_rcvr_det_gt; + + pcie_7x_0_pcie_7x_0_pcie_pipe_lane \pipe_2_lane.pipe_lane_1_i + (.D(D), + .PIPE_POWERDOWN(PIPE_POWERDOWN[3:2]), + .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[1]), + .PIPE_RXPOLARITY(PIPE_RXPOLARITY[1]), + .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[1]), + .PIPE_TXDATA(PIPE_TXDATA[31:16]), + .PIPE_TXDATAK(PIPE_TXDATAK[3:2]), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE[1]), + .Q(Q), + .SR(SR), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rx1_chanisaligned(pipe_rx1_chanisaligned), + .pipe_rx1_elec_idle(pipe_rx1_elec_idle), + .pipe_rx1_phy_status(pipe_rx1_phy_status), + .pipe_rx1_polarity(pipe_rx1_polarity), + .pipe_rx1_valid(pipe_rx1_valid), + .pipe_rx1_valid_gt(pipe_rx1_valid_gt), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_0 (\pipe_stages_1.pipe_rx_data_q_reg[15] ), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_1 (\pipe_stages_1.pipe_rx_data_q_reg[15]_3 ), + .\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 (\pipe_stages_1.pipe_rx_elec_idle_q_reg ), + .\pipe_stages_1.pipe_rx_phy_status_q_reg_0 (\pipe_stages_1.pipe_rx_phy_status_q_reg ), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_0 (\pipe_stages_1.pipe_rx_status_q_reg[2] ), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_1 (\pipe_stages_1.pipe_rx_status_q_reg[2]_3 ), + .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 (\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ), + .\pipe_stages_1.pipe_tx_data_q_reg[15]_0 (\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ), + .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 (\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ), + .pipe_tx1_compliance(pipe_tx1_compliance), + .pipe_tx1_elec_idle(pipe_tx1_elec_idle)); + pcie_7x_0_pcie_7x_0_pcie_pipe_lane_0 \pipe_4_lane.pipe_lane_2_i + (.PIPE_POWERDOWN(PIPE_POWERDOWN[5:4]), + .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[2]), + .PIPE_RXPOLARITY(PIPE_RXPOLARITY[2]), + .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[2]), + .PIPE_TXDATA(PIPE_TXDATA[47:32]), + .PIPE_TXDATAK(PIPE_TXDATAK[5:4]), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE[2]), + .SR(SR), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rx2_chanisaligned(pipe_rx2_chanisaligned), + .pipe_rx2_elec_idle(pipe_rx2_elec_idle), + .pipe_rx2_phy_status(pipe_rx2_phy_status), + .pipe_rx2_polarity(pipe_rx2_polarity), + .pipe_rx2_valid(pipe_rx2_valid), + .pipe_rx2_valid_gt(pipe_rx2_valid_gt), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 ), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_0 (\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_1 (\pipe_stages_1.pipe_rx_data_q_reg[15]_4 ), + .\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 (\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ), + .\pipe_stages_1.pipe_rx_phy_status_q_reg_0 (\pipe_stages_1.pipe_rx_phy_status_q_reg_0 ), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_0 (\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_1 (\pipe_stages_1.pipe_rx_status_q_reg[2]_4 ), + .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 (\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 ), + .\pipe_stages_1.pipe_tx_data_q_reg[15]_0 (\pipe_stages_1.pipe_tx_data_q_reg[15]_1 ), + .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 (\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 ), + .pipe_tx2_compliance(pipe_tx2_compliance), + .pipe_tx2_elec_idle(pipe_tx2_elec_idle)); + pcie_7x_0_pcie_7x_0_pcie_pipe_lane_1 \pipe_4_lane.pipe_lane_3_i + (.PIPE_POWERDOWN(PIPE_POWERDOWN[7:6]), + .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[3]), + .PIPE_RXPOLARITY(PIPE_RXPOLARITY[3]), + .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[3]), + .PIPE_TXDATA(PIPE_TXDATA[63:48]), + .PIPE_TXDATAK(PIPE_TXDATAK[7:6]), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE[3]), + .SR(SR), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rx3_chanisaligned(pipe_rx3_chanisaligned), + .pipe_rx3_elec_idle(pipe_rx3_elec_idle), + .pipe_rx3_phy_status(pipe_rx3_phy_status), + .pipe_rx3_polarity(pipe_rx3_polarity), + .pipe_rx3_valid(pipe_rx3_valid), + .pipe_rx3_valid_gt(pipe_rx3_valid_gt), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 ), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_0 (\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_1 (\pipe_stages_1.pipe_rx_data_q_reg[15]_5 ), + .\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 (\pipe_stages_1.pipe_rx_elec_idle_q_reg_1 ), + .\pipe_stages_1.pipe_rx_phy_status_q_reg_0 (\pipe_stages_1.pipe_rx_phy_status_q_reg_1 ), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_0 (\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_1 (\pipe_stages_1.pipe_rx_status_q_reg[2]_5 ), + .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 (\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2 ), + .\pipe_stages_1.pipe_tx_data_q_reg[15]_0 (\pipe_stages_1.pipe_tx_data_q_reg[15]_2 ), + .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 (\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2 ), + .pipe_tx3_compliance(pipe_tx3_compliance), + .pipe_tx3_elec_idle(pipe_tx3_elec_idle)); + pcie_7x_0_pcie_7x_0_pcie_pipe_lane_2 pipe_lane_0_i + (.PIPE_POWERDOWN(PIPE_POWERDOWN[1:0]), + .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[0]), + .PIPE_RXPOLARITY(PIPE_RXPOLARITY[0]), + .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[0]), + .PIPE_TXDATA(PIPE_TXDATA[15:0]), + .PIPE_TXDATAK(PIPE_TXDATAK[1:0]), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE[0]), + .SR(SR), + .gt_rx_phy_status_q(gt_rx_phy_status_q), + .gt_rxelecidle_q(gt_rxelecidle_q), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rx0_chanisaligned(pipe_rx0_chanisaligned), + .pipe_rx0_elec_idle(pipe_rx0_elec_idle), + .pipe_rx0_phy_status(pipe_rx0_phy_status), + .pipe_rx0_polarity(pipe_rx0_polarity), + .pipe_rx0_valid(pipe_rx0_valid), + .pipe_rx0_valid_gt(pipe_rx0_valid_gt), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 ), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_0 (\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_1 (\pipe_stages_1.pipe_rx_data_q_reg[15]_6 ), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_0 (\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_1 (\pipe_stages_1.pipe_rx_status_q_reg[2]_6 ), + .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 (\pipe_stages_1.pipe_tx_char_is_k_q_reg[1] ), + .\pipe_stages_1.pipe_tx_data_q_reg[15]_0 (\pipe_stages_1.pipe_tx_data_q_reg[15] ), + .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 (\pipe_stages_1.pipe_tx_powerdown_q_reg[1] ), + .pipe_tx0_compliance(pipe_tx0_compliance), + .pipe_tx0_elec_idle(pipe_tx0_elec_idle)); + pcie_7x_0_pcie_7x_0_pcie_pipe_misc pipe_misc_i + (.SR(SR), + .pipe_pclk_in(pipe_pclk_in), + .\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 (\pipe_stages_1.pipe_tx_margin_q_reg[2] ), + .\pipe_stages_1.pipe_tx_margin_q_reg[2]_1 (\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 ), + .\pipe_stages_1.pipe_tx_rate_q_reg_0 (\pipe_stages_1.pipe_tx_rate_q_reg ), + .pipe_tx_deemph(pipe_tx_deemph), + .pipe_tx_deemph_gt(pipe_tx_deemph_gt), + .pipe_tx_rate(pipe_tx_rate), + .pipe_tx_rcvr_det(pipe_tx_rcvr_det), + .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt)); +endmodule + +module pcie_7x_0_pcie_7x_0_pcie_top + (m_axis_rx_tvalid_reg, + m_axis_rx_tkeep, + m_axis_rx_tlast, + trn_tcfg_req, + tready_thrtl_reg, + PIPE_RXPOLARITY, + PIPE_TXCOMPLIANCE, + PIPE_TXELECIDLE, + pipe_tx_rcvr_det_gt, + \pipe_stages_1.pipe_tx_rate_q_reg , + pipe_tx_deemph_gt, + user_reset_int_reg, + src_in, + cfg_mgmt_rd_wr_done, + cfg_err_aer_headerlog_set, + cfg_err_cpl_rdy, + cfg_interrupt_rdy, + cfg_msg_received, + cfg_received_func_lvl_rst, + cfg_pcie_link_state, + m_axis_rx_tdata, + m_axis_rx_tuser, + trn_tbuf_av, + cfg_to_turnoff, + cfg_bus_number, + cfg_msg_data, + cfg_device_number, + cfg_function_number, + PIPE_TXDATAK, + PIPE_TXDATA, + PIPE_POWERDOWN, + Q, + cfg_aer_ecrc_check_en, + cfg_aer_ecrc_gen_en, + cfg_aer_rooterr_corr_err_received, + cfg_aer_rooterr_corr_err_reporting_en, + cfg_aer_rooterr_fatal_err_received, + cfg_aer_rooterr_fatal_err_reporting_en, + cfg_aer_rooterr_non_fatal_err_received, + cfg_aer_rooterr_non_fatal_err_reporting_en, + cfg_bridge_serr_en, + cfg_command, + cfg_dcommand2, + cfg_dcommand, + cfg_dstatus, + cfg_interrupt_msienable, + cfg_interrupt_msixenable, + cfg_interrupt_msixfm, + cfg_lcommand, + cfg_lstatus, + cfg_msg_received_assert_int_a, + cfg_msg_received_assert_int_b, + cfg_msg_received_assert_int_c, + cfg_msg_received_assert_int_d, + cfg_msg_received_deassert_int_a, + cfg_msg_received_deassert_int_b, + cfg_msg_received_deassert_int_c, + cfg_msg_received_deassert_int_d, + cfg_msg_received_err_cor, + cfg_msg_received_err_fatal, + cfg_msg_received_err_non_fatal, + cfg_msg_received_pm_as_nak, + cfg_msg_received_pme_to_ack, + cfg_msg_received_pm_pme, + cfg_msg_received_setslotpowerlimit, + cfg_pmcsr_pme_en, + cfg_pmcsr_pme_status, + cfg_root_control_pme_int_en, + cfg_root_control_syserr_corr_err_en, + cfg_root_control_syserr_fatal_err_en, + cfg_root_control_syserr_non_fatal_err_en, + cfg_slot_control_electromech_il_ctl_pulse, + pcie_drp_rdy, + pl_directed_change_done, + pl_link_gen2_cap, + pl_link_partner_gen2_supported, + pl_link_upcfg_cap, + pl_received_hot_rst, + pl_sel_lnk_rate, + trn_lnk_up, + tx_err_drop, + fc_cpld, + fc_npd, + fc_pd, + pcie_drp_do, + cfg_pmcsr_powerstate, + pl_lane_reversal_mode, + pl_rx_pm_state, + pl_sel_lnk_width, + cfg_interrupt_mmenable, + pl_initial_link_width, + pl_tx_pm_state, + cfg_mgmt_do, + pl_ltssm_state, + cfg_vc_tcvc_map, + cfg_interrupt_do, + fc_cplh, + fc_nph, + fc_ph, + \throttle_ctl_pipeline.reg_tkeep_reg[7] , + pipe_userclk2_in, + tx_cfg_gnt, + cfg_turnoff_ok, + s_axis_tx_tlast, + s_axis_tx_tvalid, + s_axis_tx_tkeep, + SR, + pipe_rx1_valid_gt, + pipe_pclk_in, + PIPE_RXCHANISALIGNED, + \pipe_stages_1.pipe_rx_phy_status_q_reg , + \pipe_stages_1.pipe_rx_elec_idle_q_reg , + pipe_rx2_valid_gt, + \pipe_stages_1.pipe_rx_phy_status_q_reg_0 , + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 , + pipe_rx3_valid_gt, + \pipe_stages_1.pipe_rx_phy_status_q_reg_1 , + \pipe_stages_1.pipe_rx_elec_idle_q_reg_1 , + pipe_rx0_valid_gt, + gt_rx_phy_status_q, + gt_rxelecidle_q, + bridge_reset_int, + pl_phy_lnk_up, + m_axis_rx_tready, + cfg_trn_pending, + cfg_mgmt_wr_rw1c_as_rw, + cfg_mgmt_wr_readonly, + cfg_mgmt_wr_en, + cfg_mgmt_rd_en, + cfg_err_malformed, + cfg_err_cor, + cfg_err_ur, + cfg_err_ecrc, + cfg_err_cpl_timeout, + cfg_err_cpl_abort, + cfg_err_cpl_unexpect, + cfg_err_poisoned, + cfg_err_atomic_egress_blocked, + cfg_err_mc_blocked, + cfg_err_internal_uncor, + cfg_err_internal_cor, + cfg_err_posted, + cfg_err_locked, + cfg_err_norecovery, + cfg_interrupt, + cfg_interrupt_assert, + cfg_interrupt_stat, + cfg_pm_halt_aspm_l0s, + cfg_pm_halt_aspm_l1, + cfg_pm_force_state_en, + cfg_pm_wake, + out, + s_axis_tx_tdata, + s_axis_tx_tuser, + D, + \pipe_stages_1.pipe_rx_data_q_reg[15] , + \pipe_stages_1.pipe_rx_status_q_reg[2] , + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] , + \pipe_stages_1.pipe_rx_data_q_reg[15]_0 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_0 , + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 , + \pipe_stages_1.pipe_rx_data_q_reg[15]_1 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_1 , + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 , + \pipe_stages_1.pipe_rx_data_q_reg[15]_2 , + \pipe_stages_1.pipe_rx_status_q_reg[2]_2 , + pipe_userclk1_in, + pcie_drp_clk, + pcie_drp_en, + pcie_drp_we, + pl_directed_link_auton, + pl_directed_link_speed, + pl_downstream_deemph_source, + pl_transmit_hot_rst, + pl_upstream_prefer_deemph, + sys_rst_n, + rx_np_ok, + rx_np_req, + cfg_err_aer_headerlog, + pcie_drp_di, + cfg_pm_force_state, + pl_directed_link_change, + pl_directed_link_width, + cfg_ds_function_number, + fc_sel, + cfg_mgmt_di, + cfg_mgmt_byte_en_n, + cfg_err_tlp_cpl_header, + cfg_aer_interrupt_msgnum, + cfg_ds_device_number, + cfg_pciecap_interrupt_msgnum, + cfg_dsn, + cfg_ds_bus_number, + cfg_interrupt_di, + pcie_drp_addr, + cfg_mgmt_dwaddr); + output m_axis_rx_tvalid_reg; + output [0:0]m_axis_rx_tkeep; + output m_axis_rx_tlast; + output trn_tcfg_req; + output tready_thrtl_reg; + output [3:0]PIPE_RXPOLARITY; + output [3:0]PIPE_TXCOMPLIANCE; + output [3:0]PIPE_TXELECIDLE; + output pipe_tx_rcvr_det_gt; + output [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ; + output pipe_tx_deemph_gt; + output user_reset_int_reg; + output src_in; + output cfg_mgmt_rd_wr_done; + output cfg_err_aer_headerlog_set; + output cfg_err_cpl_rdy; + output cfg_interrupt_rdy; + output cfg_msg_received; + output cfg_received_func_lvl_rst; + output [2:0]cfg_pcie_link_state; + output [63:0]m_axis_rx_tdata; + output [12:0]m_axis_rx_tuser; + output [5:0]trn_tbuf_av; + output cfg_to_turnoff; + output [7:0]cfg_bus_number; + output [15:0]cfg_msg_data; + output [4:0]cfg_device_number; + output [2:0]cfg_function_number; + output [7:0]PIPE_TXDATAK; + output [63:0]PIPE_TXDATA; + output [7:0]PIPE_POWERDOWN; + output [2:0]Q; + output cfg_aer_ecrc_check_en; + output cfg_aer_ecrc_gen_en; + output cfg_aer_rooterr_corr_err_received; + output cfg_aer_rooterr_corr_err_reporting_en; + output cfg_aer_rooterr_fatal_err_received; + output cfg_aer_rooterr_fatal_err_reporting_en; + output cfg_aer_rooterr_non_fatal_err_received; + output cfg_aer_rooterr_non_fatal_err_reporting_en; + output cfg_bridge_serr_en; + output [4:0]cfg_command; + output [11:0]cfg_dcommand2; + output [14:0]cfg_dcommand; + output [3:0]cfg_dstatus; + output cfg_interrupt_msienable; + output cfg_interrupt_msixenable; + output cfg_interrupt_msixfm; + output [10:0]cfg_lcommand; + output [9:0]cfg_lstatus; + output cfg_msg_received_assert_int_a; + output cfg_msg_received_assert_int_b; + output cfg_msg_received_assert_int_c; + output cfg_msg_received_assert_int_d; + output cfg_msg_received_deassert_int_a; + output cfg_msg_received_deassert_int_b; + output cfg_msg_received_deassert_int_c; + output cfg_msg_received_deassert_int_d; + output cfg_msg_received_err_cor; + output cfg_msg_received_err_fatal; + output cfg_msg_received_err_non_fatal; + output cfg_msg_received_pm_as_nak; + output cfg_msg_received_pme_to_ack; + output cfg_msg_received_pm_pme; + output cfg_msg_received_setslotpowerlimit; + output cfg_pmcsr_pme_en; + output cfg_pmcsr_pme_status; + output cfg_root_control_pme_int_en; + output cfg_root_control_syserr_corr_err_en; + output cfg_root_control_syserr_fatal_err_en; + output cfg_root_control_syserr_non_fatal_err_en; + output cfg_slot_control_electromech_il_ctl_pulse; + output pcie_drp_rdy; + output pl_directed_change_done; + output pl_link_gen2_cap; + output pl_link_partner_gen2_supported; + output pl_link_upcfg_cap; + output pl_received_hot_rst; + output pl_sel_lnk_rate; + output trn_lnk_up; + output tx_err_drop; + output [11:0]fc_cpld; + output [11:0]fc_npd; + output [11:0]fc_pd; + output [15:0]pcie_drp_do; + output [1:0]cfg_pmcsr_powerstate; + output [1:0]pl_lane_reversal_mode; + output [1:0]pl_rx_pm_state; + output [1:0]pl_sel_lnk_width; + output [2:0]cfg_interrupt_mmenable; + output [2:0]pl_initial_link_width; + output [2:0]pl_tx_pm_state; + output [31:0]cfg_mgmt_do; + output [5:0]pl_ltssm_state; + output [6:0]cfg_vc_tcvc_map; + output [7:0]cfg_interrupt_do; + output [7:0]fc_cplh; + output [7:0]fc_nph; + output [7:0]fc_ph; + input \throttle_ctl_pipeline.reg_tkeep_reg[7] ; + input pipe_userclk2_in; + input tx_cfg_gnt; + input cfg_turnoff_ok; + input s_axis_tx_tlast; + input s_axis_tx_tvalid; + input [0:0]s_axis_tx_tkeep; + input [0:0]SR; + input pipe_rx1_valid_gt; + input pipe_pclk_in; + input [3:0]PIPE_RXCHANISALIGNED; + input \pipe_stages_1.pipe_rx_phy_status_q_reg ; + input \pipe_stages_1.pipe_rx_elec_idle_q_reg ; + input pipe_rx2_valid_gt; + input \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ; + input \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ; + input pipe_rx3_valid_gt; + input \pipe_stages_1.pipe_rx_phy_status_q_reg_1 ; + input \pipe_stages_1.pipe_rx_elec_idle_q_reg_1 ; + input pipe_rx0_valid_gt; + input gt_rx_phy_status_q; + input gt_rxelecidle_q; + input bridge_reset_int; + input pl_phy_lnk_up; + input m_axis_rx_tready; + input cfg_trn_pending; + input cfg_mgmt_wr_rw1c_as_rw; + input cfg_mgmt_wr_readonly; + input cfg_mgmt_wr_en; + input cfg_mgmt_rd_en; + input cfg_err_malformed; + input cfg_err_cor; + input cfg_err_ur; + input cfg_err_ecrc; + input cfg_err_cpl_timeout; + input cfg_err_cpl_abort; + input cfg_err_cpl_unexpect; + input cfg_err_poisoned; + input cfg_err_atomic_egress_blocked; + input cfg_err_mc_blocked; + input cfg_err_internal_uncor; + input cfg_err_internal_cor; + input cfg_err_posted; + input cfg_err_locked; + input cfg_err_norecovery; + input cfg_interrupt; + input cfg_interrupt_assert; + input cfg_interrupt_stat; + input cfg_pm_halt_aspm_l0s; + input cfg_pm_halt_aspm_l1; + input cfg_pm_force_state_en; + input cfg_pm_wake; + input out; + input [63:0]s_axis_tx_tdata; + input [3:0]s_axis_tx_tuser; + input [1:0]D; + input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ; + input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ; + input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ; + input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ; + input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ; + input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ; + input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ; + input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ; + input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ; + input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ; + input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ; + input pipe_userclk1_in; + input pcie_drp_clk; + input pcie_drp_en; + input pcie_drp_we; + input pl_directed_link_auton; + input pl_directed_link_speed; + input pl_downstream_deemph_source; + input pl_transmit_hot_rst; + input pl_upstream_prefer_deemph; + input sys_rst_n; + input rx_np_ok; + input rx_np_req; + input [127:0]cfg_err_aer_headerlog; + input [15:0]pcie_drp_di; + input [1:0]cfg_pm_force_state; + input [1:0]pl_directed_link_change; + input [1:0]pl_directed_link_width; + input [2:0]cfg_ds_function_number; + input [2:0]fc_sel; + input [31:0]cfg_mgmt_di; + input [3:0]cfg_mgmt_byte_en_n; + input [47:0]cfg_err_tlp_cpl_header; + input [4:0]cfg_aer_interrupt_msgnum; + input [4:0]cfg_ds_device_number; + input [4:0]cfg_pciecap_interrupt_msgnum; + input [63:0]cfg_dsn; + input [7:0]cfg_ds_bus_number; + input [7:0]cfg_interrupt_di; + input [8:0]pcie_drp_addr; + input [9:0]cfg_mgmt_dwaddr; + + wire [1:0]D; + wire [7:0]PIPE_POWERDOWN; + wire [3:0]PIPE_RXCHANISALIGNED; + wire [3:0]PIPE_RXPOLARITY; + wire [3:0]PIPE_TXCOMPLIANCE; + wire [63:0]PIPE_TXDATA; + wire [7:0]PIPE_TXDATAK; + wire [3:0]PIPE_TXELECIDLE; + wire [2:0]Q; + wire [0:0]SR; + wire bridge_reset_int; + wire cfg_aer_ecrc_check_en; + wire cfg_aer_ecrc_gen_en; + wire [4:0]cfg_aer_interrupt_msgnum; + wire cfg_aer_rooterr_corr_err_received; + wire cfg_aer_rooterr_corr_err_reporting_en; + wire cfg_aer_rooterr_fatal_err_received; + wire cfg_aer_rooterr_fatal_err_reporting_en; + wire cfg_aer_rooterr_non_fatal_err_received; + wire cfg_aer_rooterr_non_fatal_err_reporting_en; + wire cfg_bridge_serr_en; + wire [7:0]cfg_bus_number; + wire [4:0]cfg_command; + wire [14:0]cfg_dcommand; + wire [11:0]cfg_dcommand2; + wire [4:0]cfg_device_number; + wire [7:0]cfg_ds_bus_number; + wire [4:0]cfg_ds_device_number; + wire [2:0]cfg_ds_function_number; + wire [63:0]cfg_dsn; + wire [3:0]cfg_dstatus; + wire [127:0]cfg_err_aer_headerlog; + wire cfg_err_aer_headerlog_set; + wire cfg_err_atomic_egress_blocked; + wire cfg_err_cor; + wire cfg_err_cpl_abort; + wire cfg_err_cpl_rdy; + wire cfg_err_cpl_timeout; + wire cfg_err_cpl_unexpect; + wire cfg_err_ecrc; + wire cfg_err_internal_cor; + wire cfg_err_internal_uncor; + wire cfg_err_locked; + wire cfg_err_malformed; + wire cfg_err_mc_blocked; + wire cfg_err_norecovery; + wire cfg_err_poisoned; + wire cfg_err_posted; + wire [47:0]cfg_err_tlp_cpl_header; + wire cfg_err_ur; + wire [2:0]cfg_function_number; + wire cfg_interrupt; + wire cfg_interrupt_assert; + wire [7:0]cfg_interrupt_di; + wire [7:0]cfg_interrupt_do; + wire [2:0]cfg_interrupt_mmenable; + wire cfg_interrupt_msienable; + wire cfg_interrupt_msixenable; + wire cfg_interrupt_msixfm; + wire cfg_interrupt_rdy; + wire cfg_interrupt_stat; + wire [10:0]cfg_lcommand; + wire [9:0]cfg_lstatus; + wire [3:0]cfg_mgmt_byte_en_n; + wire [31:0]cfg_mgmt_di; + wire [31:0]cfg_mgmt_do; + wire [9:0]cfg_mgmt_dwaddr; + wire cfg_mgmt_rd_en; + wire cfg_mgmt_rd_wr_done; + wire cfg_mgmt_wr_en; + wire cfg_mgmt_wr_readonly; + wire cfg_mgmt_wr_rw1c_as_rw; + wire [15:0]cfg_msg_data; + wire cfg_msg_received; + wire cfg_msg_received_assert_int_a; + wire cfg_msg_received_assert_int_b; + wire cfg_msg_received_assert_int_c; + wire cfg_msg_received_assert_int_d; + wire cfg_msg_received_deassert_int_a; + wire cfg_msg_received_deassert_int_b; + wire cfg_msg_received_deassert_int_c; + wire cfg_msg_received_deassert_int_d; + wire cfg_msg_received_err_cor; + wire cfg_msg_received_err_fatal; + wire cfg_msg_received_err_non_fatal; + wire cfg_msg_received_pm_as_nak; + wire cfg_msg_received_pm_pme; + wire cfg_msg_received_pme_to_ack; + wire cfg_msg_received_setslotpowerlimit; + wire [2:0]cfg_pcie_link_state; + wire [4:0]cfg_pciecap_interrupt_msgnum; + wire [1:0]cfg_pm_force_state; + wire cfg_pm_force_state_en; + wire cfg_pm_halt_aspm_l0s; + wire cfg_pm_halt_aspm_l1; + wire cfg_pm_wake; + wire cfg_pmcsr_pme_en; + wire cfg_pmcsr_pme_status; + wire [1:0]cfg_pmcsr_powerstate; + wire cfg_received_func_lvl_rst; + wire cfg_root_control_pme_int_en; + wire cfg_root_control_syserr_corr_err_en; + wire cfg_root_control_syserr_fatal_err_en; + wire cfg_root_control_syserr_non_fatal_err_en; + wire cfg_slot_control_electromech_il_ctl_pulse; + wire cfg_to_turnoff; + wire cfg_trn_pending; + wire cfg_turnoff_ok; + wire cfg_turnoff_ok_w; + wire [6:0]cfg_vc_tcvc_map; + wire [11:0]fc_cpld; + wire [7:0]fc_cplh; + wire [11:0]fc_npd; + wire [7:0]fc_nph; + wire [11:0]fc_pd; + wire [7:0]fc_ph; + wire [2:0]fc_sel; + wire gt_rx_phy_status_q; + wire gt_rxelecidle_q; + wire [63:0]m_axis_rx_tdata; + wire [0:0]m_axis_rx_tkeep; + wire m_axis_rx_tlast; + wire m_axis_rx_tready; + wire [12:0]m_axis_rx_tuser; + wire m_axis_rx_tvalid_reg; + wire out; + wire pcie_7x_i_n_13; + wire pcie_7x_i_n_22; + wire pcie_7x_i_n_30; + wire pcie_7x_i_n_6; + wire pcie_7x_i_n_9; + wire [8:0]pcie_drp_addr; + wire pcie_drp_clk; + wire [15:0]pcie_drp_di; + wire [15:0]pcie_drp_do; + wire pcie_drp_en; + wire pcie_drp_rdy; + wire pcie_drp_we; + wire pipe_pclk_in; + wire pipe_rx0_chanisaligned; + wire [1:0]pipe_rx0_char_is_k; + wire [15:0]pipe_rx0_data; + wire pipe_rx0_elec_idle; + wire pipe_rx0_phy_status; + wire pipe_rx0_polarity; + wire [2:0]pipe_rx0_status; + wire pipe_rx0_valid; + wire pipe_rx0_valid_gt; + wire pipe_rx1_chanisaligned; + wire [1:0]pipe_rx1_char_is_k; + wire [15:0]pipe_rx1_data; + wire pipe_rx1_elec_idle; + wire pipe_rx1_phy_status; + wire pipe_rx1_polarity; + wire [2:0]pipe_rx1_status; + wire pipe_rx1_valid; + wire pipe_rx1_valid_gt; + wire pipe_rx2_chanisaligned; + wire [1:0]pipe_rx2_char_is_k; + wire [15:0]pipe_rx2_data; + wire pipe_rx2_elec_idle; + wire pipe_rx2_phy_status; + wire pipe_rx2_polarity; + wire [2:0]pipe_rx2_status; + wire pipe_rx2_valid; + wire pipe_rx2_valid_gt; + wire pipe_rx3_chanisaligned; + wire [1:0]pipe_rx3_char_is_k; + wire [15:0]pipe_rx3_data; + wire pipe_rx3_elec_idle; + wire pipe_rx3_phy_status; + wire pipe_rx3_polarity; + wire [2:0]pipe_rx3_status; + wire pipe_rx3_valid; + wire pipe_rx3_valid_gt; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ; + wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ; + wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ; + wire \pipe_stages_1.pipe_rx_elec_idle_q_reg ; + wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ; + wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_1 ; + wire \pipe_stages_1.pipe_rx_phy_status_q_reg ; + wire \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ; + wire \pipe_stages_1.pipe_rx_phy_status_q_reg_1 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ; + wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ; + wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ; + wire [1:0]pipe_tx0_char_is_k; + wire pipe_tx0_compliance; + wire [15:0]pipe_tx0_data; + wire pipe_tx0_elec_idle; + wire [1:0]pipe_tx0_powerdown; + wire [1:0]pipe_tx1_char_is_k; + wire pipe_tx1_compliance; + wire [15:0]pipe_tx1_data; + wire pipe_tx1_elec_idle; + wire [1:0]pipe_tx1_powerdown; + wire [1:0]pipe_tx2_char_is_k; + wire pipe_tx2_compliance; + wire [15:0]pipe_tx2_data; + wire pipe_tx2_elec_idle; + wire [1:0]pipe_tx2_powerdown; + wire [1:0]pipe_tx3_char_is_k; + wire pipe_tx3_compliance; + wire [15:0]pipe_tx3_data; + wire pipe_tx3_elec_idle; + wire [1:0]pipe_tx3_powerdown; + wire pipe_tx_deemph; + wire pipe_tx_deemph_gt; + wire [2:0]pipe_tx_margin; + wire pipe_tx_rate; + wire pipe_tx_rcvr_det; + wire pipe_tx_rcvr_det_gt; + wire pipe_userclk1_in; + wire pipe_userclk2_in; + wire pl_directed_change_done; + wire pl_directed_link_auton; + wire [1:0]pl_directed_link_change; + wire pl_directed_link_speed; + wire [1:0]pl_directed_link_width; + wire pl_downstream_deemph_source; + wire [2:0]pl_initial_link_width; + wire [1:0]pl_lane_reversal_mode; + wire pl_link_gen2_cap; + wire pl_link_partner_gen2_supported; + wire pl_link_upcfg_cap; + wire [5:0]pl_ltssm_state; + wire pl_phy_lnk_up; + wire pl_received_hot_rst; + wire [1:0]pl_rx_pm_state; + wire pl_sel_lnk_rate; + wire [1:0]pl_sel_lnk_width; + wire pl_transmit_hot_rst; + wire [2:0]pl_tx_pm_state; + wire pl_upstream_prefer_deemph; + wire \rx_inst/rx_pipeline_inst/dsc_detect ; + wire \rx_inst/rx_pipeline_inst/reg_dsc_detect ; + wire \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered ; + wire \rx_inst/rx_pipeline_inst/trn_in_packet ; + wire \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d ; + wire \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0 ; + wire rx_np_ok; + wire rx_np_req; + wire [63:0]s_axis_tx_tdata; + wire [0:0]s_axis_tx_tkeep; + wire s_axis_tx_tlast; + wire [3:0]s_axis_tx_tuser; + wire s_axis_tx_tvalid; + wire src_in; + wire sys_rst_n; + wire \throttle_ctl_pipeline.reg_tkeep_reg[7] ; + wire tready_thrtl_reg; + wire trn_lnk_up; + wire [6:0]trn_rbar_hit; + wire [63:0]trn_rd; + wire trn_rdst_rdy; + wire trn_recrc_err; + wire trn_reof; + wire trn_rerrfwd; + wire [0:0]trn_rrem; + wire trn_rsof; + wire trn_rsrc_dsc; + wire [5:0]trn_tbuf_av; + wire trn_tcfg_gnt; + wire trn_tcfg_req; + wire [63:0]trn_td; + wire trn_tdst_rdy; + wire trn_tecrc_gen; + wire trn_teof; + wire trn_terrfwd; + wire trn_trem; + wire trn_tsof; + wire trn_tsrc_dsc; + wire trn_tsrc_rdy; + wire trn_tstr; + wire tx_cfg_gnt; + wire tx_err_drop; + wire \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/lnk_up_thrtl ; + wire \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_thrtl ; + wire \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_trig ; + wire \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/reg_tcfg_gnt ; + wire \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tbuf_av_min_trig ; + wire \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tcfg_req_trig ; + wire \tx_inst/tx_pipeline_inst/reg_disable_trn2 ; + wire user_reset_int_reg; + + pcie_7x_0_pcie_7x_0_axi_basic_top axi_basic_top + (.E(trn_rdst_rdy), + .Q(m_axis_rx_tdata), + .cfg_pcie_link_state(cfg_pcie_link_state), + .cfg_pm_turnoff_ok_n(cfg_turnoff_ok_w), + .cfg_to_turnoff(cfg_to_turnoff), + .cfg_turnoff_ok(cfg_turnoff_ok), + .dsc_detect(\rx_inst/rx_pipeline_inst/dsc_detect ), + .lnk_up_thrtl(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/lnk_up_thrtl ), + .lnk_up_thrtl_reg(pcie_7x_i_n_30), + .m_axis_rx_tkeep(m_axis_rx_tkeep), + .m_axis_rx_tlast(m_axis_rx_tlast), + .m_axis_rx_tready(m_axis_rx_tready), + .m_axis_rx_tuser(m_axis_rx_tuser), + .m_axis_rx_tvalid_reg(m_axis_rx_tvalid_reg), + .out(out), + .pipe_userclk2_in(pipe_userclk2_in), + .ppm_L1_thrtl(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_thrtl ), + .ppm_L1_thrtl_reg(pcie_7x_i_n_13), + .ppm_L1_trig(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_trig ), + .reg_dsc_detect(\rx_inst/rx_pipeline_inst/reg_dsc_detect ), + .reg_tcfg_gnt(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/reg_tcfg_gnt ), + .rsrc_rdy_filtered(\rx_inst/rx_pipeline_inst/rsrc_rdy_filtered ), + .s_axis_tx_tdata(s_axis_tx_tdata), + .s_axis_tx_tkeep(s_axis_tx_tkeep), + .s_axis_tx_tlast(s_axis_tx_tlast), + .s_axis_tx_tuser(s_axis_tx_tuser), + .s_axis_tx_tvalid(s_axis_tx_tvalid), + .tbuf_av_min_trig(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tbuf_av_min_trig ), + .tcfg_req_trig(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tcfg_req_trig ), + .\throttle_ctl_pipeline.reg_tdata_reg[63] ({trn_td[31:0],trn_td[63:32]}), + .\throttle_ctl_pipeline.reg_tkeep_reg[7] (\throttle_ctl_pipeline.reg_tkeep_reg[7] ), + .\throttle_ctl_pipeline.reg_tuser_reg[3] ({trn_tsrc_dsc,trn_tstr,trn_terrfwd,trn_tecrc_gen}), + .tready_thrtl_i_5(pcie_7x_i_n_22), + .tready_thrtl_reg(tready_thrtl_reg), + .trn_in_packet(\rx_inst/rx_pipeline_inst/trn_in_packet ), + .trn_in_packet_reg(pcie_7x_i_n_9), + .trn_rbar_hit(trn_rbar_hit), + .trn_rd(trn_rd), + .trn_recrc_err(trn_recrc_err), + .trn_reof(trn_reof), + .trn_rerrfwd(trn_rerrfwd), + .trn_rrem(trn_rrem), + .trn_rsof(trn_rsof), + .trn_rsrc_dsc(trn_rsrc_dsc), + .trn_rsrc_dsc_d(\rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d ), + .trn_rsrc_dsc_prev0(\rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0 ), + .trn_tbuf_av(trn_tbuf_av), + .trn_tcfg_gnt(trn_tcfg_gnt), + .trn_tcfg_req(trn_tcfg_req), + .trn_tdst_rdy(trn_tdst_rdy), + .trn_teof(trn_teof), + .trn_trem(trn_trem), + .trn_tsof(trn_tsof), + .trn_tsrc_rdy(trn_tsrc_rdy), + .tx_cfg_gnt(tx_cfg_gnt)); + LUT1 #( + .INIT(2'h1)) + \cfg_bus_number_d[7]_i_1 + (.I0(out), + .O(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_bus_number_d_reg[0] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[8]), + .Q(cfg_bus_number[0]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_bus_number_d_reg[1] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[9]), + .Q(cfg_bus_number[1]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_bus_number_d_reg[2] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[10]), + .Q(cfg_bus_number[2]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_bus_number_d_reg[3] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[11]), + .Q(cfg_bus_number[3]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_bus_number_d_reg[4] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[12]), + .Q(cfg_bus_number[4]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_bus_number_d_reg[5] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[13]), + .Q(cfg_bus_number[5]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_bus_number_d_reg[6] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[14]), + .Q(cfg_bus_number[6]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_bus_number_d_reg[7] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[15]), + .Q(cfg_bus_number[7]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_device_number_d_reg[0] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[3]), + .Q(cfg_device_number[0]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_device_number_d_reg[1] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[4]), + .Q(cfg_device_number[1]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_device_number_d_reg[2] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[5]), + .Q(cfg_device_number[2]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_device_number_d_reg[3] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[6]), + .Q(cfg_device_number[3]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_device_number_d_reg[4] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[7]), + .Q(cfg_device_number[4]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_function_number_d_reg[0] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[0]), + .Q(cfg_function_number[0]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_function_number_d_reg[1] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[1]), + .Q(cfg_function_number[1]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + FDRE \cfg_function_number_d_reg[2] + (.C(pipe_userclk2_in), + .CE(pcie_7x_i_n_6), + .D(cfg_msg_data[2]), + .Q(cfg_function_number[2]), + .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 )); + pcie_7x_0_pcie_7x_0_pcie_7x pcie_7x_i + (.E(pcie_7x_i_n_6), + .Q(pipe_rx0_data), + .bridge_reset_int(bridge_reset_int), + .cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en), + .cfg_aer_ecrc_check_en_0({trn_tsrc_dsc,trn_tstr,trn_terrfwd,trn_tecrc_gen}), + .cfg_aer_ecrc_check_en_1(pipe_rx1_data), + .cfg_aer_ecrc_check_en_10(pipe_rx2_status), + .cfg_aer_ecrc_check_en_11(pipe_rx3_status), + .cfg_aer_ecrc_check_en_2(pipe_rx2_data), + .cfg_aer_ecrc_check_en_3(pipe_rx3_data), + .cfg_aer_ecrc_check_en_4(pipe_rx0_char_is_k), + .cfg_aer_ecrc_check_en_5(pipe_rx1_char_is_k), + .cfg_aer_ecrc_check_en_6(pipe_rx2_char_is_k), + .cfg_aer_ecrc_check_en_7(pipe_rx3_char_is_k), + .cfg_aer_ecrc_check_en_8(pipe_rx0_status), + .cfg_aer_ecrc_check_en_9(pipe_rx1_status), + .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en), + .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum), + .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received), + .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en), + .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received), + .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en), + .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received), + .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en), + .cfg_bridge_serr_en(cfg_bridge_serr_en), + .cfg_command(cfg_command), + .cfg_dcommand(cfg_dcommand), + .cfg_dcommand2(cfg_dcommand2), + .cfg_ds_bus_number(cfg_ds_bus_number), + .cfg_ds_device_number(cfg_ds_device_number), + .cfg_ds_function_number(cfg_ds_function_number), + .cfg_dsn(cfg_dsn), + .cfg_dstatus(cfg_dstatus), + .cfg_err_aer_headerlog(cfg_err_aer_headerlog), + .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set), + .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked), + .cfg_err_cor(cfg_err_cor), + .cfg_err_cpl_abort(cfg_err_cpl_abort), + .cfg_err_cpl_rdy(cfg_err_cpl_rdy), + .cfg_err_cpl_timeout(cfg_err_cpl_timeout), + .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect), + .cfg_err_ecrc(cfg_err_ecrc), + .cfg_err_internal_cor(cfg_err_internal_cor), + .cfg_err_internal_uncor(cfg_err_internal_uncor), + .cfg_err_locked(cfg_err_locked), + .cfg_err_malformed(cfg_err_malformed), + .cfg_err_mc_blocked(cfg_err_mc_blocked), + .cfg_err_norecovery(cfg_err_norecovery), + .cfg_err_poisoned(cfg_err_poisoned), + .cfg_err_posted(cfg_err_posted), + .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header), + .cfg_err_ur(cfg_err_ur), + .cfg_interrupt(cfg_interrupt), + .cfg_interrupt_assert(cfg_interrupt_assert), + .cfg_interrupt_di(cfg_interrupt_di), + .cfg_interrupt_do(cfg_interrupt_do), + .cfg_interrupt_mmenable(cfg_interrupt_mmenable), + .cfg_interrupt_msienable(cfg_interrupt_msienable), + .cfg_interrupt_msixenable(cfg_interrupt_msixenable), + .cfg_interrupt_msixfm(cfg_interrupt_msixfm), + .cfg_interrupt_rdy(cfg_interrupt_rdy), + .cfg_interrupt_stat(cfg_interrupt_stat), + .cfg_lcommand(cfg_lcommand), + .cfg_lstatus(cfg_lstatus), + .cfg_mgmt_byte_en_n(cfg_mgmt_byte_en_n), + .cfg_mgmt_di(cfg_mgmt_di), + .cfg_mgmt_do(cfg_mgmt_do), + .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr), + .cfg_mgmt_rd_en(cfg_mgmt_rd_en), + .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done), + .cfg_mgmt_wr_en(cfg_mgmt_wr_en), + .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly), + .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw), + .cfg_msg_data(cfg_msg_data), + .cfg_msg_received(cfg_msg_received), + .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a), + .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b), + .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c), + .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d), + .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a), + .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b), + .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c), + .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d), + .cfg_msg_received_err_cor(cfg_msg_received_err_cor), + .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal), + .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal), + .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak), + .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme), + .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack), + .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit), + .cfg_pcie_link_state(cfg_pcie_link_state), + .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum), + .cfg_pm_force_state(cfg_pm_force_state), + .cfg_pm_force_state_en(cfg_pm_force_state_en), + .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s), + .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1), + .cfg_pm_turnoff_ok_n(cfg_turnoff_ok_w), + .cfg_pm_wake(cfg_pm_wake), + .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en), + .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status), + .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate), + .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst), + .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en), + .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en), + .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en), + .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en), + .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse), + .cfg_to_turnoff(cfg_to_turnoff), + .cfg_trn_pending(cfg_trn_pending), + .cfg_vc_tcvc_map(cfg_vc_tcvc_map), + .dsc_detect(\rx_inst/rx_pipeline_inst/dsc_detect ), + .fc_cpld(fc_cpld), + .fc_cplh(fc_cplh), + .fc_npd(fc_npd), + .fc_nph(fc_nph), + .fc_pd(fc_pd), + .fc_ph(fc_ph), + .fc_sel(fc_sel), + .lnk_up_thrtl(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/lnk_up_thrtl ), + .lnk_up_thrtl_reg(pcie_7x_i_n_30), + .out(out), + .pcie_drp_addr(pcie_drp_addr), + .pcie_drp_clk(pcie_drp_clk), + .pcie_drp_clk_0(pcie_7x_i_n_22), + .pcie_drp_clk_1(trn_rd), + .pcie_drp_clk_2(trn_rrem), + .pcie_drp_di(pcie_drp_di), + .pcie_drp_do(pcie_drp_do), + .pcie_drp_en(pcie_drp_en), + .pcie_drp_rdy(pcie_drp_rdy), + .pcie_drp_we(pcie_drp_we), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rx0_chanisaligned(pipe_rx0_chanisaligned), + .pipe_rx0_elec_idle(pipe_rx0_elec_idle), + .pipe_rx0_phy_status(pipe_rx0_phy_status), + .pipe_rx0_polarity(pipe_rx0_polarity), + .pipe_rx0_valid(pipe_rx0_valid), + .pipe_rx1_chanisaligned(pipe_rx1_chanisaligned), + .pipe_rx1_elec_idle(pipe_rx1_elec_idle), + .pipe_rx1_phy_status(pipe_rx1_phy_status), + .pipe_rx1_polarity(pipe_rx1_polarity), + .pipe_rx1_valid(pipe_rx1_valid), + .pipe_rx2_chanisaligned(pipe_rx2_chanisaligned), + .pipe_rx2_elec_idle(pipe_rx2_elec_idle), + .pipe_rx2_phy_status(pipe_rx2_phy_status), + .pipe_rx2_polarity(pipe_rx2_polarity), + .pipe_rx2_valid(pipe_rx2_valid), + .pipe_rx3_chanisaligned(pipe_rx3_chanisaligned), + .pipe_rx3_elec_idle(pipe_rx3_elec_idle), + .pipe_rx3_phy_status(pipe_rx3_phy_status), + .pipe_rx3_polarity(pipe_rx3_polarity), + .pipe_rx3_valid(pipe_rx3_valid), + .pipe_tx0_char_is_k(pipe_tx0_char_is_k), + .pipe_tx0_compliance(pipe_tx0_compliance), + .pipe_tx0_data(pipe_tx0_data), + .pipe_tx0_elec_idle(pipe_tx0_elec_idle), + .pipe_tx0_powerdown(pipe_tx0_powerdown), + .pipe_tx1_char_is_k(pipe_tx1_char_is_k), + .pipe_tx1_compliance(pipe_tx1_compliance), + .pipe_tx1_data(pipe_tx1_data), + .pipe_tx1_elec_idle(pipe_tx1_elec_idle), + .pipe_tx1_powerdown(pipe_tx1_powerdown), + .pipe_tx2_char_is_k(pipe_tx2_char_is_k), + .pipe_tx2_compliance(pipe_tx2_compliance), + .pipe_tx2_data(pipe_tx2_data), + .pipe_tx2_elec_idle(pipe_tx2_elec_idle), + .pipe_tx2_powerdown(pipe_tx2_powerdown), + .pipe_tx3_char_is_k(pipe_tx3_char_is_k), + .pipe_tx3_compliance(pipe_tx3_compliance), + .pipe_tx3_data(pipe_tx3_data), + .pipe_tx3_elec_idle(pipe_tx3_elec_idle), + .pipe_tx3_powerdown(pipe_tx3_powerdown), + .pipe_tx_deemph(pipe_tx_deemph), + .pipe_tx_margin(pipe_tx_margin), + .pipe_tx_rate(pipe_tx_rate), + .pipe_tx_rcvr_det(pipe_tx_rcvr_det), + .pipe_userclk1_in(pipe_userclk1_in), + .pipe_userclk2_in(pipe_userclk2_in), + .pl_directed_change_done(pl_directed_change_done), + .pl_directed_link_auton(pl_directed_link_auton), + .pl_directed_link_change(pl_directed_link_change), + .pl_directed_link_speed(pl_directed_link_speed), + .pl_directed_link_width(pl_directed_link_width), + .pl_downstream_deemph_source(pl_downstream_deemph_source), + .pl_initial_link_width(pl_initial_link_width), + .pl_lane_reversal_mode(pl_lane_reversal_mode), + .pl_link_gen2_cap(pl_link_gen2_cap), + .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported), + .pl_link_upcfg_cap(pl_link_upcfg_cap), + .pl_ltssm_state(pl_ltssm_state), + .pl_phy_lnk_up(pl_phy_lnk_up), + .pl_received_hot_rst(pl_received_hot_rst), + .pl_rx_pm_state(pl_rx_pm_state), + .pl_sel_lnk_rate(pl_sel_lnk_rate), + .pl_sel_lnk_width(pl_sel_lnk_width), + .pl_transmit_hot_rst(pl_transmit_hot_rst), + .pl_tx_pm_state(pl_tx_pm_state), + .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph), + .ppm_L1_thrtl(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_thrtl ), + .ppm_L1_thrtl_reg(pcie_7x_i_n_13), + .ppm_L1_trig(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_trig ), + .reg_dsc_detect(\rx_inst/rx_pipeline_inst/reg_dsc_detect ), + .reg_tcfg_gnt(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/reg_tcfg_gnt ), + .rsrc_rdy_filtered(\rx_inst/rx_pipeline_inst/rsrc_rdy_filtered ), + .rx_np_ok(rx_np_ok), + .rx_np_req(rx_np_req), + .src_in(src_in), + .sys_rst_n(sys_rst_n), + .tbuf_av_min_trig(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tbuf_av_min_trig ), + .tcfg_req_trig(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tcfg_req_trig ), + .trn_in_packet(\rx_inst/rx_pipeline_inst/trn_in_packet ), + .trn_in_packet_reg(pcie_7x_i_n_9), + .trn_lnk_up(trn_lnk_up), + .trn_rbar_hit(trn_rbar_hit), + .trn_rdst_rdy(trn_rdst_rdy), + .trn_recrc_err(trn_recrc_err), + .trn_reof(trn_reof), + .trn_rerrfwd(trn_rerrfwd), + .trn_rsof(trn_rsof), + .trn_rsrc_dsc(trn_rsrc_dsc), + .trn_rsrc_dsc_d(\rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d ), + .trn_rsrc_dsc_prev0(\rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0 ), + .trn_tbuf_av(trn_tbuf_av), + .trn_tcfg_gnt(trn_tcfg_gnt), + .trn_tcfg_req(trn_tcfg_req), + .trn_td(trn_td), + .trn_tdst_rdy(trn_tdst_rdy), + .trn_teof(trn_teof), + .trn_trem(trn_trem), + .trn_tsof(trn_tsof), + .trn_tsrc_rdy(trn_tsrc_rdy), + .tx_err_drop(tx_err_drop), + .user_reset_int_reg(user_reset_int_reg)); + pcie_7x_0_pcie_7x_0_pcie_pipe_pipeline pcie_pipe_pipeline_i + (.D(D), + .PIPE_POWERDOWN(PIPE_POWERDOWN), + .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED), + .PIPE_RXPOLARITY(PIPE_RXPOLARITY), + .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE), + .PIPE_TXDATA(PIPE_TXDATA), + .PIPE_TXDATAK(PIPE_TXDATAK), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE), + .Q(pipe_rx1_char_is_k), + .SR(SR), + .gt_rx_phy_status_q(gt_rx_phy_status_q), + .gt_rxelecidle_q(gt_rxelecidle_q), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rx0_chanisaligned(pipe_rx0_chanisaligned), + .pipe_rx0_elec_idle(pipe_rx0_elec_idle), + .pipe_rx0_phy_status(pipe_rx0_phy_status), + .pipe_rx0_polarity(pipe_rx0_polarity), + .pipe_rx0_valid(pipe_rx0_valid), + .pipe_rx0_valid_gt(pipe_rx0_valid_gt), + .pipe_rx1_chanisaligned(pipe_rx1_chanisaligned), + .pipe_rx1_elec_idle(pipe_rx1_elec_idle), + .pipe_rx1_phy_status(pipe_rx1_phy_status), + .pipe_rx1_polarity(pipe_rx1_polarity), + .pipe_rx1_valid(pipe_rx1_valid), + .pipe_rx1_valid_gt(pipe_rx1_valid_gt), + .pipe_rx2_chanisaligned(pipe_rx2_chanisaligned), + .pipe_rx2_elec_idle(pipe_rx2_elec_idle), + .pipe_rx2_phy_status(pipe_rx2_phy_status), + .pipe_rx2_polarity(pipe_rx2_polarity), + .pipe_rx2_valid(pipe_rx2_valid), + .pipe_rx2_valid_gt(pipe_rx2_valid_gt), + .pipe_rx3_chanisaligned(pipe_rx3_chanisaligned), + .pipe_rx3_elec_idle(pipe_rx3_elec_idle), + .pipe_rx3_phy_status(pipe_rx3_phy_status), + .pipe_rx3_polarity(pipe_rx3_polarity), + .pipe_rx3_valid(pipe_rx3_valid), + .pipe_rx3_valid_gt(pipe_rx3_valid_gt), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (pipe_rx2_char_is_k), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 (pipe_rx3_char_is_k), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 (pipe_rx0_char_is_k), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ), + .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ), + .\pipe_stages_1.pipe_rx_data_q_reg[15] (pipe_rx1_data), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_0 (pipe_rx2_data), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_1 (pipe_rx3_data), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_2 (pipe_rx0_data), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_3 (\pipe_stages_1.pipe_rx_data_q_reg[15] ), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_4 (\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_5 (\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ), + .\pipe_stages_1.pipe_rx_data_q_reg[15]_6 (\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ), + .\pipe_stages_1.pipe_rx_elec_idle_q_reg (\pipe_stages_1.pipe_rx_elec_idle_q_reg ), + .\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 (\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ), + .\pipe_stages_1.pipe_rx_elec_idle_q_reg_1 (\pipe_stages_1.pipe_rx_elec_idle_q_reg_1 ), + .\pipe_stages_1.pipe_rx_phy_status_q_reg (\pipe_stages_1.pipe_rx_phy_status_q_reg ), + .\pipe_stages_1.pipe_rx_phy_status_q_reg_0 (\pipe_stages_1.pipe_rx_phy_status_q_reg_0 ), + .\pipe_stages_1.pipe_rx_phy_status_q_reg_1 (\pipe_stages_1.pipe_rx_phy_status_q_reg_1 ), + .\pipe_stages_1.pipe_rx_status_q_reg[2] (pipe_rx1_status), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_0 (pipe_rx2_status), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_1 (pipe_rx3_status), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_2 (pipe_rx0_status), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_3 (\pipe_stages_1.pipe_rx_status_q_reg[2] ), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_4 (\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_5 (\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ), + .\pipe_stages_1.pipe_rx_status_q_reg[2]_6 (\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ), + .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1] (pipe_tx0_char_is_k), + .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 (pipe_tx1_char_is_k), + .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 (pipe_tx2_char_is_k), + .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2 (pipe_tx3_char_is_k), + .\pipe_stages_1.pipe_tx_data_q_reg[15] (pipe_tx0_data), + .\pipe_stages_1.pipe_tx_data_q_reg[15]_0 (pipe_tx1_data), + .\pipe_stages_1.pipe_tx_data_q_reg[15]_1 (pipe_tx2_data), + .\pipe_stages_1.pipe_tx_data_q_reg[15]_2 (pipe_tx3_data), + .\pipe_stages_1.pipe_tx_margin_q_reg[2] (Q), + .\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 (pipe_tx_margin), + .\pipe_stages_1.pipe_tx_powerdown_q_reg[1] (pipe_tx0_powerdown), + .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 (pipe_tx1_powerdown), + .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 (pipe_tx2_powerdown), + .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2 (pipe_tx3_powerdown), + .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ), + .pipe_tx0_compliance(pipe_tx0_compliance), + .pipe_tx0_elec_idle(pipe_tx0_elec_idle), + .pipe_tx1_compliance(pipe_tx1_compliance), + .pipe_tx1_elec_idle(pipe_tx1_elec_idle), + .pipe_tx2_compliance(pipe_tx2_compliance), + .pipe_tx2_elec_idle(pipe_tx2_elec_idle), + .pipe_tx3_compliance(pipe_tx3_compliance), + .pipe_tx3_elec_idle(pipe_tx3_elec_idle), + .pipe_tx_deemph(pipe_tx_deemph), + .pipe_tx_deemph_gt(pipe_tx_deemph_gt), + .pipe_tx_rate(pipe_tx_rate), + .pipe_tx_rcvr_det(pipe_tx_rcvr_det), + .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt)); +endmodule + +module pcie_7x_0_pcie_7x_0_pipe_drp + (\fsm_reg[1]_0 , + \fsm_reg[1]_1 , + DRPDI, + DRPADDR, + DRP_DONE, + RST_DCLK_RESET, + RATE_DRP_X16X20_MODE, + pipe_dclk_in, + RATE_DRP_START, + DRP_RDY, + \rate_reg1_reg[0]_0 , + RATE_DRP_X16, + D, + DRP_GTXRESET); + output \fsm_reg[1]_0 ; + output \fsm_reg[1]_1 ; + output [15:0]DRPDI; + output [7:0]DRPADDR; + output DRP_DONE; + input RST_DCLK_RESET; + input RATE_DRP_X16X20_MODE; + input pipe_dclk_in; + input RATE_DRP_START; + input DRP_RDY; + input [0:0]\rate_reg1_reg[0]_0 ; + input RATE_DRP_X16; + input [15:0]D; + input DRP_GTXRESET; + + wire [15:0]D; + wire [7:0]DRPADDR; + wire [15:0]DRPDI; + wire DRP_DONE; + wire DRP_GTXRESET; + wire DRP_RDY; + wire RATE_DRP_START; + wire RATE_DRP_X16; + wire RATE_DRP_X16X20_MODE; + wire RST_DCLK_RESET; + wire [7:0]addr_reg; + wire \addr_reg[4]_i_1_n_0 ; + wire \addr_reg[6]_i_1_n_0 ; + wire [15:15]data_pma_rsv_a; + wire [15:0]di_reg; + wire \di_reg[0]_i_2_n_0 ; + wire \di_reg[0]_i_3_n_0 ; + wire \di_reg[11]_i_2_n_0 ; + wire \di_reg[11]_i_3_n_0 ; + wire \di_reg[11]_i_4_n_0 ; + wire \di_reg[11]_i_5_n_0 ; + wire \di_reg[12]_i_2_n_0 ; + wire \di_reg[12]_i_3_n_0 ; + wire \di_reg[13]_i_2_n_0 ; + wire \di_reg[13]_i_3_n_0 ; + wire \di_reg[14]_i_2_n_0 ; + wire \di_reg[15]_i_2_n_0 ; + wire \di_reg[1]_i_2_n_0 ; + wire \di_reg[1]_i_3_n_0 ; + wire \di_reg[2]_i_2_n_0 ; + wire \di_reg[2]_i_3_n_0 ; + wire \di_reg[3]_i_2_n_0 ; + wire \di_reg[3]_i_3_n_0 ; + wire \di_reg[4]_i_2_n_0 ; + wire \di_reg[4]_i_3_n_0 ; + wire \di_reg[4]_i_4_n_0 ; + wire \di_reg[5]_i_2_n_0 ; + wire \di_reg[5]_i_3_n_0 ; + wire \di_reg[6]_i_2_n_0 ; + wire \di_reg[6]_i_3_n_0 ; + wire \di_reg[7]_i_2_n_0 ; + wire \di_reg[7]_i_3_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg2; + wire done_i_1__0_n_0; + wire [7:0]drp_addr_0; + wire [15:0]drp_di_0; + wire [2:0]fsm; + wire fsm1; + wire \fsm[0]_i_2__0_n_0 ; + wire \fsm_reg[1]_0 ; + wire \fsm_reg[1]_1 ; + wire \fsm_reg_n_0_[0] ; + wire \fsm_reg_n_0_[1] ; + wire \fsm_reg_n_0_[2] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gtxreset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gtxreset_reg2; + wire [4:0]index; + wire \index[0]_i_1_n_0 ; + wire \index[1]_i_1_n_0 ; + wire \index[2]_i_1_n_0 ; + wire \index[3]_i_1_n_0 ; + wire \index[3]_i_2_n_0 ; + wire \index[4]_i_1_n_0 ; + wire \index[4]_i_2_n_0 ; + wire \index[4]_i_3_n_0 ; + wire [0:0]load_cnt; + wire \load_cnt[0]_i_1_n_0 ; + wire pipe_dclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_reg1; + wire [0:0]\rate_reg1_reg[0]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16x20_mode_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16x20_mode_reg2; + + LUT6 #( + .INIT(64'h1736415517364154)) + \addr_reg[0]_i_1 + (.I0(index[4]), + .I1(index[3]), + .I2(index[2]), + .I3(index[1]), + .I4(index[0]), + .I5(x16x20_mode_reg2), + .O(addr_reg[0])); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT5 #( + .INIT(32'h40500F00)) + \addr_reg[1]_i_1 + (.I0(index[4]), + .I1(index[0]), + .I2(index[3]), + .I3(index[1]), + .I4(index[2]), + .O(addr_reg[1])); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT5 #( + .INIT(32'h05105A00)) + \addr_reg[2]_i_1 + (.I0(index[4]), + .I1(index[0]), + .I2(index[3]), + .I3(index[2]), + .I4(index[1]), + .O(addr_reg[2])); + LUT6 #( + .INIT(64'h5767576753265327)) + \addr_reg[3]_i_1 + (.I0(index[4]), + .I1(index[3]), + .I2(index[2]), + .I3(index[1]), + .I4(x16x20_mode_reg2), + .I5(index[0]), + .O(addr_reg[3])); + LUT6 #( + .INIT(64'h00000000FAAFFF04)) + \addr_reg[4]_i_1 + (.I0(index[0]), + .I1(x16x20_mode_reg2), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(index[4]), + .O(\addr_reg[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT5 #( + .INIT(32'h001A0F0A)) + \addr_reg[5]_i_1 + (.I0(index[4]), + .I1(index[0]), + .I2(index[3]), + .I3(index[1]), + .I4(index[2]), + .O(addr_reg[5])); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT5 #( + .INIT(32'h00001454)) + \addr_reg[6]_i_1 + (.I0(index[2]), + .I1(index[1]), + .I2(index[3]), + .I3(index[0]), + .I4(index[4]), + .O(\addr_reg[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5252424223236263)) + \addr_reg[7]_i_1 + (.I0(index[4]), + .I1(index[3]), + .I2(index[2]), + .I3(x16x20_mode_reg2), + .I4(index[0]), + .I5(index[1]), + .O(addr_reg[7])); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[0]), + .Q(drp_addr_0[0]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[1]), + .Q(drp_addr_0[1]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[2]), + .Q(drp_addr_0[2]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[3]), + .Q(drp_addr_0[3]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\addr_reg[4]_i_1_n_0 ), + .Q(drp_addr_0[4]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[5]), + .Q(drp_addr_0[5]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\addr_reg[6]_i_1_n_0 ), + .Q(drp_addr_0[6]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[7]), + .Q(drp_addr_0[7]), + .R(RST_DCLK_RESET)); + LUT6 #( + .INIT(64'hFF5E7F6FA1001000)) + \di_reg[0]_i_2 + (.I0(index[3]), + .I1(index[2]), + .I2(index[1]), + .I3(data_pma_rsv_a), + .I4(index[0]), + .I5(do_reg2[0]), + .O(\di_reg[0]_i_2_n_0 )); + LUT5 #( + .INIT(32'h000005D0)) + \di_reg[0]_i_3 + (.I0(index[0]), + .I1(do_reg2[0]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'h45555F5540000000)) + \di_reg[10]_i_1 + (.I0(index[4]), + .I1(\di_reg[15]_i_2_n_0 ), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[10]), + .O(di_reg[10])); + LUT6 #( + .INIT(64'h4F40DDDD4F408888)) + \di_reg[11]_i_2 + (.I0(index[3]), + .I1(do_reg2[11]), + .I2(index[1]), + .I3(\di_reg[11]_i_4_n_0 ), + .I4(index[2]), + .I5(\di_reg[11]_i_5_n_0 ), + .O(\di_reg[11]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000008080838)) + \di_reg[11]_i_3 + (.I0(do_reg2[11]), + .I1(index[2]), + .I2(index[1]), + .I3(data_pma_rsv_a), + .I4(index[0]), + .I5(index[3]), + .O(\di_reg[11]_i_3_n_0 )); + LUT4 #( + .INIT(16'hB8BB)) + \di_reg[11]_i_4 + (.I0(do_reg2[11]), + .I1(index[0]), + .I2(rate_reg2[0]), + .I3(rate_reg2[1]), + .O(\di_reg[11]_i_4_n_0 )); + LUT5 #( + .INIT(32'hEFFF0100)) + \di_reg[11]_i_5 + (.I0(index[1]), + .I1(index[0]), + .I2(x16_reg2), + .I3(x16x20_mode_reg2), + .I4(do_reg2[11]), + .O(\di_reg[11]_i_5_n_0 )); + LUT6 #( + .INIT(64'h777EFFFF01080000)) + \di_reg[12]_i_2 + (.I0(index[3]), + .I1(index[1]), + .I2(index[0]), + .I3(data_pma_rsv_a), + .I4(index[2]), + .I5(do_reg2[12]), + .O(\di_reg[12]_i_2_n_0 )); + LUT5 #( + .INIT(32'h00000B08)) + \di_reg[12]_i_3 + (.I0(do_reg2[12]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(index[3]), + .O(\di_reg[12]_i_3_n_0 )); + LUT6 #( + .INIT(64'h767FFFFF00090000)) + \di_reg[13]_i_2 + (.I0(index[3]), + .I1(index[1]), + .I2(index[0]), + .I3(data_pma_rsv_a), + .I4(index[2]), + .I5(do_reg2[13]), + .O(\di_reg[13]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000008380808)) + \di_reg[13]_i_3 + (.I0(do_reg2[13]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(data_pma_rsv_a), + .I5(index[3]), + .O(\di_reg[13]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0040FFFF00400000)) + \di_reg[14]_i_1 + (.I0(index[1]), + .I1(index[2]), + .I2(do_reg2[14]), + .I3(index[3]), + .I4(index[4]), + .I5(\di_reg[14]_i_2_n_0 ), + .O(di_reg[14])); + LUT6 #( + .INIT(64'h653BFFF721080080)) + \di_reg[14]_i_2 + (.I0(index[3]), + .I1(index[1]), + .I2(data_pma_rsv_a), + .I3(index[0]), + .I4(index[2]), + .I5(do_reg2[14]), + .O(\di_reg[14]_i_2_n_0 )); + LUT2 #( + .INIT(4'hB)) + \di_reg[14]_i_3__2 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .O(data_pma_rsv_a)); + LUT6 #( + .INIT(64'h45555F5540000000)) + \di_reg[15]_i_1 + (.I0(index[4]), + .I1(\di_reg[15]_i_2_n_0 ), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[15]), + .O(di_reg[15])); + LUT3 #( + .INIT(8'h0D)) + \di_reg[15]_i_2 + (.I0(rate_reg2[1]), + .I1(rate_reg2[0]), + .I2(index[0]), + .O(\di_reg[15]_i_2_n_0 )); + LUT6 #( + .INIT(64'h5FEE4E0076FF1000)) + \di_reg[1]_i_2 + (.I0(index[3]), + .I1(index[2]), + .I2(data_pma_rsv_a), + .I3(index[1]), + .I4(do_reg2[1]), + .I5(index[0]), + .O(\di_reg[1]_i_2_n_0 )); + LUT5 #( + .INIT(32'h000005D0)) + \di_reg[1]_i_3 + (.I0(index[0]), + .I1(do_reg2[1]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h5DEE080067FF0100)) + \di_reg[2]_i_2 + (.I0(index[3]), + .I1(index[2]), + .I2(data_pma_rsv_a), + .I3(index[1]), + .I4(do_reg2[2]), + .I5(index[0]), + .O(\di_reg[2]_i_2_n_0 )); + LUT5 #( + .INIT(32'h00000380)) + \di_reg[2]_i_3 + (.I0(do_reg2[2]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'h43FFFFFF40000000)) + \di_reg[3]_i_2 + (.I0(data_pma_rsv_a), + .I1(index[2]), + .I2(index[0]), + .I3(index[1]), + .I4(index[3]), + .I5(do_reg2[3]), + .O(\di_reg[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h000000000033D100)) + \di_reg[3]_i_3 + (.I0(data_pma_rsv_a), + .I1(index[0]), + .I2(do_reg2[3]), + .I3(index[2]), + .I4(index[1]), + .I5(index[3]), + .O(\di_reg[3]_i_3_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \di_reg[4]_i_1 + (.I0(\di_reg[4]_i_2_n_0 ), + .I1(index[4]), + .I2(\di_reg[4]_i_3_n_0 ), + .I3(index[3]), + .I4(\di_reg[4]_i_4_n_0 ), + .O(di_reg[4])); + LUT6 #( + .INIT(64'h0F0400F0000400F0)) + \di_reg[4]_i_2 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .I2(index[1]), + .I3(index[2]), + .I4(index[0]), + .I5(do_reg2[4]), + .O(\di_reg[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'h400FFFFF40000000)) + \di_reg[4]_i_3 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .I2(index[2]), + .I3(index[0]), + .I4(index[1]), + .I5(do_reg2[4]), + .O(\di_reg[4]_i_3_n_0 )); + LUT6 #( + .INIT(64'hBF00BF01FF40FE40)) + \di_reg[4]_i_4 + (.I0(index[2]), + .I1(index[1]), + .I2(index[0]), + .I3(do_reg2[4]), + .I4(x16x20_mode_reg2), + .I5(data_pma_rsv_a), + .O(\di_reg[4]_i_4_n_0 )); + LUT6 #( + .INIT(64'h7F7F7F7E00000000)) + \di_reg[5]_i_2 + (.I0(index[3]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(x16x20_mode_reg2), + .I5(do_reg2[5]), + .O(\di_reg[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'h00000000038F0380)) + \di_reg[5]_i_3 + (.I0(do_reg2[5]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(data_pma_rsv_a), + .I5(index[3]), + .O(\di_reg[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'h7D7F7D7E00000000)) + \di_reg[6]_i_2 + (.I0(index[3]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(x16x20_mode_reg2), + .I5(do_reg2[6]), + .O(\di_reg[6]_i_2_n_0 )); + LUT5 #( + .INIT(32'h00000380)) + \di_reg[6]_i_3 + (.I0(do_reg2[6]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[6]_i_3_n_0 )); + LUT5 #( + .INIT(32'h7FFF0900)) + \di_reg[7]_i_2 + (.I0(index[2]), + .I1(index[1]), + .I2(index[0]), + .I3(index[3]), + .I4(do_reg2[7]), + .O(\di_reg[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000003800383)) + \di_reg[7]_i_3 + (.I0(do_reg2[7]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(data_pma_rsv_a), + .I5(index[3]), + .O(\di_reg[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'h03333F7300000040)) + \di_reg[8]_i_1 + (.I0(index[0]), + .I1(index[4]), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[8]), + .O(di_reg[8])); + LUT6 #( + .INIT(64'h03333F7300000040)) + \di_reg[9]_i_1 + (.I0(index[0]), + .I1(index[4]), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[9]), + .O(di_reg[9])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[0]), + .Q(drp_di_0[0]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[0]_i_1 + (.I0(\di_reg[0]_i_2_n_0 ), + .I1(\di_reg[0]_i_3_n_0 ), + .O(di_reg[0]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[10]), + .Q(drp_di_0[10]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[11]), + .Q(drp_di_0[11]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[11]_i_1 + (.I0(\di_reg[11]_i_2_n_0 ), + .I1(\di_reg[11]_i_3_n_0 ), + .O(di_reg[11]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[12]), + .Q(drp_di_0[12]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[12]_i_1 + (.I0(\di_reg[12]_i_2_n_0 ), + .I1(\di_reg[12]_i_3_n_0 ), + .O(di_reg[12]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[13]), + .Q(drp_di_0[13]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[13]_i_1 + (.I0(\di_reg[13]_i_2_n_0 ), + .I1(\di_reg[13]_i_3_n_0 ), + .O(di_reg[13]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[14]), + .Q(drp_di_0[14]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[15]), + .Q(drp_di_0[15]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[1]), + .Q(drp_di_0[1]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[1]_i_1 + (.I0(\di_reg[1]_i_2_n_0 ), + .I1(\di_reg[1]_i_3_n_0 ), + .O(di_reg[1]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[2]), + .Q(drp_di_0[2]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[2]_i_1 + (.I0(\di_reg[2]_i_2_n_0 ), + .I1(\di_reg[2]_i_3_n_0 ), + .O(di_reg[2]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[3]), + .Q(drp_di_0[3]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[3]_i_1 + (.I0(\di_reg[3]_i_2_n_0 ), + .I1(\di_reg[3]_i_3_n_0 ), + .O(di_reg[3]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[4]), + .Q(drp_di_0[4]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[5]), + .Q(drp_di_0[5]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[5]_i_1 + (.I0(\di_reg[5]_i_2_n_0 ), + .I1(\di_reg[5]_i_3_n_0 ), + .O(di_reg[5]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[6]), + .Q(drp_di_0[6]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[6]_i_1 + (.I0(\di_reg[6]_i_2_n_0 ), + .I1(\di_reg[6]_i_3_n_0 ), + .O(di_reg[6]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[7]), + .Q(drp_di_0[7]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[7]_i_1 + (.I0(\di_reg[7]_i_2_n_0 ), + .I1(\di_reg[7]_i_3_n_0 ), + .O(di_reg[7]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[8]), + .Q(drp_di_0[8]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[9]), + .Q(drp_di_0[9]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[0]), + .Q(do_reg1[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[10]), + .Q(do_reg1[10]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[11]), + .Q(do_reg1[11]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[12]), + .Q(do_reg1[12]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[13]), + .Q(do_reg1[13]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[14]), + .Q(do_reg1[14]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[15]), + .Q(do_reg1[15]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[1]), + .Q(do_reg1[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[2]), + .Q(do_reg1[2]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[3]), + .Q(do_reg1[3]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[4]), + .Q(do_reg1[4]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[5]), + .Q(do_reg1[5]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[6]), + .Q(do_reg1[6]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[7]), + .Q(do_reg1[7]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[8]), + .Q(do_reg1[8]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[9]), + .Q(do_reg1[9]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[0]), + .Q(do_reg2[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[10]), + .Q(do_reg2[10]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[11]), + .Q(do_reg2[11]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[12]), + .Q(do_reg2[12]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[13]), + .Q(do_reg2[13]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[14]), + .Q(do_reg2[14]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[15]), + .Q(do_reg2[15]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[1]), + .Q(do_reg2[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[2]), + .Q(do_reg2[2]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[3]), + .Q(do_reg2[3]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[4]), + .Q(do_reg2[4]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[5]), + .Q(do_reg2[5]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[6]), + .Q(do_reg2[6]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[7]), + .Q(do_reg2[7]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[8]), + .Q(do_reg2[8]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[9]), + .Q(do_reg2[9]), + .R(RST_DCLK_RESET)); + LUT4 #( + .INIT(16'h0001)) + done_i_1__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(start_reg2), + .I3(\fsm_reg_n_0_[1] ), + .O(done_i_1__0_n_0)); + FDRE #( + .INIT(1'b0)) + done_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(done_i_1__0_n_0), + .Q(DRP_DONE), + .R(RST_DCLK_RESET)); + LUT6 #( + .INIT(64'h0737FFFF07370000)) + \fsm[0]_i_1__0 + (.I0(fsm1), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(rdy_reg2), + .I4(\fsm_reg_n_0_[2] ), + .I5(\fsm[0]_i_2__0_n_0 ), + .O(fsm[0])); + LUT5 #( + .INIT(32'h47FF47CC)) + \fsm[0]_i_2__0 + (.I0(rdy_reg2), + .I1(\fsm_reg_n_0_[1] ), + .I2(load_cnt), + .I3(\fsm_reg_n_0_[0] ), + .I4(start_reg2), + .O(\fsm[0]_i_2__0_n_0 )); + LUT5 #( + .INIT(32'h1D501850)) + \fsm[1]_i_1__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(rdy_reg2), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(load_cnt), + .O(fsm[1])); + LUT4 #( + .INIT(16'h6222)) + \fsm[2]_i_1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(rdy_reg2), + .O(fsm[2])); + FDRE #( + .INIT(1'b0)) + \fsm_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(fsm[0]), + .Q(\fsm_reg_n_0_[0] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \fsm_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(fsm[1]), + .Q(\fsm_reg_n_0_[1] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \fsm_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(fsm[2]), + .Q(\fsm_reg_n_0_[2] ), + .R(RST_DCLK_RESET)); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_10 + (.I0(drp_di_0[11]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[11])); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_11 + (.I0(drp_di_0[10]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[10])); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_12 + (.I0(drp_di_0[9]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[9])); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_13 + (.I0(drp_di_0[8]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[8])); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_14 + (.I0(drp_di_0[7]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[7])); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_15 + (.I0(drp_di_0[6]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[6])); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_16 + (.I0(drp_di_0[5]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[5])); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_17 + (.I0(drp_di_0[4]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[4])); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_18 + (.I0(drp_di_0[3]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[3])); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_19 + (.I0(drp_di_0[2]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[2])); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_20 + (.I0(drp_di_0[1]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[1])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_21 + (.I0(drp_di_0[0]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[0])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'h12)) + \gtx_channel.gtxe2_channel_i_i_3 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\fsm_reg[1]_0 )); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_39__0 + (.I0(drp_addr_0[7]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[7])); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'h10)) + \gtx_channel.gtxe2_channel_i_i_4 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\fsm_reg[1]_1 )); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_40 + (.I0(drp_addr_0[6]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[6])); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_41 + (.I0(drp_addr_0[5]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[5])); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_42 + (.I0(drp_addr_0[4]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[4])); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_43 + (.I0(drp_addr_0[3]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[3])); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_44 + (.I0(drp_addr_0[2]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[2])); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_45 + (.I0(drp_addr_0[1]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[1])); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_46 + (.I0(drp_addr_0[0]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[0])); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_6 + (.I0(drp_di_0[15]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[15])); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_7 + (.I0(drp_di_0[14]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[14])); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_8 + (.I0(drp_di_0[13]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[13])); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_9 + (.I0(drp_di_0[12]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[12])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gtxreset_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(DRP_GTXRESET), + .Q(gtxreset_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gtxreset_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(gtxreset_reg1), + .Q(gtxreset_reg2), + .R(RST_DCLK_RESET)); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT4 #( + .INIT(16'h0100)) + \index[0]_i_1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(fsm1), + .I2(index[0]), + .I3(\fsm_reg_n_0_[2] ), + .O(\index[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT5 #( + .INIT(32'h00140000)) + \index[1]_i_1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[1]), + .I2(index[0]), + .I3(fsm1), + .I4(\fsm_reg_n_0_[2] ), + .O(\index[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000144400000000)) + \index[2]_i_1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(fsm1), + .I5(\fsm_reg_n_0_[2] ), + .O(\index[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000144400000000)) + \index[3]_i_1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[3]), + .I2(index[2]), + .I3(\index[3]_i_2_n_0 ), + .I4(fsm1), + .I5(\fsm_reg_n_0_[2] ), + .O(\index[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT2 #( + .INIT(4'h8)) + \index[3]_i_2 + (.I0(index[1]), + .I1(index[0]), + .O(\index[3]_i_2_n_0 )); + LUT3 #( + .INIT(8'hA1)) + \index[4]_i_1 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\index[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000144400000000)) + \index[4]_i_2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[4]), + .I2(index[3]), + .I3(\index[4]_i_3_n_0 ), + .I4(fsm1), + .I5(\fsm_reg_n_0_[2] ), + .O(\index[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT3 #( + .INIT(8'h80)) + \index[4]_i_3 + (.I0(index[2]), + .I1(index[0]), + .I2(index[1]), + .O(\index[4]_i_3_n_0 )); + LUT6 #( + .INIT(64'h1000000110000000)) + \index[4]_i_4 + (.I0(index[3]), + .I1(index[1]), + .I2(index[0]), + .I3(index[4]), + .I4(index[2]), + .I5(x16x20_mode_reg2), + .O(fsm1)); + FDRE #( + .INIT(1'b0)) + \index_reg[0] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1_n_0 ), + .D(\index[0]_i_1_n_0 ), + .Q(index[0]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[1] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1_n_0 ), + .D(\index[1]_i_1_n_0 ), + .Q(index[1]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[2] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1_n_0 ), + .D(\index[2]_i_1_n_0 ), + .Q(index[2]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[3] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1_n_0 ), + .D(\index[3]_i_1_n_0 ), + .Q(index[3]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[4] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1_n_0 ), + .D(\index[4]_i_2_n_0 ), + .Q(index[4]), + .R(RST_DCLK_RESET)); + LUT3 #( + .INIT(8'h10)) + \load_cnt[0]_i_1 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .O(\load_cnt[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \load_cnt_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\load_cnt[0]_i_1_n_0 ), + .Q(load_cnt), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg1_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\rate_reg1_reg[0]_0 ), + .Q(rate_reg1[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg1_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rate_reg1[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg2_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(rate_reg1[0]), + .Q(rate_reg2[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg2_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(rate_reg1[1]), + .Q(rate_reg2[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rdy_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(DRP_RDY), + .Q(rdy_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rdy_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(rdy_reg1), + .Q(rdy_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE start_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(RATE_DRP_START), + .Q(start_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE start_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(start_reg1), + .Q(start_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(RATE_DRP_X16), + .Q(x16_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(x16_reg1), + .Q(x16_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16x20_mode_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(RATE_DRP_X16X20_MODE), + .Q(x16x20_mode_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16x20_mode_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(x16x20_mode_reg1), + .Q(x16x20_mode_reg2), + .R(RST_DCLK_RESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_drp" *) +module pcie_7x_0_pcie_7x_0_pipe_drp_38 + (\fsm_reg[1]_0 , + \fsm_reg[1]_1 , + DRPADDR, + DRPDI, + DRP_DONE, + RST_DCLK_RESET, + RATE_DRP_X16X20_MODE, + pipe_dclk_in, + RATE_DRP_START, + DRP_RDY, + \rate_reg1_reg[0]_0 , + RATE_DRP_X16, + D, + DRP_GTXRESET); + output \fsm_reg[1]_0 ; + output \fsm_reg[1]_1 ; + output [7:0]DRPADDR; + output [15:0]DRPDI; + output DRP_DONE; + input RST_DCLK_RESET; + input RATE_DRP_X16X20_MODE; + input pipe_dclk_in; + input RATE_DRP_START; + input DRP_RDY; + input [0:0]\rate_reg1_reg[0]_0 ; + input RATE_DRP_X16; + input [15:0]D; + input DRP_GTXRESET; + + wire [15:0]D; + wire [7:0]DRPADDR; + wire [15:0]DRPDI; + wire DRP_DONE; + wire DRP_GTXRESET; + wire DRP_RDY; + wire RATE_DRP_START; + wire RATE_DRP_X16; + wire RATE_DRP_X16X20_MODE; + wire RST_DCLK_RESET; + wire [7:0]addr_reg; + wire \addr_reg[4]_i_1__0_n_0 ; + wire \addr_reg[6]_i_1__0_n_0 ; + wire [15:15]data_pma_rsv_a; + wire [15:0]di_reg; + wire \di_reg[0]_i_2__0_n_0 ; + wire \di_reg[0]_i_3__0_n_0 ; + wire \di_reg[11]_i_2__0_n_0 ; + wire \di_reg[11]_i_3__0_n_0 ; + wire \di_reg[11]_i_4__0_n_0 ; + wire \di_reg[11]_i_5__0_n_0 ; + wire \di_reg[12]_i_2__0_n_0 ; + wire \di_reg[12]_i_3__0_n_0 ; + wire \di_reg[13]_i_2__0_n_0 ; + wire \di_reg[13]_i_3__0_n_0 ; + wire \di_reg[14]_i_2__0_n_0 ; + wire \di_reg[15]_i_2__0_n_0 ; + wire \di_reg[1]_i_2__0_n_0 ; + wire \di_reg[1]_i_3__0_n_0 ; + wire \di_reg[2]_i_2__0_n_0 ; + wire \di_reg[2]_i_3__0_n_0 ; + wire \di_reg[3]_i_2__0_n_0 ; + wire \di_reg[3]_i_3__0_n_0 ; + wire \di_reg[4]_i_2__0_n_0 ; + wire \di_reg[4]_i_3__0_n_0 ; + wire \di_reg[4]_i_4__0_n_0 ; + wire \di_reg[5]_i_2__0_n_0 ; + wire \di_reg[5]_i_3__0_n_0 ; + wire \di_reg[6]_i_2__0_n_0 ; + wire \di_reg[6]_i_3__0_n_0 ; + wire \di_reg[7]_i_2__0_n_0 ; + wire \di_reg[7]_i_3__0_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg2; + wire done_i_1__1_n_0; + wire [7:0]drp_addr_9; + wire [15:0]drp_di_16; + wire [2:0]fsm; + wire fsm1; + wire \fsm[0]_i_2__3_n_0 ; + wire \fsm_reg[1]_0 ; + wire \fsm_reg[1]_1 ; + wire \fsm_reg_n_0_[0] ; + wire \fsm_reg_n_0_[1] ; + wire \fsm_reg_n_0_[2] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gtxreset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gtxreset_reg2; + wire [4:0]index; + wire \index[0]_i_1__0_n_0 ; + wire \index[1]_i_1__0_n_0 ; + wire \index[2]_i_1__0_n_0 ; + wire \index[3]_i_1__0_n_0 ; + wire \index[3]_i_2__0_n_0 ; + wire \index[4]_i_1__0_n_0 ; + wire \index[4]_i_2__0_n_0 ; + wire \index[4]_i_3__0_n_0 ; + wire [0:0]load_cnt; + wire \load_cnt[0]_i_1__1_n_0 ; + wire pipe_dclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_reg1; + wire [0:0]\rate_reg1_reg[0]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16x20_mode_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16x20_mode_reg2; + + LUT6 #( + .INIT(64'h1736415517364154)) + \addr_reg[0]_i_1__0 + (.I0(index[4]), + .I1(index[3]), + .I2(index[2]), + .I3(index[1]), + .I4(index[0]), + .I5(x16x20_mode_reg2), + .O(addr_reg[0])); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT5 #( + .INIT(32'h40500F00)) + \addr_reg[1]_i_1__0 + (.I0(index[4]), + .I1(index[0]), + .I2(index[3]), + .I3(index[1]), + .I4(index[2]), + .O(addr_reg[1])); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT5 #( + .INIT(32'h05105A00)) + \addr_reg[2]_i_1__0 + (.I0(index[4]), + .I1(index[0]), + .I2(index[3]), + .I3(index[2]), + .I4(index[1]), + .O(addr_reg[2])); + LUT6 #( + .INIT(64'h5767576753265327)) + \addr_reg[3]_i_1__0 + (.I0(index[4]), + .I1(index[3]), + .I2(index[2]), + .I3(index[1]), + .I4(x16x20_mode_reg2), + .I5(index[0]), + .O(addr_reg[3])); + LUT6 #( + .INIT(64'h00000000FAAFFF04)) + \addr_reg[4]_i_1__0 + (.I0(index[0]), + .I1(x16x20_mode_reg2), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(index[4]), + .O(\addr_reg[4]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT5 #( + .INIT(32'h001A0F0A)) + \addr_reg[5]_i_1__0 + (.I0(index[4]), + .I1(index[0]), + .I2(index[3]), + .I3(index[1]), + .I4(index[2]), + .O(addr_reg[5])); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT5 #( + .INIT(32'h00001454)) + \addr_reg[6]_i_1__0 + (.I0(index[2]), + .I1(index[1]), + .I2(index[3]), + .I3(index[0]), + .I4(index[4]), + .O(\addr_reg[6]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'h5252424223236263)) + \addr_reg[7]_i_1__0 + (.I0(index[4]), + .I1(index[3]), + .I2(index[2]), + .I3(x16x20_mode_reg2), + .I4(index[0]), + .I5(index[1]), + .O(addr_reg[7])); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[0]), + .Q(drp_addr_9[0]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[1]), + .Q(drp_addr_9[1]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[2]), + .Q(drp_addr_9[2]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[3]), + .Q(drp_addr_9[3]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\addr_reg[4]_i_1__0_n_0 ), + .Q(drp_addr_9[4]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[5]), + .Q(drp_addr_9[5]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\addr_reg[6]_i_1__0_n_0 ), + .Q(drp_addr_9[6]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[7]), + .Q(drp_addr_9[7]), + .R(RST_DCLK_RESET)); + LUT6 #( + .INIT(64'hFF5E7F6FA1001000)) + \di_reg[0]_i_2__0 + (.I0(index[3]), + .I1(index[2]), + .I2(index[1]), + .I3(data_pma_rsv_a), + .I4(index[0]), + .I5(do_reg2[0]), + .O(\di_reg[0]_i_2__0_n_0 )); + LUT5 #( + .INIT(32'h000005D0)) + \di_reg[0]_i_3__0 + (.I0(index[0]), + .I1(do_reg2[0]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[0]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h45555F5540000000)) + \di_reg[10]_i_1__0 + (.I0(index[4]), + .I1(\di_reg[15]_i_2__0_n_0 ), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[10]), + .O(di_reg[10])); + LUT6 #( + .INIT(64'h4F40DDDD4F408888)) + \di_reg[11]_i_2__0 + (.I0(index[3]), + .I1(do_reg2[11]), + .I2(index[1]), + .I3(\di_reg[11]_i_4__0_n_0 ), + .I4(index[2]), + .I5(\di_reg[11]_i_5__0_n_0 ), + .O(\di_reg[11]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h0000000008080838)) + \di_reg[11]_i_3__0 + (.I0(do_reg2[11]), + .I1(index[2]), + .I2(index[1]), + .I3(data_pma_rsv_a), + .I4(index[0]), + .I5(index[3]), + .O(\di_reg[11]_i_3__0_n_0 )); + LUT4 #( + .INIT(16'hB8BB)) + \di_reg[11]_i_4__0 + (.I0(do_reg2[11]), + .I1(index[0]), + .I2(rate_reg2[0]), + .I3(rate_reg2[1]), + .O(\di_reg[11]_i_4__0_n_0 )); + LUT5 #( + .INIT(32'hEFFF0100)) + \di_reg[11]_i_5__0 + (.I0(index[1]), + .I1(index[0]), + .I2(x16_reg2), + .I3(x16x20_mode_reg2), + .I4(do_reg2[11]), + .O(\di_reg[11]_i_5__0_n_0 )); + LUT6 #( + .INIT(64'h777EFFFF01080000)) + \di_reg[12]_i_2__0 + (.I0(index[3]), + .I1(index[1]), + .I2(index[0]), + .I3(data_pma_rsv_a), + .I4(index[2]), + .I5(do_reg2[12]), + .O(\di_reg[12]_i_2__0_n_0 )); + LUT5 #( + .INIT(32'h00000B08)) + \di_reg[12]_i_3__0 + (.I0(do_reg2[12]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(index[3]), + .O(\di_reg[12]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h767FFFFF00090000)) + \di_reg[13]_i_2__0 + (.I0(index[3]), + .I1(index[1]), + .I2(index[0]), + .I3(data_pma_rsv_a), + .I4(index[2]), + .I5(do_reg2[13]), + .O(\di_reg[13]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h0000000008380808)) + \di_reg[13]_i_3__0 + (.I0(do_reg2[13]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(data_pma_rsv_a), + .I5(index[3]), + .O(\di_reg[13]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h0040FFFF00400000)) + \di_reg[14]_i_1__0 + (.I0(index[1]), + .I1(index[2]), + .I2(do_reg2[14]), + .I3(index[3]), + .I4(index[4]), + .I5(\di_reg[14]_i_2__0_n_0 ), + .O(di_reg[14])); + LUT6 #( + .INIT(64'h653BFFF721080080)) + \di_reg[14]_i_2__0 + (.I0(index[3]), + .I1(index[1]), + .I2(data_pma_rsv_a), + .I3(index[0]), + .I4(index[2]), + .I5(do_reg2[14]), + .O(\di_reg[14]_i_2__0_n_0 )); + LUT2 #( + .INIT(4'hB)) + \di_reg[14]_i_3__1 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .O(data_pma_rsv_a)); + LUT6 #( + .INIT(64'h45555F5540000000)) + \di_reg[15]_i_1__0 + (.I0(index[4]), + .I1(\di_reg[15]_i_2__0_n_0 ), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[15]), + .O(di_reg[15])); + LUT3 #( + .INIT(8'h0D)) + \di_reg[15]_i_2__0 + (.I0(rate_reg2[1]), + .I1(rate_reg2[0]), + .I2(index[0]), + .O(\di_reg[15]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h5FEE4E0076FF1000)) + \di_reg[1]_i_2__0 + (.I0(index[3]), + .I1(index[2]), + .I2(data_pma_rsv_a), + .I3(index[1]), + .I4(do_reg2[1]), + .I5(index[0]), + .O(\di_reg[1]_i_2__0_n_0 )); + LUT5 #( + .INIT(32'h000005D0)) + \di_reg[1]_i_3__0 + (.I0(index[0]), + .I1(do_reg2[1]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[1]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h5DEE080067FF0100)) + \di_reg[2]_i_2__0 + (.I0(index[3]), + .I1(index[2]), + .I2(data_pma_rsv_a), + .I3(index[1]), + .I4(do_reg2[2]), + .I5(index[0]), + .O(\di_reg[2]_i_2__0_n_0 )); + LUT5 #( + .INIT(32'h00000380)) + \di_reg[2]_i_3__0 + (.I0(do_reg2[2]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[2]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h43FFFFFF40000000)) + \di_reg[3]_i_2__0 + (.I0(data_pma_rsv_a), + .I1(index[2]), + .I2(index[0]), + .I3(index[1]), + .I4(index[3]), + .I5(do_reg2[3]), + .O(\di_reg[3]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h000000000033D100)) + \di_reg[3]_i_3__0 + (.I0(data_pma_rsv_a), + .I1(index[0]), + .I2(do_reg2[3]), + .I3(index[2]), + .I4(index[1]), + .I5(index[3]), + .O(\di_reg[3]_i_3__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \di_reg[4]_i_1__0 + (.I0(\di_reg[4]_i_2__0_n_0 ), + .I1(index[4]), + .I2(\di_reg[4]_i_3__0_n_0 ), + .I3(index[3]), + .I4(\di_reg[4]_i_4__0_n_0 ), + .O(di_reg[4])); + LUT6 #( + .INIT(64'h0F0400F0000400F0)) + \di_reg[4]_i_2__0 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .I2(index[1]), + .I3(index[2]), + .I4(index[0]), + .I5(do_reg2[4]), + .O(\di_reg[4]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h400FFFFF40000000)) + \di_reg[4]_i_3__0 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .I2(index[2]), + .I3(index[0]), + .I4(index[1]), + .I5(do_reg2[4]), + .O(\di_reg[4]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hBF00BF01FF40FE40)) + \di_reg[4]_i_4__0 + (.I0(index[2]), + .I1(index[1]), + .I2(index[0]), + .I3(do_reg2[4]), + .I4(x16x20_mode_reg2), + .I5(data_pma_rsv_a), + .O(\di_reg[4]_i_4__0_n_0 )); + LUT6 #( + .INIT(64'h7F7F7F7E00000000)) + \di_reg[5]_i_2__0 + (.I0(index[3]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(x16x20_mode_reg2), + .I5(do_reg2[5]), + .O(\di_reg[5]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h00000000038F0380)) + \di_reg[5]_i_3__0 + (.I0(do_reg2[5]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(data_pma_rsv_a), + .I5(index[3]), + .O(\di_reg[5]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h7D7F7D7E00000000)) + \di_reg[6]_i_2__0 + (.I0(index[3]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(x16x20_mode_reg2), + .I5(do_reg2[6]), + .O(\di_reg[6]_i_2__0_n_0 )); + LUT5 #( + .INIT(32'h00000380)) + \di_reg[6]_i_3__0 + (.I0(do_reg2[6]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[6]_i_3__0_n_0 )); + LUT5 #( + .INIT(32'h7FFF0900)) + \di_reg[7]_i_2__0 + (.I0(index[2]), + .I1(index[1]), + .I2(index[0]), + .I3(index[3]), + .I4(do_reg2[7]), + .O(\di_reg[7]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h0000000003800383)) + \di_reg[7]_i_3__0 + (.I0(do_reg2[7]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(data_pma_rsv_a), + .I5(index[3]), + .O(\di_reg[7]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h03333F7300000040)) + \di_reg[8]_i_1__0 + (.I0(index[0]), + .I1(index[4]), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[8]), + .O(di_reg[8])); + LUT6 #( + .INIT(64'h03333F7300000040)) + \di_reg[9]_i_1__0 + (.I0(index[0]), + .I1(index[4]), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[9]), + .O(di_reg[9])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[0]), + .Q(drp_di_16[0]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[0]_i_1__0 + (.I0(\di_reg[0]_i_2__0_n_0 ), + .I1(\di_reg[0]_i_3__0_n_0 ), + .O(di_reg[0]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[10]), + .Q(drp_di_16[10]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[11]), + .Q(drp_di_16[11]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[11]_i_1__0 + (.I0(\di_reg[11]_i_2__0_n_0 ), + .I1(\di_reg[11]_i_3__0_n_0 ), + .O(di_reg[11]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[12]), + .Q(drp_di_16[12]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[12]_i_1__0 + (.I0(\di_reg[12]_i_2__0_n_0 ), + .I1(\di_reg[12]_i_3__0_n_0 ), + .O(di_reg[12]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[13]), + .Q(drp_di_16[13]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[13]_i_1__0 + (.I0(\di_reg[13]_i_2__0_n_0 ), + .I1(\di_reg[13]_i_3__0_n_0 ), + .O(di_reg[13]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[14]), + .Q(drp_di_16[14]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[15]), + .Q(drp_di_16[15]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[1]), + .Q(drp_di_16[1]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[1]_i_1__0 + (.I0(\di_reg[1]_i_2__0_n_0 ), + .I1(\di_reg[1]_i_3__0_n_0 ), + .O(di_reg[1]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[2]), + .Q(drp_di_16[2]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[2]_i_1__0 + (.I0(\di_reg[2]_i_2__0_n_0 ), + .I1(\di_reg[2]_i_3__0_n_0 ), + .O(di_reg[2]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[3]), + .Q(drp_di_16[3]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[3]_i_1__0 + (.I0(\di_reg[3]_i_2__0_n_0 ), + .I1(\di_reg[3]_i_3__0_n_0 ), + .O(di_reg[3]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[4]), + .Q(drp_di_16[4]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[5]), + .Q(drp_di_16[5]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[5]_i_1__0 + (.I0(\di_reg[5]_i_2__0_n_0 ), + .I1(\di_reg[5]_i_3__0_n_0 ), + .O(di_reg[5]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[6]), + .Q(drp_di_16[6]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[6]_i_1__0 + (.I0(\di_reg[6]_i_2__0_n_0 ), + .I1(\di_reg[6]_i_3__0_n_0 ), + .O(di_reg[6]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[7]), + .Q(drp_di_16[7]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[7]_i_1__0 + (.I0(\di_reg[7]_i_2__0_n_0 ), + .I1(\di_reg[7]_i_3__0_n_0 ), + .O(di_reg[7]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[8]), + .Q(drp_di_16[8]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[9]), + .Q(drp_di_16[9]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[0]), + .Q(do_reg1[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[10]), + .Q(do_reg1[10]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[11]), + .Q(do_reg1[11]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[12]), + .Q(do_reg1[12]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[13]), + .Q(do_reg1[13]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[14]), + .Q(do_reg1[14]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[15]), + .Q(do_reg1[15]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[1]), + .Q(do_reg1[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[2]), + .Q(do_reg1[2]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[3]), + .Q(do_reg1[3]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[4]), + .Q(do_reg1[4]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[5]), + .Q(do_reg1[5]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[6]), + .Q(do_reg1[6]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[7]), + .Q(do_reg1[7]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[8]), + .Q(do_reg1[8]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[9]), + .Q(do_reg1[9]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[0]), + .Q(do_reg2[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[10]), + .Q(do_reg2[10]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[11]), + .Q(do_reg2[11]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[12]), + .Q(do_reg2[12]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[13]), + .Q(do_reg2[13]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[14]), + .Q(do_reg2[14]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[15]), + .Q(do_reg2[15]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[1]), + .Q(do_reg2[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[2]), + .Q(do_reg2[2]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[3]), + .Q(do_reg2[3]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[4]), + .Q(do_reg2[4]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[5]), + .Q(do_reg2[5]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[6]), + .Q(do_reg2[6]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[7]), + .Q(do_reg2[7]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[8]), + .Q(do_reg2[8]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[9]), + .Q(do_reg2[9]), + .R(RST_DCLK_RESET)); + LUT4 #( + .INIT(16'h0001)) + done_i_1__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(start_reg2), + .I3(\fsm_reg_n_0_[1] ), + .O(done_i_1__1_n_0)); + FDRE #( + .INIT(1'b0)) + done_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(done_i_1__1_n_0), + .Q(DRP_DONE), + .R(RST_DCLK_RESET)); + LUT6 #( + .INIT(64'h0737FFFF07370000)) + \fsm[0]_i_1__3 + (.I0(fsm1), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(rdy_reg2), + .I4(\fsm_reg_n_0_[2] ), + .I5(\fsm[0]_i_2__3_n_0 ), + .O(fsm[0])); + LUT5 #( + .INIT(32'h47FF47CC)) + \fsm[0]_i_2__3 + (.I0(rdy_reg2), + .I1(\fsm_reg_n_0_[1] ), + .I2(load_cnt), + .I3(\fsm_reg_n_0_[0] ), + .I4(start_reg2), + .O(\fsm[0]_i_2__3_n_0 )); + LUT5 #( + .INIT(32'h1D501850)) + \fsm[1]_i_1__3 + (.I0(\fsm_reg_n_0_[2] ), + .I1(rdy_reg2), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(load_cnt), + .O(fsm[1])); + LUT4 #( + .INIT(16'h6222)) + \fsm[2]_i_1__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(rdy_reg2), + .O(fsm[2])); + FDRE #( + .INIT(1'b0)) + \fsm_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(fsm[0]), + .Q(\fsm_reg_n_0_[0] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \fsm_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(fsm[1]), + .Q(\fsm_reg_n_0_[1] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \fsm_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(fsm[2]), + .Q(\fsm_reg_n_0_[2] ), + .R(RST_DCLK_RESET)); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_10__0 + (.I0(drp_di_16[11]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[11])); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_11__0 + (.I0(drp_di_16[10]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[10])); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_12__0 + (.I0(drp_di_16[9]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[9])); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_13__0 + (.I0(drp_di_16[8]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[8])); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_14__0 + (.I0(drp_di_16[7]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[7])); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_15__0 + (.I0(drp_di_16[6]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[6])); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_16__0 + (.I0(drp_di_16[5]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[5])); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_17__0 + (.I0(drp_di_16[4]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[4])); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_18__0 + (.I0(drp_di_16[3]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[3])); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_19__0 + (.I0(drp_di_16[2]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[2])); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_20__0 + (.I0(drp_di_16[1]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[1])); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_21__0 + (.I0(drp_di_16[0]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[0])); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_39__1 + (.I0(drp_addr_9[7]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[7])); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT3 #( + .INIT(8'h12)) + \gtx_channel.gtxe2_channel_i_i_3__0 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\fsm_reg[1]_0 )); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_40__0 + (.I0(drp_addr_9[6]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[6])); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_41__0 + (.I0(drp_addr_9[5]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[5])); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_42__0 + (.I0(drp_addr_9[4]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[4])); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_43__0 + (.I0(drp_addr_9[3]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[3])); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_44__0 + (.I0(drp_addr_9[2]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[2])); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_45__0 + (.I0(drp_addr_9[1]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[1])); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_46__0 + (.I0(drp_addr_9[0]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[0])); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT3 #( + .INIT(8'h10)) + \gtx_channel.gtxe2_channel_i_i_4__0 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\fsm_reg[1]_1 )); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_6__0 + (.I0(drp_di_16[15]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[15])); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_7__0 + (.I0(drp_di_16[14]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[14])); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_8__0 + (.I0(drp_di_16[13]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[13])); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_9__0 + (.I0(drp_di_16[12]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[12])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gtxreset_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(DRP_GTXRESET), + .Q(gtxreset_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gtxreset_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(gtxreset_reg1), + .Q(gtxreset_reg2), + .R(RST_DCLK_RESET)); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT4 #( + .INIT(16'h0100)) + \index[0]_i_1__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(fsm1), + .I2(index[0]), + .I3(\fsm_reg_n_0_[2] ), + .O(\index[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT5 #( + .INIT(32'h00140000)) + \index[1]_i_1__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[1]), + .I2(index[0]), + .I3(fsm1), + .I4(\fsm_reg_n_0_[2] ), + .O(\index[1]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'h0000144400000000)) + \index[2]_i_1__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(fsm1), + .I5(\fsm_reg_n_0_[2] ), + .O(\index[2]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'h0000144400000000)) + \index[3]_i_1__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[3]), + .I2(index[2]), + .I3(\index[3]_i_2__0_n_0 ), + .I4(fsm1), + .I5(\fsm_reg_n_0_[2] ), + .O(\index[3]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT2 #( + .INIT(4'h8)) + \index[3]_i_2__0 + (.I0(index[1]), + .I1(index[0]), + .O(\index[3]_i_2__0_n_0 )); + LUT3 #( + .INIT(8'hA1)) + \index[4]_i_1__0 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\index[4]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'h0000144400000000)) + \index[4]_i_2__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[4]), + .I2(index[3]), + .I3(\index[4]_i_3__0_n_0 ), + .I4(fsm1), + .I5(\fsm_reg_n_0_[2] ), + .O(\index[4]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT3 #( + .INIT(8'h80)) + \index[4]_i_3__0 + (.I0(index[2]), + .I1(index[0]), + .I2(index[1]), + .O(\index[4]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h1000000110000000)) + \index[4]_i_4__0 + (.I0(index[3]), + .I1(index[1]), + .I2(index[0]), + .I3(index[4]), + .I4(index[2]), + .I5(x16x20_mode_reg2), + .O(fsm1)); + FDRE #( + .INIT(1'b0)) + \index_reg[0] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__0_n_0 ), + .D(\index[0]_i_1__0_n_0 ), + .Q(index[0]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[1] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__0_n_0 ), + .D(\index[1]_i_1__0_n_0 ), + .Q(index[1]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[2] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__0_n_0 ), + .D(\index[2]_i_1__0_n_0 ), + .Q(index[2]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[3] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__0_n_0 ), + .D(\index[3]_i_1__0_n_0 ), + .Q(index[3]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[4] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__0_n_0 ), + .D(\index[4]_i_2__0_n_0 ), + .Q(index[4]), + .R(RST_DCLK_RESET)); + LUT3 #( + .INIT(8'h10)) + \load_cnt[0]_i_1__1 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .O(\load_cnt[0]_i_1__1_n_0 )); + FDRE #( + .INIT(1'b0)) + \load_cnt_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\load_cnt[0]_i_1__1_n_0 ), + .Q(load_cnt), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg1_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\rate_reg1_reg[0]_0 ), + .Q(rate_reg1[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg1_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rate_reg1[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg2_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(rate_reg1[0]), + .Q(rate_reg2[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg2_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(rate_reg1[1]), + .Q(rate_reg2[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rdy_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(DRP_RDY), + .Q(rdy_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rdy_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(rdy_reg1), + .Q(rdy_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE start_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(RATE_DRP_START), + .Q(start_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE start_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(start_reg1), + .Q(start_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(RATE_DRP_X16), + .Q(x16_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(x16_reg1), + .Q(x16_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16x20_mode_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(RATE_DRP_X16X20_MODE), + .Q(x16x20_mode_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16x20_mode_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(x16x20_mode_reg1), + .Q(x16x20_mode_reg2), + .R(RST_DCLK_RESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_drp" *) +module pcie_7x_0_pcie_7x_0_pipe_drp_44 + (\fsm_reg[1]_0 , + \fsm_reg[1]_1 , + DRPADDR, + DRPDI, + DRP_DONE, + RST_DCLK_RESET, + RATE_DRP_X16X20_MODE, + pipe_dclk_in, + RATE_DRP_START, + DRP_RDY, + \rate_reg1_reg[0]_0 , + RATE_DRP_X16, + D, + DRP_GTXRESET); + output \fsm_reg[1]_0 ; + output \fsm_reg[1]_1 ; + output [7:0]DRPADDR; + output [15:0]DRPDI; + output DRP_DONE; + input RST_DCLK_RESET; + input RATE_DRP_X16X20_MODE; + input pipe_dclk_in; + input RATE_DRP_START; + input DRP_RDY; + input [0:0]\rate_reg1_reg[0]_0 ; + input RATE_DRP_X16; + input [15:0]D; + input DRP_GTXRESET; + + wire [15:0]D; + wire [7:0]DRPADDR; + wire [15:0]DRPDI; + wire DRP_DONE; + wire DRP_GTXRESET; + wire DRP_RDY; + wire RATE_DRP_START; + wire RATE_DRP_X16; + wire RATE_DRP_X16X20_MODE; + wire RST_DCLK_RESET; + wire [7:0]addr_reg; + wire \addr_reg[4]_i_1__1_n_0 ; + wire \addr_reg[6]_i_1__1_n_0 ; + wire [15:15]data_pma_rsv_a; + wire [15:0]di_reg; + wire \di_reg[0]_i_2__1_n_0 ; + wire \di_reg[0]_i_3__1_n_0 ; + wire \di_reg[11]_i_2__1_n_0 ; + wire \di_reg[11]_i_3__1_n_0 ; + wire \di_reg[11]_i_4__1_n_0 ; + wire \di_reg[11]_i_5__1_n_0 ; + wire \di_reg[12]_i_2__1_n_0 ; + wire \di_reg[12]_i_3__1_n_0 ; + wire \di_reg[13]_i_2__1_n_0 ; + wire \di_reg[13]_i_3__1_n_0 ; + wire \di_reg[14]_i_2__1_n_0 ; + wire \di_reg[15]_i_2__1_n_0 ; + wire \di_reg[1]_i_2__1_n_0 ; + wire \di_reg[1]_i_3__1_n_0 ; + wire \di_reg[2]_i_2__1_n_0 ; + wire \di_reg[2]_i_3__1_n_0 ; + wire \di_reg[3]_i_2__1_n_0 ; + wire \di_reg[3]_i_3__1_n_0 ; + wire \di_reg[4]_i_2__1_n_0 ; + wire \di_reg[4]_i_3__1_n_0 ; + wire \di_reg[4]_i_4__1_n_0 ; + wire \di_reg[5]_i_2__1_n_0 ; + wire \di_reg[5]_i_3__1_n_0 ; + wire \di_reg[6]_i_2__1_n_0 ; + wire \di_reg[6]_i_3__1_n_0 ; + wire \di_reg[7]_i_2__1_n_0 ; + wire \di_reg[7]_i_3__1_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg2; + wire done_i_1__2_n_0; + wire [7:0]drp_addr_18; + wire [15:0]drp_di_32; + wire [2:0]fsm; + wire fsm1; + wire \fsm[0]_i_2__5_n_0 ; + wire \fsm_reg[1]_0 ; + wire \fsm_reg[1]_1 ; + wire \fsm_reg_n_0_[0] ; + wire \fsm_reg_n_0_[1] ; + wire \fsm_reg_n_0_[2] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gtxreset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gtxreset_reg2; + wire [4:0]index; + wire \index[0]_i_1__1_n_0 ; + wire \index[1]_i_1__1_n_0 ; + wire \index[2]_i_1__1_n_0 ; + wire \index[3]_i_1__1_n_0 ; + wire \index[3]_i_2__1_n_0 ; + wire \index[4]_i_1__1_n_0 ; + wire \index[4]_i_2__1_n_0 ; + wire \index[4]_i_3__1_n_0 ; + wire [0:0]load_cnt; + wire \load_cnt[0]_i_1__2_n_0 ; + wire pipe_dclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_reg1; + wire [0:0]\rate_reg1_reg[0]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16x20_mode_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16x20_mode_reg2; + + LUT6 #( + .INIT(64'h1736415517364154)) + \addr_reg[0]_i_1__1 + (.I0(index[4]), + .I1(index[3]), + .I2(index[2]), + .I3(index[1]), + .I4(index[0]), + .I5(x16x20_mode_reg2), + .O(addr_reg[0])); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT5 #( + .INIT(32'h40500F00)) + \addr_reg[1]_i_1__1 + (.I0(index[4]), + .I1(index[0]), + .I2(index[3]), + .I3(index[1]), + .I4(index[2]), + .O(addr_reg[1])); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT5 #( + .INIT(32'h05105A00)) + \addr_reg[2]_i_1__1 + (.I0(index[4]), + .I1(index[0]), + .I2(index[3]), + .I3(index[2]), + .I4(index[1]), + .O(addr_reg[2])); + LUT6 #( + .INIT(64'h5767576753265327)) + \addr_reg[3]_i_1__1 + (.I0(index[4]), + .I1(index[3]), + .I2(index[2]), + .I3(index[1]), + .I4(x16x20_mode_reg2), + .I5(index[0]), + .O(addr_reg[3])); + LUT6 #( + .INIT(64'h00000000FAAFFF04)) + \addr_reg[4]_i_1__1 + (.I0(index[0]), + .I1(x16x20_mode_reg2), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(index[4]), + .O(\addr_reg[4]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT5 #( + .INIT(32'h001A0F0A)) + \addr_reg[5]_i_1__1 + (.I0(index[4]), + .I1(index[0]), + .I2(index[3]), + .I3(index[1]), + .I4(index[2]), + .O(addr_reg[5])); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT5 #( + .INIT(32'h00001454)) + \addr_reg[6]_i_1__1 + (.I0(index[2]), + .I1(index[1]), + .I2(index[3]), + .I3(index[0]), + .I4(index[4]), + .O(\addr_reg[6]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'h5252424223236263)) + \addr_reg[7]_i_1__1 + (.I0(index[4]), + .I1(index[3]), + .I2(index[2]), + .I3(x16x20_mode_reg2), + .I4(index[0]), + .I5(index[1]), + .O(addr_reg[7])); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[0]), + .Q(drp_addr_18[0]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[1]), + .Q(drp_addr_18[1]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[2]), + .Q(drp_addr_18[2]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[3]), + .Q(drp_addr_18[3]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\addr_reg[4]_i_1__1_n_0 ), + .Q(drp_addr_18[4]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[5]), + .Q(drp_addr_18[5]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\addr_reg[6]_i_1__1_n_0 ), + .Q(drp_addr_18[6]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[7]), + .Q(drp_addr_18[7]), + .R(RST_DCLK_RESET)); + LUT6 #( + .INIT(64'hFF5E7F6FA1001000)) + \di_reg[0]_i_2__1 + (.I0(index[3]), + .I1(index[2]), + .I2(index[1]), + .I3(data_pma_rsv_a), + .I4(index[0]), + .I5(do_reg2[0]), + .O(\di_reg[0]_i_2__1_n_0 )); + LUT5 #( + .INIT(32'h000005D0)) + \di_reg[0]_i_3__1 + (.I0(index[0]), + .I1(do_reg2[0]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[0]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h45555F5540000000)) + \di_reg[10]_i_1__1 + (.I0(index[4]), + .I1(\di_reg[15]_i_2__1_n_0 ), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[10]), + .O(di_reg[10])); + LUT6 #( + .INIT(64'h4F40DDDD4F408888)) + \di_reg[11]_i_2__1 + (.I0(index[3]), + .I1(do_reg2[11]), + .I2(index[1]), + .I3(\di_reg[11]_i_4__1_n_0 ), + .I4(index[2]), + .I5(\di_reg[11]_i_5__1_n_0 ), + .O(\di_reg[11]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h0000000008080838)) + \di_reg[11]_i_3__1 + (.I0(do_reg2[11]), + .I1(index[2]), + .I2(index[1]), + .I3(data_pma_rsv_a), + .I4(index[0]), + .I5(index[3]), + .O(\di_reg[11]_i_3__1_n_0 )); + LUT4 #( + .INIT(16'hB8BB)) + \di_reg[11]_i_4__1 + (.I0(do_reg2[11]), + .I1(index[0]), + .I2(rate_reg2[0]), + .I3(rate_reg2[1]), + .O(\di_reg[11]_i_4__1_n_0 )); + LUT5 #( + .INIT(32'hEFFF0100)) + \di_reg[11]_i_5__1 + (.I0(index[1]), + .I1(index[0]), + .I2(x16_reg2), + .I3(x16x20_mode_reg2), + .I4(do_reg2[11]), + .O(\di_reg[11]_i_5__1_n_0 )); + LUT6 #( + .INIT(64'h777EFFFF01080000)) + \di_reg[12]_i_2__1 + (.I0(index[3]), + .I1(index[1]), + .I2(index[0]), + .I3(data_pma_rsv_a), + .I4(index[2]), + .I5(do_reg2[12]), + .O(\di_reg[12]_i_2__1_n_0 )); + LUT5 #( + .INIT(32'h00000B08)) + \di_reg[12]_i_3__1 + (.I0(do_reg2[12]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(index[3]), + .O(\di_reg[12]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h767FFFFF00090000)) + \di_reg[13]_i_2__1 + (.I0(index[3]), + .I1(index[1]), + .I2(index[0]), + .I3(data_pma_rsv_a), + .I4(index[2]), + .I5(do_reg2[13]), + .O(\di_reg[13]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h0000000008380808)) + \di_reg[13]_i_3__1 + (.I0(do_reg2[13]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(data_pma_rsv_a), + .I5(index[3]), + .O(\di_reg[13]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h0040FFFF00400000)) + \di_reg[14]_i_1__1 + (.I0(index[1]), + .I1(index[2]), + .I2(do_reg2[14]), + .I3(index[3]), + .I4(index[4]), + .I5(\di_reg[14]_i_2__1_n_0 ), + .O(di_reg[14])); + LUT6 #( + .INIT(64'h653BFFF721080080)) + \di_reg[14]_i_2__1 + (.I0(index[3]), + .I1(index[1]), + .I2(data_pma_rsv_a), + .I3(index[0]), + .I4(index[2]), + .I5(do_reg2[14]), + .O(\di_reg[14]_i_2__1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \di_reg[14]_i_3__0 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .O(data_pma_rsv_a)); + LUT6 #( + .INIT(64'h45555F5540000000)) + \di_reg[15]_i_1__1 + (.I0(index[4]), + .I1(\di_reg[15]_i_2__1_n_0 ), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[15]), + .O(di_reg[15])); + LUT3 #( + .INIT(8'h0D)) + \di_reg[15]_i_2__1 + (.I0(rate_reg2[1]), + .I1(rate_reg2[0]), + .I2(index[0]), + .O(\di_reg[15]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h5FEE4E0076FF1000)) + \di_reg[1]_i_2__1 + (.I0(index[3]), + .I1(index[2]), + .I2(data_pma_rsv_a), + .I3(index[1]), + .I4(do_reg2[1]), + .I5(index[0]), + .O(\di_reg[1]_i_2__1_n_0 )); + LUT5 #( + .INIT(32'h000005D0)) + \di_reg[1]_i_3__1 + (.I0(index[0]), + .I1(do_reg2[1]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[1]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h5DEE080067FF0100)) + \di_reg[2]_i_2__1 + (.I0(index[3]), + .I1(index[2]), + .I2(data_pma_rsv_a), + .I3(index[1]), + .I4(do_reg2[2]), + .I5(index[0]), + .O(\di_reg[2]_i_2__1_n_0 )); + LUT5 #( + .INIT(32'h00000380)) + \di_reg[2]_i_3__1 + (.I0(do_reg2[2]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[2]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h43FFFFFF40000000)) + \di_reg[3]_i_2__1 + (.I0(data_pma_rsv_a), + .I1(index[2]), + .I2(index[0]), + .I3(index[1]), + .I4(index[3]), + .I5(do_reg2[3]), + .O(\di_reg[3]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h000000000033D100)) + \di_reg[3]_i_3__1 + (.I0(data_pma_rsv_a), + .I1(index[0]), + .I2(do_reg2[3]), + .I3(index[2]), + .I4(index[1]), + .I5(index[3]), + .O(\di_reg[3]_i_3__1_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \di_reg[4]_i_1__1 + (.I0(\di_reg[4]_i_2__1_n_0 ), + .I1(index[4]), + .I2(\di_reg[4]_i_3__1_n_0 ), + .I3(index[3]), + .I4(\di_reg[4]_i_4__1_n_0 ), + .O(di_reg[4])); + LUT6 #( + .INIT(64'h0F0400F0000400F0)) + \di_reg[4]_i_2__1 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .I2(index[1]), + .I3(index[2]), + .I4(index[0]), + .I5(do_reg2[4]), + .O(\di_reg[4]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h400FFFFF40000000)) + \di_reg[4]_i_3__1 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .I2(index[2]), + .I3(index[0]), + .I4(index[1]), + .I5(do_reg2[4]), + .O(\di_reg[4]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'hBF00BF01FF40FE40)) + \di_reg[4]_i_4__1 + (.I0(index[2]), + .I1(index[1]), + .I2(index[0]), + .I3(do_reg2[4]), + .I4(x16x20_mode_reg2), + .I5(data_pma_rsv_a), + .O(\di_reg[4]_i_4__1_n_0 )); + LUT6 #( + .INIT(64'h7F7F7F7E00000000)) + \di_reg[5]_i_2__1 + (.I0(index[3]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(x16x20_mode_reg2), + .I5(do_reg2[5]), + .O(\di_reg[5]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h00000000038F0380)) + \di_reg[5]_i_3__1 + (.I0(do_reg2[5]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(data_pma_rsv_a), + .I5(index[3]), + .O(\di_reg[5]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h7D7F7D7E00000000)) + \di_reg[6]_i_2__1 + (.I0(index[3]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(x16x20_mode_reg2), + .I5(do_reg2[6]), + .O(\di_reg[6]_i_2__1_n_0 )); + LUT5 #( + .INIT(32'h00000380)) + \di_reg[6]_i_3__1 + (.I0(do_reg2[6]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[6]_i_3__1_n_0 )); + LUT5 #( + .INIT(32'h7FFF0900)) + \di_reg[7]_i_2__1 + (.I0(index[2]), + .I1(index[1]), + .I2(index[0]), + .I3(index[3]), + .I4(do_reg2[7]), + .O(\di_reg[7]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h0000000003800383)) + \di_reg[7]_i_3__1 + (.I0(do_reg2[7]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(data_pma_rsv_a), + .I5(index[3]), + .O(\di_reg[7]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h03333F7300000040)) + \di_reg[8]_i_1__1 + (.I0(index[0]), + .I1(index[4]), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[8]), + .O(di_reg[8])); + LUT6 #( + .INIT(64'h03333F7300000040)) + \di_reg[9]_i_1__1 + (.I0(index[0]), + .I1(index[4]), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[9]), + .O(di_reg[9])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[0]), + .Q(drp_di_32[0]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[0]_i_1__1 + (.I0(\di_reg[0]_i_2__1_n_0 ), + .I1(\di_reg[0]_i_3__1_n_0 ), + .O(di_reg[0]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[10]), + .Q(drp_di_32[10]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[11]), + .Q(drp_di_32[11]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[11]_i_1__1 + (.I0(\di_reg[11]_i_2__1_n_0 ), + .I1(\di_reg[11]_i_3__1_n_0 ), + .O(di_reg[11]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[12]), + .Q(drp_di_32[12]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[12]_i_1__1 + (.I0(\di_reg[12]_i_2__1_n_0 ), + .I1(\di_reg[12]_i_3__1_n_0 ), + .O(di_reg[12]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[13]), + .Q(drp_di_32[13]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[13]_i_1__1 + (.I0(\di_reg[13]_i_2__1_n_0 ), + .I1(\di_reg[13]_i_3__1_n_0 ), + .O(di_reg[13]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[14]), + .Q(drp_di_32[14]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[15]), + .Q(drp_di_32[15]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[1]), + .Q(drp_di_32[1]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[1]_i_1__1 + (.I0(\di_reg[1]_i_2__1_n_0 ), + .I1(\di_reg[1]_i_3__1_n_0 ), + .O(di_reg[1]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[2]), + .Q(drp_di_32[2]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[2]_i_1__1 + (.I0(\di_reg[2]_i_2__1_n_0 ), + .I1(\di_reg[2]_i_3__1_n_0 ), + .O(di_reg[2]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[3]), + .Q(drp_di_32[3]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[3]_i_1__1 + (.I0(\di_reg[3]_i_2__1_n_0 ), + .I1(\di_reg[3]_i_3__1_n_0 ), + .O(di_reg[3]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[4]), + .Q(drp_di_32[4]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[5]), + .Q(drp_di_32[5]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[5]_i_1__1 + (.I0(\di_reg[5]_i_2__1_n_0 ), + .I1(\di_reg[5]_i_3__1_n_0 ), + .O(di_reg[5]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[6]), + .Q(drp_di_32[6]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[6]_i_1__1 + (.I0(\di_reg[6]_i_2__1_n_0 ), + .I1(\di_reg[6]_i_3__1_n_0 ), + .O(di_reg[6]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[7]), + .Q(drp_di_32[7]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[7]_i_1__1 + (.I0(\di_reg[7]_i_2__1_n_0 ), + .I1(\di_reg[7]_i_3__1_n_0 ), + .O(di_reg[7]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[8]), + .Q(drp_di_32[8]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[9]), + .Q(drp_di_32[9]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[0]), + .Q(do_reg1[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[10]), + .Q(do_reg1[10]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[11]), + .Q(do_reg1[11]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[12]), + .Q(do_reg1[12]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[13]), + .Q(do_reg1[13]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[14]), + .Q(do_reg1[14]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[15]), + .Q(do_reg1[15]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[1]), + .Q(do_reg1[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[2]), + .Q(do_reg1[2]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[3]), + .Q(do_reg1[3]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[4]), + .Q(do_reg1[4]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[5]), + .Q(do_reg1[5]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[6]), + .Q(do_reg1[6]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[7]), + .Q(do_reg1[7]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[8]), + .Q(do_reg1[8]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[9]), + .Q(do_reg1[9]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[0]), + .Q(do_reg2[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[10]), + .Q(do_reg2[10]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[11]), + .Q(do_reg2[11]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[12]), + .Q(do_reg2[12]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[13]), + .Q(do_reg2[13]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[14]), + .Q(do_reg2[14]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[15]), + .Q(do_reg2[15]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[1]), + .Q(do_reg2[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[2]), + .Q(do_reg2[2]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[3]), + .Q(do_reg2[3]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[4]), + .Q(do_reg2[4]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[5]), + .Q(do_reg2[5]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[6]), + .Q(do_reg2[6]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[7]), + .Q(do_reg2[7]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[8]), + .Q(do_reg2[8]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[9]), + .Q(do_reg2[9]), + .R(RST_DCLK_RESET)); + LUT4 #( + .INIT(16'h0001)) + done_i_1__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(start_reg2), + .I3(\fsm_reg_n_0_[1] ), + .O(done_i_1__2_n_0)); + FDRE #( + .INIT(1'b0)) + done_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(done_i_1__2_n_0), + .Q(DRP_DONE), + .R(RST_DCLK_RESET)); + LUT6 #( + .INIT(64'h0737FFFF07370000)) + \fsm[0]_i_1__5 + (.I0(fsm1), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(rdy_reg2), + .I4(\fsm_reg_n_0_[2] ), + .I5(\fsm[0]_i_2__5_n_0 ), + .O(fsm[0])); + LUT5 #( + .INIT(32'h47FF47CC)) + \fsm[0]_i_2__5 + (.I0(rdy_reg2), + .I1(\fsm_reg_n_0_[1] ), + .I2(load_cnt), + .I3(\fsm_reg_n_0_[0] ), + .I4(start_reg2), + .O(\fsm[0]_i_2__5_n_0 )); + LUT5 #( + .INIT(32'h1D501850)) + \fsm[1]_i_1__5 + (.I0(\fsm_reg_n_0_[2] ), + .I1(rdy_reg2), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(load_cnt), + .O(fsm[1])); + LUT4 #( + .INIT(16'h6222)) + \fsm[2]_i_1__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(rdy_reg2), + .O(fsm[2])); + FDRE #( + .INIT(1'b0)) + \fsm_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(fsm[0]), + .Q(\fsm_reg_n_0_[0] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \fsm_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(fsm[1]), + .Q(\fsm_reg_n_0_[1] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \fsm_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(fsm[2]), + .Q(\fsm_reg_n_0_[2] ), + .R(RST_DCLK_RESET)); + (* SOFT_HLUTNM = "soft_lutpair135" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_10__1 + (.I0(drp_di_32[11]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[11])); + (* SOFT_HLUTNM = "soft_lutpair135" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_11__1 + (.I0(drp_di_32[10]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[10])); + (* SOFT_HLUTNM = "soft_lutpair134" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_12__1 + (.I0(drp_di_32[9]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[9])); + (* SOFT_HLUTNM = "soft_lutpair134" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_13__1 + (.I0(drp_di_32[8]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[8])); + (* SOFT_HLUTNM = "soft_lutpair133" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_14__1 + (.I0(drp_di_32[7]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[7])); + (* SOFT_HLUTNM = "soft_lutpair133" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_15__1 + (.I0(drp_di_32[6]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[6])); + (* SOFT_HLUTNM = "soft_lutpair132" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_16__1 + (.I0(drp_di_32[5]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[5])); + (* SOFT_HLUTNM = "soft_lutpair132" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_17__1 + (.I0(drp_di_32[4]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[4])); + (* SOFT_HLUTNM = "soft_lutpair131" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_18__1 + (.I0(drp_di_32[3]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[3])); + (* SOFT_HLUTNM = "soft_lutpair131" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_19__1 + (.I0(drp_di_32[2]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[2])); + (* SOFT_HLUTNM = "soft_lutpair130" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_20__1 + (.I0(drp_di_32[1]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[1])); + (* SOFT_HLUTNM = "soft_lutpair130" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_21__1 + (.I0(drp_di_32[0]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[0])); + (* SOFT_HLUTNM = "soft_lutpair129" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_39__2 + (.I0(drp_addr_18[7]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[7])); + (* SOFT_HLUTNM = "soft_lutpair125" *) + LUT3 #( + .INIT(8'h12)) + \gtx_channel.gtxe2_channel_i_i_3__1 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\fsm_reg[1]_0 )); + (* SOFT_HLUTNM = "soft_lutpair129" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_40__1 + (.I0(drp_addr_18[6]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[6])); + (* SOFT_HLUTNM = "soft_lutpair128" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_41__1 + (.I0(drp_addr_18[5]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[5])); + (* SOFT_HLUTNM = "soft_lutpair128" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_42__1 + (.I0(drp_addr_18[4]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[4])); + (* SOFT_HLUTNM = "soft_lutpair127" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_43__1 + (.I0(drp_addr_18[3]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[3])); + (* SOFT_HLUTNM = "soft_lutpair127" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_44__1 + (.I0(drp_addr_18[2]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[2])); + (* SOFT_HLUTNM = "soft_lutpair126" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_45__1 + (.I0(drp_addr_18[1]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[1])); + (* SOFT_HLUTNM = "soft_lutpair125" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_46__1 + (.I0(drp_addr_18[0]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[0])); + (* SOFT_HLUTNM = "soft_lutpair126" *) + LUT3 #( + .INIT(8'h10)) + \gtx_channel.gtxe2_channel_i_i_4__1 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\fsm_reg[1]_1 )); + (* SOFT_HLUTNM = "soft_lutpair137" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_6__1 + (.I0(drp_di_32[15]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[15])); + (* SOFT_HLUTNM = "soft_lutpair137" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_7__1 + (.I0(drp_di_32[14]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[14])); + (* SOFT_HLUTNM = "soft_lutpair136" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_8__1 + (.I0(drp_di_32[13]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[13])); + (* SOFT_HLUTNM = "soft_lutpair136" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_9__1 + (.I0(drp_di_32[12]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[12])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gtxreset_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(DRP_GTXRESET), + .Q(gtxreset_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gtxreset_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(gtxreset_reg1), + .Q(gtxreset_reg2), + .R(RST_DCLK_RESET)); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT4 #( + .INIT(16'h0100)) + \index[0]_i_1__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(fsm1), + .I2(index[0]), + .I3(\fsm_reg_n_0_[2] ), + .O(\index[0]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT5 #( + .INIT(32'h00140000)) + \index[1]_i_1__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[1]), + .I2(index[0]), + .I3(fsm1), + .I4(\fsm_reg_n_0_[2] ), + .O(\index[1]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'h0000144400000000)) + \index[2]_i_1__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(fsm1), + .I5(\fsm_reg_n_0_[2] ), + .O(\index[2]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'h0000144400000000)) + \index[3]_i_1__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[3]), + .I2(index[2]), + .I3(\index[3]_i_2__1_n_0 ), + .I4(fsm1), + .I5(\fsm_reg_n_0_[2] ), + .O(\index[3]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair138" *) + LUT2 #( + .INIT(4'h8)) + \index[3]_i_2__1 + (.I0(index[1]), + .I1(index[0]), + .O(\index[3]_i_2__1_n_0 )); + LUT3 #( + .INIT(8'hA1)) + \index[4]_i_1__1 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\index[4]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'h0000144400000000)) + \index[4]_i_2__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[4]), + .I2(index[3]), + .I3(\index[4]_i_3__1_n_0 ), + .I4(fsm1), + .I5(\fsm_reg_n_0_[2] ), + .O(\index[4]_i_2__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair138" *) + LUT3 #( + .INIT(8'h80)) + \index[4]_i_3__1 + (.I0(index[2]), + .I1(index[0]), + .I2(index[1]), + .O(\index[4]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h1000000110000000)) + \index[4]_i_4__1 + (.I0(index[3]), + .I1(index[1]), + .I2(index[0]), + .I3(index[4]), + .I4(index[2]), + .I5(x16x20_mode_reg2), + .O(fsm1)); + FDRE #( + .INIT(1'b0)) + \index_reg[0] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__1_n_0 ), + .D(\index[0]_i_1__1_n_0 ), + .Q(index[0]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[1] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__1_n_0 ), + .D(\index[1]_i_1__1_n_0 ), + .Q(index[1]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[2] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__1_n_0 ), + .D(\index[2]_i_1__1_n_0 ), + .Q(index[2]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[3] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__1_n_0 ), + .D(\index[3]_i_1__1_n_0 ), + .Q(index[3]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[4] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__1_n_0 ), + .D(\index[4]_i_2__1_n_0 ), + .Q(index[4]), + .R(RST_DCLK_RESET)); + LUT3 #( + .INIT(8'h10)) + \load_cnt[0]_i_1__2 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .O(\load_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \load_cnt_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\load_cnt[0]_i_1__2_n_0 ), + .Q(load_cnt), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg1_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\rate_reg1_reg[0]_0 ), + .Q(rate_reg1[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg1_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rate_reg1[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg2_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(rate_reg1[0]), + .Q(rate_reg2[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg2_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(rate_reg1[1]), + .Q(rate_reg2[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rdy_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(DRP_RDY), + .Q(rdy_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rdy_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(rdy_reg1), + .Q(rdy_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE start_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(RATE_DRP_START), + .Q(start_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE start_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(start_reg1), + .Q(start_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(RATE_DRP_X16), + .Q(x16_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(x16_reg1), + .Q(x16_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16x20_mode_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(RATE_DRP_X16X20_MODE), + .Q(x16x20_mode_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16x20_mode_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(x16x20_mode_reg1), + .Q(x16x20_mode_reg2), + .R(RST_DCLK_RESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_drp" *) +module pcie_7x_0_pcie_7x_0_pipe_drp_50 + (\fsm_reg[1]_0 , + \fsm_reg[1]_1 , + DRPADDR, + DRPDI, + DRP_DONE, + RST_DCLK_RESET, + RATE_DRP_X16X20_MODE, + pipe_dclk_in, + RATE_DRP_START, + DRP_RDY, + \rate_reg1_reg[0]_0 , + RATE_DRP_X16, + D, + DRP_GTXRESET); + output \fsm_reg[1]_0 ; + output \fsm_reg[1]_1 ; + output [7:0]DRPADDR; + output [15:0]DRPDI; + output DRP_DONE; + input RST_DCLK_RESET; + input RATE_DRP_X16X20_MODE; + input pipe_dclk_in; + input RATE_DRP_START; + input DRP_RDY; + input [0:0]\rate_reg1_reg[0]_0 ; + input RATE_DRP_X16; + input [15:0]D; + input DRP_GTXRESET; + + wire [15:0]D; + wire [7:0]DRPADDR; + wire [15:0]DRPDI; + wire DRP_DONE; + wire DRP_GTXRESET; + wire DRP_RDY; + wire RATE_DRP_START; + wire RATE_DRP_X16; + wire RATE_DRP_X16X20_MODE; + wire RST_DCLK_RESET; + wire [7:0]addr_reg; + wire \addr_reg[4]_i_1__2_n_0 ; + wire \addr_reg[6]_i_1__2_n_0 ; + wire [15:15]data_pma_rsv_a; + wire [15:0]di_reg; + wire \di_reg[0]_i_2__2_n_0 ; + wire \di_reg[0]_i_3__2_n_0 ; + wire \di_reg[11]_i_2__2_n_0 ; + wire \di_reg[11]_i_3__2_n_0 ; + wire \di_reg[11]_i_4__2_n_0 ; + wire \di_reg[11]_i_5__2_n_0 ; + wire \di_reg[12]_i_2__2_n_0 ; + wire \di_reg[12]_i_3__2_n_0 ; + wire \di_reg[13]_i_2__2_n_0 ; + wire \di_reg[13]_i_3__2_n_0 ; + wire \di_reg[14]_i_2__2_n_0 ; + wire \di_reg[15]_i_2__2_n_0 ; + wire \di_reg[1]_i_2__2_n_0 ; + wire \di_reg[1]_i_3__2_n_0 ; + wire \di_reg[2]_i_2__2_n_0 ; + wire \di_reg[2]_i_3__2_n_0 ; + wire \di_reg[3]_i_2__2_n_0 ; + wire \di_reg[3]_i_3__2_n_0 ; + wire \di_reg[4]_i_2__2_n_0 ; + wire \di_reg[4]_i_3__2_n_0 ; + wire \di_reg[4]_i_4__2_n_0 ; + wire \di_reg[5]_i_2__2_n_0 ; + wire \di_reg[5]_i_3__2_n_0 ; + wire \di_reg[6]_i_2__2_n_0 ; + wire \di_reg[6]_i_3__2_n_0 ; + wire \di_reg[7]_i_2__2_n_0 ; + wire \di_reg[7]_i_3__2_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg2; + wire done_i_1__3_n_0; + wire [7:0]drp_addr_27; + wire [15:0]drp_di_48; + wire [2:0]fsm; + wire fsm1; + wire \fsm[0]_i_2__7_n_0 ; + wire \fsm_reg[1]_0 ; + wire \fsm_reg[1]_1 ; + wire \fsm_reg_n_0_[0] ; + wire \fsm_reg_n_0_[1] ; + wire \fsm_reg_n_0_[2] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gtxreset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gtxreset_reg2; + wire [4:0]index; + wire \index[0]_i_1__2_n_0 ; + wire \index[1]_i_1__2_n_0 ; + wire \index[2]_i_1__2_n_0 ; + wire \index[3]_i_1__2_n_0 ; + wire \index[3]_i_2__2_n_0 ; + wire \index[4]_i_1__2_n_0 ; + wire \index[4]_i_2__2_n_0 ; + wire \index[4]_i_3__2_n_0 ; + wire [0:0]load_cnt; + wire \load_cnt[0]_i_1__3_n_0 ; + wire pipe_dclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_reg1; + wire [0:0]\rate_reg1_reg[0]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16x20_mode_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16x20_mode_reg2; + + LUT6 #( + .INIT(64'h1736415517364154)) + \addr_reg[0]_i_1__2 + (.I0(index[4]), + .I1(index[3]), + .I2(index[2]), + .I3(index[1]), + .I4(index[0]), + .I5(x16x20_mode_reg2), + .O(addr_reg[0])); + (* SOFT_HLUTNM = "soft_lutpair165" *) + LUT5 #( + .INIT(32'h40500F00)) + \addr_reg[1]_i_1__2 + (.I0(index[4]), + .I1(index[0]), + .I2(index[3]), + .I3(index[1]), + .I4(index[2]), + .O(addr_reg[1])); + (* SOFT_HLUTNM = "soft_lutpair165" *) + LUT5 #( + .INIT(32'h05105A00)) + \addr_reg[2]_i_1__2 + (.I0(index[4]), + .I1(index[0]), + .I2(index[3]), + .I3(index[2]), + .I4(index[1]), + .O(addr_reg[2])); + LUT6 #( + .INIT(64'h5767576753265327)) + \addr_reg[3]_i_1__2 + (.I0(index[4]), + .I1(index[3]), + .I2(index[2]), + .I3(index[1]), + .I4(x16x20_mode_reg2), + .I5(index[0]), + .O(addr_reg[3])); + LUT6 #( + .INIT(64'h00000000FAAFFF04)) + \addr_reg[4]_i_1__2 + (.I0(index[0]), + .I1(x16x20_mode_reg2), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(index[4]), + .O(\addr_reg[4]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair164" *) + LUT5 #( + .INIT(32'h001A0F0A)) + \addr_reg[5]_i_1__2 + (.I0(index[4]), + .I1(index[0]), + .I2(index[3]), + .I3(index[1]), + .I4(index[2]), + .O(addr_reg[5])); + (* SOFT_HLUTNM = "soft_lutpair164" *) + LUT5 #( + .INIT(32'h00001454)) + \addr_reg[6]_i_1__2 + (.I0(index[2]), + .I1(index[1]), + .I2(index[3]), + .I3(index[0]), + .I4(index[4]), + .O(\addr_reg[6]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'h5252424223236263)) + \addr_reg[7]_i_1__2 + (.I0(index[4]), + .I1(index[3]), + .I2(index[2]), + .I3(x16x20_mode_reg2), + .I4(index[0]), + .I5(index[1]), + .O(addr_reg[7])); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[0]), + .Q(drp_addr_27[0]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[1]), + .Q(drp_addr_27[1]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[2]), + .Q(drp_addr_27[2]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[3]), + .Q(drp_addr_27[3]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\addr_reg[4]_i_1__2_n_0 ), + .Q(drp_addr_27[4]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[5]), + .Q(drp_addr_27[5]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\addr_reg[6]_i_1__2_n_0 ), + .Q(drp_addr_27[6]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(addr_reg[7]), + .Q(drp_addr_27[7]), + .R(RST_DCLK_RESET)); + LUT6 #( + .INIT(64'hFF5E7F6FA1001000)) + \di_reg[0]_i_2__2 + (.I0(index[3]), + .I1(index[2]), + .I2(index[1]), + .I3(data_pma_rsv_a), + .I4(index[0]), + .I5(do_reg2[0]), + .O(\di_reg[0]_i_2__2_n_0 )); + LUT5 #( + .INIT(32'h000005D0)) + \di_reg[0]_i_3__2 + (.I0(index[0]), + .I1(do_reg2[0]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[0]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'h45555F5540000000)) + \di_reg[10]_i_1__2 + (.I0(index[4]), + .I1(\di_reg[15]_i_2__2_n_0 ), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[10]), + .O(di_reg[10])); + LUT6 #( + .INIT(64'h4F40DDDD4F408888)) + \di_reg[11]_i_2__2 + (.I0(index[3]), + .I1(do_reg2[11]), + .I2(index[1]), + .I3(\di_reg[11]_i_4__2_n_0 ), + .I4(index[2]), + .I5(\di_reg[11]_i_5__2_n_0 ), + .O(\di_reg[11]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h0000000008080838)) + \di_reg[11]_i_3__2 + (.I0(do_reg2[11]), + .I1(index[2]), + .I2(index[1]), + .I3(data_pma_rsv_a), + .I4(index[0]), + .I5(index[3]), + .O(\di_reg[11]_i_3__2_n_0 )); + LUT4 #( + .INIT(16'hB8BB)) + \di_reg[11]_i_4__2 + (.I0(do_reg2[11]), + .I1(index[0]), + .I2(rate_reg2[0]), + .I3(rate_reg2[1]), + .O(\di_reg[11]_i_4__2_n_0 )); + LUT5 #( + .INIT(32'hEFFF0100)) + \di_reg[11]_i_5__2 + (.I0(index[1]), + .I1(index[0]), + .I2(x16_reg2), + .I3(x16x20_mode_reg2), + .I4(do_reg2[11]), + .O(\di_reg[11]_i_5__2_n_0 )); + LUT6 #( + .INIT(64'h777EFFFF01080000)) + \di_reg[12]_i_2__2 + (.I0(index[3]), + .I1(index[1]), + .I2(index[0]), + .I3(data_pma_rsv_a), + .I4(index[2]), + .I5(do_reg2[12]), + .O(\di_reg[12]_i_2__2_n_0 )); + LUT5 #( + .INIT(32'h00000B08)) + \di_reg[12]_i_3__2 + (.I0(do_reg2[12]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(index[3]), + .O(\di_reg[12]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'h767FFFFF00090000)) + \di_reg[13]_i_2__2 + (.I0(index[3]), + .I1(index[1]), + .I2(index[0]), + .I3(data_pma_rsv_a), + .I4(index[2]), + .I5(do_reg2[13]), + .O(\di_reg[13]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h0000000008380808)) + \di_reg[13]_i_3__2 + (.I0(do_reg2[13]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(data_pma_rsv_a), + .I5(index[3]), + .O(\di_reg[13]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'h0040FFFF00400000)) + \di_reg[14]_i_1__2 + (.I0(index[1]), + .I1(index[2]), + .I2(do_reg2[14]), + .I3(index[3]), + .I4(index[4]), + .I5(\di_reg[14]_i_2__2_n_0 ), + .O(di_reg[14])); + LUT6 #( + .INIT(64'h653BFFF721080080)) + \di_reg[14]_i_2__2 + (.I0(index[3]), + .I1(index[1]), + .I2(data_pma_rsv_a), + .I3(index[0]), + .I4(index[2]), + .I5(do_reg2[14]), + .O(\di_reg[14]_i_2__2_n_0 )); + LUT2 #( + .INIT(4'hB)) + \di_reg[14]_i_3 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .O(data_pma_rsv_a)); + LUT6 #( + .INIT(64'h45555F5540000000)) + \di_reg[15]_i_1__2 + (.I0(index[4]), + .I1(\di_reg[15]_i_2__2_n_0 ), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[15]), + .O(di_reg[15])); + LUT3 #( + .INIT(8'h0D)) + \di_reg[15]_i_2__2 + (.I0(rate_reg2[1]), + .I1(rate_reg2[0]), + .I2(index[0]), + .O(\di_reg[15]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h5FEE4E0076FF1000)) + \di_reg[1]_i_2__2 + (.I0(index[3]), + .I1(index[2]), + .I2(data_pma_rsv_a), + .I3(index[1]), + .I4(do_reg2[1]), + .I5(index[0]), + .O(\di_reg[1]_i_2__2_n_0 )); + LUT5 #( + .INIT(32'h000005D0)) + \di_reg[1]_i_3__2 + (.I0(index[0]), + .I1(do_reg2[1]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[1]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'h5DEE080067FF0100)) + \di_reg[2]_i_2__2 + (.I0(index[3]), + .I1(index[2]), + .I2(data_pma_rsv_a), + .I3(index[1]), + .I4(do_reg2[2]), + .I5(index[0]), + .O(\di_reg[2]_i_2__2_n_0 )); + LUT5 #( + .INIT(32'h00000380)) + \di_reg[2]_i_3__2 + (.I0(do_reg2[2]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[2]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'h43FFFFFF40000000)) + \di_reg[3]_i_2__2 + (.I0(data_pma_rsv_a), + .I1(index[2]), + .I2(index[0]), + .I3(index[1]), + .I4(index[3]), + .I5(do_reg2[3]), + .O(\di_reg[3]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h000000000033D100)) + \di_reg[3]_i_3__2 + (.I0(data_pma_rsv_a), + .I1(index[0]), + .I2(do_reg2[3]), + .I3(index[2]), + .I4(index[1]), + .I5(index[3]), + .O(\di_reg[3]_i_3__2_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \di_reg[4]_i_1__2 + (.I0(\di_reg[4]_i_2__2_n_0 ), + .I1(index[4]), + .I2(\di_reg[4]_i_3__2_n_0 ), + .I3(index[3]), + .I4(\di_reg[4]_i_4__2_n_0 ), + .O(di_reg[4])); + LUT6 #( + .INIT(64'h0F0400F0000400F0)) + \di_reg[4]_i_2__2 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .I2(index[1]), + .I3(index[2]), + .I4(index[0]), + .I5(do_reg2[4]), + .O(\di_reg[4]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h400FFFFF40000000)) + \di_reg[4]_i_3__2 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .I2(index[2]), + .I3(index[0]), + .I4(index[1]), + .I5(do_reg2[4]), + .O(\di_reg[4]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'hBF00BF01FF40FE40)) + \di_reg[4]_i_4__2 + (.I0(index[2]), + .I1(index[1]), + .I2(index[0]), + .I3(do_reg2[4]), + .I4(x16x20_mode_reg2), + .I5(data_pma_rsv_a), + .O(\di_reg[4]_i_4__2_n_0 )); + LUT6 #( + .INIT(64'h7F7F7F7E00000000)) + \di_reg[5]_i_2__2 + (.I0(index[3]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(x16x20_mode_reg2), + .I5(do_reg2[5]), + .O(\di_reg[5]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h00000000038F0380)) + \di_reg[5]_i_3__2 + (.I0(do_reg2[5]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(data_pma_rsv_a), + .I5(index[3]), + .O(\di_reg[5]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'h7D7F7D7E00000000)) + \di_reg[6]_i_2__2 + (.I0(index[3]), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(x16x20_mode_reg2), + .I5(do_reg2[6]), + .O(\di_reg[6]_i_2__2_n_0 )); + LUT5 #( + .INIT(32'h00000380)) + \di_reg[6]_i_3__2 + (.I0(do_reg2[6]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(index[3]), + .O(\di_reg[6]_i_3__2_n_0 )); + LUT5 #( + .INIT(32'h7FFF0900)) + \di_reg[7]_i_2__2 + (.I0(index[2]), + .I1(index[1]), + .I2(index[0]), + .I3(index[3]), + .I4(do_reg2[7]), + .O(\di_reg[7]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h0000000003800383)) + \di_reg[7]_i_3__2 + (.I0(do_reg2[7]), + .I1(index[0]), + .I2(index[2]), + .I3(index[1]), + .I4(data_pma_rsv_a), + .I5(index[3]), + .O(\di_reg[7]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'h03333F7300000040)) + \di_reg[8]_i_1__2 + (.I0(index[0]), + .I1(index[4]), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[8]), + .O(di_reg[8])); + LUT6 #( + .INIT(64'h03333F7300000040)) + \di_reg[9]_i_1__2 + (.I0(index[0]), + .I1(index[4]), + .I2(index[1]), + .I3(index[2]), + .I4(index[3]), + .I5(do_reg2[9]), + .O(di_reg[9])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[0]), + .Q(drp_di_48[0]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[0]_i_1__2 + (.I0(\di_reg[0]_i_2__2_n_0 ), + .I1(\di_reg[0]_i_3__2_n_0 ), + .O(di_reg[0]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[10]), + .Q(drp_di_48[10]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[11]), + .Q(drp_di_48[11]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[11]_i_1__2 + (.I0(\di_reg[11]_i_2__2_n_0 ), + .I1(\di_reg[11]_i_3__2_n_0 ), + .O(di_reg[11]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[12]), + .Q(drp_di_48[12]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[12]_i_1__2 + (.I0(\di_reg[12]_i_2__2_n_0 ), + .I1(\di_reg[12]_i_3__2_n_0 ), + .O(di_reg[12]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[13]), + .Q(drp_di_48[13]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[13]_i_1__2 + (.I0(\di_reg[13]_i_2__2_n_0 ), + .I1(\di_reg[13]_i_3__2_n_0 ), + .O(di_reg[13]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[14]), + .Q(drp_di_48[14]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[15]), + .Q(drp_di_48[15]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[1]), + .Q(drp_di_48[1]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[1]_i_1__2 + (.I0(\di_reg[1]_i_2__2_n_0 ), + .I1(\di_reg[1]_i_3__2_n_0 ), + .O(di_reg[1]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[2]), + .Q(drp_di_48[2]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[2]_i_1__2 + (.I0(\di_reg[2]_i_2__2_n_0 ), + .I1(\di_reg[2]_i_3__2_n_0 ), + .O(di_reg[2]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[3]), + .Q(drp_di_48[3]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[3]_i_1__2 + (.I0(\di_reg[3]_i_2__2_n_0 ), + .I1(\di_reg[3]_i_3__2_n_0 ), + .O(di_reg[3]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[4]), + .Q(drp_di_48[4]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[5]), + .Q(drp_di_48[5]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[5]_i_1__2 + (.I0(\di_reg[5]_i_2__2_n_0 ), + .I1(\di_reg[5]_i_3__2_n_0 ), + .O(di_reg[5]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[6]), + .Q(drp_di_48[6]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[6]_i_1__2 + (.I0(\di_reg[6]_i_2__2_n_0 ), + .I1(\di_reg[6]_i_3__2_n_0 ), + .O(di_reg[6]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[7]), + .Q(drp_di_48[7]), + .R(RST_DCLK_RESET)); + MUXF7 \di_reg_reg[7]_i_1__2 + (.I0(\di_reg[7]_i_2__2_n_0 ), + .I1(\di_reg[7]_i_3__2_n_0 ), + .O(di_reg[7]), + .S(index[4])); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[8]), + .Q(drp_di_48[8]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di_reg[9]), + .Q(drp_di_48[9]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[0]), + .Q(do_reg1[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[10]), + .Q(do_reg1[10]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[11]), + .Q(do_reg1[11]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[12]), + .Q(do_reg1[12]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[13]), + .Q(do_reg1[13]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[14]), + .Q(do_reg1[14]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[15]), + .Q(do_reg1[15]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[1]), + .Q(do_reg1[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[2]), + .Q(do_reg1[2]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[3]), + .Q(do_reg1[3]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[4]), + .Q(do_reg1[4]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[5]), + .Q(do_reg1[5]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[6]), + .Q(do_reg1[6]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[7]), + .Q(do_reg1[7]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[8]), + .Q(do_reg1[8]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[9]), + .Q(do_reg1[9]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[0]), + .Q(do_reg2[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[10]), + .Q(do_reg2[10]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[11]), + .Q(do_reg2[11]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[12]), + .Q(do_reg2[12]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[13]), + .Q(do_reg2[13]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[14]), + .Q(do_reg2[14]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[15]), + .Q(do_reg2[15]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[1]), + .Q(do_reg2[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[2]), + .Q(do_reg2[2]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[3]), + .Q(do_reg2[3]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[4]), + .Q(do_reg2[4]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[5]), + .Q(do_reg2[5]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[6]), + .Q(do_reg2[6]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[7]), + .Q(do_reg2[7]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[8]), + .Q(do_reg2[8]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[9]), + .Q(do_reg2[9]), + .R(RST_DCLK_RESET)); + LUT4 #( + .INIT(16'h0001)) + done_i_1__3 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(start_reg2), + .I3(\fsm_reg_n_0_[1] ), + .O(done_i_1__3_n_0)); + FDRE #( + .INIT(1'b0)) + done_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(done_i_1__3_n_0), + .Q(DRP_DONE), + .R(RST_DCLK_RESET)); + LUT6 #( + .INIT(64'h0737FFFF07370000)) + \fsm[0]_i_1__7 + (.I0(fsm1), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(rdy_reg2), + .I4(\fsm_reg_n_0_[2] ), + .I5(\fsm[0]_i_2__7_n_0 ), + .O(fsm[0])); + LUT5 #( + .INIT(32'h47FF47CC)) + \fsm[0]_i_2__7 + (.I0(rdy_reg2), + .I1(\fsm_reg_n_0_[1] ), + .I2(load_cnt), + .I3(\fsm_reg_n_0_[0] ), + .I4(start_reg2), + .O(\fsm[0]_i_2__7_n_0 )); + LUT5 #( + .INIT(32'h1D501850)) + \fsm[1]_i_1__7 + (.I0(\fsm_reg_n_0_[2] ), + .I1(rdy_reg2), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(load_cnt), + .O(fsm[1])); + LUT4 #( + .INIT(16'h6222)) + \fsm[2]_i_1__3 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(rdy_reg2), + .O(fsm[2])); + FDRE #( + .INIT(1'b0)) + \fsm_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(fsm[0]), + .Q(\fsm_reg_n_0_[0] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \fsm_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(fsm[1]), + .Q(\fsm_reg_n_0_[1] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \fsm_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(fsm[2]), + .Q(\fsm_reg_n_0_[2] ), + .R(RST_DCLK_RESET)); + (* SOFT_HLUTNM = "soft_lutpair177" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_10__2 + (.I0(drp_di_48[12]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[12])); + (* SOFT_HLUTNM = "soft_lutpair176" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_11__2 + (.I0(drp_di_48[11]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[11])); + (* SOFT_HLUTNM = "soft_lutpair176" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_12__2 + (.I0(drp_di_48[10]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[10])); + (* SOFT_HLUTNM = "soft_lutpair175" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_13__2 + (.I0(drp_di_48[9]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[9])); + (* SOFT_HLUTNM = "soft_lutpair175" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_14__2 + (.I0(drp_di_48[8]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[8])); + (* SOFT_HLUTNM = "soft_lutpair174" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_15__2 + (.I0(drp_di_48[7]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[7])); + (* SOFT_HLUTNM = "soft_lutpair174" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_16__2 + (.I0(drp_di_48[6]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[6])); + (* SOFT_HLUTNM = "soft_lutpair173" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_17__2 + (.I0(drp_di_48[5]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[5])); + (* SOFT_HLUTNM = "soft_lutpair173" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_18__2 + (.I0(drp_di_48[4]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[4])); + (* SOFT_HLUTNM = "soft_lutpair172" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_19__2 + (.I0(drp_di_48[3]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[3])); + (* SOFT_HLUTNM = "soft_lutpair172" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_20__2 + (.I0(drp_di_48[2]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[2])); + (* SOFT_HLUTNM = "soft_lutpair171" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_21__2 + (.I0(drp_di_48[1]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[1])); + (* SOFT_HLUTNM = "soft_lutpair171" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_22__2 + (.I0(drp_di_48[0]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[0])); + (* SOFT_HLUTNM = "soft_lutpair166" *) + LUT3 #( + .INIT(8'h12)) + \gtx_channel.gtxe2_channel_i_i_3__2 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\fsm_reg[1]_0 )); + (* SOFT_HLUTNM = "soft_lutpair170" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_40__2 + (.I0(drp_addr_27[7]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[7])); + (* SOFT_HLUTNM = "soft_lutpair170" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_41__2 + (.I0(drp_addr_27[6]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[6])); + (* SOFT_HLUTNM = "soft_lutpair169" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_42__2 + (.I0(drp_addr_27[5]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[5])); + (* SOFT_HLUTNM = "soft_lutpair169" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_43__2 + (.I0(drp_addr_27[4]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[4])); + (* SOFT_HLUTNM = "soft_lutpair168" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_44__2 + (.I0(drp_addr_27[3]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[3])); + (* SOFT_HLUTNM = "soft_lutpair168" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_45__2 + (.I0(drp_addr_27[2]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[2])); + (* SOFT_HLUTNM = "soft_lutpair167" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_46__2 + (.I0(drp_addr_27[1]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[1])); + (* SOFT_HLUTNM = "soft_lutpair166" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_47 + (.I0(drp_addr_27[0]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPADDR[0])); + (* SOFT_HLUTNM = "soft_lutpair167" *) + LUT3 #( + .INIT(8'h10)) + \gtx_channel.gtxe2_channel_i_i_4__2 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\fsm_reg[1]_1 )); + (* SOFT_HLUTNM = "soft_lutpair178" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_7__2 + (.I0(drp_di_48[15]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[15])); + (* SOFT_HLUTNM = "soft_lutpair178" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_8__2 + (.I0(drp_di_48[14]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[14])); + (* SOFT_HLUTNM = "soft_lutpair177" *) + LUT4 #( + .INIT(16'hAAA8)) + \gtx_channel.gtxe2_channel_i_i_9__2 + (.I0(drp_di_48[13]), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .O(DRPDI[13])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gtxreset_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(DRP_GTXRESET), + .Q(gtxreset_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gtxreset_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(gtxreset_reg1), + .Q(gtxreset_reg2), + .R(RST_DCLK_RESET)); + (* SOFT_HLUTNM = "soft_lutpair163" *) + LUT4 #( + .INIT(16'h0100)) + \index[0]_i_1__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(fsm1), + .I2(index[0]), + .I3(\fsm_reg_n_0_[2] ), + .O(\index[0]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair163" *) + LUT5 #( + .INIT(32'h00140000)) + \index[1]_i_1__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[1]), + .I2(index[0]), + .I3(fsm1), + .I4(\fsm_reg_n_0_[2] ), + .O(\index[1]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'h0000144400000000)) + \index[2]_i_1__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[2]), + .I2(index[1]), + .I3(index[0]), + .I4(fsm1), + .I5(\fsm_reg_n_0_[2] ), + .O(\index[2]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'h0000144400000000)) + \index[3]_i_1__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[3]), + .I2(index[2]), + .I3(\index[3]_i_2__2_n_0 ), + .I4(fsm1), + .I5(\fsm_reg_n_0_[2] ), + .O(\index[3]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair179" *) + LUT2 #( + .INIT(4'h8)) + \index[3]_i_2__2 + (.I0(index[1]), + .I1(index[0]), + .O(\index[3]_i_2__2_n_0 )); + LUT3 #( + .INIT(8'hA1)) + \index[4]_i_1__2 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\index[4]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'h0000144400000000)) + \index[4]_i_2__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(index[4]), + .I2(index[3]), + .I3(\index[4]_i_3__2_n_0 ), + .I4(fsm1), + .I5(\fsm_reg_n_0_[2] ), + .O(\index[4]_i_2__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair179" *) + LUT3 #( + .INIT(8'h80)) + \index[4]_i_3__2 + (.I0(index[2]), + .I1(index[0]), + .I2(index[1]), + .O(\index[4]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'h1000000110000000)) + \index[4]_i_4__2 + (.I0(index[3]), + .I1(index[1]), + .I2(index[0]), + .I3(index[4]), + .I4(index[2]), + .I5(x16x20_mode_reg2), + .O(fsm1)); + FDRE #( + .INIT(1'b0)) + \index_reg[0] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__2_n_0 ), + .D(\index[0]_i_1__2_n_0 ), + .Q(index[0]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[1] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__2_n_0 ), + .D(\index[1]_i_1__2_n_0 ), + .Q(index[1]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[2] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__2_n_0 ), + .D(\index[2]_i_1__2_n_0 ), + .Q(index[2]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[3] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__2_n_0 ), + .D(\index[3]_i_1__2_n_0 ), + .Q(index[3]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[4] + (.C(pipe_dclk_in), + .CE(\index[4]_i_1__2_n_0 ), + .D(\index[4]_i_2__2_n_0 ), + .Q(index[4]), + .R(RST_DCLK_RESET)); + LUT3 #( + .INIT(8'h10)) + \load_cnt[0]_i_1__3 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .O(\load_cnt[0]_i_1__3_n_0 )); + FDRE #( + .INIT(1'b0)) + \load_cnt_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\load_cnt[0]_i_1__3_n_0 ), + .Q(load_cnt), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg1_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\rate_reg1_reg[0]_0 ), + .Q(rate_reg1[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg1_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rate_reg1[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg2_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(rate_reg1[0]), + .Q(rate_reg2[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg2_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(rate_reg1[1]), + .Q(rate_reg2[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rdy_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(DRP_RDY), + .Q(rdy_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rdy_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(rdy_reg1), + .Q(rdy_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE start_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(RATE_DRP_START), + .Q(start_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE start_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(start_reg1), + .Q(start_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(RATE_DRP_X16), + .Q(x16_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(x16_reg1), + .Q(x16_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16x20_mode_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(RATE_DRP_X16X20_MODE), + .Q(x16x20_mode_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE x16x20_mode_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(x16x20_mode_reg1), + .Q(x16x20_mode_reg2), + .R(RST_DCLK_RESET)); +endmodule + +module pcie_7x_0_pcie_7x_0_pipe_eq + (TXPRECURSOR, + TXMAINCURSOR, + TXPOSTCURSOR, + USER_RXEQ_ADAPT_DONE, + RST_CPLLRESET, + pipe_pclk_in, + USER_RATE_GEN3); + output [4:0]TXPRECURSOR; + output [6:0]TXMAINCURSOR; + output [4:0]TXPOSTCURSOR; + output USER_RXEQ_ADAPT_DONE; + input RST_CPLLRESET; + input pipe_pclk_in; + input USER_RATE_GEN3; + + wire \FSM_onehot_fsm_rx[1]_i_1_n_0 ; + wire \FSM_onehot_fsm_rx[1]_i_2_n_0 ; + wire \FSM_onehot_fsm_rx[3]_i_1_n_0 ; + wire \FSM_onehot_fsm_rx[4]_i_1_n_0 ; + wire \FSM_onehot_fsm_rx_reg_n_0_[1] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[2] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[3] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[4] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[5] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[6] ; + wire \FSM_sequential_fsm_tx[1]_i_2_n_0 ; + wire \FSM_sequential_fsm_tx[2]_i_2_n_0 ; + wire RST_CPLLRESET; + wire [6:0]TXMAINCURSOR; + wire [4:0]TXPOSTCURSOR; + wire [4:0]TXPRECURSOR; + wire USER_RATE_GEN3; + wire USER_RXEQ_ADAPT_DONE; + wire [2:0]fsm_tx; + wire [2:0]fsm_tx__0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2; + wire [17:0]p_0_out; + wire pipe_pclk_in; + wire rxeq_adapt_done_i_2_n_0; + wire rxeq_adapt_done_reg_i_2_n_0; + wire rxeq_adapt_done_reg_reg_n_0; + wire [2:0]rxeq_cnt; + wire \rxeq_cnt_reg_n_0_[0] ; + wire \rxeq_cnt_reg_n_0_[1] ; + wire \rxeq_cnt_reg_n_0_[2] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxeq_control_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxeq_control_reg2; + wire [5:0]rxeq_fs; + wire \rxeq_fs[5]_i_1_n_0 ; + wire \rxeq_fs_reg_n_0_[0] ; + wire \rxeq_fs_reg_n_0_[1] ; + wire \rxeq_fs_reg_n_0_[2] ; + wire \rxeq_fs_reg_n_0_[3] ; + wire \rxeq_fs_reg_n_0_[4] ; + wire \rxeq_fs_reg_n_0_[5] ; + wire [5:0]rxeq_lf; + wire \rxeq_lf[5]_i_1_n_0 ; + wire \rxeq_lf_reg_n_0_[0] ; + wire \rxeq_lf_reg_n_0_[1] ; + wire \rxeq_lf_reg_n_0_[2] ; + wire \rxeq_lf_reg_n_0_[3] ; + wire \rxeq_lf_reg_n_0_[4] ; + wire \rxeq_lf_reg_n_0_[5] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]rxeq_lffs_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]rxeq_lffs_reg2; + wire rxeq_new_txcoeff_req; + wire rxeq_new_txcoeff_req_reg_n_0; + wire \rxeq_preset[0]_i_1_n_0 ; + wire \rxeq_preset[1]_i_1_n_0 ; + wire \rxeq_preset[2]_i_1_n_0 ; + wire \rxeq_preset[2]_i_2_n_0 ; + wire \rxeq_preset[2]_i_3_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]rxeq_preset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]rxeq_preset_reg2; + wire \rxeq_preset_reg_n_0_[0] ; + wire \rxeq_preset_reg_n_0_[1] ; + wire \rxeq_preset_reg_n_0_[2] ; + wire rxeq_preset_valid; + wire rxeq_scan_i_n_0; + wire rxeq_scan_i_n_1; + wire rxeq_scan_i_n_2; + wire rxeq_scan_i_n_4; + wire rxeq_scan_i_n_5; + wire [17:0]rxeq_txcoeff; + wire \rxeq_txcoeff_reg_n_0_[0] ; + wire \rxeq_txcoeff_reg_n_0_[10] ; + wire \rxeq_txcoeff_reg_n_0_[11] ; + wire \rxeq_txcoeff_reg_n_0_[12] ; + wire \rxeq_txcoeff_reg_n_0_[13] ; + wire \rxeq_txcoeff_reg_n_0_[14] ; + wire \rxeq_txcoeff_reg_n_0_[15] ; + wire \rxeq_txcoeff_reg_n_0_[16] ; + wire \rxeq_txcoeff_reg_n_0_[17] ; + wire \rxeq_txcoeff_reg_n_0_[1] ; + wire \rxeq_txcoeff_reg_n_0_[2] ; + wire \rxeq_txcoeff_reg_n_0_[3] ; + wire \rxeq_txcoeff_reg_n_0_[4] ; + wire \rxeq_txcoeff_reg_n_0_[5] ; + wire \rxeq_txcoeff_reg_n_0_[6] ; + wire \rxeq_txcoeff_reg_n_0_[7] ; + wire \rxeq_txcoeff_reg_n_0_[8] ; + wire \rxeq_txcoeff_reg_n_0_[9] ; + wire [3:0]rxeq_txpreset; + wire \rxeq_txpreset[3]_i_1_n_0 ; + wire \rxeq_txpreset[3]_i_3_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxeq_txpreset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxeq_txpreset_reg2; + wire \rxeq_txpreset_reg_n_0_[0] ; + wire \rxeq_txpreset_reg_n_0_[1] ; + wire \rxeq_txpreset_reg_n_0_[2] ; + wire \rxeq_txpreset_reg_n_0_[3] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_en_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_en_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_mode_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_mode_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]rxeq_user_txcoeff_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]rxeq_user_txcoeff_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txeq_control_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txeq_control_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]txeq_deemph_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]txeq_deemph_reg2; + wire \txeq_preset[17]_i_1_n_0 ; + wire \txeq_preset[3]_i_1_n_0 ; + wire \txeq_preset[7]_i_1_n_0 ; + wire txeq_preset_done; + wire txeq_preset_done_i_1_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txeq_preset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txeq_preset_reg2; + wire \txeq_preset_reg_n_0_[0] ; + wire \txeq_preset_reg_n_0_[10] ; + wire \txeq_preset_reg_n_0_[11] ; + wire \txeq_preset_reg_n_0_[12] ; + wire \txeq_preset_reg_n_0_[13] ; + wire \txeq_preset_reg_n_0_[14] ; + wire \txeq_preset_reg_n_0_[15] ; + wire \txeq_preset_reg_n_0_[16] ; + wire \txeq_preset_reg_n_0_[17] ; + wire \txeq_preset_reg_n_0_[1] ; + wire \txeq_preset_reg_n_0_[2] ; + wire \txeq_preset_reg_n_0_[3] ; + wire \txeq_preset_reg_n_0_[7] ; + wire \txeq_preset_reg_n_0_[8] ; + wire \txeq_preset_reg_n_0_[9] ; + wire txeq_txcoeff; + wire \txeq_txcoeff[0]_i_1_n_0 ; + wire \txeq_txcoeff[0]_i_2_n_0 ; + wire \txeq_txcoeff[10]_i_1_n_0 ; + wire \txeq_txcoeff[10]_i_2_n_0 ; + wire \txeq_txcoeff[11]_i_1_n_0 ; + wire \txeq_txcoeff[11]_i_2_n_0 ; + wire \txeq_txcoeff[12]_i_1_n_0 ; + wire \txeq_txcoeff[12]_i_2_n_0 ; + wire \txeq_txcoeff[13]_i_1_n_0 ; + wire \txeq_txcoeff[13]_i_2_n_0 ; + wire \txeq_txcoeff[14]_i_1_n_0 ; + wire \txeq_txcoeff[14]_i_2_n_0 ; + wire \txeq_txcoeff[15]_i_1_n_0 ; + wire \txeq_txcoeff[15]_i_2_n_0 ; + wire \txeq_txcoeff[16]_i_1_n_0 ; + wire \txeq_txcoeff[16]_i_2_n_0 ; + wire \txeq_txcoeff[17]_i_1_n_0 ; + wire \txeq_txcoeff[17]_i_2_n_0 ; + wire \txeq_txcoeff[18]_i_2_n_0 ; + wire \txeq_txcoeff[18]_i_3_n_0 ; + wire \txeq_txcoeff[1]_i_1_n_0 ; + wire \txeq_txcoeff[1]_i_2_n_0 ; + wire \txeq_txcoeff[2]_i_1_n_0 ; + wire \txeq_txcoeff[2]_i_2_n_0 ; + wire \txeq_txcoeff[3]_i_1_n_0 ; + wire \txeq_txcoeff[3]_i_2_n_0 ; + wire \txeq_txcoeff[4]_i_1_n_0 ; + wire \txeq_txcoeff[4]_i_2_n_0 ; + wire \txeq_txcoeff[5]_i_1_n_0 ; + wire \txeq_txcoeff[5]_i_2_n_0 ; + wire \txeq_txcoeff[6]_i_1_n_0 ; + wire \txeq_txcoeff[6]_i_2_n_0 ; + wire \txeq_txcoeff[7]_i_1_n_0 ; + wire \txeq_txcoeff[7]_i_2_n_0 ; + wire \txeq_txcoeff[8]_i_1_n_0 ; + wire \txeq_txcoeff[8]_i_2_n_0 ; + wire \txeq_txcoeff[9]_i_1_n_0 ; + wire \txeq_txcoeff[9]_i_2_n_0 ; + wire [1:0]txeq_txcoeff_cnt; + wire \txeq_txcoeff_cnt_reg_n_0_[0] ; + wire \txeq_txcoeff_cnt_reg_n_0_[1] ; + wire \txeq_txcoeff_reg_n_0_[0] ; + wire \txeq_txcoeff_reg_n_0_[10] ; + wire \txeq_txcoeff_reg_n_0_[11] ; + wire \txeq_txcoeff_reg_n_0_[12] ; + wire \txeq_txcoeff_reg_n_0_[13] ; + wire \txeq_txcoeff_reg_n_0_[14] ; + wire \txeq_txcoeff_reg_n_0_[15] ; + wire \txeq_txcoeff_reg_n_0_[16] ; + wire \txeq_txcoeff_reg_n_0_[17] ; + wire \txeq_txcoeff_reg_n_0_[18] ; + wire \txeq_txcoeff_reg_n_0_[1] ; + wire \txeq_txcoeff_reg_n_0_[2] ; + wire \txeq_txcoeff_reg_n_0_[3] ; + wire \txeq_txcoeff_reg_n_0_[4] ; + wire \txeq_txcoeff_reg_n_0_[5] ; + wire \txeq_txcoeff_reg_n_0_[6] ; + wire \txeq_txcoeff_reg_n_0_[7] ; + wire \txeq_txcoeff_reg_n_0_[8] ; + wire \txeq_txcoeff_reg_n_0_[9] ; + + LUT5 #( + .INIT(32'hABABABAA)) + \FSM_onehot_fsm_rx[1]_i_1 + (.I0(\FSM_onehot_fsm_rx[1]_i_2_n_0 ), + .I1(rxeq_control_reg2[1]), + .I2(rxeq_control_reg2[0]), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .O(\FSM_onehot_fsm_rx[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \FSM_onehot_fsm_rx[1]_i_2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .O(\FSM_onehot_fsm_rx[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF8FF88888888)) + \FSM_onehot_fsm_rx[3]_i_1 + (.I0(rxeq_control_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\rxeq_cnt_reg_n_0_[2] ), + .I3(\rxeq_cnt_reg_n_0_[1] ), + .I4(\rxeq_cnt_reg_n_0_[0] ), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\FSM_onehot_fsm_rx[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT5 #( + .INIT(32'h2ABA2AAA)) + \FSM_onehot_fsm_rx[4]_i_1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(\rxeq_cnt_reg_n_0_[2] ), + .I2(\rxeq_cnt_reg_n_0_[1] ), + .I3(\rxeq_cnt_reg_n_0_[0] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\FSM_onehot_fsm_rx[4]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDSE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx[1]_i_1_n_0 ), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_2), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx[3]_i_1_n_0 ), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx[4]_i_1_n_0 ), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_1), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_0), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hC04FC043C04FF04F)) + \FSM_sequential_fsm_tx[0]_i_1 + (.I0(\FSM_sequential_fsm_tx[1]_i_2_n_0 ), + .I1(fsm_tx[0]), + .I2(fsm_tx[1]), + .I3(fsm_tx[2]), + .I4(txeq_control_reg2[1]), + .I5(txeq_control_reg2[0]), + .O(fsm_tx__0[0])); + LUT6 #( + .INIT(64'h3F703F7C3F7C0F70)) + \FSM_sequential_fsm_tx[1]_i_1 + (.I0(\FSM_sequential_fsm_tx[1]_i_2_n_0 ), + .I1(fsm_tx[0]), + .I2(fsm_tx[1]), + .I3(fsm_tx[2]), + .I4(txeq_control_reg2[1]), + .I5(txeq_control_reg2[0]), + .O(fsm_tx__0[1])); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_fsm_tx[1]_i_2 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .O(\FSM_sequential_fsm_tx[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h3A2A2A227F7F7F77)) + \FSM_sequential_fsm_tx[2]_i_1 + (.I0(fsm_tx[2]), + .I1(fsm_tx[1]), + .I2(fsm_tx[0]), + .I3(txeq_control_reg2[1]), + .I4(txeq_control_reg2[0]), + .I5(\FSM_sequential_fsm_tx[2]_i_2_n_0 ), + .O(fsm_tx__0[2])); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT5 #( + .INIT(32'hD0FFDFFF)) + \FSM_sequential_fsm_tx[2]_i_2 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I2(fsm_tx[0]), + .I3(fsm_tx[1]), + .I4(txeq_preset_done), + .O(\FSM_sequential_fsm_tx[2]_i_2_n_0 )); + (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) + FDSE #( + .INIT(1'b0)) + \FSM_sequential_fsm_tx_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm_tx__0[0]), + .Q(fsm_tx[0]), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_fsm_tx_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm_tx__0[1]), + .Q(fsm_tx[1]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_fsm_tx_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm_tx__0[2]), + .Q(fsm_tx[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RATE_GEN3), + .Q(gen3_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_reg1), + .Q(gen3_reg2), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_22 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[17] ), + .O(TXPOSTCURSOR[4])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_23 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[16] ), + .O(TXPOSTCURSOR[3])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_24 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[15] ), + .O(TXPOSTCURSOR[2])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_25 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[14] ), + .O(TXPOSTCURSOR[1])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_26 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[13] ), + .O(TXPOSTCURSOR[0])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_27 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[4] ), + .O(TXPRECURSOR[4])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_28 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[3] ), + .O(TXPRECURSOR[3])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_29 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[2] ), + .O(TXPRECURSOR[2])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_30 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[1] ), + .O(TXPRECURSOR[1])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_31 + (.I0(\txeq_txcoeff_reg_n_0_[0] ), + .I1(gen3_reg2), + .O(TXPRECURSOR[0])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_32 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[12] ), + .O(TXMAINCURSOR[6])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_33 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[11] ), + .O(TXMAINCURSOR[5])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_34 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[10] ), + .O(TXMAINCURSOR[4])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_35 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[9] ), + .O(TXMAINCURSOR[3])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_36 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[8] ), + .O(TXMAINCURSOR[2])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_37 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[7] ), + .O(TXMAINCURSOR[1])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_38 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[6] ), + .O(TXMAINCURSOR[0])); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + rxeq_adapt_done_i_2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .O(rxeq_adapt_done_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + rxeq_adapt_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_5), + .Q(USER_RXEQ_ADAPT_DONE), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'h08)) + rxeq_adapt_done_reg_i_2 + (.I0(rxeq_control_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(rxeq_control_reg2[1]), + .O(rxeq_adapt_done_reg_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + rxeq_adapt_done_reg_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_4), + .Q(rxeq_adapt_done_reg_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h8888FFF8)) + \rxeq_cnt[0]_i_1 + (.I0(rxeq_control_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I4(\rxeq_cnt_reg_n_0_[0] ), + .O(rxeq_cnt[0])); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT4 #( + .INIT(16'h6660)) + \rxeq_cnt[1]_i_1 + (.I0(\rxeq_cnt_reg_n_0_[0] ), + .I1(\rxeq_cnt_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(rxeq_cnt[1])); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT5 #( + .INIT(32'h78787800)) + \rxeq_cnt[2]_i_1 + (.I0(\rxeq_cnt_reg_n_0_[1] ), + .I1(\rxeq_cnt_reg_n_0_[0] ), + .I2(\rxeq_cnt_reg_n_0_[2] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(rxeq_cnt[2])); + FDRE #( + .INIT(1'b0)) + \rxeq_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_cnt[0]), + .Q(\rxeq_cnt_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_cnt[1]), + .Q(\rxeq_cnt_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_cnt[2]), + .Q(\rxeq_cnt_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_control_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_control_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_control_reg1[0]), + .Q(rxeq_control_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_control_reg1[1]), + .Q(rxeq_control_reg2[1]), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[0]_i_1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[0]), + .O(rxeq_fs[0])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[1]_i_1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[1]), + .O(rxeq_fs[1])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[2]_i_1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[2]), + .O(rxeq_fs[2])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[3]_i_1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[3]), + .O(rxeq_fs[3])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[4]_i_1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[4]), + .O(rxeq_fs[4])); + LUT3 #( + .INIT(8'hF8)) + \rxeq_fs[5]_i_1 + (.I0(rxeq_control_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx[1]_i_2_n_0 ), + .O(\rxeq_fs[5]_i_1_n_0 )); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[5]_i_2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[5]), + .O(rxeq_fs[5])); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1_n_0 ), + .D(rxeq_fs[0]), + .Q(\rxeq_fs_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1_n_0 ), + .D(rxeq_fs[1]), + .Q(\rxeq_fs_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1_n_0 ), + .D(rxeq_fs[2]), + .Q(\rxeq_fs_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1_n_0 ), + .D(rxeq_fs[3]), + .Q(\rxeq_fs_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[4] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1_n_0 ), + .D(rxeq_fs[4]), + .Q(\rxeq_fs_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[5] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1_n_0 ), + .D(rxeq_fs[5]), + .Q(\rxeq_fs_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[0]_i_1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[0]), + .O(rxeq_lf[0])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[1]_i_1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[1]), + .O(rxeq_lf[1])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[2]_i_1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[2]), + .O(rxeq_lf[2])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[3]_i_1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[3]), + .O(rxeq_lf[3])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[4]_i_1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[4]), + .O(rxeq_lf[4])); + LUT5 #( + .INIT(32'hEAAAAAAA)) + \rxeq_lf[5]_i_1 + (.I0(\FSM_onehot_fsm_rx[1]_i_2_n_0 ), + .I1(\rxeq_cnt_reg_n_0_[2] ), + .I2(\rxeq_cnt_reg_n_0_[0] ), + .I3(\rxeq_cnt_reg_n_0_[1] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .O(\rxeq_lf[5]_i_1_n_0 )); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[5]_i_2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[5]), + .O(rxeq_lf[5])); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1_n_0 ), + .D(rxeq_lf[0]), + .Q(\rxeq_lf_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1_n_0 ), + .D(rxeq_lf[1]), + .Q(\rxeq_lf_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1_n_0 ), + .D(rxeq_lf[2]), + .Q(\rxeq_lf_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1_n_0 ), + .D(rxeq_lf[3]), + .Q(\rxeq_lf_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[4] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1_n_0 ), + .D(rxeq_lf[4]), + .Q(\rxeq_lf_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[5] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1_n_0 ), + .D(rxeq_lf[5]), + .Q(\rxeq_lf_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[0]), + .Q(rxeq_lffs_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[1]), + .Q(rxeq_lffs_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[2]), + .Q(rxeq_lffs_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[3]), + .Q(rxeq_lffs_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[4]), + .Q(rxeq_lffs_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[5]), + .Q(rxeq_lffs_reg2[5]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + rxeq_new_txcoeff_req_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_new_txcoeff_req), + .Q(rxeq_new_txcoeff_req_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hA8FFA800)) + \rxeq_preset[0]_i_1 + (.I0(rxeq_preset_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(\rxeq_preset[2]_i_2_n_0 ), + .I4(\rxeq_preset_reg_n_0_[0] ), + .O(\rxeq_preset[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hA8FFA800)) + \rxeq_preset[1]_i_1 + (.I0(rxeq_preset_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(\rxeq_preset[2]_i_2_n_0 ), + .I4(\rxeq_preset_reg_n_0_[1] ), + .O(\rxeq_preset[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hA8FFA800)) + \rxeq_preset[2]_i_1 + (.I0(rxeq_preset_reg2[2]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(\rxeq_preset[2]_i_2_n_0 ), + .I4(\rxeq_preset_reg_n_0_[2] ), + .O(\rxeq_preset[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF0002)) + \rxeq_preset[2]_i_2 + (.I0(\rxeq_preset[2]_i_3_n_0 ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .I4(rxeq_adapt_done_reg_i_2_n_0), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .O(\rxeq_preset[2]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT2 #( + .INIT(4'h1)) + \rxeq_preset[2]_i_3 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\rxeq_preset[2]_i_3_n_0 )); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_preset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_preset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_preset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_reg1[0]), + .Q(rxeq_preset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_reg1[1]), + .Q(rxeq_preset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_reg1[2]), + .Q(rxeq_preset_reg2[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_preset_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxeq_preset[0]_i_1_n_0 ), + .Q(\rxeq_preset_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_preset_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxeq_preset[1]_i_1_n_0 ), + .Q(\rxeq_preset_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_preset_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxeq_preset[2]_i_1_n_0 ), + .Q(\rxeq_preset_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + rxeq_preset_valid_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .Q(rxeq_preset_valid), + .R(RST_CPLLRESET)); + pcie_7x_0_pcie_7x_0_rxeq_scan_59 rxeq_scan_i + (.D({rxeq_scan_i_n_0,rxeq_scan_i_n_1,rxeq_scan_i_n_2}), + .\FSM_onehot_fsm_rx_reg[5] ({\rxeq_cnt_reg_n_0_[2] ,\rxeq_cnt_reg_n_0_[1] ,\rxeq_cnt_reg_n_0_[0] }), + .Q({\FSM_onehot_fsm_rx_reg_n_0_[6] ,\FSM_onehot_fsm_rx_reg_n_0_[5] ,\FSM_onehot_fsm_rx_reg_n_0_[4] ,\FSM_onehot_fsm_rx_reg_n_0_[2] ,\FSM_onehot_fsm_rx_reg_n_0_[1] }), + .RST_CPLLRESET(RST_CPLLRESET), + .USER_RXEQ_ADAPT_DONE(USER_RXEQ_ADAPT_DONE), + .adapt_done_reg_0(rxeq_scan_i_n_4), + .\fs_reg1_reg[5]_0 ({\rxeq_fs_reg_n_0_[5] ,\rxeq_fs_reg_n_0_[4] ,\rxeq_fs_reg_n_0_[3] ,\rxeq_fs_reg_n_0_[2] ,\rxeq_fs_reg_n_0_[1] ,\rxeq_fs_reg_n_0_[0] }), + .\lf_reg1_reg[5]_0 ({\rxeq_lf_reg_n_0_[5] ,\rxeq_lf_reg_n_0_[4] ,\rxeq_lf_reg_n_0_[3] ,\rxeq_lf_reg_n_0_[2] ,\rxeq_lf_reg_n_0_[1] ,\rxeq_lf_reg_n_0_[0] }), + .new_txcoeff_done_reg_0(rxeq_scan_i_n_5), + .new_txcoeff_req_reg1_reg_0(rxeq_new_txcoeff_req_reg_n_0), + .out(rxeq_control_reg2), + .pipe_pclk_in(pipe_pclk_in), + .\preset_reg1_reg[2]_0 ({\rxeq_preset_reg_n_0_[2] ,\rxeq_preset_reg_n_0_[1] ,\rxeq_preset_reg_n_0_[0] }), + .rxeq_adapt_done_reg(rxeq_adapt_done_i_2_n_0), + .rxeq_adapt_done_reg_reg(\FSM_onehot_fsm_rx[1]_i_2_n_0 ), + .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_i_2_n_0), + .rxeq_adapt_done_reg_reg_1(rxeq_adapt_done_reg_reg_n_0), + .rxeq_new_txcoeff_req(rxeq_new_txcoeff_req), + .rxeq_preset_valid(rxeq_preset_valid), + .\txcoeff_reg1_reg[17]_0 ({\rxeq_txcoeff_reg_n_0_[17] ,\rxeq_txcoeff_reg_n_0_[16] ,\rxeq_txcoeff_reg_n_0_[15] ,\rxeq_txcoeff_reg_n_0_[14] ,\rxeq_txcoeff_reg_n_0_[13] ,\rxeq_txcoeff_reg_n_0_[12] ,\rxeq_txcoeff_reg_n_0_[11] ,\rxeq_txcoeff_reg_n_0_[10] ,\rxeq_txcoeff_reg_n_0_[9] ,\rxeq_txcoeff_reg_n_0_[8] ,\rxeq_txcoeff_reg_n_0_[7] ,\rxeq_txcoeff_reg_n_0_[6] ,\rxeq_txcoeff_reg_n_0_[5] ,\rxeq_txcoeff_reg_n_0_[4] ,\rxeq_txcoeff_reg_n_0_[3] ,\rxeq_txcoeff_reg_n_0_[2] ,\rxeq_txcoeff_reg_n_0_[1] ,\rxeq_txcoeff_reg_n_0_[0] }), + .\txpreset_reg1_reg[3]_0 ({\rxeq_txpreset_reg_n_0_[3] ,\rxeq_txpreset_reg_n_0_[2] ,\rxeq_txpreset_reg_n_0_[1] ,\rxeq_txpreset_reg_n_0_[0] })); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[0]_i_1 + (.I0(\rxeq_txcoeff_reg_n_0_[6] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[0])); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[10]_i_1 + (.I0(\rxeq_txcoeff_reg_n_0_[16] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[10])); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[11]_i_1 + (.I0(\rxeq_txcoeff_reg_n_0_[17] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[11])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[12]_i_1 + (.I0(txeq_deemph_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[12])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[13]_i_1 + (.I0(txeq_deemph_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[13])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[14]_i_1 + (.I0(txeq_deemph_reg2[2]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[14])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[15]_i_1 + (.I0(txeq_deemph_reg2[3]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[15])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[16]_i_1 + (.I0(txeq_deemph_reg2[4]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[16])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[17]_i_1 + (.I0(txeq_deemph_reg2[5]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[17])); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[1]_i_1 + (.I0(\rxeq_txcoeff_reg_n_0_[7] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[1])); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[2]_i_1 + (.I0(\rxeq_txcoeff_reg_n_0_[8] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[2])); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[3]_i_1 + (.I0(\rxeq_txcoeff_reg_n_0_[9] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[3])); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[4]_i_1 + (.I0(\rxeq_txcoeff_reg_n_0_[10] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[4])); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[5]_i_1 + (.I0(\rxeq_txcoeff_reg_n_0_[11] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[5])); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[6]_i_1 + (.I0(\rxeq_txcoeff_reg_n_0_[12] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[6])); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[7]_i_1 + (.I0(\rxeq_txcoeff_reg_n_0_[13] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[7])); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[8]_i_1 + (.I0(\rxeq_txcoeff_reg_n_0_[14] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[8])); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[9]_i_1 + (.I0(\rxeq_txcoeff_reg_n_0_[15] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[9])); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[0]), + .Q(\rxeq_txcoeff_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[10] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[10]), + .Q(\rxeq_txcoeff_reg_n_0_[10] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[11] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[11]), + .Q(\rxeq_txcoeff_reg_n_0_[11] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[12] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[12]), + .Q(\rxeq_txcoeff_reg_n_0_[12] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[13] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[13]), + .Q(\rxeq_txcoeff_reg_n_0_[13] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[14] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[14]), + .Q(\rxeq_txcoeff_reg_n_0_[14] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[15] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[15]), + .Q(\rxeq_txcoeff_reg_n_0_[15] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[16] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[16]), + .Q(\rxeq_txcoeff_reg_n_0_[16] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[17] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[17]), + .Q(\rxeq_txcoeff_reg_n_0_[17] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[1]), + .Q(\rxeq_txcoeff_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[2]), + .Q(\rxeq_txcoeff_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[3]), + .Q(\rxeq_txcoeff_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[4] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[4]), + .Q(\rxeq_txcoeff_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[5] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[5]), + .Q(\rxeq_txcoeff_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[6] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[6]), + .Q(\rxeq_txcoeff_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[7] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[7]), + .Q(\rxeq_txcoeff_reg_n_0_[7] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[8] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[8]), + .Q(\rxeq_txcoeff_reg_n_0_[8] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[9] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txcoeff[9]), + .Q(\rxeq_txcoeff_reg_n_0_[9] ), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[0]_i_1 + (.I0(rxeq_txpreset_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[0])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[1]_i_1 + (.I0(rxeq_txpreset_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[1])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[2]_i_1 + (.I0(rxeq_txpreset_reg2[2]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[2])); + LUT5 #( + .INIT(32'hFFFFF404)) + \rxeq_txpreset[3]_i_1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .I1(\rxeq_txpreset[3]_i_3_n_0 ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(rxeq_control_reg2[1]), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\rxeq_txpreset[3]_i_1_n_0 )); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[3]_i_2 + (.I0(rxeq_txpreset_reg2[3]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[3])); + LUT3 #( + .INIT(8'h01)) + \rxeq_txpreset[3]_i_3 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .O(\rxeq_txpreset[3]_i_3_n_0 )); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[0]), + .Q(rxeq_txpreset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[1]), + .Q(rxeq_txpreset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[2]), + .Q(rxeq_txpreset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[3]), + .Q(rxeq_txpreset_reg2[3]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txpreset[0]), + .Q(\rxeq_txpreset_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txpreset[1]), + .Q(\rxeq_txpreset_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txpreset[2]), + .Q(\rxeq_txpreset_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1_n_0 ), + .D(rxeq_txpreset[3]), + .Q(\rxeq_txpreset_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_en_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_en_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_en_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_en_reg1), + .Q(rxeq_user_en_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_mode_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_mode_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_mode_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_mode_reg1), + .Q(rxeq_user_mode_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[0]), + .Q(rxeq_user_txcoeff_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[10]), + .Q(rxeq_user_txcoeff_reg2[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[11]), + .Q(rxeq_user_txcoeff_reg2[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[12]), + .Q(rxeq_user_txcoeff_reg2[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[13]), + .Q(rxeq_user_txcoeff_reg2[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[14]), + .Q(rxeq_user_txcoeff_reg2[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[15]), + .Q(rxeq_user_txcoeff_reg2[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[16]), + .Q(rxeq_user_txcoeff_reg2[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[17]), + .Q(rxeq_user_txcoeff_reg2[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[1]), + .Q(rxeq_user_txcoeff_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[2]), + .Q(rxeq_user_txcoeff_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[3]), + .Q(rxeq_user_txcoeff_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[4]), + .Q(rxeq_user_txcoeff_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[5]), + .Q(rxeq_user_txcoeff_reg2[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[6]), + .Q(rxeq_user_txcoeff_reg2[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[7]), + .Q(rxeq_user_txcoeff_reg2[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[8]), + .Q(rxeq_user_txcoeff_reg2[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[9]), + .Q(rxeq_user_txcoeff_reg2[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_control_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_control_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_control_reg1[0]), + .Q(txeq_control_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_control_reg1[1]), + .Q(txeq_control_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \txeq_deemph_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[0]), + .S(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \txeq_deemph_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[0]), + .Q(txeq_deemph_reg2[0]), + .S(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[1]), + .Q(txeq_deemph_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[2]), + .Q(txeq_deemph_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[3]), + .Q(txeq_deemph_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[4]), + .Q(txeq_deemph_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[5]), + .Q(txeq_deemph_reg2[5]), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h00001000)) + \txeq_preset[0]_i_1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[2]), + .I2(txeq_preset_reg2[0]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[1]), + .O(p_0_out[0])); + LUT5 #( + .INIT(32'hABEAABAF)) + \txeq_preset[10]_i_1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[2]), + .I2(txeq_preset_reg2[0]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[1]), + .O(p_0_out[10])); + LUT5 #( + .INIT(32'hFFFF200D)) + \txeq_preset[11]_i_1 + (.I0(txeq_preset_reg2[1]), + .I1(txeq_preset_reg2[3]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[0]), + .I4(RST_CPLLRESET), + .O(p_0_out[11])); + LUT5 #( + .INIT(32'h01151110)) + \txeq_preset[12]_i_1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[3]), + .I2(txeq_preset_reg2[1]), + .I3(txeq_preset_reg2[2]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[12])); + LUT5 #( + .INIT(32'h01000010)) + \txeq_preset[13]_i_1 + (.I0(txeq_preset_reg2[2]), + .I1(RST_CPLLRESET), + .I2(txeq_preset_reg2[0]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[1]), + .O(p_0_out[13])); + LUT5 #( + .INIT(32'h01000010)) + \txeq_preset[14]_i_1 + (.I0(txeq_preset_reg2[2]), + .I1(RST_CPLLRESET), + .I2(txeq_preset_reg2[3]), + .I3(txeq_preset_reg2[1]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[14])); + LUT4 #( + .INIT(16'hF0F1)) + \txeq_preset[15]_i_1 + (.I0(txeq_preset_reg2[2]), + .I1(txeq_preset_reg2[1]), + .I2(RST_CPLLRESET), + .I3(txeq_preset_reg2[3]), + .O(p_0_out[15])); + LUT4 #( + .INIT(16'h0006)) + \txeq_preset[16]_i_1 + (.I0(txeq_preset_reg2[3]), + .I1(txeq_preset_reg2[0]), + .I2(txeq_preset_reg2[2]), + .I3(RST_CPLLRESET), + .O(p_0_out[16])); + LUT4 #( + .INIT(16'hAABA)) + \txeq_preset[17]_i_1 + (.I0(RST_CPLLRESET), + .I1(fsm_tx[0]), + .I2(fsm_tx[1]), + .I3(fsm_tx[2]), + .O(\txeq_preset[17]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFFF400D)) + \txeq_preset[17]_i_2 + (.I0(txeq_preset_reg2[3]), + .I1(txeq_preset_reg2[1]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[0]), + .I4(RST_CPLLRESET), + .O(p_0_out[17])); + LUT5 #( + .INIT(32'h00001004)) + \txeq_preset[1]_i_1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[3]), + .I2(txeq_preset_reg2[1]), + .I3(txeq_preset_reg2[2]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[1])); + LUT4 #( + .INIT(16'h0E00)) + \txeq_preset[2]_i_1 + (.I0(txeq_preset_reg2[2]), + .I1(txeq_preset_reg2[0]), + .I2(RST_CPLLRESET), + .I3(txeq_preset_reg2[3]), + .O(p_0_out[2])); + LUT5 #( + .INIT(32'h01440140)) + \txeq_preset[3]_i_1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[2]), + .I2(txeq_preset_reg2[1]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[0]), + .O(\txeq_preset[3]_i_1_n_0 )); + LUT5 #( + .INIT(32'h00001400)) + \txeq_preset[7]_i_1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[0]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[1]), + .I4(txeq_preset_reg2[3]), + .O(\txeq_preset[7]_i_1_n_0 )); + LUT5 #( + .INIT(32'hAAAFBEAF)) + \txeq_preset[8]_i_1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[0]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[1]), + .I4(txeq_preset_reg2[3]), + .O(p_0_out[8])); + LUT5 #( + .INIT(32'hCCFCCFCD)) + \txeq_preset[9]_i_1 + (.I0(txeq_preset_reg2[1]), + .I1(RST_CPLLRESET), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[9])); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT3 #( + .INIT(8'h04)) + txeq_preset_done_i_1 + (.I0(fsm_tx[2]), + .I1(fsm_tx[1]), + .I2(fsm_tx[0]), + .O(txeq_preset_done_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + txeq_preset_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_done_i_1_n_0), + .Q(txeq_preset_done), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[0]), + .Q(txeq_preset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[1]), + .Q(txeq_preset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[2]), + .Q(txeq_preset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[3]), + .Q(txeq_preset_reg2[3]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[0] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(p_0_out[0]), + .Q(\txeq_preset_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[10] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(p_0_out[10]), + .Q(\txeq_preset_reg_n_0_[10] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[11] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(p_0_out[11]), + .Q(\txeq_preset_reg_n_0_[11] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[12] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(p_0_out[12]), + .Q(\txeq_preset_reg_n_0_[12] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[13] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(p_0_out[13]), + .Q(\txeq_preset_reg_n_0_[13] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[14] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(p_0_out[14]), + .Q(\txeq_preset_reg_n_0_[14] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[15] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(p_0_out[15]), + .Q(\txeq_preset_reg_n_0_[15] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[16] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(p_0_out[16]), + .Q(\txeq_preset_reg_n_0_[16] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[17] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(p_0_out[17]), + .Q(\txeq_preset_reg_n_0_[17] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[1] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(p_0_out[1]), + .Q(\txeq_preset_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[2] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(p_0_out[2]), + .Q(\txeq_preset_reg_n_0_[2] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[3] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(\txeq_preset[3]_i_1_n_0 ), + .Q(\txeq_preset_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[7] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(\txeq_preset[7]_i_1_n_0 ), + .Q(\txeq_preset_reg_n_0_[7] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[8] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(p_0_out[8]), + .Q(\txeq_preset_reg_n_0_[8] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[9] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1_n_0 ), + .D(p_0_out[9]), + .Q(\txeq_preset_reg_n_0_[9] ), + .R(1'b0)); + LUT5 #( + .INIT(32'h45404040)) + \txeq_txcoeff[0]_i_1 + (.I0(fsm_tx[2]), + .I1(\txeq_txcoeff[0]_i_2_n_0 ), + .I2(fsm_tx[1]), + .I3(fsm_tx[0]), + .I4(\txeq_txcoeff_reg_n_0_[6] ), + .O(\txeq_txcoeff[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[0]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[6] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[7] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[0] ), + .O(\txeq_txcoeff[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[10]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[9] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[10]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[16] ), + .O(\txeq_txcoeff[10]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[10]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[16] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[17] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[10] ), + .O(\txeq_txcoeff[10]_i_2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[11]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[10] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[11]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[17] ), + .O(\txeq_txcoeff[11]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[11]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[17] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[18] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[11] ), + .O(\txeq_txcoeff[11]_i_2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[12]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[11] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[12]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[18] ), + .O(\txeq_txcoeff[12]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[12]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[18] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[0]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[12] ), + .O(\txeq_txcoeff[12]_i_2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[13]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[12] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[13]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[0]), + .O(\txeq_txcoeff[13]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[13]_i_2 + (.I0(txeq_deemph_reg2[0]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[1]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[13] ), + .O(\txeq_txcoeff[13]_i_2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[14]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[13] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[14]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[1]), + .O(\txeq_txcoeff[14]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[14]_i_2 + (.I0(txeq_deemph_reg2[1]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[2]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[14] ), + .O(\txeq_txcoeff[14]_i_2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[15]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[14] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[15]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[2]), + .O(\txeq_txcoeff[15]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[15]_i_2 + (.I0(txeq_deemph_reg2[2]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[3]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[15] ), + .O(\txeq_txcoeff[15]_i_2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[16]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[15] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[16]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[3]), + .O(\txeq_txcoeff[16]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[16]_i_2 + (.I0(txeq_deemph_reg2[3]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[4]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[16] ), + .O(\txeq_txcoeff[16]_i_2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[17]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[16] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[17]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[4]), + .O(\txeq_txcoeff[17]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[17]_i_2 + (.I0(txeq_deemph_reg2[4]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[5]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[17] ), + .O(\txeq_txcoeff[17]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFF040FFF)) + \txeq_txcoeff[18]_i_1 + (.I0(txeq_control_reg2[0]), + .I1(txeq_control_reg2[1]), + .I2(fsm_tx[2]), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .O(txeq_txcoeff)); + LUT6 #( + .INIT(64'h22F3220022002200)) + \txeq_txcoeff[18]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[17] ), + .I1(fsm_tx[1]), + .I2(\txeq_txcoeff[18]_i_3_n_0 ), + .I3(fsm_tx[2]), + .I4(txeq_deemph_reg2[5]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[18]_i_2_n_0 )); + LUT2 #( + .INIT(4'hB)) + \txeq_txcoeff[18]_i_3 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .O(\txeq_txcoeff[18]_i_3_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[1]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[0] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[1]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[7] ), + .O(\txeq_txcoeff[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[1]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[7] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[8] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[1] ), + .O(\txeq_txcoeff[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[2]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[1] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[2]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[8] ), + .O(\txeq_txcoeff[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[2]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[8] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[9] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[2] ), + .O(\txeq_txcoeff[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[3]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[2] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[3]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[9] ), + .O(\txeq_txcoeff[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[3]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[9] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[10] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[3] ), + .O(\txeq_txcoeff[3]_i_2_n_0 )); + LUT4 #( + .INIT(16'h2F20)) + \txeq_txcoeff[4]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[3] ), + .I1(fsm_tx[1]), + .I2(fsm_tx[2]), + .I3(\txeq_txcoeff[4]_i_2_n_0 ), + .O(\txeq_txcoeff[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hCACCCCCC00000000)) + \txeq_txcoeff[4]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[11] ), + .I1(\txeq_txcoeff_reg_n_0_[10] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I4(fsm_tx[1]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[4]_i_2_n_0 )); + LUT4 #( + .INIT(16'h2F20)) + \txeq_txcoeff[5]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[4] ), + .I1(fsm_tx[1]), + .I2(fsm_tx[2]), + .I3(\txeq_txcoeff[5]_i_2_n_0 ), + .O(\txeq_txcoeff[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hCACCCCCC00000000)) + \txeq_txcoeff[5]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[12] ), + .I1(\txeq_txcoeff_reg_n_0_[11] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I4(fsm_tx[1]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[5]_i_2_n_0 )); + LUT4 #( + .INIT(16'h2F20)) + \txeq_txcoeff[6]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[5] ), + .I1(fsm_tx[1]), + .I2(fsm_tx[2]), + .I3(\txeq_txcoeff[6]_i_2_n_0 ), + .O(\txeq_txcoeff[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'hCACCCCCC00000000)) + \txeq_txcoeff[6]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[13] ), + .I1(\txeq_txcoeff_reg_n_0_[12] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I4(fsm_tx[1]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[7]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[6] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[7]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[13] ), + .O(\txeq_txcoeff[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[7]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[13] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[14] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[7] ), + .O(\txeq_txcoeff[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[8]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[7] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[8]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[14] ), + .O(\txeq_txcoeff[8]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[8]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[14] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[15] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[8] ), + .O(\txeq_txcoeff[8]_i_2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[9]_i_1 + (.I0(\txeq_txcoeff_reg_n_0_[8] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[9]_i_2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[15] ), + .O(\txeq_txcoeff[9]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[9]_i_2 + (.I0(\txeq_txcoeff_reg_n_0_[15] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[16] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[9] ), + .O(\txeq_txcoeff[9]_i_2_n_0 )); + LUT6 #( + .INIT(64'h000004000F000400)) + \txeq_txcoeff_cnt[0]_i_1 + (.I0(txeq_control_reg2[0]), + .I1(txeq_control_reg2[1]), + .I2(fsm_tx[2]), + .I3(fsm_tx[0]), + .I4(fsm_tx[1]), + .I5(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .O(txeq_txcoeff_cnt[0])); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT5 #( + .INIT(32'h00006000)) + \txeq_txcoeff_cnt[1]_i_1 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I2(fsm_tx[0]), + .I3(fsm_tx[1]), + .I4(fsm_tx[2]), + .O(txeq_txcoeff_cnt[1])); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_txcoeff_cnt[0]), + .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_txcoeff_cnt[1]), + .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[0] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[0]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[10] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[10]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[10] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[11] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[11]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[11] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[12] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[12]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[12] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[13] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[13]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[13] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[14] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[14]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[14] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[15] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[15]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[15] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[16] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[16]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[16] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[17] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[17]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[17] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[18] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[18]_i_2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[18] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[1] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[1]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[2] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[2]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[3] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[3]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[4] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[4]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[5] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[5]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[6] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[6]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[7] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[7]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[7] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[8] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[8]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[8] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[9] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[9]_i_1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[9] ), + .R(RST_CPLLRESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_eq" *) +module pcie_7x_0_pcie_7x_0_pipe_eq_39 + (TXPRECURSOR, + TXMAINCURSOR, + TXPOSTCURSOR, + USER_RXEQ_ADAPT_DONE, + RST_CPLLRESET, + pipe_pclk_in, + rate_gen3_1); + output [4:0]TXPRECURSOR; + output [6:0]TXMAINCURSOR; + output [4:0]TXPOSTCURSOR; + output USER_RXEQ_ADAPT_DONE; + input RST_CPLLRESET; + input pipe_pclk_in; + input rate_gen3_1; + + wire \FSM_onehot_fsm_rx[1]_i_1__0_n_0 ; + wire \FSM_onehot_fsm_rx[1]_i_2__0_n_0 ; + wire \FSM_onehot_fsm_rx[3]_i_1__0_n_0 ; + wire \FSM_onehot_fsm_rx[4]_i_1__0_n_0 ; + wire \FSM_onehot_fsm_rx_reg_n_0_[1] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[2] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[3] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[4] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[5] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[6] ; + wire \FSM_sequential_fsm_tx[1]_i_2__0_n_0 ; + wire \FSM_sequential_fsm_tx[2]_i_2__0_n_0 ; + wire RST_CPLLRESET; + wire [6:0]TXMAINCURSOR; + wire [4:0]TXPOSTCURSOR; + wire [4:0]TXPRECURSOR; + wire USER_RXEQ_ADAPT_DONE; + wire [2:0]fsm_tx; + wire [2:0]fsm_tx__0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2; + wire [17:0]p_0_out; + wire pipe_pclk_in; + wire rate_gen3_1; + wire rxeq_adapt_done_i_2__0_n_0; + wire rxeq_adapt_done_reg_i_2__0_n_0; + wire rxeq_adapt_done_reg_reg_n_0; + wire [2:0]rxeq_cnt; + wire \rxeq_cnt_reg_n_0_[0] ; + wire \rxeq_cnt_reg_n_0_[1] ; + wire \rxeq_cnt_reg_n_0_[2] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxeq_control_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxeq_control_reg2; + wire [5:0]rxeq_fs; + wire \rxeq_fs[5]_i_1__0_n_0 ; + wire \rxeq_fs_reg_n_0_[0] ; + wire \rxeq_fs_reg_n_0_[1] ; + wire \rxeq_fs_reg_n_0_[2] ; + wire \rxeq_fs_reg_n_0_[3] ; + wire \rxeq_fs_reg_n_0_[4] ; + wire \rxeq_fs_reg_n_0_[5] ; + wire [5:0]rxeq_lf; + wire \rxeq_lf[5]_i_1__0_n_0 ; + wire \rxeq_lf_reg_n_0_[0] ; + wire \rxeq_lf_reg_n_0_[1] ; + wire \rxeq_lf_reg_n_0_[2] ; + wire \rxeq_lf_reg_n_0_[3] ; + wire \rxeq_lf_reg_n_0_[4] ; + wire \rxeq_lf_reg_n_0_[5] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]rxeq_lffs_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]rxeq_lffs_reg2; + wire rxeq_new_txcoeff_req; + wire rxeq_new_txcoeff_req_reg_n_0; + wire \rxeq_preset[0]_i_1__0_n_0 ; + wire \rxeq_preset[1]_i_1__0_n_0 ; + wire \rxeq_preset[2]_i_1__0_n_0 ; + wire \rxeq_preset[2]_i_2__0_n_0 ; + wire \rxeq_preset[2]_i_3__0_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]rxeq_preset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]rxeq_preset_reg2; + wire \rxeq_preset_reg_n_0_[0] ; + wire \rxeq_preset_reg_n_0_[1] ; + wire \rxeq_preset_reg_n_0_[2] ; + wire rxeq_preset_valid; + wire rxeq_scan_i_n_0; + wire rxeq_scan_i_n_1; + wire rxeq_scan_i_n_2; + wire rxeq_scan_i_n_4; + wire rxeq_scan_i_n_5; + wire [17:0]rxeq_txcoeff; + wire \rxeq_txcoeff_reg_n_0_[0] ; + wire \rxeq_txcoeff_reg_n_0_[10] ; + wire \rxeq_txcoeff_reg_n_0_[11] ; + wire \rxeq_txcoeff_reg_n_0_[12] ; + wire \rxeq_txcoeff_reg_n_0_[13] ; + wire \rxeq_txcoeff_reg_n_0_[14] ; + wire \rxeq_txcoeff_reg_n_0_[15] ; + wire \rxeq_txcoeff_reg_n_0_[16] ; + wire \rxeq_txcoeff_reg_n_0_[17] ; + wire \rxeq_txcoeff_reg_n_0_[1] ; + wire \rxeq_txcoeff_reg_n_0_[2] ; + wire \rxeq_txcoeff_reg_n_0_[3] ; + wire \rxeq_txcoeff_reg_n_0_[4] ; + wire \rxeq_txcoeff_reg_n_0_[5] ; + wire \rxeq_txcoeff_reg_n_0_[6] ; + wire \rxeq_txcoeff_reg_n_0_[7] ; + wire \rxeq_txcoeff_reg_n_0_[8] ; + wire \rxeq_txcoeff_reg_n_0_[9] ; + wire [3:0]rxeq_txpreset; + wire \rxeq_txpreset[3]_i_1__0_n_0 ; + wire \rxeq_txpreset[3]_i_3__0_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxeq_txpreset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxeq_txpreset_reg2; + wire \rxeq_txpreset_reg_n_0_[0] ; + wire \rxeq_txpreset_reg_n_0_[1] ; + wire \rxeq_txpreset_reg_n_0_[2] ; + wire \rxeq_txpreset_reg_n_0_[3] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_en_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_en_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_mode_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_mode_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]rxeq_user_txcoeff_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]rxeq_user_txcoeff_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txeq_control_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txeq_control_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]txeq_deemph_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]txeq_deemph_reg2; + wire \txeq_preset[17]_i_1__0_n_0 ; + wire \txeq_preset[3]_i_1__0_n_0 ; + wire \txeq_preset[7]_i_1__0_n_0 ; + wire txeq_preset_done; + wire txeq_preset_done_i_1__0_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txeq_preset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txeq_preset_reg2; + wire \txeq_preset_reg_n_0_[0] ; + wire \txeq_preset_reg_n_0_[10] ; + wire \txeq_preset_reg_n_0_[11] ; + wire \txeq_preset_reg_n_0_[12] ; + wire \txeq_preset_reg_n_0_[13] ; + wire \txeq_preset_reg_n_0_[14] ; + wire \txeq_preset_reg_n_0_[15] ; + wire \txeq_preset_reg_n_0_[16] ; + wire \txeq_preset_reg_n_0_[17] ; + wire \txeq_preset_reg_n_0_[1] ; + wire \txeq_preset_reg_n_0_[2] ; + wire \txeq_preset_reg_n_0_[3] ; + wire \txeq_preset_reg_n_0_[7] ; + wire \txeq_preset_reg_n_0_[8] ; + wire \txeq_preset_reg_n_0_[9] ; + wire txeq_txcoeff; + wire \txeq_txcoeff[0]_i_1__0_n_0 ; + wire \txeq_txcoeff[0]_i_2__0_n_0 ; + wire \txeq_txcoeff[10]_i_1__0_n_0 ; + wire \txeq_txcoeff[10]_i_2__0_n_0 ; + wire \txeq_txcoeff[11]_i_1__0_n_0 ; + wire \txeq_txcoeff[11]_i_2__0_n_0 ; + wire \txeq_txcoeff[12]_i_1__0_n_0 ; + wire \txeq_txcoeff[12]_i_2__0_n_0 ; + wire \txeq_txcoeff[13]_i_1__0_n_0 ; + wire \txeq_txcoeff[13]_i_2__0_n_0 ; + wire \txeq_txcoeff[14]_i_1__0_n_0 ; + wire \txeq_txcoeff[14]_i_2__0_n_0 ; + wire \txeq_txcoeff[15]_i_1__0_n_0 ; + wire \txeq_txcoeff[15]_i_2__0_n_0 ; + wire \txeq_txcoeff[16]_i_1__0_n_0 ; + wire \txeq_txcoeff[16]_i_2__0_n_0 ; + wire \txeq_txcoeff[17]_i_1__0_n_0 ; + wire \txeq_txcoeff[17]_i_2__0_n_0 ; + wire \txeq_txcoeff[18]_i_2__0_n_0 ; + wire \txeq_txcoeff[18]_i_3__0_n_0 ; + wire \txeq_txcoeff[1]_i_1__0_n_0 ; + wire \txeq_txcoeff[1]_i_2__0_n_0 ; + wire \txeq_txcoeff[2]_i_1__0_n_0 ; + wire \txeq_txcoeff[2]_i_2__0_n_0 ; + wire \txeq_txcoeff[3]_i_1__0_n_0 ; + wire \txeq_txcoeff[3]_i_2__0_n_0 ; + wire \txeq_txcoeff[4]_i_1__0_n_0 ; + wire \txeq_txcoeff[4]_i_2__0_n_0 ; + wire \txeq_txcoeff[5]_i_1__0_n_0 ; + wire \txeq_txcoeff[5]_i_2__0_n_0 ; + wire \txeq_txcoeff[6]_i_1__0_n_0 ; + wire \txeq_txcoeff[6]_i_2__0_n_0 ; + wire \txeq_txcoeff[7]_i_1__0_n_0 ; + wire \txeq_txcoeff[7]_i_2__0_n_0 ; + wire \txeq_txcoeff[8]_i_1__0_n_0 ; + wire \txeq_txcoeff[8]_i_2__0_n_0 ; + wire \txeq_txcoeff[9]_i_1__0_n_0 ; + wire \txeq_txcoeff[9]_i_2__0_n_0 ; + wire [1:0]txeq_txcoeff_cnt; + wire \txeq_txcoeff_cnt_reg_n_0_[0] ; + wire \txeq_txcoeff_cnt_reg_n_0_[1] ; + wire \txeq_txcoeff_reg_n_0_[0] ; + wire \txeq_txcoeff_reg_n_0_[10] ; + wire \txeq_txcoeff_reg_n_0_[11] ; + wire \txeq_txcoeff_reg_n_0_[12] ; + wire \txeq_txcoeff_reg_n_0_[13] ; + wire \txeq_txcoeff_reg_n_0_[14] ; + wire \txeq_txcoeff_reg_n_0_[15] ; + wire \txeq_txcoeff_reg_n_0_[16] ; + wire \txeq_txcoeff_reg_n_0_[17] ; + wire \txeq_txcoeff_reg_n_0_[18] ; + wire \txeq_txcoeff_reg_n_0_[1] ; + wire \txeq_txcoeff_reg_n_0_[2] ; + wire \txeq_txcoeff_reg_n_0_[3] ; + wire \txeq_txcoeff_reg_n_0_[4] ; + wire \txeq_txcoeff_reg_n_0_[5] ; + wire \txeq_txcoeff_reg_n_0_[6] ; + wire \txeq_txcoeff_reg_n_0_[7] ; + wire \txeq_txcoeff_reg_n_0_[8] ; + wire \txeq_txcoeff_reg_n_0_[9] ; + + LUT5 #( + .INIT(32'hABABABAA)) + \FSM_onehot_fsm_rx[1]_i_1__0 + (.I0(\FSM_onehot_fsm_rx[1]_i_2__0_n_0 ), + .I1(rxeq_control_reg2[1]), + .I2(rxeq_control_reg2[0]), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .O(\FSM_onehot_fsm_rx[1]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \FSM_onehot_fsm_rx[1]_i_2__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .O(\FSM_onehot_fsm_rx[1]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFF8FF88888888)) + \FSM_onehot_fsm_rx[3]_i_1__0 + (.I0(rxeq_control_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\rxeq_cnt_reg_n_0_[2] ), + .I3(\rxeq_cnt_reg_n_0_[1] ), + .I4(\rxeq_cnt_reg_n_0_[0] ), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\FSM_onehot_fsm_rx[3]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair102" *) + LUT5 #( + .INIT(32'h2ABA2AAA)) + \FSM_onehot_fsm_rx[4]_i_1__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(\rxeq_cnt_reg_n_0_[2] ), + .I2(\rxeq_cnt_reg_n_0_[1] ), + .I3(\rxeq_cnt_reg_n_0_[0] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\FSM_onehot_fsm_rx[4]_i_1__0_n_0 )); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDSE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx[1]_i_1__0_n_0 ), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_2), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx[3]_i_1__0_n_0 ), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx[4]_i_1__0_n_0 ), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_1), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_0), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hC04FC043C04FF04F)) + \FSM_sequential_fsm_tx[0]_i_1__0 + (.I0(\FSM_sequential_fsm_tx[1]_i_2__0_n_0 ), + .I1(fsm_tx[0]), + .I2(fsm_tx[1]), + .I3(fsm_tx[2]), + .I4(txeq_control_reg2[1]), + .I5(txeq_control_reg2[0]), + .O(fsm_tx__0[0])); + LUT6 #( + .INIT(64'h3F703F7C3F7C0F70)) + \FSM_sequential_fsm_tx[1]_i_1__0 + (.I0(\FSM_sequential_fsm_tx[1]_i_2__0_n_0 ), + .I1(fsm_tx[0]), + .I2(fsm_tx[1]), + .I3(fsm_tx[2]), + .I4(txeq_control_reg2[1]), + .I5(txeq_control_reg2[0]), + .O(fsm_tx__0[1])); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_fsm_tx[1]_i_2__0 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .O(\FSM_sequential_fsm_tx[1]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h3A2A2A227F7F7F77)) + \FSM_sequential_fsm_tx[2]_i_1__0 + (.I0(fsm_tx[2]), + .I1(fsm_tx[1]), + .I2(fsm_tx[0]), + .I3(txeq_control_reg2[1]), + .I4(txeq_control_reg2[0]), + .I5(\FSM_sequential_fsm_tx[2]_i_2__0_n_0 ), + .O(fsm_tx__0[2])); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT5 #( + .INIT(32'hD0FFDFFF)) + \FSM_sequential_fsm_tx[2]_i_2__0 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I2(fsm_tx[0]), + .I3(fsm_tx[1]), + .I4(txeq_preset_done), + .O(\FSM_sequential_fsm_tx[2]_i_2__0_n_0 )); + (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) + FDSE #( + .INIT(1'b0)) + \FSM_sequential_fsm_tx_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm_tx__0[0]), + .Q(fsm_tx[0]), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_fsm_tx_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm_tx__0[1]), + .Q(fsm_tx[1]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_fsm_tx_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm_tx__0[2]), + .Q(fsm_tx[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_gen3_1), + .Q(gen3_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_reg1), + .Q(gen3_reg2), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_22__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[17] ), + .O(TXPOSTCURSOR[4])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_23__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[16] ), + .O(TXPOSTCURSOR[3])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_24__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[15] ), + .O(TXPOSTCURSOR[2])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_25__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[14] ), + .O(TXPOSTCURSOR[1])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_26__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[13] ), + .O(TXPOSTCURSOR[0])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_27__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[4] ), + .O(TXPRECURSOR[4])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_28__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[3] ), + .O(TXPRECURSOR[3])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_29__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[2] ), + .O(TXPRECURSOR[2])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_30__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[1] ), + .O(TXPRECURSOR[1])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_31__0 + (.I0(\txeq_txcoeff_reg_n_0_[0] ), + .I1(gen3_reg2), + .O(TXPRECURSOR[0])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_32__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[12] ), + .O(TXMAINCURSOR[6])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_33__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[11] ), + .O(TXMAINCURSOR[5])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_34__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[10] ), + .O(TXMAINCURSOR[4])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_35__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[9] ), + .O(TXMAINCURSOR[3])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_36__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[8] ), + .O(TXMAINCURSOR[2])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_37__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[7] ), + .O(TXMAINCURSOR[1])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_38__0 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[6] ), + .O(TXMAINCURSOR[0])); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + rxeq_adapt_done_i_2__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .O(rxeq_adapt_done_i_2__0_n_0)); + FDRE #( + .INIT(1'b0)) + rxeq_adapt_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_5), + .Q(USER_RXEQ_ADAPT_DONE), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'h08)) + rxeq_adapt_done_reg_i_2__0 + (.I0(rxeq_control_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(rxeq_control_reg2[1]), + .O(rxeq_adapt_done_reg_i_2__0_n_0)); + FDRE #( + .INIT(1'b0)) + rxeq_adapt_done_reg_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_4), + .Q(rxeq_adapt_done_reg_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h8888FFF8)) + \rxeq_cnt[0]_i_1__0 + (.I0(rxeq_control_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I4(\rxeq_cnt_reg_n_0_[0] ), + .O(rxeq_cnt[0])); + (* SOFT_HLUTNM = "soft_lutpair103" *) + LUT4 #( + .INIT(16'h6660)) + \rxeq_cnt[1]_i_1__0 + (.I0(\rxeq_cnt_reg_n_0_[0] ), + .I1(\rxeq_cnt_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(rxeq_cnt[1])); + (* SOFT_HLUTNM = "soft_lutpair102" *) + LUT5 #( + .INIT(32'h78787800)) + \rxeq_cnt[2]_i_1__0 + (.I0(\rxeq_cnt_reg_n_0_[1] ), + .I1(\rxeq_cnt_reg_n_0_[0] ), + .I2(\rxeq_cnt_reg_n_0_[2] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(rxeq_cnt[2])); + FDRE #( + .INIT(1'b0)) + \rxeq_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_cnt[0]), + .Q(\rxeq_cnt_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_cnt[1]), + .Q(\rxeq_cnt_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_cnt[2]), + .Q(\rxeq_cnt_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_control_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_control_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_control_reg1[0]), + .Q(rxeq_control_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_control_reg1[1]), + .Q(rxeq_control_reg2[1]), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[0]_i_1__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[0]), + .O(rxeq_fs[0])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[1]_i_1__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[1]), + .O(rxeq_fs[1])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[2]_i_1__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[2]), + .O(rxeq_fs[2])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[3]_i_1__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[3]), + .O(rxeq_fs[3])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[4]_i_1__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[4]), + .O(rxeq_fs[4])); + LUT3 #( + .INIT(8'hF8)) + \rxeq_fs[5]_i_1__0 + (.I0(rxeq_control_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx[1]_i_2__0_n_0 ), + .O(\rxeq_fs[5]_i_1__0_n_0 )); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[5]_i_2__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[5]), + .O(rxeq_fs[5])); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__0_n_0 ), + .D(rxeq_fs[0]), + .Q(\rxeq_fs_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__0_n_0 ), + .D(rxeq_fs[1]), + .Q(\rxeq_fs_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__0_n_0 ), + .D(rxeq_fs[2]), + .Q(\rxeq_fs_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__0_n_0 ), + .D(rxeq_fs[3]), + .Q(\rxeq_fs_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[4] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__0_n_0 ), + .D(rxeq_fs[4]), + .Q(\rxeq_fs_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[5] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__0_n_0 ), + .D(rxeq_fs[5]), + .Q(\rxeq_fs_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[0]_i_1__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[0]), + .O(rxeq_lf[0])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[1]_i_1__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[1]), + .O(rxeq_lf[1])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[2]_i_1__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[2]), + .O(rxeq_lf[2])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[3]_i_1__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[3]), + .O(rxeq_lf[3])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[4]_i_1__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[4]), + .O(rxeq_lf[4])); + LUT5 #( + .INIT(32'hEAAAAAAA)) + \rxeq_lf[5]_i_1__0 + (.I0(\FSM_onehot_fsm_rx[1]_i_2__0_n_0 ), + .I1(\rxeq_cnt_reg_n_0_[2] ), + .I2(\rxeq_cnt_reg_n_0_[0] ), + .I3(\rxeq_cnt_reg_n_0_[1] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .O(\rxeq_lf[5]_i_1__0_n_0 )); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[5]_i_2__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[5]), + .O(rxeq_lf[5])); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__0_n_0 ), + .D(rxeq_lf[0]), + .Q(\rxeq_lf_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__0_n_0 ), + .D(rxeq_lf[1]), + .Q(\rxeq_lf_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__0_n_0 ), + .D(rxeq_lf[2]), + .Q(\rxeq_lf_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__0_n_0 ), + .D(rxeq_lf[3]), + .Q(\rxeq_lf_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[4] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__0_n_0 ), + .D(rxeq_lf[4]), + .Q(\rxeq_lf_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[5] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__0_n_0 ), + .D(rxeq_lf[5]), + .Q(\rxeq_lf_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[0]), + .Q(rxeq_lffs_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[1]), + .Q(rxeq_lffs_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[2]), + .Q(rxeq_lffs_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[3]), + .Q(rxeq_lffs_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[4]), + .Q(rxeq_lffs_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[5]), + .Q(rxeq_lffs_reg2[5]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + rxeq_new_txcoeff_req_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_new_txcoeff_req), + .Q(rxeq_new_txcoeff_req_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hA8FFA800)) + \rxeq_preset[0]_i_1__0 + (.I0(rxeq_preset_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(\rxeq_preset[2]_i_2__0_n_0 ), + .I4(\rxeq_preset_reg_n_0_[0] ), + .O(\rxeq_preset[0]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'hA8FFA800)) + \rxeq_preset[1]_i_1__0 + (.I0(rxeq_preset_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(\rxeq_preset[2]_i_2__0_n_0 ), + .I4(\rxeq_preset_reg_n_0_[1] ), + .O(\rxeq_preset[1]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'hA8FFA800)) + \rxeq_preset[2]_i_1__0 + (.I0(rxeq_preset_reg2[2]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(\rxeq_preset[2]_i_2__0_n_0 ), + .I4(\rxeq_preset_reg_n_0_[2] ), + .O(\rxeq_preset[2]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF0002)) + \rxeq_preset[2]_i_2__0 + (.I0(\rxeq_preset[2]_i_3__0_n_0 ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .I4(rxeq_adapt_done_reg_i_2__0_n_0), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .O(\rxeq_preset[2]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair103" *) + LUT2 #( + .INIT(4'h1)) + \rxeq_preset[2]_i_3__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\rxeq_preset[2]_i_3__0_n_0 )); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_preset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_preset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_preset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_reg1[0]), + .Q(rxeq_preset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_reg1[1]), + .Q(rxeq_preset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_reg1[2]), + .Q(rxeq_preset_reg2[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_preset_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxeq_preset[0]_i_1__0_n_0 ), + .Q(\rxeq_preset_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_preset_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxeq_preset[1]_i_1__0_n_0 ), + .Q(\rxeq_preset_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_preset_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxeq_preset[2]_i_1__0_n_0 ), + .Q(\rxeq_preset_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + rxeq_preset_valid_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .Q(rxeq_preset_valid), + .R(RST_CPLLRESET)); + pcie_7x_0_pcie_7x_0_rxeq_scan_57 rxeq_scan_i + (.D({rxeq_scan_i_n_0,rxeq_scan_i_n_1,rxeq_scan_i_n_2}), + .\FSM_onehot_fsm_rx_reg[5] ({\rxeq_cnt_reg_n_0_[2] ,\rxeq_cnt_reg_n_0_[1] ,\rxeq_cnt_reg_n_0_[0] }), + .Q({\FSM_onehot_fsm_rx_reg_n_0_[6] ,\FSM_onehot_fsm_rx_reg_n_0_[5] ,\FSM_onehot_fsm_rx_reg_n_0_[4] ,\FSM_onehot_fsm_rx_reg_n_0_[2] ,\FSM_onehot_fsm_rx_reg_n_0_[1] }), + .RST_CPLLRESET(RST_CPLLRESET), + .USER_RXEQ_ADAPT_DONE(USER_RXEQ_ADAPT_DONE), + .adapt_done_reg_0(rxeq_scan_i_n_4), + .\fs_reg1_reg[5]_0 ({\rxeq_fs_reg_n_0_[5] ,\rxeq_fs_reg_n_0_[4] ,\rxeq_fs_reg_n_0_[3] ,\rxeq_fs_reg_n_0_[2] ,\rxeq_fs_reg_n_0_[1] ,\rxeq_fs_reg_n_0_[0] }), + .\lf_reg1_reg[5]_0 ({\rxeq_lf_reg_n_0_[5] ,\rxeq_lf_reg_n_0_[4] ,\rxeq_lf_reg_n_0_[3] ,\rxeq_lf_reg_n_0_[2] ,\rxeq_lf_reg_n_0_[1] ,\rxeq_lf_reg_n_0_[0] }), + .new_txcoeff_done_reg_0(rxeq_scan_i_n_5), + .new_txcoeff_req_reg1_reg_0(rxeq_new_txcoeff_req_reg_n_0), + .out(rxeq_control_reg2), + .pipe_pclk_in(pipe_pclk_in), + .\preset_reg1_reg[2]_0 ({\rxeq_preset_reg_n_0_[2] ,\rxeq_preset_reg_n_0_[1] ,\rxeq_preset_reg_n_0_[0] }), + .rxeq_adapt_done_reg(rxeq_adapt_done_i_2__0_n_0), + .rxeq_adapt_done_reg_reg(\FSM_onehot_fsm_rx[1]_i_2__0_n_0 ), + .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_i_2__0_n_0), + .rxeq_adapt_done_reg_reg_1(rxeq_adapt_done_reg_reg_n_0), + .rxeq_new_txcoeff_req(rxeq_new_txcoeff_req), + .rxeq_preset_valid(rxeq_preset_valid), + .\txcoeff_reg1_reg[17]_0 ({\rxeq_txcoeff_reg_n_0_[17] ,\rxeq_txcoeff_reg_n_0_[16] ,\rxeq_txcoeff_reg_n_0_[15] ,\rxeq_txcoeff_reg_n_0_[14] ,\rxeq_txcoeff_reg_n_0_[13] ,\rxeq_txcoeff_reg_n_0_[12] ,\rxeq_txcoeff_reg_n_0_[11] ,\rxeq_txcoeff_reg_n_0_[10] ,\rxeq_txcoeff_reg_n_0_[9] ,\rxeq_txcoeff_reg_n_0_[8] ,\rxeq_txcoeff_reg_n_0_[7] ,\rxeq_txcoeff_reg_n_0_[6] ,\rxeq_txcoeff_reg_n_0_[5] ,\rxeq_txcoeff_reg_n_0_[4] ,\rxeq_txcoeff_reg_n_0_[3] ,\rxeq_txcoeff_reg_n_0_[2] ,\rxeq_txcoeff_reg_n_0_[1] ,\rxeq_txcoeff_reg_n_0_[0] }), + .\txpreset_reg1_reg[3]_0 ({\rxeq_txpreset_reg_n_0_[3] ,\rxeq_txpreset_reg_n_0_[2] ,\rxeq_txpreset_reg_n_0_[1] ,\rxeq_txpreset_reg_n_0_[0] })); + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[0]_i_1__0 + (.I0(\rxeq_txcoeff_reg_n_0_[6] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[0])); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[10]_i_1__0 + (.I0(\rxeq_txcoeff_reg_n_0_[16] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[10])); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[11]_i_1__0 + (.I0(\rxeq_txcoeff_reg_n_0_[17] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[11])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[12]_i_1__0 + (.I0(txeq_deemph_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[12])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[13]_i_1__0 + (.I0(txeq_deemph_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[13])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[14]_i_1__0 + (.I0(txeq_deemph_reg2[2]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[14])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[15]_i_1__0 + (.I0(txeq_deemph_reg2[3]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[15])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[16]_i_1__0 + (.I0(txeq_deemph_reg2[4]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[16])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[17]_i_1__0 + (.I0(txeq_deemph_reg2[5]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[17])); + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[1]_i_1__0 + (.I0(\rxeq_txcoeff_reg_n_0_[7] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[1])); + (* SOFT_HLUTNM = "soft_lutpair105" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[2]_i_1__0 + (.I0(\rxeq_txcoeff_reg_n_0_[8] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[2])); + (* SOFT_HLUTNM = "soft_lutpair105" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[3]_i_1__0 + (.I0(\rxeq_txcoeff_reg_n_0_[9] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[3])); + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[4]_i_1__0 + (.I0(\rxeq_txcoeff_reg_n_0_[10] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[4])); + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[5]_i_1__0 + (.I0(\rxeq_txcoeff_reg_n_0_[11] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[5])); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[6]_i_1__0 + (.I0(\rxeq_txcoeff_reg_n_0_[12] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[6])); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[7]_i_1__0 + (.I0(\rxeq_txcoeff_reg_n_0_[13] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[7])); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[8]_i_1__0 + (.I0(\rxeq_txcoeff_reg_n_0_[14] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[8])); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[9]_i_1__0 + (.I0(\rxeq_txcoeff_reg_n_0_[15] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[9])); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[0]), + .Q(\rxeq_txcoeff_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[10] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[10]), + .Q(\rxeq_txcoeff_reg_n_0_[10] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[11] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[11]), + .Q(\rxeq_txcoeff_reg_n_0_[11] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[12] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[12]), + .Q(\rxeq_txcoeff_reg_n_0_[12] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[13] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[13]), + .Q(\rxeq_txcoeff_reg_n_0_[13] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[14] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[14]), + .Q(\rxeq_txcoeff_reg_n_0_[14] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[15] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[15]), + .Q(\rxeq_txcoeff_reg_n_0_[15] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[16] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[16]), + .Q(\rxeq_txcoeff_reg_n_0_[16] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[17] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[17]), + .Q(\rxeq_txcoeff_reg_n_0_[17] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[1]), + .Q(\rxeq_txcoeff_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[2]), + .Q(\rxeq_txcoeff_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[3]), + .Q(\rxeq_txcoeff_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[4] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[4]), + .Q(\rxeq_txcoeff_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[5] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[5]), + .Q(\rxeq_txcoeff_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[6] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[6]), + .Q(\rxeq_txcoeff_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[7] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[7]), + .Q(\rxeq_txcoeff_reg_n_0_[7] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[8] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[8]), + .Q(\rxeq_txcoeff_reg_n_0_[8] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[9] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txcoeff[9]), + .Q(\rxeq_txcoeff_reg_n_0_[9] ), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[0]_i_1__0 + (.I0(rxeq_txpreset_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[0])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[1]_i_1__0 + (.I0(rxeq_txpreset_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[1])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[2]_i_1__0 + (.I0(rxeq_txpreset_reg2[2]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[2])); + LUT5 #( + .INIT(32'hFFFFF404)) + \rxeq_txpreset[3]_i_1__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .I1(\rxeq_txpreset[3]_i_3__0_n_0 ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(rxeq_control_reg2[1]), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\rxeq_txpreset[3]_i_1__0_n_0 )); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[3]_i_2__0 + (.I0(rxeq_txpreset_reg2[3]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[3])); + LUT3 #( + .INIT(8'h01)) + \rxeq_txpreset[3]_i_3__0 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .O(\rxeq_txpreset[3]_i_3__0_n_0 )); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[0]), + .Q(rxeq_txpreset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[1]), + .Q(rxeq_txpreset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[2]), + .Q(rxeq_txpreset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[3]), + .Q(rxeq_txpreset_reg2[3]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txpreset[0]), + .Q(\rxeq_txpreset_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txpreset[1]), + .Q(\rxeq_txpreset_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txpreset[2]), + .Q(\rxeq_txpreset_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__0_n_0 ), + .D(rxeq_txpreset[3]), + .Q(\rxeq_txpreset_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_en_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_en_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_en_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_en_reg1), + .Q(rxeq_user_en_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_mode_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_mode_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_mode_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_mode_reg1), + .Q(rxeq_user_mode_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[0]), + .Q(rxeq_user_txcoeff_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[10]), + .Q(rxeq_user_txcoeff_reg2[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[11]), + .Q(rxeq_user_txcoeff_reg2[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[12]), + .Q(rxeq_user_txcoeff_reg2[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[13]), + .Q(rxeq_user_txcoeff_reg2[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[14]), + .Q(rxeq_user_txcoeff_reg2[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[15]), + .Q(rxeq_user_txcoeff_reg2[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[16]), + .Q(rxeq_user_txcoeff_reg2[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[17]), + .Q(rxeq_user_txcoeff_reg2[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[1]), + .Q(rxeq_user_txcoeff_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[2]), + .Q(rxeq_user_txcoeff_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[3]), + .Q(rxeq_user_txcoeff_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[4]), + .Q(rxeq_user_txcoeff_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[5]), + .Q(rxeq_user_txcoeff_reg2[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[6]), + .Q(rxeq_user_txcoeff_reg2[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[7]), + .Q(rxeq_user_txcoeff_reg2[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[8]), + .Q(rxeq_user_txcoeff_reg2[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[9]), + .Q(rxeq_user_txcoeff_reg2[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_control_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_control_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_control_reg1[0]), + .Q(txeq_control_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_control_reg1[1]), + .Q(txeq_control_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \txeq_deemph_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[0]), + .S(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \txeq_deemph_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[0]), + .Q(txeq_deemph_reg2[0]), + .S(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[1]), + .Q(txeq_deemph_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[2]), + .Q(txeq_deemph_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[3]), + .Q(txeq_deemph_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[4]), + .Q(txeq_deemph_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[5]), + .Q(txeq_deemph_reg2[5]), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h00001000)) + \txeq_preset[0]_i_1__0 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[2]), + .I2(txeq_preset_reg2[0]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[1]), + .O(p_0_out[0])); + LUT5 #( + .INIT(32'hABEAABAF)) + \txeq_preset[10]_i_1__0 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[2]), + .I2(txeq_preset_reg2[0]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[1]), + .O(p_0_out[10])); + LUT5 #( + .INIT(32'hFFFF200D)) + \txeq_preset[11]_i_1__0 + (.I0(txeq_preset_reg2[1]), + .I1(txeq_preset_reg2[3]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[0]), + .I4(RST_CPLLRESET), + .O(p_0_out[11])); + LUT5 #( + .INIT(32'h01151110)) + \txeq_preset[12]_i_1__0 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[3]), + .I2(txeq_preset_reg2[1]), + .I3(txeq_preset_reg2[2]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[12])); + LUT5 #( + .INIT(32'h01000010)) + \txeq_preset[13]_i_1__0 + (.I0(txeq_preset_reg2[2]), + .I1(RST_CPLLRESET), + .I2(txeq_preset_reg2[0]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[1]), + .O(p_0_out[13])); + LUT5 #( + .INIT(32'h01000010)) + \txeq_preset[14]_i_1__0 + (.I0(txeq_preset_reg2[2]), + .I1(RST_CPLLRESET), + .I2(txeq_preset_reg2[3]), + .I3(txeq_preset_reg2[1]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[14])); + LUT4 #( + .INIT(16'hF0F1)) + \txeq_preset[15]_i_1__0 + (.I0(txeq_preset_reg2[2]), + .I1(txeq_preset_reg2[1]), + .I2(RST_CPLLRESET), + .I3(txeq_preset_reg2[3]), + .O(p_0_out[15])); + LUT4 #( + .INIT(16'h0006)) + \txeq_preset[16]_i_1__0 + (.I0(txeq_preset_reg2[3]), + .I1(txeq_preset_reg2[0]), + .I2(txeq_preset_reg2[2]), + .I3(RST_CPLLRESET), + .O(p_0_out[16])); + LUT4 #( + .INIT(16'hAABA)) + \txeq_preset[17]_i_1__0 + (.I0(RST_CPLLRESET), + .I1(fsm_tx[0]), + .I2(fsm_tx[1]), + .I3(fsm_tx[2]), + .O(\txeq_preset[17]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'hFFFF400D)) + \txeq_preset[17]_i_2__0 + (.I0(txeq_preset_reg2[3]), + .I1(txeq_preset_reg2[1]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[0]), + .I4(RST_CPLLRESET), + .O(p_0_out[17])); + LUT5 #( + .INIT(32'h00001004)) + \txeq_preset[1]_i_1__0 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[3]), + .I2(txeq_preset_reg2[1]), + .I3(txeq_preset_reg2[2]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[1])); + LUT4 #( + .INIT(16'h0E00)) + \txeq_preset[2]_i_1__0 + (.I0(txeq_preset_reg2[2]), + .I1(txeq_preset_reg2[0]), + .I2(RST_CPLLRESET), + .I3(txeq_preset_reg2[3]), + .O(p_0_out[2])); + LUT5 #( + .INIT(32'h01440140)) + \txeq_preset[3]_i_1__0 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[2]), + .I2(txeq_preset_reg2[1]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[0]), + .O(\txeq_preset[3]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'h00001400)) + \txeq_preset[7]_i_1__0 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[0]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[1]), + .I4(txeq_preset_reg2[3]), + .O(\txeq_preset[7]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'hAAAFBEAF)) + \txeq_preset[8]_i_1__0 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[0]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[1]), + .I4(txeq_preset_reg2[3]), + .O(p_0_out[8])); + LUT5 #( + .INIT(32'hCCFCCFCD)) + \txeq_preset[9]_i_1__0 + (.I0(txeq_preset_reg2[1]), + .I1(RST_CPLLRESET), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[9])); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT3 #( + .INIT(8'h04)) + txeq_preset_done_i_1__0 + (.I0(fsm_tx[2]), + .I1(fsm_tx[1]), + .I2(fsm_tx[0]), + .O(txeq_preset_done_i_1__0_n_0)); + FDRE #( + .INIT(1'b0)) + txeq_preset_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_done_i_1__0_n_0), + .Q(txeq_preset_done), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[0]), + .Q(txeq_preset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[1]), + .Q(txeq_preset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[2]), + .Q(txeq_preset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[3]), + .Q(txeq_preset_reg2[3]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[0] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(p_0_out[0]), + .Q(\txeq_preset_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[10] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(p_0_out[10]), + .Q(\txeq_preset_reg_n_0_[10] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[11] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(p_0_out[11]), + .Q(\txeq_preset_reg_n_0_[11] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[12] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(p_0_out[12]), + .Q(\txeq_preset_reg_n_0_[12] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[13] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(p_0_out[13]), + .Q(\txeq_preset_reg_n_0_[13] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[14] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(p_0_out[14]), + .Q(\txeq_preset_reg_n_0_[14] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[15] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(p_0_out[15]), + .Q(\txeq_preset_reg_n_0_[15] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[16] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(p_0_out[16]), + .Q(\txeq_preset_reg_n_0_[16] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[17] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(p_0_out[17]), + .Q(\txeq_preset_reg_n_0_[17] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[1] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(p_0_out[1]), + .Q(\txeq_preset_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[2] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(p_0_out[2]), + .Q(\txeq_preset_reg_n_0_[2] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[3] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(\txeq_preset[3]_i_1__0_n_0 ), + .Q(\txeq_preset_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[7] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(\txeq_preset[7]_i_1__0_n_0 ), + .Q(\txeq_preset_reg_n_0_[7] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[8] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(p_0_out[8]), + .Q(\txeq_preset_reg_n_0_[8] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[9] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__0_n_0 ), + .D(p_0_out[9]), + .Q(\txeq_preset_reg_n_0_[9] ), + .R(1'b0)); + LUT5 #( + .INIT(32'h45404040)) + \txeq_txcoeff[0]_i_1__0 + (.I0(fsm_tx[2]), + .I1(\txeq_txcoeff[0]_i_2__0_n_0 ), + .I2(fsm_tx[1]), + .I3(fsm_tx[0]), + .I4(\txeq_txcoeff_reg_n_0_[6] ), + .O(\txeq_txcoeff[0]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[0]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[6] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[7] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[0] ), + .O(\txeq_txcoeff[0]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[10]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[9] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[10]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[16] ), + .O(\txeq_txcoeff[10]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[10]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[16] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[17] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[10] ), + .O(\txeq_txcoeff[10]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[11]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[10] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[11]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[17] ), + .O(\txeq_txcoeff[11]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[11]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[17] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[18] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[11] ), + .O(\txeq_txcoeff[11]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[12]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[11] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[12]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[18] ), + .O(\txeq_txcoeff[12]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[12]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[18] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[0]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[12] ), + .O(\txeq_txcoeff[12]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[13]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[12] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[13]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[0]), + .O(\txeq_txcoeff[13]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[13]_i_2__0 + (.I0(txeq_deemph_reg2[0]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[1]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[13] ), + .O(\txeq_txcoeff[13]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[14]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[13] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[14]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[1]), + .O(\txeq_txcoeff[14]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[14]_i_2__0 + (.I0(txeq_deemph_reg2[1]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[2]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[14] ), + .O(\txeq_txcoeff[14]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[15]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[14] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[15]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[2]), + .O(\txeq_txcoeff[15]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[15]_i_2__0 + (.I0(txeq_deemph_reg2[2]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[3]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[15] ), + .O(\txeq_txcoeff[15]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[16]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[15] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[16]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[3]), + .O(\txeq_txcoeff[16]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[16]_i_2__0 + (.I0(txeq_deemph_reg2[3]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[4]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[16] ), + .O(\txeq_txcoeff[16]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[17]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[16] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[17]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[4]), + .O(\txeq_txcoeff[17]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[17]_i_2__0 + (.I0(txeq_deemph_reg2[4]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[5]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[17] ), + .O(\txeq_txcoeff[17]_i_2__0_n_0 )); + LUT5 #( + .INIT(32'hFF040FFF)) + \txeq_txcoeff[18]_i_1__0 + (.I0(txeq_control_reg2[0]), + .I1(txeq_control_reg2[1]), + .I2(fsm_tx[2]), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .O(txeq_txcoeff)); + LUT6 #( + .INIT(64'h22F3220022002200)) + \txeq_txcoeff[18]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[17] ), + .I1(fsm_tx[1]), + .I2(\txeq_txcoeff[18]_i_3__0_n_0 ), + .I3(fsm_tx[2]), + .I4(txeq_deemph_reg2[5]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[18]_i_2__0_n_0 )); + LUT2 #( + .INIT(4'hB)) + \txeq_txcoeff[18]_i_3__0 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .O(\txeq_txcoeff[18]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[1]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[0] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[1]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[7] ), + .O(\txeq_txcoeff[1]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[1]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[7] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[8] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[1] ), + .O(\txeq_txcoeff[1]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[2]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[1] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[2]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[8] ), + .O(\txeq_txcoeff[2]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[2]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[8] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[9] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[2] ), + .O(\txeq_txcoeff[2]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[3]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[2] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[3]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[9] ), + .O(\txeq_txcoeff[3]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[3]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[9] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[10] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[3] ), + .O(\txeq_txcoeff[3]_i_2__0_n_0 )); + LUT4 #( + .INIT(16'h2F20)) + \txeq_txcoeff[4]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[3] ), + .I1(fsm_tx[1]), + .I2(fsm_tx[2]), + .I3(\txeq_txcoeff[4]_i_2__0_n_0 ), + .O(\txeq_txcoeff[4]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hCACCCCCC00000000)) + \txeq_txcoeff[4]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[11] ), + .I1(\txeq_txcoeff_reg_n_0_[10] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I4(fsm_tx[1]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[4]_i_2__0_n_0 )); + LUT4 #( + .INIT(16'h2F20)) + \txeq_txcoeff[5]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[4] ), + .I1(fsm_tx[1]), + .I2(fsm_tx[2]), + .I3(\txeq_txcoeff[5]_i_2__0_n_0 ), + .O(\txeq_txcoeff[5]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hCACCCCCC00000000)) + \txeq_txcoeff[5]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[12] ), + .I1(\txeq_txcoeff_reg_n_0_[11] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I4(fsm_tx[1]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[5]_i_2__0_n_0 )); + LUT4 #( + .INIT(16'h2F20)) + \txeq_txcoeff[6]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[5] ), + .I1(fsm_tx[1]), + .I2(fsm_tx[2]), + .I3(\txeq_txcoeff[6]_i_2__0_n_0 ), + .O(\txeq_txcoeff[6]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hCACCCCCC00000000)) + \txeq_txcoeff[6]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[13] ), + .I1(\txeq_txcoeff_reg_n_0_[12] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I4(fsm_tx[1]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[6]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[7]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[6] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[7]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[13] ), + .O(\txeq_txcoeff[7]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[7]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[13] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[14] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[7] ), + .O(\txeq_txcoeff[7]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[8]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[7] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[8]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[14] ), + .O(\txeq_txcoeff[8]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[8]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[14] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[15] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[8] ), + .O(\txeq_txcoeff[8]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[9]_i_1__0 + (.I0(\txeq_txcoeff_reg_n_0_[8] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[9]_i_2__0_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[15] ), + .O(\txeq_txcoeff[9]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[9]_i_2__0 + (.I0(\txeq_txcoeff_reg_n_0_[15] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[16] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[9] ), + .O(\txeq_txcoeff[9]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h000004000F000400)) + \txeq_txcoeff_cnt[0]_i_1__0 + (.I0(txeq_control_reg2[0]), + .I1(txeq_control_reg2[1]), + .I2(fsm_tx[2]), + .I3(fsm_tx[0]), + .I4(fsm_tx[1]), + .I5(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .O(txeq_txcoeff_cnt[0])); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT5 #( + .INIT(32'h00006000)) + \txeq_txcoeff_cnt[1]_i_1__0 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I2(fsm_tx[0]), + .I3(fsm_tx[1]), + .I4(fsm_tx[2]), + .O(txeq_txcoeff_cnt[1])); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_txcoeff_cnt[0]), + .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_txcoeff_cnt[1]), + .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[0] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[0]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[10] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[10]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[10] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[11] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[11]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[11] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[12] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[12]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[12] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[13] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[13]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[13] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[14] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[14]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[14] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[15] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[15]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[15] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[16] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[16]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[16] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[17] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[17]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[17] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[18] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[18]_i_2__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[18] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[1] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[1]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[2] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[2]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[3] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[3]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[4] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[4]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[5] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[5]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[6] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[6]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[7] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[7]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[7] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[8] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[8]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[8] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[9] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[9]_i_1__0_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[9] ), + .R(RST_CPLLRESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_eq" *) +module pcie_7x_0_pcie_7x_0_pipe_eq_45 + (TXPRECURSOR, + TXMAINCURSOR, + TXPOSTCURSOR, + USER_RXEQ_ADAPT_DONE, + RST_CPLLRESET, + pipe_pclk_in, + rate_gen3_2); + output [4:0]TXPRECURSOR; + output [6:0]TXMAINCURSOR; + output [4:0]TXPOSTCURSOR; + output USER_RXEQ_ADAPT_DONE; + input RST_CPLLRESET; + input pipe_pclk_in; + input rate_gen3_2; + + wire \FSM_onehot_fsm_rx[1]_i_1__1_n_0 ; + wire \FSM_onehot_fsm_rx[1]_i_2__1_n_0 ; + wire \FSM_onehot_fsm_rx[3]_i_1__1_n_0 ; + wire \FSM_onehot_fsm_rx[4]_i_1__1_n_0 ; + wire \FSM_onehot_fsm_rx_reg_n_0_[1] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[2] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[3] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[4] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[5] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[6] ; + wire \FSM_sequential_fsm_tx[1]_i_2__1_n_0 ; + wire \FSM_sequential_fsm_tx[2]_i_2__1_n_0 ; + wire RST_CPLLRESET; + wire [6:0]TXMAINCURSOR; + wire [4:0]TXPOSTCURSOR; + wire [4:0]TXPRECURSOR; + wire USER_RXEQ_ADAPT_DONE; + wire [2:0]fsm_tx; + wire [2:0]fsm_tx__0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2; + wire [17:0]p_0_out; + wire pipe_pclk_in; + wire rate_gen3_2; + wire rxeq_adapt_done_i_2__1_n_0; + wire rxeq_adapt_done_reg_i_2__1_n_0; + wire rxeq_adapt_done_reg_reg_n_0; + wire [2:0]rxeq_cnt; + wire \rxeq_cnt_reg_n_0_[0] ; + wire \rxeq_cnt_reg_n_0_[1] ; + wire \rxeq_cnt_reg_n_0_[2] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxeq_control_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxeq_control_reg2; + wire [5:0]rxeq_fs; + wire \rxeq_fs[5]_i_1__1_n_0 ; + wire \rxeq_fs_reg_n_0_[0] ; + wire \rxeq_fs_reg_n_0_[1] ; + wire \rxeq_fs_reg_n_0_[2] ; + wire \rxeq_fs_reg_n_0_[3] ; + wire \rxeq_fs_reg_n_0_[4] ; + wire \rxeq_fs_reg_n_0_[5] ; + wire [5:0]rxeq_lf; + wire \rxeq_lf[5]_i_1__1_n_0 ; + wire \rxeq_lf_reg_n_0_[0] ; + wire \rxeq_lf_reg_n_0_[1] ; + wire \rxeq_lf_reg_n_0_[2] ; + wire \rxeq_lf_reg_n_0_[3] ; + wire \rxeq_lf_reg_n_0_[4] ; + wire \rxeq_lf_reg_n_0_[5] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]rxeq_lffs_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]rxeq_lffs_reg2; + wire rxeq_new_txcoeff_req; + wire rxeq_new_txcoeff_req_reg_n_0; + wire \rxeq_preset[0]_i_1__1_n_0 ; + wire \rxeq_preset[1]_i_1__1_n_0 ; + wire \rxeq_preset[2]_i_1__1_n_0 ; + wire \rxeq_preset[2]_i_2__1_n_0 ; + wire \rxeq_preset[2]_i_3__1_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]rxeq_preset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]rxeq_preset_reg2; + wire \rxeq_preset_reg_n_0_[0] ; + wire \rxeq_preset_reg_n_0_[1] ; + wire \rxeq_preset_reg_n_0_[2] ; + wire rxeq_preset_valid; + wire rxeq_scan_i_n_0; + wire rxeq_scan_i_n_1; + wire rxeq_scan_i_n_2; + wire rxeq_scan_i_n_4; + wire rxeq_scan_i_n_5; + wire [17:0]rxeq_txcoeff; + wire \rxeq_txcoeff_reg_n_0_[0] ; + wire \rxeq_txcoeff_reg_n_0_[10] ; + wire \rxeq_txcoeff_reg_n_0_[11] ; + wire \rxeq_txcoeff_reg_n_0_[12] ; + wire \rxeq_txcoeff_reg_n_0_[13] ; + wire \rxeq_txcoeff_reg_n_0_[14] ; + wire \rxeq_txcoeff_reg_n_0_[15] ; + wire \rxeq_txcoeff_reg_n_0_[16] ; + wire \rxeq_txcoeff_reg_n_0_[17] ; + wire \rxeq_txcoeff_reg_n_0_[1] ; + wire \rxeq_txcoeff_reg_n_0_[2] ; + wire \rxeq_txcoeff_reg_n_0_[3] ; + wire \rxeq_txcoeff_reg_n_0_[4] ; + wire \rxeq_txcoeff_reg_n_0_[5] ; + wire \rxeq_txcoeff_reg_n_0_[6] ; + wire \rxeq_txcoeff_reg_n_0_[7] ; + wire \rxeq_txcoeff_reg_n_0_[8] ; + wire \rxeq_txcoeff_reg_n_0_[9] ; + wire [3:0]rxeq_txpreset; + wire \rxeq_txpreset[3]_i_1__1_n_0 ; + wire \rxeq_txpreset[3]_i_3__1_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxeq_txpreset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxeq_txpreset_reg2; + wire \rxeq_txpreset_reg_n_0_[0] ; + wire \rxeq_txpreset_reg_n_0_[1] ; + wire \rxeq_txpreset_reg_n_0_[2] ; + wire \rxeq_txpreset_reg_n_0_[3] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_en_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_en_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_mode_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_mode_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]rxeq_user_txcoeff_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]rxeq_user_txcoeff_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txeq_control_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txeq_control_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]txeq_deemph_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]txeq_deemph_reg2; + wire \txeq_preset[17]_i_1__1_n_0 ; + wire \txeq_preset[3]_i_1__1_n_0 ; + wire \txeq_preset[7]_i_1__1_n_0 ; + wire txeq_preset_done; + wire txeq_preset_done_i_1__1_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txeq_preset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txeq_preset_reg2; + wire \txeq_preset_reg_n_0_[0] ; + wire \txeq_preset_reg_n_0_[10] ; + wire \txeq_preset_reg_n_0_[11] ; + wire \txeq_preset_reg_n_0_[12] ; + wire \txeq_preset_reg_n_0_[13] ; + wire \txeq_preset_reg_n_0_[14] ; + wire \txeq_preset_reg_n_0_[15] ; + wire \txeq_preset_reg_n_0_[16] ; + wire \txeq_preset_reg_n_0_[17] ; + wire \txeq_preset_reg_n_0_[1] ; + wire \txeq_preset_reg_n_0_[2] ; + wire \txeq_preset_reg_n_0_[3] ; + wire \txeq_preset_reg_n_0_[7] ; + wire \txeq_preset_reg_n_0_[8] ; + wire \txeq_preset_reg_n_0_[9] ; + wire txeq_txcoeff; + wire \txeq_txcoeff[0]_i_1__1_n_0 ; + wire \txeq_txcoeff[0]_i_2__1_n_0 ; + wire \txeq_txcoeff[10]_i_1__1_n_0 ; + wire \txeq_txcoeff[10]_i_2__1_n_0 ; + wire \txeq_txcoeff[11]_i_1__1_n_0 ; + wire \txeq_txcoeff[11]_i_2__1_n_0 ; + wire \txeq_txcoeff[12]_i_1__1_n_0 ; + wire \txeq_txcoeff[12]_i_2__1_n_0 ; + wire \txeq_txcoeff[13]_i_1__1_n_0 ; + wire \txeq_txcoeff[13]_i_2__1_n_0 ; + wire \txeq_txcoeff[14]_i_1__1_n_0 ; + wire \txeq_txcoeff[14]_i_2__1_n_0 ; + wire \txeq_txcoeff[15]_i_1__1_n_0 ; + wire \txeq_txcoeff[15]_i_2__1_n_0 ; + wire \txeq_txcoeff[16]_i_1__1_n_0 ; + wire \txeq_txcoeff[16]_i_2__1_n_0 ; + wire \txeq_txcoeff[17]_i_1__1_n_0 ; + wire \txeq_txcoeff[17]_i_2__1_n_0 ; + wire \txeq_txcoeff[18]_i_2__1_n_0 ; + wire \txeq_txcoeff[18]_i_3__1_n_0 ; + wire \txeq_txcoeff[1]_i_1__1_n_0 ; + wire \txeq_txcoeff[1]_i_2__1_n_0 ; + wire \txeq_txcoeff[2]_i_1__1_n_0 ; + wire \txeq_txcoeff[2]_i_2__1_n_0 ; + wire \txeq_txcoeff[3]_i_1__1_n_0 ; + wire \txeq_txcoeff[3]_i_2__1_n_0 ; + wire \txeq_txcoeff[4]_i_1__1_n_0 ; + wire \txeq_txcoeff[4]_i_2__1_n_0 ; + wire \txeq_txcoeff[5]_i_1__1_n_0 ; + wire \txeq_txcoeff[5]_i_2__1_n_0 ; + wire \txeq_txcoeff[6]_i_1__1_n_0 ; + wire \txeq_txcoeff[6]_i_2__1_n_0 ; + wire \txeq_txcoeff[7]_i_1__1_n_0 ; + wire \txeq_txcoeff[7]_i_2__1_n_0 ; + wire \txeq_txcoeff[8]_i_1__1_n_0 ; + wire \txeq_txcoeff[8]_i_2__1_n_0 ; + wire \txeq_txcoeff[9]_i_1__1_n_0 ; + wire \txeq_txcoeff[9]_i_2__1_n_0 ; + wire [1:0]txeq_txcoeff_cnt; + wire \txeq_txcoeff_cnt_reg_n_0_[0] ; + wire \txeq_txcoeff_cnt_reg_n_0_[1] ; + wire \txeq_txcoeff_reg_n_0_[0] ; + wire \txeq_txcoeff_reg_n_0_[10] ; + wire \txeq_txcoeff_reg_n_0_[11] ; + wire \txeq_txcoeff_reg_n_0_[12] ; + wire \txeq_txcoeff_reg_n_0_[13] ; + wire \txeq_txcoeff_reg_n_0_[14] ; + wire \txeq_txcoeff_reg_n_0_[15] ; + wire \txeq_txcoeff_reg_n_0_[16] ; + wire \txeq_txcoeff_reg_n_0_[17] ; + wire \txeq_txcoeff_reg_n_0_[18] ; + wire \txeq_txcoeff_reg_n_0_[1] ; + wire \txeq_txcoeff_reg_n_0_[2] ; + wire \txeq_txcoeff_reg_n_0_[3] ; + wire \txeq_txcoeff_reg_n_0_[4] ; + wire \txeq_txcoeff_reg_n_0_[5] ; + wire \txeq_txcoeff_reg_n_0_[6] ; + wire \txeq_txcoeff_reg_n_0_[7] ; + wire \txeq_txcoeff_reg_n_0_[8] ; + wire \txeq_txcoeff_reg_n_0_[9] ; + + LUT5 #( + .INIT(32'hABABABAA)) + \FSM_onehot_fsm_rx[1]_i_1__1 + (.I0(\FSM_onehot_fsm_rx[1]_i_2__1_n_0 ), + .I1(rxeq_control_reg2[1]), + .I2(rxeq_control_reg2[0]), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .O(\FSM_onehot_fsm_rx[1]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \FSM_onehot_fsm_rx[1]_i_2__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .O(\FSM_onehot_fsm_rx[1]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFF8FF88888888)) + \FSM_onehot_fsm_rx[3]_i_1__1 + (.I0(rxeq_control_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\rxeq_cnt_reg_n_0_[2] ), + .I3(\rxeq_cnt_reg_n_0_[1] ), + .I4(\rxeq_cnt_reg_n_0_[0] ), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\FSM_onehot_fsm_rx[3]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair144" *) + LUT5 #( + .INIT(32'h2ABA2AAA)) + \FSM_onehot_fsm_rx[4]_i_1__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(\rxeq_cnt_reg_n_0_[2] ), + .I2(\rxeq_cnt_reg_n_0_[1] ), + .I3(\rxeq_cnt_reg_n_0_[0] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\FSM_onehot_fsm_rx[4]_i_1__1_n_0 )); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDSE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx[1]_i_1__1_n_0 ), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_2), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx[3]_i_1__1_n_0 ), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx[4]_i_1__1_n_0 ), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_1), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_0), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hC04FC043C04FF04F)) + \FSM_sequential_fsm_tx[0]_i_1__1 + (.I0(\FSM_sequential_fsm_tx[1]_i_2__1_n_0 ), + .I1(fsm_tx[0]), + .I2(fsm_tx[1]), + .I3(fsm_tx[2]), + .I4(txeq_control_reg2[1]), + .I5(txeq_control_reg2[0]), + .O(fsm_tx__0[0])); + LUT6 #( + .INIT(64'h3F703F7C3F7C0F70)) + \FSM_sequential_fsm_tx[1]_i_1__1 + (.I0(\FSM_sequential_fsm_tx[1]_i_2__1_n_0 ), + .I1(fsm_tx[0]), + .I2(fsm_tx[1]), + .I3(fsm_tx[2]), + .I4(txeq_control_reg2[1]), + .I5(txeq_control_reg2[0]), + .O(fsm_tx__0[1])); + (* SOFT_HLUTNM = "soft_lutpair142" *) + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_fsm_tx[1]_i_2__1 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .O(\FSM_sequential_fsm_tx[1]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h3A2A2A227F7F7F77)) + \FSM_sequential_fsm_tx[2]_i_1__1 + (.I0(fsm_tx[2]), + .I1(fsm_tx[1]), + .I2(fsm_tx[0]), + .I3(txeq_control_reg2[1]), + .I4(txeq_control_reg2[0]), + .I5(\FSM_sequential_fsm_tx[2]_i_2__1_n_0 ), + .O(fsm_tx__0[2])); + (* SOFT_HLUTNM = "soft_lutpair142" *) + LUT5 #( + .INIT(32'hD0FFDFFF)) + \FSM_sequential_fsm_tx[2]_i_2__1 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I2(fsm_tx[0]), + .I3(fsm_tx[1]), + .I4(txeq_preset_done), + .O(\FSM_sequential_fsm_tx[2]_i_2__1_n_0 )); + (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) + FDSE #( + .INIT(1'b0)) + \FSM_sequential_fsm_tx_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm_tx__0[0]), + .Q(fsm_tx[0]), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_fsm_tx_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm_tx__0[1]), + .Q(fsm_tx[1]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_fsm_tx_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm_tx__0[2]), + .Q(fsm_tx[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_gen3_2), + .Q(gen3_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_reg1), + .Q(gen3_reg2), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_22__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[17] ), + .O(TXPOSTCURSOR[4])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_23__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[16] ), + .O(TXPOSTCURSOR[3])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_24__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[15] ), + .O(TXPOSTCURSOR[2])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_25__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[14] ), + .O(TXPOSTCURSOR[1])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_26__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[13] ), + .O(TXPOSTCURSOR[0])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_27__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[4] ), + .O(TXPRECURSOR[4])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_28__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[3] ), + .O(TXPRECURSOR[3])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_29__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[2] ), + .O(TXPRECURSOR[2])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_30__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[1] ), + .O(TXPRECURSOR[1])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_31__1 + (.I0(\txeq_txcoeff_reg_n_0_[0] ), + .I1(gen3_reg2), + .O(TXPRECURSOR[0])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_32__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[12] ), + .O(TXMAINCURSOR[6])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_33__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[11] ), + .O(TXMAINCURSOR[5])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_34__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[10] ), + .O(TXMAINCURSOR[4])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_35__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[9] ), + .O(TXMAINCURSOR[3])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_36__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[8] ), + .O(TXMAINCURSOR[2])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_37__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[7] ), + .O(TXMAINCURSOR[1])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_38__1 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[6] ), + .O(TXMAINCURSOR[0])); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + rxeq_adapt_done_i_2__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .O(rxeq_adapt_done_i_2__1_n_0)); + FDRE #( + .INIT(1'b0)) + rxeq_adapt_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_5), + .Q(USER_RXEQ_ADAPT_DONE), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'h08)) + rxeq_adapt_done_reg_i_2__1 + (.I0(rxeq_control_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(rxeq_control_reg2[1]), + .O(rxeq_adapt_done_reg_i_2__1_n_0)); + FDRE #( + .INIT(1'b0)) + rxeq_adapt_done_reg_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_4), + .Q(rxeq_adapt_done_reg_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h8888FFF8)) + \rxeq_cnt[0]_i_1__1 + (.I0(rxeq_control_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I4(\rxeq_cnt_reg_n_0_[0] ), + .O(rxeq_cnt[0])); + (* SOFT_HLUTNM = "soft_lutpair145" *) + LUT4 #( + .INIT(16'h6660)) + \rxeq_cnt[1]_i_1__1 + (.I0(\rxeq_cnt_reg_n_0_[0] ), + .I1(\rxeq_cnt_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(rxeq_cnt[1])); + (* SOFT_HLUTNM = "soft_lutpair144" *) + LUT5 #( + .INIT(32'h78787800)) + \rxeq_cnt[2]_i_1__1 + (.I0(\rxeq_cnt_reg_n_0_[1] ), + .I1(\rxeq_cnt_reg_n_0_[0] ), + .I2(\rxeq_cnt_reg_n_0_[2] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(rxeq_cnt[2])); + FDRE #( + .INIT(1'b0)) + \rxeq_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_cnt[0]), + .Q(\rxeq_cnt_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_cnt[1]), + .Q(\rxeq_cnt_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_cnt[2]), + .Q(\rxeq_cnt_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_control_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_control_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_control_reg1[0]), + .Q(rxeq_control_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_control_reg1[1]), + .Q(rxeq_control_reg2[1]), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[0]_i_1__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[0]), + .O(rxeq_fs[0])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[1]_i_1__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[1]), + .O(rxeq_fs[1])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[2]_i_1__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[2]), + .O(rxeq_fs[2])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[3]_i_1__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[3]), + .O(rxeq_fs[3])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[4]_i_1__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[4]), + .O(rxeq_fs[4])); + LUT3 #( + .INIT(8'hF8)) + \rxeq_fs[5]_i_1__1 + (.I0(rxeq_control_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx[1]_i_2__1_n_0 ), + .O(\rxeq_fs[5]_i_1__1_n_0 )); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[5]_i_2__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[5]), + .O(rxeq_fs[5])); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__1_n_0 ), + .D(rxeq_fs[0]), + .Q(\rxeq_fs_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__1_n_0 ), + .D(rxeq_fs[1]), + .Q(\rxeq_fs_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__1_n_0 ), + .D(rxeq_fs[2]), + .Q(\rxeq_fs_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__1_n_0 ), + .D(rxeq_fs[3]), + .Q(\rxeq_fs_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[4] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__1_n_0 ), + .D(rxeq_fs[4]), + .Q(\rxeq_fs_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[5] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__1_n_0 ), + .D(rxeq_fs[5]), + .Q(\rxeq_fs_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[0]_i_1__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[0]), + .O(rxeq_lf[0])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[1]_i_1__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[1]), + .O(rxeq_lf[1])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[2]_i_1__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[2]), + .O(rxeq_lf[2])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[3]_i_1__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[3]), + .O(rxeq_lf[3])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[4]_i_1__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[4]), + .O(rxeq_lf[4])); + LUT5 #( + .INIT(32'hEAAAAAAA)) + \rxeq_lf[5]_i_1__1 + (.I0(\FSM_onehot_fsm_rx[1]_i_2__1_n_0 ), + .I1(\rxeq_cnt_reg_n_0_[2] ), + .I2(\rxeq_cnt_reg_n_0_[0] ), + .I3(\rxeq_cnt_reg_n_0_[1] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .O(\rxeq_lf[5]_i_1__1_n_0 )); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[5]_i_2__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[5]), + .O(rxeq_lf[5])); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__1_n_0 ), + .D(rxeq_lf[0]), + .Q(\rxeq_lf_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__1_n_0 ), + .D(rxeq_lf[1]), + .Q(\rxeq_lf_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__1_n_0 ), + .D(rxeq_lf[2]), + .Q(\rxeq_lf_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__1_n_0 ), + .D(rxeq_lf[3]), + .Q(\rxeq_lf_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[4] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__1_n_0 ), + .D(rxeq_lf[4]), + .Q(\rxeq_lf_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[5] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__1_n_0 ), + .D(rxeq_lf[5]), + .Q(\rxeq_lf_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[0]), + .Q(rxeq_lffs_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[1]), + .Q(rxeq_lffs_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[2]), + .Q(rxeq_lffs_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[3]), + .Q(rxeq_lffs_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[4]), + .Q(rxeq_lffs_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[5]), + .Q(rxeq_lffs_reg2[5]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + rxeq_new_txcoeff_req_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_new_txcoeff_req), + .Q(rxeq_new_txcoeff_req_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hA8FFA800)) + \rxeq_preset[0]_i_1__1 + (.I0(rxeq_preset_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(\rxeq_preset[2]_i_2__1_n_0 ), + .I4(\rxeq_preset_reg_n_0_[0] ), + .O(\rxeq_preset[0]_i_1__1_n_0 )); + LUT5 #( + .INIT(32'hA8FFA800)) + \rxeq_preset[1]_i_1__1 + (.I0(rxeq_preset_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(\rxeq_preset[2]_i_2__1_n_0 ), + .I4(\rxeq_preset_reg_n_0_[1] ), + .O(\rxeq_preset[1]_i_1__1_n_0 )); + LUT5 #( + .INIT(32'hA8FFA800)) + \rxeq_preset[2]_i_1__1 + (.I0(rxeq_preset_reg2[2]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(\rxeq_preset[2]_i_2__1_n_0 ), + .I4(\rxeq_preset_reg_n_0_[2] ), + .O(\rxeq_preset[2]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF0002)) + \rxeq_preset[2]_i_2__1 + (.I0(\rxeq_preset[2]_i_3__1_n_0 ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .I4(rxeq_adapt_done_reg_i_2__1_n_0), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .O(\rxeq_preset[2]_i_2__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair145" *) + LUT2 #( + .INIT(4'h1)) + \rxeq_preset[2]_i_3__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\rxeq_preset[2]_i_3__1_n_0 )); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_preset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_preset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_preset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_reg1[0]), + .Q(rxeq_preset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_reg1[1]), + .Q(rxeq_preset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_reg1[2]), + .Q(rxeq_preset_reg2[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_preset_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxeq_preset[0]_i_1__1_n_0 ), + .Q(\rxeq_preset_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_preset_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxeq_preset[1]_i_1__1_n_0 ), + .Q(\rxeq_preset_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_preset_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxeq_preset[2]_i_1__1_n_0 ), + .Q(\rxeq_preset_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + rxeq_preset_valid_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .Q(rxeq_preset_valid), + .R(RST_CPLLRESET)); + pcie_7x_0_pcie_7x_0_rxeq_scan_55 rxeq_scan_i + (.D({rxeq_scan_i_n_0,rxeq_scan_i_n_1,rxeq_scan_i_n_2}), + .\FSM_onehot_fsm_rx_reg[5] ({\rxeq_cnt_reg_n_0_[2] ,\rxeq_cnt_reg_n_0_[1] ,\rxeq_cnt_reg_n_0_[0] }), + .Q({\FSM_onehot_fsm_rx_reg_n_0_[6] ,\FSM_onehot_fsm_rx_reg_n_0_[5] ,\FSM_onehot_fsm_rx_reg_n_0_[4] ,\FSM_onehot_fsm_rx_reg_n_0_[2] ,\FSM_onehot_fsm_rx_reg_n_0_[1] }), + .RST_CPLLRESET(RST_CPLLRESET), + .USER_RXEQ_ADAPT_DONE(USER_RXEQ_ADAPT_DONE), + .adapt_done_reg_0(rxeq_scan_i_n_4), + .\fs_reg1_reg[5]_0 ({\rxeq_fs_reg_n_0_[5] ,\rxeq_fs_reg_n_0_[4] ,\rxeq_fs_reg_n_0_[3] ,\rxeq_fs_reg_n_0_[2] ,\rxeq_fs_reg_n_0_[1] ,\rxeq_fs_reg_n_0_[0] }), + .\lf_reg1_reg[5]_0 ({\rxeq_lf_reg_n_0_[5] ,\rxeq_lf_reg_n_0_[4] ,\rxeq_lf_reg_n_0_[3] ,\rxeq_lf_reg_n_0_[2] ,\rxeq_lf_reg_n_0_[1] ,\rxeq_lf_reg_n_0_[0] }), + .new_txcoeff_done_reg_0(rxeq_scan_i_n_5), + .new_txcoeff_req_reg1_reg_0(rxeq_new_txcoeff_req_reg_n_0), + .out(rxeq_control_reg2), + .pipe_pclk_in(pipe_pclk_in), + .\preset_reg1_reg[2]_0 ({\rxeq_preset_reg_n_0_[2] ,\rxeq_preset_reg_n_0_[1] ,\rxeq_preset_reg_n_0_[0] }), + .rxeq_adapt_done_reg(rxeq_adapt_done_i_2__1_n_0), + .rxeq_adapt_done_reg_reg(\FSM_onehot_fsm_rx[1]_i_2__1_n_0 ), + .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_i_2__1_n_0), + .rxeq_adapt_done_reg_reg_1(rxeq_adapt_done_reg_reg_n_0), + .rxeq_new_txcoeff_req(rxeq_new_txcoeff_req), + .rxeq_preset_valid(rxeq_preset_valid), + .\txcoeff_reg1_reg[17]_0 ({\rxeq_txcoeff_reg_n_0_[17] ,\rxeq_txcoeff_reg_n_0_[16] ,\rxeq_txcoeff_reg_n_0_[15] ,\rxeq_txcoeff_reg_n_0_[14] ,\rxeq_txcoeff_reg_n_0_[13] ,\rxeq_txcoeff_reg_n_0_[12] ,\rxeq_txcoeff_reg_n_0_[11] ,\rxeq_txcoeff_reg_n_0_[10] ,\rxeq_txcoeff_reg_n_0_[9] ,\rxeq_txcoeff_reg_n_0_[8] ,\rxeq_txcoeff_reg_n_0_[7] ,\rxeq_txcoeff_reg_n_0_[6] ,\rxeq_txcoeff_reg_n_0_[5] ,\rxeq_txcoeff_reg_n_0_[4] ,\rxeq_txcoeff_reg_n_0_[3] ,\rxeq_txcoeff_reg_n_0_[2] ,\rxeq_txcoeff_reg_n_0_[1] ,\rxeq_txcoeff_reg_n_0_[0] }), + .\txpreset_reg1_reg[3]_0 ({\rxeq_txpreset_reg_n_0_[3] ,\rxeq_txpreset_reg_n_0_[2] ,\rxeq_txpreset_reg_n_0_[1] ,\rxeq_txpreset_reg_n_0_[0] })); + (* SOFT_HLUTNM = "soft_lutpair146" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[0]_i_1__1 + (.I0(\rxeq_txcoeff_reg_n_0_[6] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[0])); + (* SOFT_HLUTNM = "soft_lutpair151" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[10]_i_1__1 + (.I0(\rxeq_txcoeff_reg_n_0_[16] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[10])); + (* SOFT_HLUTNM = "soft_lutpair151" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[11]_i_1__1 + (.I0(\rxeq_txcoeff_reg_n_0_[17] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[11])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[12]_i_1__1 + (.I0(txeq_deemph_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[12])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[13]_i_1__1 + (.I0(txeq_deemph_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[13])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[14]_i_1__1 + (.I0(txeq_deemph_reg2[2]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[14])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[15]_i_1__1 + (.I0(txeq_deemph_reg2[3]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[15])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[16]_i_1__1 + (.I0(txeq_deemph_reg2[4]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[16])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[17]_i_1__1 + (.I0(txeq_deemph_reg2[5]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[17])); + (* SOFT_HLUTNM = "soft_lutpair146" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[1]_i_1__1 + (.I0(\rxeq_txcoeff_reg_n_0_[7] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[1])); + (* SOFT_HLUTNM = "soft_lutpair147" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[2]_i_1__1 + (.I0(\rxeq_txcoeff_reg_n_0_[8] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[2])); + (* SOFT_HLUTNM = "soft_lutpair147" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[3]_i_1__1 + (.I0(\rxeq_txcoeff_reg_n_0_[9] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[3])); + (* SOFT_HLUTNM = "soft_lutpair148" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[4]_i_1__1 + (.I0(\rxeq_txcoeff_reg_n_0_[10] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[4])); + (* SOFT_HLUTNM = "soft_lutpair148" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[5]_i_1__1 + (.I0(\rxeq_txcoeff_reg_n_0_[11] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[5])); + (* SOFT_HLUTNM = "soft_lutpair149" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[6]_i_1__1 + (.I0(\rxeq_txcoeff_reg_n_0_[12] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[6])); + (* SOFT_HLUTNM = "soft_lutpair149" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[7]_i_1__1 + (.I0(\rxeq_txcoeff_reg_n_0_[13] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[7])); + (* SOFT_HLUTNM = "soft_lutpair150" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[8]_i_1__1 + (.I0(\rxeq_txcoeff_reg_n_0_[14] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[8])); + (* SOFT_HLUTNM = "soft_lutpair150" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[9]_i_1__1 + (.I0(\rxeq_txcoeff_reg_n_0_[15] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[9])); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[0]), + .Q(\rxeq_txcoeff_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[10] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[10]), + .Q(\rxeq_txcoeff_reg_n_0_[10] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[11] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[11]), + .Q(\rxeq_txcoeff_reg_n_0_[11] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[12] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[12]), + .Q(\rxeq_txcoeff_reg_n_0_[12] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[13] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[13]), + .Q(\rxeq_txcoeff_reg_n_0_[13] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[14] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[14]), + .Q(\rxeq_txcoeff_reg_n_0_[14] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[15] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[15]), + .Q(\rxeq_txcoeff_reg_n_0_[15] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[16] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[16]), + .Q(\rxeq_txcoeff_reg_n_0_[16] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[17] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[17]), + .Q(\rxeq_txcoeff_reg_n_0_[17] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[1]), + .Q(\rxeq_txcoeff_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[2]), + .Q(\rxeq_txcoeff_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[3]), + .Q(\rxeq_txcoeff_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[4] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[4]), + .Q(\rxeq_txcoeff_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[5] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[5]), + .Q(\rxeq_txcoeff_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[6] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[6]), + .Q(\rxeq_txcoeff_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[7] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[7]), + .Q(\rxeq_txcoeff_reg_n_0_[7] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[8] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[8]), + .Q(\rxeq_txcoeff_reg_n_0_[8] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[9] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txcoeff[9]), + .Q(\rxeq_txcoeff_reg_n_0_[9] ), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[0]_i_1__1 + (.I0(rxeq_txpreset_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[0])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[1]_i_1__1 + (.I0(rxeq_txpreset_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[1])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[2]_i_1__1 + (.I0(rxeq_txpreset_reg2[2]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[2])); + LUT5 #( + .INIT(32'hFFFFF404)) + \rxeq_txpreset[3]_i_1__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .I1(\rxeq_txpreset[3]_i_3__1_n_0 ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(rxeq_control_reg2[1]), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\rxeq_txpreset[3]_i_1__1_n_0 )); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[3]_i_2__1 + (.I0(rxeq_txpreset_reg2[3]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[3])); + LUT3 #( + .INIT(8'h01)) + \rxeq_txpreset[3]_i_3__1 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .O(\rxeq_txpreset[3]_i_3__1_n_0 )); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[0]), + .Q(rxeq_txpreset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[1]), + .Q(rxeq_txpreset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[2]), + .Q(rxeq_txpreset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[3]), + .Q(rxeq_txpreset_reg2[3]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txpreset[0]), + .Q(\rxeq_txpreset_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txpreset[1]), + .Q(\rxeq_txpreset_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txpreset[2]), + .Q(\rxeq_txpreset_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__1_n_0 ), + .D(rxeq_txpreset[3]), + .Q(\rxeq_txpreset_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_en_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_en_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_en_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_en_reg1), + .Q(rxeq_user_en_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_mode_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_mode_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_mode_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_mode_reg1), + .Q(rxeq_user_mode_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[0]), + .Q(rxeq_user_txcoeff_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[10]), + .Q(rxeq_user_txcoeff_reg2[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[11]), + .Q(rxeq_user_txcoeff_reg2[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[12]), + .Q(rxeq_user_txcoeff_reg2[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[13]), + .Q(rxeq_user_txcoeff_reg2[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[14]), + .Q(rxeq_user_txcoeff_reg2[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[15]), + .Q(rxeq_user_txcoeff_reg2[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[16]), + .Q(rxeq_user_txcoeff_reg2[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[17]), + .Q(rxeq_user_txcoeff_reg2[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[1]), + .Q(rxeq_user_txcoeff_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[2]), + .Q(rxeq_user_txcoeff_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[3]), + .Q(rxeq_user_txcoeff_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[4]), + .Q(rxeq_user_txcoeff_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[5]), + .Q(rxeq_user_txcoeff_reg2[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[6]), + .Q(rxeq_user_txcoeff_reg2[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[7]), + .Q(rxeq_user_txcoeff_reg2[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[8]), + .Q(rxeq_user_txcoeff_reg2[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[9]), + .Q(rxeq_user_txcoeff_reg2[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_control_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_control_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_control_reg1[0]), + .Q(txeq_control_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_control_reg1[1]), + .Q(txeq_control_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \txeq_deemph_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[0]), + .S(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \txeq_deemph_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[0]), + .Q(txeq_deemph_reg2[0]), + .S(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[1]), + .Q(txeq_deemph_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[2]), + .Q(txeq_deemph_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[3]), + .Q(txeq_deemph_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[4]), + .Q(txeq_deemph_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[5]), + .Q(txeq_deemph_reg2[5]), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h00001000)) + \txeq_preset[0]_i_1__1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[2]), + .I2(txeq_preset_reg2[0]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[1]), + .O(p_0_out[0])); + LUT5 #( + .INIT(32'hABEAABAF)) + \txeq_preset[10]_i_1__1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[2]), + .I2(txeq_preset_reg2[0]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[1]), + .O(p_0_out[10])); + LUT5 #( + .INIT(32'hFFFF200D)) + \txeq_preset[11]_i_1__1 + (.I0(txeq_preset_reg2[1]), + .I1(txeq_preset_reg2[3]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[0]), + .I4(RST_CPLLRESET), + .O(p_0_out[11])); + LUT5 #( + .INIT(32'h01151110)) + \txeq_preset[12]_i_1__1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[3]), + .I2(txeq_preset_reg2[1]), + .I3(txeq_preset_reg2[2]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[12])); + LUT5 #( + .INIT(32'h01000010)) + \txeq_preset[13]_i_1__1 + (.I0(txeq_preset_reg2[2]), + .I1(RST_CPLLRESET), + .I2(txeq_preset_reg2[0]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[1]), + .O(p_0_out[13])); + LUT5 #( + .INIT(32'h01000010)) + \txeq_preset[14]_i_1__1 + (.I0(txeq_preset_reg2[2]), + .I1(RST_CPLLRESET), + .I2(txeq_preset_reg2[3]), + .I3(txeq_preset_reg2[1]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[14])); + LUT4 #( + .INIT(16'hF0F1)) + \txeq_preset[15]_i_1__1 + (.I0(txeq_preset_reg2[2]), + .I1(txeq_preset_reg2[1]), + .I2(RST_CPLLRESET), + .I3(txeq_preset_reg2[3]), + .O(p_0_out[15])); + LUT4 #( + .INIT(16'h0006)) + \txeq_preset[16]_i_1__1 + (.I0(txeq_preset_reg2[3]), + .I1(txeq_preset_reg2[0]), + .I2(txeq_preset_reg2[2]), + .I3(RST_CPLLRESET), + .O(p_0_out[16])); + LUT4 #( + .INIT(16'hAABA)) + \txeq_preset[17]_i_1__1 + (.I0(RST_CPLLRESET), + .I1(fsm_tx[0]), + .I2(fsm_tx[1]), + .I3(fsm_tx[2]), + .O(\txeq_preset[17]_i_1__1_n_0 )); + LUT5 #( + .INIT(32'hFFFF400D)) + \txeq_preset[17]_i_2__1 + (.I0(txeq_preset_reg2[3]), + .I1(txeq_preset_reg2[1]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[0]), + .I4(RST_CPLLRESET), + .O(p_0_out[17])); + LUT5 #( + .INIT(32'h00001004)) + \txeq_preset[1]_i_1__1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[3]), + .I2(txeq_preset_reg2[1]), + .I3(txeq_preset_reg2[2]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[1])); + LUT4 #( + .INIT(16'h0E00)) + \txeq_preset[2]_i_1__1 + (.I0(txeq_preset_reg2[2]), + .I1(txeq_preset_reg2[0]), + .I2(RST_CPLLRESET), + .I3(txeq_preset_reg2[3]), + .O(p_0_out[2])); + LUT5 #( + .INIT(32'h01440140)) + \txeq_preset[3]_i_1__1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[2]), + .I2(txeq_preset_reg2[1]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[0]), + .O(\txeq_preset[3]_i_1__1_n_0 )); + LUT5 #( + .INIT(32'h00001400)) + \txeq_preset[7]_i_1__1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[0]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[1]), + .I4(txeq_preset_reg2[3]), + .O(\txeq_preset[7]_i_1__1_n_0 )); + LUT5 #( + .INIT(32'hAAAFBEAF)) + \txeq_preset[8]_i_1__1 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[0]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[1]), + .I4(txeq_preset_reg2[3]), + .O(p_0_out[8])); + LUT5 #( + .INIT(32'hCCFCCFCD)) + \txeq_preset[9]_i_1__1 + (.I0(txeq_preset_reg2[1]), + .I1(RST_CPLLRESET), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[9])); + (* SOFT_HLUTNM = "soft_lutpair143" *) + LUT3 #( + .INIT(8'h04)) + txeq_preset_done_i_1__1 + (.I0(fsm_tx[2]), + .I1(fsm_tx[1]), + .I2(fsm_tx[0]), + .O(txeq_preset_done_i_1__1_n_0)); + FDRE #( + .INIT(1'b0)) + txeq_preset_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_done_i_1__1_n_0), + .Q(txeq_preset_done), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[0]), + .Q(txeq_preset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[1]), + .Q(txeq_preset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[2]), + .Q(txeq_preset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[3]), + .Q(txeq_preset_reg2[3]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[0] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(p_0_out[0]), + .Q(\txeq_preset_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[10] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(p_0_out[10]), + .Q(\txeq_preset_reg_n_0_[10] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[11] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(p_0_out[11]), + .Q(\txeq_preset_reg_n_0_[11] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[12] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(p_0_out[12]), + .Q(\txeq_preset_reg_n_0_[12] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[13] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(p_0_out[13]), + .Q(\txeq_preset_reg_n_0_[13] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[14] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(p_0_out[14]), + .Q(\txeq_preset_reg_n_0_[14] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[15] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(p_0_out[15]), + .Q(\txeq_preset_reg_n_0_[15] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[16] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(p_0_out[16]), + .Q(\txeq_preset_reg_n_0_[16] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[17] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(p_0_out[17]), + .Q(\txeq_preset_reg_n_0_[17] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[1] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(p_0_out[1]), + .Q(\txeq_preset_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[2] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(p_0_out[2]), + .Q(\txeq_preset_reg_n_0_[2] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[3] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(\txeq_preset[3]_i_1__1_n_0 ), + .Q(\txeq_preset_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[7] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(\txeq_preset[7]_i_1__1_n_0 ), + .Q(\txeq_preset_reg_n_0_[7] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[8] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(p_0_out[8]), + .Q(\txeq_preset_reg_n_0_[8] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[9] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__1_n_0 ), + .D(p_0_out[9]), + .Q(\txeq_preset_reg_n_0_[9] ), + .R(1'b0)); + LUT5 #( + .INIT(32'h45404040)) + \txeq_txcoeff[0]_i_1__1 + (.I0(fsm_tx[2]), + .I1(\txeq_txcoeff[0]_i_2__1_n_0 ), + .I2(fsm_tx[1]), + .I3(fsm_tx[0]), + .I4(\txeq_txcoeff_reg_n_0_[6] ), + .O(\txeq_txcoeff[0]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[0]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[6] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[7] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[0] ), + .O(\txeq_txcoeff[0]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[10]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[9] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[10]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[16] ), + .O(\txeq_txcoeff[10]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[10]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[16] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[17] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[10] ), + .O(\txeq_txcoeff[10]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[11]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[10] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[11]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[17] ), + .O(\txeq_txcoeff[11]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[11]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[17] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[18] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[11] ), + .O(\txeq_txcoeff[11]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[12]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[11] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[12]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[18] ), + .O(\txeq_txcoeff[12]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[12]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[18] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[0]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[12] ), + .O(\txeq_txcoeff[12]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[13]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[12] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[13]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[0]), + .O(\txeq_txcoeff[13]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[13]_i_2__1 + (.I0(txeq_deemph_reg2[0]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[1]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[13] ), + .O(\txeq_txcoeff[13]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[14]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[13] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[14]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[1]), + .O(\txeq_txcoeff[14]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[14]_i_2__1 + (.I0(txeq_deemph_reg2[1]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[2]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[14] ), + .O(\txeq_txcoeff[14]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[15]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[14] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[15]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[2]), + .O(\txeq_txcoeff[15]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[15]_i_2__1 + (.I0(txeq_deemph_reg2[2]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[3]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[15] ), + .O(\txeq_txcoeff[15]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[16]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[15] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[16]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[3]), + .O(\txeq_txcoeff[16]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[16]_i_2__1 + (.I0(txeq_deemph_reg2[3]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[4]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[16] ), + .O(\txeq_txcoeff[16]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[17]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[16] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[17]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[4]), + .O(\txeq_txcoeff[17]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[17]_i_2__1 + (.I0(txeq_deemph_reg2[4]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[5]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[17] ), + .O(\txeq_txcoeff[17]_i_2__1_n_0 )); + LUT5 #( + .INIT(32'hFF040FFF)) + \txeq_txcoeff[18]_i_1__1 + (.I0(txeq_control_reg2[0]), + .I1(txeq_control_reg2[1]), + .I2(fsm_tx[2]), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .O(txeq_txcoeff)); + LUT6 #( + .INIT(64'h22F3220022002200)) + \txeq_txcoeff[18]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[17] ), + .I1(fsm_tx[1]), + .I2(\txeq_txcoeff[18]_i_3__1_n_0 ), + .I3(fsm_tx[2]), + .I4(txeq_deemph_reg2[5]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[18]_i_2__1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \txeq_txcoeff[18]_i_3__1 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .O(\txeq_txcoeff[18]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[1]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[0] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[1]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[7] ), + .O(\txeq_txcoeff[1]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[1]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[7] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[8] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[1] ), + .O(\txeq_txcoeff[1]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[2]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[1] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[2]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[8] ), + .O(\txeq_txcoeff[2]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[2]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[8] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[9] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[2] ), + .O(\txeq_txcoeff[2]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[3]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[2] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[3]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[9] ), + .O(\txeq_txcoeff[3]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[3]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[9] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[10] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[3] ), + .O(\txeq_txcoeff[3]_i_2__1_n_0 )); + LUT4 #( + .INIT(16'h2F20)) + \txeq_txcoeff[4]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[3] ), + .I1(fsm_tx[1]), + .I2(fsm_tx[2]), + .I3(\txeq_txcoeff[4]_i_2__1_n_0 ), + .O(\txeq_txcoeff[4]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hCACCCCCC00000000)) + \txeq_txcoeff[4]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[11] ), + .I1(\txeq_txcoeff_reg_n_0_[10] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I4(fsm_tx[1]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[4]_i_2__1_n_0 )); + LUT4 #( + .INIT(16'h2F20)) + \txeq_txcoeff[5]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[4] ), + .I1(fsm_tx[1]), + .I2(fsm_tx[2]), + .I3(\txeq_txcoeff[5]_i_2__1_n_0 ), + .O(\txeq_txcoeff[5]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hCACCCCCC00000000)) + \txeq_txcoeff[5]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[12] ), + .I1(\txeq_txcoeff_reg_n_0_[11] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I4(fsm_tx[1]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[5]_i_2__1_n_0 )); + LUT4 #( + .INIT(16'h2F20)) + \txeq_txcoeff[6]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[5] ), + .I1(fsm_tx[1]), + .I2(fsm_tx[2]), + .I3(\txeq_txcoeff[6]_i_2__1_n_0 ), + .O(\txeq_txcoeff[6]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hCACCCCCC00000000)) + \txeq_txcoeff[6]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[13] ), + .I1(\txeq_txcoeff_reg_n_0_[12] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I4(fsm_tx[1]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[6]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[7]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[6] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[7]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[13] ), + .O(\txeq_txcoeff[7]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[7]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[13] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[14] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[7] ), + .O(\txeq_txcoeff[7]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[8]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[7] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[8]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[14] ), + .O(\txeq_txcoeff[8]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[8]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[14] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[15] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[8] ), + .O(\txeq_txcoeff[8]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[9]_i_1__1 + (.I0(\txeq_txcoeff_reg_n_0_[8] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[9]_i_2__1_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[15] ), + .O(\txeq_txcoeff[9]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[9]_i_2__1 + (.I0(\txeq_txcoeff_reg_n_0_[15] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[16] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[9] ), + .O(\txeq_txcoeff[9]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h000004000F000400)) + \txeq_txcoeff_cnt[0]_i_1__1 + (.I0(txeq_control_reg2[0]), + .I1(txeq_control_reg2[1]), + .I2(fsm_tx[2]), + .I3(fsm_tx[0]), + .I4(fsm_tx[1]), + .I5(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .O(txeq_txcoeff_cnt[0])); + (* SOFT_HLUTNM = "soft_lutpair143" *) + LUT5 #( + .INIT(32'h00006000)) + \txeq_txcoeff_cnt[1]_i_1__1 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I2(fsm_tx[0]), + .I3(fsm_tx[1]), + .I4(fsm_tx[2]), + .O(txeq_txcoeff_cnt[1])); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_txcoeff_cnt[0]), + .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_txcoeff_cnt[1]), + .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[0] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[0]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[10] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[10]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[10] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[11] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[11]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[11] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[12] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[12]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[12] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[13] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[13]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[13] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[14] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[14]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[14] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[15] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[15]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[15] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[16] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[16]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[16] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[17] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[17]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[17] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[18] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[18]_i_2__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[18] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[1] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[1]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[2] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[2]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[3] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[3]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[4] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[4]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[5] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[5]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[6] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[6]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[7] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[7]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[7] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[8] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[8]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[8] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[9] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[9]_i_1__1_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[9] ), + .R(RST_CPLLRESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_eq" *) +module pcie_7x_0_pcie_7x_0_pipe_eq_51 + (TXPRECURSOR, + TXMAINCURSOR, + TXPOSTCURSOR, + USER_RXEQ_ADAPT_DONE, + RST_CPLLRESET, + pipe_pclk_in, + rate_gen3_3); + output [4:0]TXPRECURSOR; + output [6:0]TXMAINCURSOR; + output [4:0]TXPOSTCURSOR; + output USER_RXEQ_ADAPT_DONE; + input RST_CPLLRESET; + input pipe_pclk_in; + input rate_gen3_3; + + wire \FSM_onehot_fsm_rx[1]_i_1__2_n_0 ; + wire \FSM_onehot_fsm_rx[1]_i_2__2_n_0 ; + wire \FSM_onehot_fsm_rx[3]_i_1__2_n_0 ; + wire \FSM_onehot_fsm_rx[4]_i_1__2_n_0 ; + wire \FSM_onehot_fsm_rx_reg_n_0_[1] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[2] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[3] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[4] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[5] ; + wire \FSM_onehot_fsm_rx_reg_n_0_[6] ; + wire \FSM_sequential_fsm_tx[1]_i_2__2_n_0 ; + wire \FSM_sequential_fsm_tx[2]_i_2__2_n_0 ; + wire RST_CPLLRESET; + wire [6:0]TXMAINCURSOR; + wire [4:0]TXPOSTCURSOR; + wire [4:0]TXPRECURSOR; + wire USER_RXEQ_ADAPT_DONE; + wire [2:0]fsm_tx; + wire [2:0]fsm_tx__0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2; + wire [17:0]p_0_out; + wire pipe_pclk_in; + wire rate_gen3_3; + wire rxeq_adapt_done_i_2__2_n_0; + wire rxeq_adapt_done_reg_i_2__2_n_0; + wire rxeq_adapt_done_reg_reg_n_0; + wire [2:0]rxeq_cnt; + wire \rxeq_cnt_reg_n_0_[0] ; + wire \rxeq_cnt_reg_n_0_[1] ; + wire \rxeq_cnt_reg_n_0_[2] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxeq_control_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxeq_control_reg2; + wire [5:0]rxeq_fs; + wire \rxeq_fs[5]_i_1__2_n_0 ; + wire \rxeq_fs_reg_n_0_[0] ; + wire \rxeq_fs_reg_n_0_[1] ; + wire \rxeq_fs_reg_n_0_[2] ; + wire \rxeq_fs_reg_n_0_[3] ; + wire \rxeq_fs_reg_n_0_[4] ; + wire \rxeq_fs_reg_n_0_[5] ; + wire [5:0]rxeq_lf; + wire \rxeq_lf[5]_i_1__2_n_0 ; + wire \rxeq_lf_reg_n_0_[0] ; + wire \rxeq_lf_reg_n_0_[1] ; + wire \rxeq_lf_reg_n_0_[2] ; + wire \rxeq_lf_reg_n_0_[3] ; + wire \rxeq_lf_reg_n_0_[4] ; + wire \rxeq_lf_reg_n_0_[5] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]rxeq_lffs_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]rxeq_lffs_reg2; + wire rxeq_new_txcoeff_req; + wire rxeq_new_txcoeff_req_reg_n_0; + wire \rxeq_preset[0]_i_1__2_n_0 ; + wire \rxeq_preset[1]_i_1__2_n_0 ; + wire \rxeq_preset[2]_i_1__2_n_0 ; + wire \rxeq_preset[2]_i_2__2_n_0 ; + wire \rxeq_preset[2]_i_3__2_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]rxeq_preset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]rxeq_preset_reg2; + wire \rxeq_preset_reg_n_0_[0] ; + wire \rxeq_preset_reg_n_0_[1] ; + wire \rxeq_preset_reg_n_0_[2] ; + wire rxeq_preset_valid; + wire rxeq_scan_i_n_0; + wire rxeq_scan_i_n_1; + wire rxeq_scan_i_n_2; + wire rxeq_scan_i_n_4; + wire rxeq_scan_i_n_5; + wire [17:0]rxeq_txcoeff; + wire \rxeq_txcoeff_reg_n_0_[0] ; + wire \rxeq_txcoeff_reg_n_0_[10] ; + wire \rxeq_txcoeff_reg_n_0_[11] ; + wire \rxeq_txcoeff_reg_n_0_[12] ; + wire \rxeq_txcoeff_reg_n_0_[13] ; + wire \rxeq_txcoeff_reg_n_0_[14] ; + wire \rxeq_txcoeff_reg_n_0_[15] ; + wire \rxeq_txcoeff_reg_n_0_[16] ; + wire \rxeq_txcoeff_reg_n_0_[17] ; + wire \rxeq_txcoeff_reg_n_0_[1] ; + wire \rxeq_txcoeff_reg_n_0_[2] ; + wire \rxeq_txcoeff_reg_n_0_[3] ; + wire \rxeq_txcoeff_reg_n_0_[4] ; + wire \rxeq_txcoeff_reg_n_0_[5] ; + wire \rxeq_txcoeff_reg_n_0_[6] ; + wire \rxeq_txcoeff_reg_n_0_[7] ; + wire \rxeq_txcoeff_reg_n_0_[8] ; + wire \rxeq_txcoeff_reg_n_0_[9] ; + wire [3:0]rxeq_txpreset; + wire \rxeq_txpreset[3]_i_1__2_n_0 ; + wire \rxeq_txpreset[3]_i_3__2_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxeq_txpreset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxeq_txpreset_reg2; + wire \rxeq_txpreset_reg_n_0_[0] ; + wire \rxeq_txpreset_reg_n_0_[1] ; + wire \rxeq_txpreset_reg_n_0_[2] ; + wire \rxeq_txpreset_reg_n_0_[3] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_en_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_en_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_mode_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_mode_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]rxeq_user_txcoeff_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]rxeq_user_txcoeff_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txeq_control_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txeq_control_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]txeq_deemph_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]txeq_deemph_reg2; + wire \txeq_preset[17]_i_1__2_n_0 ; + wire \txeq_preset[3]_i_1__2_n_0 ; + wire \txeq_preset[7]_i_1__2_n_0 ; + wire txeq_preset_done; + wire txeq_preset_done_i_1__2_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txeq_preset_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txeq_preset_reg2; + wire \txeq_preset_reg_n_0_[0] ; + wire \txeq_preset_reg_n_0_[10] ; + wire \txeq_preset_reg_n_0_[11] ; + wire \txeq_preset_reg_n_0_[12] ; + wire \txeq_preset_reg_n_0_[13] ; + wire \txeq_preset_reg_n_0_[14] ; + wire \txeq_preset_reg_n_0_[15] ; + wire \txeq_preset_reg_n_0_[16] ; + wire \txeq_preset_reg_n_0_[17] ; + wire \txeq_preset_reg_n_0_[1] ; + wire \txeq_preset_reg_n_0_[2] ; + wire \txeq_preset_reg_n_0_[3] ; + wire \txeq_preset_reg_n_0_[7] ; + wire \txeq_preset_reg_n_0_[8] ; + wire \txeq_preset_reg_n_0_[9] ; + wire txeq_txcoeff; + wire \txeq_txcoeff[0]_i_1__2_n_0 ; + wire \txeq_txcoeff[0]_i_2__2_n_0 ; + wire \txeq_txcoeff[10]_i_1__2_n_0 ; + wire \txeq_txcoeff[10]_i_2__2_n_0 ; + wire \txeq_txcoeff[11]_i_1__2_n_0 ; + wire \txeq_txcoeff[11]_i_2__2_n_0 ; + wire \txeq_txcoeff[12]_i_1__2_n_0 ; + wire \txeq_txcoeff[12]_i_2__2_n_0 ; + wire \txeq_txcoeff[13]_i_1__2_n_0 ; + wire \txeq_txcoeff[13]_i_2__2_n_0 ; + wire \txeq_txcoeff[14]_i_1__2_n_0 ; + wire \txeq_txcoeff[14]_i_2__2_n_0 ; + wire \txeq_txcoeff[15]_i_1__2_n_0 ; + wire \txeq_txcoeff[15]_i_2__2_n_0 ; + wire \txeq_txcoeff[16]_i_1__2_n_0 ; + wire \txeq_txcoeff[16]_i_2__2_n_0 ; + wire \txeq_txcoeff[17]_i_1__2_n_0 ; + wire \txeq_txcoeff[17]_i_2__2_n_0 ; + wire \txeq_txcoeff[18]_i_2__2_n_0 ; + wire \txeq_txcoeff[18]_i_3__2_n_0 ; + wire \txeq_txcoeff[1]_i_1__2_n_0 ; + wire \txeq_txcoeff[1]_i_2__2_n_0 ; + wire \txeq_txcoeff[2]_i_1__2_n_0 ; + wire \txeq_txcoeff[2]_i_2__2_n_0 ; + wire \txeq_txcoeff[3]_i_1__2_n_0 ; + wire \txeq_txcoeff[3]_i_2__2_n_0 ; + wire \txeq_txcoeff[4]_i_1__2_n_0 ; + wire \txeq_txcoeff[4]_i_2__2_n_0 ; + wire \txeq_txcoeff[5]_i_1__2_n_0 ; + wire \txeq_txcoeff[5]_i_2__2_n_0 ; + wire \txeq_txcoeff[6]_i_1__2_n_0 ; + wire \txeq_txcoeff[6]_i_2__2_n_0 ; + wire \txeq_txcoeff[7]_i_1__2_n_0 ; + wire \txeq_txcoeff[7]_i_2__2_n_0 ; + wire \txeq_txcoeff[8]_i_1__2_n_0 ; + wire \txeq_txcoeff[8]_i_2__2_n_0 ; + wire \txeq_txcoeff[9]_i_1__2_n_0 ; + wire \txeq_txcoeff[9]_i_2__2_n_0 ; + wire [1:0]txeq_txcoeff_cnt; + wire \txeq_txcoeff_cnt_reg_n_0_[0] ; + wire \txeq_txcoeff_cnt_reg_n_0_[1] ; + wire \txeq_txcoeff_reg_n_0_[0] ; + wire \txeq_txcoeff_reg_n_0_[10] ; + wire \txeq_txcoeff_reg_n_0_[11] ; + wire \txeq_txcoeff_reg_n_0_[12] ; + wire \txeq_txcoeff_reg_n_0_[13] ; + wire \txeq_txcoeff_reg_n_0_[14] ; + wire \txeq_txcoeff_reg_n_0_[15] ; + wire \txeq_txcoeff_reg_n_0_[16] ; + wire \txeq_txcoeff_reg_n_0_[17] ; + wire \txeq_txcoeff_reg_n_0_[18] ; + wire \txeq_txcoeff_reg_n_0_[1] ; + wire \txeq_txcoeff_reg_n_0_[2] ; + wire \txeq_txcoeff_reg_n_0_[3] ; + wire \txeq_txcoeff_reg_n_0_[4] ; + wire \txeq_txcoeff_reg_n_0_[5] ; + wire \txeq_txcoeff_reg_n_0_[6] ; + wire \txeq_txcoeff_reg_n_0_[7] ; + wire \txeq_txcoeff_reg_n_0_[8] ; + wire \txeq_txcoeff_reg_n_0_[9] ; + + LUT5 #( + .INIT(32'hABABABAA)) + \FSM_onehot_fsm_rx[1]_i_1__2 + (.I0(\FSM_onehot_fsm_rx[1]_i_2__2_n_0 ), + .I1(rxeq_control_reg2[1]), + .I2(rxeq_control_reg2[0]), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .O(\FSM_onehot_fsm_rx[1]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \FSM_onehot_fsm_rx[1]_i_2__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .O(\FSM_onehot_fsm_rx[1]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF8FF88888888)) + \FSM_onehot_fsm_rx[3]_i_1__2 + (.I0(rxeq_control_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\rxeq_cnt_reg_n_0_[2] ), + .I3(\rxeq_cnt_reg_n_0_[1] ), + .I4(\rxeq_cnt_reg_n_0_[0] ), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\FSM_onehot_fsm_rx[3]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair185" *) + LUT5 #( + .INIT(32'h2ABA2AAA)) + \FSM_onehot_fsm_rx[4]_i_1__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(\rxeq_cnt_reg_n_0_[2] ), + .I2(\rxeq_cnt_reg_n_0_[1] ), + .I3(\rxeq_cnt_reg_n_0_[0] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\FSM_onehot_fsm_rx[4]_i_1__2_n_0 )); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDSE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx[1]_i_1__2_n_0 ), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_2), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx[3]_i_1__2_n_0 ), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx[4]_i_1__2_n_0 ), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_1), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_rx_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_0), + .Q(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hC04FC043C04FF04F)) + \FSM_sequential_fsm_tx[0]_i_1__2 + (.I0(\FSM_sequential_fsm_tx[1]_i_2__2_n_0 ), + .I1(fsm_tx[0]), + .I2(fsm_tx[1]), + .I3(fsm_tx[2]), + .I4(txeq_control_reg2[1]), + .I5(txeq_control_reg2[0]), + .O(fsm_tx__0[0])); + LUT6 #( + .INIT(64'h3F703F7C3F7C0F70)) + \FSM_sequential_fsm_tx[1]_i_1__2 + (.I0(\FSM_sequential_fsm_tx[1]_i_2__2_n_0 ), + .I1(fsm_tx[0]), + .I2(fsm_tx[1]), + .I3(fsm_tx[2]), + .I4(txeq_control_reg2[1]), + .I5(txeq_control_reg2[0]), + .O(fsm_tx__0[1])); + (* SOFT_HLUTNM = "soft_lutpair183" *) + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_fsm_tx[1]_i_2__2 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .O(\FSM_sequential_fsm_tx[1]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h3A2A2A227F7F7F77)) + \FSM_sequential_fsm_tx[2]_i_1__2 + (.I0(fsm_tx[2]), + .I1(fsm_tx[1]), + .I2(fsm_tx[0]), + .I3(txeq_control_reg2[1]), + .I4(txeq_control_reg2[0]), + .I5(\FSM_sequential_fsm_tx[2]_i_2__2_n_0 ), + .O(fsm_tx__0[2])); + (* SOFT_HLUTNM = "soft_lutpair183" *) + LUT5 #( + .INIT(32'hD0FFDFFF)) + \FSM_sequential_fsm_tx[2]_i_2__2 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I2(fsm_tx[0]), + .I3(fsm_tx[1]), + .I4(txeq_preset_done), + .O(\FSM_sequential_fsm_tx[2]_i_2__2_n_0 )); + (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) + FDSE #( + .INIT(1'b0)) + \FSM_sequential_fsm_tx_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm_tx__0[0]), + .Q(fsm_tx[0]), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_fsm_tx_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm_tx__0[1]), + .Q(fsm_tx[1]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) + FDRE #( + .INIT(1'b0)) + \FSM_sequential_fsm_tx_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm_tx__0[2]), + .Q(fsm_tx[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_gen3_3), + .Q(gen3_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_reg1), + .Q(gen3_reg2), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_23__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[17] ), + .O(TXPOSTCURSOR[4])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_24__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[16] ), + .O(TXPOSTCURSOR[3])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_25__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[15] ), + .O(TXPOSTCURSOR[2])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_26__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[14] ), + .O(TXPOSTCURSOR[1])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_27__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[13] ), + .O(TXPOSTCURSOR[0])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_28__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[4] ), + .O(TXPRECURSOR[4])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_29__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[3] ), + .O(TXPRECURSOR[3])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_30__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[2] ), + .O(TXPRECURSOR[2])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_31__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[1] ), + .O(TXPRECURSOR[1])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_32__2 + (.I0(\txeq_txcoeff_reg_n_0_[0] ), + .I1(gen3_reg2), + .O(TXPRECURSOR[0])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_33__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[12] ), + .O(TXMAINCURSOR[6])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_34__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[11] ), + .O(TXMAINCURSOR[5])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_35__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[10] ), + .O(TXMAINCURSOR[4])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_36__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[9] ), + .O(TXMAINCURSOR[3])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_37__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[8] ), + .O(TXMAINCURSOR[2])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_38__2 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[7] ), + .O(TXMAINCURSOR[1])); + LUT2 #( + .INIT(4'h8)) + \gtx_channel.gtxe2_channel_i_i_39 + (.I0(gen3_reg2), + .I1(\txeq_txcoeff_reg_n_0_[6] ), + .O(TXMAINCURSOR[0])); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + rxeq_adapt_done_i_2__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .O(rxeq_adapt_done_i_2__2_n_0)); + FDRE #( + .INIT(1'b0)) + rxeq_adapt_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_5), + .Q(USER_RXEQ_ADAPT_DONE), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'h08)) + rxeq_adapt_done_reg_i_2__2 + (.I0(rxeq_control_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(rxeq_control_reg2[1]), + .O(rxeq_adapt_done_reg_i_2__2_n_0)); + FDRE #( + .INIT(1'b0)) + rxeq_adapt_done_reg_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_scan_i_n_4), + .Q(rxeq_adapt_done_reg_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h8888FFF8)) + \rxeq_cnt[0]_i_1__2 + (.I0(rxeq_control_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I4(\rxeq_cnt_reg_n_0_[0] ), + .O(rxeq_cnt[0])); + (* SOFT_HLUTNM = "soft_lutpair186" *) + LUT4 #( + .INIT(16'h6660)) + \rxeq_cnt[1]_i_1__2 + (.I0(\rxeq_cnt_reg_n_0_[0] ), + .I1(\rxeq_cnt_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(rxeq_cnt[1])); + (* SOFT_HLUTNM = "soft_lutpair185" *) + LUT5 #( + .INIT(32'h78787800)) + \rxeq_cnt[2]_i_1__2 + (.I0(\rxeq_cnt_reg_n_0_[1] ), + .I1(\rxeq_cnt_reg_n_0_[0] ), + .I2(\rxeq_cnt_reg_n_0_[2] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(rxeq_cnt[2])); + FDRE #( + .INIT(1'b0)) + \rxeq_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_cnt[0]), + .Q(\rxeq_cnt_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_cnt[1]), + .Q(\rxeq_cnt_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_cnt[2]), + .Q(\rxeq_cnt_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_control_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_control_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_control_reg1[0]), + .Q(rxeq_control_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_control_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_control_reg1[1]), + .Q(rxeq_control_reg2[1]), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[0]_i_1__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[0]), + .O(rxeq_fs[0])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[1]_i_1__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[1]), + .O(rxeq_fs[1])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[2]_i_1__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[2]), + .O(rxeq_fs[2])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[3]_i_1__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[3]), + .O(rxeq_fs[3])); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[4]_i_1__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[4]), + .O(rxeq_fs[4])); + LUT3 #( + .INIT(8'hF8)) + \rxeq_fs[5]_i_1__2 + (.I0(rxeq_control_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm_rx[1]_i_2__2_n_0 ), + .O(\rxeq_fs[5]_i_1__2_n_0 )); + LUT2 #( + .INIT(4'h8)) + \rxeq_fs[5]_i_2__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(rxeq_lffs_reg2[5]), + .O(rxeq_fs[5])); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__2_n_0 ), + .D(rxeq_fs[0]), + .Q(\rxeq_fs_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__2_n_0 ), + .D(rxeq_fs[1]), + .Q(\rxeq_fs_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__2_n_0 ), + .D(rxeq_fs[2]), + .Q(\rxeq_fs_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__2_n_0 ), + .D(rxeq_fs[3]), + .Q(\rxeq_fs_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[4] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__2_n_0 ), + .D(rxeq_fs[4]), + .Q(\rxeq_fs_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_fs_reg[5] + (.C(pipe_pclk_in), + .CE(\rxeq_fs[5]_i_1__2_n_0 ), + .D(rxeq_fs[5]), + .Q(\rxeq_fs_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[0]_i_1__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[0]), + .O(rxeq_lf[0])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[1]_i_1__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[1]), + .O(rxeq_lf[1])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[2]_i_1__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[2]), + .O(rxeq_lf[2])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[3]_i_1__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[3]), + .O(rxeq_lf[3])); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[4]_i_1__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[4]), + .O(rxeq_lf[4])); + LUT5 #( + .INIT(32'hEAAAAAAA)) + \rxeq_lf[5]_i_1__2 + (.I0(\FSM_onehot_fsm_rx[1]_i_2__2_n_0 ), + .I1(\rxeq_cnt_reg_n_0_[2] ), + .I2(\rxeq_cnt_reg_n_0_[0] ), + .I3(\rxeq_cnt_reg_n_0_[1] ), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .O(\rxeq_lf[5]_i_1__2_n_0 )); + LUT2 #( + .INIT(4'h8)) + \rxeq_lf[5]_i_2__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I1(rxeq_lffs_reg2[5]), + .O(rxeq_lf[5])); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__2_n_0 ), + .D(rxeq_lf[0]), + .Q(\rxeq_lf_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__2_n_0 ), + .D(rxeq_lf[1]), + .Q(\rxeq_lf_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__2_n_0 ), + .D(rxeq_lf[2]), + .Q(\rxeq_lf_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__2_n_0 ), + .D(rxeq_lf[3]), + .Q(\rxeq_lf_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[4] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__2_n_0 ), + .D(rxeq_lf[4]), + .Q(\rxeq_lf_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_lf_reg[5] + (.C(pipe_pclk_in), + .CE(\rxeq_lf[5]_i_1__2_n_0 ), + .D(rxeq_lf[5]), + .Q(\rxeq_lf_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_lffs_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[0]), + .Q(rxeq_lffs_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[1]), + .Q(rxeq_lffs_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[2]), + .Q(rxeq_lffs_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[3]), + .Q(rxeq_lffs_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[4]), + .Q(rxeq_lffs_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_lffs_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_lffs_reg1[5]), + .Q(rxeq_lffs_reg2[5]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + rxeq_new_txcoeff_req_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_new_txcoeff_req), + .Q(rxeq_new_txcoeff_req_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hA8FFA800)) + \rxeq_preset[0]_i_1__2 + (.I0(rxeq_preset_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(\rxeq_preset[2]_i_2__2_n_0 ), + .I4(\rxeq_preset_reg_n_0_[0] ), + .O(\rxeq_preset[0]_i_1__2_n_0 )); + LUT5 #( + .INIT(32'hA8FFA800)) + \rxeq_preset[1]_i_1__2 + (.I0(rxeq_preset_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(\rxeq_preset[2]_i_2__2_n_0 ), + .I4(\rxeq_preset_reg_n_0_[1] ), + .O(\rxeq_preset[1]_i_1__2_n_0 )); + LUT5 #( + .INIT(32'hA8FFA800)) + \rxeq_preset[2]_i_1__2 + (.I0(rxeq_preset_reg2[2]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(\rxeq_preset[2]_i_2__2_n_0 ), + .I4(\rxeq_preset_reg_n_0_[2] ), + .O(\rxeq_preset[2]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF0002)) + \rxeq_preset[2]_i_2__2 + (.I0(\rxeq_preset[2]_i_3__2_n_0 ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I3(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .I4(rxeq_adapt_done_reg_i_2__2_n_0), + .I5(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .O(\rxeq_preset[2]_i_2__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair186" *) + LUT2 #( + .INIT(4'h1)) + \rxeq_preset[2]_i_3__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\rxeq_preset[2]_i_3__2_n_0 )); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_preset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_preset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_preset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_reg1[0]), + .Q(rxeq_preset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_reg1[1]), + .Q(rxeq_preset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_preset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_reg1[2]), + .Q(rxeq_preset_reg2[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_preset_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxeq_preset[0]_i_1__2_n_0 ), + .Q(\rxeq_preset_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_preset_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxeq_preset[1]_i_1__2_n_0 ), + .Q(\rxeq_preset_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_preset_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxeq_preset[2]_i_1__2_n_0 ), + .Q(\rxeq_preset_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + rxeq_preset_valid_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .Q(rxeq_preset_valid), + .R(RST_CPLLRESET)); + pcie_7x_0_pcie_7x_0_rxeq_scan rxeq_scan_i + (.D({rxeq_scan_i_n_0,rxeq_scan_i_n_1,rxeq_scan_i_n_2}), + .\FSM_onehot_fsm_rx_reg[5] ({\rxeq_cnt_reg_n_0_[2] ,\rxeq_cnt_reg_n_0_[1] ,\rxeq_cnt_reg_n_0_[0] }), + .Q({\FSM_onehot_fsm_rx_reg_n_0_[6] ,\FSM_onehot_fsm_rx_reg_n_0_[5] ,\FSM_onehot_fsm_rx_reg_n_0_[4] ,\FSM_onehot_fsm_rx_reg_n_0_[2] ,\FSM_onehot_fsm_rx_reg_n_0_[1] }), + .RST_CPLLRESET(RST_CPLLRESET), + .USER_RXEQ_ADAPT_DONE(USER_RXEQ_ADAPT_DONE), + .adapt_done_reg_0(rxeq_scan_i_n_4), + .\fs_reg1_reg[5]_0 ({\rxeq_fs_reg_n_0_[5] ,\rxeq_fs_reg_n_0_[4] ,\rxeq_fs_reg_n_0_[3] ,\rxeq_fs_reg_n_0_[2] ,\rxeq_fs_reg_n_0_[1] ,\rxeq_fs_reg_n_0_[0] }), + .\lf_reg1_reg[5]_0 ({\rxeq_lf_reg_n_0_[5] ,\rxeq_lf_reg_n_0_[4] ,\rxeq_lf_reg_n_0_[3] ,\rxeq_lf_reg_n_0_[2] ,\rxeq_lf_reg_n_0_[1] ,\rxeq_lf_reg_n_0_[0] }), + .new_txcoeff_done_reg_0(rxeq_scan_i_n_5), + .new_txcoeff_req_reg1_reg_0(rxeq_new_txcoeff_req_reg_n_0), + .out(rxeq_control_reg2), + .pipe_pclk_in(pipe_pclk_in), + .\preset_reg1_reg[2]_0 ({\rxeq_preset_reg_n_0_[2] ,\rxeq_preset_reg_n_0_[1] ,\rxeq_preset_reg_n_0_[0] }), + .rxeq_adapt_done_reg(rxeq_adapt_done_i_2__2_n_0), + .rxeq_adapt_done_reg_reg(\FSM_onehot_fsm_rx[1]_i_2__2_n_0 ), + .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_i_2__2_n_0), + .rxeq_adapt_done_reg_reg_1(rxeq_adapt_done_reg_reg_n_0), + .rxeq_new_txcoeff_req(rxeq_new_txcoeff_req), + .rxeq_preset_valid(rxeq_preset_valid), + .\txcoeff_reg1_reg[17]_0 ({\rxeq_txcoeff_reg_n_0_[17] ,\rxeq_txcoeff_reg_n_0_[16] ,\rxeq_txcoeff_reg_n_0_[15] ,\rxeq_txcoeff_reg_n_0_[14] ,\rxeq_txcoeff_reg_n_0_[13] ,\rxeq_txcoeff_reg_n_0_[12] ,\rxeq_txcoeff_reg_n_0_[11] ,\rxeq_txcoeff_reg_n_0_[10] ,\rxeq_txcoeff_reg_n_0_[9] ,\rxeq_txcoeff_reg_n_0_[8] ,\rxeq_txcoeff_reg_n_0_[7] ,\rxeq_txcoeff_reg_n_0_[6] ,\rxeq_txcoeff_reg_n_0_[5] ,\rxeq_txcoeff_reg_n_0_[4] ,\rxeq_txcoeff_reg_n_0_[3] ,\rxeq_txcoeff_reg_n_0_[2] ,\rxeq_txcoeff_reg_n_0_[1] ,\rxeq_txcoeff_reg_n_0_[0] }), + .\txpreset_reg1_reg[3]_0 ({\rxeq_txpreset_reg_n_0_[3] ,\rxeq_txpreset_reg_n_0_[2] ,\rxeq_txpreset_reg_n_0_[1] ,\rxeq_txpreset_reg_n_0_[0] })); + (* SOFT_HLUTNM = "soft_lutpair187" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[0]_i_1__2 + (.I0(\rxeq_txcoeff_reg_n_0_[6] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[0])); + (* SOFT_HLUTNM = "soft_lutpair192" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[10]_i_1__2 + (.I0(\rxeq_txcoeff_reg_n_0_[16] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[10])); + (* SOFT_HLUTNM = "soft_lutpair192" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[11]_i_1__2 + (.I0(\rxeq_txcoeff_reg_n_0_[17] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[11])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[12]_i_1__2 + (.I0(txeq_deemph_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[12])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[13]_i_1__2 + (.I0(txeq_deemph_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[13])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[14]_i_1__2 + (.I0(txeq_deemph_reg2[2]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[14])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[15]_i_1__2 + (.I0(txeq_deemph_reg2[3]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[15])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[16]_i_1__2 + (.I0(txeq_deemph_reg2[4]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[16])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[17]_i_1__2 + (.I0(txeq_deemph_reg2[5]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[17])); + (* SOFT_HLUTNM = "soft_lutpair187" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[1]_i_1__2 + (.I0(\rxeq_txcoeff_reg_n_0_[7] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[1])); + (* SOFT_HLUTNM = "soft_lutpair188" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[2]_i_1__2 + (.I0(\rxeq_txcoeff_reg_n_0_[8] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[2])); + (* SOFT_HLUTNM = "soft_lutpair188" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[3]_i_1__2 + (.I0(\rxeq_txcoeff_reg_n_0_[9] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[3])); + (* SOFT_HLUTNM = "soft_lutpair189" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[4]_i_1__2 + (.I0(\rxeq_txcoeff_reg_n_0_[10] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[4])); + (* SOFT_HLUTNM = "soft_lutpair189" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[5]_i_1__2 + (.I0(\rxeq_txcoeff_reg_n_0_[11] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[5])); + (* SOFT_HLUTNM = "soft_lutpair190" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[6]_i_1__2 + (.I0(\rxeq_txcoeff_reg_n_0_[12] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[6])); + (* SOFT_HLUTNM = "soft_lutpair190" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[7]_i_1__2 + (.I0(\rxeq_txcoeff_reg_n_0_[13] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[7])); + (* SOFT_HLUTNM = "soft_lutpair191" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[8]_i_1__2 + (.I0(\rxeq_txcoeff_reg_n_0_[14] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[8])); + (* SOFT_HLUTNM = "soft_lutpair191" *) + LUT3 #( + .INIT(8'hA8)) + \rxeq_txcoeff[9]_i_1__2 + (.I0(\rxeq_txcoeff_reg_n_0_[15] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txcoeff[9])); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[0]), + .Q(\rxeq_txcoeff_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[10] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[10]), + .Q(\rxeq_txcoeff_reg_n_0_[10] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[11] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[11]), + .Q(\rxeq_txcoeff_reg_n_0_[11] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[12] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[12]), + .Q(\rxeq_txcoeff_reg_n_0_[12] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[13] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[13]), + .Q(\rxeq_txcoeff_reg_n_0_[13] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[14] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[14]), + .Q(\rxeq_txcoeff_reg_n_0_[14] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[15] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[15]), + .Q(\rxeq_txcoeff_reg_n_0_[15] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[16] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[16]), + .Q(\rxeq_txcoeff_reg_n_0_[16] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[17] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[17]), + .Q(\rxeq_txcoeff_reg_n_0_[17] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[1]), + .Q(\rxeq_txcoeff_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[2]), + .Q(\rxeq_txcoeff_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[3]), + .Q(\rxeq_txcoeff_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[4] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[4]), + .Q(\rxeq_txcoeff_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[5] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[5]), + .Q(\rxeq_txcoeff_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[6] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[6]), + .Q(\rxeq_txcoeff_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[7] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[7]), + .Q(\rxeq_txcoeff_reg_n_0_[7] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[8] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[8]), + .Q(\rxeq_txcoeff_reg_n_0_[8] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txcoeff_reg[9] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txcoeff[9]), + .Q(\rxeq_txcoeff_reg_n_0_[9] ), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[0]_i_1__2 + (.I0(rxeq_txpreset_reg2[0]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[0])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[1]_i_1__2 + (.I0(rxeq_txpreset_reg2[1]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[1])); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[2]_i_1__2 + (.I0(rxeq_txpreset_reg2[2]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[2])); + LUT5 #( + .INIT(32'hFFFFF404)) + \rxeq_txpreset[3]_i_1__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[6] ), + .I1(\rxeq_txpreset[3]_i_3__2_n_0 ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .I3(rxeq_control_reg2[1]), + .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .O(\rxeq_txpreset[3]_i_1__2_n_0 )); + LUT3 #( + .INIT(8'hA8)) + \rxeq_txpreset[3]_i_2__2 + (.I0(rxeq_txpreset_reg2[3]), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ), + .O(rxeq_txpreset[3])); + LUT3 #( + .INIT(8'h01)) + \rxeq_txpreset[3]_i_3__2 + (.I0(\FSM_onehot_fsm_rx_reg_n_0_[2] ), + .I1(\FSM_onehot_fsm_rx_reg_n_0_[4] ), + .I2(\FSM_onehot_fsm_rx_reg_n_0_[5] ), + .O(\rxeq_txpreset[3]_i_3__2_n_0 )); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_txpreset_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[0]), + .Q(rxeq_txpreset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[1]), + .Q(rxeq_txpreset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[2]), + .Q(rxeq_txpreset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_txpreset_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_txpreset_reg1[3]), + .Q(rxeq_txpreset_reg2[3]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[0] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txpreset[0]), + .Q(\rxeq_txpreset_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[1] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txpreset[1]), + .Q(\rxeq_txpreset_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[2] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txpreset[2]), + .Q(\rxeq_txpreset_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxeq_txpreset_reg[3] + (.C(pipe_pclk_in), + .CE(\rxeq_txpreset[3]_i_1__2_n_0 ), + .D(rxeq_txpreset[3]), + .Q(\rxeq_txpreset_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_en_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_en_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_en_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_en_reg1), + .Q(rxeq_user_en_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_mode_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_mode_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_user_mode_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_mode_reg1), + .Q(rxeq_user_mode_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg1_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxeq_user_txcoeff_reg1[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[0]), + .Q(rxeq_user_txcoeff_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[10]), + .Q(rxeq_user_txcoeff_reg2[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[11]), + .Q(rxeq_user_txcoeff_reg2[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[12]), + .Q(rxeq_user_txcoeff_reg2[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[13]), + .Q(rxeq_user_txcoeff_reg2[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[14]), + .Q(rxeq_user_txcoeff_reg2[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[15]), + .Q(rxeq_user_txcoeff_reg2[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[16]), + .Q(rxeq_user_txcoeff_reg2[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[17]), + .Q(rxeq_user_txcoeff_reg2[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[1]), + .Q(rxeq_user_txcoeff_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[2]), + .Q(rxeq_user_txcoeff_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[3]), + .Q(rxeq_user_txcoeff_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[4]), + .Q(rxeq_user_txcoeff_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[5]), + .Q(rxeq_user_txcoeff_reg2[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[6]), + .Q(rxeq_user_txcoeff_reg2[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[7]), + .Q(rxeq_user_txcoeff_reg2[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[8]), + .Q(rxeq_user_txcoeff_reg2[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxeq_user_txcoeff_reg2_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_user_txcoeff_reg1[9]), + .Q(rxeq_user_txcoeff_reg2[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_control_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_control_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_control_reg1[0]), + .Q(txeq_control_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_control_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_control_reg1[1]), + .Q(txeq_control_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \txeq_deemph_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[0]), + .S(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_deemph_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \txeq_deemph_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[0]), + .Q(txeq_deemph_reg2[0]), + .S(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[1]), + .Q(txeq_deemph_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[2]), + .Q(txeq_deemph_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[3]), + .Q(txeq_deemph_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[4]), + .Q(txeq_deemph_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_deemph_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_deemph_reg1[5]), + .Q(txeq_deemph_reg2[5]), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h00001000)) + \txeq_preset[0]_i_1__2 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[2]), + .I2(txeq_preset_reg2[0]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[1]), + .O(p_0_out[0])); + LUT5 #( + .INIT(32'hABEAABAF)) + \txeq_preset[10]_i_1__2 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[2]), + .I2(txeq_preset_reg2[0]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[1]), + .O(p_0_out[10])); + LUT5 #( + .INIT(32'hFFFF200D)) + \txeq_preset[11]_i_1__2 + (.I0(txeq_preset_reg2[1]), + .I1(txeq_preset_reg2[3]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[0]), + .I4(RST_CPLLRESET), + .O(p_0_out[11])); + LUT5 #( + .INIT(32'h01151110)) + \txeq_preset[12]_i_1__2 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[3]), + .I2(txeq_preset_reg2[1]), + .I3(txeq_preset_reg2[2]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[12])); + LUT5 #( + .INIT(32'h01000010)) + \txeq_preset[13]_i_1__2 + (.I0(txeq_preset_reg2[2]), + .I1(RST_CPLLRESET), + .I2(txeq_preset_reg2[0]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[1]), + .O(p_0_out[13])); + LUT5 #( + .INIT(32'h01000010)) + \txeq_preset[14]_i_1__2 + (.I0(txeq_preset_reg2[2]), + .I1(RST_CPLLRESET), + .I2(txeq_preset_reg2[3]), + .I3(txeq_preset_reg2[1]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[14])); + LUT4 #( + .INIT(16'hF0F1)) + \txeq_preset[15]_i_1__2 + (.I0(txeq_preset_reg2[2]), + .I1(txeq_preset_reg2[1]), + .I2(RST_CPLLRESET), + .I3(txeq_preset_reg2[3]), + .O(p_0_out[15])); + LUT4 #( + .INIT(16'h0006)) + \txeq_preset[16]_i_1__2 + (.I0(txeq_preset_reg2[3]), + .I1(txeq_preset_reg2[0]), + .I2(txeq_preset_reg2[2]), + .I3(RST_CPLLRESET), + .O(p_0_out[16])); + LUT4 #( + .INIT(16'hAABA)) + \txeq_preset[17]_i_1__2 + (.I0(RST_CPLLRESET), + .I1(fsm_tx[0]), + .I2(fsm_tx[1]), + .I3(fsm_tx[2]), + .O(\txeq_preset[17]_i_1__2_n_0 )); + LUT5 #( + .INIT(32'hFFFF400D)) + \txeq_preset[17]_i_2__2 + (.I0(txeq_preset_reg2[3]), + .I1(txeq_preset_reg2[1]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[0]), + .I4(RST_CPLLRESET), + .O(p_0_out[17])); + LUT5 #( + .INIT(32'h00001004)) + \txeq_preset[1]_i_1__2 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[3]), + .I2(txeq_preset_reg2[1]), + .I3(txeq_preset_reg2[2]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[1])); + LUT4 #( + .INIT(16'h0E00)) + \txeq_preset[2]_i_1__2 + (.I0(txeq_preset_reg2[2]), + .I1(txeq_preset_reg2[0]), + .I2(RST_CPLLRESET), + .I3(txeq_preset_reg2[3]), + .O(p_0_out[2])); + LUT5 #( + .INIT(32'h01440140)) + \txeq_preset[3]_i_1__2 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[2]), + .I2(txeq_preset_reg2[1]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[0]), + .O(\txeq_preset[3]_i_1__2_n_0 )); + LUT5 #( + .INIT(32'h00001400)) + \txeq_preset[7]_i_1__2 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[0]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[1]), + .I4(txeq_preset_reg2[3]), + .O(\txeq_preset[7]_i_1__2_n_0 )); + LUT5 #( + .INIT(32'hAAAFBEAF)) + \txeq_preset[8]_i_1__2 + (.I0(RST_CPLLRESET), + .I1(txeq_preset_reg2[0]), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[1]), + .I4(txeq_preset_reg2[3]), + .O(p_0_out[8])); + LUT5 #( + .INIT(32'hCCFCCFCD)) + \txeq_preset[9]_i_1__2 + (.I0(txeq_preset_reg2[1]), + .I1(RST_CPLLRESET), + .I2(txeq_preset_reg2[2]), + .I3(txeq_preset_reg2[3]), + .I4(txeq_preset_reg2[0]), + .O(p_0_out[9])); + (* SOFT_HLUTNM = "soft_lutpair184" *) + LUT3 #( + .INIT(8'h04)) + txeq_preset_done_i_1__2 + (.I0(fsm_tx[2]), + .I1(fsm_tx[1]), + .I2(fsm_tx[0]), + .O(txeq_preset_done_i_1__2_n_0)); + FDRE #( + .INIT(1'b0)) + txeq_preset_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_done_i_1__2_n_0), + .Q(txeq_preset_done), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txeq_preset_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[0]), + .Q(txeq_preset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[1]), + .Q(txeq_preset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[2]), + .Q(txeq_preset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txeq_preset_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_preset_reg1[3]), + .Q(txeq_preset_reg2[3]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[0] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(p_0_out[0]), + .Q(\txeq_preset_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[10] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(p_0_out[10]), + .Q(\txeq_preset_reg_n_0_[10] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[11] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(p_0_out[11]), + .Q(\txeq_preset_reg_n_0_[11] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[12] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(p_0_out[12]), + .Q(\txeq_preset_reg_n_0_[12] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[13] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(p_0_out[13]), + .Q(\txeq_preset_reg_n_0_[13] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[14] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(p_0_out[14]), + .Q(\txeq_preset_reg_n_0_[14] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[15] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(p_0_out[15]), + .Q(\txeq_preset_reg_n_0_[15] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[16] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(p_0_out[16]), + .Q(\txeq_preset_reg_n_0_[16] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[17] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(p_0_out[17]), + .Q(\txeq_preset_reg_n_0_[17] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[1] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(p_0_out[1]), + .Q(\txeq_preset_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[2] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(p_0_out[2]), + .Q(\txeq_preset_reg_n_0_[2] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[3] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(\txeq_preset[3]_i_1__2_n_0 ), + .Q(\txeq_preset_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[7] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(\txeq_preset[7]_i_1__2_n_0 ), + .Q(\txeq_preset_reg_n_0_[7] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[8] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(p_0_out[8]), + .Q(\txeq_preset_reg_n_0_[8] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \txeq_preset_reg[9] + (.C(pipe_pclk_in), + .CE(\txeq_preset[17]_i_1__2_n_0 ), + .D(p_0_out[9]), + .Q(\txeq_preset_reg_n_0_[9] ), + .R(1'b0)); + LUT5 #( + .INIT(32'h45404040)) + \txeq_txcoeff[0]_i_1__2 + (.I0(fsm_tx[2]), + .I1(\txeq_txcoeff[0]_i_2__2_n_0 ), + .I2(fsm_tx[1]), + .I3(fsm_tx[0]), + .I4(\txeq_txcoeff_reg_n_0_[6] ), + .O(\txeq_txcoeff[0]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[0]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[6] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[7] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[0] ), + .O(\txeq_txcoeff[0]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[10]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[9] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[10]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[16] ), + .O(\txeq_txcoeff[10]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[10]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[16] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[17] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[10] ), + .O(\txeq_txcoeff[10]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[11]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[10] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[11]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[17] ), + .O(\txeq_txcoeff[11]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[11]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[17] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[18] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[11] ), + .O(\txeq_txcoeff[11]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[12]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[11] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[12]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[18] ), + .O(\txeq_txcoeff[12]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[12]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[18] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[0]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[12] ), + .O(\txeq_txcoeff[12]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[13]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[12] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[13]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[0]), + .O(\txeq_txcoeff[13]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[13]_i_2__2 + (.I0(txeq_deemph_reg2[0]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[1]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[13] ), + .O(\txeq_txcoeff[13]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[14]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[13] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[14]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[1]), + .O(\txeq_txcoeff[14]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[14]_i_2__2 + (.I0(txeq_deemph_reg2[1]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[2]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[14] ), + .O(\txeq_txcoeff[14]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[15]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[14] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[15]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[2]), + .O(\txeq_txcoeff[15]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[15]_i_2__2 + (.I0(txeq_deemph_reg2[2]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[3]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[15] ), + .O(\txeq_txcoeff[15]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[16]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[15] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[16]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[3]), + .O(\txeq_txcoeff[16]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[16]_i_2__2 + (.I0(txeq_deemph_reg2[3]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[4]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[16] ), + .O(\txeq_txcoeff[16]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[17]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[16] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[17]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(txeq_deemph_reg2[4]), + .O(\txeq_txcoeff[17]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[17]_i_2__2 + (.I0(txeq_deemph_reg2[4]), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(txeq_deemph_reg2[5]), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[17] ), + .O(\txeq_txcoeff[17]_i_2__2_n_0 )); + LUT5 #( + .INIT(32'hFF040FFF)) + \txeq_txcoeff[18]_i_1__2 + (.I0(txeq_control_reg2[0]), + .I1(txeq_control_reg2[1]), + .I2(fsm_tx[2]), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .O(txeq_txcoeff)); + LUT6 #( + .INIT(64'h22F3220022002200)) + \txeq_txcoeff[18]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[17] ), + .I1(fsm_tx[1]), + .I2(\txeq_txcoeff[18]_i_3__2_n_0 ), + .I3(fsm_tx[2]), + .I4(txeq_deemph_reg2[5]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[18]_i_2__2_n_0 )); + LUT2 #( + .INIT(4'hB)) + \txeq_txcoeff[18]_i_3__2 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .O(\txeq_txcoeff[18]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[1]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[0] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[1]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[7] ), + .O(\txeq_txcoeff[1]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[1]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[7] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[8] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[1] ), + .O(\txeq_txcoeff[1]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[2]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[1] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[2]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[8] ), + .O(\txeq_txcoeff[2]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[2]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[8] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[9] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[2] ), + .O(\txeq_txcoeff[2]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[3]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[2] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[3]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[9] ), + .O(\txeq_txcoeff[3]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[3]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[9] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[10] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[3] ), + .O(\txeq_txcoeff[3]_i_2__2_n_0 )); + LUT4 #( + .INIT(16'h2F20)) + \txeq_txcoeff[4]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[3] ), + .I1(fsm_tx[1]), + .I2(fsm_tx[2]), + .I3(\txeq_txcoeff[4]_i_2__2_n_0 ), + .O(\txeq_txcoeff[4]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hCACCCCCC00000000)) + \txeq_txcoeff[4]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[11] ), + .I1(\txeq_txcoeff_reg_n_0_[10] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I4(fsm_tx[1]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[4]_i_2__2_n_0 )); + LUT4 #( + .INIT(16'h2F20)) + \txeq_txcoeff[5]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[4] ), + .I1(fsm_tx[1]), + .I2(fsm_tx[2]), + .I3(\txeq_txcoeff[5]_i_2__2_n_0 ), + .O(\txeq_txcoeff[5]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hCACCCCCC00000000)) + \txeq_txcoeff[5]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[12] ), + .I1(\txeq_txcoeff_reg_n_0_[11] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I4(fsm_tx[1]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[5]_i_2__2_n_0 )); + LUT4 #( + .INIT(16'h2F20)) + \txeq_txcoeff[6]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[5] ), + .I1(fsm_tx[1]), + .I2(fsm_tx[2]), + .I3(\txeq_txcoeff[6]_i_2__2_n_0 ), + .O(\txeq_txcoeff[6]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hCACCCCCC00000000)) + \txeq_txcoeff[6]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[13] ), + .I1(\txeq_txcoeff_reg_n_0_[12] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I4(fsm_tx[1]), + .I5(fsm_tx[0]), + .O(\txeq_txcoeff[6]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[7]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[6] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[7]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[13] ), + .O(\txeq_txcoeff[7]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[7]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[13] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[14] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[7] ), + .O(\txeq_txcoeff[7]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[8]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[7] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[8]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[14] ), + .O(\txeq_txcoeff[8]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[8]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[14] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[15] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[8] ), + .O(\txeq_txcoeff[8]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h30BB308830883088)) + \txeq_txcoeff[9]_i_1__2 + (.I0(\txeq_txcoeff_reg_n_0_[8] ), + .I1(fsm_tx[2]), + .I2(\txeq_txcoeff[9]_i_2__2_n_0 ), + .I3(fsm_tx[1]), + .I4(fsm_tx[0]), + .I5(\txeq_txcoeff_reg_n_0_[15] ), + .O(\txeq_txcoeff[9]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hBA8AFFFFBA8A0000)) + \txeq_txcoeff[9]_i_2__2 + (.I0(\txeq_txcoeff_reg_n_0_[15] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I3(\txeq_txcoeff_reg_n_0_[16] ), + .I4(fsm_tx[0]), + .I5(\txeq_preset_reg_n_0_[9] ), + .O(\txeq_txcoeff[9]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h000004000F000400)) + \txeq_txcoeff_cnt[0]_i_1__2 + (.I0(txeq_control_reg2[0]), + .I1(txeq_control_reg2[1]), + .I2(fsm_tx[2]), + .I3(fsm_tx[0]), + .I4(fsm_tx[1]), + .I5(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .O(txeq_txcoeff_cnt[0])); + (* SOFT_HLUTNM = "soft_lutpair184" *) + LUT5 #( + .INIT(32'h00006000)) + \txeq_txcoeff_cnt[1]_i_1__2 + (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .I2(fsm_tx[0]), + .I3(fsm_tx[1]), + .I4(fsm_tx[2]), + .O(txeq_txcoeff_cnt[1])); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_txcoeff_cnt[0]), + .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txeq_txcoeff_cnt[1]), + .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[0] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[0]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[0] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[10] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[10]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[10] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[11] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[11]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[11] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[12] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[12]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[12] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[13] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[13]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[13] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[14] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[14]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[14] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[15] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[15]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[15] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[16] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[16]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[16] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[17] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[17]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[17] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[18] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[18]_i_2__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[18] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[1] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[1]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[1] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[2] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[2]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[3] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[3]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[4] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[4]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[5] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[5]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[5] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[6] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[6]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[7] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[7]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[7] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[8] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[8]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[8] ), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txeq_txcoeff_reg[9] + (.C(pipe_pclk_in), + .CE(txeq_txcoeff), + .D(\txeq_txcoeff[9]_i_1__2_n_0 ), + .Q(\txeq_txcoeff_reg_n_0_[9] ), + .R(RST_CPLLRESET)); +endmodule + +module pcie_7x_0_pcie_7x_0_pipe_rate + (SYNC_TXSYNC_START, + rxchbonden_0, + USER_RATE_GEN3, + RATE_DRP_START, + RATE_DRP_X16X20_MODE, + RATE_DRP_X16, + USER_RATE_RXSYNC, + SYNC_RXSYNC_START, + USER_RATE_DONE, + USER_RESETOVRD_START, + SYNC_RATE_IDLE, + rate_txpmareset_0, + RXSYSCLKSEL, + pipe_pclk_sel_out, + RXRATE, + QRST_QPLLPD_IN, + rate_cpllpd_0, + QRST_QPLLRESET_IN, + rate_cpllreset_0, + RST_TXSYNC_START, + RST_CPLLRESET, + pipe_pclk_in, + \rate_in_reg1_reg[0]_0 , + RST_IDLE, + QRST_CPLLLOCK, + RATE_QPLLLOCK, + RATE_DRP_DONE, + pipe_mmcm_lock_in, + RATE_PHYSTATUS, + USER_TXRESETDONE, + USER_RXRESETDONE, + RATE_TXRATEDONE, + RATE_RXRATEDONE, + RATE_TXSYNC_DONE, + user_active_lane_0, + out, + \fsm[0]_i_9_0 ); + output SYNC_TXSYNC_START; + output rxchbonden_0; + output USER_RATE_GEN3; + output RATE_DRP_START; + output RATE_DRP_X16X20_MODE; + output RATE_DRP_X16; + output USER_RATE_RXSYNC; + output SYNC_RXSYNC_START; + output USER_RATE_DONE; + output USER_RESETOVRD_START; + output SYNC_RATE_IDLE; + output rate_txpmareset_0; + output [0:0]RXSYSCLKSEL; + output [0:0]pipe_pclk_sel_out; + output [0:0]RXRATE; + output [0:0]QRST_QPLLPD_IN; + output rate_cpllpd_0; + output [0:0]QRST_QPLLRESET_IN; + output rate_cpllreset_0; + input RST_TXSYNC_START; + input RST_CPLLRESET; + input pipe_pclk_in; + input [0:0]\rate_in_reg1_reg[0]_0 ; + input RST_IDLE; + input [0:0]QRST_CPLLLOCK; + input RATE_QPLLLOCK; + input RATE_DRP_DONE; + input pipe_mmcm_lock_in; + input RATE_PHYSTATUS; + input USER_TXRESETDONE; + input USER_RXRESETDONE; + input RATE_TXRATEDONE; + input RATE_RXRATEDONE; + input RATE_TXSYNC_DONE; + input user_active_lane_0; + input out; + input \fsm[0]_i_9_0 ; + + wire [0:0]QRST_CPLLLOCK; + wire [0:0]QRST_QPLLPD_IN; + wire [0:0]QRST_QPLLRESET_IN; + wire RATE_DRP_DONE; + wire RATE_DRP_START; + wire RATE_DRP_X16; + wire RATE_DRP_X16X20_MODE; + wire RATE_PHYSTATUS; + wire RATE_QPLLLOCK; + wire RATE_RXRATEDONE; + wire RATE_TXRATEDONE; + wire RATE_TXSYNC_DONE; + wire RST_CPLLRESET; + wire RST_IDLE; + wire RST_TXSYNC_START; + wire [0:0]RXRATE; + wire [0:0]RXSYSCLKSEL; + wire SYNC_RATE_IDLE; + wire SYNC_RXSYNC_START; + wire SYNC_TXSYNC_START; + wire USER_RATE_DONE; + wire USER_RATE_GEN3; + wire USER_RATE_RXSYNC; + wire USER_RESETOVRD_START; + wire USER_RXRESETDONE; + wire USER_TXRESETDONE; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire cplllock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire cplllock_reg2; + wire cpllpd_i_1_n_0; + wire cpllreset_i_1__0_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg2; + wire drp_start_i_1_n_0; + wire drp_x16_i_1_n_0; + wire drp_x16x20_mode_i_1_n_0; + wire [4:0]fsm; + wire fsm1; + wire \fsm[0]_i_10_n_0 ; + wire \fsm[0]_i_11_n_0 ; + wire \fsm[0]_i_12_n_0 ; + wire \fsm[0]_i_2_n_0 ; + wire \fsm[0]_i_3_n_0 ; + wire \fsm[0]_i_4_n_0 ; + wire \fsm[0]_i_5_n_0 ; + wire \fsm[0]_i_7_n_0 ; + wire \fsm[0]_i_8_n_0 ; + wire \fsm[0]_i_9_0 ; + wire \fsm[0]_i_9_n_0 ; + wire \fsm[1]_i_2_n_0 ; + wire \fsm[1]_i_3_n_0 ; + wire \fsm[1]_i_4_n_0 ; + wire \fsm[1]_i_5_n_0 ; + wire \fsm[1]_i_6_n_0 ; + wire \fsm[1]_i_7_n_0 ; + wire \fsm[1]_i_8_n_0 ; + wire \fsm[2]_i_2_n_0 ; + wire \fsm[2]_i_3_n_0 ; + wire \fsm[2]_i_4_n_0 ; + wire \fsm[2]_i_5_n_0 ; + wire \fsm[2]_i_6_n_0 ; + wire \fsm[3]_i_2_n_0 ; + wire \fsm[3]_i_3_n_0 ; + wire \fsm[3]_i_4_n_0 ; + wire \fsm[3]_i_6_n_0 ; + wire \fsm[4]_i_2_n_0 ; + wire \fsm[4]_i_3_n_0 ; + wire \fsm_reg_n_0_[0] ; + wire \fsm_reg_n_0_[1] ; + wire \fsm_reg_n_0_[2] ; + wire \fsm_reg_n_0_[3] ; + wire \fsm_reg_n_0_[4] ; + wire gen3_exit; + wire gen3_exit_i_1_n_0; + wire gen3_exit_i_2_n_0; + wire gen3_i_1_n_0; + wire gen3_i_2_n_0; + wire gen3_i_3_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2; + wire out; + wire [3:0]p_0_in__0; + wire pclk_sel_i_1_n_0; + wire pclk_sel_i_2_n_0; + wire phystatus; + wire phystatus_i_1_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire phystatus_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire phystatus_reg2; + wire pipe_mmcm_lock_in; + wire pipe_pclk_in; + wire [0:0]pipe_pclk_sel_out; + wire pll_lock; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg2; + wire qpllpd; + wire qpllpd_i_1__0_n_0; + wire qpllreset; + wire qpllreset_i_1__0_n_0; + wire rate_cpllpd_0; + wire rate_cpllreset_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_in_reg1; + wire [0:0]\rate_in_reg1_reg[0]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_in_reg2; + wire \rate_out[0]_i_1_n_0 ; + wire \rate_out[0]_i_2_n_0 ; + wire rate_txpmareset_0; + wire ratedone; + wire ratedone_i_1_n_0; + wire ratedone_i_2_n_0; + wire ratedone_i_3_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_done_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg2; + wire rxchbonden_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxpmaresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxpmaresetdone_reg2; + wire rxratedone; + wire rxratedone_i_1_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxratedone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxratedone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_done_reg2; + wire \sysclksel[0]_i_1_n_0 ; + wire \sysclksel[0]_i_2_n_0 ; + wire \txdata_wait_cnt[3]_i_2_n_0 ; + wire \txdata_wait_cnt[3]_i_3_n_0 ; + wire [3:0]txdata_wait_cnt_reg; + wire txpmareset0; + wire txpmareset_i_1_n_0; + wire txpmareset_i_2_n_0; + wire txratedone; + wire txratedone_i_1_n_0; + wire txratedone_i_2_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txratedone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txratedone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_done_reg2; + wire user_active_lane_0; + + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE cplllock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(QRST_CPLLLOCK), + .Q(cplllock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE cplllock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cplllock_reg1), + .Q(cplllock_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0400FFFF04000000)) + cpllpd_i_1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllpd), + .I5(rate_cpllpd_0), + .O(cpllpd_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT5 #( + .INIT(32'h80000900)) + cpllpd_i_2 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[2] ), + .O(qpllpd)); + FDRE #( + .INIT(1'b0)) + cpllpd_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cpllpd_i_1_n_0), + .Q(rate_cpllpd_0), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0400FFFF04000000)) + cpllreset_i_1__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllreset), + .I5(rate_cpllreset_0), + .O(cpllreset_i_1__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT5 #( + .INIT(32'h80001004)) + cpllreset_i_2__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm_reg_n_0_[0] ), + .O(qpllreset)); + FDRE #( + .INIT(1'b0)) + cpllreset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cpllreset_i_1__0_n_0), + .Q(rate_cpllreset_0), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE drp_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_DRP_DONE), + .Q(drp_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE drp_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_done_reg1), + .Q(drp_done_reg2), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT5 #( + .INIT(32'h08420100)) + drp_start_i_1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[0] ), + .O(drp_start_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + drp_start_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_start_i_1_n_0), + .Q(RATE_DRP_START), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT5 #( + .INIT(32'h20100014)) + drp_x16_i_1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .O(drp_x16_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + drp_x16_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_x16_i_1_n_0), + .Q(RATE_DRP_X16), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT5 #( + .INIT(32'h20080074)) + drp_x16x20_mode_i_1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[1] ), + .O(drp_x16x20_mode_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + drp_x16x20_mode_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_x16x20_mode_i_1_n_0), + .Q(RATE_DRP_X16X20_MODE), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT5 #( + .INIT(32'hFFFF3210)) + \fsm[0]_i_1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm[0]_i_2_n_0 ), + .I3(\fsm[0]_i_3_n_0 ), + .I4(\fsm[0]_i_4_n_0 ), + .O(fsm[0])); + LUT6 #( + .INIT(64'h0901595100000000)) + \fsm[0]_i_10 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(rxsync_done_reg2), + .I4(txsync_done_reg2), + .I5(\fsm_reg_n_0_[3] ), + .O(\fsm[0]_i_10_n_0 )); + LUT6 #( + .INIT(64'h1101111101000110)) + \fsm[0]_i_11 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(rxpmaresetdone_reg2), + .I5(drp_done_reg2), + .O(\fsm[0]_i_11_n_0 )); + LUT5 #( + .INIT(32'h20202320)) + \fsm[0]_i_12 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(mmcm_lock_reg2), + .I4(rxpmaresetdone_reg2), + .O(\fsm[0]_i_12_n_0 )); + LUT6 #( + .INIT(64'h0F0F3F3F47444744)) + \fsm[0]_i_2 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm[0]_i_5_n_0 ), + .I4(pll_lock), + .I5(\fsm_reg_n_0_[1] ), + .O(\fsm[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hF3F3AAAAFF00AAAA)) + \fsm[0]_i_3 + (.I0(\fsm[0]_i_7_n_0 ), + .I1(\fsm_reg_n_0_[0] ), + .I2(drp_done_reg2), + .I3(\fsm[0]_i_8_n_0 ), + .I4(\fsm_reg_n_0_[2] ), + .I5(\fsm_reg_n_0_[1] ), + .O(\fsm[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFF4000000000)) + \fsm[0]_i_4 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm[0]_i_9_n_0 ), + .I3(\fsm[0]_i_10_n_0 ), + .I4(\fsm[0]_i_11_n_0 ), + .I5(\fsm_reg_n_0_[4] ), + .O(\fsm[0]_i_4_n_0 )); + LUT4 #( + .INIT(16'h6FF6)) + \fsm[0]_i_5 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg1[1]), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg1[0]), + .O(\fsm[0]_i_5_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \fsm[0]_i_6 + (.I0(qplllock_reg2), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(cplllock_reg2), + .O(pll_lock)); + LUT6 #( + .INIT(64'hAAAAAAAAEAAAAAAA)) + \fsm[0]_i_7 + (.I0(\fsm[0]_i_12_n_0 ), + .I1(pll_lock), + .I2(rst_idle_reg2), + .I3(drp_done_reg2), + .I4(\fsm_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[0] ), + .O(\fsm[0]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFF5D5500005D55)) + \fsm[0]_i_8 + (.I0(user_active_lane_0), + .I1(txresetdone_reg2), + .I2(phystatus_reg2), + .I3(rxresetdone_reg2), + .I4(\fsm_reg_n_0_[0] ), + .I5(\fsm[1]_i_7_n_0 ), + .O(\fsm[0]_i_8_n_0 )); + LUT5 #( + .INIT(32'h33330FAA)) + \fsm[0]_i_9 + (.I0(drp_done_reg2), + .I1(resetovrd_done_reg2), + .I2(fsm1), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[1] ), + .O(\fsm[0]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFE4FFE4FFE400E4)) + \fsm[1]_i_1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm[1]_i_2_n_0 ), + .I2(\fsm[1]_i_3_n_0 ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm[1]_i_4_n_0 ), + .I5(\fsm[1]_i_5_n_0 ), + .O(fsm[1])); + LUT5 #( + .INIT(32'h3388F0CC)) + \fsm[1]_i_2 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm[1]_i_6_n_0 ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[2] ), + .O(\fsm[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hCC5500000033F000)) + \fsm[1]_i_3 + (.I0(\fsm[1]_i_7_n_0 ), + .I1(drp_done_reg2), + .I2(\fsm[1]_i_8_n_0 ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h000000005FCF0000)) + \fsm[1]_i_4 + (.I0(resetovrd_done_reg2), + .I1(drp_done_reg2), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[3] ), + .O(\fsm[1]_i_4_n_0 )); + LUT6 #( + .INIT(64'h143C547C00000000)) + \fsm[1]_i_5 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(rxsync_done_reg2), + .I4(txsync_done_reg2), + .I5(\fsm_reg_n_0_[3] ), + .O(\fsm[1]_i_5_n_0 )); + LUT6 #( + .INIT(64'h34F7FFFFFFFFFFFF)) + \fsm[1]_i_6 + (.I0(qplllock_reg2), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(cplllock_reg2), + .I4(rst_idle_reg2), + .I5(\fsm_reg_n_0_[0] ), + .O(\fsm[1]_i_6_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \fsm[1]_i_7 + (.I0(txdata_wait_cnt_reg[3]), + .I1(txdata_wait_cnt_reg[1]), + .I2(txdata_wait_cnt_reg[0]), + .I3(txdata_wait_cnt_reg[2]), + .O(\fsm[1]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF04F7FFFF)) + \fsm[1]_i_8 + (.I0(qplllock_reg2), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(cplllock_reg2), + .I4(drp_done_reg2), + .I5(rst_idle_reg2), + .O(\fsm[1]_i_8_n_0 )); + LUT6 #( + .INIT(64'hEAFFAAAAAAAAAAAA)) + \fsm[2]_i_2 + (.I0(\fsm[2]_i_4_n_0 ), + .I1(drp_done_reg2), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFBAAAAAAAAAAAAA)) + \fsm[2]_i_3 + (.I0(\fsm[2]_i_5_n_0 ), + .I1(rxsync_done_reg2), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'h00FA554455005544)) + \fsm[2]_i_4 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm[3]_i_6_n_0 ), + .I2(pll_lock), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[0] ), + .O(\fsm[2]_i_4_n_0 )); + LUT6 #( + .INIT(64'h2000FFFF20000000)) + \fsm[2]_i_5 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(txsync_done_reg2), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm[2]_i_6_n_0 ), + .O(\fsm[2]_i_5_n_0 )); + LUT6 #( + .INIT(64'h1CDC3C3C1CDCFCFC)) + \fsm[2]_i_6 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(resetovrd_done_reg2), + .I4(\fsm_reg_n_0_[1] ), + .I5(fsm1), + .O(\fsm[2]_i_6_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFB0803080)) + \fsm[3]_i_2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(drp_done_reg2), + .I5(\fsm[3]_i_4_n_0 ), + .O(\fsm[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF8880000F888)) + \fsm[3]_i_3 + (.I0(\txdata_wait_cnt[3]_i_2_n_0 ), + .I1(fsm1), + .I2(resetovrd_done_reg2), + .I3(\sysclksel[0]_i_2_n_0 ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm[4]_i_2_n_0 ), + .O(\fsm[3]_i_3_n_0 )); + LUT6 #( + .INIT(64'h00000000EEFF00F0)) + \fsm[3]_i_4 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm[1]_i_8_n_0 ), + .I2(\fsm[3]_i_6_n_0 ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[3]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFF8F8FFF8)) + \fsm[3]_i_5 + (.I0(out), + .I1(\fsm[0]_i_9_0 ), + .I2(ratedone), + .I3(rate_in_reg2[1]), + .I4(rate_in_reg2[0]), + .I5(gen3_exit), + .O(fsm1)); + LUT5 #( + .INIT(32'h00504414)) + \fsm[3]_i_6 + (.I0(\fsm_reg_n_0_[0] ), + .I1(rate_in_reg1[0]), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg1[1]), + .I4(rate_in_reg2[1]), + .O(\fsm[3]_i_6_n_0 )); + LUT6 #( + .INIT(64'hC5F0CFF0C0F0C0F0)) + \fsm[4]_i_1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm[4]_i_2_n_0 ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(drp_done_reg2), + .I5(\fsm[4]_i_3_n_0 ), + .O(fsm[4])); + LUT4 #( + .INIT(16'h26FF)) + \fsm[4]_i_2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(rxsync_done_reg2), + .I3(\fsm_reg_n_0_[2] ), + .O(\fsm[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT2 #( + .INIT(4'h8)) + \fsm[4]_i_3 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[2] ), + .O(\fsm[4]_i_3_n_0 )); + FDSE #( + .INIT(1'b0)) + \fsm_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[0]), + .Q(\fsm_reg_n_0_[0] ), + .S(RST_CPLLRESET)); + FDSE #( + .INIT(1'b0)) + \fsm_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[1]), + .Q(\fsm_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \fsm_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[2]), + .Q(\fsm_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + MUXF7 \fsm_reg[2]_i_1 + (.I0(\fsm[2]_i_2_n_0 ), + .I1(\fsm[2]_i_3_n_0 ), + .O(fsm[2]), + .S(\fsm_reg_n_0_[4] )); + FDRE #( + .INIT(1'b0)) + \fsm_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[3]), + .Q(\fsm_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + MUXF7 \fsm_reg[3]_i_1 + (.I0(\fsm[3]_i_2_n_0 ), + .I1(\fsm[3]_i_3_n_0 ), + .O(fsm[3]), + .S(\fsm_reg_n_0_[4] )); + FDRE #( + .INIT(1'b0)) + \fsm_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[4]), + .Q(\fsm_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h04FF0400)) + gen3_exit_i_1 + (.I0(rate_in_reg2[0]), + .I1(rate_in_reg2[1]), + .I2(\fsm_reg_n_0_[4] ), + .I3(gen3_exit_i_2_n_0), + .I4(gen3_exit), + .O(gen3_exit_i_1_n_0)); + LUT6 #( + .INIT(64'h8000000180000000)) + gen3_exit_i_2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[4] ), + .I5(\fsm[0]_i_5_n_0 ), + .O(gen3_exit_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + gen3_exit_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_exit_i_1_n_0), + .Q(gen3_exit), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h3FFFFFFB00000008)) + gen3_i_1 + (.I0(gen3_i_2_n_0), + .I1(gen3_i_3_n_0), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[4] ), + .I5(USER_RATE_GEN3), + .O(gen3_i_1_n_0)); + LUT2 #( + .INIT(4'h2)) + gen3_i_2 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg2[0]), + .O(gen3_i_2_n_0)); + LUT2 #( + .INIT(4'h8)) + gen3_i_3 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[0] ), + .O(gen3_i_3_n_0)); + FDRE #( + .INIT(1'b0)) + gen3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_i_1_n_0), + .Q(USER_RATE_GEN3), + .R(RST_CPLLRESET)); + LUT1 #( + .INIT(2'h1)) + \gtx_channel.gtxe2_channel_i_i_5 + (.I0(USER_RATE_GEN3), + .O(rxchbonden_0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_mmcm_lock_in), + .Q(mmcm_lock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(mmcm_lock_reg1), + .Q(mmcm_lock_reg2), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h14FF1400)) + pclk_sel_i_1 + (.I0(\fsm_reg_n_0_[4] ), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(pclk_sel_i_2_n_0), + .I4(pipe_pclk_sel_out), + .O(pclk_sel_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT5 #( + .INIT(32'h80022000)) + pclk_sel_i_2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .O(pclk_sel_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + pclk_sel_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pclk_sel_i_1_n_0), + .Q(pipe_pclk_sel_out), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0800080008000000)) + phystatus_i_1 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(txratedone_i_2_n_0), + .I3(\fsm_reg_n_0_[0] ), + .I4(phystatus_reg2), + .I5(phystatus), + .O(phystatus_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + phystatus_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(phystatus_i_1_n_0), + .Q(phystatus), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE phystatus_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_PHYSTATUS), + .Q(phystatus_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE phystatus_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(phystatus_reg1), + .Q(phystatus_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE qplllock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_QPLLLOCK), + .Q(qplllock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE qplllock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qplllock_reg1), + .Q(qplllock_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h4044FFFF40440000)) + qpllpd_i_1__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllpd), + .I5(QRST_QPLLPD_IN), + .O(qpllpd_i_1__0_n_0)); + FDRE #( + .INIT(1'b0)) + qpllpd_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllpd_i_1__0_n_0), + .Q(QRST_QPLLPD_IN), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h4044FFFF40440000)) + qpllreset_i_1__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllreset), + .I5(QRST_QPLLRESET_IN), + .O(qpllreset_i_1__0_n_0)); + FDRE #( + .INIT(1'b0)) + qpllreset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllreset_i_1__0_n_0), + .Q(QRST_QPLLRESET_IN), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT5 #( + .INIT(32'h00000080)) + rate_done_reg1_i_1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[1] ), + .O(USER_RATE_DONE)); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT5 #( + .INIT(32'h00000001)) + \rate_idle_reg1[0]_i_1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[3] ), + .O(SYNC_RATE_IDLE)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rate_in_reg1_reg[0]_0 ), + .Q(rate_in_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rate_in_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_in_reg1[0]), + .Q(rate_in_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_in_reg1[1]), + .Q(rate_in_reg2[1]), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0444FFFF04440000)) + \rate_out[0]_i_1 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg2[0]), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\rate_out[0]_i_2_n_0 ), + .I5(RXRATE), + .O(\rate_out[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h8002020080000200)) + \rate_out[0]_i_2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(txpmareset0), + .O(\rate_out[0]_i_2_n_0 )); + LUT3 #( + .INIT(8'hBA)) + \rate_out[0]_i_3 + (.I0(gen3_exit), + .I1(rate_in_reg2[0]), + .I2(rate_in_reg2[1]), + .O(txpmareset0)); + FDRE #( + .INIT(1'b0)) + \rate_out_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rate_out[0]_i_1_n_0 ), + .Q(RXRATE), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT5 #( + .INIT(32'h08800000)) + rate_rxsync_reg1_i_1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[2] ), + .O(USER_RATE_RXSYNC)); + LUT6 #( + .INIT(64'hA3333333A0000000)) + ratedone_i_1 + (.I0(ratedone_i_2_n_0), + .I1(ratedone_i_3_n_0), + .I2(rxratedone), + .I3(phystatus), + .I4(txratedone), + .I5(ratedone), + .O(ratedone_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT5 #( + .INIT(32'h00080000)) + ratedone_i_2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .O(ratedone_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT5 #( + .INIT(32'hFDFFFFFF)) + ratedone_i_3 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[4] ), + .O(ratedone_i_3_n_0)); + FDRE #( + .INIT(1'b0)) + ratedone_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(ratedone_i_1_n_0), + .Q(ratedone), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b1), + .Q(resetovrd_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(resetovrd_done_reg1), + .Q(resetovrd_done_reg2), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT5 #( + .INIT(32'h00000080)) + resetovrd_start_reg1_i_1 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[3] ), + .O(USER_RESETOVRD_START)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RST_IDLE), + .Q(rst_idle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rst_idle_reg1), + .Q(rst_idle_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxpmaresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxpmaresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxpmaresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxpmaresetdone_reg1), + .Q(rxpmaresetdone_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0800080008000000)) + rxratedone_i_1 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(txratedone_i_2_n_0), + .I3(\fsm_reg_n_0_[0] ), + .I4(rxratedone_reg2), + .I5(rxratedone), + .O(rxratedone_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + rxratedone_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxratedone_i_1_n_0), + .Q(rxratedone), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxratedone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_RXRATEDONE), + .Q(rxratedone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxratedone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxratedone_reg1), + .Q(rxratedone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RXRESETDONE), + .Q(rxresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxresetdone_reg1), + .Q(rxresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxsync_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsync_done_reg1), + .Q(rxsync_done_reg2), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT5 #( + .INIT(32'h08000000)) + rxsync_start_reg1_i_1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm_reg_n_0_[3] ), + .O(SYNC_RXSYNC_START)); + LUT6 #( + .INIT(64'h0FFFFF4F00000040)) + \sysclksel[0]_i_1 + (.I0(rate_in_reg2[0]), + .I1(rate_in_reg2[1]), + .I2(\sysclksel[0]_i_2_n_0 ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[4] ), + .I5(RXSYSCLKSEL), + .O(\sysclksel[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT3 #( + .INIT(8'h80)) + \sysclksel[0]_i_2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .O(\sysclksel[0]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \sysclksel_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\sysclksel[0]_i_1_n_0 ), + .Q(RXSYSCLKSEL), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hB333000000000000)) + \txdata_wait_cnt[0]_i_1 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3_n_0 ), + .O(p_0_in__0[0])); + LUT6 #( + .INIT(64'hE666000000000000)) + \txdata_wait_cnt[1]_i_1 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3_n_0 ), + .O(p_0_in__0[1])); + LUT6 #( + .INIT(64'hF878000000000000)) + \txdata_wait_cnt[2]_i_1 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3_n_0 ), + .O(p_0_in__0[2])); + LUT6 #( + .INIT(64'hFF80000000000000)) + \txdata_wait_cnt[3]_i_1 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3_n_0 ), + .O(p_0_in__0[3])); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT3 #( + .INIT(8'h40)) + \txdata_wait_cnt[3]_i_2 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\txdata_wait_cnt[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT2 #( + .INIT(4'h2)) + \txdata_wait_cnt[3]_i_3 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .O(\txdata_wait_cnt[3]_i_3_n_0 )); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[0]), + .Q(txdata_wait_cnt_reg[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[1]), + .Q(txdata_wait_cnt_reg[1]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[2]), + .Q(txdata_wait_cnt_reg[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[3]), + .Q(txdata_wait_cnt_reg[3]), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h00F2FFFF00F20000)) + txpmareset_i_1 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg2[0]), + .I2(gen3_exit), + .I3(\fsm_reg_n_0_[3] ), + .I4(txpmareset_i_2_n_0), + .I5(rate_txpmareset_0), + .O(txpmareset_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT5 #( + .INIT(32'h80004200)) + txpmareset_i_2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[4] ), + .O(txpmareset_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + txpmareset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpmareset_i_1_n_0), + .Q(rate_txpmareset_0), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0800080008000000)) + txratedone_i_1 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(txratedone_i_2_n_0), + .I3(\fsm_reg_n_0_[0] ), + .I4(txratedone_reg2), + .I5(txratedone), + .O(txratedone_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT2 #( + .INIT(4'hE)) + txratedone_i_2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[1] ), + .O(txratedone_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + txratedone_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txratedone_i_1_n_0), + .Q(txratedone), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txratedone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_TXRATEDONE), + .Q(txratedone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txratedone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txratedone_reg1), + .Q(txratedone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_TXRESETDONE), + .Q(txresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txresetdone_reg1), + .Q(txresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_TXSYNC_DONE), + .Q(txsync_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_done_reg1), + .Q(txsync_done_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hFFFFFFFF00004000)) + txsync_start_reg1_i_1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[2] ), + .I5(RST_TXSYNC_START), + .O(SYNC_TXSYNC_START)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_rate" *) +module pcie_7x_0_pcie_7x_0_pipe_rate_40 + (SYNC_TXSYNC_START, + QPLL_DRP_GEN3, + rate_gen3_1, + rxchbonden_1, + RATE_DRP_START, + RATE_DRP_X16X20_MODE, + RATE_DRP_X16, + USER_RATE_RXSYNC, + SYNC_RXSYNC_START, + USER_RATE_DONE, + USER_RESETOVRD_START, + SYNC_RATE_IDLE, + rate_txpmareset_1, + RXSYSCLKSEL, + pipe_pclk_sel_out, + RXRATE, + QRST_QPLLPD_IN, + rate_cpllpd_1, + QRST_QPLLRESET_IN, + rate_cpllreset_1, + RST_TXSYNC_START, + USER_RATE_GEN3, + rate_gen3_3, + rate_gen3_2, + RST_CPLLRESET, + pipe_pclk_in, + \rate_in_reg1_reg[0]_0 , + RST_IDLE, + QRST_CPLLLOCK, + RATE_QPLLLOCK, + RATE_DRP_DONE, + pipe_mmcm_lock_in, + RATE_PHYSTATUS, + USER_TXRESETDONE, + USER_RXRESETDONE, + RATE_TXRATEDONE, + RATE_RXRATEDONE, + RATE_TXSYNC_DONE, + user_active_lane_1, + out, + \fsm[0]_i_9__0_0 ); + output SYNC_TXSYNC_START; + output QPLL_DRP_GEN3; + output rate_gen3_1; + output rxchbonden_1; + output RATE_DRP_START; + output RATE_DRP_X16X20_MODE; + output RATE_DRP_X16; + output USER_RATE_RXSYNC; + output SYNC_RXSYNC_START; + output USER_RATE_DONE; + output USER_RESETOVRD_START; + output SYNC_RATE_IDLE; + output rate_txpmareset_1; + output [0:0]RXSYSCLKSEL; + output [0:0]pipe_pclk_sel_out; + output [0:0]RXRATE; + output [0:0]QRST_QPLLPD_IN; + output rate_cpllpd_1; + output [0:0]QRST_QPLLRESET_IN; + output rate_cpllreset_1; + input RST_TXSYNC_START; + input USER_RATE_GEN3; + input rate_gen3_3; + input rate_gen3_2; + input RST_CPLLRESET; + input pipe_pclk_in; + input [0:0]\rate_in_reg1_reg[0]_0 ; + input RST_IDLE; + input [0:0]QRST_CPLLLOCK; + input RATE_QPLLLOCK; + input RATE_DRP_DONE; + input pipe_mmcm_lock_in; + input RATE_PHYSTATUS; + input USER_TXRESETDONE; + input USER_RXRESETDONE; + input RATE_TXRATEDONE; + input RATE_RXRATEDONE; + input RATE_TXSYNC_DONE; + input user_active_lane_1; + input out; + input \fsm[0]_i_9__0_0 ; + + wire QPLL_DRP_GEN3; + wire [0:0]QRST_CPLLLOCK; + wire [0:0]QRST_QPLLPD_IN; + wire [0:0]QRST_QPLLRESET_IN; + wire RATE_DRP_DONE; + wire RATE_DRP_START; + wire RATE_DRP_X16; + wire RATE_DRP_X16X20_MODE; + wire RATE_PHYSTATUS; + wire RATE_QPLLLOCK; + wire RATE_RXRATEDONE; + wire RATE_TXRATEDONE; + wire RATE_TXSYNC_DONE; + wire RST_CPLLRESET; + wire RST_IDLE; + wire RST_TXSYNC_START; + wire [0:0]RXRATE; + wire [0:0]RXSYSCLKSEL; + wire SYNC_RATE_IDLE; + wire SYNC_RXSYNC_START; + wire SYNC_TXSYNC_START; + wire USER_RATE_DONE; + wire USER_RATE_GEN3; + wire USER_RATE_RXSYNC; + wire USER_RESETOVRD_START; + wire USER_RXRESETDONE; + wire USER_TXRESETDONE; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire cplllock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire cplllock_reg2; + wire cpllpd_i_1__0_n_0; + wire cpllreset_i_1__1_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg2; + wire drp_start_i_1__0_n_0; + wire drp_x16_i_1__0_n_0; + wire drp_x16x20_mode_i_1__0_n_0; + wire [4:0]fsm; + wire fsm1; + wire \fsm[0]_i_10__0_n_0 ; + wire \fsm[0]_i_11__0_n_0 ; + wire \fsm[0]_i_12__0_n_0 ; + wire \fsm[0]_i_2__2_n_0 ; + wire \fsm[0]_i_3__0_n_0 ; + wire \fsm[0]_i_4__0_n_0 ; + wire \fsm[0]_i_5__0_n_0 ; + wire \fsm[0]_i_7__0_n_0 ; + wire \fsm[0]_i_8__0_n_0 ; + wire \fsm[0]_i_9__0_0 ; + wire \fsm[0]_i_9__0_n_0 ; + wire \fsm[1]_i_2__1_n_0 ; + wire \fsm[1]_i_3__0_n_0 ; + wire \fsm[1]_i_4__0_n_0 ; + wire \fsm[1]_i_5__0_n_0 ; + wire \fsm[1]_i_6__0_n_0 ; + wire \fsm[1]_i_7__0_n_0 ; + wire \fsm[1]_i_8__0_n_0 ; + wire \fsm[2]_i_2__0_n_0 ; + wire \fsm[2]_i_3__0_n_0 ; + wire \fsm[2]_i_4__0_n_0 ; + wire \fsm[2]_i_5__0_n_0 ; + wire \fsm[2]_i_6__0_n_0 ; + wire \fsm[3]_i_2__0_n_0 ; + wire \fsm[3]_i_3__0_n_0 ; + wire \fsm[3]_i_4__0_n_0 ; + wire \fsm[3]_i_6__0_n_0 ; + wire \fsm[4]_i_2__0_n_0 ; + wire \fsm[4]_i_3__0_n_0 ; + wire \fsm_reg_n_0_[0] ; + wire \fsm_reg_n_0_[1] ; + wire \fsm_reg_n_0_[2] ; + wire \fsm_reg_n_0_[3] ; + wire \fsm_reg_n_0_[4] ; + wire gen3_exit; + wire gen3_exit_i_1__0_n_0; + wire gen3_exit_i_2__0_n_0; + wire gen3_i_1__0_n_0; + wire gen3_i_2__0_n_0; + wire gen3_i_3__0_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2; + wire out; + wire [3:0]p_0_in__0; + wire pclk_sel_i_1__0_n_0; + wire pclk_sel_i_2__0_n_0; + wire phystatus; + wire phystatus_i_1__0_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire phystatus_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire phystatus_reg2; + wire pipe_mmcm_lock_in; + wire pipe_pclk_in; + wire [0:0]pipe_pclk_sel_out; + wire pll_lock; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg2; + wire qpllpd; + wire qpllpd_i_1__1_n_0; + wire qpllreset; + wire qpllreset_i_1__1_n_0; + wire rate_cpllpd_1; + wire rate_cpllreset_1; + wire rate_gen3_1; + wire rate_gen3_2; + wire rate_gen3_3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_in_reg1; + wire [0:0]\rate_in_reg1_reg[0]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_in_reg2; + wire \rate_out[0]_i_1__0_n_0 ; + wire \rate_out[0]_i_2__0_n_0 ; + wire rate_txpmareset_1; + wire ratedone; + wire ratedone_i_1__0_n_0; + wire ratedone_i_2__0_n_0; + wire ratedone_i_3__0_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_done_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg2; + wire rxchbonden_1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxpmaresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxpmaresetdone_reg2; + wire rxratedone; + wire rxratedone_i_1__0_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxratedone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxratedone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_done_reg2; + wire \sysclksel[0]_i_1__0_n_0 ; + wire \sysclksel[0]_i_2__0_n_0 ; + wire \txdata_wait_cnt[3]_i_2__0_n_0 ; + wire \txdata_wait_cnt[3]_i_3__0_n_0 ; + wire [3:0]txdata_wait_cnt_reg; + wire txpmareset0; + wire txpmareset_i_1__0_n_0; + wire txpmareset_i_2__0_n_0; + wire txratedone; + wire txratedone_i_1__0_n_0; + wire txratedone_i_2__0_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txratedone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txratedone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_done_reg2; + wire user_active_lane_1; + + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE cplllock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(QRST_CPLLLOCK), + .Q(cplllock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE cplllock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cplllock_reg1), + .Q(cplllock_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0400FFFF04000000)) + cpllpd_i_1__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllpd), + .I5(rate_cpllpd_1), + .O(cpllpd_i_1__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT5 #( + .INIT(32'h80000900)) + cpllpd_i_2__0 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[2] ), + .O(qpllpd)); + FDRE #( + .INIT(1'b0)) + cpllpd_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cpllpd_i_1__0_n_0), + .Q(rate_cpllpd_1), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0400FFFF04000000)) + cpllreset_i_1__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllreset), + .I5(rate_cpllreset_1), + .O(cpllreset_i_1__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT5 #( + .INIT(32'h80001004)) + cpllreset_i_2__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm_reg_n_0_[0] ), + .O(qpllreset)); + FDRE #( + .INIT(1'b0)) + cpllreset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cpllreset_i_1__1_n_0), + .Q(rate_cpllreset_1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE drp_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_DRP_DONE), + .Q(drp_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE drp_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_done_reg1), + .Q(drp_done_reg2), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT5 #( + .INIT(32'h08420100)) + drp_start_i_1__0 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[0] ), + .O(drp_start_i_1__0_n_0)); + FDRE #( + .INIT(1'b0)) + drp_start_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_start_i_1__0_n_0), + .Q(RATE_DRP_START), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT5 #( + .INIT(32'h20100014)) + drp_x16_i_1__0 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .O(drp_x16_i_1__0_n_0)); + FDRE #( + .INIT(1'b0)) + drp_x16_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_x16_i_1__0_n_0), + .Q(RATE_DRP_X16), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT5 #( + .INIT(32'h20080074)) + drp_x16x20_mode_i_1__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[1] ), + .O(drp_x16x20_mode_i_1__0_n_0)); + FDRE #( + .INIT(1'b0)) + drp_x16x20_mode_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_x16x20_mode_i_1__0_n_0), + .Q(RATE_DRP_X16X20_MODE), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0901595100000000)) + \fsm[0]_i_10__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(rxsync_done_reg2), + .I4(txsync_done_reg2), + .I5(\fsm_reg_n_0_[3] ), + .O(\fsm[0]_i_10__0_n_0 )); + LUT6 #( + .INIT(64'h1101111101000110)) + \fsm[0]_i_11__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(rxpmaresetdone_reg2), + .I5(drp_done_reg2), + .O(\fsm[0]_i_11__0_n_0 )); + LUT5 #( + .INIT(32'h20202320)) + \fsm[0]_i_12__0 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(mmcm_lock_reg2), + .I4(rxpmaresetdone_reg2), + .O(\fsm[0]_i_12__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT5 #( + .INIT(32'hFFFF3210)) + \fsm[0]_i_1__2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm[0]_i_2__2_n_0 ), + .I3(\fsm[0]_i_3__0_n_0 ), + .I4(\fsm[0]_i_4__0_n_0 ), + .O(fsm[0])); + LUT6 #( + .INIT(64'h0F0F3F3F47444744)) + \fsm[0]_i_2__2 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm[0]_i_5__0_n_0 ), + .I4(pll_lock), + .I5(\fsm_reg_n_0_[1] ), + .O(\fsm[0]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'hF3F3AAAAFF00AAAA)) + \fsm[0]_i_3__0 + (.I0(\fsm[0]_i_7__0_n_0 ), + .I1(\fsm_reg_n_0_[0] ), + .I2(drp_done_reg2), + .I3(\fsm[0]_i_8__0_n_0 ), + .I4(\fsm_reg_n_0_[2] ), + .I5(\fsm_reg_n_0_[1] ), + .O(\fsm[0]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFF4000000000)) + \fsm[0]_i_4__0 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm[0]_i_9__0_n_0 ), + .I3(\fsm[0]_i_10__0_n_0 ), + .I4(\fsm[0]_i_11__0_n_0 ), + .I5(\fsm_reg_n_0_[4] ), + .O(\fsm[0]_i_4__0_n_0 )); + LUT4 #( + .INIT(16'h6FF6)) + \fsm[0]_i_5__0 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg1[1]), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg1[0]), + .O(\fsm[0]_i_5__0_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \fsm[0]_i_6__0 + (.I0(qplllock_reg2), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(cplllock_reg2), + .O(pll_lock)); + LUT6 #( + .INIT(64'hAAAAAAAAEAAAAAAA)) + \fsm[0]_i_7__0 + (.I0(\fsm[0]_i_12__0_n_0 ), + .I1(pll_lock), + .I2(rst_idle_reg2), + .I3(drp_done_reg2), + .I4(\fsm_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[0] ), + .O(\fsm[0]_i_7__0_n_0 )); + LUT6 #( + .INIT(64'hFFFF5D5500005D55)) + \fsm[0]_i_8__0 + (.I0(user_active_lane_1), + .I1(txresetdone_reg2), + .I2(phystatus_reg2), + .I3(rxresetdone_reg2), + .I4(\fsm_reg_n_0_[0] ), + .I5(\fsm[1]_i_7__0_n_0 ), + .O(\fsm[0]_i_8__0_n_0 )); + LUT5 #( + .INIT(32'h33330FAA)) + \fsm[0]_i_9__0 + (.I0(drp_done_reg2), + .I1(resetovrd_done_reg2), + .I2(fsm1), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[1] ), + .O(\fsm[0]_i_9__0_n_0 )); + LUT6 #( + .INIT(64'hFFE4FFE4FFE400E4)) + \fsm[1]_i_1__2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm[1]_i_2__1_n_0 ), + .I2(\fsm[1]_i_3__0_n_0 ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm[1]_i_4__0_n_0 ), + .I5(\fsm[1]_i_5__0_n_0 ), + .O(fsm[1])); + LUT5 #( + .INIT(32'h3388F0CC)) + \fsm[1]_i_2__1 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm[1]_i_6__0_n_0 ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[2] ), + .O(\fsm[1]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'hCC5500000033F000)) + \fsm[1]_i_3__0 + (.I0(\fsm[1]_i_7__0_n_0 ), + .I1(drp_done_reg2), + .I2(\fsm[1]_i_8__0_n_0 ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[1]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h000000005FCF0000)) + \fsm[1]_i_4__0 + (.I0(resetovrd_done_reg2), + .I1(drp_done_reg2), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[3] ), + .O(\fsm[1]_i_4__0_n_0 )); + LUT6 #( + .INIT(64'h143C547C00000000)) + \fsm[1]_i_5__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(rxsync_done_reg2), + .I4(txsync_done_reg2), + .I5(\fsm_reg_n_0_[3] ), + .O(\fsm[1]_i_5__0_n_0 )); + LUT6 #( + .INIT(64'h34F7FFFFFFFFFFFF)) + \fsm[1]_i_6__0 + (.I0(qplllock_reg2), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(cplllock_reg2), + .I4(rst_idle_reg2), + .I5(\fsm_reg_n_0_[0] ), + .O(\fsm[1]_i_6__0_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \fsm[1]_i_7__0 + (.I0(txdata_wait_cnt_reg[3]), + .I1(txdata_wait_cnt_reg[1]), + .I2(txdata_wait_cnt_reg[0]), + .I3(txdata_wait_cnt_reg[2]), + .O(\fsm[1]_i_7__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF04F7FFFF)) + \fsm[1]_i_8__0 + (.I0(qplllock_reg2), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(cplllock_reg2), + .I4(drp_done_reg2), + .I5(rst_idle_reg2), + .O(\fsm[1]_i_8__0_n_0 )); + LUT6 #( + .INIT(64'hEAFFAAAAAAAAAAAA)) + \fsm[2]_i_2__0 + (.I0(\fsm[2]_i_4__0_n_0 ), + .I1(drp_done_reg2), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[2]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFBAAAAAAAAAAAAA)) + \fsm[2]_i_3__0 + (.I0(\fsm[2]_i_5__0_n_0 ), + .I1(rxsync_done_reg2), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[2]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h00FA554455005544)) + \fsm[2]_i_4__0 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm[3]_i_6__0_n_0 ), + .I2(pll_lock), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[0] ), + .O(\fsm[2]_i_4__0_n_0 )); + LUT6 #( + .INIT(64'h2000FFFF20000000)) + \fsm[2]_i_5__0 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(txsync_done_reg2), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm[2]_i_6__0_n_0 ), + .O(\fsm[2]_i_5__0_n_0 )); + LUT6 #( + .INIT(64'h1CDC3C3C1CDCFCFC)) + \fsm[2]_i_6__0 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(resetovrd_done_reg2), + .I4(\fsm_reg_n_0_[1] ), + .I5(fsm1), + .O(\fsm[2]_i_6__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFB0803080)) + \fsm[3]_i_2__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(drp_done_reg2), + .I5(\fsm[3]_i_4__0_n_0 ), + .O(\fsm[3]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFF8880000F888)) + \fsm[3]_i_3__0 + (.I0(\txdata_wait_cnt[3]_i_2__0_n_0 ), + .I1(fsm1), + .I2(resetovrd_done_reg2), + .I3(\sysclksel[0]_i_2__0_n_0 ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm[4]_i_2__0_n_0 ), + .O(\fsm[3]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h00000000EEFF00F0)) + \fsm[3]_i_4__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm[1]_i_8__0_n_0 ), + .I2(\fsm[3]_i_6__0_n_0 ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[3]_i_4__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFF8F8FFF8)) + \fsm[3]_i_5__0 + (.I0(out), + .I1(\fsm[0]_i_9__0_0 ), + .I2(ratedone), + .I3(rate_in_reg2[1]), + .I4(rate_in_reg2[0]), + .I5(gen3_exit), + .O(fsm1)); + LUT5 #( + .INIT(32'h00504414)) + \fsm[3]_i_6__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(rate_in_reg1[0]), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg1[1]), + .I4(rate_in_reg2[1]), + .O(\fsm[3]_i_6__0_n_0 )); + LUT6 #( + .INIT(64'hC5F0CFF0C0F0C0F0)) + \fsm[4]_i_1__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm[4]_i_2__0_n_0 ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(drp_done_reg2), + .I5(\fsm[4]_i_3__0_n_0 ), + .O(fsm[4])); + LUT4 #( + .INIT(16'h26FF)) + \fsm[4]_i_2__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(rxsync_done_reg2), + .I3(\fsm_reg_n_0_[2] ), + .O(\fsm[4]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT2 #( + .INIT(4'h8)) + \fsm[4]_i_3__0 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[2] ), + .O(\fsm[4]_i_3__0_n_0 )); + FDSE #( + .INIT(1'b0)) + \fsm_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[0]), + .Q(\fsm_reg_n_0_[0] ), + .S(RST_CPLLRESET)); + FDSE #( + .INIT(1'b0)) + \fsm_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[1]), + .Q(\fsm_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \fsm_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[2]), + .Q(\fsm_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + MUXF7 \fsm_reg[2]_i_1__0 + (.I0(\fsm[2]_i_2__0_n_0 ), + .I1(\fsm[2]_i_3__0_n_0 ), + .O(fsm[2]), + .S(\fsm_reg_n_0_[4] )); + FDRE #( + .INIT(1'b0)) + \fsm_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[3]), + .Q(\fsm_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + MUXF7 \fsm_reg[3]_i_1__0 + (.I0(\fsm[3]_i_2__0_n_0 ), + .I1(\fsm[3]_i_3__0_n_0 ), + .O(fsm[3]), + .S(\fsm_reg_n_0_[4] )); + FDRE #( + .INIT(1'b0)) + \fsm_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[4]), + .Q(\fsm_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h04FF0400)) + gen3_exit_i_1__0 + (.I0(rate_in_reg2[0]), + .I1(rate_in_reg2[1]), + .I2(\fsm_reg_n_0_[4] ), + .I3(gen3_exit_i_2__0_n_0), + .I4(gen3_exit), + .O(gen3_exit_i_1__0_n_0)); + LUT6 #( + .INIT(64'h8000000180000000)) + gen3_exit_i_2__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[4] ), + .I5(\fsm[0]_i_5__0_n_0 ), + .O(gen3_exit_i_2__0_n_0)); + FDRE #( + .INIT(1'b0)) + gen3_exit_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_exit_i_1__0_n_0), + .Q(gen3_exit), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h3FFFFFFB00000008)) + gen3_i_1__0 + (.I0(gen3_i_2__0_n_0), + .I1(gen3_i_3__0_n_0), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[4] ), + .I5(rate_gen3_1), + .O(gen3_i_1__0_n_0)); + LUT2 #( + .INIT(4'h2)) + gen3_i_2__0 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg2[0]), + .O(gen3_i_2__0_n_0)); + LUT2 #( + .INIT(4'h8)) + gen3_i_3__0 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[0] ), + .O(gen3_i_3__0_n_0)); + FDRE #( + .INIT(1'b0)) + gen3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_i_1__0_n_0), + .Q(rate_gen3_1), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT4 #( + .INIT(16'h8000)) + gen3_reg1_i_1 + (.I0(rate_gen3_1), + .I1(USER_RATE_GEN3), + .I2(rate_gen3_3), + .I3(rate_gen3_2), + .O(QPLL_DRP_GEN3)); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT1 #( + .INIT(2'h1)) + \gtx_channel.gtxe2_channel_i_i_5__0 + (.I0(rate_gen3_1), + .O(rxchbonden_1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_mmcm_lock_in), + .Q(mmcm_lock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(mmcm_lock_reg1), + .Q(mmcm_lock_reg2), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h14FF1400)) + pclk_sel_i_1__0 + (.I0(\fsm_reg_n_0_[4] ), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(pclk_sel_i_2__0_n_0), + .I4(pipe_pclk_sel_out), + .O(pclk_sel_i_1__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT5 #( + .INIT(32'h80022000)) + pclk_sel_i_2__0 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .O(pclk_sel_i_2__0_n_0)); + FDRE #( + .INIT(1'b0)) + pclk_sel_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pclk_sel_i_1__0_n_0), + .Q(pipe_pclk_sel_out), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0800080008000000)) + phystatus_i_1__0 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(txratedone_i_2__0_n_0), + .I3(\fsm_reg_n_0_[0] ), + .I4(phystatus_reg2), + .I5(phystatus), + .O(phystatus_i_1__0_n_0)); + FDRE #( + .INIT(1'b0)) + phystatus_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(phystatus_i_1__0_n_0), + .Q(phystatus), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE phystatus_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_PHYSTATUS), + .Q(phystatus_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE phystatus_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(phystatus_reg1), + .Q(phystatus_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE qplllock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_QPLLLOCK), + .Q(qplllock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE qplllock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qplllock_reg1), + .Q(qplllock_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h4044FFFF40440000)) + qpllpd_i_1__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllpd), + .I5(QRST_QPLLPD_IN), + .O(qpllpd_i_1__1_n_0)); + FDRE #( + .INIT(1'b0)) + qpllpd_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllpd_i_1__1_n_0), + .Q(QRST_QPLLPD_IN), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h4044FFFF40440000)) + qpllreset_i_1__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllreset), + .I5(QRST_QPLLRESET_IN), + .O(qpllreset_i_1__1_n_0)); + FDRE #( + .INIT(1'b0)) + qpllreset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllreset_i_1__1_n_0), + .Q(QRST_QPLLRESET_IN), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT5 #( + .INIT(32'h00000080)) + rate_done_reg1_i_1__0 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[1] ), + .O(USER_RATE_DONE)); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT5 #( + .INIT(32'h00000001)) + \rate_idle_reg1[1]_i_1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[3] ), + .O(SYNC_RATE_IDLE)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rate_in_reg1_reg[0]_0 ), + .Q(rate_in_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rate_in_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_in_reg1[0]), + .Q(rate_in_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_in_reg1[1]), + .Q(rate_in_reg2[1]), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0444FFFF04440000)) + \rate_out[0]_i_1__0 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg2[0]), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\rate_out[0]_i_2__0_n_0 ), + .I5(RXRATE), + .O(\rate_out[0]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'h8002020080000200)) + \rate_out[0]_i_2__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(txpmareset0), + .O(\rate_out[0]_i_2__0_n_0 )); + LUT3 #( + .INIT(8'hBA)) + \rate_out[0]_i_3__0 + (.I0(gen3_exit), + .I1(rate_in_reg2[0]), + .I2(rate_in_reg2[1]), + .O(txpmareset0)); + FDRE #( + .INIT(1'b0)) + \rate_out_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rate_out[0]_i_1__0_n_0 ), + .Q(RXRATE), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT5 #( + .INIT(32'h08800000)) + rate_rxsync_reg1_i_1__0 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[2] ), + .O(USER_RATE_RXSYNC)); + LUT6 #( + .INIT(64'hA3333333A0000000)) + ratedone_i_1__0 + (.I0(ratedone_i_2__0_n_0), + .I1(ratedone_i_3__0_n_0), + .I2(rxratedone), + .I3(phystatus), + .I4(txratedone), + .I5(ratedone), + .O(ratedone_i_1__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT5 #( + .INIT(32'h00080000)) + ratedone_i_2__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .O(ratedone_i_2__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT5 #( + .INIT(32'hFDFFFFFF)) + ratedone_i_3__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[4] ), + .O(ratedone_i_3__0_n_0)); + FDRE #( + .INIT(1'b0)) + ratedone_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(ratedone_i_1__0_n_0), + .Q(ratedone), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b1), + .Q(resetovrd_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(resetovrd_done_reg1), + .Q(resetovrd_done_reg2), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT5 #( + .INIT(32'h00000080)) + resetovrd_start_reg1_i_1__0 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[3] ), + .O(USER_RESETOVRD_START)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RST_IDLE), + .Q(rst_idle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rst_idle_reg1), + .Q(rst_idle_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxpmaresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxpmaresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxpmaresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxpmaresetdone_reg1), + .Q(rxpmaresetdone_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0800080008000000)) + rxratedone_i_1__0 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(txratedone_i_2__0_n_0), + .I3(\fsm_reg_n_0_[0] ), + .I4(rxratedone_reg2), + .I5(rxratedone), + .O(rxratedone_i_1__0_n_0)); + FDRE #( + .INIT(1'b0)) + rxratedone_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxratedone_i_1__0_n_0), + .Q(rxratedone), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxratedone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_RXRATEDONE), + .Q(rxratedone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxratedone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxratedone_reg1), + .Q(rxratedone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RXRESETDONE), + .Q(rxresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxresetdone_reg1), + .Q(rxresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxsync_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsync_done_reg1), + .Q(rxsync_done_reg2), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT5 #( + .INIT(32'h08000000)) + rxsync_start_reg1_i_1__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm_reg_n_0_[3] ), + .O(SYNC_RXSYNC_START)); + LUT6 #( + .INIT(64'h0FFFFF4F00000040)) + \sysclksel[0]_i_1__0 + (.I0(rate_in_reg2[0]), + .I1(rate_in_reg2[1]), + .I2(\sysclksel[0]_i_2__0_n_0 ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[4] ), + .I5(RXSYSCLKSEL), + .O(\sysclksel[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT3 #( + .INIT(8'h80)) + \sysclksel[0]_i_2__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .O(\sysclksel[0]_i_2__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sysclksel_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\sysclksel[0]_i_1__0_n_0 ), + .Q(RXSYSCLKSEL), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hB333000000000000)) + \txdata_wait_cnt[0]_i_1__0 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2__0_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3__0_n_0 ), + .O(p_0_in__0[0])); + LUT6 #( + .INIT(64'hE666000000000000)) + \txdata_wait_cnt[1]_i_1__0 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2__0_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3__0_n_0 ), + .O(p_0_in__0[1])); + LUT6 #( + .INIT(64'hF878000000000000)) + \txdata_wait_cnt[2]_i_1__0 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2__0_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3__0_n_0 ), + .O(p_0_in__0[2])); + LUT6 #( + .INIT(64'hFF80000000000000)) + \txdata_wait_cnt[3]_i_1__0 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2__0_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3__0_n_0 ), + .O(p_0_in__0[3])); + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT3 #( + .INIT(8'h40)) + \txdata_wait_cnt[3]_i_2__0 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\txdata_wait_cnt[3]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT2 #( + .INIT(4'h2)) + \txdata_wait_cnt[3]_i_3__0 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .O(\txdata_wait_cnt[3]_i_3__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[0]), + .Q(txdata_wait_cnt_reg[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[1]), + .Q(txdata_wait_cnt_reg[1]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[2]), + .Q(txdata_wait_cnt_reg[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[3]), + .Q(txdata_wait_cnt_reg[3]), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h00F2FFFF00F20000)) + txpmareset_i_1__0 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg2[0]), + .I2(gen3_exit), + .I3(\fsm_reg_n_0_[3] ), + .I4(txpmareset_i_2__0_n_0), + .I5(rate_txpmareset_1), + .O(txpmareset_i_1__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT5 #( + .INIT(32'h80004200)) + txpmareset_i_2__0 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[4] ), + .O(txpmareset_i_2__0_n_0)); + FDRE #( + .INIT(1'b0)) + txpmareset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpmareset_i_1__0_n_0), + .Q(rate_txpmareset_1), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0800080008000000)) + txratedone_i_1__0 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(txratedone_i_2__0_n_0), + .I3(\fsm_reg_n_0_[0] ), + .I4(txratedone_reg2), + .I5(txratedone), + .O(txratedone_i_1__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT2 #( + .INIT(4'hE)) + txratedone_i_2__0 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[1] ), + .O(txratedone_i_2__0_n_0)); + FDRE #( + .INIT(1'b0)) + txratedone_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txratedone_i_1__0_n_0), + .Q(txratedone), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txratedone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_TXRATEDONE), + .Q(txratedone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txratedone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txratedone_reg1), + .Q(txratedone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_TXRESETDONE), + .Q(txresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txresetdone_reg1), + .Q(txresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_TXSYNC_DONE), + .Q(txsync_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_done_reg1), + .Q(txsync_done_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hFFFFFFFF00004000)) + txsync_start_reg1_i_1__0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[2] ), + .I5(RST_TXSYNC_START), + .O(SYNC_TXSYNC_START)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_rate" *) +module pcie_7x_0_pcie_7x_0_pipe_rate_46 + (SYNC_TXSYNC_START, + rxchbonden_2, + rate_gen3_2, + RATE_DRP_START, + RATE_DRP_X16X20_MODE, + RATE_DRP_X16, + USER_RATE_RXSYNC, + SYNC_RXSYNC_START, + USER_RATE_DONE, + USER_RESETOVRD_START, + SYNC_RATE_IDLE, + rate_txpmareset_2, + RXSYSCLKSEL, + pipe_pclk_sel_out, + RXRATE, + QRST_QPLLPD_IN, + rate_cpllpd_2, + QRST_QPLLRESET_IN, + rate_cpllreset_2, + RST_TXSYNC_START, + RST_CPLLRESET, + pipe_pclk_in, + \rate_in_reg1_reg[0]_0 , + RST_IDLE, + QRST_CPLLLOCK, + RATE_QPLLLOCK, + RATE_DRP_DONE, + pipe_mmcm_lock_in, + RATE_PHYSTATUS, + USER_TXRESETDONE, + USER_RXRESETDONE, + RATE_TXRATEDONE, + RATE_RXRATEDONE, + RATE_TXSYNC_DONE, + user_active_lane_2, + out, + \fsm[0]_i_9__1_0 ); + output SYNC_TXSYNC_START; + output rxchbonden_2; + output rate_gen3_2; + output RATE_DRP_START; + output RATE_DRP_X16X20_MODE; + output RATE_DRP_X16; + output USER_RATE_RXSYNC; + output SYNC_RXSYNC_START; + output USER_RATE_DONE; + output USER_RESETOVRD_START; + output SYNC_RATE_IDLE; + output rate_txpmareset_2; + output [0:0]RXSYSCLKSEL; + output [0:0]pipe_pclk_sel_out; + output [0:0]RXRATE; + output [0:0]QRST_QPLLPD_IN; + output rate_cpllpd_2; + output [0:0]QRST_QPLLRESET_IN; + output rate_cpllreset_2; + input RST_TXSYNC_START; + input RST_CPLLRESET; + input pipe_pclk_in; + input [0:0]\rate_in_reg1_reg[0]_0 ; + input RST_IDLE; + input [0:0]QRST_CPLLLOCK; + input RATE_QPLLLOCK; + input RATE_DRP_DONE; + input pipe_mmcm_lock_in; + input RATE_PHYSTATUS; + input USER_TXRESETDONE; + input USER_RXRESETDONE; + input RATE_TXRATEDONE; + input RATE_RXRATEDONE; + input RATE_TXSYNC_DONE; + input user_active_lane_2; + input out; + input \fsm[0]_i_9__1_0 ; + + wire [0:0]QRST_CPLLLOCK; + wire [0:0]QRST_QPLLPD_IN; + wire [0:0]QRST_QPLLRESET_IN; + wire RATE_DRP_DONE; + wire RATE_DRP_START; + wire RATE_DRP_X16; + wire RATE_DRP_X16X20_MODE; + wire RATE_PHYSTATUS; + wire RATE_QPLLLOCK; + wire RATE_RXRATEDONE; + wire RATE_TXRATEDONE; + wire RATE_TXSYNC_DONE; + wire RST_CPLLRESET; + wire RST_IDLE; + wire RST_TXSYNC_START; + wire [0:0]RXRATE; + wire [0:0]RXSYSCLKSEL; + wire SYNC_RATE_IDLE; + wire SYNC_RXSYNC_START; + wire SYNC_TXSYNC_START; + wire USER_RATE_DONE; + wire USER_RATE_RXSYNC; + wire USER_RESETOVRD_START; + wire USER_RXRESETDONE; + wire USER_TXRESETDONE; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire cplllock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire cplllock_reg2; + wire cpllpd_i_1__1_n_0; + wire cpllreset_i_1__2_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg2; + wire drp_start_i_1__1_n_0; + wire drp_x16_i_1__1_n_0; + wire drp_x16x20_mode_i_1__1_n_0; + wire [4:0]fsm; + wire fsm1; + wire \fsm[0]_i_10__1_n_0 ; + wire \fsm[0]_i_11__1_n_0 ; + wire \fsm[0]_i_12__1_n_0 ; + wire \fsm[0]_i_2__4_n_0 ; + wire \fsm[0]_i_3__1_n_0 ; + wire \fsm[0]_i_4__1_n_0 ; + wire \fsm[0]_i_5__1_n_0 ; + wire \fsm[0]_i_7__1_n_0 ; + wire \fsm[0]_i_8__1_n_0 ; + wire \fsm[0]_i_9__1_0 ; + wire \fsm[0]_i_9__1_n_0 ; + wire \fsm[1]_i_2__2_n_0 ; + wire \fsm[1]_i_3__1_n_0 ; + wire \fsm[1]_i_4__1_n_0 ; + wire \fsm[1]_i_5__1_n_0 ; + wire \fsm[1]_i_6__1_n_0 ; + wire \fsm[1]_i_7__1_n_0 ; + wire \fsm[1]_i_8__1_n_0 ; + wire \fsm[2]_i_2__1_n_0 ; + wire \fsm[2]_i_3__1_n_0 ; + wire \fsm[2]_i_4__1_n_0 ; + wire \fsm[2]_i_5__1_n_0 ; + wire \fsm[2]_i_6__1_n_0 ; + wire \fsm[3]_i_2__1_n_0 ; + wire \fsm[3]_i_3__1_n_0 ; + wire \fsm[3]_i_4__1_n_0 ; + wire \fsm[3]_i_6__1_n_0 ; + wire \fsm[4]_i_2__1_n_0 ; + wire \fsm[4]_i_3__1_n_0 ; + wire \fsm_reg_n_0_[0] ; + wire \fsm_reg_n_0_[1] ; + wire \fsm_reg_n_0_[2] ; + wire \fsm_reg_n_0_[3] ; + wire \fsm_reg_n_0_[4] ; + wire gen3_exit; + wire gen3_exit_i_1__1_n_0; + wire gen3_exit_i_2__1_n_0; + wire gen3_i_1__1_n_0; + wire gen3_i_2__1_n_0; + wire gen3_i_3__1_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2; + wire out; + wire [3:0]p_0_in__0; + wire pclk_sel_i_1__1_n_0; + wire pclk_sel_i_2__1_n_0; + wire phystatus; + wire phystatus_i_1__1_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire phystatus_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire phystatus_reg2; + wire pipe_mmcm_lock_in; + wire pipe_pclk_in; + wire [0:0]pipe_pclk_sel_out; + wire pll_lock; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg2; + wire qpllpd; + wire qpllpd_i_1__2_n_0; + wire qpllreset; + wire qpllreset_i_1__2_n_0; + wire rate_cpllpd_2; + wire rate_cpllreset_2; + wire rate_gen3_2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_in_reg1; + wire [0:0]\rate_in_reg1_reg[0]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_in_reg2; + wire \rate_out[0]_i_1__1_n_0 ; + wire \rate_out[0]_i_2__1_n_0 ; + wire rate_txpmareset_2; + wire ratedone; + wire ratedone_i_1__1_n_0; + wire ratedone_i_2__1_n_0; + wire ratedone_i_3__1_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_done_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg2; + wire rxchbonden_2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxpmaresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxpmaresetdone_reg2; + wire rxratedone; + wire rxratedone_i_1__1_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxratedone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxratedone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_done_reg2; + wire \sysclksel[0]_i_1__1_n_0 ; + wire \sysclksel[0]_i_2__1_n_0 ; + wire \txdata_wait_cnt[3]_i_2__1_n_0 ; + wire \txdata_wait_cnt[3]_i_3__1_n_0 ; + wire [3:0]txdata_wait_cnt_reg; + wire txpmareset0; + wire txpmareset_i_1__1_n_0; + wire txpmareset_i_2__1_n_0; + wire txratedone; + wire txratedone_i_1__1_n_0; + wire txratedone_i_2__1_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txratedone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txratedone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_done_reg2; + wire user_active_lane_2; + + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE cplllock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(QRST_CPLLLOCK), + .Q(cplllock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE cplllock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cplllock_reg1), + .Q(cplllock_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0400FFFF04000000)) + cpllpd_i_1__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllpd), + .I5(rate_cpllpd_2), + .O(cpllpd_i_1__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair153" *) + LUT5 #( + .INIT(32'h80000900)) + cpllpd_i_2__1 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[2] ), + .O(qpllpd)); + FDRE #( + .INIT(1'b0)) + cpllpd_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cpllpd_i_1__1_n_0), + .Q(rate_cpllpd_2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0400FFFF04000000)) + cpllreset_i_1__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllreset), + .I5(rate_cpllreset_2), + .O(cpllreset_i_1__2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair154" *) + LUT5 #( + .INIT(32'h80001004)) + cpllreset_i_2__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm_reg_n_0_[0] ), + .O(qpllreset)); + FDRE #( + .INIT(1'b0)) + cpllreset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cpllreset_i_1__2_n_0), + .Q(rate_cpllreset_2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE drp_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_DRP_DONE), + .Q(drp_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE drp_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_done_reg1), + .Q(drp_done_reg2), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair157" *) + LUT5 #( + .INIT(32'h08420100)) + drp_start_i_1__1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[0] ), + .O(drp_start_i_1__1_n_0)); + FDRE #( + .INIT(1'b0)) + drp_start_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_start_i_1__1_n_0), + .Q(RATE_DRP_START), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair158" *) + LUT5 #( + .INIT(32'h20100014)) + drp_x16_i_1__1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .O(drp_x16_i_1__1_n_0)); + FDRE #( + .INIT(1'b0)) + drp_x16_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_x16_i_1__1_n_0), + .Q(RATE_DRP_X16), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair159" *) + LUT5 #( + .INIT(32'h20080074)) + drp_x16x20_mode_i_1__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[1] ), + .O(drp_x16x20_mode_i_1__1_n_0)); + FDRE #( + .INIT(1'b0)) + drp_x16x20_mode_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_x16x20_mode_i_1__1_n_0), + .Q(RATE_DRP_X16X20_MODE), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0901595100000000)) + \fsm[0]_i_10__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(rxsync_done_reg2), + .I4(txsync_done_reg2), + .I5(\fsm_reg_n_0_[3] ), + .O(\fsm[0]_i_10__1_n_0 )); + LUT6 #( + .INIT(64'h1101111101000110)) + \fsm[0]_i_11__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(rxpmaresetdone_reg2), + .I5(drp_done_reg2), + .O(\fsm[0]_i_11__1_n_0 )); + LUT5 #( + .INIT(32'h20202320)) + \fsm[0]_i_12__1 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(mmcm_lock_reg2), + .I4(rxpmaresetdone_reg2), + .O(\fsm[0]_i_12__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair152" *) + LUT5 #( + .INIT(32'hFFFF3210)) + \fsm[0]_i_1__4 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm[0]_i_2__4_n_0 ), + .I3(\fsm[0]_i_3__1_n_0 ), + .I4(\fsm[0]_i_4__1_n_0 ), + .O(fsm[0])); + LUT6 #( + .INIT(64'h0F0F3F3F47444744)) + \fsm[0]_i_2__4 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm[0]_i_5__1_n_0 ), + .I4(pll_lock), + .I5(\fsm_reg_n_0_[1] ), + .O(\fsm[0]_i_2__4_n_0 )); + LUT6 #( + .INIT(64'hF3F3AAAAFF00AAAA)) + \fsm[0]_i_3__1 + (.I0(\fsm[0]_i_7__1_n_0 ), + .I1(\fsm_reg_n_0_[0] ), + .I2(drp_done_reg2), + .I3(\fsm[0]_i_8__1_n_0 ), + .I4(\fsm_reg_n_0_[2] ), + .I5(\fsm_reg_n_0_[1] ), + .O(\fsm[0]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFF4000000000)) + \fsm[0]_i_4__1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm[0]_i_9__1_n_0 ), + .I3(\fsm[0]_i_10__1_n_0 ), + .I4(\fsm[0]_i_11__1_n_0 ), + .I5(\fsm_reg_n_0_[4] ), + .O(\fsm[0]_i_4__1_n_0 )); + LUT4 #( + .INIT(16'h6FF6)) + \fsm[0]_i_5__1 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg1[1]), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg1[0]), + .O(\fsm[0]_i_5__1_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \fsm[0]_i_6__1 + (.I0(qplllock_reg2), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(cplllock_reg2), + .O(pll_lock)); + LUT6 #( + .INIT(64'hAAAAAAAAEAAAAAAA)) + \fsm[0]_i_7__1 + (.I0(\fsm[0]_i_12__1_n_0 ), + .I1(pll_lock), + .I2(rst_idle_reg2), + .I3(drp_done_reg2), + .I4(\fsm_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[0] ), + .O(\fsm[0]_i_7__1_n_0 )); + LUT6 #( + .INIT(64'hFFFF5D5500005D55)) + \fsm[0]_i_8__1 + (.I0(user_active_lane_2), + .I1(txresetdone_reg2), + .I2(phystatus_reg2), + .I3(rxresetdone_reg2), + .I4(\fsm_reg_n_0_[0] ), + .I5(\fsm[1]_i_7__1_n_0 ), + .O(\fsm[0]_i_8__1_n_0 )); + LUT5 #( + .INIT(32'h33330FAA)) + \fsm[0]_i_9__1 + (.I0(drp_done_reg2), + .I1(resetovrd_done_reg2), + .I2(fsm1), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[1] ), + .O(\fsm[0]_i_9__1_n_0 )); + LUT6 #( + .INIT(64'hFFE4FFE4FFE400E4)) + \fsm[1]_i_1__4 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm[1]_i_2__2_n_0 ), + .I2(\fsm[1]_i_3__1_n_0 ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm[1]_i_4__1_n_0 ), + .I5(\fsm[1]_i_5__1_n_0 ), + .O(fsm[1])); + LUT5 #( + .INIT(32'h3388F0CC)) + \fsm[1]_i_2__2 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm[1]_i_6__1_n_0 ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[2] ), + .O(\fsm[1]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'hCC5500000033F000)) + \fsm[1]_i_3__1 + (.I0(\fsm[1]_i_7__1_n_0 ), + .I1(drp_done_reg2), + .I2(\fsm[1]_i_8__1_n_0 ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[1]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h000000005FCF0000)) + \fsm[1]_i_4__1 + (.I0(resetovrd_done_reg2), + .I1(drp_done_reg2), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[3] ), + .O(\fsm[1]_i_4__1_n_0 )); + LUT6 #( + .INIT(64'h143C547C00000000)) + \fsm[1]_i_5__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(rxsync_done_reg2), + .I4(txsync_done_reg2), + .I5(\fsm_reg_n_0_[3] ), + .O(\fsm[1]_i_5__1_n_0 )); + LUT6 #( + .INIT(64'h34F7FFFFFFFFFFFF)) + \fsm[1]_i_6__1 + (.I0(qplllock_reg2), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(cplllock_reg2), + .I4(rst_idle_reg2), + .I5(\fsm_reg_n_0_[0] ), + .O(\fsm[1]_i_6__1_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \fsm[1]_i_7__1 + (.I0(txdata_wait_cnt_reg[3]), + .I1(txdata_wait_cnt_reg[1]), + .I2(txdata_wait_cnt_reg[0]), + .I3(txdata_wait_cnt_reg[2]), + .O(\fsm[1]_i_7__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF04F7FFFF)) + \fsm[1]_i_8__1 + (.I0(qplllock_reg2), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(cplllock_reg2), + .I4(drp_done_reg2), + .I5(rst_idle_reg2), + .O(\fsm[1]_i_8__1_n_0 )); + LUT6 #( + .INIT(64'hEAFFAAAAAAAAAAAA)) + \fsm[2]_i_2__1 + (.I0(\fsm[2]_i_4__1_n_0 ), + .I1(drp_done_reg2), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[2]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'hAFBAAAAAAAAAAAAA)) + \fsm[2]_i_3__1 + (.I0(\fsm[2]_i_5__1_n_0 ), + .I1(rxsync_done_reg2), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[2]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h00FA554455005544)) + \fsm[2]_i_4__1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm[3]_i_6__1_n_0 ), + .I2(pll_lock), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[0] ), + .O(\fsm[2]_i_4__1_n_0 )); + LUT6 #( + .INIT(64'h2000FFFF20000000)) + \fsm[2]_i_5__1 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(txsync_done_reg2), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm[2]_i_6__1_n_0 ), + .O(\fsm[2]_i_5__1_n_0 )); + LUT6 #( + .INIT(64'h1CDC3C3C1CDCFCFC)) + \fsm[2]_i_6__1 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(resetovrd_done_reg2), + .I4(\fsm_reg_n_0_[1] ), + .I5(fsm1), + .O(\fsm[2]_i_6__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFB0803080)) + \fsm[3]_i_2__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(drp_done_reg2), + .I5(\fsm[3]_i_4__1_n_0 ), + .O(\fsm[3]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFF8880000F888)) + \fsm[3]_i_3__1 + (.I0(\txdata_wait_cnt[3]_i_2__1_n_0 ), + .I1(fsm1), + .I2(resetovrd_done_reg2), + .I3(\sysclksel[0]_i_2__1_n_0 ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm[4]_i_2__1_n_0 ), + .O(\fsm[3]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h00000000EEFF00F0)) + \fsm[3]_i_4__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm[1]_i_8__1_n_0 ), + .I2(\fsm[3]_i_6__1_n_0 ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[3]_i_4__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFF8F8FFF8)) + \fsm[3]_i_5__1 + (.I0(out), + .I1(\fsm[0]_i_9__1_0 ), + .I2(ratedone), + .I3(rate_in_reg2[1]), + .I4(rate_in_reg2[0]), + .I5(gen3_exit), + .O(fsm1)); + LUT5 #( + .INIT(32'h00504414)) + \fsm[3]_i_6__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(rate_in_reg1[0]), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg1[1]), + .I4(rate_in_reg2[1]), + .O(\fsm[3]_i_6__1_n_0 )); + LUT6 #( + .INIT(64'hC5F0CFF0C0F0C0F0)) + \fsm[4]_i_1__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm[4]_i_2__1_n_0 ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(drp_done_reg2), + .I5(\fsm[4]_i_3__1_n_0 ), + .O(fsm[4])); + LUT4 #( + .INIT(16'h26FF)) + \fsm[4]_i_2__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(rxsync_done_reg2), + .I3(\fsm_reg_n_0_[2] ), + .O(\fsm[4]_i_2__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair161" *) + LUT2 #( + .INIT(4'h8)) + \fsm[4]_i_3__1 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[2] ), + .O(\fsm[4]_i_3__1_n_0 )); + FDSE #( + .INIT(1'b0)) + \fsm_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[0]), + .Q(\fsm_reg_n_0_[0] ), + .S(RST_CPLLRESET)); + FDSE #( + .INIT(1'b0)) + \fsm_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[1]), + .Q(\fsm_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \fsm_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[2]), + .Q(\fsm_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + MUXF7 \fsm_reg[2]_i_1__1 + (.I0(\fsm[2]_i_2__1_n_0 ), + .I1(\fsm[2]_i_3__1_n_0 ), + .O(fsm[2]), + .S(\fsm_reg_n_0_[4] )); + FDRE #( + .INIT(1'b0)) + \fsm_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[3]), + .Q(\fsm_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + MUXF7 \fsm_reg[3]_i_1__1 + (.I0(\fsm[3]_i_2__1_n_0 ), + .I1(\fsm[3]_i_3__1_n_0 ), + .O(fsm[3]), + .S(\fsm_reg_n_0_[4] )); + FDRE #( + .INIT(1'b0)) + \fsm_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[4]), + .Q(\fsm_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h04FF0400)) + gen3_exit_i_1__1 + (.I0(rate_in_reg2[0]), + .I1(rate_in_reg2[1]), + .I2(\fsm_reg_n_0_[4] ), + .I3(gen3_exit_i_2__1_n_0), + .I4(gen3_exit), + .O(gen3_exit_i_1__1_n_0)); + LUT6 #( + .INIT(64'h8000000180000000)) + gen3_exit_i_2__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[4] ), + .I5(\fsm[0]_i_5__1_n_0 ), + .O(gen3_exit_i_2__1_n_0)); + FDRE #( + .INIT(1'b0)) + gen3_exit_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_exit_i_1__1_n_0), + .Q(gen3_exit), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h3FFFFFFB00000008)) + gen3_i_1__1 + (.I0(gen3_i_2__1_n_0), + .I1(gen3_i_3__1_n_0), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[4] ), + .I5(rate_gen3_2), + .O(gen3_i_1__1_n_0)); + LUT2 #( + .INIT(4'h2)) + gen3_i_2__1 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg2[0]), + .O(gen3_i_2__1_n_0)); + LUT2 #( + .INIT(4'h8)) + gen3_i_3__1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[0] ), + .O(gen3_i_3__1_n_0)); + FDRE #( + .INIT(1'b0)) + gen3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_i_1__1_n_0), + .Q(rate_gen3_2), + .R(RST_CPLLRESET)); + LUT1 #( + .INIT(2'h1)) + \gtx_channel.gtxe2_channel_i_i_5__1 + (.I0(rate_gen3_2), + .O(rxchbonden_2)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_mmcm_lock_in), + .Q(mmcm_lock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(mmcm_lock_reg1), + .Q(mmcm_lock_reg2), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h14FF1400)) + pclk_sel_i_1__1 + (.I0(\fsm_reg_n_0_[4] ), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(pclk_sel_i_2__1_n_0), + .I4(pipe_pclk_sel_out), + .O(pclk_sel_i_1__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair153" *) + LUT5 #( + .INIT(32'h80022000)) + pclk_sel_i_2__1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .O(pclk_sel_i_2__1_n_0)); + FDRE #( + .INIT(1'b0)) + pclk_sel_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pclk_sel_i_1__1_n_0), + .Q(pipe_pclk_sel_out), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0800080008000000)) + phystatus_i_1__1 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(txratedone_i_2__1_n_0), + .I3(\fsm_reg_n_0_[0] ), + .I4(phystatus_reg2), + .I5(phystatus), + .O(phystatus_i_1__1_n_0)); + FDRE #( + .INIT(1'b0)) + phystatus_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(phystatus_i_1__1_n_0), + .Q(phystatus), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE phystatus_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_PHYSTATUS), + .Q(phystatus_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE phystatus_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(phystatus_reg1), + .Q(phystatus_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE qplllock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_QPLLLOCK), + .Q(qplllock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE qplllock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qplllock_reg1), + .Q(qplllock_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h4044FFFF40440000)) + qpllpd_i_1__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllpd), + .I5(QRST_QPLLPD_IN), + .O(qpllpd_i_1__2_n_0)); + FDRE #( + .INIT(1'b0)) + qpllpd_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllpd_i_1__2_n_0), + .Q(QRST_QPLLPD_IN), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h4044FFFF40440000)) + qpllreset_i_1__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllreset), + .I5(QRST_QPLLRESET_IN), + .O(qpllreset_i_1__2_n_0)); + FDRE #( + .INIT(1'b0)) + qpllreset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllreset_i_1__2_n_0), + .Q(QRST_QPLLRESET_IN), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair157" *) + LUT5 #( + .INIT(32'h00000080)) + rate_done_reg1_i_1__1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[1] ), + .O(USER_RATE_DONE)); + (* SOFT_HLUTNM = "soft_lutpair159" *) + LUT5 #( + .INIT(32'h00000001)) + \rate_idle_reg1[2]_i_1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[3] ), + .O(SYNC_RATE_IDLE)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rate_in_reg1_reg[0]_0 ), + .Q(rate_in_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rate_in_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_in_reg1[0]), + .Q(rate_in_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_in_reg1[1]), + .Q(rate_in_reg2[1]), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0444FFFF04440000)) + \rate_out[0]_i_1__1 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg2[0]), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\rate_out[0]_i_2__1_n_0 ), + .I5(RXRATE), + .O(\rate_out[0]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'h8002020080000200)) + \rate_out[0]_i_2__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(txpmareset0), + .O(\rate_out[0]_i_2__1_n_0 )); + LUT3 #( + .INIT(8'hBA)) + \rate_out[0]_i_3__1 + (.I0(gen3_exit), + .I1(rate_in_reg2[0]), + .I2(rate_in_reg2[1]), + .O(txpmareset0)); + FDRE #( + .INIT(1'b0)) + \rate_out_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rate_out[0]_i_1__1_n_0 ), + .Q(RXRATE), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair156" *) + LUT5 #( + .INIT(32'h08800000)) + rate_rxsync_reg1_i_1__1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[2] ), + .O(USER_RATE_RXSYNC)); + LUT6 #( + .INIT(64'hA3333333A0000000)) + ratedone_i_1__1 + (.I0(ratedone_i_2__1_n_0), + .I1(ratedone_i_3__1_n_0), + .I2(rxratedone), + .I3(phystatus), + .I4(txratedone), + .I5(ratedone), + .O(ratedone_i_1__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair155" *) + LUT5 #( + .INIT(32'h00080000)) + ratedone_i_2__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .O(ratedone_i_2__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair155" *) + LUT5 #( + .INIT(32'hFDFFFFFF)) + ratedone_i_3__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[4] ), + .O(ratedone_i_3__1_n_0)); + FDRE #( + .INIT(1'b0)) + ratedone_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(ratedone_i_1__1_n_0), + .Q(ratedone), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b1), + .Q(resetovrd_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(resetovrd_done_reg1), + .Q(resetovrd_done_reg2), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair158" *) + LUT5 #( + .INIT(32'h00000080)) + resetovrd_start_reg1_i_1__1 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[3] ), + .O(USER_RESETOVRD_START)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RST_IDLE), + .Q(rst_idle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rst_idle_reg1), + .Q(rst_idle_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxpmaresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxpmaresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxpmaresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxpmaresetdone_reg1), + .Q(rxpmaresetdone_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0800080008000000)) + rxratedone_i_1__1 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(txratedone_i_2__1_n_0), + .I3(\fsm_reg_n_0_[0] ), + .I4(rxratedone_reg2), + .I5(rxratedone), + .O(rxratedone_i_1__1_n_0)); + FDRE #( + .INIT(1'b0)) + rxratedone_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxratedone_i_1__1_n_0), + .Q(rxratedone), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxratedone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_RXRATEDONE), + .Q(rxratedone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxratedone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxratedone_reg1), + .Q(rxratedone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RXRESETDONE), + .Q(rxresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxresetdone_reg1), + .Q(rxresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxsync_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsync_done_reg1), + .Q(rxsync_done_reg2), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair156" *) + LUT5 #( + .INIT(32'h08000000)) + rxsync_start_reg1_i_1__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm_reg_n_0_[3] ), + .O(SYNC_RXSYNC_START)); + LUT6 #( + .INIT(64'h0FFFFF4F00000040)) + \sysclksel[0]_i_1__1 + (.I0(rate_in_reg2[0]), + .I1(rate_in_reg2[1]), + .I2(\sysclksel[0]_i_2__1_n_0 ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[4] ), + .I5(RXSYSCLKSEL), + .O(\sysclksel[0]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair160" *) + LUT3 #( + .INIT(8'h80)) + \sysclksel[0]_i_2__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .O(\sysclksel[0]_i_2__1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sysclksel_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\sysclksel[0]_i_1__1_n_0 ), + .Q(RXSYSCLKSEL), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hB333000000000000)) + \txdata_wait_cnt[0]_i_1__1 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2__1_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3__1_n_0 ), + .O(p_0_in__0[0])); + LUT6 #( + .INIT(64'hE666000000000000)) + \txdata_wait_cnt[1]_i_1__1 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2__1_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3__1_n_0 ), + .O(p_0_in__0[1])); + LUT6 #( + .INIT(64'hF878000000000000)) + \txdata_wait_cnt[2]_i_1__1 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2__1_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3__1_n_0 ), + .O(p_0_in__0[2])); + LUT6 #( + .INIT(64'hFF80000000000000)) + \txdata_wait_cnt[3]_i_1__1 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2__1_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3__1_n_0 ), + .O(p_0_in__0[3])); + (* SOFT_HLUTNM = "soft_lutpair160" *) + LUT3 #( + .INIT(8'h40)) + \txdata_wait_cnt[3]_i_2__1 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\txdata_wait_cnt[3]_i_2__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair152" *) + LUT2 #( + .INIT(4'h2)) + \txdata_wait_cnt[3]_i_3__1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .O(\txdata_wait_cnt[3]_i_3__1_n_0 )); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[0]), + .Q(txdata_wait_cnt_reg[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[1]), + .Q(txdata_wait_cnt_reg[1]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[2]), + .Q(txdata_wait_cnt_reg[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[3]), + .Q(txdata_wait_cnt_reg[3]), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h00F2FFFF00F20000)) + txpmareset_i_1__1 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg2[0]), + .I2(gen3_exit), + .I3(\fsm_reg_n_0_[3] ), + .I4(txpmareset_i_2__1_n_0), + .I5(rate_txpmareset_2), + .O(txpmareset_i_1__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair154" *) + LUT5 #( + .INIT(32'h80004200)) + txpmareset_i_2__1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[4] ), + .O(txpmareset_i_2__1_n_0)); + FDRE #( + .INIT(1'b0)) + txpmareset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpmareset_i_1__1_n_0), + .Q(rate_txpmareset_2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0800080008000000)) + txratedone_i_1__1 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(txratedone_i_2__1_n_0), + .I3(\fsm_reg_n_0_[0] ), + .I4(txratedone_reg2), + .I5(txratedone), + .O(txratedone_i_1__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair161" *) + LUT2 #( + .INIT(4'hE)) + txratedone_i_2__1 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[1] ), + .O(txratedone_i_2__1_n_0)); + FDRE #( + .INIT(1'b0)) + txratedone_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txratedone_i_1__1_n_0), + .Q(txratedone), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txratedone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_TXRATEDONE), + .Q(txratedone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txratedone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txratedone_reg1), + .Q(txratedone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_TXRESETDONE), + .Q(txresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txresetdone_reg1), + .Q(txresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_TXSYNC_DONE), + .Q(txsync_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_done_reg1), + .Q(txsync_done_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hFFFFFFFF00004000)) + txsync_start_reg1_i_1__1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[2] ), + .I5(RST_TXSYNC_START), + .O(SYNC_TXSYNC_START)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_rate" *) +module pcie_7x_0_pcie_7x_0_pipe_rate_52 + (SYNC_TXSYNC_START, + rxchbonden_3, + rate_gen3_3, + RATE_DRP_START, + RATE_DRP_X16X20_MODE, + RATE_DRP_X16, + USER_RATE_RXSYNC, + SYNC_RXSYNC_START, + USER_RATE_DONE, + USER_RESETOVRD_START, + SYNC_RATE_IDLE, + rate_txpmareset_3, + RXSYSCLKSEL, + pipe_pclk_sel_out, + RXRATE, + QRST_QPLLPD_IN, + rate_cpllpd_3, + QRST_QPLLRESET_IN, + rate_cpllreset_3, + RST_TXSYNC_START, + RST_CPLLRESET, + pipe_pclk_in, + \rate_in_reg1_reg[0]_0 , + RST_IDLE, + QRST_CPLLLOCK, + QPLL_QPLLLOCK, + RATE_DRP_DONE, + pipe_mmcm_lock_in, + RATE_PHYSTATUS, + USER_TXRESETDONE, + USER_RXRESETDONE, + RATE_TXRATEDONE, + RATE_RXRATEDONE, + RATE_TXSYNC_DONE, + user_active_lane_3, + out, + \fsm[0]_i_9__2_0 ); + output SYNC_TXSYNC_START; + output rxchbonden_3; + output rate_gen3_3; + output RATE_DRP_START; + output RATE_DRP_X16X20_MODE; + output RATE_DRP_X16; + output USER_RATE_RXSYNC; + output SYNC_RXSYNC_START; + output USER_RATE_DONE; + output USER_RESETOVRD_START; + output SYNC_RATE_IDLE; + output rate_txpmareset_3; + output [0:0]RXSYSCLKSEL; + output [0:0]pipe_pclk_sel_out; + output [0:0]RXRATE; + output [0:0]QRST_QPLLPD_IN; + output rate_cpllpd_3; + output [0:0]QRST_QPLLRESET_IN; + output rate_cpllreset_3; + input RST_TXSYNC_START; + input RST_CPLLRESET; + input pipe_pclk_in; + input [0:0]\rate_in_reg1_reg[0]_0 ; + input RST_IDLE; + input [0:0]QRST_CPLLLOCK; + input QPLL_QPLLLOCK; + input RATE_DRP_DONE; + input pipe_mmcm_lock_in; + input RATE_PHYSTATUS; + input USER_TXRESETDONE; + input USER_RXRESETDONE; + input RATE_TXRATEDONE; + input RATE_RXRATEDONE; + input RATE_TXSYNC_DONE; + input user_active_lane_3; + input out; + input \fsm[0]_i_9__2_0 ; + + wire QPLL_QPLLLOCK; + wire [0:0]QRST_CPLLLOCK; + wire [0:0]QRST_QPLLPD_IN; + wire [0:0]QRST_QPLLRESET_IN; + wire RATE_DRP_DONE; + wire RATE_DRP_START; + wire RATE_DRP_X16; + wire RATE_DRP_X16X20_MODE; + wire RATE_PHYSTATUS; + wire RATE_RXRATEDONE; + wire RATE_TXRATEDONE; + wire RATE_TXSYNC_DONE; + wire RST_CPLLRESET; + wire RST_IDLE; + wire RST_TXSYNC_START; + wire [0:0]RXRATE; + wire [0:0]RXSYSCLKSEL; + wire SYNC_RATE_IDLE; + wire SYNC_RXSYNC_START; + wire SYNC_TXSYNC_START; + wire USER_RATE_DONE; + wire USER_RATE_RXSYNC; + wire USER_RESETOVRD_START; + wire USER_RXRESETDONE; + wire USER_TXRESETDONE; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire cplllock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire cplllock_reg2; + wire cpllpd_i_1__2_n_0; + wire cpllreset_i_1__3_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg2; + wire drp_start_i_1__2_n_0; + wire drp_x16_i_1__2_n_0; + wire drp_x16x20_mode_i_1__2_n_0; + wire [4:0]fsm; + wire fsm1; + wire \fsm[0]_i_10__2_n_0 ; + wire \fsm[0]_i_11__2_n_0 ; + wire \fsm[0]_i_12__2_n_0 ; + wire \fsm[0]_i_2__6_n_0 ; + wire \fsm[0]_i_3__2_n_0 ; + wire \fsm[0]_i_4__2_n_0 ; + wire \fsm[0]_i_5__2_n_0 ; + wire \fsm[0]_i_7__2_n_0 ; + wire \fsm[0]_i_8__2_n_0 ; + wire \fsm[0]_i_9__2_0 ; + wire \fsm[0]_i_9__2_n_0 ; + wire \fsm[1]_i_2__3_n_0 ; + wire \fsm[1]_i_3__2_n_0 ; + wire \fsm[1]_i_4__2_n_0 ; + wire \fsm[1]_i_5__2_n_0 ; + wire \fsm[1]_i_6__2_n_0 ; + wire \fsm[1]_i_7__2_n_0 ; + wire \fsm[1]_i_8__2_n_0 ; + wire \fsm[2]_i_2__2_n_0 ; + wire \fsm[2]_i_3__2_n_0 ; + wire \fsm[2]_i_4__2_n_0 ; + wire \fsm[2]_i_5__2_n_0 ; + wire \fsm[2]_i_6__2_n_0 ; + wire \fsm[3]_i_2__2_n_0 ; + wire \fsm[3]_i_3__2_n_0 ; + wire \fsm[3]_i_4__2_n_0 ; + wire \fsm[3]_i_6__2_n_0 ; + wire \fsm[4]_i_2__2_n_0 ; + wire \fsm[4]_i_3__2_n_0 ; + wire \fsm_reg_n_0_[0] ; + wire \fsm_reg_n_0_[1] ; + wire \fsm_reg_n_0_[2] ; + wire \fsm_reg_n_0_[3] ; + wire \fsm_reg_n_0_[4] ; + wire gen3_exit; + wire gen3_exit_i_1__2_n_0; + wire gen3_exit_i_2__2_n_0; + wire gen3_i_1__2_n_0; + wire gen3_i_2__2_n_0; + wire gen3_i_3__2_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2; + wire out; + wire [3:0]p_0_in__0; + wire pclk_sel_i_1__2_n_0; + wire pclk_sel_i_2__2_n_0; + wire phystatus; + wire phystatus_i_1__2_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire phystatus_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire phystatus_reg2; + wire pipe_mmcm_lock_in; + wire pipe_pclk_in; + wire [0:0]pipe_pclk_sel_out; + wire pll_lock; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg2; + wire qpllpd; + wire qpllpd_i_1__3_n_0; + wire qpllreset; + wire qpllreset_i_1__3_n_0; + wire rate_cpllpd_3; + wire rate_cpllreset_3; + wire rate_gen3_3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_in_reg1; + wire [0:0]\rate_in_reg1_reg[0]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_in_reg2; + wire \rate_out[0]_i_1__2_n_0 ; + wire \rate_out[0]_i_2__2_n_0 ; + wire rate_txpmareset_3; + wire ratedone; + wire ratedone_i_1__2_n_0; + wire ratedone_i_2__2_n_0; + wire ratedone_i_3__2_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_done_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg2; + wire rxchbonden_3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxpmaresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxpmaresetdone_reg2; + wire rxratedone; + wire rxratedone_i_1__2_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxratedone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxratedone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_done_reg2; + wire \sysclksel[0]_i_1__2_n_0 ; + wire \sysclksel[0]_i_2__2_n_0 ; + wire \txdata_wait_cnt[3]_i_2__2_n_0 ; + wire \txdata_wait_cnt[3]_i_3__2_n_0 ; + wire [3:0]txdata_wait_cnt_reg; + wire txpmareset0; + wire txpmareset_i_1__2_n_0; + wire txpmareset_i_2__2_n_0; + wire txratedone; + wire txratedone_i_1__2_n_0; + wire txratedone_i_2__2_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txratedone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txratedone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_done_reg2; + wire user_active_lane_3; + + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE cplllock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(QRST_CPLLLOCK), + .Q(cplllock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE cplllock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cplllock_reg1), + .Q(cplllock_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0400FFFF04000000)) + cpllpd_i_1__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllpd), + .I5(rate_cpllpd_3), + .O(cpllpd_i_1__2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair194" *) + LUT5 #( + .INIT(32'h80000900)) + cpllpd_i_2__2 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[2] ), + .O(qpllpd)); + FDRE #( + .INIT(1'b0)) + cpllpd_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cpllpd_i_1__2_n_0), + .Q(rate_cpllpd_3), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0400FFFF04000000)) + cpllreset_i_1__3 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllreset), + .I5(rate_cpllreset_3), + .O(cpllreset_i_1__3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair195" *) + LUT5 #( + .INIT(32'h80001004)) + cpllreset_i_2__3 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm_reg_n_0_[0] ), + .O(qpllreset)); + FDRE #( + .INIT(1'b0)) + cpllreset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cpllreset_i_1__3_n_0), + .Q(rate_cpllreset_3), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE drp_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_DRP_DONE), + .Q(drp_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE drp_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_done_reg1), + .Q(drp_done_reg2), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair198" *) + LUT5 #( + .INIT(32'h08420100)) + drp_start_i_1__2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[0] ), + .O(drp_start_i_1__2_n_0)); + FDRE #( + .INIT(1'b0)) + drp_start_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_start_i_1__2_n_0), + .Q(RATE_DRP_START), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair199" *) + LUT5 #( + .INIT(32'h20100014)) + drp_x16_i_1__2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .O(drp_x16_i_1__2_n_0)); + FDRE #( + .INIT(1'b0)) + drp_x16_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_x16_i_1__2_n_0), + .Q(RATE_DRP_X16), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair200" *) + LUT5 #( + .INIT(32'h20080074)) + drp_x16x20_mode_i_1__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[1] ), + .O(drp_x16x20_mode_i_1__2_n_0)); + FDRE #( + .INIT(1'b0)) + drp_x16x20_mode_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_x16x20_mode_i_1__2_n_0), + .Q(RATE_DRP_X16X20_MODE), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0901595100000000)) + \fsm[0]_i_10__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(rxsync_done_reg2), + .I4(txsync_done_reg2), + .I5(\fsm_reg_n_0_[3] ), + .O(\fsm[0]_i_10__2_n_0 )); + LUT6 #( + .INIT(64'h1101111101000110)) + \fsm[0]_i_11__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(rxpmaresetdone_reg2), + .I5(drp_done_reg2), + .O(\fsm[0]_i_11__2_n_0 )); + LUT5 #( + .INIT(32'h20202320)) + \fsm[0]_i_12__2 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(mmcm_lock_reg2), + .I4(rxpmaresetdone_reg2), + .O(\fsm[0]_i_12__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair193" *) + LUT5 #( + .INIT(32'hFFFF3210)) + \fsm[0]_i_1__6 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm[0]_i_2__6_n_0 ), + .I3(\fsm[0]_i_3__2_n_0 ), + .I4(\fsm[0]_i_4__2_n_0 ), + .O(fsm[0])); + LUT6 #( + .INIT(64'h0F0F3F3F47444744)) + \fsm[0]_i_2__6 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm[0]_i_5__2_n_0 ), + .I4(pll_lock), + .I5(\fsm_reg_n_0_[1] ), + .O(\fsm[0]_i_2__6_n_0 )); + LUT6 #( + .INIT(64'hF3F3AAAAFF00AAAA)) + \fsm[0]_i_3__2 + (.I0(\fsm[0]_i_7__2_n_0 ), + .I1(\fsm_reg_n_0_[0] ), + .I2(drp_done_reg2), + .I3(\fsm[0]_i_8__2_n_0 ), + .I4(\fsm_reg_n_0_[2] ), + .I5(\fsm_reg_n_0_[1] ), + .O(\fsm[0]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFF4000000000)) + \fsm[0]_i_4__2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm[0]_i_9__2_n_0 ), + .I3(\fsm[0]_i_10__2_n_0 ), + .I4(\fsm[0]_i_11__2_n_0 ), + .I5(\fsm_reg_n_0_[4] ), + .O(\fsm[0]_i_4__2_n_0 )); + LUT4 #( + .INIT(16'h6FF6)) + \fsm[0]_i_5__2 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg1[1]), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg1[0]), + .O(\fsm[0]_i_5__2_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \fsm[0]_i_6__2 + (.I0(qplllock_reg2), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(cplllock_reg2), + .O(pll_lock)); + LUT6 #( + .INIT(64'hAAAAAAAAEAAAAAAA)) + \fsm[0]_i_7__2 + (.I0(\fsm[0]_i_12__2_n_0 ), + .I1(pll_lock), + .I2(rst_idle_reg2), + .I3(drp_done_reg2), + .I4(\fsm_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[0] ), + .O(\fsm[0]_i_7__2_n_0 )); + LUT6 #( + .INIT(64'hFFFF5D5500005D55)) + \fsm[0]_i_8__2 + (.I0(user_active_lane_3), + .I1(txresetdone_reg2), + .I2(phystatus_reg2), + .I3(rxresetdone_reg2), + .I4(\fsm_reg_n_0_[0] ), + .I5(\fsm[1]_i_7__2_n_0 ), + .O(\fsm[0]_i_8__2_n_0 )); + LUT5 #( + .INIT(32'h33330FAA)) + \fsm[0]_i_9__2 + (.I0(drp_done_reg2), + .I1(resetovrd_done_reg2), + .I2(fsm1), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[1] ), + .O(\fsm[0]_i_9__2_n_0 )); + LUT6 #( + .INIT(64'hFFE4FFE4FFE400E4)) + \fsm[1]_i_1__6 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm[1]_i_2__3_n_0 ), + .I2(\fsm[1]_i_3__2_n_0 ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm[1]_i_4__2_n_0 ), + .I5(\fsm[1]_i_5__2_n_0 ), + .O(fsm[1])); + LUT5 #( + .INIT(32'h3388F0CC)) + \fsm[1]_i_2__3 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm[1]_i_6__2_n_0 ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[2] ), + .O(\fsm[1]_i_2__3_n_0 )); + LUT6 #( + .INIT(64'hCC5500000033F000)) + \fsm[1]_i_3__2 + (.I0(\fsm[1]_i_7__2_n_0 ), + .I1(drp_done_reg2), + .I2(\fsm[1]_i_8__2_n_0 ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[1]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'h000000005FCF0000)) + \fsm[1]_i_4__2 + (.I0(resetovrd_done_reg2), + .I1(drp_done_reg2), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[3] ), + .O(\fsm[1]_i_4__2_n_0 )); + LUT6 #( + .INIT(64'h143C547C00000000)) + \fsm[1]_i_5__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(rxsync_done_reg2), + .I4(txsync_done_reg2), + .I5(\fsm_reg_n_0_[3] ), + .O(\fsm[1]_i_5__2_n_0 )); + LUT6 #( + .INIT(64'h34F7FFFFFFFFFFFF)) + \fsm[1]_i_6__2 + (.I0(qplllock_reg2), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(cplllock_reg2), + .I4(rst_idle_reg2), + .I5(\fsm_reg_n_0_[0] ), + .O(\fsm[1]_i_6__2_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \fsm[1]_i_7__2 + (.I0(txdata_wait_cnt_reg[3]), + .I1(txdata_wait_cnt_reg[1]), + .I2(txdata_wait_cnt_reg[0]), + .I3(txdata_wait_cnt_reg[2]), + .O(\fsm[1]_i_7__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF04F7FFFF)) + \fsm[1]_i_8__2 + (.I0(qplllock_reg2), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(cplllock_reg2), + .I4(drp_done_reg2), + .I5(rst_idle_reg2), + .O(\fsm[1]_i_8__2_n_0 )); + LUT6 #( + .INIT(64'hEAFFAAAAAAAAAAAA)) + \fsm[2]_i_2__2 + (.I0(\fsm[2]_i_4__2_n_0 ), + .I1(drp_done_reg2), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[2]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'hAFBAAAAAAAAAAAAA)) + \fsm[2]_i_3__2 + (.I0(\fsm[2]_i_5__2_n_0 ), + .I1(rxsync_done_reg2), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[2]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'h00FA554455005544)) + \fsm[2]_i_4__2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm[3]_i_6__2_n_0 ), + .I2(pll_lock), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[0] ), + .O(\fsm[2]_i_4__2_n_0 )); + LUT6 #( + .INIT(64'h2000FFFF20000000)) + \fsm[2]_i_5__2 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(txsync_done_reg2), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm[2]_i_6__2_n_0 ), + .O(\fsm[2]_i_5__2_n_0 )); + LUT6 #( + .INIT(64'h1CDC3C3C1CDCFCFC)) + \fsm[2]_i_6__2 + (.I0(drp_done_reg2), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(resetovrd_done_reg2), + .I4(\fsm_reg_n_0_[1] ), + .I5(fsm1), + .O(\fsm[2]_i_6__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFB0803080)) + \fsm[3]_i_2__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(drp_done_reg2), + .I5(\fsm[3]_i_4__2_n_0 ), + .O(\fsm[3]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF8880000F888)) + \fsm[3]_i_3__2 + (.I0(\txdata_wait_cnt[3]_i_2__2_n_0 ), + .I1(fsm1), + .I2(resetovrd_done_reg2), + .I3(\sysclksel[0]_i_2__2_n_0 ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm[4]_i_2__2_n_0 ), + .O(\fsm[3]_i_3__2_n_0 )); + LUT6 #( + .INIT(64'h00000000EEFF00F0)) + \fsm[3]_i_4__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm[1]_i_8__2_n_0 ), + .I2(\fsm[3]_i_6__2_n_0 ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(\fsm_reg_n_0_[2] ), + .O(\fsm[3]_i_4__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFF8F8FFF8)) + \fsm[3]_i_5__2 + (.I0(out), + .I1(\fsm[0]_i_9__2_0 ), + .I2(ratedone), + .I3(rate_in_reg2[1]), + .I4(rate_in_reg2[0]), + .I5(gen3_exit), + .O(fsm1)); + LUT5 #( + .INIT(32'h00504414)) + \fsm[3]_i_6__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(rate_in_reg1[0]), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg1[1]), + .I4(rate_in_reg2[1]), + .O(\fsm[3]_i_6__2_n_0 )); + LUT6 #( + .INIT(64'hC5F0CFF0C0F0C0F0)) + \fsm[4]_i_1__3 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm[4]_i_2__2_n_0 ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(drp_done_reg2), + .I5(\fsm[4]_i_3__2_n_0 ), + .O(fsm[4])); + LUT4 #( + .INIT(16'h26FF)) + \fsm[4]_i_2__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(rxsync_done_reg2), + .I3(\fsm_reg_n_0_[2] ), + .O(\fsm[4]_i_2__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair202" *) + LUT2 #( + .INIT(4'h8)) + \fsm[4]_i_3__2 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[2] ), + .O(\fsm[4]_i_3__2_n_0 )); + FDSE #( + .INIT(1'b0)) + \fsm_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[0]), + .Q(\fsm_reg_n_0_[0] ), + .S(RST_CPLLRESET)); + FDSE #( + .INIT(1'b0)) + \fsm_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[1]), + .Q(\fsm_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \fsm_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[2]), + .Q(\fsm_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + MUXF7 \fsm_reg[2]_i_1__2 + (.I0(\fsm[2]_i_2__2_n_0 ), + .I1(\fsm[2]_i_3__2_n_0 ), + .O(fsm[2]), + .S(\fsm_reg_n_0_[4] )); + FDRE #( + .INIT(1'b0)) + \fsm_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[3]), + .Q(\fsm_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + MUXF7 \fsm_reg[3]_i_1__2 + (.I0(\fsm[3]_i_2__2_n_0 ), + .I1(\fsm[3]_i_3__2_n_0 ), + .O(fsm[3]), + .S(\fsm_reg_n_0_[4] )); + FDRE #( + .INIT(1'b0)) + \fsm_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fsm[4]), + .Q(\fsm_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h04FF0400)) + gen3_exit_i_1__2 + (.I0(rate_in_reg2[0]), + .I1(rate_in_reg2[1]), + .I2(\fsm_reg_n_0_[4] ), + .I3(gen3_exit_i_2__2_n_0), + .I4(gen3_exit), + .O(gen3_exit_i_1__2_n_0)); + LUT6 #( + .INIT(64'h8000000180000000)) + gen3_exit_i_2__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[4] ), + .I5(\fsm[0]_i_5__2_n_0 ), + .O(gen3_exit_i_2__2_n_0)); + FDRE #( + .INIT(1'b0)) + gen3_exit_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_exit_i_1__2_n_0), + .Q(gen3_exit), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h3FFFFFFB00000008)) + gen3_i_1__2 + (.I0(gen3_i_2__2_n_0), + .I1(gen3_i_3__2_n_0), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[4] ), + .I5(rate_gen3_3), + .O(gen3_i_1__2_n_0)); + LUT2 #( + .INIT(4'h2)) + gen3_i_2__2 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg2[0]), + .O(gen3_i_2__2_n_0)); + LUT2 #( + .INIT(4'h8)) + gen3_i_3__2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[0] ), + .O(gen3_i_3__2_n_0)); + FDRE #( + .INIT(1'b0)) + gen3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_i_1__2_n_0), + .Q(rate_gen3_3), + .R(RST_CPLLRESET)); + LUT1 #( + .INIT(2'h1)) + \gtx_channel.gtxe2_channel_i_i_5__2 + (.I0(rate_gen3_3), + .O(rxchbonden_3)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_mmcm_lock_in), + .Q(mmcm_lock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(mmcm_lock_reg1), + .Q(mmcm_lock_reg2), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h14FF1400)) + pclk_sel_i_1__2 + (.I0(\fsm_reg_n_0_[4] ), + .I1(rate_in_reg2[1]), + .I2(rate_in_reg2[0]), + .I3(pclk_sel_i_2__2_n_0), + .I4(pipe_pclk_sel_out), + .O(pclk_sel_i_1__2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair194" *) + LUT5 #( + .INIT(32'h80022000)) + pclk_sel_i_2__2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .O(pclk_sel_i_2__2_n_0)); + FDRE #( + .INIT(1'b0)) + pclk_sel_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pclk_sel_i_1__2_n_0), + .Q(pipe_pclk_sel_out), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0800080008000000)) + phystatus_i_1__2 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(txratedone_i_2__2_n_0), + .I3(\fsm_reg_n_0_[0] ), + .I4(phystatus_reg2), + .I5(phystatus), + .O(phystatus_i_1__2_n_0)); + FDRE #( + .INIT(1'b0)) + phystatus_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(phystatus_i_1__2_n_0), + .Q(phystatus), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE phystatus_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_PHYSTATUS), + .Q(phystatus_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE phystatus_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(phystatus_reg1), + .Q(phystatus_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE qplllock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(QPLL_QPLLLOCK), + .Q(qplllock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE qplllock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qplllock_reg1), + .Q(qplllock_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h4044FFFF40440000)) + qpllpd_i_1__3 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllpd), + .I5(QRST_QPLLPD_IN), + .O(qpllpd_i_1__3_n_0)); + FDRE #( + .INIT(1'b0)) + qpllpd_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllpd_i_1__3_n_0), + .Q(QRST_QPLLPD_IN), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h4044FFFF40440000)) + qpllreset_i_1__3 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(rate_in_reg2[0]), + .I3(rate_in_reg2[1]), + .I4(qpllreset), + .I5(QRST_QPLLRESET_IN), + .O(qpllreset_i_1__3_n_0)); + FDRE #( + .INIT(1'b0)) + qpllreset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllreset_i_1__3_n_0), + .Q(QRST_QPLLRESET_IN), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair198" *) + LUT5 #( + .INIT(32'h00000080)) + rate_done_reg1_i_1__2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[1] ), + .O(USER_RATE_DONE)); + (* SOFT_HLUTNM = "soft_lutpair200" *) + LUT5 #( + .INIT(32'h00000001)) + \rate_idle_reg1[3]_i_1 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[3] ), + .O(SYNC_RATE_IDLE)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rate_in_reg1_reg[0]_0 ), + .Q(rate_in_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rate_in_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_in_reg1[0]), + .Q(rate_in_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_in_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_in_reg1[1]), + .Q(rate_in_reg2[1]), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0444FFFF04440000)) + \rate_out[0]_i_1__2 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg2[0]), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\rate_out[0]_i_2__2_n_0 ), + .I5(RXRATE), + .O(\rate_out[0]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'h8002020080000200)) + \rate_out[0]_i_2__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm_reg_n_0_[3] ), + .I5(txpmareset0), + .O(\rate_out[0]_i_2__2_n_0 )); + LUT3 #( + .INIT(8'hBA)) + \rate_out[0]_i_3__2 + (.I0(gen3_exit), + .I1(rate_in_reg2[0]), + .I2(rate_in_reg2[1]), + .O(txpmareset0)); + FDRE #( + .INIT(1'b0)) + \rate_out_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rate_out[0]_i_1__2_n_0 ), + .Q(RXRATE), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair197" *) + LUT5 #( + .INIT(32'h08800000)) + rate_rxsync_reg1_i_1__2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[2] ), + .O(USER_RATE_RXSYNC)); + LUT6 #( + .INIT(64'hA3333333A0000000)) + ratedone_i_1__2 + (.I0(ratedone_i_2__2_n_0), + .I1(ratedone_i_3__2_n_0), + .I2(rxratedone), + .I3(phystatus), + .I4(txratedone), + .I5(ratedone), + .O(ratedone_i_1__2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair196" *) + LUT5 #( + .INIT(32'h00080000)) + ratedone_i_2__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[4] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[0] ), + .O(ratedone_i_2__2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair196" *) + LUT5 #( + .INIT(32'hFDFFFFFF)) + ratedone_i_3__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[4] ), + .O(ratedone_i_3__2_n_0)); + FDRE #( + .INIT(1'b0)) + ratedone_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(ratedone_i_1__2_n_0), + .Q(ratedone), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b1), + .Q(resetovrd_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(resetovrd_done_reg1), + .Q(resetovrd_done_reg2), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair199" *) + LUT5 #( + .INIT(32'h00000080)) + resetovrd_start_reg1_i_1__2 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[0] ), + .I4(\fsm_reg_n_0_[3] ), + .O(USER_RESETOVRD_START)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RST_IDLE), + .Q(rst_idle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rst_idle_reg1), + .Q(rst_idle_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxpmaresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxpmaresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxpmaresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxpmaresetdone_reg1), + .Q(rxpmaresetdone_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0800080008000000)) + rxratedone_i_1__2 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(txratedone_i_2__2_n_0), + .I3(\fsm_reg_n_0_[0] ), + .I4(rxratedone_reg2), + .I5(rxratedone), + .O(rxratedone_i_1__2_n_0)); + FDRE #( + .INIT(1'b0)) + rxratedone_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxratedone_i_1__2_n_0), + .Q(rxratedone), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxratedone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_RXRATEDONE), + .Q(rxratedone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxratedone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxratedone_reg1), + .Q(rxratedone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RXRESETDONE), + .Q(rxresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxresetdone_reg1), + .Q(rxresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxsync_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsync_done_reg1), + .Q(rxsync_done_reg2), + .R(RST_CPLLRESET)); + (* SOFT_HLUTNM = "soft_lutpair197" *) + LUT5 #( + .INIT(32'h08000000)) + rxsync_start_reg1_i_1__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm_reg_n_0_[3] ), + .O(SYNC_RXSYNC_START)); + LUT6 #( + .INIT(64'h0FFFFF4F00000040)) + \sysclksel[0]_i_1__2 + (.I0(rate_in_reg2[0]), + .I1(rate_in_reg2[1]), + .I2(\sysclksel[0]_i_2__2_n_0 ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[4] ), + .I5(RXSYSCLKSEL), + .O(\sysclksel[0]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair201" *) + LUT3 #( + .INIT(8'h80)) + \sysclksel[0]_i_2__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[0] ), + .O(\sysclksel[0]_i_2__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \sysclksel_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\sysclksel[0]_i_1__2_n_0 ), + .Q(RXSYSCLKSEL), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hB333000000000000)) + \txdata_wait_cnt[0]_i_1__2 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2__2_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3__2_n_0 ), + .O(p_0_in__0[0])); + LUT6 #( + .INIT(64'hE666000000000000)) + \txdata_wait_cnt[1]_i_1__2 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2__2_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3__2_n_0 ), + .O(p_0_in__0[1])); + LUT6 #( + .INIT(64'hF878000000000000)) + \txdata_wait_cnt[2]_i_1__2 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2__2_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3__2_n_0 ), + .O(p_0_in__0[2])); + LUT6 #( + .INIT(64'hFF80000000000000)) + \txdata_wait_cnt[3]_i_1__2 + (.I0(txdata_wait_cnt_reg[1]), + .I1(txdata_wait_cnt_reg[0]), + .I2(txdata_wait_cnt_reg[2]), + .I3(txdata_wait_cnt_reg[3]), + .I4(\txdata_wait_cnt[3]_i_2__2_n_0 ), + .I5(\txdata_wait_cnt[3]_i_3__2_n_0 ), + .O(p_0_in__0[3])); + (* SOFT_HLUTNM = "soft_lutpair201" *) + LUT3 #( + .INIT(8'h40)) + \txdata_wait_cnt[3]_i_2__2 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\txdata_wait_cnt[3]_i_2__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair193" *) + LUT2 #( + .INIT(4'h2)) + \txdata_wait_cnt[3]_i_3__2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[4] ), + .O(\txdata_wait_cnt[3]_i_3__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[0]), + .Q(txdata_wait_cnt_reg[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[1]), + .Q(txdata_wait_cnt_reg[1]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[2]), + .Q(txdata_wait_cnt_reg[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \txdata_wait_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[3]), + .Q(txdata_wait_cnt_reg[3]), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h00F2FFFF00F20000)) + txpmareset_i_1__2 + (.I0(rate_in_reg2[1]), + .I1(rate_in_reg2[0]), + .I2(gen3_exit), + .I3(\fsm_reg_n_0_[3] ), + .I4(txpmareset_i_2__2_n_0), + .I5(rate_txpmareset_3), + .O(txpmareset_i_1__2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair195" *) + LUT5 #( + .INIT(32'h80004200)) + txpmareset_i_2__2 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[4] ), + .O(txpmareset_i_2__2_n_0)); + FDRE #( + .INIT(1'b0)) + txpmareset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpmareset_i_1__2_n_0), + .Q(rate_txpmareset_3), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0800080008000000)) + txratedone_i_1__2 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[2] ), + .I2(txratedone_i_2__2_n_0), + .I3(\fsm_reg_n_0_[0] ), + .I4(txratedone_reg2), + .I5(txratedone), + .O(txratedone_i_1__2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair202" *) + LUT2 #( + .INIT(4'hE)) + txratedone_i_2__2 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[1] ), + .O(txratedone_i_2__2_n_0)); + FDRE #( + .INIT(1'b0)) + txratedone_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txratedone_i_1__2_n_0), + .Q(txratedone), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txratedone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_TXRATEDONE), + .Q(txratedone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txratedone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txratedone_reg1), + .Q(txratedone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_TXRESETDONE), + .Q(txresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txresetdone_reg1), + .Q(txresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(RATE_TXSYNC_DONE), + .Q(txsync_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_done_reg1), + .Q(txsync_done_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hFFFFFFFF00004000)) + txsync_start_reg1_i_1__2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[3] ), + .I4(\fsm_reg_n_0_[2] ), + .I5(RST_TXSYNC_START), + .O(SYNC_TXSYNC_START)); +endmodule + +module pcie_7x_0_pcie_7x_0_pipe_reset + (SS, + Q, + RST_CPLLRESET, + RST_RXUSRCLK_RESET, + RST_DCLK_RESET, + DRP_GTXRESET, + rst_userrdy, + pipe_pclk_in, + pipe_mmcm_lock_in, + D, + QRST_CPLLLOCK, + \rate_idle_reg1_reg[3]_0 , + \drp_done_reg1_reg[3]_0 , + \phystatus_reg1_reg[3]_0 , + \txsync_done_reg1_reg[3]_0 , + pipe_rxusrclk_in, + pipe_dclk_in, + QRST_IDLE, + \rxcdrlock_reg1_reg[3]_0 , + out); + output [0:0]SS; + output [1:0]Q; + output RST_CPLLRESET; + output RST_RXUSRCLK_RESET; + output RST_DCLK_RESET; + output DRP_GTXRESET; + output rst_userrdy; + input pipe_pclk_in; + input pipe_mmcm_lock_in; + input [3:0]D; + input [3:0]QRST_CPLLLOCK; + input [3:0]\rate_idle_reg1_reg[3]_0 ; + input [3:0]\drp_done_reg1_reg[3]_0 ; + input [3:0]\phystatus_reg1_reg[3]_0 ; + input [3:0]\txsync_done_reg1_reg[3]_0 ; + input pipe_rxusrclk_in; + input pipe_dclk_in; + input QRST_IDLE; + input [3:0]\rxcdrlock_reg1_reg[3]_0 ; + input out; + + wire [3:0]D; + wire DRP_GTXRESET; + wire \FSM_onehot_fsm[0]_i_1_n_0 ; + wire \FSM_onehot_fsm[10]_i_1_n_0 ; + wire \FSM_onehot_fsm[13]_i_1_n_0 ; + wire \FSM_onehot_fsm[14]_i_2_n_0 ; + wire \FSM_onehot_fsm[14]_i_3_n_0 ; + wire \FSM_onehot_fsm[14]_i_4_n_0 ; + wire \FSM_onehot_fsm[1]_i_1_n_0 ; + wire \FSM_onehot_fsm[1]_i_2_n_0 ; + wire \FSM_onehot_fsm[2]_i_1_n_0 ; + wire \FSM_onehot_fsm[2]_i_2_n_0 ; + wire \FSM_onehot_fsm[3]_i_1_n_0 ; + wire \FSM_onehot_fsm[4]_i_1_n_0 ; + wire \FSM_onehot_fsm[4]_i_2_n_0 ; + wire \FSM_onehot_fsm[5]_i_1_n_0 ; + wire \FSM_onehot_fsm[8]_i_1_n_0 ; + wire \FSM_onehot_fsm[8]_i_2_n_0 ; + wire \FSM_onehot_fsm[8]_i_3_n_0 ; + wire \FSM_onehot_fsm[9]_i_1_n_0 ; + wire \FSM_onehot_fsm_reg_n_0_[0] ; + wire \FSM_onehot_fsm_reg_n_0_[13] ; + wire \FSM_onehot_fsm_reg_n_0_[14] ; + wire \FSM_onehot_fsm_reg_n_0_[1] ; + wire \FSM_onehot_fsm_reg_n_0_[4] ; + wire \FSM_onehot_fsm_reg_n_0_[8] ; + wire \FSM_onehot_fsm_reg_n_0_[9] ; + wire [1:0]Q; + wire [3:0]QRST_CPLLLOCK; + wire QRST_IDLE; + wire [0:0]SS; + wire \cfg_wait_cnt[5]_i_2_n_0 ; + wire [5:0]cfg_wait_cnt_reg; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]cplllock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]cplllock_reg2; + wire cpllpd; + wire cpllreset; + wire cpllreset_i_1_n_0; + wire cpllreset_i_2_n_0; + wire dclk_rst; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire dclk_rst_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire dclk_rst_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]drp_done_reg1; + wire [3:0]\drp_done_reg1_reg[3]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]drp_done_reg2; + wire gtreset_i_1_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2; + wire out; + wire [5:0]p_0_in__0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]phystatus_reg1; + wire [3:0]\phystatus_reg1_reg[3]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]phystatus_reg2; + wire pipe_dclk_in; + wire pipe_mmcm_lock_in; + wire pipe_pclk_in; + wire pipe_rxusrclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qpll_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qpll_idle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rate_idle_reg1; + wire [3:0]\rate_idle_reg1_reg[3]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rate_idle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]resetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]resetdone_reg2; + wire rst_userrdy; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxcdrlock_reg1; + wire [3:0]\rxcdrlock_reg1_reg[3]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxcdrlock_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxpmaresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxpmaresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxusrclk_rst_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxusrclk_rst_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txsync_done_reg1; + wire [3:0]\txsync_done_reg1_reg[3]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txsync_done_reg2; + wire userrdy; + wire userrdy_i_1_n_0; + + assign RST_CPLLRESET = cpllreset; + assign RST_DCLK_RESET = dclk_rst_reg2; + assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2; + (* SOFT_HLUTNM = "soft_lutpair206" *) + LUT4 #( + .INIT(16'h4F44)) + \FSM_onehot_fsm[0]_i_1 + (.I0(\FSM_onehot_fsm[1]_i_2_n_0 ), + .I1(\FSM_onehot_fsm_reg_n_0_[1] ), + .I2(\FSM_onehot_fsm[8]_i_2_n_0 ), + .I3(\FSM_onehot_fsm_reg_n_0_[0] ), + .O(\FSM_onehot_fsm[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEAAAAAAAAAAAAAAA)) + \FSM_onehot_fsm[10]_i_1 + (.I0(Q[1]), + .I1(txsync_done_reg2[3]), + .I2(txsync_done_reg2[0]), + .I3(txsync_done_reg2[2]), + .I4(txsync_done_reg2[1]), + .I5(\FSM_onehot_fsm_reg_n_0_[9] ), + .O(\FSM_onehot_fsm[10]_i_1_n_0 )); + LUT5 #( + .INIT(32'h80000000)) + \FSM_onehot_fsm[13]_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[14] ), + .I1(rate_idle_reg2[3]), + .I2(rate_idle_reg2[0]), + .I3(rate_idle_reg2[2]), + .I4(rate_idle_reg2[1]), + .O(\FSM_onehot_fsm[13]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \FSM_onehot_fsm[14]_i_1 + (.I0(out), + .O(SS)); + LUT4 #( + .INIT(16'hF888)) + \FSM_onehot_fsm[14]_i_2 + (.I0(\FSM_onehot_fsm[14]_i_3_n_0 ), + .I1(\FSM_onehot_fsm_reg_n_0_[14] ), + .I2(\FSM_onehot_fsm[14]_i_4_n_0 ), + .I3(\FSM_onehot_fsm_reg_n_0_[8] ), + .O(\FSM_onehot_fsm[14]_i_2_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \FSM_onehot_fsm[14]_i_3 + (.I0(rate_idle_reg2[1]), + .I1(rate_idle_reg2[2]), + .I2(rate_idle_reg2[0]), + .I3(rate_idle_reg2[3]), + .O(\FSM_onehot_fsm[14]_i_3_n_0 )); + LUT4 #( + .INIT(16'h8000)) + \FSM_onehot_fsm[14]_i_4 + (.I0(cplllock_reg2[3]), + .I1(cplllock_reg2[0]), + .I2(cplllock_reg2[2]), + .I3(cplllock_reg2[1]), + .O(\FSM_onehot_fsm[14]_i_4_n_0 )); + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_fsm[1]_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[1] ), + .I1(\FSM_onehot_fsm[1]_i_2_n_0 ), + .O(\FSM_onehot_fsm[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h7FFFFFFFFFFFFFFF)) + \FSM_onehot_fsm[1]_i_2 + (.I0(cfg_wait_cnt_reg[4]), + .I1(cfg_wait_cnt_reg[3]), + .I2(cfg_wait_cnt_reg[5]), + .I3(cfg_wait_cnt_reg[0]), + .I4(cfg_wait_cnt_reg[1]), + .I5(cfg_wait_cnt_reg[2]), + .O(\FSM_onehot_fsm[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0008000000000000)) + \FSM_onehot_fsm[2]_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(\FSM_onehot_fsm[2]_i_2_n_0 ), + .I2(phystatus_reg2[1]), + .I3(phystatus_reg2[0]), + .I4(resetdone_reg2[1]), + .I5(resetdone_reg2[0]), + .O(\FSM_onehot_fsm[2]_i_1_n_0 )); + LUT4 #( + .INIT(16'h1000)) + \FSM_onehot_fsm[2]_i_2 + (.I0(phystatus_reg2[3]), + .I1(phystatus_reg2[2]), + .I2(resetdone_reg2[3]), + .I3(resetdone_reg2[2]), + .O(\FSM_onehot_fsm[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFEAAAAAAAA)) + \FSM_onehot_fsm[3]_i_1 + (.I0(cpllpd), + .I1(txsync_done_reg2[3]), + .I2(txsync_done_reg2[0]), + .I3(txsync_done_reg2[2]), + .I4(txsync_done_reg2[1]), + .I5(Q[0]), + .O(\FSM_onehot_fsm[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \FSM_onehot_fsm[4]_i_1 + (.I0(userrdy), + .I1(mmcm_lock_reg2), + .I2(\FSM_onehot_fsm[4]_i_2_n_0 ), + .I3(\FSM_onehot_fsm_reg_n_0_[4] ), + .O(\FSM_onehot_fsm[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFF7FFFF)) + \FSM_onehot_fsm[4]_i_2 + (.I0(resetdone_reg2[0]), + .I1(resetdone_reg2[1]), + .I2(phystatus_reg2[0]), + .I3(phystatus_reg2[1]), + .I4(\FSM_onehot_fsm[2]_i_2_n_0 ), + .O(\FSM_onehot_fsm[4]_i_2_n_0 )); + LUT3 #( + .INIT(8'hBA)) + \FSM_onehot_fsm[5]_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[13] ), + .I1(mmcm_lock_reg2), + .I2(userrdy), + .O(\FSM_onehot_fsm[5]_i_1_n_0 )); + LUT4 #( + .INIT(16'hF444)) + \FSM_onehot_fsm[8]_i_1 + (.I0(\FSM_onehot_fsm[14]_i_4_n_0 ), + .I1(\FSM_onehot_fsm_reg_n_0_[8] ), + .I2(\FSM_onehot_fsm[8]_i_2_n_0 ), + .I3(\FSM_onehot_fsm_reg_n_0_[0] ), + .O(\FSM_onehot_fsm[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'h00000001)) + \FSM_onehot_fsm[8]_i_2 + (.I0(resetdone_reg2[1]), + .I1(resetdone_reg2[2]), + .I2(resetdone_reg2[0]), + .I3(resetdone_reg2[3]), + .I4(\FSM_onehot_fsm[8]_i_3_n_0 ), + .O(\FSM_onehot_fsm[8]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_fsm[8]_i_3 + (.I0(cplllock_reg2[3]), + .I1(cplllock_reg2[1]), + .I2(cplllock_reg2[2]), + .I3(cplllock_reg2[0]), + .O(\FSM_onehot_fsm[8]_i_3_n_0 )); + LUT6 #( + .INIT(64'h2AAAAAAB2AAAAAAA)) + \FSM_onehot_fsm[9]_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[9] ), + .I1(txsync_done_reg2[3]), + .I2(txsync_done_reg2[0]), + .I3(txsync_done_reg2[2]), + .I4(txsync_done_reg2[1]), + .I5(Q[0]), + .O(\FSM_onehot_fsm[9]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000" *) + FDRE #( + .INIT(1'b1)) + \FSM_onehot_fsm_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[0]_i_1_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[0] ), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[10]_i_1_n_0 ), + .Q(Q[1]), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[13]_i_1_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[13] ), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[14]_i_2_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[14] ), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000" *) + FDSE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[1]_i_1_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[1] ), + .S(SS)); + (* FSM_ENCODED_STATES = "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[2]_i_1_n_0 ), + .Q(cpllpd), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[3]_i_1_n_0 ), + .Q(Q[0]), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[4]_i_1_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[4] ), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[5]_i_1_n_0 ), + .Q(userrdy), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[8]_i_1_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[8] ), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[9]_i_1_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[9] ), + .R(SS)); + (* SOFT_HLUTNM = "soft_lutpair206" *) + LUT3 #( + .INIT(8'h2A)) + \cfg_wait_cnt[0]_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[1] ), + .I1(\FSM_onehot_fsm[1]_i_2_n_0 ), + .I2(cfg_wait_cnt_reg[0]), + .O(p_0_in__0[0])); + (* SOFT_HLUTNM = "soft_lutpair204" *) + LUT4 #( + .INIT(16'h28AA)) + \cfg_wait_cnt[1]_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[1] ), + .I1(cfg_wait_cnt_reg[0]), + .I2(cfg_wait_cnt_reg[1]), + .I3(\FSM_onehot_fsm[1]_i_2_n_0 ), + .O(p_0_in__0[1])); + (* SOFT_HLUTNM = "soft_lutpair204" *) + LUT5 #( + .INIT(32'h2888AAAA)) + \cfg_wait_cnt[2]_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[1] ), + .I1(cfg_wait_cnt_reg[2]), + .I2(cfg_wait_cnt_reg[1]), + .I3(cfg_wait_cnt_reg[0]), + .I4(\FSM_onehot_fsm[1]_i_2_n_0 ), + .O(p_0_in__0[2])); + LUT6 #( + .INIT(64'h28888888AAAAAAAA)) + \cfg_wait_cnt[3]_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[1] ), + .I1(cfg_wait_cnt_reg[3]), + .I2(cfg_wait_cnt_reg[0]), + .I3(cfg_wait_cnt_reg[1]), + .I4(cfg_wait_cnt_reg[2]), + .I5(\FSM_onehot_fsm[1]_i_2_n_0 ), + .O(p_0_in__0[3])); + (* SOFT_HLUTNM = "soft_lutpair205" *) + LUT5 #( + .INIT(32'hEA006A00)) + \cfg_wait_cnt[4]_i_1 + (.I0(cfg_wait_cnt_reg[4]), + .I1(\cfg_wait_cnt[5]_i_2_n_0 ), + .I2(cfg_wait_cnt_reg[3]), + .I3(\FSM_onehot_fsm_reg_n_0_[1] ), + .I4(cfg_wait_cnt_reg[5]), + .O(p_0_in__0[4])); + (* SOFT_HLUTNM = "soft_lutpair205" *) + LUT5 #( + .INIT(32'hA8888888)) + \cfg_wait_cnt[5]_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[1] ), + .I1(cfg_wait_cnt_reg[5]), + .I2(\cfg_wait_cnt[5]_i_2_n_0 ), + .I3(cfg_wait_cnt_reg[3]), + .I4(cfg_wait_cnt_reg[4]), + .O(p_0_in__0[5])); + LUT3 #( + .INIT(8'h80)) + \cfg_wait_cnt[5]_i_2 + (.I0(cfg_wait_cnt_reg[2]), + .I1(cfg_wait_cnt_reg[1]), + .I2(cfg_wait_cnt_reg[0]), + .O(\cfg_wait_cnt[5]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \cfg_wait_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[0]), + .Q(cfg_wait_cnt_reg[0]), + .R(SS)); + FDRE #( + .INIT(1'b0)) + \cfg_wait_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[1]), + .Q(cfg_wait_cnt_reg[1]), + .R(SS)); + FDRE #( + .INIT(1'b0)) + \cfg_wait_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[2]), + .Q(cfg_wait_cnt_reg[2]), + .R(SS)); + FDRE #( + .INIT(1'b0)) + \cfg_wait_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[3]), + .Q(cfg_wait_cnt_reg[3]), + .R(SS)); + FDRE #( + .INIT(1'b0)) + \cfg_wait_cnt_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[4]), + .Q(cfg_wait_cnt_reg[4]), + .R(SS)); + FDRE #( + .INIT(1'b0)) + \cfg_wait_cnt_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[5]), + .Q(cfg_wait_cnt_reg[5]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \cplllock_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(QRST_CPLLLOCK[0]), + .Q(cplllock_reg1[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \cplllock_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(QRST_CPLLLOCK[1]), + .Q(cplllock_reg1[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \cplllock_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(QRST_CPLLLOCK[2]), + .Q(cplllock_reg1[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \cplllock_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(QRST_CPLLLOCK[3]), + .Q(cplllock_reg1[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \cplllock_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cplllock_reg1[0]), + .Q(cplllock_reg2[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \cplllock_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cplllock_reg1[1]), + .Q(cplllock_reg2[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \cplllock_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cplllock_reg1[2]), + .Q(cplllock_reg2[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \cplllock_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cplllock_reg1[3]), + .Q(cplllock_reg2[3]), + .R(SS)); + LUT6 #( + .INIT(64'hFFFFFFFEAAAAAAAA)) + cpllreset_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[0] ), + .I1(Q[1]), + .I2(userrdy), + .I3(\FSM_onehot_fsm_reg_n_0_[1] ), + .I4(cpllreset_i_2_n_0), + .I5(cpllreset), + .O(cpllreset_i_1_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + cpllreset_i_2 + (.I0(Q[0]), + .I1(cpllpd), + .I2(\FSM_onehot_fsm_reg_n_0_[9] ), + .I3(\FSM_onehot_fsm_reg_n_0_[14] ), + .I4(\FSM_onehot_fsm_reg_n_0_[13] ), + .I5(\FSM_onehot_fsm_reg_n_0_[4] ), + .O(cpllreset_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + cpllreset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cpllreset_i_1_n_0), + .Q(cpllreset), + .R(SS)); + FDRE #( + .INIT(1'b0)) + dclk_rst_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_reg_n_0_[1] ), + .Q(dclk_rst), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE #( + .INIT(1'b0)) + dclk_rst_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(dclk_rst), + .Q(dclk_rst_reg1), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE #( + .INIT(1'b0)) + dclk_rst_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(dclk_rst_reg1), + .Q(dclk_rst_reg2), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \drp_done_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\drp_done_reg1_reg[3]_0 [0]), + .Q(drp_done_reg1[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \drp_done_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\drp_done_reg1_reg[3]_0 [1]), + .Q(drp_done_reg1[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \drp_done_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\drp_done_reg1_reg[3]_0 [2]), + .Q(drp_done_reg1[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \drp_done_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\drp_done_reg1_reg[3]_0 [3]), + .Q(drp_done_reg1[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \drp_done_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_done_reg1[0]), + .Q(drp_done_reg2[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \drp_done_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_done_reg1[1]), + .Q(drp_done_reg2[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \drp_done_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_done_reg1[2]), + .Q(drp_done_reg2[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \drp_done_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_done_reg1[3]), + .Q(drp_done_reg2[3]), + .R(SS)); + LUT3 #( + .INIT(8'hDC)) + gtreset_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[13] ), + .I1(\FSM_onehot_fsm_reg_n_0_[0] ), + .I2(DRP_GTXRESET), + .O(gtreset_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + gtreset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gtreset_i_1_n_0), + .Q(DRP_GTXRESET), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_mmcm_lock_in), + .Q(mmcm_lock_reg1), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(mmcm_lock_reg1), + .Q(mmcm_lock_reg2), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \phystatus_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\phystatus_reg1_reg[3]_0 [0]), + .Q(phystatus_reg1[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \phystatus_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\phystatus_reg1_reg[3]_0 [1]), + .Q(phystatus_reg1[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \phystatus_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\phystatus_reg1_reg[3]_0 [2]), + .Q(phystatus_reg1[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \phystatus_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\phystatus_reg1_reg[3]_0 [3]), + .Q(phystatus_reg1[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \phystatus_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(phystatus_reg1[0]), + .Q(phystatus_reg2[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \phystatus_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(phystatus_reg1[1]), + .Q(phystatus_reg2[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \phystatus_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(phystatus_reg1[2]), + .Q(phystatus_reg2[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \phystatus_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(phystatus_reg1[3]), + .Q(phystatus_reg2[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE qpll_idle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(QRST_IDLE), + .Q(qpll_idle_reg1), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE qpll_idle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpll_idle_reg1), + .Q(qpll_idle_reg2), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_idle_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rate_idle_reg1_reg[3]_0 [0]), + .Q(rate_idle_reg1[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_idle_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rate_idle_reg1_reg[3]_0 [1]), + .Q(rate_idle_reg1[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_idle_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rate_idle_reg1_reg[3]_0 [2]), + .Q(rate_idle_reg1[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_idle_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rate_idle_reg1_reg[3]_0 [3]), + .Q(rate_idle_reg1[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_idle_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_idle_reg1[0]), + .Q(rate_idle_reg2[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_idle_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_idle_reg1[1]), + .Q(rate_idle_reg2[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_idle_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_idle_reg1[2]), + .Q(rate_idle_reg2[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_idle_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_idle_reg1[3]), + .Q(rate_idle_reg2[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \resetdone_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(D[0]), + .Q(resetdone_reg1[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \resetdone_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(D[1]), + .Q(resetdone_reg1[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \resetdone_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(D[2]), + .Q(resetdone_reg1[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \resetdone_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(D[3]), + .Q(resetdone_reg1[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \resetdone_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(resetdone_reg1[0]), + .Q(resetdone_reg2[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \resetdone_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(resetdone_reg1[1]), + .Q(resetdone_reg2[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \resetdone_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(resetdone_reg1[2]), + .Q(resetdone_reg2[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \resetdone_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(resetdone_reg1[3]), + .Q(resetdone_reg2[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxcdrlock_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxcdrlock_reg1_reg[3]_0 [0]), + .Q(rxcdrlock_reg1[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxcdrlock_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxcdrlock_reg1_reg[3]_0 [1]), + .Q(rxcdrlock_reg1[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxcdrlock_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxcdrlock_reg1_reg[3]_0 [2]), + .Q(rxcdrlock_reg1[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxcdrlock_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rxcdrlock_reg1_reg[3]_0 [3]), + .Q(rxcdrlock_reg1[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxcdrlock_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxcdrlock_reg1[0]), + .Q(rxcdrlock_reg2[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxcdrlock_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxcdrlock_reg1[1]), + .Q(rxcdrlock_reg2[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxcdrlock_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxcdrlock_reg1[2]), + .Q(rxcdrlock_reg2[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxcdrlock_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxcdrlock_reg1[3]), + .Q(rxcdrlock_reg2[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxpmaresetdone_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxpmaresetdone_reg1[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxpmaresetdone_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxpmaresetdone_reg1[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxpmaresetdone_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxpmaresetdone_reg1[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxpmaresetdone_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxpmaresetdone_reg1[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxpmaresetdone_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxpmaresetdone_reg1[0]), + .Q(rxpmaresetdone_reg2[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxpmaresetdone_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxpmaresetdone_reg1[1]), + .Q(rxpmaresetdone_reg2[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxpmaresetdone_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxpmaresetdone_reg1[2]), + .Q(rxpmaresetdone_reg2[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rxpmaresetdone_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxpmaresetdone_reg1[3]), + .Q(rxpmaresetdone_reg2[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE #( + .INIT(1'b0)) + rxusrclk_rst_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(cpllreset), + .Q(rxusrclk_rst_reg1), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE #( + .INIT(1'b0)) + rxusrclk_rst_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rxusrclk_rst_reg1), + .Q(rxusrclk_rst_reg2), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txsync_done_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txsync_done_reg1_reg[3]_0 [0]), + .Q(txsync_done_reg1[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txsync_done_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txsync_done_reg1_reg[3]_0 [1]), + .Q(txsync_done_reg1[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txsync_done_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txsync_done_reg1_reg[3]_0 [2]), + .Q(txsync_done_reg1[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txsync_done_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txsync_done_reg1_reg[3]_0 [3]), + .Q(txsync_done_reg1[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txsync_done_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_done_reg1[0]), + .Q(txsync_done_reg2[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txsync_done_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_done_reg1[1]), + .Q(txsync_done_reg2[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txsync_done_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_done_reg1[2]), + .Q(txsync_done_reg2[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txsync_done_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_done_reg1[3]), + .Q(txsync_done_reg2[3]), + .R(SS)); + LUT3 #( + .INIT(8'hB8)) + userrdy_i_1 + (.I0(mmcm_lock_reg2), + .I1(userrdy), + .I2(rst_userrdy), + .O(userrdy_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + userrdy_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(userrdy_i_1_n_0), + .Q(rst_userrdy), + .R(SS)); +endmodule + +module pcie_7x_0_pcie_7x_0_pipe_sync + (out, + txphaligndone_reg3_reg_0, + sync_txdlyen_0, + RST_TXSYNC_DONE, + Q, + RST_CPLLRESET, + SYNC_TXPHALIGNDONE, + pipe_pclk_in, + SYNC_TXSYNC_START, + pipe_mmcm_lock_in, + SYNC_TXDLYSRESETDONE, + SYNC_TXPHINITDONE, + USER_RATE_GEN3, + SYNC_RATE_IDLE, + gt_rx_elec_idle_wire_filter, + SYNC_RXCDRLOCK, + SYNC_RXSYNC_START, + SYNC_RXDLYSRESETDONE, + SYNC_RXPHALIGNDONE_M, + SYNC_RXPHALIGNDONE_S, + \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 , + user_active_lane_0, + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 , + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 ); + output out; + output txphaligndone_reg3_reg_0; + output sync_txdlyen_0; + output [0:0]RST_TXSYNC_DONE; + output [2:0]Q; + input RST_CPLLRESET; + input SYNC_TXPHALIGNDONE; + input pipe_pclk_in; + input SYNC_TXSYNC_START; + input pipe_mmcm_lock_in; + input SYNC_TXDLYSRESETDONE; + input SYNC_TXPHINITDONE; + input USER_RATE_GEN3; + input SYNC_RATE_IDLE; + input [0:0]gt_rx_elec_idle_wire_filter; + input SYNC_RXCDRLOCK; + input SYNC_RXSYNC_START; + input SYNC_RXDLYSRESETDONE; + input SYNC_RXPHALIGNDONE_M; + input SYNC_RXPHALIGNDONE_S; + input \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ; + input user_active_lane_0; + input \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ; + input \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 ; + + wire \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[4]_i_2_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ; + wire [2:0]Q; + wire RST_CPLLRESET; + wire [0:0]RST_TXSYNC_DONE; + wire SYNC_RATE_IDLE; + wire SYNC_RXCDRLOCK; + wire SYNC_RXDLYSRESETDONE; + wire SYNC_RXPHALIGNDONE_M; + wire SYNC_RXPHALIGNDONE_S; + wire SYNC_RXSYNC_START; + wire SYNC_TXDLYSRESETDONE; + wire SYNC_TXPHALIGNDONE; + wire SYNC_TXPHINITDONE; + wire SYNC_TXSYNC_START; + wire USER_RATE_GEN3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2; + wire [0:0]gt_rx_elec_idle_wire_filter; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2; + wire pipe_mmcm_lock_in; + wire pipe_pclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxdlysresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxdlysresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxelecidle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxelecidle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_m_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_m_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_s_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_s_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_donem_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_donem_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsyncdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsyncdone_reg2; + wire sync_txdlyen_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg3; + wire \txsync_fsm.txdlyen_i_1_n_0 ; + wire \txsync_fsm.txsync_done_i_1_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg3; + wire user_active_lane_0; + + assign out = txphaligndone_reg2; + assign txphaligndone_reg3_reg_0 = txphaligndone_reg3; + LUT5 #( + .INIT(32'h1D1DFF1D)) + \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0 ), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .I2(txsync_start_reg2), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2 + (.I0(Q[1]), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .I3(Q[0]), + .I4(Q[2]), + .O(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF444)) + \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1 + (.I0(mmcm_lock_reg2), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .I3(txsync_start_reg2), + .O(\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFD0D0D0)) + \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1 + (.I0(txdlysresetdone_reg2), + .I1(txdlysresetdone_reg3), + .I2(Q[0]), + .I3(mmcm_lock_reg2), + .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0 )); + LUT5 #( + .INIT(32'h44F44444)) + \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_2_n_0 ), + .I1(Q[1]), + .I2(txdlysresetdone_reg2), + .I3(txdlysresetdone_reg3), + .I4(Q[0]), + .O(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0 )); + LUT4 #( + .INIT(16'hF444)) + \FSM_onehot_txsync_fsm.fsm_tx[4]_i_2 + (.I0(txphinitdone_reg3), + .I1(txphinitdone_reg2), + .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'h8F88FFFF88888888)) + \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ), + .I1(Q[2]), + .I2(txphinitdone_reg3), + .I3(txphinitdone_reg2), + .I4(user_active_lane_0), + .I5(Q[1]), + .O(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEAFFEAEA2A002A2A)) + \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ), + .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 ), + .I3(txphaligndone_reg3), + .I4(txphaligndone_reg2), + .I5(Q[2]), + .O(\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0 )); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDSE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0 ), + .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0 ), + .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0 ), + .Q(Q[0]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0 ), + .Q(Q[1]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0 ), + .Q(Q[2]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0 ), + .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RATE_GEN3), + .Q(gen3_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_reg1), + .Q(gen3_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_mmcm_lock_in), + .Q(mmcm_lock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(mmcm_lock_reg1), + .Q(mmcm_lock_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RATE_IDLE), + .Q(rate_idle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_idle_reg1), + .Q(rate_idle_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXCDRLOCK), + .Q(rxcdrlock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxcdrlock_reg1), + .Q(rxcdrlock_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxdlysresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXDLYSRESETDONE), + .Q(rxdlysresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxdlysresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxdlysresetdone_reg1), + .Q(rxdlysresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxelecidle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rx_elec_idle_wire_filter), + .Q(rxelecidle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxelecidle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxelecidle_reg1), + .Q(rxelecidle_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_m_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXPHALIGNDONE_M), + .Q(rxphaligndone_m_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_m_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxphaligndone_m_reg1), + .Q(rxphaligndone_m_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_s_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXPHALIGNDONE_S), + .Q(rxphaligndone_s_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_s_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxphaligndone_s_reg1), + .Q(rxphaligndone_s_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_donem_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxsync_donem_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_donem_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsync_donem_reg1), + .Q(rxsync_donem_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_start_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXSYNC_START), + .Q(rxsync_start_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_start_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsync_start_reg1), + .Q(rxsync_start_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsyncdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxsyncdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsyncdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsyncdone_reg1), + .Q(rxsyncdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txdlysresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXDLYSRESETDONE), + .Q(txdlysresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txdlysresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txdlysresetdone_reg1), + .Q(txdlysresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txdlysresetdone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txdlysresetdone_reg2), + .Q(txdlysresetdone_reg3), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphaligndone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXPHALIGNDONE), + .Q(txphaligndone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphaligndone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphaligndone_reg1), + .Q(txphaligndone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphaligndone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphaligndone_reg2), + .Q(txphaligndone_reg3), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphinitdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXPHINITDONE), + .Q(txphinitdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphinitdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphinitdone_reg1), + .Q(txphinitdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphinitdone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphinitdone_reg2), + .Q(txphinitdone_reg3), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hABAAA8AA)) + \txsync_fsm.txdlyen_i_1 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .I1(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0 ), + .I2(txsync_start_reg2), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .I4(sync_txdlyen_0), + .O(\txsync_fsm.txdlyen_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \txsync_fsm.txdlyen_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txsync_fsm.txdlyen_i_1_n_0 ), + .Q(sync_txdlyen_0), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h222F222222202222)) + \txsync_fsm.txsync_done_i_1 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ), + .I2(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0 ), + .I3(txsync_start_reg2), + .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .I5(RST_TXSYNC_DONE), + .O(\txsync_fsm.txsync_done_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \txsync_fsm.txsync_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txsync_fsm.txsync_done_i_1_n_0 ), + .Q(RST_TXSYNC_DONE), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_start_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXSYNC_START), + .Q(txsync_start_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_start_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_start_reg1), + .Q(txsync_start_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_start_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_start_reg2), + .Q(txsync_start_reg3), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsyncdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txsyncdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsyncdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsyncdone_reg1), + .Q(txsyncdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsyncdone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsyncdone_reg2), + .Q(txsyncdone_reg3), + .R(RST_CPLLRESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_sync" *) +module pcie_7x_0_pcie_7x_0_pipe_sync_41 + (Q, + RST_TXSYNC_DONE, + out, + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 , + RST_CPLLRESET, + pipe_pclk_in, + SYNC_TXPHALIGNDONE, + SYNC_TXSYNC_START, + pipe_mmcm_lock_in, + SYNC_TXDLYSRESETDONE, + SYNC_TXPHINITDONE, + SYNC_GEN3, + SYNC_RATE_IDLE, + gt_rx_elec_idle_wire_filter, + SYNC_RXCDRLOCK, + SYNC_RXSYNC_START, + SYNC_RXDLYSRESETDONE, + SYNC_RXPHALIGNDONE_M, + SYNC_RXPHALIGNDONE_S, + user_active_lane_1); + output [2:0]Q; + output [0:0]RST_TXSYNC_DONE; + input out; + input \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ; + input RST_CPLLRESET; + input pipe_pclk_in; + input SYNC_TXPHALIGNDONE; + input SYNC_TXSYNC_START; + input pipe_mmcm_lock_in; + input SYNC_TXDLYSRESETDONE; + input SYNC_TXPHINITDONE; + input SYNC_GEN3; + input SYNC_RATE_IDLE; + input [0:0]gt_rx_elec_idle_wire_filter; + input SYNC_RXCDRLOCK; + input SYNC_RXSYNC_START; + input SYNC_RXDLYSRESETDONE; + input SYNC_RXPHALIGNDONE_M; + input SYNC_RXPHALIGNDONE_S; + input user_active_lane_1; + + wire \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__2_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ; + wire [2:0]Q; + wire RST_CPLLRESET; + wire [0:0]RST_TXSYNC_DONE; + wire SYNC_GEN3; + wire SYNC_RATE_IDLE; + wire SYNC_RXCDRLOCK; + wire SYNC_RXDLYSRESETDONE; + wire SYNC_RXPHALIGNDONE_M; + wire SYNC_RXPHALIGNDONE_S; + wire SYNC_RXSYNC_START; + wire SYNC_TXDLYSRESETDONE; + wire SYNC_TXPHALIGNDONE; + wire SYNC_TXPHINITDONE; + wire SYNC_TXSYNC_START; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2; + wire [0:0]gt_rx_elec_idle_wire_filter; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2; + wire out; + wire pipe_mmcm_lock_in; + wire pipe_pclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxdlysresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxdlysresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxelecidle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxelecidle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_m_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_m_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_s_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_s_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_donem_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_donem_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsyncdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsyncdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg3; + wire \txsync_fsm.txsync_done_i_1__0_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg3; + wire user_active_lane_1; + + LUT4 #( + .INIT(16'hFF1D)) + \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0 ), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .I2(txsync_start_reg2), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0 + (.I0(Q[2]), + .I1(Q[1]), + .I2(Q[0]), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0 )); + LUT4 #( + .INIT(16'hF444)) + \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0 + (.I0(mmcm_lock_reg2), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .I3(txsync_start_reg2), + .O(\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'hFFD0D0D0)) + \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0 + (.I0(txdlysresetdone_reg2), + .I1(txdlysresetdone_reg3), + .I2(Q[0]), + .I3(mmcm_lock_reg2), + .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'h44F44444)) + \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__2_n_0 ), + .I1(Q[1]), + .I2(txdlysresetdone_reg2), + .I3(txdlysresetdone_reg3), + .I4(Q[0]), + .O(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFB000B000B000)) + \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0 + (.I0(txphaligndone_reg3), + .I1(txphaligndone_reg2), + .I2(user_active_lane_1), + .I3(Q[2]), + .I4(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__2_n_0 ), + .I5(Q[1]), + .O(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0 )); + LUT4 #( + .INIT(16'hF444)) + \FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__2 + (.I0(txphinitdone_reg3), + .I1(txphinitdone_reg2), + .I2(out), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__2_n_0 )); + LUT5 #( + .INIT(32'h8080AA80)) + \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0 + (.I0(Q[2]), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ), + .I2(out), + .I3(txphaligndone_reg2), + .I4(txphaligndone_reg3), + .O(\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0 )); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDSE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0 ), + .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0 ), + .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0 ), + .Q(Q[0]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0 ), + .Q(Q[1]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0 ), + .Q(Q[2]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0 ), + .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_GEN3), + .Q(gen3_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_reg1), + .Q(gen3_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_mmcm_lock_in), + .Q(mmcm_lock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(mmcm_lock_reg1), + .Q(mmcm_lock_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RATE_IDLE), + .Q(rate_idle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_idle_reg1), + .Q(rate_idle_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXCDRLOCK), + .Q(rxcdrlock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxcdrlock_reg1), + .Q(rxcdrlock_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxdlysresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXDLYSRESETDONE), + .Q(rxdlysresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxdlysresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxdlysresetdone_reg1), + .Q(rxdlysresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxelecidle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rx_elec_idle_wire_filter), + .Q(rxelecidle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxelecidle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxelecidle_reg1), + .Q(rxelecidle_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_m_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXPHALIGNDONE_M), + .Q(rxphaligndone_m_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_m_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxphaligndone_m_reg1), + .Q(rxphaligndone_m_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_s_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXPHALIGNDONE_S), + .Q(rxphaligndone_s_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_s_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxphaligndone_s_reg1), + .Q(rxphaligndone_s_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_donem_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxsync_donem_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_donem_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsync_donem_reg1), + .Q(rxsync_donem_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_start_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXSYNC_START), + .Q(rxsync_start_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_start_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsync_start_reg1), + .Q(rxsync_start_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsyncdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxsyncdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsyncdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsyncdone_reg1), + .Q(rxsyncdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txdlysresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXDLYSRESETDONE), + .Q(txdlysresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txdlysresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txdlysresetdone_reg1), + .Q(txdlysresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txdlysresetdone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txdlysresetdone_reg2), + .Q(txdlysresetdone_reg3), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphaligndone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXPHALIGNDONE), + .Q(txphaligndone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphaligndone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphaligndone_reg1), + .Q(txphaligndone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphaligndone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphaligndone_reg2), + .Q(txphaligndone_reg3), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphinitdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXPHINITDONE), + .Q(txphinitdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphinitdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphinitdone_reg1), + .Q(txphinitdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphinitdone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphinitdone_reg2), + .Q(txphinitdone_reg3), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hABAAA8AA)) + \txsync_fsm.txsync_done_i_1__0 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .I1(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0 ), + .I2(txsync_start_reg2), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .I4(RST_TXSYNC_DONE), + .O(\txsync_fsm.txsync_done_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \txsync_fsm.txsync_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txsync_fsm.txsync_done_i_1__0_n_0 ), + .Q(RST_TXSYNC_DONE), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_start_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXSYNC_START), + .Q(txsync_start_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_start_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_start_reg1), + .Q(txsync_start_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_start_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_start_reg2), + .Q(txsync_start_reg3), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsyncdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txsyncdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsyncdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsyncdone_reg1), + .Q(txsyncdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsyncdone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsyncdone_reg2), + .Q(txsyncdone_reg3), + .R(RST_CPLLRESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_sync" *) +module pcie_7x_0_pcie_7x_0_pipe_sync_47 + (Q, + RST_TXSYNC_DONE, + out, + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 , + RST_CPLLRESET, + pipe_pclk_in, + SYNC_TXPHALIGNDONE, + SYNC_TXSYNC_START, + pipe_mmcm_lock_in, + SYNC_TXDLYSRESETDONE, + SYNC_TXPHINITDONE, + SYNC_GEN3, + SYNC_RATE_IDLE, + gt_rx_elec_idle_wire_filter, + SYNC_RXCDRLOCK, + SYNC_RXSYNC_START, + SYNC_RXDLYSRESETDONE, + SYNC_RXPHALIGNDONE_M, + SYNC_RXPHALIGNDONE_S, + user_active_lane_2); + output [2:0]Q; + output [0:0]RST_TXSYNC_DONE; + input out; + input \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ; + input RST_CPLLRESET; + input pipe_pclk_in; + input SYNC_TXPHALIGNDONE; + input SYNC_TXSYNC_START; + input pipe_mmcm_lock_in; + input SYNC_TXDLYSRESETDONE; + input SYNC_TXPHINITDONE; + input SYNC_GEN3; + input SYNC_RATE_IDLE; + input [0:0]gt_rx_elec_idle_wire_filter; + input SYNC_RXCDRLOCK; + input SYNC_RXSYNC_START; + input SYNC_RXDLYSRESETDONE; + input SYNC_RXPHALIGNDONE_M; + input SYNC_RXPHALIGNDONE_S; + input user_active_lane_2; + + wire \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__0_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ; + wire [2:0]Q; + wire RST_CPLLRESET; + wire [0:0]RST_TXSYNC_DONE; + wire SYNC_GEN3; + wire SYNC_RATE_IDLE; + wire SYNC_RXCDRLOCK; + wire SYNC_RXDLYSRESETDONE; + wire SYNC_RXPHALIGNDONE_M; + wire SYNC_RXPHALIGNDONE_S; + wire SYNC_RXSYNC_START; + wire SYNC_TXDLYSRESETDONE; + wire SYNC_TXPHALIGNDONE; + wire SYNC_TXPHINITDONE; + wire SYNC_TXSYNC_START; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2; + wire [0:0]gt_rx_elec_idle_wire_filter; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2; + wire out; + wire pipe_mmcm_lock_in; + wire pipe_pclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxdlysresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxdlysresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxelecidle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxelecidle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_m_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_m_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_s_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_s_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_donem_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_donem_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsyncdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsyncdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg3; + wire \txsync_fsm.txsync_done_i_1__1_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg3; + wire user_active_lane_2; + + LUT4 #( + .INIT(16'hFF1D)) + \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__1 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__1_n_0 ), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .I2(txsync_start_reg2), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__1_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__1 + (.I0(Q[2]), + .I1(Q[1]), + .I2(Q[0]), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__1_n_0 )); + LUT4 #( + .INIT(16'hF444)) + \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__1 + (.I0(mmcm_lock_reg2), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .I3(txsync_start_reg2), + .O(\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__1_n_0 )); + LUT5 #( + .INIT(32'hFFD0D0D0)) + \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__1 + (.I0(txdlysresetdone_reg2), + .I1(txdlysresetdone_reg3), + .I2(Q[0]), + .I3(mmcm_lock_reg2), + .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__1_n_0 )); + LUT5 #( + .INIT(32'h44F44444)) + \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__1 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__0_n_0 ), + .I1(Q[1]), + .I2(txdlysresetdone_reg2), + .I3(txdlysresetdone_reg3), + .I4(Q[0]), + .O(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFB000B000B000)) + \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__1 + (.I0(txphaligndone_reg3), + .I1(txphaligndone_reg2), + .I2(user_active_lane_2), + .I3(Q[2]), + .I4(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__0_n_0 ), + .I5(Q[1]), + .O(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__1_n_0 )); + LUT4 #( + .INIT(16'hF444)) + \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__0 + (.I0(txphinitdone_reg3), + .I1(txphinitdone_reg2), + .I2(out), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__0_n_0 )); + LUT5 #( + .INIT(32'h8080AA80)) + \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__1 + (.I0(Q[2]), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ), + .I2(out), + .I3(txphaligndone_reg2), + .I4(txphaligndone_reg3), + .O(\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__1_n_0 )); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDSE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__1_n_0 ), + .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__1_n_0 ), + .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__1_n_0 ), + .Q(Q[0]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__1_n_0 ), + .Q(Q[1]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__1_n_0 ), + .Q(Q[2]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__1_n_0 ), + .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_GEN3), + .Q(gen3_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_reg1), + .Q(gen3_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_mmcm_lock_in), + .Q(mmcm_lock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(mmcm_lock_reg1), + .Q(mmcm_lock_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RATE_IDLE), + .Q(rate_idle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_idle_reg1), + .Q(rate_idle_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXCDRLOCK), + .Q(rxcdrlock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxcdrlock_reg1), + .Q(rxcdrlock_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxdlysresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXDLYSRESETDONE), + .Q(rxdlysresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxdlysresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxdlysresetdone_reg1), + .Q(rxdlysresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxelecidle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rx_elec_idle_wire_filter), + .Q(rxelecidle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxelecidle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxelecidle_reg1), + .Q(rxelecidle_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_m_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXPHALIGNDONE_M), + .Q(rxphaligndone_m_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_m_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxphaligndone_m_reg1), + .Q(rxphaligndone_m_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_s_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXPHALIGNDONE_S), + .Q(rxphaligndone_s_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_s_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxphaligndone_s_reg1), + .Q(rxphaligndone_s_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_donem_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxsync_donem_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_donem_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsync_donem_reg1), + .Q(rxsync_donem_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_start_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXSYNC_START), + .Q(rxsync_start_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_start_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsync_start_reg1), + .Q(rxsync_start_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsyncdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxsyncdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsyncdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsyncdone_reg1), + .Q(rxsyncdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txdlysresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXDLYSRESETDONE), + .Q(txdlysresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txdlysresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txdlysresetdone_reg1), + .Q(txdlysresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txdlysresetdone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txdlysresetdone_reg2), + .Q(txdlysresetdone_reg3), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphaligndone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXPHALIGNDONE), + .Q(txphaligndone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphaligndone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphaligndone_reg1), + .Q(txphaligndone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphaligndone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphaligndone_reg2), + .Q(txphaligndone_reg3), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphinitdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXPHINITDONE), + .Q(txphinitdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphinitdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphinitdone_reg1), + .Q(txphinitdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphinitdone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphinitdone_reg2), + .Q(txphinitdone_reg3), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hABAAA8AA)) + \txsync_fsm.txsync_done_i_1__1 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .I1(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__1_n_0 ), + .I2(txsync_start_reg2), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .I4(RST_TXSYNC_DONE), + .O(\txsync_fsm.txsync_done_i_1__1_n_0 )); + FDRE #( + .INIT(1'b0)) + \txsync_fsm.txsync_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txsync_fsm.txsync_done_i_1__1_n_0 ), + .Q(RST_TXSYNC_DONE), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_start_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXSYNC_START), + .Q(txsync_start_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_start_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_start_reg1), + .Q(txsync_start_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_start_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_start_reg2), + .Q(txsync_start_reg3), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsyncdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txsyncdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsyncdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsyncdone_reg1), + .Q(txsyncdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsyncdone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsyncdone_reg2), + .Q(txsyncdone_reg3), + .R(RST_CPLLRESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_sync" *) +module pcie_7x_0_pcie_7x_0_pipe_sync_53 + (Q, + RST_TXSYNC_DONE, + out, + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 , + RST_CPLLRESET, + pipe_pclk_in, + SYNC_TXPHALIGNDONE, + SYNC_TXSYNC_START, + pipe_mmcm_lock_in, + SYNC_TXDLYSRESETDONE, + SYNC_TXPHINITDONE, + SYNC_GEN3, + SYNC_RATE_IDLE, + gt_rx_elec_idle_wire_filter, + SYNC_RXCDRLOCK, + SYNC_RXSYNC_START, + SYNC_RXDLYSRESETDONE, + SYNC_RXPHALIGNDONE_M, + SYNC_RXPHALIGNDONE_S, + user_active_lane_3); + output [2:0]Q; + output [0:0]RST_TXSYNC_DONE; + input out; + input \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ; + input RST_CPLLRESET; + input pipe_pclk_in; + input SYNC_TXPHALIGNDONE; + input SYNC_TXSYNC_START; + input pipe_mmcm_lock_in; + input SYNC_TXDLYSRESETDONE; + input SYNC_TXPHINITDONE; + input SYNC_GEN3; + input SYNC_RATE_IDLE; + input [0:0]gt_rx_elec_idle_wire_filter; + input SYNC_RXCDRLOCK; + input SYNC_RXSYNC_START; + input SYNC_RXDLYSRESETDONE; + input SYNC_RXPHALIGNDONE_M; + input SYNC_RXPHALIGNDONE_S; + input user_active_lane_3; + + wire \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__2_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__2_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__2_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__2_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__2_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__2_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__1_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__2_n_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ; + wire [2:0]Q; + wire RST_CPLLRESET; + wire [0:0]RST_TXSYNC_DONE; + wire SYNC_GEN3; + wire SYNC_RATE_IDLE; + wire SYNC_RXCDRLOCK; + wire SYNC_RXDLYSRESETDONE; + wire SYNC_RXPHALIGNDONE_M; + wire SYNC_RXPHALIGNDONE_S; + wire SYNC_RXSYNC_START; + wire SYNC_TXDLYSRESETDONE; + wire SYNC_TXPHALIGNDONE; + wire SYNC_TXPHINITDONE; + wire SYNC_TXSYNC_START; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2; + wire [0:0]gt_rx_elec_idle_wire_filter; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2; + wire out; + wire pipe_mmcm_lock_in; + wire pipe_pclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxdlysresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxdlysresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxelecidle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxelecidle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_m_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_m_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_s_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_s_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_donem_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_donem_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsyncdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsyncdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg3; + wire \txsync_fsm.txsync_done_i_1__2_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg3; + wire user_active_lane_3; + + LUT4 #( + .INIT(16'hFF1D)) + \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__2 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__2_n_0 ), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .I2(txsync_start_reg2), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__2_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__2 + (.I0(Q[2]), + .I1(Q[1]), + .I2(Q[0]), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__2_n_0 )); + LUT4 #( + .INIT(16'hF444)) + \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__2 + (.I0(mmcm_lock_reg2), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .I3(txsync_start_reg2), + .O(\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__2_n_0 )); + LUT5 #( + .INIT(32'hFFD0D0D0)) + \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__2 + (.I0(txdlysresetdone_reg2), + .I1(txdlysresetdone_reg3), + .I2(Q[0]), + .I3(mmcm_lock_reg2), + .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__2_n_0 )); + LUT5 #( + .INIT(32'h44F44444)) + \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__2 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__1_n_0 ), + .I1(Q[1]), + .I2(txdlysresetdone_reg2), + .I3(txdlysresetdone_reg3), + .I4(Q[0]), + .O(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFB000B000B000)) + \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__2 + (.I0(txphaligndone_reg3), + .I1(txphaligndone_reg2), + .I2(user_active_lane_3), + .I3(Q[2]), + .I4(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__1_n_0 ), + .I5(Q[1]), + .O(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__2_n_0 )); + LUT4 #( + .INIT(16'hF444)) + \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__1 + (.I0(txphinitdone_reg3), + .I1(txphinitdone_reg2), + .I2(out), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ), + .O(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__1_n_0 )); + LUT5 #( + .INIT(32'h8080AA80)) + \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__2 + (.I0(Q[2]), + .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ), + .I2(out), + .I3(txphaligndone_reg2), + .I4(txphaligndone_reg3), + .O(\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__2_n_0 )); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDSE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__2_n_0 ), + .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__2_n_0 ), + .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__2_n_0 ), + .Q(Q[0]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__2_n_0 ), + .Q(Q[1]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__2_n_0 ), + .Q(Q[2]), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_txsync_fsm.fsm_tx_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__2_n_0 ), + .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_GEN3), + .Q(gen3_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gen3_reg1), + .Q(gen3_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_mmcm_lock_in), + .Q(mmcm_lock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(mmcm_lock_reg1), + .Q(mmcm_lock_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RATE_IDLE), + .Q(rate_idle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_idle_reg1), + .Q(rate_idle_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXCDRLOCK), + .Q(rxcdrlock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxcdrlock_reg1), + .Q(rxcdrlock_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxdlysresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXDLYSRESETDONE), + .Q(rxdlysresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxdlysresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxdlysresetdone_reg1), + .Q(rxdlysresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxelecidle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rx_elec_idle_wire_filter), + .Q(rxelecidle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxelecidle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxelecidle_reg1), + .Q(rxelecidle_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_m_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXPHALIGNDONE_M), + .Q(rxphaligndone_m_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_m_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxphaligndone_m_reg1), + .Q(rxphaligndone_m_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_s_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXPHALIGNDONE_S), + .Q(rxphaligndone_s_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxphaligndone_s_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxphaligndone_s_reg1), + .Q(rxphaligndone_s_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_donem_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxsync_donem_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_donem_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsync_donem_reg1), + .Q(rxsync_donem_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_start_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_RXSYNC_START), + .Q(rxsync_start_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsync_start_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsync_start_reg1), + .Q(rxsync_start_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsyncdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rxsyncdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxsyncdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxsyncdone_reg1), + .Q(rxsyncdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txdlysresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXDLYSRESETDONE), + .Q(txdlysresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txdlysresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txdlysresetdone_reg1), + .Q(txdlysresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txdlysresetdone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txdlysresetdone_reg2), + .Q(txdlysresetdone_reg3), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphaligndone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXPHALIGNDONE), + .Q(txphaligndone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphaligndone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphaligndone_reg1), + .Q(txphaligndone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphaligndone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphaligndone_reg2), + .Q(txphaligndone_reg3), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphinitdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXPHINITDONE), + .Q(txphinitdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphinitdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphinitdone_reg1), + .Q(txphinitdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txphinitdone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txphinitdone_reg2), + .Q(txphinitdone_reg3), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hABAAA8AA)) + \txsync_fsm.txsync_done_i_1__2 + (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ), + .I1(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__2_n_0 ), + .I2(txsync_start_reg2), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ), + .I4(RST_TXSYNC_DONE), + .O(\txsync_fsm.txsync_done_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \txsync_fsm.txsync_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txsync_fsm.txsync_done_i_1__2_n_0 ), + .Q(RST_TXSYNC_DONE), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_start_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(SYNC_TXSYNC_START), + .Q(txsync_start_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_start_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_start_reg1), + .Q(txsync_start_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsync_start_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsync_start_reg2), + .Q(txsync_start_reg3), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsyncdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(txsyncdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsyncdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsyncdone_reg1), + .Q(txsyncdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txsyncdone_reg3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txsyncdone_reg2), + .Q(txsyncdone_reg3), + .R(RST_CPLLRESET)); +endmodule + +module pcie_7x_0_pcie_7x_0_pipe_user + (gt_rxvalid_q_reg, + out, + SYNC_TXPHALIGNDONE, + txelecidle_reg2_reg_0, + txcompliance_reg2_reg_0, + SYNC_TXPHINITDONE, + txelecidle_reg2_reg_1, + USER_OOBCLK, + RST_RXCDRLOCK, + gt_rx_phy_status_wire_filter, + \converge_cnt_reg[15]_0 , + \converge_cnt_reg[1]_0 , + \converge_cnt_reg[6]_0 , + RST_RESETDONE, + user_active_lane_0, + converge_gen3_reg_0, + gt_rx_elec_idle_wire_filter, + pipe_rx0_valid_gt, + gt_rxvalid_0, + txphaligndone_reg1_reg, + user_active_lane_1, + txphaligndone_reg1_reg_0, + txphaligndone_reg1_reg_1, + txphinitdone_reg1_reg, + txphinitdone_reg1_reg_0, + txphinitdone_reg1_reg_1, + \FSM_onehot_txsync_fsm.fsm_tx_reg[5] , + \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 , + RST_CPLLRESET, + pipe_pclk_sel_out, + pipe_pclk_in, + pipe_oobclk_in, + USER_TXRESETDONE, + USER_RXRESETDONE, + PIPE_TXELECIDLE, + PIPE_TXCOMPLIANCE, + gt_rxcdrlock_0, + RST_RXUSRCLK_RESET, + pipe_rxusrclk_in, + PIPE_RXSTATUS, + RST_IDLE, + USER_RATE_IDLE, + USER_RATE_RXSYNC, + USER_RATE_DONE, + USER_RATE_GEN3, + USER_RXEQ_ADAPT_DONE, + USER_RESETOVRD_START, + RST_PHYSTATUS); + output gt_rxvalid_q_reg; + output out; + output SYNC_TXPHALIGNDONE; + output txelecidle_reg2_reg_0; + output txcompliance_reg2_reg_0; + output SYNC_TXPHINITDONE; + output txelecidle_reg2_reg_1; + output USER_OOBCLK; + output [0:0]RST_RXCDRLOCK; + output [0:0]gt_rx_phy_status_wire_filter; + output \converge_cnt_reg[15]_0 ; + output \converge_cnt_reg[1]_0 ; + output \converge_cnt_reg[6]_0 ; + output [0:0]RST_RESETDONE; + output user_active_lane_0; + output converge_gen3_reg_0; + input [0:0]gt_rx_elec_idle_wire_filter; + input pipe_rx0_valid_gt; + input gt_rxvalid_0; + input txphaligndone_reg1_reg; + input user_active_lane_1; + input txphaligndone_reg1_reg_0; + input txphaligndone_reg1_reg_1; + input txphinitdone_reg1_reg; + input txphinitdone_reg1_reg_0; + input txphinitdone_reg1_reg_1; + input \FSM_onehot_txsync_fsm.fsm_tx_reg[5] ; + input \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ; + input RST_CPLLRESET; + input [0:0]pipe_pclk_sel_out; + input pipe_pclk_in; + input pipe_oobclk_in; + input USER_TXRESETDONE; + input USER_RXRESETDONE; + input [0:0]PIPE_TXELECIDLE; + input [0:0]PIPE_TXCOMPLIANCE; + input gt_rxcdrlock_0; + input RST_RXUSRCLK_RESET; + input pipe_rxusrclk_in; + input [0:0]PIPE_RXSTATUS; + input RST_IDLE; + input USER_RATE_IDLE; + input USER_RATE_RXSYNC; + input USER_RATE_DONE; + input USER_RATE_GEN3; + input USER_RXEQ_ADAPT_DONE; + input USER_RESETOVRD_START; + input [0:0]RST_PHYSTATUS; + + wire \FSM_onehot_txsync_fsm.fsm_tx_reg[5] ; + wire \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ; + wire [0:0]PIPE_RXSTATUS; + wire [0:0]PIPE_TXCOMPLIANCE; + wire [0:0]PIPE_TXELECIDLE; + wire RST_CPLLRESET; + wire RST_IDLE; + wire [0:0]RST_PHYSTATUS; + wire [0:0]RST_RESETDONE; + wire [0:0]RST_RXCDRLOCK; + wire RST_RXUSRCLK_RESET; + wire SYNC_TXPHALIGNDONE; + wire SYNC_TXPHINITDONE; + wire USER_OOBCLK; + wire USER_RATE_DONE; + wire USER_RATE_GEN3; + wire USER_RATE_IDLE; + wire USER_RATE_RXSYNC; + wire USER_RESETOVRD_START; + wire USER_RXEQ_ADAPT_DONE; + wire USER_RXRESETDONE; + wire USER_TXRESETDONE; + wire \converge_cnt[0]_i_1__0_n_0 ; + wire \converge_cnt[0]_i_4_n_0 ; + wire \converge_cnt[0]_i_5_n_0 ; + wire \converge_cnt[0]_i_6_n_0 ; + wire [21:0]converge_cnt_reg; + wire \converge_cnt_reg[0]_i_3_n_0 ; + wire \converge_cnt_reg[0]_i_3_n_1 ; + wire \converge_cnt_reg[0]_i_3_n_2 ; + wire \converge_cnt_reg[0]_i_3_n_3 ; + wire \converge_cnt_reg[0]_i_3_n_4 ; + wire \converge_cnt_reg[0]_i_3_n_5 ; + wire \converge_cnt_reg[0]_i_3_n_6 ; + wire \converge_cnt_reg[0]_i_3_n_7 ; + wire \converge_cnt_reg[12]_i_1_n_0 ; + wire \converge_cnt_reg[12]_i_1_n_1 ; + wire \converge_cnt_reg[12]_i_1_n_2 ; + wire \converge_cnt_reg[12]_i_1_n_3 ; + wire \converge_cnt_reg[12]_i_1_n_4 ; + wire \converge_cnt_reg[12]_i_1_n_5 ; + wire \converge_cnt_reg[12]_i_1_n_6 ; + wire \converge_cnt_reg[12]_i_1_n_7 ; + wire \converge_cnt_reg[15]_0 ; + wire \converge_cnt_reg[16]_i_1_n_0 ; + wire \converge_cnt_reg[16]_i_1_n_1 ; + wire \converge_cnt_reg[16]_i_1_n_2 ; + wire \converge_cnt_reg[16]_i_1_n_3 ; + wire \converge_cnt_reg[16]_i_1_n_4 ; + wire \converge_cnt_reg[16]_i_1_n_5 ; + wire \converge_cnt_reg[16]_i_1_n_6 ; + wire \converge_cnt_reg[16]_i_1_n_7 ; + wire \converge_cnt_reg[1]_0 ; + wire \converge_cnt_reg[20]_i_1_n_3 ; + wire \converge_cnt_reg[20]_i_1_n_6 ; + wire \converge_cnt_reg[20]_i_1_n_7 ; + wire \converge_cnt_reg[4]_i_1_n_0 ; + wire \converge_cnt_reg[4]_i_1_n_1 ; + wire \converge_cnt_reg[4]_i_1_n_2 ; + wire \converge_cnt_reg[4]_i_1_n_3 ; + wire \converge_cnt_reg[4]_i_1_n_4 ; + wire \converge_cnt_reg[4]_i_1_n_5 ; + wire \converge_cnt_reg[4]_i_1_n_6 ; + wire \converge_cnt_reg[4]_i_1_n_7 ; + wire \converge_cnt_reg[6]_0 ; + wire \converge_cnt_reg[8]_i_1_n_0 ; + wire \converge_cnt_reg[8]_i_1_n_1 ; + wire \converge_cnt_reg[8]_i_1_n_2 ; + wire \converge_cnt_reg[8]_i_1_n_3 ; + wire \converge_cnt_reg[8]_i_1_n_4 ; + wire \converge_cnt_reg[8]_i_1_n_5 ; + wire \converge_cnt_reg[8]_i_1_n_6 ; + wire \converge_cnt_reg[8]_i_1_n_7 ; + wire converge_gen3_i_1_n_0; + wire converge_gen3_reg_0; + wire [0:0]gt_rx_elec_idle_wire_filter; + wire [0:0]gt_rx_phy_status_wire_filter; + wire gt_rxcdrlock_0; + wire gt_rxvalid_0; + wire gt_rxvalid_q_i_4_n_0; + wire gt_rxvalid_q_reg; + wire \gtx_channel.gtxe2_channel_i_i_58_n_0 ; + wire \gtx_channel.gtxe2_channel_i_i_59_n_0 ; + wire [1:0]oobclk_cnt; + wire \oobclk_div.oobclk_i_1_n_0 ; + wire [3:0]p_0_in__0; + wire [3:0]p_0_in__0__0; + wire [1:0]p_1_in__0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire pclk_sel_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire pclk_sel_reg2; + wire pipe_oobclk_in; + wire pipe_pclk_in; + wire [0:0]pipe_pclk_sel_out; + wire pipe_rx0_valid_gt; + wire pipe_rxusrclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_done_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_gen3_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_gen3_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_rxsync_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_rxsync_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg2; + wire [3:0]rxcdrlock_cnt_reg; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_adapt_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_adapt_done_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxstatus_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxstatus_reg2; + wire [3:0]rxvalid_cnt_reg; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxvalid_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxvalid_reg2; + wire sel; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txcompliance_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txcompliance_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txelecidle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txelecidle_reg2; + wire txelecidle_reg2_reg_1; + wire txphaligndone_reg1_reg; + wire txphaligndone_reg1_reg_0; + wire txphaligndone_reg1_reg_1; + wire txphinitdone_reg1_reg; + wire txphinitdone_reg1_reg_0; + wire txphinitdone_reg1_reg_1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg2; + wire user_active_lane_0; + wire user_active_lane_1; + wire [3:1]\NLW_converge_cnt_reg[20]_i_1_CO_UNCONNECTED ; + wire [3:2]\NLW_converge_cnt_reg[20]_i_1_O_UNCONNECTED ; + + assign out = rst_idle_reg2; + assign txcompliance_reg2_reg_0 = txcompliance_reg2; + assign txelecidle_reg2_reg_0 = txelecidle_reg2; + LUT4 #( + .INIT(16'h7077)) + \FSM_onehot_txsync_fsm.fsm_tx[5]_i_2 + (.I0(txelecidle_reg2), + .I1(txcompliance_reg2), + .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg[5] ), + .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ), + .O(txelecidle_reg2_reg_1)); + LUT2 #( + .INIT(4'h7)) + \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3 + (.I0(txcompliance_reg2), + .I1(txelecidle_reg2), + .O(user_active_lane_0)); + LUT4 #( + .INIT(16'hEFFF)) + \converge_cnt[0]_i_1__0 + (.I0(rate_gen3_reg2), + .I1(RST_CPLLRESET), + .I2(rst_idle_reg2), + .I3(rate_idle_reg2), + .O(\converge_cnt[0]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF5555555D)) + \converge_cnt[0]_i_2 + (.I0(converge_cnt_reg[21]), + .I1(\converge_cnt[0]_i_4_n_0 ), + .I2(converge_cnt_reg[12]), + .I3(converge_cnt_reg[14]), + .I4(converge_cnt_reg[20]), + .I5(\converge_cnt[0]_i_5_n_0 ), + .O(sel)); + LUT5 #( + .INIT(32'h00000001)) + \converge_cnt[0]_i_4 + (.I0(converge_cnt_reg[3]), + .I1(converge_cnt_reg[4]), + .I2(converge_cnt_reg[5]), + .I3(converge_cnt_reg[7]), + .I4(converge_cnt_reg[6]), + .O(\converge_cnt[0]_i_4_n_0 )); + LUT6 #( + .INIT(64'h0A0B0A0F0A0B0A0B)) + \converge_cnt[0]_i_5 + (.I0(\converge_cnt_reg[15]_0 ), + .I1(converge_cnt_reg[13]), + .I2(converge_cnt_reg[20]), + .I3(converge_cnt_reg[14]), + .I4(converge_cnt_reg[12]), + .I5(\gtx_channel.gtxe2_channel_i_i_59_n_0 ), + .O(\converge_cnt[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \converge_cnt[0]_i_6 + (.I0(converge_cnt_reg[0]), + .O(\converge_cnt[0]_i_6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3_n_7 ), + .Q(converge_cnt_reg[0]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[0]_i_3 + (.CI(1'b0), + .CO({\converge_cnt_reg[0]_i_3_n_0 ,\converge_cnt_reg[0]_i_3_n_1 ,\converge_cnt_reg[0]_i_3_n_2 ,\converge_cnt_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\converge_cnt_reg[0]_i_3_n_4 ,\converge_cnt_reg[0]_i_3_n_5 ,\converge_cnt_reg[0]_i_3_n_6 ,\converge_cnt_reg[0]_i_3_n_7 }), + .S({converge_cnt_reg[3:1],\converge_cnt[0]_i_6_n_0 })); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[10] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1_n_5 ), + .Q(converge_cnt_reg[10]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[11] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1_n_4 ), + .Q(converge_cnt_reg[11]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[12] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1_n_7 ), + .Q(converge_cnt_reg[12]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[12]_i_1 + (.CI(\converge_cnt_reg[8]_i_1_n_0 ), + .CO({\converge_cnt_reg[12]_i_1_n_0 ,\converge_cnt_reg[12]_i_1_n_1 ,\converge_cnt_reg[12]_i_1_n_2 ,\converge_cnt_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[12]_i_1_n_4 ,\converge_cnt_reg[12]_i_1_n_5 ,\converge_cnt_reg[12]_i_1_n_6 ,\converge_cnt_reg[12]_i_1_n_7 }), + .S(converge_cnt_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[13] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1_n_6 ), + .Q(converge_cnt_reg[13]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[14] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1_n_5 ), + .Q(converge_cnt_reg[14]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[15] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1_n_4 ), + .Q(converge_cnt_reg[15]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[16] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1_n_7 ), + .Q(converge_cnt_reg[16]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[16]_i_1 + (.CI(\converge_cnt_reg[12]_i_1_n_0 ), + .CO({\converge_cnt_reg[16]_i_1_n_0 ,\converge_cnt_reg[16]_i_1_n_1 ,\converge_cnt_reg[16]_i_1_n_2 ,\converge_cnt_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[16]_i_1_n_4 ,\converge_cnt_reg[16]_i_1_n_5 ,\converge_cnt_reg[16]_i_1_n_6 ,\converge_cnt_reg[16]_i_1_n_7 }), + .S(converge_cnt_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[17] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1_n_6 ), + .Q(converge_cnt_reg[17]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[18] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1_n_5 ), + .Q(converge_cnt_reg[18]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[19] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1_n_4 ), + .Q(converge_cnt_reg[19]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3_n_6 ), + .Q(converge_cnt_reg[1]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[20] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[20]_i_1_n_7 ), + .Q(converge_cnt_reg[20]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[20]_i_1 + (.CI(\converge_cnt_reg[16]_i_1_n_0 ), + .CO({\NLW_converge_cnt_reg[20]_i_1_CO_UNCONNECTED [3:1],\converge_cnt_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_converge_cnt_reg[20]_i_1_O_UNCONNECTED [3:2],\converge_cnt_reg[20]_i_1_n_6 ,\converge_cnt_reg[20]_i_1_n_7 }), + .S({1'b0,1'b0,converge_cnt_reg[21:20]})); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[21] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[20]_i_1_n_6 ), + .Q(converge_cnt_reg[21]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3_n_5 ), + .Q(converge_cnt_reg[2]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3_n_4 ), + .Q(converge_cnt_reg[3]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[4] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1_n_7 ), + .Q(converge_cnt_reg[4]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[4]_i_1 + (.CI(\converge_cnt_reg[0]_i_3_n_0 ), + .CO({\converge_cnt_reg[4]_i_1_n_0 ,\converge_cnt_reg[4]_i_1_n_1 ,\converge_cnt_reg[4]_i_1_n_2 ,\converge_cnt_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[4]_i_1_n_4 ,\converge_cnt_reg[4]_i_1_n_5 ,\converge_cnt_reg[4]_i_1_n_6 ,\converge_cnt_reg[4]_i_1_n_7 }), + .S(converge_cnt_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[5] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1_n_6 ), + .Q(converge_cnt_reg[5]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[6] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1_n_5 ), + .Q(converge_cnt_reg[6]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[7] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1_n_4 ), + .Q(converge_cnt_reg[7]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[8] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1_n_7 ), + .Q(converge_cnt_reg[8]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[8]_i_1 + (.CI(\converge_cnt_reg[4]_i_1_n_0 ), + .CO({\converge_cnt_reg[8]_i_1_n_0 ,\converge_cnt_reg[8]_i_1_n_1 ,\converge_cnt_reg[8]_i_1_n_2 ,\converge_cnt_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[8]_i_1_n_4 ,\converge_cnt_reg[8]_i_1_n_5 ,\converge_cnt_reg[8]_i_1_n_6 ,\converge_cnt_reg[8]_i_1_n_7 }), + .S(converge_cnt_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[9] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1_n_6 ), + .Q(converge_cnt_reg[9]), + .R(\converge_cnt[0]_i_1__0_n_0 )); + LUT3 #( + .INIT(8'hC8)) + converge_gen3_i_1 + (.I0(rxeq_adapt_done_reg2), + .I1(rate_gen3_reg2), + .I2(converge_gen3_reg_0), + .O(converge_gen3_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + converge_gen3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_gen3_i_1_n_0), + .Q(converge_gen3_reg_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hFFFFA8FF)) + gt_rx_phy_status_q_i_1 + (.I0(RST_PHYSTATUS), + .I1(rate_idle_reg2), + .I2(rate_rxsync_reg2), + .I3(rst_idle_reg2), + .I4(rate_done_reg2), + .O(gt_rx_phy_status_wire_filter)); + LUT6 #( + .INIT(64'hD000000000000000)) + gt_rxvalid_q_i_3 + (.I0(gt_rx_elec_idle_wire_filter), + .I1(pipe_rx0_valid_gt), + .I2(gt_rxvalid_q_i_4_n_0), + .I3(gt_rxvalid_0), + .I4(rst_idle_reg2), + .I5(rate_idle_reg2), + .O(gt_rxvalid_q_reg)); + LUT4 #( + .INIT(16'h8000)) + gt_rxvalid_q_i_4 + (.I0(rxvalid_cnt_reg[0]), + .I1(rxvalid_cnt_reg[1]), + .I2(rxvalid_cnt_reg[2]), + .I3(rxvalid_cnt_reg[3]), + .O(gt_rxvalid_q_i_4_n_0)); + LUT6 #( + .INIT(64'h0000000000020000)) + \gtx_channel.gtxe2_channel_i_i_49 + (.I0(\gtx_channel.gtxe2_channel_i_i_58_n_0 ), + .I1(converge_cnt_reg[1]), + .I2(converge_cnt_reg[0]), + .I3(converge_cnt_reg[2]), + .I4(converge_cnt_reg[3]), + .I5(\gtx_channel.gtxe2_channel_i_i_59_n_0 ), + .O(\converge_cnt_reg[1]_0 )); + LUT6 #( + .INIT(64'h0001000000000000)) + \gtx_channel.gtxe2_channel_i_i_50 + (.I0(converge_cnt_reg[6]), + .I1(converge_cnt_reg[7]), + .I2(converge_cnt_reg[4]), + .I3(converge_cnt_reg[5]), + .I4(converge_cnt_reg[21]), + .I5(converge_cnt_reg[13]), + .O(\converge_cnt_reg[6]_0 )); + LUT5 #( + .INIT(32'h7FFFFFFF)) + \gtx_channel.gtxe2_channel_i_i_51 + (.I0(converge_cnt_reg[15]), + .I1(converge_cnt_reg[18]), + .I2(converge_cnt_reg[19]), + .I3(converge_cnt_reg[17]), + .I4(converge_cnt_reg[16]), + .O(\converge_cnt_reg[15]_0 )); + LUT3 #( + .INIT(8'h01)) + \gtx_channel.gtxe2_channel_i_i_58 + (.I0(converge_cnt_reg[20]), + .I1(converge_cnt_reg[14]), + .I2(converge_cnt_reg[12]), + .O(\gtx_channel.gtxe2_channel_i_i_58_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \gtx_channel.gtxe2_channel_i_i_59 + (.I0(converge_cnt_reg[9]), + .I1(converge_cnt_reg[8]), + .I2(converge_cnt_reg[11]), + .I3(converge_cnt_reg[10]), + .O(\gtx_channel.gtxe2_channel_i_i_59_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT1 #( + .INIT(2'h1)) + \oobclk_div.oobclk_cnt[0]_i_1 + (.I0(oobclk_cnt[0]), + .O(p_1_in__0[0])); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT2 #( + .INIT(4'h6)) + \oobclk_div.oobclk_cnt[1]_i_1 + (.I0(oobclk_cnt[0]), + .I1(oobclk_cnt[1]), + .O(p_1_in__0[1])); + FDRE #( + .INIT(1'b0)) + \oobclk_div.oobclk_cnt_reg[0] + (.C(pipe_oobclk_in), + .CE(1'b1), + .D(p_1_in__0[0]), + .Q(oobclk_cnt[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \oobclk_div.oobclk_cnt_reg[1] + (.C(pipe_oobclk_in), + .CE(1'b1), + .D(p_1_in__0[1]), + .Q(oobclk_cnt[1]), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'hB8)) + \oobclk_div.oobclk_i_1 + (.I0(oobclk_cnt[1]), + .I1(pclk_sel_reg2), + .I2(oobclk_cnt[0]), + .O(\oobclk_div.oobclk_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \oobclk_div.oobclk_reg + (.C(pipe_oobclk_in), + .CE(1'b1), + .D(\oobclk_div.oobclk_i_1_n_0 ), + .Q(USER_OOBCLK), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE pclk_sel_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_pclk_sel_out), + .Q(pclk_sel_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE pclk_sel_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pclk_sel_reg1), + .Q(pclk_sel_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_done_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_DONE), + .Q(rate_done_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_done_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_done_reg1), + .Q(rate_done_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_gen3_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_GEN3), + .Q(rate_gen3_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_gen3_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_gen3_reg1), + .Q(rate_gen3_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_IDLE), + .Q(rate_idle_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_idle_reg1), + .Q(rate_idle_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_rxsync_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_RXSYNC), + .Q(rate_rxsync_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_rxsync_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_rxsync_reg1), + .Q(rate_rxsync_reg2), + .R(RST_RXUSRCLK_RESET)); + LUT2 #( + .INIT(4'h8)) + \resetdone_reg1[0]_i_1 + (.I0(rxresetdone_reg2), + .I1(txresetdone_reg2), + .O(RST_RESETDONE)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_start_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RESETOVRD_START), + .Q(resetovrd_start_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_start_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(resetovrd_start_reg1), + .Q(resetovrd_start_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(RST_IDLE), + .Q(rst_idle_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rst_idle_reg1), + .Q(rst_idle_reg2), + .R(RST_RXUSRCLK_RESET)); + LUT5 #( + .INIT(32'hD0505050)) + \rxcdrlock_cnt[0]_i_1 + (.I0(rxcdrlock_cnt_reg[0]), + .I1(rxcdrlock_cnt_reg[2]), + .I2(rxcdrlock_reg2), + .I3(rxcdrlock_cnt_reg[1]), + .I4(rxcdrlock_cnt_reg[3]), + .O(p_0_in__0[0])); + LUT5 #( + .INIT(32'h8FF00000)) + \rxcdrlock_cnt[1]_i_1 + (.I0(rxcdrlock_cnt_reg[3]), + .I1(rxcdrlock_cnt_reg[2]), + .I2(rxcdrlock_cnt_reg[0]), + .I3(rxcdrlock_cnt_reg[1]), + .I4(rxcdrlock_reg2), + .O(p_0_in__0[1])); + LUT5 #( + .INIT(32'hF8780000)) + \rxcdrlock_cnt[2]_i_1 + (.I0(rxcdrlock_cnt_reg[0]), + .I1(rxcdrlock_cnt_reg[1]), + .I2(rxcdrlock_cnt_reg[2]), + .I3(rxcdrlock_cnt_reg[3]), + .I4(rxcdrlock_reg2), + .O(p_0_in__0[2])); + LUT5 #( + .INIT(32'hFF008000)) + \rxcdrlock_cnt[3]_i_1 + (.I0(rxcdrlock_cnt_reg[0]), + .I1(rxcdrlock_cnt_reg[1]), + .I2(rxcdrlock_cnt_reg[2]), + .I3(rxcdrlock_reg2), + .I4(rxcdrlock_cnt_reg[3]), + .O(p_0_in__0[3])); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[0]), + .Q(rxcdrlock_cnt_reg[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[1]), + .Q(rxcdrlock_cnt_reg[1]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[2]), + .Q(rxcdrlock_cnt_reg[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[3]), + .Q(rxcdrlock_cnt_reg[3]), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h80000000)) + \rxcdrlock_reg1[0]_i_1 + (.I0(rxcdrlock_cnt_reg[2]), + .I1(rxcdrlock_cnt_reg[3]), + .I2(gt_rxcdrlock_0), + .I3(rxcdrlock_cnt_reg[1]), + .I4(rxcdrlock_cnt_reg[0]), + .O(RST_RXCDRLOCK)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rxcdrlock_0), + .Q(rxcdrlock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxcdrlock_reg1), + .Q(rxcdrlock_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_adapt_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RXEQ_ADAPT_DONE), + .Q(rxeq_adapt_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_adapt_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_adapt_done_reg1), + .Q(rxeq_adapt_done_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RXRESETDONE), + .Q(rxresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxresetdone_reg1), + .Q(rxresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxstatus_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(PIPE_RXSTATUS), + .Q(rxstatus_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxstatus_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rxstatus_reg1), + .Q(rxstatus_reg2), + .R(RST_RXUSRCLK_RESET)); + LUT6 #( + .INIT(64'hC404040404040404)) + \rxvalid_cnt[0]_i_1 + (.I0(rxstatus_reg2), + .I1(rxvalid_reg2), + .I2(rxvalid_cnt_reg[0]), + .I3(rxvalid_cnt_reg[1]), + .I4(rxvalid_cnt_reg[2]), + .I5(rxvalid_cnt_reg[3]), + .O(p_0_in__0__0[0])); + LUT6 #( + .INIT(64'h808000F000F00000)) + \rxvalid_cnt[1]_i_1 + (.I0(rxvalid_cnt_reg[3]), + .I1(rxvalid_cnt_reg[2]), + .I2(rxvalid_reg2), + .I3(rxstatus_reg2), + .I4(rxvalid_cnt_reg[1]), + .I5(rxvalid_cnt_reg[0]), + .O(p_0_in__0__0[1])); + LUT6 #( + .INIT(64'h80BF000000C00000)) + \rxvalid_cnt[2]_i_1 + (.I0(rxvalid_cnt_reg[3]), + .I1(rxvalid_cnt_reg[0]), + .I2(rxvalid_cnt_reg[1]), + .I3(rxstatus_reg2), + .I4(rxvalid_reg2), + .I5(rxvalid_cnt_reg[2]), + .O(p_0_in__0__0[2])); + LUT6 #( + .INIT(64'h8C08080808080808)) + \rxvalid_cnt[3]_i_1 + (.I0(rxvalid_cnt_reg[3]), + .I1(rxvalid_reg2), + .I2(rxstatus_reg2), + .I3(rxvalid_cnt_reg[2]), + .I4(rxvalid_cnt_reg[1]), + .I5(rxvalid_cnt_reg[0]), + .O(p_0_in__0__0[3])); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[0] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[0]), + .Q(rxvalid_cnt_reg[0]), + .R(RST_RXUSRCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[1] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[1]), + .Q(rxvalid_cnt_reg[1]), + .R(RST_RXUSRCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[2] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[2]), + .Q(rxvalid_cnt_reg[2]), + .R(RST_RXUSRCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[3] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[3]), + .Q(rxvalid_cnt_reg[3]), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxvalid_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(gt_rxvalid_0), + .Q(rxvalid_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxvalid_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rxvalid_reg1), + .Q(rxvalid_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txcompliance_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_TXCOMPLIANCE), + .Q(txcompliance_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txcompliance_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcompliance_reg1), + .Q(txcompliance_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txelecidle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_TXELECIDLE), + .Q(txelecidle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txelecidle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txelecidle_reg1), + .Q(txelecidle_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h00000000BBB0B0B0)) + txphaligndone_reg1_i_1 + (.I0(txphaligndone_reg1_reg), + .I1(user_active_lane_1), + .I2(txphaligndone_reg1_reg_0), + .I3(txelecidle_reg2), + .I4(txcompliance_reg2), + .I5(txphaligndone_reg1_reg_1), + .O(SYNC_TXPHALIGNDONE)); + LUT6 #( + .INIT(64'h00000000BBB0B0B0)) + txphinitdone_reg1_i_1 + (.I0(txphinitdone_reg1_reg), + .I1(user_active_lane_1), + .I2(txphinitdone_reg1_reg_0), + .I3(txelecidle_reg2), + .I4(txcompliance_reg2), + .I5(txphinitdone_reg1_reg_1), + .O(SYNC_TXPHINITDONE)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_TXRESETDONE), + .Q(txresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txresetdone_reg1), + .Q(txresetdone_reg2), + .R(RST_CPLLRESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_user" *) +module pcie_7x_0_pcie_7x_0_pipe_user_42 + (gt_rxvalid_q_reg, + out, + txelecidle_reg2_reg_0, + txcompliance_reg2_reg_0, + USER_OOBCLK, + RST_RXCDRLOCK, + gt_rx_phy_status_wire_filter, + user_rx_converge, + RST_RESETDONE, + user_active_lane_1, + gt_rx_elec_idle_wire_filter, + pipe_rx1_valid_gt, + gt_rxvalid_1, + RST_CPLLRESET, + pipe_pclk_sel_out, + pipe_pclk_in, + pipe_oobclk_in, + USER_TXRESETDONE, + USER_RXRESETDONE, + PIPE_TXELECIDLE, + PIPE_TXCOMPLIANCE, + gt_rxcdrlock_1, + RST_RXUSRCLK_RESET, + pipe_rxusrclk_in, + rxstatus_reg1_reg_0, + RST_IDLE, + USER_RATE_IDLE, + USER_RATE_RXSYNC, + USER_RATE_DONE, + USER_RATE_GEN3, + USER_RXEQ_ADAPT_DONE, + USER_RESETOVRD_START, + RST_PHYSTATUS); + output gt_rxvalid_q_reg; + output out; + output txelecidle_reg2_reg_0; + output txcompliance_reg2_reg_0; + output USER_OOBCLK; + output [0:0]RST_RXCDRLOCK; + output [0:0]gt_rx_phy_status_wire_filter; + output [0:0]user_rx_converge; + output [0:0]RST_RESETDONE; + output user_active_lane_1; + input [0:0]gt_rx_elec_idle_wire_filter; + input pipe_rx1_valid_gt; + input gt_rxvalid_1; + input RST_CPLLRESET; + input [0:0]pipe_pclk_sel_out; + input pipe_pclk_in; + input pipe_oobclk_in; + input USER_TXRESETDONE; + input USER_RXRESETDONE; + input [0:0]PIPE_TXELECIDLE; + input [0:0]PIPE_TXCOMPLIANCE; + input gt_rxcdrlock_1; + input RST_RXUSRCLK_RESET; + input pipe_rxusrclk_in; + input [0:0]rxstatus_reg1_reg_0; + input RST_IDLE; + input USER_RATE_IDLE; + input USER_RATE_RXSYNC; + input USER_RATE_DONE; + input USER_RATE_GEN3; + input USER_RXEQ_ADAPT_DONE; + input USER_RESETOVRD_START; + input [0:0]RST_PHYSTATUS; + + wire [0:0]PIPE_TXCOMPLIANCE; + wire [0:0]PIPE_TXELECIDLE; + wire RST_CPLLRESET; + wire RST_IDLE; + wire [0:0]RST_PHYSTATUS; + wire [0:0]RST_RESETDONE; + wire [0:0]RST_RXCDRLOCK; + wire RST_RXUSRCLK_RESET; + wire USER_OOBCLK; + wire USER_RATE_DONE; + wire USER_RATE_GEN3; + wire USER_RATE_IDLE; + wire USER_RATE_RXSYNC; + wire USER_RESETOVRD_START; + wire USER_RXEQ_ADAPT_DONE; + wire USER_RXRESETDONE; + wire USER_TXRESETDONE; + wire \converge_cnt[0]_i_1__2_n_0 ; + wire \converge_cnt[0]_i_4__0_n_0 ; + wire \converge_cnt[0]_i_5__0_n_0 ; + wire \converge_cnt[0]_i_6__0_n_0 ; + wire [21:0]converge_cnt_reg; + wire \converge_cnt_reg[0]_i_3__0_n_0 ; + wire \converge_cnt_reg[0]_i_3__0_n_1 ; + wire \converge_cnt_reg[0]_i_3__0_n_2 ; + wire \converge_cnt_reg[0]_i_3__0_n_3 ; + wire \converge_cnt_reg[0]_i_3__0_n_4 ; + wire \converge_cnt_reg[0]_i_3__0_n_5 ; + wire \converge_cnt_reg[0]_i_3__0_n_6 ; + wire \converge_cnt_reg[0]_i_3__0_n_7 ; + wire \converge_cnt_reg[12]_i_1__0_n_0 ; + wire \converge_cnt_reg[12]_i_1__0_n_1 ; + wire \converge_cnt_reg[12]_i_1__0_n_2 ; + wire \converge_cnt_reg[12]_i_1__0_n_3 ; + wire \converge_cnt_reg[12]_i_1__0_n_4 ; + wire \converge_cnt_reg[12]_i_1__0_n_5 ; + wire \converge_cnt_reg[12]_i_1__0_n_6 ; + wire \converge_cnt_reg[12]_i_1__0_n_7 ; + wire \converge_cnt_reg[16]_i_1__0_n_0 ; + wire \converge_cnt_reg[16]_i_1__0_n_1 ; + wire \converge_cnt_reg[16]_i_1__0_n_2 ; + wire \converge_cnt_reg[16]_i_1__0_n_3 ; + wire \converge_cnt_reg[16]_i_1__0_n_4 ; + wire \converge_cnt_reg[16]_i_1__0_n_5 ; + wire \converge_cnt_reg[16]_i_1__0_n_6 ; + wire \converge_cnt_reg[16]_i_1__0_n_7 ; + wire \converge_cnt_reg[20]_i_1__0_n_3 ; + wire \converge_cnt_reg[20]_i_1__0_n_6 ; + wire \converge_cnt_reg[20]_i_1__0_n_7 ; + wire \converge_cnt_reg[4]_i_1__0_n_0 ; + wire \converge_cnt_reg[4]_i_1__0_n_1 ; + wire \converge_cnt_reg[4]_i_1__0_n_2 ; + wire \converge_cnt_reg[4]_i_1__0_n_3 ; + wire \converge_cnt_reg[4]_i_1__0_n_4 ; + wire \converge_cnt_reg[4]_i_1__0_n_5 ; + wire \converge_cnt_reg[4]_i_1__0_n_6 ; + wire \converge_cnt_reg[4]_i_1__0_n_7 ; + wire \converge_cnt_reg[8]_i_1__0_n_0 ; + wire \converge_cnt_reg[8]_i_1__0_n_1 ; + wire \converge_cnt_reg[8]_i_1__0_n_2 ; + wire \converge_cnt_reg[8]_i_1__0_n_3 ; + wire \converge_cnt_reg[8]_i_1__0_n_4 ; + wire \converge_cnt_reg[8]_i_1__0_n_5 ; + wire \converge_cnt_reg[8]_i_1__0_n_6 ; + wire \converge_cnt_reg[8]_i_1__0_n_7 ; + wire converge_gen3_i_1__0_n_0; + wire converge_gen3_reg_n_0; + wire [0:0]gt_rx_elec_idle_wire_filter; + wire [0:0]gt_rx_phy_status_wire_filter; + wire gt_rxcdrlock_1; + wire gt_rxvalid_1; + wire gt_rxvalid_q_i_4__0_n_0; + wire gt_rxvalid_q_reg; + wire \gtx_channel.gtxe2_channel_i_i_53_n_0 ; + wire \gtx_channel.gtxe2_channel_i_i_54_n_0 ; + wire \gtx_channel.gtxe2_channel_i_i_55_n_0 ; + wire \gtx_channel.gtxe2_channel_i_i_56_n_0 ; + wire \gtx_channel.gtxe2_channel_i_i_57_n_0 ; + wire [1:0]oobclk_cnt; + wire \oobclk_div.oobclk_i_1__0_n_0 ; + wire [3:0]p_0_in__0; + wire [3:0]p_0_in__0__0; + wire [1:0]p_1_in__0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire pclk_sel_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire pclk_sel_reg2; + wire pipe_oobclk_in; + wire pipe_pclk_in; + wire [0:0]pipe_pclk_sel_out; + wire pipe_rx1_valid_gt; + wire pipe_rxusrclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_done_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_gen3_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_gen3_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_rxsync_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_rxsync_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg2; + wire [3:0]rxcdrlock_cnt_reg; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_adapt_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_adapt_done_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxstatus_reg1; + wire [0:0]rxstatus_reg1_reg_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxstatus_reg2; + wire [3:0]rxvalid_cnt_reg; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxvalid_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxvalid_reg2; + wire sel; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txcompliance_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txcompliance_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txelecidle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txelecidle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg2; + wire user_active_lane_1; + wire [0:0]user_rx_converge; + wire [3:1]\NLW_converge_cnt_reg[20]_i_1__0_CO_UNCONNECTED ; + wire [3:2]\NLW_converge_cnt_reg[20]_i_1__0_O_UNCONNECTED ; + + assign out = rst_idle_reg2; + assign txcompliance_reg2_reg_0 = txcompliance_reg2; + assign txelecidle_reg2_reg_0 = txelecidle_reg2; + LUT4 #( + .INIT(16'hEFFF)) + \converge_cnt[0]_i_1__2 + (.I0(rate_gen3_reg2), + .I1(RST_CPLLRESET), + .I2(rst_idle_reg2), + .I3(rate_idle_reg2), + .O(\converge_cnt[0]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF5555555D)) + \converge_cnt[0]_i_2__0 + (.I0(converge_cnt_reg[21]), + .I1(\converge_cnt[0]_i_4__0_n_0 ), + .I2(converge_cnt_reg[12]), + .I3(converge_cnt_reg[14]), + .I4(converge_cnt_reg[20]), + .I5(\converge_cnt[0]_i_5__0_n_0 ), + .O(sel)); + LUT5 #( + .INIT(32'h00000001)) + \converge_cnt[0]_i_4__0 + (.I0(converge_cnt_reg[3]), + .I1(converge_cnt_reg[4]), + .I2(converge_cnt_reg[5]), + .I3(converge_cnt_reg[7]), + .I4(converge_cnt_reg[6]), + .O(\converge_cnt[0]_i_4__0_n_0 )); + LUT6 #( + .INIT(64'h0A0B0A0F0A0B0A0B)) + \converge_cnt[0]_i_5__0 + (.I0(\gtx_channel.gtxe2_channel_i_i_57_n_0 ), + .I1(converge_cnt_reg[13]), + .I2(converge_cnt_reg[20]), + .I3(converge_cnt_reg[14]), + .I4(converge_cnt_reg[12]), + .I5(\gtx_channel.gtxe2_channel_i_i_55_n_0 ), + .O(\converge_cnt[0]_i_5__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \converge_cnt[0]_i_6__0 + (.I0(converge_cnt_reg[0]), + .O(\converge_cnt[0]_i_6__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3__0_n_7 ), + .Q(converge_cnt_reg[0]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[0]_i_3__0 + (.CI(1'b0), + .CO({\converge_cnt_reg[0]_i_3__0_n_0 ,\converge_cnt_reg[0]_i_3__0_n_1 ,\converge_cnt_reg[0]_i_3__0_n_2 ,\converge_cnt_reg[0]_i_3__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\converge_cnt_reg[0]_i_3__0_n_4 ,\converge_cnt_reg[0]_i_3__0_n_5 ,\converge_cnt_reg[0]_i_3__0_n_6 ,\converge_cnt_reg[0]_i_3__0_n_7 }), + .S({converge_cnt_reg[3:1],\converge_cnt[0]_i_6__0_n_0 })); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[10] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1__0_n_5 ), + .Q(converge_cnt_reg[10]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[11] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1__0_n_4 ), + .Q(converge_cnt_reg[11]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[12] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1__0_n_7 ), + .Q(converge_cnt_reg[12]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[12]_i_1__0 + (.CI(\converge_cnt_reg[8]_i_1__0_n_0 ), + .CO({\converge_cnt_reg[12]_i_1__0_n_0 ,\converge_cnt_reg[12]_i_1__0_n_1 ,\converge_cnt_reg[12]_i_1__0_n_2 ,\converge_cnt_reg[12]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[12]_i_1__0_n_4 ,\converge_cnt_reg[12]_i_1__0_n_5 ,\converge_cnt_reg[12]_i_1__0_n_6 ,\converge_cnt_reg[12]_i_1__0_n_7 }), + .S(converge_cnt_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[13] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1__0_n_6 ), + .Q(converge_cnt_reg[13]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[14] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1__0_n_5 ), + .Q(converge_cnt_reg[14]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[15] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1__0_n_4 ), + .Q(converge_cnt_reg[15]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[16] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1__0_n_7 ), + .Q(converge_cnt_reg[16]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[16]_i_1__0 + (.CI(\converge_cnt_reg[12]_i_1__0_n_0 ), + .CO({\converge_cnt_reg[16]_i_1__0_n_0 ,\converge_cnt_reg[16]_i_1__0_n_1 ,\converge_cnt_reg[16]_i_1__0_n_2 ,\converge_cnt_reg[16]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[16]_i_1__0_n_4 ,\converge_cnt_reg[16]_i_1__0_n_5 ,\converge_cnt_reg[16]_i_1__0_n_6 ,\converge_cnt_reg[16]_i_1__0_n_7 }), + .S(converge_cnt_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[17] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1__0_n_6 ), + .Q(converge_cnt_reg[17]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[18] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1__0_n_5 ), + .Q(converge_cnt_reg[18]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[19] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1__0_n_4 ), + .Q(converge_cnt_reg[19]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3__0_n_6 ), + .Q(converge_cnt_reg[1]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[20] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[20]_i_1__0_n_7 ), + .Q(converge_cnt_reg[20]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[20]_i_1__0 + (.CI(\converge_cnt_reg[16]_i_1__0_n_0 ), + .CO({\NLW_converge_cnt_reg[20]_i_1__0_CO_UNCONNECTED [3:1],\converge_cnt_reg[20]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_converge_cnt_reg[20]_i_1__0_O_UNCONNECTED [3:2],\converge_cnt_reg[20]_i_1__0_n_6 ,\converge_cnt_reg[20]_i_1__0_n_7 }), + .S({1'b0,1'b0,converge_cnt_reg[21:20]})); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[21] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[20]_i_1__0_n_6 ), + .Q(converge_cnt_reg[21]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3__0_n_5 ), + .Q(converge_cnt_reg[2]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3__0_n_4 ), + .Q(converge_cnt_reg[3]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[4] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1__0_n_7 ), + .Q(converge_cnt_reg[4]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[4]_i_1__0 + (.CI(\converge_cnt_reg[0]_i_3__0_n_0 ), + .CO({\converge_cnt_reg[4]_i_1__0_n_0 ,\converge_cnt_reg[4]_i_1__0_n_1 ,\converge_cnt_reg[4]_i_1__0_n_2 ,\converge_cnt_reg[4]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[4]_i_1__0_n_4 ,\converge_cnt_reg[4]_i_1__0_n_5 ,\converge_cnt_reg[4]_i_1__0_n_6 ,\converge_cnt_reg[4]_i_1__0_n_7 }), + .S(converge_cnt_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[5] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1__0_n_6 ), + .Q(converge_cnt_reg[5]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[6] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1__0_n_5 ), + .Q(converge_cnt_reg[6]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[7] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1__0_n_4 ), + .Q(converge_cnt_reg[7]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[8] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1__0_n_7 ), + .Q(converge_cnt_reg[8]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[8]_i_1__0 + (.CI(\converge_cnt_reg[4]_i_1__0_n_0 ), + .CO({\converge_cnt_reg[8]_i_1__0_n_0 ,\converge_cnt_reg[8]_i_1__0_n_1 ,\converge_cnt_reg[8]_i_1__0_n_2 ,\converge_cnt_reg[8]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[8]_i_1__0_n_4 ,\converge_cnt_reg[8]_i_1__0_n_5 ,\converge_cnt_reg[8]_i_1__0_n_6 ,\converge_cnt_reg[8]_i_1__0_n_7 }), + .S(converge_cnt_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[9] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1__0_n_6 ), + .Q(converge_cnt_reg[9]), + .R(\converge_cnt[0]_i_1__2_n_0 )); + LUT3 #( + .INIT(8'hC8)) + converge_gen3_i_1__0 + (.I0(rxeq_adapt_done_reg2), + .I1(rate_gen3_reg2), + .I2(converge_gen3_reg_n_0), + .O(converge_gen3_i_1__0_n_0)); + FDRE #( + .INIT(1'b0)) + converge_gen3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_gen3_i_1__0_n_0), + .Q(converge_gen3_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hFFFFA8FF)) + gt_rx_phy_status_q_i_1__0 + (.I0(RST_PHYSTATUS), + .I1(rate_idle_reg2), + .I2(rate_rxsync_reg2), + .I3(rst_idle_reg2), + .I4(rate_done_reg2), + .O(gt_rx_phy_status_wire_filter)); + LUT6 #( + .INIT(64'hD000000000000000)) + gt_rxvalid_q_i_3__0 + (.I0(gt_rx_elec_idle_wire_filter), + .I1(pipe_rx1_valid_gt), + .I2(gt_rxvalid_q_i_4__0_n_0), + .I3(gt_rxvalid_1), + .I4(rst_idle_reg2), + .I5(rate_idle_reg2), + .O(gt_rxvalid_q_reg)); + LUT4 #( + .INIT(16'h8000)) + gt_rxvalid_q_i_4__0 + (.I0(rxvalid_cnt_reg[0]), + .I1(rxvalid_cnt_reg[1]), + .I2(rxvalid_cnt_reg[2]), + .I3(rxvalid_cnt_reg[3]), + .O(gt_rxvalid_q_i_4__0_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFF00000800)) + \gtx_channel.gtxe2_channel_i_i_48 + (.I0(\gtx_channel.gtxe2_channel_i_i_53_n_0 ), + .I1(\gtx_channel.gtxe2_channel_i_i_54_n_0 ), + .I2(\gtx_channel.gtxe2_channel_i_i_55_n_0 ), + .I3(\gtx_channel.gtxe2_channel_i_i_56_n_0 ), + .I4(\gtx_channel.gtxe2_channel_i_i_57_n_0 ), + .I5(converge_gen3_reg_n_0), + .O(user_rx_converge)); + LUT3 #( + .INIT(8'h01)) + \gtx_channel.gtxe2_channel_i_i_53 + (.I0(converge_cnt_reg[20]), + .I1(converge_cnt_reg[14]), + .I2(converge_cnt_reg[12]), + .O(\gtx_channel.gtxe2_channel_i_i_53_n_0 )); + LUT4 #( + .INIT(16'h0100)) + \gtx_channel.gtxe2_channel_i_i_54 + (.I0(converge_cnt_reg[1]), + .I1(converge_cnt_reg[0]), + .I2(converge_cnt_reg[2]), + .I3(converge_cnt_reg[3]), + .O(\gtx_channel.gtxe2_channel_i_i_54_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \gtx_channel.gtxe2_channel_i_i_55 + (.I0(converge_cnt_reg[9]), + .I1(converge_cnt_reg[8]), + .I2(converge_cnt_reg[11]), + .I3(converge_cnt_reg[10]), + .O(\gtx_channel.gtxe2_channel_i_i_55_n_0 )); + LUT6 #( + .INIT(64'h0001000000000000)) + \gtx_channel.gtxe2_channel_i_i_56 + (.I0(converge_cnt_reg[6]), + .I1(converge_cnt_reg[7]), + .I2(converge_cnt_reg[4]), + .I3(converge_cnt_reg[5]), + .I4(converge_cnt_reg[21]), + .I5(converge_cnt_reg[13]), + .O(\gtx_channel.gtxe2_channel_i_i_56_n_0 )); + LUT5 #( + .INIT(32'h7FFFFFFF)) + \gtx_channel.gtxe2_channel_i_i_57 + (.I0(converge_cnt_reg[15]), + .I1(converge_cnt_reg[18]), + .I2(converge_cnt_reg[19]), + .I3(converge_cnt_reg[17]), + .I4(converge_cnt_reg[16]), + .O(\gtx_channel.gtxe2_channel_i_i_57_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT1 #( + .INIT(2'h1)) + \oobclk_div.oobclk_cnt[0]_i_1__0 + (.I0(oobclk_cnt[0]), + .O(p_1_in__0[0])); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT2 #( + .INIT(4'h6)) + \oobclk_div.oobclk_cnt[1]_i_1__0 + (.I0(oobclk_cnt[0]), + .I1(oobclk_cnt[1]), + .O(p_1_in__0[1])); + FDRE #( + .INIT(1'b0)) + \oobclk_div.oobclk_cnt_reg[0] + (.C(pipe_oobclk_in), + .CE(1'b1), + .D(p_1_in__0[0]), + .Q(oobclk_cnt[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \oobclk_div.oobclk_cnt_reg[1] + (.C(pipe_oobclk_in), + .CE(1'b1), + .D(p_1_in__0[1]), + .Q(oobclk_cnt[1]), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'hB8)) + \oobclk_div.oobclk_i_1__0 + (.I0(oobclk_cnt[1]), + .I1(pclk_sel_reg2), + .I2(oobclk_cnt[0]), + .O(\oobclk_div.oobclk_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \oobclk_div.oobclk_reg + (.C(pipe_oobclk_in), + .CE(1'b1), + .D(\oobclk_div.oobclk_i_1__0_n_0 ), + .Q(USER_OOBCLK), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE pclk_sel_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_pclk_sel_out), + .Q(pclk_sel_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE pclk_sel_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pclk_sel_reg1), + .Q(pclk_sel_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_done_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_DONE), + .Q(rate_done_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_done_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_done_reg1), + .Q(rate_done_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_gen3_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_GEN3), + .Q(rate_gen3_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_gen3_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_gen3_reg1), + .Q(rate_gen3_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_IDLE), + .Q(rate_idle_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_idle_reg1), + .Q(rate_idle_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_rxsync_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_RXSYNC), + .Q(rate_rxsync_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_rxsync_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_rxsync_reg1), + .Q(rate_rxsync_reg2), + .R(RST_RXUSRCLK_RESET)); + LUT2 #( + .INIT(4'h8)) + \resetdone_reg1[1]_i_1 + (.I0(rxresetdone_reg2), + .I1(txresetdone_reg2), + .O(RST_RESETDONE)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_start_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RESETOVRD_START), + .Q(resetovrd_start_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_start_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(resetovrd_start_reg1), + .Q(resetovrd_start_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(RST_IDLE), + .Q(rst_idle_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rst_idle_reg1), + .Q(rst_idle_reg2), + .R(RST_RXUSRCLK_RESET)); + LUT5 #( + .INIT(32'hD0505050)) + \rxcdrlock_cnt[0]_i_1__0 + (.I0(rxcdrlock_cnt_reg[0]), + .I1(rxcdrlock_cnt_reg[2]), + .I2(rxcdrlock_reg2), + .I3(rxcdrlock_cnt_reg[1]), + .I4(rxcdrlock_cnt_reg[3]), + .O(p_0_in__0[0])); + LUT5 #( + .INIT(32'h8FF00000)) + \rxcdrlock_cnt[1]_i_1__0 + (.I0(rxcdrlock_cnt_reg[3]), + .I1(rxcdrlock_cnt_reg[2]), + .I2(rxcdrlock_cnt_reg[0]), + .I3(rxcdrlock_cnt_reg[1]), + .I4(rxcdrlock_reg2), + .O(p_0_in__0[1])); + LUT5 #( + .INIT(32'hF8780000)) + \rxcdrlock_cnt[2]_i_1__0 + (.I0(rxcdrlock_cnt_reg[0]), + .I1(rxcdrlock_cnt_reg[1]), + .I2(rxcdrlock_cnt_reg[2]), + .I3(rxcdrlock_cnt_reg[3]), + .I4(rxcdrlock_reg2), + .O(p_0_in__0[2])); + LUT5 #( + .INIT(32'hFF008000)) + \rxcdrlock_cnt[3]_i_1__0 + (.I0(rxcdrlock_cnt_reg[0]), + .I1(rxcdrlock_cnt_reg[1]), + .I2(rxcdrlock_cnt_reg[2]), + .I3(rxcdrlock_reg2), + .I4(rxcdrlock_cnt_reg[3]), + .O(p_0_in__0[3])); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[0]), + .Q(rxcdrlock_cnt_reg[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[1]), + .Q(rxcdrlock_cnt_reg[1]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[2]), + .Q(rxcdrlock_cnt_reg[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[3]), + .Q(rxcdrlock_cnt_reg[3]), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h80000000)) + \rxcdrlock_reg1[1]_i_1 + (.I0(rxcdrlock_cnt_reg[2]), + .I1(rxcdrlock_cnt_reg[3]), + .I2(gt_rxcdrlock_1), + .I3(rxcdrlock_cnt_reg[1]), + .I4(rxcdrlock_cnt_reg[0]), + .O(RST_RXCDRLOCK)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rxcdrlock_1), + .Q(rxcdrlock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxcdrlock_reg1), + .Q(rxcdrlock_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_adapt_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RXEQ_ADAPT_DONE), + .Q(rxeq_adapt_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_adapt_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_adapt_done_reg1), + .Q(rxeq_adapt_done_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RXRESETDONE), + .Q(rxresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxresetdone_reg1), + .Q(rxresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxstatus_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rxstatus_reg1_reg_0), + .Q(rxstatus_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxstatus_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rxstatus_reg1), + .Q(rxstatus_reg2), + .R(RST_RXUSRCLK_RESET)); + LUT6 #( + .INIT(64'hC404040404040404)) + \rxvalid_cnt[0]_i_1__0 + (.I0(rxstatus_reg2), + .I1(rxvalid_reg2), + .I2(rxvalid_cnt_reg[0]), + .I3(rxvalid_cnt_reg[1]), + .I4(rxvalid_cnt_reg[2]), + .I5(rxvalid_cnt_reg[3]), + .O(p_0_in__0__0[0])); + LUT6 #( + .INIT(64'h808000F000F00000)) + \rxvalid_cnt[1]_i_1__0 + (.I0(rxvalid_cnt_reg[3]), + .I1(rxvalid_cnt_reg[2]), + .I2(rxvalid_reg2), + .I3(rxstatus_reg2), + .I4(rxvalid_cnt_reg[1]), + .I5(rxvalid_cnt_reg[0]), + .O(p_0_in__0__0[1])); + LUT6 #( + .INIT(64'h80BF000000C00000)) + \rxvalid_cnt[2]_i_1__0 + (.I0(rxvalid_cnt_reg[3]), + .I1(rxvalid_cnt_reg[0]), + .I2(rxvalid_cnt_reg[1]), + .I3(rxstatus_reg2), + .I4(rxvalid_reg2), + .I5(rxvalid_cnt_reg[2]), + .O(p_0_in__0__0[2])); + LUT6 #( + .INIT(64'h8C08080808080808)) + \rxvalid_cnt[3]_i_1__0 + (.I0(rxvalid_cnt_reg[3]), + .I1(rxvalid_reg2), + .I2(rxstatus_reg2), + .I3(rxvalid_cnt_reg[2]), + .I4(rxvalid_cnt_reg[1]), + .I5(rxvalid_cnt_reg[0]), + .O(p_0_in__0__0[3])); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[0] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[0]), + .Q(rxvalid_cnt_reg[0]), + .R(RST_RXUSRCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[1] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[1]), + .Q(rxvalid_cnt_reg[1]), + .R(RST_RXUSRCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[2] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[2]), + .Q(rxvalid_cnt_reg[2]), + .R(RST_RXUSRCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[3] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[3]), + .Q(rxvalid_cnt_reg[3]), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxvalid_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(gt_rxvalid_1), + .Q(rxvalid_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxvalid_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rxvalid_reg1), + .Q(rxvalid_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txcompliance_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_TXCOMPLIANCE), + .Q(txcompliance_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txcompliance_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcompliance_reg1), + .Q(txcompliance_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txelecidle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_TXELECIDLE), + .Q(txelecidle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txelecidle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txelecidle_reg1), + .Q(txelecidle_reg2), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h7)) + txphaligndone_reg1_i_2 + (.I0(txcompliance_reg2), + .I1(txelecidle_reg2), + .O(user_active_lane_1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_TXRESETDONE), + .Q(txresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txresetdone_reg1), + .Q(txresetdone_reg2), + .R(RST_CPLLRESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_user" *) +module pcie_7x_0_pcie_7x_0_pipe_user_48 + (reg_clock_locked_reg, + gt_rxvalid_q_reg, + txcompliance_reg2_reg_0, + txcompliance_reg2_reg_1, + txelecidle_reg2_reg_0, + txcompliance_reg2_reg_2, + USER_OOBCLK, + RST_RXCDRLOCK, + gt_rx_phy_status_wire_filter, + \converge_cnt_reg[15]_0 , + \converge_cnt_reg[1]_0 , + \converge_cnt_reg[6]_0 , + RST_RESETDONE, + user_active_lane_2, + converge_gen3_reg_0, + reg_clock_locked, + out, + phy_rdy_n_int_reg, + phy_rdy_n_int_reg_0, + gt_rx_elec_idle_wire_filter, + pipe_rx2_valid_gt, + gt_rxvalid_2, + txphaligndone_reg1_reg, + txphaligndone_reg1_reg_0, + txphaligndone_reg1_reg_1, + txphaligndone_reg1_reg_2, + txphinitdone_reg1_reg, + txphinitdone_reg1_reg_0, + RST_CPLLRESET, + pipe_pclk_sel_out, + pipe_pclk_in, + pipe_oobclk_in, + USER_TXRESETDONE, + USER_RXRESETDONE, + PIPE_TXELECIDLE, + PIPE_TXCOMPLIANCE, + gt_rxcdrlock_2, + RST_RXUSRCLK_RESET, + pipe_rxusrclk_in, + rxstatus_reg1_reg_0, + RST_IDLE, + USER_RATE_IDLE, + USER_RATE_RXSYNC, + USER_RATE_DONE, + rate_gen3_2, + USER_RXEQ_ADAPT_DONE, + USER_RESETOVRD_START, + RST_PHYSTATUS); + output reg_clock_locked_reg; + output gt_rxvalid_q_reg; + output txcompliance_reg2_reg_0; + output txcompliance_reg2_reg_1; + output txelecidle_reg2_reg_0; + output txcompliance_reg2_reg_2; + output USER_OOBCLK; + output [0:0]RST_RXCDRLOCK; + output [0:0]gt_rx_phy_status_wire_filter; + output \converge_cnt_reg[15]_0 ; + output \converge_cnt_reg[1]_0 ; + output \converge_cnt_reg[6]_0 ; + output [0:0]RST_RESETDONE; + output user_active_lane_2; + output converge_gen3_reg_0; + input reg_clock_locked; + input out; + input phy_rdy_n_int_reg; + input phy_rdy_n_int_reg_0; + input [0:0]gt_rx_elec_idle_wire_filter; + input pipe_rx2_valid_gt; + input gt_rxvalid_2; + input txphaligndone_reg1_reg; + input txphaligndone_reg1_reg_0; + input txphaligndone_reg1_reg_1; + input txphaligndone_reg1_reg_2; + input txphinitdone_reg1_reg; + input txphinitdone_reg1_reg_0; + input RST_CPLLRESET; + input [0:0]pipe_pclk_sel_out; + input pipe_pclk_in; + input pipe_oobclk_in; + input USER_TXRESETDONE; + input USER_RXRESETDONE; + input [0:0]PIPE_TXELECIDLE; + input [0:0]PIPE_TXCOMPLIANCE; + input gt_rxcdrlock_2; + input RST_RXUSRCLK_RESET; + input pipe_rxusrclk_in; + input [0:0]rxstatus_reg1_reg_0; + input RST_IDLE; + input USER_RATE_IDLE; + input USER_RATE_RXSYNC; + input USER_RATE_DONE; + input rate_gen3_2; + input USER_RXEQ_ADAPT_DONE; + input USER_RESETOVRD_START; + input [0:0]RST_PHYSTATUS; + + wire [0:0]PIPE_TXCOMPLIANCE; + wire [0:0]PIPE_TXELECIDLE; + wire RST_CPLLRESET; + wire RST_IDLE; + wire [0:0]RST_PHYSTATUS; + wire [0:0]RST_RESETDONE; + wire [0:0]RST_RXCDRLOCK; + wire RST_RXUSRCLK_RESET; + wire USER_OOBCLK; + wire USER_RATE_DONE; + wire USER_RATE_IDLE; + wire USER_RATE_RXSYNC; + wire USER_RESETOVRD_START; + wire USER_RXEQ_ADAPT_DONE; + wire USER_RXRESETDONE; + wire USER_TXRESETDONE; + wire \converge_cnt[0]_i_1__4_n_0 ; + wire \converge_cnt[0]_i_4__1_n_0 ; + wire \converge_cnt[0]_i_5__1_n_0 ; + wire \converge_cnt[0]_i_6__1_n_0 ; + wire \converge_cnt[0]_i_7_n_0 ; + wire [21:0]converge_cnt_reg; + wire \converge_cnt_reg[0]_i_3__1_n_0 ; + wire \converge_cnt_reg[0]_i_3__1_n_1 ; + wire \converge_cnt_reg[0]_i_3__1_n_2 ; + wire \converge_cnt_reg[0]_i_3__1_n_3 ; + wire \converge_cnt_reg[0]_i_3__1_n_4 ; + wire \converge_cnt_reg[0]_i_3__1_n_5 ; + wire \converge_cnt_reg[0]_i_3__1_n_6 ; + wire \converge_cnt_reg[0]_i_3__1_n_7 ; + wire \converge_cnt_reg[12]_i_1__1_n_0 ; + wire \converge_cnt_reg[12]_i_1__1_n_1 ; + wire \converge_cnt_reg[12]_i_1__1_n_2 ; + wire \converge_cnt_reg[12]_i_1__1_n_3 ; + wire \converge_cnt_reg[12]_i_1__1_n_4 ; + wire \converge_cnt_reg[12]_i_1__1_n_5 ; + wire \converge_cnt_reg[12]_i_1__1_n_6 ; + wire \converge_cnt_reg[12]_i_1__1_n_7 ; + wire \converge_cnt_reg[15]_0 ; + wire \converge_cnt_reg[16]_i_1__1_n_0 ; + wire \converge_cnt_reg[16]_i_1__1_n_1 ; + wire \converge_cnt_reg[16]_i_1__1_n_2 ; + wire \converge_cnt_reg[16]_i_1__1_n_3 ; + wire \converge_cnt_reg[16]_i_1__1_n_4 ; + wire \converge_cnt_reg[16]_i_1__1_n_5 ; + wire \converge_cnt_reg[16]_i_1__1_n_6 ; + wire \converge_cnt_reg[16]_i_1__1_n_7 ; + wire \converge_cnt_reg[1]_0 ; + wire \converge_cnt_reg[20]_i_1__1_n_3 ; + wire \converge_cnt_reg[20]_i_1__1_n_6 ; + wire \converge_cnt_reg[20]_i_1__1_n_7 ; + wire \converge_cnt_reg[4]_i_1__1_n_0 ; + wire \converge_cnt_reg[4]_i_1__1_n_1 ; + wire \converge_cnt_reg[4]_i_1__1_n_2 ; + wire \converge_cnt_reg[4]_i_1__1_n_3 ; + wire \converge_cnt_reg[4]_i_1__1_n_4 ; + wire \converge_cnt_reg[4]_i_1__1_n_5 ; + wire \converge_cnt_reg[4]_i_1__1_n_6 ; + wire \converge_cnt_reg[4]_i_1__1_n_7 ; + wire \converge_cnt_reg[6]_0 ; + wire \converge_cnt_reg[8]_i_1__1_n_0 ; + wire \converge_cnt_reg[8]_i_1__1_n_1 ; + wire \converge_cnt_reg[8]_i_1__1_n_2 ; + wire \converge_cnt_reg[8]_i_1__1_n_3 ; + wire \converge_cnt_reg[8]_i_1__1_n_4 ; + wire \converge_cnt_reg[8]_i_1__1_n_5 ; + wire \converge_cnt_reg[8]_i_1__1_n_6 ; + wire \converge_cnt_reg[8]_i_1__1_n_7 ; + wire converge_gen3_i_1__1_n_0; + wire converge_gen3_reg_0; + wire [0:0]gt_rx_elec_idle_wire_filter; + wire [0:0]gt_rx_phy_status_wire_filter; + wire gt_rxcdrlock_2; + wire gt_rxvalid_2; + wire gt_rxvalid_q_i_4__1_n_0; + wire gt_rxvalid_q_reg; + wire \gtx_channel.gtxe2_channel_i_i_64_n_0 ; + wire [1:0]oobclk_cnt; + wire \oobclk_div.oobclk_i_1__1_n_0 ; + wire out; + wire [3:0]p_0_in__0; + wire [3:0]p_0_in__0__0; + wire [1:0]p_1_in__0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire pclk_sel_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire pclk_sel_reg2; + wire phy_rdy_n_int_reg; + wire phy_rdy_n_int_reg_0; + wire pipe_oobclk_in; + wire pipe_pclk_in; + wire [0:0]pipe_pclk_sel_out; + wire pipe_rx2_valid_gt; + wire pipe_rxusrclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_done_reg2; + wire rate_gen3_2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_gen3_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_gen3_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_rxsync_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_rxsync_reg2; + wire reg_clock_locked; + wire reg_clock_locked_reg; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg2; + wire [3:0]rxcdrlock_cnt_reg; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_adapt_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_adapt_done_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxstatus_reg1; + wire [0:0]rxstatus_reg1_reg_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxstatus_reg2; + wire [3:0]rxvalid_cnt_reg; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxvalid_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxvalid_reg2; + wire sel; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txcompliance_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txcompliance_reg2; + wire txcompliance_reg2_reg_0; + wire txcompliance_reg2_reg_2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txelecidle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txelecidle_reg2; + wire txphaligndone_reg1_reg; + wire txphaligndone_reg1_reg_0; + wire txphaligndone_reg1_reg_1; + wire txphaligndone_reg1_reg_2; + wire txphinitdone_reg1_reg; + wire txphinitdone_reg1_reg_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg2; + wire user_active_lane_2; + wire [3:1]\NLW_converge_cnt_reg[20]_i_1__1_CO_UNCONNECTED ; + wire [3:2]\NLW_converge_cnt_reg[20]_i_1__1_O_UNCONNECTED ; + + assign txcompliance_reg2_reg_1 = txcompliance_reg2; + assign txelecidle_reg2_reg_0 = txelecidle_reg2; + LUT2 #( + .INIT(4'h7)) + \FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__0 + (.I0(txcompliance_reg2), + .I1(txelecidle_reg2), + .O(user_active_lane_2)); + LUT4 #( + .INIT(16'hEFFF)) + \converge_cnt[0]_i_1__4 + (.I0(rate_gen3_reg2), + .I1(RST_CPLLRESET), + .I2(rst_idle_reg2), + .I3(rate_idle_reg2), + .O(\converge_cnt[0]_i_1__4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF5555555D)) + \converge_cnt[0]_i_2__1 + (.I0(converge_cnt_reg[21]), + .I1(\converge_cnt[0]_i_4__1_n_0 ), + .I2(converge_cnt_reg[12]), + .I3(converge_cnt_reg[14]), + .I4(converge_cnt_reg[20]), + .I5(\converge_cnt[0]_i_5__1_n_0 ), + .O(sel)); + LUT5 #( + .INIT(32'h00000001)) + \converge_cnt[0]_i_4__1 + (.I0(converge_cnt_reg[3]), + .I1(converge_cnt_reg[4]), + .I2(converge_cnt_reg[5]), + .I3(converge_cnt_reg[7]), + .I4(converge_cnt_reg[6]), + .O(\converge_cnt[0]_i_4__1_n_0 )); + LUT6 #( + .INIT(64'h0A0B0A0F0A0B0A0B)) + \converge_cnt[0]_i_5__1 + (.I0(\converge_cnt_reg[15]_0 ), + .I1(converge_cnt_reg[13]), + .I2(converge_cnt_reg[20]), + .I3(converge_cnt_reg[14]), + .I4(converge_cnt_reg[12]), + .I5(\converge_cnt[0]_i_7_n_0 ), + .O(\converge_cnt[0]_i_5__1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \converge_cnt[0]_i_6__1 + (.I0(converge_cnt_reg[0]), + .O(\converge_cnt[0]_i_6__1_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \converge_cnt[0]_i_7 + (.I0(converge_cnt_reg[9]), + .I1(converge_cnt_reg[8]), + .I2(converge_cnt_reg[11]), + .I3(converge_cnt_reg[10]), + .O(\converge_cnt[0]_i_7_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3__1_n_7 ), + .Q(converge_cnt_reg[0]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[0]_i_3__1 + (.CI(1'b0), + .CO({\converge_cnt_reg[0]_i_3__1_n_0 ,\converge_cnt_reg[0]_i_3__1_n_1 ,\converge_cnt_reg[0]_i_3__1_n_2 ,\converge_cnt_reg[0]_i_3__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\converge_cnt_reg[0]_i_3__1_n_4 ,\converge_cnt_reg[0]_i_3__1_n_5 ,\converge_cnt_reg[0]_i_3__1_n_6 ,\converge_cnt_reg[0]_i_3__1_n_7 }), + .S({converge_cnt_reg[3:1],\converge_cnt[0]_i_6__1_n_0 })); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[10] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1__1_n_5 ), + .Q(converge_cnt_reg[10]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[11] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1__1_n_4 ), + .Q(converge_cnt_reg[11]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[12] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1__1_n_7 ), + .Q(converge_cnt_reg[12]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[12]_i_1__1 + (.CI(\converge_cnt_reg[8]_i_1__1_n_0 ), + .CO({\converge_cnt_reg[12]_i_1__1_n_0 ,\converge_cnt_reg[12]_i_1__1_n_1 ,\converge_cnt_reg[12]_i_1__1_n_2 ,\converge_cnt_reg[12]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[12]_i_1__1_n_4 ,\converge_cnt_reg[12]_i_1__1_n_5 ,\converge_cnt_reg[12]_i_1__1_n_6 ,\converge_cnt_reg[12]_i_1__1_n_7 }), + .S(converge_cnt_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[13] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1__1_n_6 ), + .Q(converge_cnt_reg[13]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[14] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1__1_n_5 ), + .Q(converge_cnt_reg[14]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[15] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1__1_n_4 ), + .Q(converge_cnt_reg[15]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[16] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1__1_n_7 ), + .Q(converge_cnt_reg[16]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[16]_i_1__1 + (.CI(\converge_cnt_reg[12]_i_1__1_n_0 ), + .CO({\converge_cnt_reg[16]_i_1__1_n_0 ,\converge_cnt_reg[16]_i_1__1_n_1 ,\converge_cnt_reg[16]_i_1__1_n_2 ,\converge_cnt_reg[16]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[16]_i_1__1_n_4 ,\converge_cnt_reg[16]_i_1__1_n_5 ,\converge_cnt_reg[16]_i_1__1_n_6 ,\converge_cnt_reg[16]_i_1__1_n_7 }), + .S(converge_cnt_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[17] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1__1_n_6 ), + .Q(converge_cnt_reg[17]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[18] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1__1_n_5 ), + .Q(converge_cnt_reg[18]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[19] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1__1_n_4 ), + .Q(converge_cnt_reg[19]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3__1_n_6 ), + .Q(converge_cnt_reg[1]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[20] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[20]_i_1__1_n_7 ), + .Q(converge_cnt_reg[20]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[20]_i_1__1 + (.CI(\converge_cnt_reg[16]_i_1__1_n_0 ), + .CO({\NLW_converge_cnt_reg[20]_i_1__1_CO_UNCONNECTED [3:1],\converge_cnt_reg[20]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_converge_cnt_reg[20]_i_1__1_O_UNCONNECTED [3:2],\converge_cnt_reg[20]_i_1__1_n_6 ,\converge_cnt_reg[20]_i_1__1_n_7 }), + .S({1'b0,1'b0,converge_cnt_reg[21:20]})); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[21] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[20]_i_1__1_n_6 ), + .Q(converge_cnt_reg[21]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3__1_n_5 ), + .Q(converge_cnt_reg[2]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3__1_n_4 ), + .Q(converge_cnt_reg[3]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[4] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1__1_n_7 ), + .Q(converge_cnt_reg[4]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[4]_i_1__1 + (.CI(\converge_cnt_reg[0]_i_3__1_n_0 ), + .CO({\converge_cnt_reg[4]_i_1__1_n_0 ,\converge_cnt_reg[4]_i_1__1_n_1 ,\converge_cnt_reg[4]_i_1__1_n_2 ,\converge_cnt_reg[4]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[4]_i_1__1_n_4 ,\converge_cnt_reg[4]_i_1__1_n_5 ,\converge_cnt_reg[4]_i_1__1_n_6 ,\converge_cnt_reg[4]_i_1__1_n_7 }), + .S(converge_cnt_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[5] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1__1_n_6 ), + .Q(converge_cnt_reg[5]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[6] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1__1_n_5 ), + .Q(converge_cnt_reg[6]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[7] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1__1_n_4 ), + .Q(converge_cnt_reg[7]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[8] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1__1_n_7 ), + .Q(converge_cnt_reg[8]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[8]_i_1__1 + (.CI(\converge_cnt_reg[4]_i_1__1_n_0 ), + .CO({\converge_cnt_reg[8]_i_1__1_n_0 ,\converge_cnt_reg[8]_i_1__1_n_1 ,\converge_cnt_reg[8]_i_1__1_n_2 ,\converge_cnt_reg[8]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[8]_i_1__1_n_4 ,\converge_cnt_reg[8]_i_1__1_n_5 ,\converge_cnt_reg[8]_i_1__1_n_6 ,\converge_cnt_reg[8]_i_1__1_n_7 }), + .S(converge_cnt_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[9] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1__1_n_6 ), + .Q(converge_cnt_reg[9]), + .R(\converge_cnt[0]_i_1__4_n_0 )); + LUT3 #( + .INIT(8'hC8)) + converge_gen3_i_1__1 + (.I0(rxeq_adapt_done_reg2), + .I1(rate_gen3_reg2), + .I2(converge_gen3_reg_0), + .O(converge_gen3_i_1__1_n_0)); + FDRE #( + .INIT(1'b0)) + converge_gen3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_gen3_i_1__1_n_0), + .Q(converge_gen3_reg_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hFFFFA8FF)) + gt_rx_phy_status_q_i_1__1 + (.I0(RST_PHYSTATUS), + .I1(rate_idle_reg2), + .I2(rate_rxsync_reg2), + .I3(rst_idle_reg2), + .I4(rate_done_reg2), + .O(gt_rx_phy_status_wire_filter)); + LUT6 #( + .INIT(64'hD000000000000000)) + gt_rxvalid_q_i_3__1 + (.I0(gt_rx_elec_idle_wire_filter), + .I1(pipe_rx2_valid_gt), + .I2(gt_rxvalid_q_i_4__1_n_0), + .I3(gt_rxvalid_2), + .I4(rst_idle_reg2), + .I5(rate_idle_reg2), + .O(gt_rxvalid_q_reg)); + LUT4 #( + .INIT(16'h8000)) + gt_rxvalid_q_i_4__1 + (.I0(rxvalid_cnt_reg[0]), + .I1(rxvalid_cnt_reg[1]), + .I2(rxvalid_cnt_reg[2]), + .I3(rxvalid_cnt_reg[3]), + .O(gt_rxvalid_q_i_4__1_n_0)); + LUT5 #( + .INIT(32'h7FFFFFFF)) + \gtx_channel.gtxe2_channel_i_i_60 + (.I0(converge_cnt_reg[15]), + .I1(converge_cnt_reg[18]), + .I2(converge_cnt_reg[19]), + .I3(converge_cnt_reg[17]), + .I4(converge_cnt_reg[16]), + .O(\converge_cnt_reg[15]_0 )); + LUT6 #( + .INIT(64'h0001000000000000)) + \gtx_channel.gtxe2_channel_i_i_61 + (.I0(converge_cnt_reg[6]), + .I1(converge_cnt_reg[7]), + .I2(converge_cnt_reg[4]), + .I3(converge_cnt_reg[5]), + .I4(converge_cnt_reg[21]), + .I5(converge_cnt_reg[13]), + .O(\converge_cnt_reg[6]_0 )); + LUT6 #( + .INIT(64'h0000000000020000)) + \gtx_channel.gtxe2_channel_i_i_62 + (.I0(\gtx_channel.gtxe2_channel_i_i_64_n_0 ), + .I1(converge_cnt_reg[1]), + .I2(converge_cnt_reg[0]), + .I3(converge_cnt_reg[2]), + .I4(converge_cnt_reg[3]), + .I5(\converge_cnt[0]_i_7_n_0 ), + .O(\converge_cnt_reg[1]_0 )); + LUT3 #( + .INIT(8'h01)) + \gtx_channel.gtxe2_channel_i_i_64 + (.I0(converge_cnt_reg[20]), + .I1(converge_cnt_reg[14]), + .I2(converge_cnt_reg[12]), + .O(\gtx_channel.gtxe2_channel_i_i_64_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair162" *) + LUT1 #( + .INIT(2'h1)) + \oobclk_div.oobclk_cnt[0]_i_1__1 + (.I0(oobclk_cnt[0]), + .O(p_1_in__0[0])); + (* SOFT_HLUTNM = "soft_lutpair162" *) + LUT2 #( + .INIT(4'h6)) + \oobclk_div.oobclk_cnt[1]_i_1__1 + (.I0(oobclk_cnt[0]), + .I1(oobclk_cnt[1]), + .O(p_1_in__0[1])); + FDRE #( + .INIT(1'b0)) + \oobclk_div.oobclk_cnt_reg[0] + (.C(pipe_oobclk_in), + .CE(1'b1), + .D(p_1_in__0[0]), + .Q(oobclk_cnt[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \oobclk_div.oobclk_cnt_reg[1] + (.C(pipe_oobclk_in), + .CE(1'b1), + .D(p_1_in__0[1]), + .Q(oobclk_cnt[1]), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'hB8)) + \oobclk_div.oobclk_i_1__1 + (.I0(oobclk_cnt[1]), + .I1(pclk_sel_reg2), + .I2(oobclk_cnt[0]), + .O(\oobclk_div.oobclk_i_1__1_n_0 )); + FDRE #( + .INIT(1'b0)) + \oobclk_div.oobclk_reg + (.C(pipe_oobclk_in), + .CE(1'b1), + .D(\oobclk_div.oobclk_i_1__1_n_0 ), + .Q(USER_OOBCLK), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE pclk_sel_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_pclk_sel_out), + .Q(pclk_sel_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE pclk_sel_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pclk_sel_reg1), + .Q(pclk_sel_reg2), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h00000002)) + phy_rdy_n_int_i_1 + (.I0(reg_clock_locked), + .I1(rst_idle_reg2), + .I2(out), + .I3(phy_rdy_n_int_reg), + .I4(phy_rdy_n_int_reg_0), + .O(reg_clock_locked_reg)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_done_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_DONE), + .Q(rate_done_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_done_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_done_reg1), + .Q(rate_done_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_gen3_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_gen3_2), + .Q(rate_gen3_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_gen3_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_gen3_reg1), + .Q(rate_gen3_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_IDLE), + .Q(rate_idle_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_idle_reg1), + .Q(rate_idle_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_rxsync_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_RXSYNC), + .Q(rate_rxsync_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_rxsync_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_rxsync_reg1), + .Q(rate_rxsync_reg2), + .R(RST_RXUSRCLK_RESET)); + LUT2 #( + .INIT(4'h8)) + \resetdone_reg1[2]_i_1 + (.I0(rxresetdone_reg2), + .I1(txresetdone_reg2), + .O(RST_RESETDONE)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_start_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RESETOVRD_START), + .Q(resetovrd_start_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_start_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(resetovrd_start_reg1), + .Q(resetovrd_start_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(RST_IDLE), + .Q(rst_idle_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rst_idle_reg1), + .Q(rst_idle_reg2), + .R(RST_RXUSRCLK_RESET)); + LUT5 #( + .INIT(32'hD0505050)) + \rxcdrlock_cnt[0]_i_1__1 + (.I0(rxcdrlock_cnt_reg[0]), + .I1(rxcdrlock_cnt_reg[2]), + .I2(rxcdrlock_reg2), + .I3(rxcdrlock_cnt_reg[1]), + .I4(rxcdrlock_cnt_reg[3]), + .O(p_0_in__0[0])); + LUT5 #( + .INIT(32'h8FF00000)) + \rxcdrlock_cnt[1]_i_1__1 + (.I0(rxcdrlock_cnt_reg[3]), + .I1(rxcdrlock_cnt_reg[2]), + .I2(rxcdrlock_cnt_reg[0]), + .I3(rxcdrlock_cnt_reg[1]), + .I4(rxcdrlock_reg2), + .O(p_0_in__0[1])); + LUT5 #( + .INIT(32'hF8780000)) + \rxcdrlock_cnt[2]_i_1__1 + (.I0(rxcdrlock_cnt_reg[0]), + .I1(rxcdrlock_cnt_reg[1]), + .I2(rxcdrlock_cnt_reg[2]), + .I3(rxcdrlock_cnt_reg[3]), + .I4(rxcdrlock_reg2), + .O(p_0_in__0[2])); + LUT5 #( + .INIT(32'hFF008000)) + \rxcdrlock_cnt[3]_i_1__1 + (.I0(rxcdrlock_cnt_reg[0]), + .I1(rxcdrlock_cnt_reg[1]), + .I2(rxcdrlock_cnt_reg[2]), + .I3(rxcdrlock_reg2), + .I4(rxcdrlock_cnt_reg[3]), + .O(p_0_in__0[3])); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[0]), + .Q(rxcdrlock_cnt_reg[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[1]), + .Q(rxcdrlock_cnt_reg[1]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[2]), + .Q(rxcdrlock_cnt_reg[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[3]), + .Q(rxcdrlock_cnt_reg[3]), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h80000000)) + \rxcdrlock_reg1[2]_i_1 + (.I0(rxcdrlock_cnt_reg[2]), + .I1(rxcdrlock_cnt_reg[3]), + .I2(gt_rxcdrlock_2), + .I3(rxcdrlock_cnt_reg[1]), + .I4(rxcdrlock_cnt_reg[0]), + .O(RST_RXCDRLOCK)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rxcdrlock_2), + .Q(rxcdrlock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxcdrlock_reg1), + .Q(rxcdrlock_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_adapt_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RXEQ_ADAPT_DONE), + .Q(rxeq_adapt_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_adapt_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_adapt_done_reg1), + .Q(rxeq_adapt_done_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RXRESETDONE), + .Q(rxresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxresetdone_reg1), + .Q(rxresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxstatus_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rxstatus_reg1_reg_0), + .Q(rxstatus_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxstatus_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rxstatus_reg1), + .Q(rxstatus_reg2), + .R(RST_RXUSRCLK_RESET)); + LUT6 #( + .INIT(64'hC404040404040404)) + \rxvalid_cnt[0]_i_1__1 + (.I0(rxstatus_reg2), + .I1(rxvalid_reg2), + .I2(rxvalid_cnt_reg[0]), + .I3(rxvalid_cnt_reg[1]), + .I4(rxvalid_cnt_reg[2]), + .I5(rxvalid_cnt_reg[3]), + .O(p_0_in__0__0[0])); + LUT6 #( + .INIT(64'h808000F000F00000)) + \rxvalid_cnt[1]_i_1__1 + (.I0(rxvalid_cnt_reg[3]), + .I1(rxvalid_cnt_reg[2]), + .I2(rxvalid_reg2), + .I3(rxstatus_reg2), + .I4(rxvalid_cnt_reg[1]), + .I5(rxvalid_cnt_reg[0]), + .O(p_0_in__0__0[1])); + LUT6 #( + .INIT(64'h80BF000000C00000)) + \rxvalid_cnt[2]_i_1__1 + (.I0(rxvalid_cnt_reg[3]), + .I1(rxvalid_cnt_reg[0]), + .I2(rxvalid_cnt_reg[1]), + .I3(rxstatus_reg2), + .I4(rxvalid_reg2), + .I5(rxvalid_cnt_reg[2]), + .O(p_0_in__0__0[2])); + LUT6 #( + .INIT(64'h8C08080808080808)) + \rxvalid_cnt[3]_i_1__1 + (.I0(rxvalid_cnt_reg[3]), + .I1(rxvalid_reg2), + .I2(rxstatus_reg2), + .I3(rxvalid_cnt_reg[2]), + .I4(rxvalid_cnt_reg[1]), + .I5(rxvalid_cnt_reg[0]), + .O(p_0_in__0__0[3])); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[0] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[0]), + .Q(rxvalid_cnt_reg[0]), + .R(RST_RXUSRCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[1] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[1]), + .Q(rxvalid_cnt_reg[1]), + .R(RST_RXUSRCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[2] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[2]), + .Q(rxvalid_cnt_reg[2]), + .R(RST_RXUSRCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[3] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[3]), + .Q(rxvalid_cnt_reg[3]), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxvalid_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(gt_rxvalid_2), + .Q(rxvalid_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxvalid_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rxvalid_reg1), + .Q(rxvalid_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txcompliance_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_TXCOMPLIANCE), + .Q(txcompliance_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txcompliance_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcompliance_reg1), + .Q(txcompliance_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txelecidle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_TXELECIDLE), + .Q(txelecidle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txelecidle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txelecidle_reg1), + .Q(txelecidle_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'h0707070707FFFFFF)) + txphaligndone_reg1_i_3 + (.I0(txcompliance_reg2), + .I1(txelecidle_reg2), + .I2(txphaligndone_reg1_reg), + .I3(txphaligndone_reg1_reg_0), + .I4(txphaligndone_reg1_reg_1), + .I5(txphaligndone_reg1_reg_2), + .O(txcompliance_reg2_reg_0)); + LUT6 #( + .INIT(64'h0707070707FFFFFF)) + txphinitdone_reg1_i_2 + (.I0(txcompliance_reg2), + .I1(txelecidle_reg2), + .I2(txphinitdone_reg1_reg), + .I3(txphaligndone_reg1_reg_0), + .I4(txphaligndone_reg1_reg_1), + .I5(txphinitdone_reg1_reg_0), + .O(txcompliance_reg2_reg_2)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_TXRESETDONE), + .Q(txresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txresetdone_reg1), + .Q(txresetdone_reg2), + .R(RST_CPLLRESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_pipe_user" *) +module pcie_7x_0_pcie_7x_0_pipe_user_54 + (gt_rxvalid_q_reg, + out, + txelecidle_reg2_reg_0, + txcompliance_reg2_reg_0, + USER_OOBCLK, + RST_RXCDRLOCK, + gt_rx_phy_status_wire_filter, + user_rx_converge, + RST_RESETDONE, + user_active_lane_3, + gt_rx_elec_idle_wire_filter, + pipe_rx3_valid_gt, + gt_rxvalid_3, + RST_CPLLRESET, + pipe_pclk_sel_out, + pipe_pclk_in, + pipe_oobclk_in, + USER_TXRESETDONE, + USER_RXRESETDONE, + PIPE_TXELECIDLE, + PIPE_TXCOMPLIANCE, + gt_rxcdrlock_3, + RST_RXUSRCLK_RESET, + pipe_rxusrclk_in, + rxstatus_reg1_reg_0, + RST_IDLE, + USER_RATE_IDLE, + USER_RATE_RXSYNC, + USER_RATE_DONE, + rate_gen3_3, + USER_RXEQ_ADAPT_DONE, + USER_RESETOVRD_START, + RST_PHYSTATUS); + output gt_rxvalid_q_reg; + output out; + output txelecidle_reg2_reg_0; + output txcompliance_reg2_reg_0; + output USER_OOBCLK; + output [0:0]RST_RXCDRLOCK; + output [0:0]gt_rx_phy_status_wire_filter; + output [0:0]user_rx_converge; + output [0:0]RST_RESETDONE; + output user_active_lane_3; + input [0:0]gt_rx_elec_idle_wire_filter; + input pipe_rx3_valid_gt; + input gt_rxvalid_3; + input RST_CPLLRESET; + input [0:0]pipe_pclk_sel_out; + input pipe_pclk_in; + input pipe_oobclk_in; + input USER_TXRESETDONE; + input USER_RXRESETDONE; + input [0:0]PIPE_TXELECIDLE; + input [0:0]PIPE_TXCOMPLIANCE; + input gt_rxcdrlock_3; + input RST_RXUSRCLK_RESET; + input pipe_rxusrclk_in; + input [0:0]rxstatus_reg1_reg_0; + input RST_IDLE; + input USER_RATE_IDLE; + input USER_RATE_RXSYNC; + input USER_RATE_DONE; + input rate_gen3_3; + input USER_RXEQ_ADAPT_DONE; + input USER_RESETOVRD_START; + input [0:0]RST_PHYSTATUS; + + wire [0:0]PIPE_TXCOMPLIANCE; + wire [0:0]PIPE_TXELECIDLE; + wire RST_CPLLRESET; + wire RST_IDLE; + wire [0:0]RST_PHYSTATUS; + wire [0:0]RST_RESETDONE; + wire [0:0]RST_RXCDRLOCK; + wire RST_RXUSRCLK_RESET; + wire USER_OOBCLK; + wire USER_RATE_DONE; + wire USER_RATE_IDLE; + wire USER_RATE_RXSYNC; + wire USER_RESETOVRD_START; + wire USER_RXEQ_ADAPT_DONE; + wire USER_RXRESETDONE; + wire USER_TXRESETDONE; + wire \converge_cnt[0]_i_1__6_n_0 ; + wire \converge_cnt[0]_i_4__2_n_0 ; + wire \converge_cnt[0]_i_5__2_n_0 ; + wire \converge_cnt[0]_i_6__2_n_0 ; + wire \converge_cnt[0]_i_7__0_n_0 ; + wire \converge_cnt[0]_i_8_n_0 ; + wire [21:0]converge_cnt_reg; + wire \converge_cnt_reg[0]_i_3__2_n_0 ; + wire \converge_cnt_reg[0]_i_3__2_n_1 ; + wire \converge_cnt_reg[0]_i_3__2_n_2 ; + wire \converge_cnt_reg[0]_i_3__2_n_3 ; + wire \converge_cnt_reg[0]_i_3__2_n_4 ; + wire \converge_cnt_reg[0]_i_3__2_n_5 ; + wire \converge_cnt_reg[0]_i_3__2_n_6 ; + wire \converge_cnt_reg[0]_i_3__2_n_7 ; + wire \converge_cnt_reg[12]_i_1__2_n_0 ; + wire \converge_cnt_reg[12]_i_1__2_n_1 ; + wire \converge_cnt_reg[12]_i_1__2_n_2 ; + wire \converge_cnt_reg[12]_i_1__2_n_3 ; + wire \converge_cnt_reg[12]_i_1__2_n_4 ; + wire \converge_cnt_reg[12]_i_1__2_n_5 ; + wire \converge_cnt_reg[12]_i_1__2_n_6 ; + wire \converge_cnt_reg[12]_i_1__2_n_7 ; + wire \converge_cnt_reg[16]_i_1__2_n_0 ; + wire \converge_cnt_reg[16]_i_1__2_n_1 ; + wire \converge_cnt_reg[16]_i_1__2_n_2 ; + wire \converge_cnt_reg[16]_i_1__2_n_3 ; + wire \converge_cnt_reg[16]_i_1__2_n_4 ; + wire \converge_cnt_reg[16]_i_1__2_n_5 ; + wire \converge_cnt_reg[16]_i_1__2_n_6 ; + wire \converge_cnt_reg[16]_i_1__2_n_7 ; + wire \converge_cnt_reg[20]_i_1__2_n_3 ; + wire \converge_cnt_reg[20]_i_1__2_n_6 ; + wire \converge_cnt_reg[20]_i_1__2_n_7 ; + wire \converge_cnt_reg[4]_i_1__2_n_0 ; + wire \converge_cnt_reg[4]_i_1__2_n_1 ; + wire \converge_cnt_reg[4]_i_1__2_n_2 ; + wire \converge_cnt_reg[4]_i_1__2_n_3 ; + wire \converge_cnt_reg[4]_i_1__2_n_4 ; + wire \converge_cnt_reg[4]_i_1__2_n_5 ; + wire \converge_cnt_reg[4]_i_1__2_n_6 ; + wire \converge_cnt_reg[4]_i_1__2_n_7 ; + wire \converge_cnt_reg[8]_i_1__2_n_0 ; + wire \converge_cnt_reg[8]_i_1__2_n_1 ; + wire \converge_cnt_reg[8]_i_1__2_n_2 ; + wire \converge_cnt_reg[8]_i_1__2_n_3 ; + wire \converge_cnt_reg[8]_i_1__2_n_4 ; + wire \converge_cnt_reg[8]_i_1__2_n_5 ; + wire \converge_cnt_reg[8]_i_1__2_n_6 ; + wire \converge_cnt_reg[8]_i_1__2_n_7 ; + wire converge_gen3_i_1__2_n_0; + wire converge_gen3_reg_n_0; + wire [0:0]gt_rx_elec_idle_wire_filter; + wire [0:0]gt_rx_phy_status_wire_filter; + wire gt_rxcdrlock_3; + wire gt_rxvalid_3; + wire gt_rxvalid_q_i_4__2_n_0; + wire gt_rxvalid_q_reg; + wire \gtx_channel.gtxe2_channel_i_i_65_n_0 ; + wire \gtx_channel.gtxe2_channel_i_i_66_n_0 ; + wire \gtx_channel.gtxe2_channel_i_i_67_n_0 ; + wire [1:0]oobclk_cnt; + wire \oobclk_div.oobclk_i_1__2_n_0 ; + wire [3:0]p_0_in__0; + wire [3:0]p_0_in__0__0; + wire [1:0]p_1_in__0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire pclk_sel_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire pclk_sel_reg2; + wire pipe_oobclk_in; + wire pipe_pclk_in; + wire [0:0]pipe_pclk_sel_out; + wire pipe_rx3_valid_gt; + wire pipe_rxusrclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_done_reg2; + wire rate_gen3_3; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_gen3_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_gen3_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_rxsync_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_rxsync_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_start_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg2; + wire [3:0]rxcdrlock_cnt_reg; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_adapt_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_adapt_done_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxstatus_reg1; + wire [0:0]rxstatus_reg1_reg_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxstatus_reg2; + wire [3:0]rxvalid_cnt_reg; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxvalid_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxvalid_reg2; + wire sel; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txcompliance_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txcompliance_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txelecidle_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txelecidle_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg2; + wire user_active_lane_3; + wire [0:0]user_rx_converge; + wire [3:1]\NLW_converge_cnt_reg[20]_i_1__2_CO_UNCONNECTED ; + wire [3:2]\NLW_converge_cnt_reg[20]_i_1__2_O_UNCONNECTED ; + + assign out = rst_idle_reg2; + assign txcompliance_reg2_reg_0 = txcompliance_reg2; + assign txelecidle_reg2_reg_0 = txelecidle_reg2; + LUT2 #( + .INIT(4'h7)) + \FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__1 + (.I0(txcompliance_reg2), + .I1(txelecidle_reg2), + .O(user_active_lane_3)); + LUT4 #( + .INIT(16'hEFFF)) + \converge_cnt[0]_i_1__6 + (.I0(rate_gen3_reg2), + .I1(RST_CPLLRESET), + .I2(rst_idle_reg2), + .I3(rate_idle_reg2), + .O(\converge_cnt[0]_i_1__6_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF5555555D)) + \converge_cnt[0]_i_2__2 + (.I0(converge_cnt_reg[21]), + .I1(\converge_cnt[0]_i_4__2_n_0 ), + .I2(converge_cnt_reg[12]), + .I3(converge_cnt_reg[14]), + .I4(converge_cnt_reg[20]), + .I5(\converge_cnt[0]_i_5__2_n_0 ), + .O(sel)); + LUT5 #( + .INIT(32'h00000001)) + \converge_cnt[0]_i_4__2 + (.I0(converge_cnt_reg[3]), + .I1(converge_cnt_reg[4]), + .I2(converge_cnt_reg[5]), + .I3(converge_cnt_reg[7]), + .I4(converge_cnt_reg[6]), + .O(\converge_cnt[0]_i_4__2_n_0 )); + LUT6 #( + .INIT(64'h0A0B0A0F0A0B0A0B)) + \converge_cnt[0]_i_5__2 + (.I0(\converge_cnt[0]_i_7__0_n_0 ), + .I1(converge_cnt_reg[13]), + .I2(converge_cnt_reg[20]), + .I3(converge_cnt_reg[14]), + .I4(converge_cnt_reg[12]), + .I5(\converge_cnt[0]_i_8_n_0 ), + .O(\converge_cnt[0]_i_5__2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \converge_cnt[0]_i_6__2 + (.I0(converge_cnt_reg[0]), + .O(\converge_cnt[0]_i_6__2_n_0 )); + LUT5 #( + .INIT(32'h7FFFFFFF)) + \converge_cnt[0]_i_7__0 + (.I0(converge_cnt_reg[15]), + .I1(converge_cnt_reg[18]), + .I2(converge_cnt_reg[19]), + .I3(converge_cnt_reg[17]), + .I4(converge_cnt_reg[16]), + .O(\converge_cnt[0]_i_7__0_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \converge_cnt[0]_i_8 + (.I0(converge_cnt_reg[9]), + .I1(converge_cnt_reg[8]), + .I2(converge_cnt_reg[11]), + .I3(converge_cnt_reg[10]), + .O(\converge_cnt[0]_i_8_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3__2_n_7 ), + .Q(converge_cnt_reg[0]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[0]_i_3__2 + (.CI(1'b0), + .CO({\converge_cnt_reg[0]_i_3__2_n_0 ,\converge_cnt_reg[0]_i_3__2_n_1 ,\converge_cnt_reg[0]_i_3__2_n_2 ,\converge_cnt_reg[0]_i_3__2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\converge_cnt_reg[0]_i_3__2_n_4 ,\converge_cnt_reg[0]_i_3__2_n_5 ,\converge_cnt_reg[0]_i_3__2_n_6 ,\converge_cnt_reg[0]_i_3__2_n_7 }), + .S({converge_cnt_reg[3:1],\converge_cnt[0]_i_6__2_n_0 })); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[10] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1__2_n_5 ), + .Q(converge_cnt_reg[10]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[11] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1__2_n_4 ), + .Q(converge_cnt_reg[11]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[12] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1__2_n_7 ), + .Q(converge_cnt_reg[12]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[12]_i_1__2 + (.CI(\converge_cnt_reg[8]_i_1__2_n_0 ), + .CO({\converge_cnt_reg[12]_i_1__2_n_0 ,\converge_cnt_reg[12]_i_1__2_n_1 ,\converge_cnt_reg[12]_i_1__2_n_2 ,\converge_cnt_reg[12]_i_1__2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[12]_i_1__2_n_4 ,\converge_cnt_reg[12]_i_1__2_n_5 ,\converge_cnt_reg[12]_i_1__2_n_6 ,\converge_cnt_reg[12]_i_1__2_n_7 }), + .S(converge_cnt_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[13] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1__2_n_6 ), + .Q(converge_cnt_reg[13]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[14] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1__2_n_5 ), + .Q(converge_cnt_reg[14]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[15] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[12]_i_1__2_n_4 ), + .Q(converge_cnt_reg[15]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[16] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1__2_n_7 ), + .Q(converge_cnt_reg[16]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[16]_i_1__2 + (.CI(\converge_cnt_reg[12]_i_1__2_n_0 ), + .CO({\converge_cnt_reg[16]_i_1__2_n_0 ,\converge_cnt_reg[16]_i_1__2_n_1 ,\converge_cnt_reg[16]_i_1__2_n_2 ,\converge_cnt_reg[16]_i_1__2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[16]_i_1__2_n_4 ,\converge_cnt_reg[16]_i_1__2_n_5 ,\converge_cnt_reg[16]_i_1__2_n_6 ,\converge_cnt_reg[16]_i_1__2_n_7 }), + .S(converge_cnt_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[17] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1__2_n_6 ), + .Q(converge_cnt_reg[17]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[18] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1__2_n_5 ), + .Q(converge_cnt_reg[18]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[19] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[16]_i_1__2_n_4 ), + .Q(converge_cnt_reg[19]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3__2_n_6 ), + .Q(converge_cnt_reg[1]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[20] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[20]_i_1__2_n_7 ), + .Q(converge_cnt_reg[20]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[20]_i_1__2 + (.CI(\converge_cnt_reg[16]_i_1__2_n_0 ), + .CO({\NLW_converge_cnt_reg[20]_i_1__2_CO_UNCONNECTED [3:1],\converge_cnt_reg[20]_i_1__2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_converge_cnt_reg[20]_i_1__2_O_UNCONNECTED [3:2],\converge_cnt_reg[20]_i_1__2_n_6 ,\converge_cnt_reg[20]_i_1__2_n_7 }), + .S({1'b0,1'b0,converge_cnt_reg[21:20]})); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[21] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[20]_i_1__2_n_6 ), + .Q(converge_cnt_reg[21]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3__2_n_5 ), + .Q(converge_cnt_reg[2]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[0]_i_3__2_n_4 ), + .Q(converge_cnt_reg[3]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[4] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1__2_n_7 ), + .Q(converge_cnt_reg[4]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[4]_i_1__2 + (.CI(\converge_cnt_reg[0]_i_3__2_n_0 ), + .CO({\converge_cnt_reg[4]_i_1__2_n_0 ,\converge_cnt_reg[4]_i_1__2_n_1 ,\converge_cnt_reg[4]_i_1__2_n_2 ,\converge_cnt_reg[4]_i_1__2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[4]_i_1__2_n_4 ,\converge_cnt_reg[4]_i_1__2_n_5 ,\converge_cnt_reg[4]_i_1__2_n_6 ,\converge_cnt_reg[4]_i_1__2_n_7 }), + .S(converge_cnt_reg[7:4])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[5] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1__2_n_6 ), + .Q(converge_cnt_reg[5]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[6] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1__2_n_5 ), + .Q(converge_cnt_reg[6]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[7] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[4]_i_1__2_n_4 ), + .Q(converge_cnt_reg[7]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[8] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1__2_n_7 ), + .Q(converge_cnt_reg[8]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + (* ADDER_THRESHOLD = "11" *) + CARRY4 \converge_cnt_reg[8]_i_1__2 + (.CI(\converge_cnt_reg[4]_i_1__2_n_0 ), + .CO({\converge_cnt_reg[8]_i_1__2_n_0 ,\converge_cnt_reg[8]_i_1__2_n_1 ,\converge_cnt_reg[8]_i_1__2_n_2 ,\converge_cnt_reg[8]_i_1__2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\converge_cnt_reg[8]_i_1__2_n_4 ,\converge_cnt_reg[8]_i_1__2_n_5 ,\converge_cnt_reg[8]_i_1__2_n_6 ,\converge_cnt_reg[8]_i_1__2_n_7 }), + .S(converge_cnt_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[9] + (.C(pipe_pclk_in), + .CE(sel), + .D(\converge_cnt_reg[8]_i_1__2_n_6 ), + .Q(converge_cnt_reg[9]), + .R(\converge_cnt[0]_i_1__6_n_0 )); + LUT3 #( + .INIT(8'hC8)) + converge_gen3_i_1__2 + (.I0(rxeq_adapt_done_reg2), + .I1(rate_gen3_reg2), + .I2(converge_gen3_reg_n_0), + .O(converge_gen3_i_1__2_n_0)); + FDRE #( + .INIT(1'b0)) + converge_gen3_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_gen3_i_1__2_n_0), + .Q(converge_gen3_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hFFFFA8FF)) + gt_rx_phy_status_q_i_1__2 + (.I0(RST_PHYSTATUS), + .I1(rate_idle_reg2), + .I2(rate_rxsync_reg2), + .I3(rst_idle_reg2), + .I4(rate_done_reg2), + .O(gt_rx_phy_status_wire_filter)); + LUT6 #( + .INIT(64'hD000000000000000)) + gt_rxvalid_q_i_3__2 + (.I0(gt_rx_elec_idle_wire_filter), + .I1(pipe_rx3_valid_gt), + .I2(gt_rxvalid_q_i_4__2_n_0), + .I3(gt_rxvalid_3), + .I4(rst_idle_reg2), + .I5(rate_idle_reg2), + .O(gt_rxvalid_q_reg)); + LUT4 #( + .INIT(16'h8000)) + gt_rxvalid_q_i_4__2 + (.I0(rxvalid_cnt_reg[0]), + .I1(rxvalid_cnt_reg[1]), + .I2(rxvalid_cnt_reg[2]), + .I3(rxvalid_cnt_reg[3]), + .O(gt_rxvalid_q_i_4__2_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFF00000800)) + \gtx_channel.gtxe2_channel_i_i_63 + (.I0(\gtx_channel.gtxe2_channel_i_i_65_n_0 ), + .I1(\gtx_channel.gtxe2_channel_i_i_66_n_0 ), + .I2(\converge_cnt[0]_i_8_n_0 ), + .I3(\gtx_channel.gtxe2_channel_i_i_67_n_0 ), + .I4(\converge_cnt[0]_i_7__0_n_0 ), + .I5(converge_gen3_reg_n_0), + .O(user_rx_converge)); + LUT3 #( + .INIT(8'h01)) + \gtx_channel.gtxe2_channel_i_i_65 + (.I0(converge_cnt_reg[20]), + .I1(converge_cnt_reg[14]), + .I2(converge_cnt_reg[12]), + .O(\gtx_channel.gtxe2_channel_i_i_65_n_0 )); + LUT4 #( + .INIT(16'h0100)) + \gtx_channel.gtxe2_channel_i_i_66 + (.I0(converge_cnt_reg[1]), + .I1(converge_cnt_reg[0]), + .I2(converge_cnt_reg[2]), + .I3(converge_cnt_reg[3]), + .O(\gtx_channel.gtxe2_channel_i_i_66_n_0 )); + LUT6 #( + .INIT(64'h0001000000000000)) + \gtx_channel.gtxe2_channel_i_i_67 + (.I0(converge_cnt_reg[6]), + .I1(converge_cnt_reg[7]), + .I2(converge_cnt_reg[4]), + .I3(converge_cnt_reg[5]), + .I4(converge_cnt_reg[21]), + .I5(converge_cnt_reg[13]), + .O(\gtx_channel.gtxe2_channel_i_i_67_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair203" *) + LUT1 #( + .INIT(2'h1)) + \oobclk_div.oobclk_cnt[0]_i_1__2 + (.I0(oobclk_cnt[0]), + .O(p_1_in__0[0])); + (* SOFT_HLUTNM = "soft_lutpair203" *) + LUT2 #( + .INIT(4'h6)) + \oobclk_div.oobclk_cnt[1]_i_1__2 + (.I0(oobclk_cnt[0]), + .I1(oobclk_cnt[1]), + .O(p_1_in__0[1])); + FDRE #( + .INIT(1'b0)) + \oobclk_div.oobclk_cnt_reg[0] + (.C(pipe_oobclk_in), + .CE(1'b1), + .D(p_1_in__0[0]), + .Q(oobclk_cnt[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \oobclk_div.oobclk_cnt_reg[1] + (.C(pipe_oobclk_in), + .CE(1'b1), + .D(p_1_in__0[1]), + .Q(oobclk_cnt[1]), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'hB8)) + \oobclk_div.oobclk_i_1__2 + (.I0(oobclk_cnt[1]), + .I1(pclk_sel_reg2), + .I2(oobclk_cnt[0]), + .O(\oobclk_div.oobclk_i_1__2_n_0 )); + FDRE #( + .INIT(1'b0)) + \oobclk_div.oobclk_reg + (.C(pipe_oobclk_in), + .CE(1'b1), + .D(\oobclk_div.oobclk_i_1__2_n_0 ), + .Q(USER_OOBCLK), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE pclk_sel_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_pclk_sel_out), + .Q(pclk_sel_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE pclk_sel_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pclk_sel_reg1), + .Q(pclk_sel_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_done_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_DONE), + .Q(rate_done_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_done_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_done_reg1), + .Q(rate_done_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_gen3_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_gen3_3), + .Q(rate_gen3_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_gen3_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_gen3_reg1), + .Q(rate_gen3_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_IDLE), + .Q(rate_idle_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_idle_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_idle_reg1), + .Q(rate_idle_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_rxsync_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(USER_RATE_RXSYNC), + .Q(rate_rxsync_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rate_rxsync_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rate_rxsync_reg1), + .Q(rate_rxsync_reg2), + .R(RST_RXUSRCLK_RESET)); + LUT2 #( + .INIT(4'h8)) + \resetdone_reg1[3]_i_1 + (.I0(rxresetdone_reg2), + .I1(txresetdone_reg2), + .O(RST_RESETDONE)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_start_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RESETOVRD_START), + .Q(resetovrd_start_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE resetovrd_start_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(resetovrd_start_reg1), + .Q(resetovrd_start_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(RST_IDLE), + .Q(rst_idle_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rst_idle_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rst_idle_reg1), + .Q(rst_idle_reg2), + .R(RST_RXUSRCLK_RESET)); + LUT5 #( + .INIT(32'hD0505050)) + \rxcdrlock_cnt[0]_i_1__2 + (.I0(rxcdrlock_cnt_reg[0]), + .I1(rxcdrlock_cnt_reg[2]), + .I2(rxcdrlock_reg2), + .I3(rxcdrlock_cnt_reg[1]), + .I4(rxcdrlock_cnt_reg[3]), + .O(p_0_in__0[0])); + LUT5 #( + .INIT(32'h8FF00000)) + \rxcdrlock_cnt[1]_i_1__2 + (.I0(rxcdrlock_cnt_reg[3]), + .I1(rxcdrlock_cnt_reg[2]), + .I2(rxcdrlock_cnt_reg[0]), + .I3(rxcdrlock_cnt_reg[1]), + .I4(rxcdrlock_reg2), + .O(p_0_in__0[1])); + LUT5 #( + .INIT(32'hF8780000)) + \rxcdrlock_cnt[2]_i_1__2 + (.I0(rxcdrlock_cnt_reg[0]), + .I1(rxcdrlock_cnt_reg[1]), + .I2(rxcdrlock_cnt_reg[2]), + .I3(rxcdrlock_cnt_reg[3]), + .I4(rxcdrlock_reg2), + .O(p_0_in__0[2])); + LUT5 #( + .INIT(32'hFF008000)) + \rxcdrlock_cnt[3]_i_1__2 + (.I0(rxcdrlock_cnt_reg[0]), + .I1(rxcdrlock_cnt_reg[1]), + .I2(rxcdrlock_cnt_reg[2]), + .I3(rxcdrlock_reg2), + .I4(rxcdrlock_cnt_reg[3]), + .O(p_0_in__0[3])); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[0]), + .Q(rxcdrlock_cnt_reg[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[1]), + .Q(rxcdrlock_cnt_reg[1]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[2]), + .Q(rxcdrlock_cnt_reg[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \rxcdrlock_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(p_0_in__0[3]), + .Q(rxcdrlock_cnt_reg[3]), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h80000000)) + \rxcdrlock_reg1[3]_i_1 + (.I0(rxcdrlock_cnt_reg[2]), + .I1(rxcdrlock_cnt_reg[3]), + .I2(gt_rxcdrlock_3), + .I3(rxcdrlock_cnt_reg[1]), + .I4(rxcdrlock_cnt_reg[0]), + .O(RST_RXCDRLOCK)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(gt_rxcdrlock_3), + .Q(rxcdrlock_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxcdrlock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxcdrlock_reg1), + .Q(rxcdrlock_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_adapt_done_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RXEQ_ADAPT_DONE), + .Q(rxeq_adapt_done_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxeq_adapt_done_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_adapt_done_reg1), + .Q(rxeq_adapt_done_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_RXRESETDONE), + .Q(rxresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxresetdone_reg1), + .Q(rxresetdone_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxstatus_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rxstatus_reg1_reg_0), + .Q(rxstatus_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxstatus_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rxstatus_reg1), + .Q(rxstatus_reg2), + .R(RST_RXUSRCLK_RESET)); + LUT6 #( + .INIT(64'hC404040404040404)) + \rxvalid_cnt[0]_i_1__2 + (.I0(rxstatus_reg2), + .I1(rxvalid_reg2), + .I2(rxvalid_cnt_reg[0]), + .I3(rxvalid_cnt_reg[1]), + .I4(rxvalid_cnt_reg[2]), + .I5(rxvalid_cnt_reg[3]), + .O(p_0_in__0__0[0])); + LUT6 #( + .INIT(64'h808000F000F00000)) + \rxvalid_cnt[1]_i_1__2 + (.I0(rxvalid_cnt_reg[3]), + .I1(rxvalid_cnt_reg[2]), + .I2(rxvalid_reg2), + .I3(rxstatus_reg2), + .I4(rxvalid_cnt_reg[1]), + .I5(rxvalid_cnt_reg[0]), + .O(p_0_in__0__0[1])); + LUT6 #( + .INIT(64'h80BF000000C00000)) + \rxvalid_cnt[2]_i_1__2 + (.I0(rxvalid_cnt_reg[3]), + .I1(rxvalid_cnt_reg[0]), + .I2(rxvalid_cnt_reg[1]), + .I3(rxstatus_reg2), + .I4(rxvalid_reg2), + .I5(rxvalid_cnt_reg[2]), + .O(p_0_in__0__0[2])); + LUT6 #( + .INIT(64'h8C08080808080808)) + \rxvalid_cnt[3]_i_1__2 + (.I0(rxvalid_cnt_reg[3]), + .I1(rxvalid_reg2), + .I2(rxstatus_reg2), + .I3(rxvalid_cnt_reg[2]), + .I4(rxvalid_cnt_reg[1]), + .I5(rxvalid_cnt_reg[0]), + .O(p_0_in__0__0[3])); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[0] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[0]), + .Q(rxvalid_cnt_reg[0]), + .R(RST_RXUSRCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[1] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[1]), + .Q(rxvalid_cnt_reg[1]), + .R(RST_RXUSRCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[2] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[2]), + .Q(rxvalid_cnt_reg[2]), + .R(RST_RXUSRCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \rxvalid_cnt_reg[3] + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(p_0_in__0__0[3]), + .Q(rxvalid_cnt_reg[3]), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxvalid_reg1_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(gt_rxvalid_3), + .Q(rxvalid_reg1), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rxvalid_reg2_reg + (.C(pipe_rxusrclk_in), + .CE(1'b1), + .D(rxvalid_reg1), + .Q(rxvalid_reg2), + .R(RST_RXUSRCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txcompliance_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_TXCOMPLIANCE), + .Q(txcompliance_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txcompliance_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcompliance_reg1), + .Q(txcompliance_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txelecidle_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(PIPE_TXELECIDLE), + .Q(txelecidle_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txelecidle_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txelecidle_reg1), + .Q(txelecidle_reg2), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(USER_TXRESETDONE), + .Q(txresetdone_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE txresetdone_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txresetdone_reg1), + .Q(txresetdone_reg2), + .R(RST_CPLLRESET)); +endmodule + +module pcie_7x_0_pcie_7x_0_pipe_wrapper + (cpllpd, + cpllpd_0, + cpllpd_1, + cpllpd_2, + pci_exp_txn, + pci_exp_txp, + PIPE_RXCHANISALIGNED, + gt_rx_elec_idle_wire_filter, + pipe_rxoutclk_out, + pipe_txoutclk_out, + PIPE_RXSTATUS, + gt_rx_data_wire_filter, + gt_rx_data_k_wire_filter, + pipe_dclk_in_0, + pipe_dclk_in_1, + pipe_dclk_in_2, + reg_clock_locked_reg, + gt_rxvalid_q_reg, + gt_rxvalid_q_reg_0, + gt_rxvalid_q_reg_1, + gt_rxvalid_q_reg_2, + gen3_reg, + pipe_pclk_sel_out, + rate_cpllpd_0, + rate_cpllpd_1, + rate_cpllpd_2, + rate_cpllpd_3, + gt_rx_phy_status_wire_filter, + CPLLPD0, + pipe_dclk_in, + sys_clk, + pci_exp_rxn, + pci_exp_rxp, + PIPE_RXPOLARITY, + pipe_rxusrclk_in, + pipe_tx_deemph_gt, + pipe_tx_rcvr_det_gt, + PIPE_TXELECIDLE, + pipe_pclk_in, + PIPE_POWERDOWN, + \cplllock_reg1_reg[3] , + PIPE_TXDATA, + PIPE_TXCOMPLIANCE, + PIPE_TXDATAK, + CPLLPD0_3, + CPLLPD0_4, + CPLLPD0_5, + reset_n_reg1_reg_0, + reg_clock_locked, + pipe_rx0_valid_gt, + pipe_rx1_valid_gt, + pipe_rx2_valid_gt, + pipe_rx3_valid_gt, + \rate_reg1_reg[0] , + pipe_mmcm_lock_in, + pipe_oobclk_in); + output cpllpd; + output cpllpd_0; + output cpllpd_1; + output cpllpd_2; + output [3:0]pci_exp_txn; + output [3:0]pci_exp_txp; + output [3:0]PIPE_RXCHANISALIGNED; + output [3:0]gt_rx_elec_idle_wire_filter; + output [3:0]pipe_rxoutclk_out; + output pipe_txoutclk_out; + output [2:0]PIPE_RXSTATUS; + output [63:0]gt_rx_data_wire_filter; + output [7:0]gt_rx_data_k_wire_filter; + output [2:0]pipe_dclk_in_0; + output [2:0]pipe_dclk_in_1; + output [2:0]pipe_dclk_in_2; + output reg_clock_locked_reg; + output gt_rxvalid_q_reg; + output gt_rxvalid_q_reg_0; + output gt_rxvalid_q_reg_1; + output gt_rxvalid_q_reg_2; + output gen3_reg; + output [3:0]pipe_pclk_sel_out; + output rate_cpllpd_0; + output rate_cpllpd_1; + output rate_cpllpd_2; + output rate_cpllpd_3; + output [3:0]gt_rx_phy_status_wire_filter; + input CPLLPD0; + input pipe_dclk_in; + input sys_clk; + input [3:0]pci_exp_rxn; + input [3:0]pci_exp_rxp; + input [3:0]PIPE_RXPOLARITY; + input pipe_rxusrclk_in; + input pipe_tx_deemph_gt; + input pipe_tx_rcvr_det_gt; + input [3:0]PIPE_TXELECIDLE; + input pipe_pclk_in; + input [7:0]PIPE_POWERDOWN; + input [2:0]\cplllock_reg1_reg[3] ; + input [63:0]PIPE_TXDATA; + input [3:0]PIPE_TXCOMPLIANCE; + input [7:0]PIPE_TXDATAK; + input CPLLPD0_3; + input CPLLPD0_4; + input CPLLPD0_5; + input reset_n_reg1_reg_0; + input reg_clock_locked; + input pipe_rx0_valid_gt; + input pipe_rx1_valid_gt; + input pipe_rx2_valid_gt; + input pipe_rx3_valid_gt; + input [0:0]\rate_reg1_reg[0] ; + input pipe_mmcm_lock_in; + input pipe_oobclk_in; + + wire CPLLPD0; + wire CPLLPD0_3; + wire CPLLPD0_4; + wire CPLLPD0_5; + wire [7:0]PIPE_POWERDOWN; + wire [3:0]PIPE_RXCHANISALIGNED; + wire [3:0]PIPE_RXPOLARITY; + wire [2:0]PIPE_RXSTATUS; + wire [3:0]PIPE_TXCOMPLIANCE; + wire [63:0]PIPE_TXDATA; + wire [7:0]PIPE_TXDATAK; + wire [3:0]PIPE_TXELECIDLE; + wire SYNC_TXSYNC_START0; + wire SYNC_TXSYNC_START00_out; + wire SYNC_TXSYNC_START010_out; + wire SYNC_TXSYNC_START05_out; + wire [2:0]\cplllock_reg1_reg[3] ; + wire cpllpd; + wire cpllpd_0; + wire cpllpd_1; + wire cpllpd_2; + wire drp_done_0; + wire drp_done_1; + wire drp_done_2; + wire drp_done_3; + wire [6:0]eq_txeq_maincursor_0; + wire [6:0]eq_txeq_maincursor_14; + wire [6:0]eq_txeq_maincursor_21; + wire [6:0]eq_txeq_maincursor_7; + wire [4:0]eq_txeq_postcursor_0; + wire [4:0]eq_txeq_postcursor_10; + wire [4:0]eq_txeq_postcursor_15; + wire [4:0]eq_txeq_postcursor_5; + wire [4:0]eq_txeq_precursor_0; + wire [4:0]eq_txeq_precursor_10; + wire [4:0]eq_txeq_precursor_15; + wire [4:0]eq_txeq_precursor_5; + wire gen3_reg; + wire gt_cpllpdrefclk; + wire gt_phystatus_0; + wire gt_phystatus_1; + wire gt_phystatus_2; + wire gt_phystatus_3; + wire [7:0]gt_rx_data_k_wire_filter; + wire [63:0]gt_rx_data_wire_filter; + wire [3:0]gt_rx_elec_idle_wire_filter; + wire [3:0]gt_rx_phy_status_wire_filter; + wire gt_rxcdrlock_0; + wire gt_rxcdrlock_1; + wire gt_rxcdrlock_2; + wire gt_rxcdrlock_3; + wire [4:0]\gt_rxchbondi[3]_0 ; + wire gt_rxratedone_0; + wire gt_rxratedone_1; + wire gt_rxratedone_2; + wire gt_rxratedone_3; + wire gt_rxresetdone_0; + wire gt_rxresetdone_1; + wire gt_rxresetdone_2; + wire gt_rxresetdone_3; + wire gt_rxvalid_0; + wire gt_rxvalid_1; + wire gt_rxvalid_2; + wire gt_rxvalid_3; + wire gt_rxvalid_q_reg; + wire gt_rxvalid_q_reg_0; + wire gt_rxvalid_q_reg_1; + wire gt_rxvalid_q_reg_2; + wire gt_txratedone_0; + wire gt_txratedone_1; + wire gt_txratedone_2; + wire gt_txratedone_3; + wire gt_txresetdone_0; + wire gt_txresetdone_1; + wire gt_txresetdone_2; + wire gt_txresetdone_3; + wire \gtx_channel.gtxe2_channel_i_i_52_n_0 ; + wire \gtx_channel.gtxe2_channel_i_i_6__2_n_0 ; + wire p_0_in1_in; + wire p_0_in1_in_0; + wire p_0_in1_in_3; + wire p_0_in1_in_4; + wire p_1_in; + wire p_1_in2_in; + wire p_1_in2_in_1; + wire p_1_in2_in_2; + wire p_1_in2_in_5; + wire [3:0]pci_exp_rxn; + wire [3:0]pci_exp_rxp; + wire [3:0]pci_exp_txn; + wire [3:0]pci_exp_txp; + wire pipe_dclk_in; + wire [2:0]pipe_dclk_in_0; + wire [2:0]pipe_dclk_in_1; + wire [2:0]pipe_dclk_in_2; + wire \pipe_lane[0].gt_wrapper_i_n_1 ; + wire \pipe_lane[0].gt_wrapper_i_n_11 ; + wire \pipe_lane[0].gt_wrapper_i_n_15 ; + wire \pipe_lane[0].gt_wrapper_i_n_17 ; + wire \pipe_lane[0].gt_wrapper_i_n_18 ; + wire \pipe_lane[0].gt_wrapper_i_n_2 ; + wire \pipe_lane[0].gt_wrapper_i_n_21 ; + wire \pipe_lane[0].gt_wrapper_i_n_22 ; + wire \pipe_lane[0].gt_wrapper_i_n_23 ; + wire \pipe_lane[0].gt_wrapper_i_n_24 ; + wire \pipe_lane[0].gt_wrapper_i_n_25 ; + wire \pipe_lane[0].gt_wrapper_i_n_26 ; + wire \pipe_lane[0].gt_wrapper_i_n_27 ; + wire \pipe_lane[0].gt_wrapper_i_n_28 ; + wire \pipe_lane[0].gt_wrapper_i_n_29 ; + wire \pipe_lane[0].gt_wrapper_i_n_30 ; + wire \pipe_lane[0].gt_wrapper_i_n_31 ; + wire \pipe_lane[0].gt_wrapper_i_n_32 ; + wire \pipe_lane[0].gt_wrapper_i_n_33 ; + wire \pipe_lane[0].gt_wrapper_i_n_34 ; + wire \pipe_lane[0].gt_wrapper_i_n_35 ; + wire \pipe_lane[0].gt_wrapper_i_n_36 ; + wire \pipe_lane[0].gt_wrapper_i_n_8 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_0 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_1 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_10 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_11 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_12 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_13 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_14 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_15 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_16 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_17 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_18 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_19 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_2 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_20 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_21 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_22 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_23 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_24 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_25 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_3 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_4 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_5 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_6 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_7 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_8 ; + wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_9 ; + wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_17 ; + wire \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0 ; + wire \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1 ; + wire \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2 ; + wire \pipe_lane[0].pipe_sync_i_n_1 ; + wire \pipe_lane[0].pipe_user_i_n_1 ; + wire \pipe_lane[0].pipe_user_i_n_10 ; + wire \pipe_lane[0].pipe_user_i_n_11 ; + wire \pipe_lane[0].pipe_user_i_n_12 ; + wire \pipe_lane[0].pipe_user_i_n_15 ; + wire \pipe_lane[0].pipe_user_i_n_5 ; + wire \pipe_lane[0].pipe_user_i_n_6 ; + wire \pipe_lane[1].gt_wrapper_i_n_1 ; + wire \pipe_lane[1].gt_wrapper_i_n_11 ; + wire \pipe_lane[1].gt_wrapper_i_n_15 ; + wire \pipe_lane[1].gt_wrapper_i_n_16 ; + wire \pipe_lane[1].gt_wrapper_i_n_17 ; + wire \pipe_lane[1].gt_wrapper_i_n_2 ; + wire \pipe_lane[1].gt_wrapper_i_n_20 ; + wire \pipe_lane[1].gt_wrapper_i_n_21 ; + wire \pipe_lane[1].gt_wrapper_i_n_22 ; + wire \pipe_lane[1].gt_wrapper_i_n_23 ; + wire \pipe_lane[1].gt_wrapper_i_n_24 ; + wire \pipe_lane[1].gt_wrapper_i_n_25 ; + wire \pipe_lane[1].gt_wrapper_i_n_26 ; + wire \pipe_lane[1].gt_wrapper_i_n_27 ; + wire \pipe_lane[1].gt_wrapper_i_n_28 ; + wire \pipe_lane[1].gt_wrapper_i_n_29 ; + wire \pipe_lane[1].gt_wrapper_i_n_30 ; + wire \pipe_lane[1].gt_wrapper_i_n_31 ; + wire \pipe_lane[1].gt_wrapper_i_n_32 ; + wire \pipe_lane[1].gt_wrapper_i_n_33 ; + wire \pipe_lane[1].gt_wrapper_i_n_34 ; + wire \pipe_lane[1].gt_wrapper_i_n_35 ; + wire \pipe_lane[1].gt_wrapper_i_n_8 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_0 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_1 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_10 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_11 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_12 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_13 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_14 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_15 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_16 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_17 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_18 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_19 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_2 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_20 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_21 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_22 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_23 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_24 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_25 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_3 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_4 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_5 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_6 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_7 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_8 ; + wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_9 ; + wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_17 ; + wire \pipe_lane[1].pipe_rate.pipe_rate_i_n_1 ; + wire \pipe_lane[1].pipe_user_i_n_1 ; + wire \pipe_lane[2].gt_wrapper_i_n_1 ; + wire \pipe_lane[2].gt_wrapper_i_n_11 ; + wire \pipe_lane[2].gt_wrapper_i_n_15 ; + wire \pipe_lane[2].gt_wrapper_i_n_16 ; + wire \pipe_lane[2].gt_wrapper_i_n_17 ; + wire \pipe_lane[2].gt_wrapper_i_n_2 ; + wire \pipe_lane[2].gt_wrapper_i_n_20 ; + wire \pipe_lane[2].gt_wrapper_i_n_21 ; + wire \pipe_lane[2].gt_wrapper_i_n_22 ; + wire \pipe_lane[2].gt_wrapper_i_n_23 ; + wire \pipe_lane[2].gt_wrapper_i_n_24 ; + wire \pipe_lane[2].gt_wrapper_i_n_25 ; + wire \pipe_lane[2].gt_wrapper_i_n_26 ; + wire \pipe_lane[2].gt_wrapper_i_n_27 ; + wire \pipe_lane[2].gt_wrapper_i_n_28 ; + wire \pipe_lane[2].gt_wrapper_i_n_29 ; + wire \pipe_lane[2].gt_wrapper_i_n_30 ; + wire \pipe_lane[2].gt_wrapper_i_n_31 ; + wire \pipe_lane[2].gt_wrapper_i_n_32 ; + wire \pipe_lane[2].gt_wrapper_i_n_33 ; + wire \pipe_lane[2].gt_wrapper_i_n_34 ; + wire \pipe_lane[2].gt_wrapper_i_n_35 ; + wire \pipe_lane[2].gt_wrapper_i_n_8 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_0 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_1 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_10 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_11 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_12 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_13 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_14 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_15 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_16 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_17 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_18 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_19 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_2 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_20 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_21 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_22 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_23 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_24 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_25 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_3 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_4 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_5 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_6 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_7 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_8 ; + wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_9 ; + wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_17 ; + wire \pipe_lane[2].pipe_user_i_n_10 ; + wire \pipe_lane[2].pipe_user_i_n_11 ; + wire \pipe_lane[2].pipe_user_i_n_14 ; + wire \pipe_lane[2].pipe_user_i_n_2 ; + wire \pipe_lane[2].pipe_user_i_n_5 ; + wire \pipe_lane[2].pipe_user_i_n_9 ; + wire \pipe_lane[3].gt_wrapper_i_n_1 ; + wire \pipe_lane[3].gt_wrapper_i_n_11 ; + wire \pipe_lane[3].gt_wrapper_i_n_15 ; + wire \pipe_lane[3].gt_wrapper_i_n_16 ; + wire \pipe_lane[3].gt_wrapper_i_n_17 ; + wire \pipe_lane[3].gt_wrapper_i_n_2 ; + wire \pipe_lane[3].gt_wrapper_i_n_20 ; + wire \pipe_lane[3].gt_wrapper_i_n_21 ; + wire \pipe_lane[3].gt_wrapper_i_n_22 ; + wire \pipe_lane[3].gt_wrapper_i_n_23 ; + wire \pipe_lane[3].gt_wrapper_i_n_24 ; + wire \pipe_lane[3].gt_wrapper_i_n_25 ; + wire \pipe_lane[3].gt_wrapper_i_n_26 ; + wire \pipe_lane[3].gt_wrapper_i_n_27 ; + wire \pipe_lane[3].gt_wrapper_i_n_28 ; + wire \pipe_lane[3].gt_wrapper_i_n_29 ; + wire \pipe_lane[3].gt_wrapper_i_n_30 ; + wire \pipe_lane[3].gt_wrapper_i_n_31 ; + wire \pipe_lane[3].gt_wrapper_i_n_32 ; + wire \pipe_lane[3].gt_wrapper_i_n_33 ; + wire \pipe_lane[3].gt_wrapper_i_n_34 ; + wire \pipe_lane[3].gt_wrapper_i_n_35 ; + wire \pipe_lane[3].gt_wrapper_i_n_8 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_0 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_1 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_10 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_11 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_12 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_13 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_14 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_15 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_16 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_17 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_18 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_19 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_2 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_20 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_21 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_22 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_23 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_24 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_25 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_3 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_4 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_5 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_6 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_7 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_8 ; + wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_9 ; + wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_17 ; + wire \pipe_lane[3].pipe_user_i_n_1 ; + wire pipe_mmcm_lock_in; + wire pipe_oobclk_in; + wire pipe_pclk_in; + wire [3:0]pipe_pclk_sel_out; + wire \pipe_reset.pipe_reset_i_n_0 ; + wire \pipe_reset.pipe_reset_i_n_1 ; + wire pipe_rx0_valid_gt; + wire pipe_rx1_valid_gt; + wire pipe_rx2_valid_gt; + wire pipe_rx3_valid_gt; + wire [3:0]pipe_rxoutclk_out; + wire pipe_rxusrclk_in; + wire pipe_tx_deemph_gt; + wire pipe_tx_rcvr_det_gt; + wire pipe_txoutclk_out; + wire qdrp_done; + wire \qpll_reset.qpll_reset_i_n_0 ; + wire qpllpd; + wire qrst_drp_start; + wire qrst_qpllreset; + wire rate_cpllpd_0; + wire rate_cpllpd_1; + wire rate_cpllpd_2; + wire rate_cpllpd_3; + wire rate_cpllreset_0; + wire rate_cpllreset_1; + wire rate_cpllreset_2; + wire rate_cpllreset_3; + wire rate_done_0; + wire rate_done_1; + wire rate_done_2; + wire rate_done_3; + wire rate_drp_start_0; + wire rate_drp_start_1; + wire rate_drp_start_2; + wire rate_drp_start_3; + wire rate_drp_x16_0; + wire rate_drp_x16_1; + wire rate_drp_x16_2; + wire rate_drp_x16_3; + wire rate_drp_x16x20_mode_0; + wire rate_drp_x16x20_mode_1; + wire rate_drp_x16x20_mode_2; + wire rate_drp_x16x20_mode_3; + wire rate_gen3_1; + wire rate_gen3_2; + wire rate_gen3_3; + wire rate_idle_0; + wire rate_idle_1; + wire rate_idle_2; + wire rate_idle_3; + wire [3:0]rate_qpllpd; + wire [3:0]rate_qpllreset; + wire [0:0]rate_rate_0; + wire [0:0]rate_rate_3; + wire [0:0]rate_rate_6; + wire [0:0]rate_rate_9; + wire [0:0]\rate_reg1_reg[0] ; + wire rate_resetovrd_start_0; + wire rate_resetovrd_start_1; + wire rate_resetovrd_start_2; + wire rate_resetovrd_start_3; + wire rate_rxsync_0; + wire rate_rxsync_1; + wire rate_rxsync_2; + wire rate_rxsync_3; + wire rate_rxsync_start_0; + wire rate_rxsync_start_1; + wire rate_rxsync_start_2; + wire rate_rxsync_start_3; + wire [0:0]rate_sysclksel_0; + wire [0:0]rate_sysclksel_2; + wire [0:0]rate_sysclksel_4; + wire [0:0]rate_sysclksel_6; + wire rate_txpmareset_0; + wire rate_txpmareset_1; + wire rate_txpmareset_2; + wire rate_txpmareset_3; + wire reg_clock_locked; + wire reg_clock_locked_reg; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire reset_n_reg1; + wire reset_n_reg1_reg_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire reset_n_reg2; + wire rst_cpllreset; + wire rst_dclk_reset; + wire rst_gtreset; + wire rst_rxusrclk_reset; + wire rst_txsync_start; + wire rst_userrdy; + wire rxchbonden_0; + wire rxchbonden_1; + wire rxchbonden_2; + wire rxchbonden_3; + wire rxdlysresetdone_3; + wire rxphaligndone_s_3; + wire sync_txdlyen_0; + wire sync_txdlysreset_0; + wire sync_txdlysreset_1; + wire sync_txdlysreset_2; + wire sync_txdlysreset_3; + wire sync_txphalign_0; + wire sync_txphalign_1; + wire sync_txphalign_2; + wire sync_txphalign_3; + wire sync_txphinit_0; + wire sync_txphinit_1; + wire sync_txphinit_2; + wire sync_txphinit_3; + wire sync_txsync_done_0; + wire sync_txsync_done_1; + wire sync_txsync_done_2; + wire sync_txsync_done_3; + wire sys_clk; + wire txdlysresetdone_3; + wire txsyncallin; + wire user_active_lane_0; + wire user_active_lane_1; + wire user_active_lane_2; + wire user_active_lane_3; + wire user_oobclk_0; + wire user_oobclk_1; + wire user_oobclk_2; + wire user_oobclk_3; + wire [3:0]user_resetdone; + wire [3:1]user_rx_converge; + wire user_rxcdrlock_0; + wire user_rxcdrlock_1; + wire user_rxcdrlock_2; + wire user_rxcdrlock_3; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG cpllpd_refclk_inst + (.I(sys_clk), + .O(gt_cpllpdrefclk)); + LUT5 #( + .INIT(32'h4555FFFF)) + \gtx_channel.gtxe2_channel_i_i_52 + (.I0(\pipe_lane[2].pipe_user_i_n_14 ), + .I1(\pipe_lane[2].pipe_user_i_n_9 ), + .I2(\pipe_lane[2].pipe_user_i_n_11 ), + .I3(\pipe_lane[2].pipe_user_i_n_10 ), + .I4(user_rx_converge[3]), + .O(\gtx_channel.gtxe2_channel_i_i_52_n_0 )); + LUT6 #( + .INIT(64'h00000000AAAA0080)) + \gtx_channel.gtxe2_channel_i_i_6__2 + (.I0(user_rx_converge[1]), + .I1(\pipe_lane[0].pipe_user_i_n_11 ), + .I2(\pipe_lane[0].pipe_user_i_n_12 ), + .I3(\pipe_lane[0].pipe_user_i_n_10 ), + .I4(\pipe_lane[0].pipe_user_i_n_15 ), + .I5(\gtx_channel.gtxe2_channel_i_i_52_n_0 ), + .O(\gtx_channel.gtxe2_channel_i_i_6__2_n_0 )); + pcie_7x_0_pcie_7x_0_gt_wrapper \pipe_lane[0].gt_wrapper_i + (.CPLLPD0(CPLLPD0), + .DRPADDR({\pipe_lane[0].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_25 }), + .DRPDI({\pipe_lane[0].pipe_drp.pipe_drp_i_n_2 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_11 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_12 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_13 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_14 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_17 }), + .DRP_DO({\pipe_lane[0].gt_wrapper_i_n_21 ,\pipe_lane[0].gt_wrapper_i_n_22 ,\pipe_lane[0].gt_wrapper_i_n_23 ,\pipe_lane[0].gt_wrapper_i_n_24 ,\pipe_lane[0].gt_wrapper_i_n_25 ,\pipe_lane[0].gt_wrapper_i_n_26 ,\pipe_lane[0].gt_wrapper_i_n_27 ,\pipe_lane[0].gt_wrapper_i_n_28 ,\pipe_lane[0].gt_wrapper_i_n_29 ,\pipe_lane[0].gt_wrapper_i_n_30 ,\pipe_lane[0].gt_wrapper_i_n_31 ,\pipe_lane[0].gt_wrapper_i_n_32 ,\pipe_lane[0].gt_wrapper_i_n_33 ,\pipe_lane[0].gt_wrapper_i_n_34 ,\pipe_lane[0].gt_wrapper_i_n_35 ,\pipe_lane[0].gt_wrapper_i_n_36 }), + .DRP_GTXRESET(rst_gtreset), + .DRP_RDY(\pipe_lane[0].gt_wrapper_i_n_2 ), + .PIPE_POWERDOWN(PIPE_POWERDOWN[1:0]), + .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[0]), + .PIPE_RXPOLARITY(PIPE_RXPOLARITY[0]), + .PIPE_RXSTATUS(PIPE_RXSTATUS), + .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[0]), + .PIPE_TXDATA(PIPE_TXDATA[15:0]), + .PIPE_TXDATAK(PIPE_TXDATAK[1:0]), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE[0]), + .QPLL_QPLLOUTCLK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1 ), + .QPLL_QPLLOUTREFCLK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2 ), + .QRST_CPLLLOCK(\pipe_lane[0].gt_wrapper_i_n_1 ), + .RATE_PHYSTATUS(gt_phystatus_0), + .RATE_RXRATEDONE(gt_rxratedone_0), + .RATE_TXRATEDONE(gt_txratedone_0), + .RST_CPLLRESET(rst_cpllreset), + .RXCHBONDO(\gt_rxchbondi[3]_0 ), + .RXRATE(rate_rate_0), + .RXSYSCLKSEL(rate_sysclksel_0), + .SYNC_RXPHALIGNDONE_M(\pipe_lane[0].gt_wrapper_i_n_11 ), + .SYNC_TXDLYSRESET(sync_txdlysreset_0), + .SYNC_TXPHALIGN(sync_txphalign_0), + .SYNC_TXPHINIT(sync_txphinit_0), + .TXMAINCURSOR(eq_txeq_maincursor_0), + .TXPOSTCURSOR(eq_txeq_postcursor_0), + .TXPRECURSOR(eq_txeq_precursor_0), + .USER_OOBCLK(user_oobclk_0), + .USER_RXRESETDONE(gt_rxresetdone_0), + .USER_TXRESETDONE(gt_txresetdone_0), + .\cplllock_reg1_reg[0] (\pipe_lane[0].pipe_drp.pipe_drp_i_n_0 ), + .\cplllock_reg1_reg[0]_0 (\pipe_lane[0].pipe_drp.pipe_drp_i_n_1 ), + .\cplllock_reg1_reg[0]_1 (\gtx_channel.gtxe2_channel_i_i_6__2_n_0 ), + .\cplllock_reg1_reg[0]_2 (\cplllock_reg1_reg[3] ), + .cpllpd(cpllpd), + .gt_cpllpdrefclk(gt_cpllpdrefclk), + .gt_rx_data_k_wire_filter(gt_rx_data_k_wire_filter[1:0]), + .gt_rx_data_wire_filter(gt_rx_data_wire_filter[15:0]), + .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[0]), + .gt_rxcdrlock_0(gt_rxcdrlock_0), + .gt_rxvalid_0(gt_rxvalid_0), + .pci_exp_rxn(pci_exp_rxn[0]), + .pci_exp_rxp(pci_exp_rxp[0]), + .pci_exp_txn(pci_exp_txn[0]), + .pci_exp_txp(pci_exp_txp[0]), + .pipe_dclk_in(pipe_dclk_in), + .pipe_dclk_in_0(\pipe_lane[0].gt_wrapper_i_n_8 ), + .pipe_dclk_in_1(\pipe_lane[0].gt_wrapper_i_n_15 ), + .pipe_dclk_in_2(\pipe_lane[0].gt_wrapper_i_n_17 ), + .pipe_dclk_in_3(\pipe_lane[0].gt_wrapper_i_n_18 ), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rxoutclk_out(pipe_rxoutclk_out[0]), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .pipe_tx_deemph_gt(pipe_tx_deemph_gt), + .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt), + .pipe_txoutclk_out(pipe_txoutclk_out), + .rate_cpllreset_0(rate_cpllreset_0), + .rate_txpmareset_0(rate_txpmareset_0), + .rst_userrdy(rst_userrdy), + .rxchbonden_0(rxchbonden_0), + .sync_txdlyen_0(sync_txdlyen_0), + .sys_clk(sys_clk)); + pcie_7x_0_pcie_7x_0_pipe_drp \pipe_lane[0].pipe_drp.pipe_drp_i + (.D({\pipe_lane[0].gt_wrapper_i_n_21 ,\pipe_lane[0].gt_wrapper_i_n_22 ,\pipe_lane[0].gt_wrapper_i_n_23 ,\pipe_lane[0].gt_wrapper_i_n_24 ,\pipe_lane[0].gt_wrapper_i_n_25 ,\pipe_lane[0].gt_wrapper_i_n_26 ,\pipe_lane[0].gt_wrapper_i_n_27 ,\pipe_lane[0].gt_wrapper_i_n_28 ,\pipe_lane[0].gt_wrapper_i_n_29 ,\pipe_lane[0].gt_wrapper_i_n_30 ,\pipe_lane[0].gt_wrapper_i_n_31 ,\pipe_lane[0].gt_wrapper_i_n_32 ,\pipe_lane[0].gt_wrapper_i_n_33 ,\pipe_lane[0].gt_wrapper_i_n_34 ,\pipe_lane[0].gt_wrapper_i_n_35 ,\pipe_lane[0].gt_wrapper_i_n_36 }), + .DRPADDR({\pipe_lane[0].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_25 }), + .DRPDI({\pipe_lane[0].pipe_drp.pipe_drp_i_n_2 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_11 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_12 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_13 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_14 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_17 }), + .DRP_DONE(drp_done_0), + .DRP_GTXRESET(rst_gtreset), + .DRP_RDY(\pipe_lane[0].gt_wrapper_i_n_2 ), + .RATE_DRP_START(rate_drp_start_0), + .RATE_DRP_X16(rate_drp_x16_0), + .RATE_DRP_X16X20_MODE(rate_drp_x16x20_mode_0), + .RST_DCLK_RESET(rst_dclk_reset), + .\fsm_reg[1]_0 (\pipe_lane[0].pipe_drp.pipe_drp_i_n_0 ), + .\fsm_reg[1]_1 (\pipe_lane[0].pipe_drp.pipe_drp_i_n_1 ), + .pipe_dclk_in(pipe_dclk_in), + .\rate_reg1_reg[0]_0 (\rate_reg1_reg[0] )); + pcie_7x_0_pcie_7x_0_pipe_eq \pipe_lane[0].pipe_eq.pipe_eq_i + (.RST_CPLLRESET(rst_cpllreset), + .TXMAINCURSOR(eq_txeq_maincursor_0), + .TXPOSTCURSOR(eq_txeq_postcursor_0), + .TXPRECURSOR(eq_txeq_precursor_0), + .USER_RATE_GEN3(gen3_reg), + .USER_RXEQ_ADAPT_DONE(\pipe_lane[0].pipe_eq.pipe_eq_i_n_17 ), + .pipe_pclk_in(pipe_pclk_in)); + pcie_7x_0_pcie_7x_0_gt_common \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i + (.QPLL_DRP_DONE(qdrp_done), + .QPLL_DRP_GEN3(\pipe_lane[1].pipe_rate.pipe_rate_i_n_1 ), + .QPLL_QPLLLOCK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0 ), + .QPLL_QPLLOUTCLK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1 ), + .QPLL_QPLLOUTREFCLK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2 ), + .QPLL_QPLLPD(qpllpd), + .QPLL_QPLLRESET(qrst_qpllreset), + .QRST_DRP_START(qrst_drp_start), + .RST_DCLK_RESET(rst_dclk_reset), + .pipe_dclk_in(pipe_dclk_in), + .sys_clk(sys_clk)); + pcie_7x_0_pcie_7x_0_pipe_rate \pipe_lane[0].pipe_rate.pipe_rate_i + (.QRST_CPLLLOCK(\pipe_lane[0].gt_wrapper_i_n_1 ), + .QRST_QPLLPD_IN(rate_qpllpd[0]), + .QRST_QPLLRESET_IN(rate_qpllreset[0]), + .RATE_DRP_DONE(drp_done_0), + .RATE_DRP_START(rate_drp_start_0), + .RATE_DRP_X16(rate_drp_x16_0), + .RATE_DRP_X16X20_MODE(rate_drp_x16x20_mode_0), + .RATE_PHYSTATUS(gt_phystatus_0), + .RATE_QPLLLOCK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0 ), + .RATE_RXRATEDONE(gt_rxratedone_0), + .RATE_TXRATEDONE(gt_txratedone_0), + .RATE_TXSYNC_DONE(sync_txsync_done_0), + .RST_CPLLRESET(rst_cpllreset), + .RST_IDLE(\pipe_reset.pipe_reset_i_n_1 ), + .RST_TXSYNC_START(rst_txsync_start), + .RXRATE(rate_rate_0), + .RXSYSCLKSEL(rate_sysclksel_0), + .SYNC_RATE_IDLE(rate_idle_0), + .SYNC_RXSYNC_START(rate_rxsync_start_0), + .SYNC_TXSYNC_START(SYNC_TXSYNC_START010_out), + .USER_RATE_DONE(rate_done_0), + .USER_RATE_GEN3(gen3_reg), + .USER_RATE_RXSYNC(rate_rxsync_0), + .USER_RESETOVRD_START(rate_resetovrd_start_0), + .USER_RXRESETDONE(gt_rxresetdone_0), + .USER_TXRESETDONE(gt_txresetdone_0), + .\fsm[0]_i_9_0 (p_1_in2_in), + .out(p_0_in1_in), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_pclk_in(pipe_pclk_in), + .pipe_pclk_sel_out(pipe_pclk_sel_out[0]), + .rate_cpllpd_0(rate_cpllpd_0), + .rate_cpllreset_0(rate_cpllreset_0), + .\rate_in_reg1_reg[0]_0 (\rate_reg1_reg[0] ), + .rate_txpmareset_0(rate_txpmareset_0), + .rxchbonden_0(rxchbonden_0), + .user_active_lane_0(user_active_lane_0)); + pcie_7x_0_pcie_7x_0_pipe_sync \pipe_lane[0].pipe_sync_i + (.\FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 (\pipe_lane[0].pipe_user_i_n_6 ), + .\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 (p_1_in2_in), + .\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 (p_0_in1_in), + .Q({sync_txphalign_0,sync_txphinit_0,sync_txdlysreset_0}), + .RST_CPLLRESET(rst_cpllreset), + .RST_TXSYNC_DONE(sync_txsync_done_0), + .SYNC_RATE_IDLE(rate_idle_0), + .SYNC_RXCDRLOCK(user_rxcdrlock_0), + .SYNC_RXDLYSRESETDONE(rxdlysresetdone_3), + .SYNC_RXPHALIGNDONE_M(\pipe_lane[0].gt_wrapper_i_n_11 ), + .SYNC_RXPHALIGNDONE_S(rxphaligndone_s_3), + .SYNC_RXSYNC_START(rate_rxsync_start_0), + .SYNC_TXDLYSRESETDONE(txdlysresetdone_3), + .SYNC_TXPHALIGNDONE(txsyncallin), + .SYNC_TXPHINITDONE(\pipe_lane[0].pipe_user_i_n_5 ), + .SYNC_TXSYNC_START(SYNC_TXSYNC_START010_out), + .USER_RATE_GEN3(gen3_reg), + .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[0]), + .out(p_1_in), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_pclk_in(pipe_pclk_in), + .sync_txdlyen_0(sync_txdlyen_0), + .txphaligndone_reg3_reg_0(\pipe_lane[0].pipe_sync_i_n_1 ), + .user_active_lane_0(user_active_lane_0)); + pcie_7x_0_pcie_7x_0_pipe_user \pipe_lane[0].pipe_user_i + (.\FSM_onehot_txsync_fsm.fsm_tx_reg[5] (\pipe_lane[0].pipe_sync_i_n_1 ), + .\FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 (p_1_in), + .PIPE_RXSTATUS(PIPE_RXSTATUS[2]), + .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[0]), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE[0]), + .RST_CPLLRESET(rst_cpllreset), + .RST_IDLE(\pipe_reset.pipe_reset_i_n_1 ), + .RST_PHYSTATUS(gt_phystatus_0), + .RST_RESETDONE(user_resetdone[0]), + .RST_RXCDRLOCK(user_rxcdrlock_0), + .RST_RXUSRCLK_RESET(rst_rxusrclk_reset), + .SYNC_TXPHALIGNDONE(txsyncallin), + .SYNC_TXPHINITDONE(\pipe_lane[0].pipe_user_i_n_5 ), + .USER_OOBCLK(user_oobclk_0), + .USER_RATE_DONE(rate_done_0), + .USER_RATE_GEN3(gen3_reg), + .USER_RATE_IDLE(rate_idle_0), + .USER_RATE_RXSYNC(rate_rxsync_0), + .USER_RESETOVRD_START(rate_resetovrd_start_0), + .USER_RXEQ_ADAPT_DONE(\pipe_lane[0].pipe_eq.pipe_eq_i_n_17 ), + .USER_RXRESETDONE(gt_rxresetdone_0), + .USER_TXRESETDONE(gt_txresetdone_0), + .\converge_cnt_reg[15]_0 (\pipe_lane[0].pipe_user_i_n_10 ), + .\converge_cnt_reg[1]_0 (\pipe_lane[0].pipe_user_i_n_11 ), + .\converge_cnt_reg[6]_0 (\pipe_lane[0].pipe_user_i_n_12 ), + .converge_gen3_reg_0(\pipe_lane[0].pipe_user_i_n_15 ), + .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[0]), + .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[0]), + .gt_rxcdrlock_0(gt_rxcdrlock_0), + .gt_rxvalid_0(gt_rxvalid_0), + .gt_rxvalid_q_reg(gt_rxvalid_q_reg), + .out(\pipe_lane[0].pipe_user_i_n_1 ), + .pipe_oobclk_in(pipe_oobclk_in), + .pipe_pclk_in(pipe_pclk_in), + .pipe_pclk_sel_out(pipe_pclk_sel_out[0]), + .pipe_rx0_valid_gt(pipe_rx0_valid_gt), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .txcompliance_reg2_reg_0(p_0_in1_in), + .txelecidle_reg2_reg_0(p_1_in2_in), + .txelecidle_reg2_reg_1(\pipe_lane[0].pipe_user_i_n_6 ), + .txphaligndone_reg1_reg(\pipe_lane[1].gt_wrapper_i_n_16 ), + .txphaligndone_reg1_reg_0(\pipe_lane[0].gt_wrapper_i_n_17 ), + .txphaligndone_reg1_reg_1(\pipe_lane[2].pipe_user_i_n_2 ), + .txphinitdone_reg1_reg(\pipe_lane[1].gt_wrapper_i_n_17 ), + .txphinitdone_reg1_reg_0(\pipe_lane[0].gt_wrapper_i_n_18 ), + .txphinitdone_reg1_reg_1(\pipe_lane[2].pipe_user_i_n_5 ), + .user_active_lane_0(user_active_lane_0), + .user_active_lane_1(user_active_lane_1)); + pcie_7x_0_pcie_7x_0_gt_wrapper_37 \pipe_lane[1].gt_wrapper_i + (.CPLLPD0_3(CPLLPD0_3), + .DRPADDR({\pipe_lane[1].pipe_drp.pipe_drp_i_n_2 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_9 }), + .DRPDI({\pipe_lane[1].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_11 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_12 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_13 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_14 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_25 }), + .DRP_DO({\pipe_lane[1].gt_wrapper_i_n_20 ,\pipe_lane[1].gt_wrapper_i_n_21 ,\pipe_lane[1].gt_wrapper_i_n_22 ,\pipe_lane[1].gt_wrapper_i_n_23 ,\pipe_lane[1].gt_wrapper_i_n_24 ,\pipe_lane[1].gt_wrapper_i_n_25 ,\pipe_lane[1].gt_wrapper_i_n_26 ,\pipe_lane[1].gt_wrapper_i_n_27 ,\pipe_lane[1].gt_wrapper_i_n_28 ,\pipe_lane[1].gt_wrapper_i_n_29 ,\pipe_lane[1].gt_wrapper_i_n_30 ,\pipe_lane[1].gt_wrapper_i_n_31 ,\pipe_lane[1].gt_wrapper_i_n_32 ,\pipe_lane[1].gt_wrapper_i_n_33 ,\pipe_lane[1].gt_wrapper_i_n_34 ,\pipe_lane[1].gt_wrapper_i_n_35 }), + .DRP_GTXRESET(rst_gtreset), + .DRP_RDY(\pipe_lane[1].gt_wrapper_i_n_2 ), + .PIPE_POWERDOWN(PIPE_POWERDOWN[3:2]), + .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[1]), + .PIPE_RXPOLARITY(PIPE_RXPOLARITY[1]), + .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[1]), + .PIPE_TXDATA(PIPE_TXDATA[31:16]), + .PIPE_TXDATAK(PIPE_TXDATAK[3:2]), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE[1]), + .QPLL_QPLLOUTCLK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1 ), + .QPLL_QPLLOUTREFCLK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2 ), + .QRST_CPLLLOCK(\pipe_lane[1].gt_wrapper_i_n_1 ), + .RATE_PHYSTATUS(gt_phystatus_1), + .RATE_RXRATEDONE(gt_rxratedone_1), + .RATE_TXRATEDONE(gt_txratedone_1), + .RST_CPLLRESET(rst_cpllreset), + .RXCHBONDO(\gt_rxchbondi[3]_0 ), + .RXRATE(rate_rate_3), + .RXSYSCLKSEL(rate_sysclksel_2), + .SYNC_TXDLYSRESET(sync_txdlysreset_1), + .SYNC_TXPHALIGN(sync_txphalign_1), + .SYNC_TXPHINIT(sync_txphinit_1), + .TXMAINCURSOR(eq_txeq_maincursor_7), + .TXPOSTCURSOR(eq_txeq_postcursor_5), + .TXPRECURSOR(eq_txeq_precursor_5), + .USER_OOBCLK(user_oobclk_1), + .USER_RXRESETDONE(gt_rxresetdone_1), + .USER_TXRESETDONE(gt_txresetdone_1), + .\cplllock_reg1_reg[1] (\pipe_lane[1].pipe_drp.pipe_drp_i_n_0 ), + .\cplllock_reg1_reg[1]_0 (\pipe_lane[1].pipe_drp.pipe_drp_i_n_1 ), + .\cplllock_reg1_reg[1]_1 (\gtx_channel.gtxe2_channel_i_i_6__2_n_0 ), + .\cplllock_reg1_reg[1]_2 (\cplllock_reg1_reg[3] ), + .cpllpd_0(cpllpd_0), + .gt_cpllpdrefclk(gt_cpllpdrefclk), + .gt_rx_data_k_wire_filter(gt_rx_data_k_wire_filter[3:2]), + .gt_rx_data_wire_filter(gt_rx_data_wire_filter[31:16]), + .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[1]), + .gt_rxcdrlock_1(gt_rxcdrlock_1), + .gt_rxvalid_1(gt_rxvalid_1), + .pci_exp_rxn(pci_exp_rxn[1]), + .pci_exp_rxp(pci_exp_rxp[1]), + .pci_exp_txn(pci_exp_txn[1]), + .pci_exp_txp(pci_exp_txp[1]), + .pipe_dclk_in(pipe_dclk_in), + .pipe_dclk_in_0(\pipe_lane[1].gt_wrapper_i_n_8 ), + .pipe_dclk_in_1(\pipe_lane[1].gt_wrapper_i_n_11 ), + .pipe_dclk_in_2(\pipe_lane[1].gt_wrapper_i_n_15 ), + .pipe_dclk_in_3(\pipe_lane[1].gt_wrapper_i_n_16 ), + .pipe_dclk_in_4(\pipe_lane[1].gt_wrapper_i_n_17 ), + .pipe_dclk_in_5(pipe_dclk_in_0), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rxoutclk_out(pipe_rxoutclk_out[1]), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .pipe_tx_deemph_gt(pipe_tx_deemph_gt), + .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt), + .rate_cpllreset_1(rate_cpllreset_1), + .rate_txpmareset_1(rate_txpmareset_1), + .rst_userrdy(rst_userrdy), + .rxchbonden_1(rxchbonden_1), + .sys_clk(sys_clk)); + pcie_7x_0_pcie_7x_0_pipe_drp_38 \pipe_lane[1].pipe_drp.pipe_drp_i + (.D({\pipe_lane[1].gt_wrapper_i_n_20 ,\pipe_lane[1].gt_wrapper_i_n_21 ,\pipe_lane[1].gt_wrapper_i_n_22 ,\pipe_lane[1].gt_wrapper_i_n_23 ,\pipe_lane[1].gt_wrapper_i_n_24 ,\pipe_lane[1].gt_wrapper_i_n_25 ,\pipe_lane[1].gt_wrapper_i_n_26 ,\pipe_lane[1].gt_wrapper_i_n_27 ,\pipe_lane[1].gt_wrapper_i_n_28 ,\pipe_lane[1].gt_wrapper_i_n_29 ,\pipe_lane[1].gt_wrapper_i_n_30 ,\pipe_lane[1].gt_wrapper_i_n_31 ,\pipe_lane[1].gt_wrapper_i_n_32 ,\pipe_lane[1].gt_wrapper_i_n_33 ,\pipe_lane[1].gt_wrapper_i_n_34 ,\pipe_lane[1].gt_wrapper_i_n_35 }), + .DRPADDR({\pipe_lane[1].pipe_drp.pipe_drp_i_n_2 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_9 }), + .DRPDI({\pipe_lane[1].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_11 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_12 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_13 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_14 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_25 }), + .DRP_DONE(drp_done_1), + .DRP_GTXRESET(rst_gtreset), + .DRP_RDY(\pipe_lane[1].gt_wrapper_i_n_2 ), + .RATE_DRP_START(rate_drp_start_1), + .RATE_DRP_X16(rate_drp_x16_1), + .RATE_DRP_X16X20_MODE(rate_drp_x16x20_mode_1), + .RST_DCLK_RESET(rst_dclk_reset), + .\fsm_reg[1]_0 (\pipe_lane[1].pipe_drp.pipe_drp_i_n_0 ), + .\fsm_reg[1]_1 (\pipe_lane[1].pipe_drp.pipe_drp_i_n_1 ), + .pipe_dclk_in(pipe_dclk_in), + .\rate_reg1_reg[0]_0 (\rate_reg1_reg[0] )); + pcie_7x_0_pcie_7x_0_pipe_eq_39 \pipe_lane[1].pipe_eq.pipe_eq_i + (.RST_CPLLRESET(rst_cpllreset), + .TXMAINCURSOR(eq_txeq_maincursor_7), + .TXPOSTCURSOR(eq_txeq_postcursor_5), + .TXPRECURSOR(eq_txeq_precursor_5), + .USER_RXEQ_ADAPT_DONE(\pipe_lane[1].pipe_eq.pipe_eq_i_n_17 ), + .pipe_pclk_in(pipe_pclk_in), + .rate_gen3_1(rate_gen3_1)); + pcie_7x_0_pcie_7x_0_pipe_rate_40 \pipe_lane[1].pipe_rate.pipe_rate_i + (.QPLL_DRP_GEN3(\pipe_lane[1].pipe_rate.pipe_rate_i_n_1 ), + .QRST_CPLLLOCK(\pipe_lane[1].gt_wrapper_i_n_1 ), + .QRST_QPLLPD_IN(rate_qpllpd[1]), + .QRST_QPLLRESET_IN(rate_qpllreset[1]), + .RATE_DRP_DONE(drp_done_1), + .RATE_DRP_START(rate_drp_start_1), + .RATE_DRP_X16(rate_drp_x16_1), + .RATE_DRP_X16X20_MODE(rate_drp_x16x20_mode_1), + .RATE_PHYSTATUS(gt_phystatus_1), + .RATE_QPLLLOCK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0 ), + .RATE_RXRATEDONE(gt_rxratedone_1), + .RATE_TXRATEDONE(gt_txratedone_1), + .RATE_TXSYNC_DONE(sync_txsync_done_1), + .RST_CPLLRESET(rst_cpllreset), + .RST_IDLE(\pipe_reset.pipe_reset_i_n_1 ), + .RST_TXSYNC_START(rst_txsync_start), + .RXRATE(rate_rate_3), + .RXSYSCLKSEL(rate_sysclksel_2), + .SYNC_RATE_IDLE(rate_idle_1), + .SYNC_RXSYNC_START(rate_rxsync_start_1), + .SYNC_TXSYNC_START(SYNC_TXSYNC_START05_out), + .USER_RATE_DONE(rate_done_1), + .USER_RATE_GEN3(gen3_reg), + .USER_RATE_RXSYNC(rate_rxsync_1), + .USER_RESETOVRD_START(rate_resetovrd_start_1), + .USER_RXRESETDONE(gt_rxresetdone_1), + .USER_TXRESETDONE(gt_txresetdone_1), + .\fsm[0]_i_9__0_0 (p_1_in2_in_1), + .out(p_0_in1_in_0), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_pclk_in(pipe_pclk_in), + .pipe_pclk_sel_out(pipe_pclk_sel_out[1]), + .rate_cpllpd_1(rate_cpllpd_1), + .rate_cpllreset_1(rate_cpllreset_1), + .rate_gen3_1(rate_gen3_1), + .rate_gen3_2(rate_gen3_2), + .rate_gen3_3(rate_gen3_3), + .\rate_in_reg1_reg[0]_0 (\rate_reg1_reg[0] ), + .rate_txpmareset_1(rate_txpmareset_1), + .rxchbonden_1(rxchbonden_1), + .user_active_lane_1(user_active_lane_1)); + pcie_7x_0_pcie_7x_0_pipe_sync_41 \pipe_lane[1].pipe_sync_i + (.\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 (p_0_in1_in_0), + .Q({sync_txphalign_1,sync_txphinit_1,sync_txdlysreset_1}), + .RST_CPLLRESET(rst_cpllreset), + .RST_TXSYNC_DONE(sync_txsync_done_1), + .SYNC_GEN3(rate_gen3_1), + .SYNC_RATE_IDLE(rate_idle_1), + .SYNC_RXCDRLOCK(user_rxcdrlock_1), + .SYNC_RXDLYSRESETDONE(rxdlysresetdone_3), + .SYNC_RXPHALIGNDONE_M(\pipe_lane[0].gt_wrapper_i_n_11 ), + .SYNC_RXPHALIGNDONE_S(rxphaligndone_s_3), + .SYNC_RXSYNC_START(rate_rxsync_start_1), + .SYNC_TXDLYSRESETDONE(txdlysresetdone_3), + .SYNC_TXPHALIGNDONE(txsyncallin), + .SYNC_TXPHINITDONE(\pipe_lane[0].pipe_user_i_n_5 ), + .SYNC_TXSYNC_START(SYNC_TXSYNC_START05_out), + .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[1]), + .out(p_1_in2_in_1), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_pclk_in(pipe_pclk_in), + .user_active_lane_1(user_active_lane_1)); + pcie_7x_0_pcie_7x_0_pipe_user_42 \pipe_lane[1].pipe_user_i + (.PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[1]), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE[1]), + .RST_CPLLRESET(rst_cpllreset), + .RST_IDLE(\pipe_reset.pipe_reset_i_n_1 ), + .RST_PHYSTATUS(gt_phystatus_1), + .RST_RESETDONE(user_resetdone[1]), + .RST_RXCDRLOCK(user_rxcdrlock_1), + .RST_RXUSRCLK_RESET(rst_rxusrclk_reset), + .USER_OOBCLK(user_oobclk_1), + .USER_RATE_DONE(rate_done_1), + .USER_RATE_GEN3(rate_gen3_1), + .USER_RATE_IDLE(rate_idle_1), + .USER_RATE_RXSYNC(rate_rxsync_1), + .USER_RESETOVRD_START(rate_resetovrd_start_1), + .USER_RXEQ_ADAPT_DONE(\pipe_lane[1].pipe_eq.pipe_eq_i_n_17 ), + .USER_RXRESETDONE(gt_rxresetdone_1), + .USER_TXRESETDONE(gt_txresetdone_1), + .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[1]), + .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[1]), + .gt_rxcdrlock_1(gt_rxcdrlock_1), + .gt_rxvalid_1(gt_rxvalid_1), + .gt_rxvalid_q_reg(gt_rxvalid_q_reg_0), + .out(\pipe_lane[1].pipe_user_i_n_1 ), + .pipe_oobclk_in(pipe_oobclk_in), + .pipe_pclk_in(pipe_pclk_in), + .pipe_pclk_sel_out(pipe_pclk_sel_out[1]), + .pipe_rx1_valid_gt(pipe_rx1_valid_gt), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .rxstatus_reg1_reg_0(pipe_dclk_in_0[2]), + .txcompliance_reg2_reg_0(p_0_in1_in_0), + .txelecidle_reg2_reg_0(p_1_in2_in_1), + .user_active_lane_1(user_active_lane_1), + .user_rx_converge(user_rx_converge[1])); + pcie_7x_0_pcie_7x_0_gt_wrapper_43 \pipe_lane[2].gt_wrapper_i + (.CPLLPD0_4(CPLLPD0_4), + .DRPADDR({\pipe_lane[2].pipe_drp.pipe_drp_i_n_2 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_9 }), + .DRPDI({\pipe_lane[2].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_11 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_12 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_13 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_14 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_25 }), + .DRP_DO({\pipe_lane[2].gt_wrapper_i_n_20 ,\pipe_lane[2].gt_wrapper_i_n_21 ,\pipe_lane[2].gt_wrapper_i_n_22 ,\pipe_lane[2].gt_wrapper_i_n_23 ,\pipe_lane[2].gt_wrapper_i_n_24 ,\pipe_lane[2].gt_wrapper_i_n_25 ,\pipe_lane[2].gt_wrapper_i_n_26 ,\pipe_lane[2].gt_wrapper_i_n_27 ,\pipe_lane[2].gt_wrapper_i_n_28 ,\pipe_lane[2].gt_wrapper_i_n_29 ,\pipe_lane[2].gt_wrapper_i_n_30 ,\pipe_lane[2].gt_wrapper_i_n_31 ,\pipe_lane[2].gt_wrapper_i_n_32 ,\pipe_lane[2].gt_wrapper_i_n_33 ,\pipe_lane[2].gt_wrapper_i_n_34 ,\pipe_lane[2].gt_wrapper_i_n_35 }), + .DRP_GTXRESET(rst_gtreset), + .DRP_RDY(\pipe_lane[2].gt_wrapper_i_n_2 ), + .PIPE_POWERDOWN(PIPE_POWERDOWN[5:4]), + .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[2]), + .PIPE_RXPOLARITY(PIPE_RXPOLARITY[2]), + .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[2]), + .PIPE_TXDATA(PIPE_TXDATA[47:32]), + .PIPE_TXDATAK(PIPE_TXDATAK[5:4]), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE[2]), + .QPLL_QPLLOUTCLK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1 ), + .QPLL_QPLLOUTREFCLK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2 ), + .QRST_CPLLLOCK(\pipe_lane[2].gt_wrapper_i_n_1 ), + .RATE_PHYSTATUS(gt_phystatus_2), + .RATE_RXRATEDONE(gt_rxratedone_2), + .RATE_TXRATEDONE(gt_txratedone_2), + .RST_CPLLRESET(rst_cpllreset), + .RXCHBONDO(\gt_rxchbondi[3]_0 ), + .RXRATE(rate_rate_6), + .RXSYSCLKSEL(rate_sysclksel_4), + .SYNC_TXDLYSRESET(sync_txdlysreset_2), + .SYNC_TXPHALIGN(sync_txphalign_2), + .SYNC_TXPHINIT(sync_txphinit_2), + .TXMAINCURSOR(eq_txeq_maincursor_14), + .TXPOSTCURSOR(eq_txeq_postcursor_10), + .TXPRECURSOR(eq_txeq_precursor_10), + .USER_OOBCLK(user_oobclk_2), + .USER_RXRESETDONE(gt_rxresetdone_2), + .USER_TXRESETDONE(gt_txresetdone_2), + .\cplllock_reg1_reg[2] (\pipe_lane[2].pipe_drp.pipe_drp_i_n_0 ), + .\cplllock_reg1_reg[2]_0 (\pipe_lane[2].pipe_drp.pipe_drp_i_n_1 ), + .\cplllock_reg1_reg[2]_1 (\gtx_channel.gtxe2_channel_i_i_6__2_n_0 ), + .\cplllock_reg1_reg[2]_2 (\cplllock_reg1_reg[3] ), + .cpllpd_1(cpllpd_1), + .gt_cpllpdrefclk(gt_cpllpdrefclk), + .gt_rx_data_k_wire_filter(gt_rx_data_k_wire_filter[5:4]), + .gt_rx_data_wire_filter(gt_rx_data_wire_filter[47:32]), + .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[2]), + .gt_rxcdrlock_2(gt_rxcdrlock_2), + .gt_rxvalid_2(gt_rxvalid_2), + .pci_exp_rxn(pci_exp_rxn[2]), + .pci_exp_rxp(pci_exp_rxp[2]), + .pci_exp_txn(pci_exp_txn[2]), + .pci_exp_txp(pci_exp_txp[2]), + .pipe_dclk_in(pipe_dclk_in), + .pipe_dclk_in_0(\pipe_lane[2].gt_wrapper_i_n_8 ), + .pipe_dclk_in_1(\pipe_lane[2].gt_wrapper_i_n_11 ), + .pipe_dclk_in_2(\pipe_lane[2].gt_wrapper_i_n_15 ), + .pipe_dclk_in_3(\pipe_lane[2].gt_wrapper_i_n_16 ), + .pipe_dclk_in_4(\pipe_lane[2].gt_wrapper_i_n_17 ), + .pipe_dclk_in_5(pipe_dclk_in_1), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rxoutclk_out(pipe_rxoutclk_out[2]), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .pipe_tx_deemph_gt(pipe_tx_deemph_gt), + .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt), + .rate_cpllreset_2(rate_cpllreset_2), + .rate_txpmareset_2(rate_txpmareset_2), + .rst_userrdy(rst_userrdy), + .rxchbonden_2(rxchbonden_2), + .sys_clk(sys_clk)); + pcie_7x_0_pcie_7x_0_pipe_drp_44 \pipe_lane[2].pipe_drp.pipe_drp_i + (.D({\pipe_lane[2].gt_wrapper_i_n_20 ,\pipe_lane[2].gt_wrapper_i_n_21 ,\pipe_lane[2].gt_wrapper_i_n_22 ,\pipe_lane[2].gt_wrapper_i_n_23 ,\pipe_lane[2].gt_wrapper_i_n_24 ,\pipe_lane[2].gt_wrapper_i_n_25 ,\pipe_lane[2].gt_wrapper_i_n_26 ,\pipe_lane[2].gt_wrapper_i_n_27 ,\pipe_lane[2].gt_wrapper_i_n_28 ,\pipe_lane[2].gt_wrapper_i_n_29 ,\pipe_lane[2].gt_wrapper_i_n_30 ,\pipe_lane[2].gt_wrapper_i_n_31 ,\pipe_lane[2].gt_wrapper_i_n_32 ,\pipe_lane[2].gt_wrapper_i_n_33 ,\pipe_lane[2].gt_wrapper_i_n_34 ,\pipe_lane[2].gt_wrapper_i_n_35 }), + .DRPADDR({\pipe_lane[2].pipe_drp.pipe_drp_i_n_2 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_9 }), + .DRPDI({\pipe_lane[2].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_11 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_12 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_13 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_14 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_25 }), + .DRP_DONE(drp_done_2), + .DRP_GTXRESET(rst_gtreset), + .DRP_RDY(\pipe_lane[2].gt_wrapper_i_n_2 ), + .RATE_DRP_START(rate_drp_start_2), + .RATE_DRP_X16(rate_drp_x16_2), + .RATE_DRP_X16X20_MODE(rate_drp_x16x20_mode_2), + .RST_DCLK_RESET(rst_dclk_reset), + .\fsm_reg[1]_0 (\pipe_lane[2].pipe_drp.pipe_drp_i_n_0 ), + .\fsm_reg[1]_1 (\pipe_lane[2].pipe_drp.pipe_drp_i_n_1 ), + .pipe_dclk_in(pipe_dclk_in), + .\rate_reg1_reg[0]_0 (\rate_reg1_reg[0] )); + pcie_7x_0_pcie_7x_0_pipe_eq_45 \pipe_lane[2].pipe_eq.pipe_eq_i + (.RST_CPLLRESET(rst_cpllreset), + .TXMAINCURSOR(eq_txeq_maincursor_14), + .TXPOSTCURSOR(eq_txeq_postcursor_10), + .TXPRECURSOR(eq_txeq_precursor_10), + .USER_RXEQ_ADAPT_DONE(\pipe_lane[2].pipe_eq.pipe_eq_i_n_17 ), + .pipe_pclk_in(pipe_pclk_in), + .rate_gen3_2(rate_gen3_2)); + pcie_7x_0_pcie_7x_0_pipe_rate_46 \pipe_lane[2].pipe_rate.pipe_rate_i + (.QRST_CPLLLOCK(\pipe_lane[2].gt_wrapper_i_n_1 ), + .QRST_QPLLPD_IN(rate_qpllpd[2]), + .QRST_QPLLRESET_IN(rate_qpllreset[2]), + .RATE_DRP_DONE(drp_done_2), + .RATE_DRP_START(rate_drp_start_2), + .RATE_DRP_X16(rate_drp_x16_2), + .RATE_DRP_X16X20_MODE(rate_drp_x16x20_mode_2), + .RATE_PHYSTATUS(gt_phystatus_2), + .RATE_QPLLLOCK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0 ), + .RATE_RXRATEDONE(gt_rxratedone_2), + .RATE_TXRATEDONE(gt_txratedone_2), + .RATE_TXSYNC_DONE(sync_txsync_done_2), + .RST_CPLLRESET(rst_cpllreset), + .RST_IDLE(\pipe_reset.pipe_reset_i_n_1 ), + .RST_TXSYNC_START(rst_txsync_start), + .RXRATE(rate_rate_6), + .RXSYSCLKSEL(rate_sysclksel_4), + .SYNC_RATE_IDLE(rate_idle_2), + .SYNC_RXSYNC_START(rate_rxsync_start_2), + .SYNC_TXSYNC_START(SYNC_TXSYNC_START00_out), + .USER_RATE_DONE(rate_done_2), + .USER_RATE_RXSYNC(rate_rxsync_2), + .USER_RESETOVRD_START(rate_resetovrd_start_2), + .USER_RXRESETDONE(gt_rxresetdone_2), + .USER_TXRESETDONE(gt_txresetdone_2), + .\fsm[0]_i_9__1_0 (p_1_in2_in_2), + .out(p_0_in1_in_3), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_pclk_in(pipe_pclk_in), + .pipe_pclk_sel_out(pipe_pclk_sel_out[2]), + .rate_cpllpd_2(rate_cpllpd_2), + .rate_cpllreset_2(rate_cpllreset_2), + .rate_gen3_2(rate_gen3_2), + .\rate_in_reg1_reg[0]_0 (\rate_reg1_reg[0] ), + .rate_txpmareset_2(rate_txpmareset_2), + .rxchbonden_2(rxchbonden_2), + .user_active_lane_2(user_active_lane_2)); + pcie_7x_0_pcie_7x_0_pipe_sync_47 \pipe_lane[2].pipe_sync_i + (.\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 (p_0_in1_in_3), + .Q({sync_txphalign_2,sync_txphinit_2,sync_txdlysreset_2}), + .RST_CPLLRESET(rst_cpllreset), + .RST_TXSYNC_DONE(sync_txsync_done_2), + .SYNC_GEN3(rate_gen3_2), + .SYNC_RATE_IDLE(rate_idle_2), + .SYNC_RXCDRLOCK(user_rxcdrlock_2), + .SYNC_RXDLYSRESETDONE(rxdlysresetdone_3), + .SYNC_RXPHALIGNDONE_M(\pipe_lane[0].gt_wrapper_i_n_11 ), + .SYNC_RXPHALIGNDONE_S(rxphaligndone_s_3), + .SYNC_RXSYNC_START(rate_rxsync_start_2), + .SYNC_TXDLYSRESETDONE(txdlysresetdone_3), + .SYNC_TXPHALIGNDONE(txsyncallin), + .SYNC_TXPHINITDONE(\pipe_lane[0].pipe_user_i_n_5 ), + .SYNC_TXSYNC_START(SYNC_TXSYNC_START00_out), + .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[2]), + .out(p_1_in2_in_2), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_pclk_in(pipe_pclk_in), + .user_active_lane_2(user_active_lane_2)); + pcie_7x_0_pcie_7x_0_pipe_user_48 \pipe_lane[2].pipe_user_i + (.PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[2]), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE[2]), + .RST_CPLLRESET(rst_cpllreset), + .RST_IDLE(\pipe_reset.pipe_reset_i_n_1 ), + .RST_PHYSTATUS(gt_phystatus_2), + .RST_RESETDONE(user_resetdone[2]), + .RST_RXCDRLOCK(user_rxcdrlock_2), + .RST_RXUSRCLK_RESET(rst_rxusrclk_reset), + .USER_OOBCLK(user_oobclk_2), + .USER_RATE_DONE(rate_done_2), + .USER_RATE_IDLE(rate_idle_2), + .USER_RATE_RXSYNC(rate_rxsync_2), + .USER_RESETOVRD_START(rate_resetovrd_start_2), + .USER_RXEQ_ADAPT_DONE(\pipe_lane[2].pipe_eq.pipe_eq_i_n_17 ), + .USER_RXRESETDONE(gt_rxresetdone_2), + .USER_TXRESETDONE(gt_txresetdone_2), + .\converge_cnt_reg[15]_0 (\pipe_lane[2].pipe_user_i_n_9 ), + .\converge_cnt_reg[1]_0 (\pipe_lane[2].pipe_user_i_n_10 ), + .\converge_cnt_reg[6]_0 (\pipe_lane[2].pipe_user_i_n_11 ), + .converge_gen3_reg_0(\pipe_lane[2].pipe_user_i_n_14 ), + .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[2]), + .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[2]), + .gt_rxcdrlock_2(gt_rxcdrlock_2), + .gt_rxvalid_2(gt_rxvalid_2), + .gt_rxvalid_q_reg(gt_rxvalid_q_reg_1), + .out(\pipe_lane[3].pipe_user_i_n_1 ), + .phy_rdy_n_int_reg(\pipe_lane[0].pipe_user_i_n_1 ), + .phy_rdy_n_int_reg_0(\pipe_lane[1].pipe_user_i_n_1 ), + .pipe_oobclk_in(pipe_oobclk_in), + .pipe_pclk_in(pipe_pclk_in), + .pipe_pclk_sel_out(pipe_pclk_sel_out[2]), + .pipe_rx2_valid_gt(pipe_rx2_valid_gt), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .rate_gen3_2(rate_gen3_2), + .reg_clock_locked(reg_clock_locked), + .reg_clock_locked_reg(reg_clock_locked_reg), + .rxstatus_reg1_reg_0(pipe_dclk_in_1[2]), + .txcompliance_reg2_reg_0(\pipe_lane[2].pipe_user_i_n_2 ), + .txcompliance_reg2_reg_1(p_0_in1_in_3), + .txcompliance_reg2_reg_2(\pipe_lane[2].pipe_user_i_n_5 ), + .txelecidle_reg2_reg_0(p_1_in2_in_2), + .txphaligndone_reg1_reg(\pipe_lane[2].gt_wrapper_i_n_16 ), + .txphaligndone_reg1_reg_0(p_0_in1_in_4), + .txphaligndone_reg1_reg_1(p_1_in2_in_5), + .txphaligndone_reg1_reg_2(\pipe_lane[3].gt_wrapper_i_n_16 ), + .txphinitdone_reg1_reg(\pipe_lane[2].gt_wrapper_i_n_17 ), + .txphinitdone_reg1_reg_0(\pipe_lane[3].gt_wrapper_i_n_17 ), + .user_active_lane_2(user_active_lane_2)); + pcie_7x_0_pcie_7x_0_gt_wrapper_49 \pipe_lane[3].gt_wrapper_i + (.CPLLPD0_5(CPLLPD0_5), + .DRPADDR({\pipe_lane[3].pipe_drp.pipe_drp_i_n_2 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_9 }), + .DRPDI({\pipe_lane[3].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_11 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_12 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_13 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_14 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_25 }), + .DRP_DO({\pipe_lane[3].gt_wrapper_i_n_20 ,\pipe_lane[3].gt_wrapper_i_n_21 ,\pipe_lane[3].gt_wrapper_i_n_22 ,\pipe_lane[3].gt_wrapper_i_n_23 ,\pipe_lane[3].gt_wrapper_i_n_24 ,\pipe_lane[3].gt_wrapper_i_n_25 ,\pipe_lane[3].gt_wrapper_i_n_26 ,\pipe_lane[3].gt_wrapper_i_n_27 ,\pipe_lane[3].gt_wrapper_i_n_28 ,\pipe_lane[3].gt_wrapper_i_n_29 ,\pipe_lane[3].gt_wrapper_i_n_30 ,\pipe_lane[3].gt_wrapper_i_n_31 ,\pipe_lane[3].gt_wrapper_i_n_32 ,\pipe_lane[3].gt_wrapper_i_n_33 ,\pipe_lane[3].gt_wrapper_i_n_34 ,\pipe_lane[3].gt_wrapper_i_n_35 }), + .DRP_GTXRESET(rst_gtreset), + .DRP_RDY(\pipe_lane[3].gt_wrapper_i_n_2 ), + .PIPE_POWERDOWN(PIPE_POWERDOWN[7:6]), + .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[3]), + .PIPE_RXPOLARITY(PIPE_RXPOLARITY[3]), + .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[3]), + .PIPE_TXDATA(PIPE_TXDATA[63:48]), + .PIPE_TXDATAK(PIPE_TXDATAK[7:6]), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE[3]), + .QPLL_QPLLOUTCLK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1 ), + .QPLL_QPLLOUTREFCLK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2 ), + .QRST_CPLLLOCK(\pipe_lane[3].gt_wrapper_i_n_1 ), + .RATE_PHYSTATUS(gt_phystatus_3), + .RATE_RXRATEDONE(gt_rxratedone_3), + .RATE_TXRATEDONE(gt_txratedone_3), + .RST_CPLLRESET(rst_cpllreset), + .RXCHBONDO(\gt_rxchbondi[3]_0 ), + .RXRATE(rate_rate_9), + .RXSYSCLKSEL(rate_sysclksel_6), + .SYNC_TXDLYSRESET(sync_txdlysreset_3), + .SYNC_TXPHALIGN(sync_txphalign_3), + .SYNC_TXPHINIT(sync_txphinit_3), + .TXMAINCURSOR(eq_txeq_maincursor_21), + .TXPOSTCURSOR(eq_txeq_postcursor_15), + .TXPRECURSOR(eq_txeq_precursor_15), + .USER_OOBCLK(user_oobclk_3), + .USER_RXRESETDONE(gt_rxresetdone_3), + .USER_TXRESETDONE(gt_txresetdone_3), + .\cplllock_reg1_reg[3] (\pipe_lane[3].pipe_drp.pipe_drp_i_n_0 ), + .\cplllock_reg1_reg[3]_0 (\pipe_lane[3].pipe_drp.pipe_drp_i_n_1 ), + .\cplllock_reg1_reg[3]_1 (\gtx_channel.gtxe2_channel_i_i_6__2_n_0 ), + .\cplllock_reg1_reg[3]_2 (\cplllock_reg1_reg[3] ), + .cpllpd_2(cpllpd_2), + .gt_cpllpdrefclk(gt_cpllpdrefclk), + .gt_rx_data_k_wire_filter(gt_rx_data_k_wire_filter[7:6]), + .gt_rx_data_wire_filter(gt_rx_data_wire_filter[63:48]), + .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[3]), + .gt_rxcdrlock_3(gt_rxcdrlock_3), + .gt_rxvalid_3(gt_rxvalid_3), + .pci_exp_rxn(pci_exp_rxn[3]), + .pci_exp_rxp(pci_exp_rxp[3]), + .pci_exp_txn(pci_exp_txn[3]), + .pci_exp_txp(pci_exp_txp[3]), + .pipe_dclk_in(pipe_dclk_in), + .pipe_dclk_in_0(\pipe_lane[3].gt_wrapper_i_n_8 ), + .pipe_dclk_in_1(\pipe_lane[3].gt_wrapper_i_n_11 ), + .pipe_dclk_in_2(\pipe_lane[3].gt_wrapper_i_n_15 ), + .pipe_dclk_in_3(\pipe_lane[3].gt_wrapper_i_n_16 ), + .pipe_dclk_in_4(\pipe_lane[3].gt_wrapper_i_n_17 ), + .pipe_dclk_in_5(pipe_dclk_in_2), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rxoutclk_out(pipe_rxoutclk_out[3]), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .pipe_tx_deemph_gt(pipe_tx_deemph_gt), + .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt), + .rate_cpllreset_3(rate_cpllreset_3), + .rate_txpmareset_3(rate_txpmareset_3), + .rst_userrdy(rst_userrdy), + .rxchbonden_3(rxchbonden_3), + .sys_clk(sys_clk)); + pcie_7x_0_pcie_7x_0_pipe_drp_50 \pipe_lane[3].pipe_drp.pipe_drp_i + (.D({\pipe_lane[3].gt_wrapper_i_n_20 ,\pipe_lane[3].gt_wrapper_i_n_21 ,\pipe_lane[3].gt_wrapper_i_n_22 ,\pipe_lane[3].gt_wrapper_i_n_23 ,\pipe_lane[3].gt_wrapper_i_n_24 ,\pipe_lane[3].gt_wrapper_i_n_25 ,\pipe_lane[3].gt_wrapper_i_n_26 ,\pipe_lane[3].gt_wrapper_i_n_27 ,\pipe_lane[3].gt_wrapper_i_n_28 ,\pipe_lane[3].gt_wrapper_i_n_29 ,\pipe_lane[3].gt_wrapper_i_n_30 ,\pipe_lane[3].gt_wrapper_i_n_31 ,\pipe_lane[3].gt_wrapper_i_n_32 ,\pipe_lane[3].gt_wrapper_i_n_33 ,\pipe_lane[3].gt_wrapper_i_n_34 ,\pipe_lane[3].gt_wrapper_i_n_35 }), + .DRPADDR({\pipe_lane[3].pipe_drp.pipe_drp_i_n_2 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_9 }), + .DRPDI({\pipe_lane[3].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_11 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_12 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_13 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_14 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_25 }), + .DRP_DONE(drp_done_3), + .DRP_GTXRESET(rst_gtreset), + .DRP_RDY(\pipe_lane[3].gt_wrapper_i_n_2 ), + .RATE_DRP_START(rate_drp_start_3), + .RATE_DRP_X16(rate_drp_x16_3), + .RATE_DRP_X16X20_MODE(rate_drp_x16x20_mode_3), + .RST_DCLK_RESET(rst_dclk_reset), + .\fsm_reg[1]_0 (\pipe_lane[3].pipe_drp.pipe_drp_i_n_0 ), + .\fsm_reg[1]_1 (\pipe_lane[3].pipe_drp.pipe_drp_i_n_1 ), + .pipe_dclk_in(pipe_dclk_in), + .\rate_reg1_reg[0]_0 (\rate_reg1_reg[0] )); + pcie_7x_0_pcie_7x_0_pipe_eq_51 \pipe_lane[3].pipe_eq.pipe_eq_i + (.RST_CPLLRESET(rst_cpllreset), + .TXMAINCURSOR(eq_txeq_maincursor_21), + .TXPOSTCURSOR(eq_txeq_postcursor_15), + .TXPRECURSOR(eq_txeq_precursor_15), + .USER_RXEQ_ADAPT_DONE(\pipe_lane[3].pipe_eq.pipe_eq_i_n_17 ), + .pipe_pclk_in(pipe_pclk_in), + .rate_gen3_3(rate_gen3_3)); + pcie_7x_0_pcie_7x_0_pipe_rate_52 \pipe_lane[3].pipe_rate.pipe_rate_i + (.QPLL_QPLLLOCK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0 ), + .QRST_CPLLLOCK(\pipe_lane[3].gt_wrapper_i_n_1 ), + .QRST_QPLLPD_IN(rate_qpllpd[3]), + .QRST_QPLLRESET_IN(rate_qpllreset[3]), + .RATE_DRP_DONE(drp_done_3), + .RATE_DRP_START(rate_drp_start_3), + .RATE_DRP_X16(rate_drp_x16_3), + .RATE_DRP_X16X20_MODE(rate_drp_x16x20_mode_3), + .RATE_PHYSTATUS(gt_phystatus_3), + .RATE_RXRATEDONE(gt_rxratedone_3), + .RATE_TXRATEDONE(gt_txratedone_3), + .RATE_TXSYNC_DONE(sync_txsync_done_3), + .RST_CPLLRESET(rst_cpllreset), + .RST_IDLE(\pipe_reset.pipe_reset_i_n_1 ), + .RST_TXSYNC_START(rst_txsync_start), + .RXRATE(rate_rate_9), + .RXSYSCLKSEL(rate_sysclksel_6), + .SYNC_RATE_IDLE(rate_idle_3), + .SYNC_RXSYNC_START(rate_rxsync_start_3), + .SYNC_TXSYNC_START(SYNC_TXSYNC_START0), + .USER_RATE_DONE(rate_done_3), + .USER_RATE_RXSYNC(rate_rxsync_3), + .USER_RESETOVRD_START(rate_resetovrd_start_3), + .USER_RXRESETDONE(gt_rxresetdone_3), + .USER_TXRESETDONE(gt_txresetdone_3), + .\fsm[0]_i_9__2_0 (p_1_in2_in_5), + .out(p_0_in1_in_4), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_pclk_in(pipe_pclk_in), + .pipe_pclk_sel_out(pipe_pclk_sel_out[3]), + .rate_cpllpd_3(rate_cpllpd_3), + .rate_cpllreset_3(rate_cpllreset_3), + .rate_gen3_3(rate_gen3_3), + .\rate_in_reg1_reg[0]_0 (\rate_reg1_reg[0] ), + .rate_txpmareset_3(rate_txpmareset_3), + .rxchbonden_3(rxchbonden_3), + .user_active_lane_3(user_active_lane_3)); + pcie_7x_0_pcie_7x_0_pipe_sync_53 \pipe_lane[3].pipe_sync_i + (.\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 (p_0_in1_in_4), + .Q({sync_txphalign_3,sync_txphinit_3,sync_txdlysreset_3}), + .RST_CPLLRESET(rst_cpllreset), + .RST_TXSYNC_DONE(sync_txsync_done_3), + .SYNC_GEN3(rate_gen3_3), + .SYNC_RATE_IDLE(rate_idle_3), + .SYNC_RXCDRLOCK(user_rxcdrlock_3), + .SYNC_RXDLYSRESETDONE(rxdlysresetdone_3), + .SYNC_RXPHALIGNDONE_M(\pipe_lane[0].gt_wrapper_i_n_11 ), + .SYNC_RXPHALIGNDONE_S(rxphaligndone_s_3), + .SYNC_RXSYNC_START(rate_rxsync_start_3), + .SYNC_TXDLYSRESETDONE(txdlysresetdone_3), + .SYNC_TXPHALIGNDONE(txsyncallin), + .SYNC_TXPHINITDONE(\pipe_lane[0].pipe_user_i_n_5 ), + .SYNC_TXSYNC_START(SYNC_TXSYNC_START0), + .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[3]), + .out(p_1_in2_in_5), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_pclk_in(pipe_pclk_in), + .user_active_lane_3(user_active_lane_3)); + pcie_7x_0_pcie_7x_0_pipe_user_54 \pipe_lane[3].pipe_user_i + (.PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[3]), + .PIPE_TXELECIDLE(PIPE_TXELECIDLE[3]), + .RST_CPLLRESET(rst_cpllreset), + .RST_IDLE(\pipe_reset.pipe_reset_i_n_1 ), + .RST_PHYSTATUS(gt_phystatus_3), + .RST_RESETDONE(user_resetdone[3]), + .RST_RXCDRLOCK(user_rxcdrlock_3), + .RST_RXUSRCLK_RESET(rst_rxusrclk_reset), + .USER_OOBCLK(user_oobclk_3), + .USER_RATE_DONE(rate_done_3), + .USER_RATE_IDLE(rate_idle_3), + .USER_RATE_RXSYNC(rate_rxsync_3), + .USER_RESETOVRD_START(rate_resetovrd_start_3), + .USER_RXEQ_ADAPT_DONE(\pipe_lane[3].pipe_eq.pipe_eq_i_n_17 ), + .USER_RXRESETDONE(gt_rxresetdone_3), + .USER_TXRESETDONE(gt_txresetdone_3), + .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[3]), + .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[3]), + .gt_rxcdrlock_3(gt_rxcdrlock_3), + .gt_rxvalid_3(gt_rxvalid_3), + .gt_rxvalid_q_reg(gt_rxvalid_q_reg_2), + .out(\pipe_lane[3].pipe_user_i_n_1 ), + .pipe_oobclk_in(pipe_oobclk_in), + .pipe_pclk_in(pipe_pclk_in), + .pipe_pclk_sel_out(pipe_pclk_sel_out[3]), + .pipe_rx3_valid_gt(pipe_rx3_valid_gt), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .rate_gen3_3(rate_gen3_3), + .rxstatus_reg1_reg_0(pipe_dclk_in_2[2]), + .txcompliance_reg2_reg_0(p_0_in1_in_4), + .txelecidle_reg2_reg_0(p_1_in2_in_5), + .user_active_lane_3(user_active_lane_3), + .user_rx_converge(user_rx_converge[3])); + pcie_7x_0_pcie_7x_0_pipe_reset \pipe_reset.pipe_reset_i + (.D(user_resetdone), + .DRP_GTXRESET(rst_gtreset), + .Q({\pipe_reset.pipe_reset_i_n_1 ,rst_txsync_start}), + .QRST_CPLLLOCK({\pipe_lane[3].gt_wrapper_i_n_1 ,\pipe_lane[2].gt_wrapper_i_n_1 ,\pipe_lane[1].gt_wrapper_i_n_1 ,\pipe_lane[0].gt_wrapper_i_n_1 }), + .QRST_IDLE(\qpll_reset.qpll_reset_i_n_0 ), + .RST_CPLLRESET(rst_cpllreset), + .RST_DCLK_RESET(rst_dclk_reset), + .RST_RXUSRCLK_RESET(rst_rxusrclk_reset), + .SS(\pipe_reset.pipe_reset_i_n_0 ), + .\drp_done_reg1_reg[3]_0 ({drp_done_3,drp_done_2,drp_done_1,drp_done_0}), + .out(reset_n_reg2), + .\phystatus_reg1_reg[3]_0 ({gt_phystatus_3,gt_phystatus_2,gt_phystatus_1,gt_phystatus_0}), + .pipe_dclk_in(pipe_dclk_in), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .\rate_idle_reg1_reg[3]_0 ({rate_idle_3,rate_idle_2,rate_idle_1,rate_idle_0}), + .rst_userrdy(rst_userrdy), + .\rxcdrlock_reg1_reg[3]_0 ({user_rxcdrlock_3,user_rxcdrlock_2,user_rxcdrlock_1,user_rxcdrlock_0}), + .\txsync_done_reg1_reg[3]_0 ({sync_txsync_done_3,sync_txsync_done_2,sync_txsync_done_1,sync_txsync_done_0})); + pcie_7x_0_pcie_7x_0_qpll_reset \qpll_reset.qpll_reset_i + (.D(rate_qpllpd), + .Q({\qpll_reset.qpll_reset_i_n_0 ,qrst_drp_start}), + .QPLL_QPLLLOCK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0 ), + .QPLL_QPLLPD(qpllpd), + .QPLL_QPLLRESET(qrst_qpllreset), + .QRST_DRP_DONE(qdrp_done), + .SS(\pipe_reset.pipe_reset_i_n_0 ), + .\cplllock_reg1_reg[3]_0 ({\pipe_lane[3].gt_wrapper_i_n_1 ,\pipe_lane[2].gt_wrapper_i_n_1 ,\pipe_lane[1].gt_wrapper_i_n_1 ,\pipe_lane[0].gt_wrapper_i_n_1 }), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_pclk_in(pipe_pclk_in), + .\qpllreset_in_reg1_reg[3]_0 (rate_qpllreset), + .\rate_reg1_reg[0]_0 (\rate_reg1_reg[0] )); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDCE reset_n_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .CLR(reset_n_reg1_reg_0), + .D(1'b1), + .Q(reset_n_reg1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDCE reset_n_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .CLR(reset_n_reg1_reg_0), + .D(reset_n_reg1), + .Q(reset_n_reg2)); + LUT4 #( + .INIT(16'h8000)) + rxdlysresetdone_0 + (.I0(\pipe_lane[1].gt_wrapper_i_n_8 ), + .I1(\pipe_lane[0].gt_wrapper_i_n_8 ), + .I2(\pipe_lane[3].gt_wrapper_i_n_8 ), + .I3(\pipe_lane[2].gt_wrapper_i_n_8 ), + .O(rxdlysresetdone_3)); + LUT3 #( + .INIT(8'h80)) + rxphaligndone_s_0 + (.I0(\pipe_lane[1].gt_wrapper_i_n_11 ), + .I1(\pipe_lane[3].gt_wrapper_i_n_11 ), + .I2(\pipe_lane[2].gt_wrapper_i_n_11 ), + .O(rxphaligndone_s_3)); + LUT4 #( + .INIT(16'h8000)) + txdlysresetdone_0 + (.I0(\pipe_lane[1].gt_wrapper_i_n_15 ), + .I1(\pipe_lane[0].gt_wrapper_i_n_15 ), + .I2(\pipe_lane[3].gt_wrapper_i_n_15 ), + .I3(\pipe_lane[2].gt_wrapper_i_n_15 ), + .O(txdlysresetdone_3)); +endmodule + +module pcie_7x_0_pcie_7x_0_qpll_drp + (QPLL_DRP_DONE, + Q, + \di_reg[15]_0 , + qpll_drp_en, + qpll_drp_we, + RST_DCLK_RESET, + QRST_DRP_START, + pipe_dclk_in, + qpll_drp_rdy, + QPLL_QPLLLOCK, + QPLL_DRP_GEN3, + D); + output QPLL_DRP_DONE; + output [4:0]Q; + output [15:0]\di_reg[15]_0 ; + output qpll_drp_en; + output qpll_drp_we; + input RST_DCLK_RESET; + input QRST_DRP_START; + input pipe_dclk_in; + input qpll_drp_rdy; + input QPLL_QPLLLOCK; + input QPLL_DRP_GEN3; + input [15:0]D; + + wire [15:0]D; + wire [4:0]Q; + wire QPLL_DRP_DONE; + wire QPLL_DRP_GEN3; + wire QPLL_QPLLLOCK; + wire QRST_DRP_START; + wire RST_DCLK_RESET; + wire \addr[0]_i_1_n_0 ; + wire \addr[1]_i_1_n_0 ; + wire \addr[2]_i_1_n_0 ; + wire \addr[5]_i_1_n_0 ; + wire \addr[7]_i_1_n_0 ; + wire \crscode_reg_n_0_[0] ; + wire \crscode_reg_n_0_[1] ; + wire \crscode_reg_n_0_[2] ; + wire \crscode_reg_n_0_[3] ; + wire \crscode_reg_n_0_[4] ; + wire \crscode_reg_n_0_[5] ; + wire [15:0]di; + wire \di[11]_i_2_n_0 ; + wire \di[12]_i_2_n_0 ; + wire \di[13]_i_2_n_0 ; + wire \di[14]_i_2_n_0 ; + wire \di[15]_i_2_n_0 ; + wire [15:0]\di_reg[15]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg2; + wire done; + wire \fsm[0]_i_2__1_n_0 ; + wire \fsm[1]_i_2__0_n_0 ; + wire \fsm_inferred__1/i___0_n_0 ; + wire \fsm_inferred__1/i___1_n_0 ; + wire \fsm_inferred__1/i__n_0 ; + wire \fsm_reg_n_0_[0] ; + wire \fsm_reg_n_0_[1] ; + wire \fsm_reg_n_0_[2] ; + wire \fsm_reg_n_0_[3] ; + wire \fsm_reg_n_0_[4] ; + wire \fsm_reg_n_0_[5] ; + wire \fsm_reg_n_0_[6] ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2; + wire \gtx_common.gtxe2_common_i_i_3_n_0 ; + wire \gtx_common.gtxe2_common_i_i_4_n_0 ; + wire index; + wire \index[0]_i_1_n_0 ; + wire \index[1]_i_1_n_0 ; + wire \index[2]_i_1_n_0 ; + wire \index[2]_i_2_n_0 ; + wire \index[2]_i_4_n_0 ; + wire \index_reg_n_0_[0] ; + wire \index_reg_n_0_[1] ; + wire \index_reg_n_0_[2] ; + wire [1:0]load_cnt; + wire \load_cnt[0]_i_1__0_n_0 ; + wire \load_cnt[1]_i_1_n_0 ; + wire \load_cnt[1]_i_2_n_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire ovrd_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire ovrd_reg2; + wire [6:0]p_0_in__0; + wire p_1_in; + wire [5:0]p_2_in; + wire pipe_dclk_in; + wire qpll_drp_en; + wire qpll_drp_rdy; + wire qpll_drp_we; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg2; + + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT3 #( + .INIT(8'h12)) + \addr[0]_i_1 + (.I0(\index_reg_n_0_[1] ), + .I1(\index_reg_n_0_[0] ), + .I2(\index_reg_n_0_[2] ), + .O(\addr[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT3 #( + .INIT(8'h0D)) + \addr[1]_i_1 + (.I0(\index_reg_n_0_[2] ), + .I1(\index_reg_n_0_[0] ), + .I2(\index_reg_n_0_[1] ), + .O(\addr[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT3 #( + .INIT(8'h4D)) + \addr[2]_i_1 + (.I0(\index_reg_n_0_[1] ), + .I1(\index_reg_n_0_[2] ), + .I2(\index_reg_n_0_[0] ), + .O(\addr[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT2 #( + .INIT(4'h7)) + \addr[5]_i_1 + (.I0(\index_reg_n_0_[1] ), + .I1(\index_reg_n_0_[0] ), + .O(\addr[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT3 #( + .INIT(8'h08)) + \addr[7]_i_1 + (.I0(\index_reg_n_0_[1] ), + .I1(\index_reg_n_0_[0] ), + .I2(\index_reg_n_0_[2] ), + .O(\addr[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \addr_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\addr[0]_i_1_n_0 ), + .Q(Q[0]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\addr[1]_i_1_n_0 ), + .Q(Q[1]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\addr[2]_i_1_n_0 ), + .Q(Q[2]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\addr[5]_i_1_n_0 ), + .Q(Q[3]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \addr_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\addr[7]_i_1_n_0 ), + .Q(Q[4]), + .R(RST_DCLK_RESET)); + LUT2 #( + .INIT(4'h2)) + \crscode[0]_i_1 + (.I0(do_reg2[1]), + .I1(\index_reg_n_0_[2] ), + .O(p_2_in[0])); + LUT2 #( + .INIT(4'h2)) + \crscode[1]_i_1 + (.I0(do_reg2[2]), + .I1(\index_reg_n_0_[2] ), + .O(p_2_in[1])); + LUT2 #( + .INIT(4'h2)) + \crscode[2]_i_1 + (.I0(do_reg2[3]), + .I1(\index_reg_n_0_[2] ), + .O(p_2_in[2])); + LUT2 #( + .INIT(4'h2)) + \crscode[3]_i_1 + (.I0(do_reg2[4]), + .I1(\index_reg_n_0_[2] ), + .O(p_2_in[3])); + LUT2 #( + .INIT(4'h2)) + \crscode[4]_i_1 + (.I0(do_reg2[5]), + .I1(\index_reg_n_0_[2] ), + .O(p_2_in[4])); + LUT4 #( + .INIT(16'hC080)) + \crscode[5]_i_1 + (.I0(ovrd_reg2), + .I1(\index_reg_n_0_[0] ), + .I2(\index_reg_n_0_[1] ), + .I3(\index_reg_n_0_[2] ), + .O(p_1_in)); + LUT2 #( + .INIT(4'h2)) + \crscode[5]_i_2 + (.I0(do_reg2[6]), + .I1(\index_reg_n_0_[2] ), + .O(p_2_in[5])); + FDRE #( + .INIT(1'b0)) + \crscode_reg[0] + (.C(pipe_dclk_in), + .CE(p_1_in), + .D(p_2_in[0]), + .Q(\crscode_reg_n_0_[0] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \crscode_reg[1] + (.C(pipe_dclk_in), + .CE(p_1_in), + .D(p_2_in[1]), + .Q(\crscode_reg_n_0_[1] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \crscode_reg[2] + (.C(pipe_dclk_in), + .CE(p_1_in), + .D(p_2_in[2]), + .Q(\crscode_reg_n_0_[2] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \crscode_reg[3] + (.C(pipe_dclk_in), + .CE(p_1_in), + .D(p_2_in[3]), + .Q(\crscode_reg_n_0_[3] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \crscode_reg[4] + (.C(pipe_dclk_in), + .CE(p_1_in), + .D(p_2_in[4]), + .Q(\crscode_reg_n_0_[4] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \crscode_reg[5] + (.C(pipe_dclk_in), + .CE(p_1_in), + .D(p_2_in[5]), + .Q(\crscode_reg_n_0_[5] ), + .R(RST_DCLK_RESET)); + LUT4 #( + .INIT(16'h7E00)) + \di[0]_i_1 + (.I0(\index_reg_n_0_[0] ), + .I1(\index_reg_n_0_[2] ), + .I2(\index_reg_n_0_[1] ), + .I3(do_reg2[0]), + .O(di[0])); + LUT5 #( + .INIT(32'h0CC5CCCC)) + \di[10]_i_1 + (.I0(\crscode_reg_n_0_[0] ), + .I1(do_reg2[10]), + .I2(\index_reg_n_0_[1] ), + .I3(\index_reg_n_0_[0] ), + .I4(\index_reg_n_0_[2] ), + .O(di[10])); + LUT6 #( + .INIT(64'hAAAAAAAAAAAAEBAA)) + \di[11]_i_1 + (.I0(\di[11]_i_2_n_0 ), + .I1(\crscode_reg_n_0_[0] ), + .I2(\crscode_reg_n_0_[1] ), + .I3(\index_reg_n_0_[2] ), + .I4(\index_reg_n_0_[0] ), + .I5(\index_reg_n_0_[1] ), + .O(di[11])); + LUT5 #( + .INIT(32'h20FF2044)) + \di[11]_i_2 + (.I0(\index_reg_n_0_[0] ), + .I1(\index_reg_n_0_[1] ), + .I2(ovrd_reg2), + .I3(\index_reg_n_0_[2] ), + .I4(do_reg2[11]), + .O(\di[11]_i_2_n_0 )); + LUT6 #( + .INIT(64'h00AA0000AAAAC3AA)) + \di[12]_i_1 + (.I0(do_reg2[12]), + .I1(\di[12]_i_2_n_0 ), + .I2(\crscode_reg_n_0_[2] ), + .I3(\index_reg_n_0_[2] ), + .I4(\index_reg_n_0_[0] ), + .I5(\index_reg_n_0_[1] ), + .O(di[12])); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT2 #( + .INIT(4'hE)) + \di[12]_i_2 + (.I0(\crscode_reg_n_0_[0] ), + .I1(\crscode_reg_n_0_[1] ), + .O(\di[12]_i_2_n_0 )); + LUT6 #( + .INIT(64'h00F0F099F0F0FFF0)) + \di[13]_i_1 + (.I0(\crscode_reg_n_0_[3] ), + .I1(\di[13]_i_2_n_0 ), + .I2(do_reg2[13]), + .I3(\index_reg_n_0_[1] ), + .I4(\index_reg_n_0_[0] ), + .I5(\index_reg_n_0_[2] ), + .O(di[13])); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT3 #( + .INIT(8'hFE)) + \di[13]_i_2 + (.I0(\crscode_reg_n_0_[1] ), + .I1(\crscode_reg_n_0_[0] ), + .I2(\crscode_reg_n_0_[2] ), + .O(\di[13]_i_2_n_0 )); + LUT6 #( + .INIT(64'h00F0F099F0F0FFF0)) + \di[14]_i_1 + (.I0(\crscode_reg_n_0_[4] ), + .I1(\di[14]_i_2_n_0 ), + .I2(do_reg2[14]), + .I3(\index_reg_n_0_[1] ), + .I4(\index_reg_n_0_[0] ), + .I5(\index_reg_n_0_[2] ), + .O(di[14])); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT4 #( + .INIT(16'hFFFE)) + \di[14]_i_2 + (.I0(\crscode_reg_n_0_[2] ), + .I1(\crscode_reg_n_0_[0] ), + .I2(\crscode_reg_n_0_[1] ), + .I3(\crscode_reg_n_0_[3] ), + .O(\di[14]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0AACAAAA0AA3AAAA)) + \di[15]_i_1 + (.I0(do_reg2[15]), + .I1(\di[15]_i_2_n_0 ), + .I2(\index_reg_n_0_[1] ), + .I3(\index_reg_n_0_[0] ), + .I4(\index_reg_n_0_[2] ), + .I5(\crscode_reg_n_0_[5] ), + .O(di[15])); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT5 #( + .INIT(32'hFFFFFFFE)) + \di[15]_i_2 + (.I0(\crscode_reg_n_0_[3] ), + .I1(\crscode_reg_n_0_[1] ), + .I2(\crscode_reg_n_0_[0] ), + .I3(\crscode_reg_n_0_[2] ), + .I4(\crscode_reg_n_0_[4] ), + .O(\di[15]_i_2_n_0 )); + LUT4 #( + .INIT(16'h7E00)) + \di[1]_i_1 + (.I0(\index_reg_n_0_[0] ), + .I1(\index_reg_n_0_[2] ), + .I2(\index_reg_n_0_[1] ), + .I3(do_reg2[1]), + .O(di[1])); + LUT4 #( + .INIT(16'h7E00)) + \di[2]_i_1 + (.I0(\index_reg_n_0_[0] ), + .I1(\index_reg_n_0_[2] ), + .I2(\index_reg_n_0_[1] ), + .I3(do_reg2[2]), + .O(di[2])); + LUT4 #( + .INIT(16'h7E00)) + \di[3]_i_1 + (.I0(\index_reg_n_0_[0] ), + .I1(\index_reg_n_0_[2] ), + .I2(\index_reg_n_0_[1] ), + .I3(do_reg2[3]), + .O(di[3])); + LUT4 #( + .INIT(16'h7E00)) + \di[4]_i_1 + (.I0(\index_reg_n_0_[0] ), + .I1(\index_reg_n_0_[2] ), + .I2(\index_reg_n_0_[1] ), + .I3(do_reg2[4]), + .O(di[4])); + LUT4 #( + .INIT(16'h2AAB)) + \di[5]_i_1 + (.I0(do_reg2[5]), + .I1(\index_reg_n_0_[1] ), + .I2(\index_reg_n_0_[0] ), + .I3(\index_reg_n_0_[2] ), + .O(di[5])); + LUT4 #( + .INIT(16'h2BA8)) + \di[6]_i_1 + (.I0(do_reg2[6]), + .I1(\index_reg_n_0_[1] ), + .I2(\index_reg_n_0_[2] ), + .I3(\index_reg_n_0_[0] ), + .O(di[6])); + LUT4 #( + .INIT(16'h7E00)) + \di[7]_i_1 + (.I0(\index_reg_n_0_[0] ), + .I1(\index_reg_n_0_[2] ), + .I2(\index_reg_n_0_[1] ), + .I3(do_reg2[7]), + .O(di[7])); + LUT4 #( + .INIT(16'h2AAB)) + \di[8]_i_1 + (.I0(do_reg2[8]), + .I1(\index_reg_n_0_[1] ), + .I2(\index_reg_n_0_[0] ), + .I3(\index_reg_n_0_[2] ), + .O(di[8])); + LUT4 #( + .INIT(16'h7E00)) + \di[9]_i_1 + (.I0(\index_reg_n_0_[0] ), + .I1(\index_reg_n_0_[2] ), + .I2(\index_reg_n_0_[1] ), + .I3(do_reg2[9]), + .O(di[9])); + FDRE #( + .INIT(1'b0)) + \di_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[0]), + .Q(\di_reg[15]_0 [0]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[10]), + .Q(\di_reg[15]_0 [10]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[11]), + .Q(\di_reg[15]_0 [11]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[12]), + .Q(\di_reg[15]_0 [12]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[13]), + .Q(\di_reg[15]_0 [13]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[14]), + .Q(\di_reg[15]_0 [14]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[15]), + .Q(\di_reg[15]_0 [15]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[1]), + .Q(\di_reg[15]_0 [1]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[2]), + .Q(\di_reg[15]_0 [2]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[3]), + .Q(\di_reg[15]_0 [3]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[4]), + .Q(\di_reg[15]_0 [4]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[5]), + .Q(\di_reg[15]_0 [5]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[6]), + .Q(\di_reg[15]_0 [6]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[7]), + .Q(\di_reg[15]_0 [7]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[8]), + .Q(\di_reg[15]_0 [8]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \di_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(di[9]), + .Q(\di_reg[15]_0 [9]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[0]), + .Q(do_reg1[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[10]), + .Q(do_reg1[10]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[11]), + .Q(do_reg1[11]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[12]), + .Q(do_reg1[12]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[13]), + .Q(do_reg1[13]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[14]), + .Q(do_reg1[14]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[15]), + .Q(do_reg1[15]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[1]), + .Q(do_reg1[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[2]), + .Q(do_reg1[2]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[3]), + .Q(do_reg1[3]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[4]), + .Q(do_reg1[4]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[5]), + .Q(do_reg1[5]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[6]), + .Q(do_reg1[6]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[7]), + .Q(do_reg1[7]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[8]), + .Q(do_reg1[8]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg1_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(D[9]), + .Q(do_reg1[9]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[0]), + .Q(do_reg2[0]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[10] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[10]), + .Q(do_reg2[10]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[11] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[11]), + .Q(do_reg2[11]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[12] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[12]), + .Q(do_reg2[12]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[13] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[13]), + .Q(do_reg2[13]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[14] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[14]), + .Q(do_reg2[14]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[15] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[15]), + .Q(do_reg2[15]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[1]), + .Q(do_reg2[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[2]), + .Q(do_reg2[2]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[3]), + .Q(do_reg2[3]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[4]), + .Q(do_reg2[4]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[5]), + .Q(do_reg2[5]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[6]), + .Q(do_reg2[6]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[7] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[7]), + .Q(do_reg2[7]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[8] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[8]), + .Q(do_reg2[8]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \do_reg2_reg[9] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(do_reg1[9]), + .Q(do_reg2[9]), + .R(RST_DCLK_RESET)); + LUT6 #( + .INIT(64'h0000000000000010)) + done_i_1 + (.I0(\fsm_reg_n_0_[6] ), + .I1(start_reg2), + .I2(\fsm_reg_n_0_[0] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm_reg_n_0_[4] ), + .I5(\gtx_common.gtxe2_common_i_i_4_n_0 ), + .O(done)); + FDRE #( + .INIT(1'b0)) + done_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(done), + .Q(QPLL_DRP_DONE), + .R(RST_DCLK_RESET)); + LUT6 #( + .INIT(64'h5DFF5D5D5D5D5D5D)) + \fsm[0]_i_1__1 + (.I0(\fsm_inferred__1/i___1_n_0 ), + .I1(\fsm_reg_n_0_[0] ), + .I2(start_reg2), + .I3(\fsm[0]_i_2__1_n_0 ), + .I4(\index_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[6] ), + .O(p_0_in__0[0])); + LUT2 #( + .INIT(4'hB)) + \fsm[0]_i_2__1 + (.I0(\index_reg_n_0_[0] ), + .I1(\index_reg_n_0_[2] ), + .O(\fsm[0]_i_2__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT5 #( + .INIT(32'hFFFF7000)) + \fsm[1]_i_1__1 + (.I0(load_cnt[0]), + .I1(load_cnt[1]), + .I2(\fsm_inferred__1/i___1_n_0 ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\fsm[1]_i_2__0_n_0 ), + .O(p_0_in__0[1])); + LUT6 #( + .INIT(64'hFF00B000B000B000)) + \fsm[1]_i_2__0 + (.I0(\fsm[0]_i_2__1_n_0 ), + .I1(\index_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[6] ), + .I3(\fsm_inferred__1/i___1_n_0 ), + .I4(\fsm_reg_n_0_[0] ), + .I5(start_reg2), + .O(\fsm[1]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT4 #( + .INIT(16'h8000)) + \fsm[2]_i_1__0 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_inferred__1/i___1_n_0 ), + .I2(load_cnt[1]), + .I3(load_cnt[0]), + .O(p_0_in__0[2])); + LUT4 #( + .INIT(16'h88C8)) + \fsm[3]_i_1 + (.I0(\fsm_reg_n_0_[2] ), + .I1(\fsm_inferred__1/i___1_n_0 ), + .I2(\fsm_reg_n_0_[3] ), + .I3(rdy_reg2), + .O(p_0_in__0[3])); + LUT3 #( + .INIT(8'h80)) + \fsm[4]_i_1__0 + (.I0(rdy_reg2), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_inferred__1/i___1_n_0 ), + .O(p_0_in__0[4])); + LUT4 #( + .INIT(16'h88C8)) + \fsm[5]_i_1 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_inferred__1/i___1_n_0 ), + .I2(\fsm_reg_n_0_[5] ), + .I3(rdy_reg2), + .O(p_0_in__0[5])); + LUT3 #( + .INIT(8'h80)) + \fsm[6]_i_1 + (.I0(rdy_reg2), + .I1(\fsm_reg_n_0_[5] ), + .I2(\fsm_inferred__1/i___1_n_0 ), + .O(p_0_in__0[6])); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT4 #( + .INIT(16'h0116)) + \fsm_inferred__1/i_ + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .O(\fsm_inferred__1/i__n_0 )); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT4 #( + .INIT(16'hFEE8)) + \fsm_inferred__1/i___0 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[1] ), + .I2(\fsm_reg_n_0_[2] ), + .I3(\fsm_reg_n_0_[3] ), + .O(\fsm_inferred__1/i___0_n_0 )); + LUT5 #( + .INIT(32'h00000116)) + \fsm_inferred__1/i___1 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[5] ), + .I2(\fsm_reg_n_0_[6] ), + .I3(\fsm_inferred__1/i__n_0 ), + .I4(\fsm_inferred__1/i___0_n_0 ), + .O(\fsm_inferred__1/i___1_n_0 )); + (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) + FDSE #( + .INIT(1'b1)) + \fsm_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(p_0_in__0[0]), + .Q(\fsm_reg_n_0_[0] ), + .S(RST_DCLK_RESET)); + (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) + FDRE #( + .INIT(1'b0)) + \fsm_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(p_0_in__0[1]), + .Q(\fsm_reg_n_0_[1] ), + .R(RST_DCLK_RESET)); + (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) + FDRE #( + .INIT(1'b0)) + \fsm_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(p_0_in__0[2]), + .Q(\fsm_reg_n_0_[2] ), + .R(RST_DCLK_RESET)); + (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) + FDRE #( + .INIT(1'b0)) + \fsm_reg[3] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(p_0_in__0[3]), + .Q(\fsm_reg_n_0_[3] ), + .R(RST_DCLK_RESET)); + (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) + FDRE #( + .INIT(1'b0)) + \fsm_reg[4] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(p_0_in__0[4]), + .Q(\fsm_reg_n_0_[4] ), + .R(RST_DCLK_RESET)); + (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) + FDRE #( + .INIT(1'b0)) + \fsm_reg[5] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(p_0_in__0[5]), + .Q(\fsm_reg_n_0_[5] ), + .R(RST_DCLK_RESET)); + (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) + FDRE #( + .INIT(1'b0)) + \fsm_reg[6] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(p_0_in__0[6]), + .Q(\fsm_reg_n_0_[6] ), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(QPLL_DRP_GEN3), + .Q(gen3_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE gen3_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(gen3_reg1), + .Q(gen3_reg2), + .R(RST_DCLK_RESET)); + LUT6 #( + .INIT(64'h0000000000010100)) + \gtx_common.gtxe2_common_i_i_1 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[0] ), + .I2(\fsm_reg_n_0_[6] ), + .I3(\fsm_reg_n_0_[4] ), + .I4(\fsm_reg_n_0_[2] ), + .I5(\gtx_common.gtxe2_common_i_i_3_n_0 ), + .O(qpll_drp_en)); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT5 #( + .INIT(32'h00000010)) + \gtx_common.gtxe2_common_i_i_2 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[6] ), + .I2(\fsm_reg_n_0_[4] ), + .I3(\fsm_reg_n_0_[1] ), + .I4(\gtx_common.gtxe2_common_i_i_4_n_0 ), + .O(qpll_drp_we)); + LUT2 #( + .INIT(4'hE)) + \gtx_common.gtxe2_common_i_i_3 + (.I0(\fsm_reg_n_0_[3] ), + .I1(\fsm_reg_n_0_[5] ), + .O(\gtx_common.gtxe2_common_i_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT3 #( + .INIT(8'hFE)) + \gtx_common.gtxe2_common_i_i_4 + (.I0(\fsm_reg_n_0_[5] ), + .I1(\fsm_reg_n_0_[3] ), + .I2(\fsm_reg_n_0_[2] ), + .O(\gtx_common.gtxe2_common_i_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT5 #( + .INIT(32'h00FF7000)) + \index[0]_i_1 + (.I0(\index_reg_n_0_[1] ), + .I1(\index_reg_n_0_[2] ), + .I2(\index[2]_i_2_n_0 ), + .I3(index), + .I4(\index_reg_n_0_[0] ), + .O(\index[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT5 #( + .INIT(32'h10FFC000)) + \index[1]_i_1 + (.I0(\index_reg_n_0_[2] ), + .I1(\index_reg_n_0_[0] ), + .I2(\index[2]_i_2_n_0 ), + .I3(index), + .I4(\index_reg_n_0_[1] ), + .O(\index[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT5 #( + .INIT(32'h22FF8000)) + \index[2]_i_1 + (.I0(\index[2]_i_2_n_0 ), + .I1(\index_reg_n_0_[1] ), + .I2(\index_reg_n_0_[0] ), + .I3(index), + .I4(\index_reg_n_0_[2] ), + .O(\index[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT5 #( + .INIT(32'h00000004)) + \index[2]_i_2 + (.I0(\fsm_reg_n_0_[1] ), + .I1(\fsm_reg_n_0_[6] ), + .I2(\fsm_reg_n_0_[0] ), + .I3(\gtx_common.gtxe2_common_i_i_4_n_0 ), + .I4(\fsm_reg_n_0_[4] ), + .O(\index[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFEEB)) + \index[2]_i_3 + (.I0(\index[2]_i_4_n_0 ), + .I1(\fsm_reg_n_0_[5] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[1] ), + .I5(\fsm_reg_n_0_[4] ), + .O(index)); + LUT2 #( + .INIT(4'hE)) + \index[2]_i_4 + (.I0(\fsm_reg_n_0_[0] ), + .I1(\fsm_reg_n_0_[6] ), + .O(\index[2]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \index_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\index[0]_i_1_n_0 ), + .Q(\index_reg_n_0_[0] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\index[1]_i_1_n_0 ), + .Q(\index_reg_n_0_[1] ), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \index_reg[2] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\index[2]_i_1_n_0 ), + .Q(\index_reg_n_0_[2] ), + .R(RST_DCLK_RESET)); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT5 #( + .INIT(32'h00B00000)) + \load_cnt[0]_i_1__0 + (.I0(load_cnt[1]), + .I1(load_cnt[0]), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[6] ), + .I4(\load_cnt[1]_i_2_n_0 ), + .O(\load_cnt[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT5 #( + .INIT(32'h00E00000)) + \load_cnt[1]_i_1 + (.I0(load_cnt[0]), + .I1(load_cnt[1]), + .I2(\fsm_reg_n_0_[1] ), + .I3(\fsm_reg_n_0_[6] ), + .I4(\load_cnt[1]_i_2_n_0 ), + .O(\load_cnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT5 #( + .INIT(32'h00000001)) + \load_cnt[1]_i_2 + (.I0(\fsm_reg_n_0_[4] ), + .I1(\fsm_reg_n_0_[5] ), + .I2(\fsm_reg_n_0_[3] ), + .I3(\fsm_reg_n_0_[2] ), + .I4(\fsm_reg_n_0_[0] ), + .O(\load_cnt[1]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \load_cnt_reg[0] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\load_cnt[0]_i_1__0_n_0 ), + .Q(load_cnt[0]), + .R(RST_DCLK_RESET)); + FDRE #( + .INIT(1'b0)) + \load_cnt_reg[1] + (.C(pipe_dclk_in), + .CE(1'b1), + .D(\load_cnt[1]_i_1_n_0 ), + .Q(load_cnt[1]), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE ovrd_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(1'b0), + .Q(ovrd_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE ovrd_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(ovrd_reg1), + .Q(ovrd_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE qplllock_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(QPLL_QPLLLOCK), + .Q(qplllock_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE qplllock_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(qplllock_reg1), + .Q(qplllock_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rdy_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(qpll_drp_rdy), + .Q(rdy_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE rdy_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(rdy_reg1), + .Q(rdy_reg2), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE start_reg1_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(QRST_DRP_START), + .Q(start_reg1), + .R(RST_DCLK_RESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE start_reg2_reg + (.C(pipe_dclk_in), + .CE(1'b1), + .D(start_reg1), + .Q(start_reg2), + .R(RST_DCLK_RESET)); +endmodule + +module pcie_7x_0_pcie_7x_0_qpll_reset + (Q, + QPLL_QPLLRESET, + QPLL_QPLLPD, + SS, + pipe_pclk_in, + D, + \rate_reg1_reg[0]_0 , + QRST_DRP_DONE, + \qpllreset_in_reg1_reg[3]_0 , + QPLL_QPLLLOCK, + \cplllock_reg1_reg[3]_0 , + pipe_mmcm_lock_in); + output [1:0]Q; + output QPLL_QPLLRESET; + output QPLL_QPLLPD; + input [0:0]SS; + input pipe_pclk_in; + input [3:0]D; + input [0:0]\rate_reg1_reg[0]_0 ; + input [0:0]QRST_DRP_DONE; + input [3:0]\qpllreset_in_reg1_reg[3]_0 ; + input QPLL_QPLLLOCK; + input [3:0]\cplllock_reg1_reg[3]_0 ; + input pipe_mmcm_lock_in; + + wire [3:0]D; + wire \FSM_onehot_fsm[0]_i_1__0_n_0 ; + wire \FSM_onehot_fsm[1]_i_1__0_n_0 ; + wire \FSM_onehot_fsm[1]_i_2__0_n_0 ; + wire \FSM_onehot_fsm[2]_i_1__0_n_0 ; + wire \FSM_onehot_fsm[3]_i_1__0_n_0 ; + wire \FSM_onehot_fsm[4]_i_1__0_n_0 ; + wire \FSM_onehot_fsm[5]_i_1__0_n_0 ; + wire \FSM_onehot_fsm_reg_n_0_[0] ; + wire \FSM_onehot_fsm_reg_n_0_[1] ; + wire \FSM_onehot_fsm_reg_n_0_[3] ; + wire \FSM_onehot_fsm_reg_n_0_[4] ; + wire \FSM_onehot_fsm_reg_n_0_[5] ; + wire \FSM_onehot_fsm_reg_n_0_[6] ; + wire [1:0]Q; + wire QPLL_QPLLLOCK; + wire QPLL_QPLLPD; + wire QPLL_QPLLRESET; + wire [0:0]QRST_DRP_DONE; + wire [0:0]SS; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]cplllock_reg1; + wire [3:0]\cplllock_reg1_reg[3]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]cplllock_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg2; + wire fsm2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2; + wire pipe_mmcm_lock_in; + wire pipe_pclk_in; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg2; + wire qpllpd; + wire qpllpd_i_1_n_0; + wire qpllpd_i_2_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]qpllpd_in_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]qpllpd_in_reg2; + wire qpllreset_i_1_n_0; + wire qpllreset_i_2_n_0; + wire qpllreset_i_3_n_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]qpllreset_in_reg1; + wire [3:0]\qpllreset_in_reg1_reg[3]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]qpllreset_in_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_reg1; + wire [0:0]\rate_reg1_reg[0]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_reg2; + + LUT6 #( + .INIT(64'hAAAAAAAAAAAAAAA8)) + \FSM_onehot_fsm[0]_i_1__0 + (.I0(\FSM_onehot_fsm_reg_n_0_[0] ), + .I1(qplllock_reg2), + .I2(cplllock_reg2[1]), + .I3(cplllock_reg2[0]), + .I4(cplllock_reg2[3]), + .I5(cplllock_reg2[2]), + .O(\FSM_onehot_fsm[0]_i_1__0_n_0 )); + LUT4 #( + .INIT(16'h8F88)) + \FSM_onehot_fsm[1]_i_1__0 + (.I0(\FSM_onehot_fsm[1]_i_2__0_n_0 ), + .I1(\FSM_onehot_fsm_reg_n_0_[0] ), + .I2(fsm2), + .I3(\FSM_onehot_fsm_reg_n_0_[1] ), + .O(\FSM_onehot_fsm[1]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'h00000001)) + \FSM_onehot_fsm[1]_i_2__0 + (.I0(cplllock_reg2[2]), + .I1(cplllock_reg2[3]), + .I2(cplllock_reg2[0]), + .I3(cplllock_reg2[1]), + .I4(qplllock_reg2), + .O(\FSM_onehot_fsm[1]_i_2__0_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \FSM_onehot_fsm[2]_i_1__0 + (.I0(fsm2), + .I1(\FSM_onehot_fsm_reg_n_0_[1] ), + .I2(drp_done_reg2), + .I3(Q[0]), + .O(\FSM_onehot_fsm[2]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'h80000000)) + \FSM_onehot_fsm[2]_i_2__0 + (.I0(mmcm_lock_reg2), + .I1(cplllock_reg2[2]), + .I2(cplllock_reg2[3]), + .I3(cplllock_reg2[0]), + .I4(cplllock_reg2[1]), + .O(fsm2)); + LUT3 #( + .INIT(8'h32)) + \FSM_onehot_fsm[3]_i_1__0 + (.I0(Q[0]), + .I1(drp_done_reg2), + .I2(\FSM_onehot_fsm_reg_n_0_[3] ), + .O(\FSM_onehot_fsm[3]_i_1__0_n_0 )); + LUT4 #( + .INIT(16'h8F88)) + \FSM_onehot_fsm[4]_i_1__0 + (.I0(drp_done_reg2), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(qplllock_reg2), + .I3(\FSM_onehot_fsm_reg_n_0_[4] ), + .O(\FSM_onehot_fsm[4]_i_1__0_n_0 )); + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_fsm[5]_i_1__0 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(qplllock_reg2), + .O(\FSM_onehot_fsm[5]_i_1__0_n_0 )); + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_fsm[7]_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[6] ), + .I1(Q[1]), + .O(qpllpd)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000" *) + FDSE #( + .INIT(1'b1)) + \FSM_onehot_fsm_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[0]_i_1__0_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[0] ), + .S(SS)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[1]_i_1__0_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[1] ), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[2]_i_1__0_n_0 ), + .Q(Q[0]), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[3]_i_1__0_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[3] ), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[4]_i_1__0_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[4] ), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[5]_i_1__0_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[5] ), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm_reg_n_0_[5] ), + .Q(\FSM_onehot_fsm_reg_n_0_[6] ), + .R(SS)); + (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllpd), + .Q(Q[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \cplllock_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\cplllock_reg1_reg[3]_0 [0]), + .Q(cplllock_reg1[0]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \cplllock_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\cplllock_reg1_reg[3]_0 [1]), + .Q(cplllock_reg1[1]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \cplllock_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\cplllock_reg1_reg[3]_0 [2]), + .Q(cplllock_reg1[2]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \cplllock_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\cplllock_reg1_reg[3]_0 [3]), + .Q(cplllock_reg1[3]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \cplllock_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cplllock_reg1[0]), + .Q(cplllock_reg2[0]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \cplllock_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cplllock_reg1[1]), + .Q(cplllock_reg2[1]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \cplllock_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cplllock_reg1[2]), + .Q(cplllock_reg2[2]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \cplllock_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(cplllock_reg1[3]), + .Q(cplllock_reg2[3]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \drp_done_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(QRST_DRP_DONE), + .Q(drp_done_reg1), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \drp_done_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(drp_done_reg1), + .Q(drp_done_reg2), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(pipe_mmcm_lock_in), + .Q(mmcm_lock_reg1), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE mmcm_lock_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(mmcm_lock_reg1), + .Q(mmcm_lock_reg2), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \qplllock_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(QPLL_QPLLLOCK), + .Q(qplllock_reg1), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \qplllock_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qplllock_reg1), + .Q(qplllock_reg2), + .R(SS)); + LUT6 #( + .INIT(64'hFBF0FBFFFBF0FB00)) + qpllpd_i_1 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .I2(qpllpd_i_2_n_0), + .I3(\FSM_onehot_fsm_reg_n_0_[6] ), + .I4(Q[1]), + .I5(QPLL_QPLLPD), + .O(qpllpd_i_1_n_0)); + LUT5 #( + .INIT(32'h80000000)) + qpllpd_i_2 + (.I0(Q[1]), + .I1(qpllpd_in_reg2[2]), + .I2(qpllpd_in_reg2[3]), + .I3(qpllpd_in_reg2[0]), + .I4(qpllpd_in_reg2[1]), + .O(qpllpd_i_2_n_0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \qpllpd_in_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(D[0]), + .Q(qpllpd_in_reg1[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \qpllpd_in_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(D[1]), + .Q(qpllpd_in_reg1[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \qpllpd_in_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(D[2]), + .Q(qpllpd_in_reg1[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \qpllpd_in_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(D[3]), + .Q(qpllpd_in_reg1[3]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \qpllpd_in_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllpd_in_reg1[0]), + .Q(qpllpd_in_reg2[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \qpllpd_in_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllpd_in_reg1[1]), + .Q(qpllpd_in_reg2[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \qpllpd_in_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllpd_in_reg1[2]), + .Q(qpllpd_in_reg2[2]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \qpllpd_in_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllpd_in_reg1[3]), + .Q(qpllpd_in_reg2[3]), + .R(SS)); + FDRE #( + .INIT(1'b0)) + qpllpd_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllpd_i_1_n_0), + .Q(QPLL_QPLLPD), + .R(SS)); + LUT6 #( + .INIT(64'hECECECEFECECECE0)) + qpllreset_i_1 + (.I0(qpllreset_i_2_n_0), + .I1(qpllreset_i_3_n_0), + .I2(\FSM_onehot_fsm_reg_n_0_[5] ), + .I3(\FSM_onehot_fsm_reg_n_0_[4] ), + .I4(Q[1]), + .I5(QPLL_QPLLRESET), + .O(qpllreset_i_1_n_0)); + LUT2 #( + .INIT(4'hB)) + qpllreset_i_2 + (.I0(rate_reg2[0]), + .I1(rate_reg2[1]), + .O(qpllreset_i_2_n_0)); + LUT5 #( + .INIT(32'h80000000)) + qpllreset_i_3 + (.I0(Q[1]), + .I1(qpllreset_in_reg2[2]), + .I2(qpllreset_in_reg2[3]), + .I3(qpllreset_in_reg2[0]), + .I4(qpllreset_in_reg2[1]), + .O(qpllreset_i_3_n_0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \qpllreset_in_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\qpllreset_in_reg1_reg[3]_0 [0]), + .Q(qpllreset_in_reg1[0]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \qpllreset_in_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\qpllreset_in_reg1_reg[3]_0 [1]), + .Q(qpllreset_in_reg1[1]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \qpllreset_in_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\qpllreset_in_reg1_reg[3]_0 [2]), + .Q(qpllreset_in_reg1[2]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \qpllreset_in_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\qpllreset_in_reg1_reg[3]_0 [3]), + .Q(qpllreset_in_reg1[3]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \qpllreset_in_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllreset_in_reg1[0]), + .Q(qpllreset_in_reg2[0]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \qpllreset_in_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllreset_in_reg1[1]), + .Q(qpllreset_in_reg2[1]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \qpllreset_in_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllreset_in_reg1[2]), + .Q(qpllreset_in_reg2[2]), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDSE \qpllreset_in_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllreset_in_reg1[3]), + .Q(qpllreset_in_reg2[3]), + .S(SS)); + FDSE #( + .INIT(1'b1)) + qpllreset_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(qpllreset_i_1_n_0), + .Q(QPLL_QPLLRESET), + .S(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\rate_reg1_reg[0]_0 ), + .Q(rate_reg1[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(1'b0), + .Q(rate_reg1[1]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_reg1[0]), + .Q(rate_reg2[0]), + .R(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \rate_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rate_reg1[1]), + .Q(rate_reg2[1]), + .R(SS)); +endmodule + +module pcie_7x_0_pcie_7x_0_qpll_wrapper + (qpll_drp_rdy, + QPLL_QPLLLOCK, + QPLL_QPLLOUTCLK, + QPLL_QPLLOUTREFCLK, + D, + pipe_dclk_in, + qpll_drp_en, + qpll_drp_we, + sys_clk, + QPLL_QPLLPD, + QPLL_QPLLRESET, + rdy_reg1_reg, + Q); + output qpll_drp_rdy; + output QPLL_QPLLLOCK; + output QPLL_QPLLOUTCLK; + output QPLL_QPLLOUTREFCLK; + output [15:0]D; + input pipe_dclk_in; + input qpll_drp_en; + input qpll_drp_we; + input sys_clk; + input QPLL_QPLLPD; + input QPLL_QPLLRESET; + input [15:0]rdy_reg1_reg; + input [4:0]Q; + + wire [15:0]D; + wire [4:0]Q; + wire QPLL_QPLLLOCK; + wire QPLL_QPLLOUTCLK; + wire QPLL_QPLLOUTREFCLK; + wire QPLL_QPLLPD; + wire QPLL_QPLLRESET; + wire pipe_dclk_in; + wire qpll_drp_en; + wire qpll_drp_rdy; + wire qpll_drp_we; + wire [15:0]rdy_reg1_reg; + wire sys_clk; + wire \NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED ; + wire \NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED ; + wire \NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED ; + wire [7:0]\NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED ; + + (* BOX_TYPE = "PRIMITIVE" *) + GTXE2_COMMON #( + .BIAS_CFG(64'h0000040000001000), + .COMMON_CFG(32'h00000000), + .IS_DRPCLK_INVERTED(1'b0), + .IS_GTGREFCLK_INVERTED(1'b0), + .IS_QPLLLOCKDETCLK_INVERTED(1'b0), + .QPLL_CFG(27'h06801C1), + .QPLL_CLKOUT_CFG(4'b0000), + .QPLL_COARSE_FREQ_OVRD(6'b010000), + .QPLL_COARSE_FREQ_OVRD_EN(1'b0), + .QPLL_CP(10'b0000011111), + .QPLL_CP_MONITOR_EN(1'b0), + .QPLL_DMONITOR_SEL(1'b0), + .QPLL_FBDIV(10'b0100100000), + .QPLL_FBDIV_MONITOR_EN(1'b0), + .QPLL_FBDIV_RATIO(1'b1), + .QPLL_INIT_CFG(24'h000006), + .QPLL_LOCK_CFG(16'h21E8), + .QPLL_LPF(4'b1101), + .QPLL_REFCLK_DIV(1), + .SIM_QPLLREFCLK_SEL(3'b001), + .SIM_RESET_SPEEDUP("FALSE"), + .SIM_VERSION("3.0")) + \gtx_common.gtxe2_common_i + (.BGBYPASSB(1'b1), + .BGMONITORENB(1'b1), + .BGPDB(1'b1), + .BGRCALOVRD({1'b1,1'b1,1'b1,1'b1,1'b1}), + .DRPADDR({Q[4],1'b0,Q[3],Q[3],Q[4],Q[2:0]}), + .DRPCLK(pipe_dclk_in), + .DRPDI(rdy_reg1_reg), + .DRPDO(D), + .DRPEN(qpll_drp_en), + .DRPRDY(qpll_drp_rdy), + .DRPWE(qpll_drp_we), + .GTGREFCLK(1'b0), + .GTNORTHREFCLK0(1'b0), + .GTNORTHREFCLK1(1'b0), + .GTREFCLK0(sys_clk), + .GTREFCLK1(1'b0), + .GTSOUTHREFCLK0(1'b0), + .GTSOUTHREFCLK1(1'b0), + .PMARSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .QPLLDMONITOR(\NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED [7:0]), + .QPLLFBCLKLOST(\NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED ), + .QPLLLOCK(QPLL_QPLLLOCK), + .QPLLLOCKDETCLK(1'b0), + .QPLLLOCKEN(1'b1), + .QPLLOUTCLK(QPLL_QPLLOUTCLK), + .QPLLOUTREFCLK(QPLL_QPLLOUTREFCLK), + .QPLLOUTRESET(1'b0), + .QPLLPD(QPLL_QPLLPD), + .QPLLREFCLKLOST(\NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED ), + .QPLLREFCLKSEL({1'b0,1'b0,1'b1}), + .QPLLRESET(QPLL_QPLLRESET), + .QPLLRSVD1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .QPLLRSVD2({1'b1,1'b1,1'b1,1'b1,1'b1}), + .RCALENB(1'b1), + .REFCLKOUTMONITOR(\NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED )); +endmodule + +module pcie_7x_0_pcie_7x_0_rxeq_scan + (D, + rxeq_new_txcoeff_req, + adapt_done_reg_0, + new_txcoeff_done_reg_0, + RST_CPLLRESET, + pipe_pclk_in, + new_txcoeff_req_reg1_reg_0, + rxeq_preset_valid, + out, + Q, + \FSM_onehot_fsm_rx_reg[5] , + rxeq_adapt_done_reg_reg, + rxeq_adapt_done_reg_reg_0, + rxeq_adapt_done_reg_reg_1, + rxeq_adapt_done_reg, + USER_RXEQ_ADAPT_DONE, + \preset_reg1_reg[2]_0 , + \txpreset_reg1_reg[3]_0 , + \txcoeff_reg1_reg[17]_0 , + \fs_reg1_reg[5]_0 , + \lf_reg1_reg[5]_0 ); + output [2:0]D; + output rxeq_new_txcoeff_req; + output adapt_done_reg_0; + output new_txcoeff_done_reg_0; + input RST_CPLLRESET; + input pipe_pclk_in; + input new_txcoeff_req_reg1_reg_0; + input rxeq_preset_valid; + input [1:0]out; + input [4:0]Q; + input [2:0]\FSM_onehot_fsm_rx_reg[5] ; + input rxeq_adapt_done_reg_reg; + input rxeq_adapt_done_reg_reg_0; + input rxeq_adapt_done_reg_reg_1; + input rxeq_adapt_done_reg; + input USER_RXEQ_ADAPT_DONE; + input [2:0]\preset_reg1_reg[2]_0 ; + input [3:0]\txpreset_reg1_reg[3]_0 ; + input [17:0]\txcoeff_reg1_reg[17]_0 ; + input [5:0]\fs_reg1_reg[5]_0 ; + input [5:0]\lf_reg1_reg[5]_0 ; + + wire [2:0]D; + wire \FSM_onehot_fsm[1]_i_1__4_n_0 ; + wire \FSM_onehot_fsm[2]_i_1__4_n_0 ; + wire \FSM_onehot_fsm[3]_i_1__4_n_0 ; + wire \FSM_onehot_fsm[3]_i_2__2_n_0 ; + wire \FSM_onehot_fsm[4]_i_10__2_n_0 ; + wire \FSM_onehot_fsm[4]_i_11__2_n_0 ; + wire \FSM_onehot_fsm[4]_i_12__2_n_0 ; + wire \FSM_onehot_fsm[4]_i_13__2_n_0 ; + wire \FSM_onehot_fsm[4]_i_1__4_n_0 ; + wire \FSM_onehot_fsm[4]_i_2__3_n_0 ; + wire \FSM_onehot_fsm[4]_i_3__2_n_0 ; + wire \FSM_onehot_fsm[4]_i_4__2_n_0 ; + wire \FSM_onehot_fsm[4]_i_5__2_n_0 ; + wire \FSM_onehot_fsm[4]_i_6__2_n_0 ; + wire \FSM_onehot_fsm[4]_i_7__2_n_0 ; + wire \FSM_onehot_fsm[4]_i_8__2_n_0 ; + wire \FSM_onehot_fsm[4]_i_9__2_n_0 ; + wire \FSM_onehot_fsm_reg_n_0_[1] ; + wire \FSM_onehot_fsm_reg_n_0_[2] ; + wire \FSM_onehot_fsm_reg_n_0_[3] ; + wire \FSM_onehot_fsm_reg_n_0_[4] ; + wire \FSM_onehot_fsm_rx[6]_i_2__2_n_0 ; + wire [2:0]\FSM_onehot_fsm_rx_reg[5] ; + wire [4:0]Q; + wire RST_CPLLRESET; + wire USER_RXEQ_ADAPT_DONE; + wire adapt_done; + wire adapt_done_cnt_i_1__2_n_0; + wire adapt_done_cnt_i_2__2_n_0; + wire adapt_done_cnt_reg_n_0; + wire adapt_done_reg_0; + wire [21:0]converge_cnt; + wire [21:1]converge_cnt0; + wire [21:0]converge_cnt_0; + wire \converge_cnt_reg[12]_i_2__2_n_0 ; + wire \converge_cnt_reg[12]_i_2__2_n_1 ; + wire \converge_cnt_reg[12]_i_2__2_n_2 ; + wire \converge_cnt_reg[12]_i_2__2_n_3 ; + wire \converge_cnt_reg[16]_i_2__2_n_0 ; + wire \converge_cnt_reg[16]_i_2__2_n_1 ; + wire \converge_cnt_reg[16]_i_2__2_n_2 ; + wire \converge_cnt_reg[16]_i_2__2_n_3 ; + wire \converge_cnt_reg[20]_i_2__2_n_0 ; + wire \converge_cnt_reg[20]_i_2__2_n_1 ; + wire \converge_cnt_reg[20]_i_2__2_n_2 ; + wire \converge_cnt_reg[20]_i_2__2_n_3 ; + wire \converge_cnt_reg[4]_i_2__2_n_0 ; + wire \converge_cnt_reg[4]_i_2__2_n_1 ; + wire \converge_cnt_reg[4]_i_2__2_n_2 ; + wire \converge_cnt_reg[4]_i_2__2_n_3 ; + wire \converge_cnt_reg[8]_i_2__2_n_0 ; + wire \converge_cnt_reg[8]_i_2__2_n_1 ; + wire \converge_cnt_reg[8]_i_2__2_n_2 ; + wire \converge_cnt_reg[8]_i_2__2_n_3 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]fs_reg1; + wire [5:0]\fs_reg1_reg[5]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]fs_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]lf_reg1; + wire [5:0]\lf_reg1_reg[5]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]lf_reg2; + wire new_txcoeff_done; + wire new_txcoeff_done_reg_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire new_txcoeff_req_reg1; + wire new_txcoeff_req_reg1_reg_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire new_txcoeff_req_reg2; + wire [1:0]out; + wire pipe_pclk_in; + wire preset_done; + wire preset_done_1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]preset_reg1; + wire [2:0]\preset_reg1_reg[2]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]preset_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire preset_valid_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire preset_valid_reg2; + wire rxeq_adapt_done_reg; + wire rxeq_adapt_done_reg_reg; + wire rxeq_adapt_done_reg_reg_0; + wire rxeq_adapt_done_reg_reg_1; + wire rxeq_new_txcoeff_req; + wire rxeq_preset_valid; + wire rxeqscan_adapt_done; + wire rxeqscan_new_txcoeff_done; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]txcoeff_reg1; + wire [17:0]\txcoeff_reg1_reg[17]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]txcoeff_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txpreset_reg1; + wire [3:0]\txpreset_reg1_reg[3]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txpreset_reg2; + wire [3:0]\NLW_converge_cnt_reg[21]_i_2__2_CO_UNCONNECTED ; + wire [3:1]\NLW_converge_cnt_reg[21]_i_2__2_O_UNCONNECTED ; + + LUT6 #( + .INIT(64'h0F00AFAF0F11AFBB)) + \FSM_onehot_fsm[1]_i_1__4 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(preset_valid_reg2), + .I3(\FSM_onehot_fsm_reg_n_0_[2] ), + .I4(new_txcoeff_req_reg2), + .I5(\FSM_onehot_fsm_reg_n_0_[1] ), + .O(\FSM_onehot_fsm[1]_i_1__4_n_0 )); + LUT3 #( + .INIT(8'hA8)) + \FSM_onehot_fsm[2]_i_1__4 + (.I0(preset_valid_reg2), + .I1(\FSM_onehot_fsm_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_reg_n_0_[1] ), + .O(\FSM_onehot_fsm[2]_i_1__4_n_0 )); + LUT6 #( + .INIT(64'h04FF040404040404)) + \FSM_onehot_fsm[3]_i_1__4 + (.I0(\FSM_onehot_fsm[3]_i_2__2_n_0 ), + .I1(\FSM_onehot_fsm[4]_i_2__3_n_0 ), + .I2(\FSM_onehot_fsm[4]_i_3__2_n_0 ), + .I3(preset_valid_reg2), + .I4(new_txcoeff_req_reg2), + .I5(\FSM_onehot_fsm_reg_n_0_[1] ), + .O(\FSM_onehot_fsm[3]_i_1__4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair181" *) + LUT4 #( + .INIT(16'h04FF)) + \FSM_onehot_fsm[3]_i_2__2 + (.I0(out[0]), + .I1(out[1]), + .I2(adapt_done_cnt_reg_n_0), + .I3(\FSM_onehot_fsm_reg_n_0_[3] ), + .O(\FSM_onehot_fsm[3]_i_2__2_n_0 )); + LUT5 #( + .INIT(32'hFFBFFFFF)) + \FSM_onehot_fsm[4]_i_10__2 + (.I0(\FSM_onehot_fsm[4]_i_13__2_n_0 ), + .I1(converge_cnt[2]), + .I2(converge_cnt[20]), + .I3(converge_cnt[10]), + .I4(converge_cnt[0]), + .O(\FSM_onehot_fsm[4]_i_10__2_n_0 )); + LUT4 #( + .INIT(16'hEFFF)) + \FSM_onehot_fsm[4]_i_11__2 + (.I0(converge_cnt[2]), + .I1(converge_cnt[6]), + .I2(converge_cnt[8]), + .I3(converge_cnt[3]), + .O(\FSM_onehot_fsm[4]_i_11__2_n_0 )); + LUT5 #( + .INIT(32'hEFFFFFFF)) + \FSM_onehot_fsm[4]_i_12__2 + (.I0(\FSM_onehot_fsm[4]_i_13__2_n_0 ), + .I1(converge_cnt[14]), + .I2(converge_cnt[10]), + .I3(converge_cnt[21]), + .I4(converge_cnt[19]), + .O(\FSM_onehot_fsm[4]_i_12__2_n_0 )); + LUT4 #( + .INIT(16'hFF7F)) + \FSM_onehot_fsm[4]_i_13__2 + (.I0(converge_cnt[16]), + .I1(converge_cnt[11]), + .I2(converge_cnt[9]), + .I3(converge_cnt[5]), + .O(\FSM_onehot_fsm[4]_i_13__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFD0FFD0FFD0)) + \FSM_onehot_fsm[4]_i_1__4 + (.I0(\FSM_onehot_fsm[4]_i_2__3_n_0 ), + .I1(\FSM_onehot_fsm[4]_i_3__2_n_0 ), + .I2(\FSM_onehot_fsm_reg_n_0_[3] ), + .I3(\FSM_onehot_fsm[4]_i_4__2_n_0 ), + .I4(\FSM_onehot_fsm_reg_n_0_[4] ), + .I5(new_txcoeff_req_reg2), + .O(\FSM_onehot_fsm[4]_i_1__4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFBF)) + \FSM_onehot_fsm[4]_i_2__3 + (.I0(\FSM_onehot_fsm[4]_i_5__2_n_0 ), + .I1(converge_cnt[17]), + .I2(converge_cnt[18]), + .I3(converge_cnt[21]), + .I4(converge_cnt[8]), + .I5(\FSM_onehot_fsm[4]_i_6__2_n_0 ), + .O(\FSM_onehot_fsm[4]_i_2__3_n_0 )); + LUT6 #( + .INIT(64'h0000000001000000)) + \FSM_onehot_fsm[4]_i_3__2 + (.I0(\FSM_onehot_fsm[4]_i_7__2_n_0 ), + .I1(converge_cnt[7]), + .I2(converge_cnt[1]), + .I3(converge_cnt[15]), + .I4(converge_cnt[13]), + .I5(\FSM_onehot_fsm[4]_i_8__2_n_0 ), + .O(\FSM_onehot_fsm[4]_i_3__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair180" *) + LUT4 #( + .INIT(16'h0400)) + \FSM_onehot_fsm[4]_i_4__2 + (.I0(out[0]), + .I1(out[1]), + .I2(adapt_done_cnt_reg_n_0), + .I3(\FSM_onehot_fsm_reg_n_0_[3] ), + .O(\FSM_onehot_fsm[4]_i_4__2_n_0 )); + LUT4 #( + .INIT(16'hFFF2)) + \FSM_onehot_fsm[4]_i_5__2 + (.I0(out[1]), + .I1(out[0]), + .I2(converge_cnt[7]), + .I3(converge_cnt[1]), + .O(\FSM_onehot_fsm[4]_i_5__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFB)) + \FSM_onehot_fsm[4]_i_6__2 + (.I0(\FSM_onehot_fsm[4]_i_9__2_n_0 ), + .I1(converge_cnt[19]), + .I2(converge_cnt[6]), + .I3(converge_cnt[3]), + .I4(converge_cnt[4]), + .I5(\FSM_onehot_fsm[4]_i_10__2_n_0 ), + .O(\FSM_onehot_fsm[4]_i_6__2_n_0 )); + LUT4 #( + .INIT(16'hDFFF)) + \FSM_onehot_fsm[4]_i_7__2 + (.I0(out[1]), + .I1(out[0]), + .I2(converge_cnt[17]), + .I3(converge_cnt[18]), + .O(\FSM_onehot_fsm[4]_i_7__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_fsm[4]_i_8__2 + (.I0(\FSM_onehot_fsm[4]_i_11__2_n_0 ), + .I1(converge_cnt[12]), + .I2(converge_cnt[20]), + .I3(converge_cnt[0]), + .I4(converge_cnt[4]), + .I5(\FSM_onehot_fsm[4]_i_12__2_n_0 ), + .O(\FSM_onehot_fsm[4]_i_8__2_n_0 )); + LUT4 #( + .INIT(16'hFFDF)) + \FSM_onehot_fsm[4]_i_9__2 + (.I0(converge_cnt[15]), + .I1(converge_cnt[13]), + .I2(converge_cnt[14]), + .I3(converge_cnt[12]), + .O(\FSM_onehot_fsm[4]_i_9__2_n_0 )); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDSE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[1]_i_1__4_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[2]_i_1__4_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[3]_i_1__4_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[4]_i_1__4_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h40FF4040)) + \FSM_onehot_fsm_rx[2]_i_1__2 + (.I0(out[1]), + .I1(Q[0]), + .I2(out[0]), + .I3(preset_done), + .I4(Q[1]), + .O(D[0])); + LUT6 #( + .INIT(64'hF444444444444444)) + \FSM_onehot_fsm_rx[5]_i_1__2 + (.I0(rxeqscan_new_txcoeff_done), + .I1(Q[3]), + .I2(\FSM_onehot_fsm_rx_reg[5] [2]), + .I3(\FSM_onehot_fsm_rx_reg[5] [0]), + .I4(\FSM_onehot_fsm_rx_reg[5] [1]), + .I5(Q[2]), + .O(D[1])); + LUT6 #( + .INIT(64'hFFFFFFFFFFE0E0E0)) + \FSM_onehot_fsm_rx[6]_i_1__2 + (.I0(out[1]), + .I1(out[0]), + .I2(Q[4]), + .I3(preset_done), + .I4(Q[1]), + .I5(\FSM_onehot_fsm_rx[6]_i_2__2_n_0 ), + .O(D[2])); + (* SOFT_HLUTNM = "soft_lutpair182" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_fsm_rx[6]_i_2__2 + (.I0(rxeqscan_new_txcoeff_done), + .I1(Q[3]), + .O(\FSM_onehot_fsm_rx[6]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h000A0A0AF0F0F8F0)) + adapt_done_cnt_i_1__2 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .I5(adapt_done_cnt_i_2__2_n_0), + .O(adapt_done_cnt_i_1__2_n_0)); + LUT5 #( + .INIT(32'h00FF0101)) + adapt_done_cnt_i_2__2 + (.I0(\FSM_onehot_fsm_reg_n_0_[3] ), + .I1(\FSM_onehot_fsm_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_reg_n_0_[1] ), + .I3(new_txcoeff_req_reg2), + .I4(\FSM_onehot_fsm_reg_n_0_[4] ), + .O(adapt_done_cnt_i_2__2_n_0)); + FDRE #( + .INIT(1'b0)) + adapt_done_cnt_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(adapt_done_cnt_i_1__2_n_0), + .Q(adapt_done_cnt_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hF8000000)) + adapt_done_i_1__2 + (.I0(out[1]), + .I1(out[0]), + .I2(adapt_done_cnt_reg_n_0), + .I3(new_txcoeff_req_reg2), + .I4(\FSM_onehot_fsm_reg_n_0_[4] ), + .O(adapt_done)); + FDRE #( + .INIT(1'b0)) + adapt_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(adapt_done), + .Q(rxeqscan_adapt_done), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h44444044)) + \converge_cnt[0]_i_1__5 + (.I0(converge_cnt[0]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[0])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[10]_i_1__2 + (.I0(converge_cnt0[10]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[10])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[11]_i_1__2 + (.I0(converge_cnt0[11]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[11])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[12]_i_1__2 + (.I0(converge_cnt0[12]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[12])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[13]_i_1__2 + (.I0(converge_cnt0[13]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[13])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[14]_i_1__2 + (.I0(converge_cnt0[14]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[14])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[15]_i_1__2 + (.I0(converge_cnt0[15]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[15])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[16]_i_1__2 + (.I0(converge_cnt0[16]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[16])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[17]_i_1__2 + (.I0(converge_cnt0[17]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[17])); + (* SOFT_HLUTNM = "soft_lutpair180" *) + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[18]_i_1__2 + (.I0(converge_cnt0[18]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[18])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[19]_i_1__2 + (.I0(converge_cnt0[19]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[19])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[1]_i_1__2 + (.I0(converge_cnt0[1]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[1])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[20]_i_1__2 + (.I0(converge_cnt0[20]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[20])); + (* SOFT_HLUTNM = "soft_lutpair181" *) + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[21]_i_1__2 + (.I0(converge_cnt0[21]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[21])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[2]_i_1__2 + (.I0(converge_cnt0[2]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[2])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[3]_i_1__2 + (.I0(converge_cnt0[3]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[3])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[4]_i_1__2 + (.I0(converge_cnt0[4]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[4])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[5]_i_1__2 + (.I0(converge_cnt0[5]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[5])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[6]_i_1__2 + (.I0(converge_cnt0[6]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[6])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[7]_i_1__2 + (.I0(converge_cnt0[7]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[7])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[8]_i_1__2 + (.I0(converge_cnt0[8]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[8])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[9]_i_1__2 + (.I0(converge_cnt0[9]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[9])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[0]), + .Q(converge_cnt[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[10]), + .Q(converge_cnt[10]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[11]), + .Q(converge_cnt[11]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[12]), + .Q(converge_cnt[12]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[12]_i_2__2 + (.CI(\converge_cnt_reg[8]_i_2__2_n_0 ), + .CO({\converge_cnt_reg[12]_i_2__2_n_0 ,\converge_cnt_reg[12]_i_2__2_n_1 ,\converge_cnt_reg[12]_i_2__2_n_2 ,\converge_cnt_reg[12]_i_2__2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[12:9]), + .S(converge_cnt[12:9])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[13]), + .Q(converge_cnt[13]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[14]), + .Q(converge_cnt[14]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[15]), + .Q(converge_cnt[15]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[16]), + .Q(converge_cnt[16]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[16]_i_2__2 + (.CI(\converge_cnt_reg[12]_i_2__2_n_0 ), + .CO({\converge_cnt_reg[16]_i_2__2_n_0 ,\converge_cnt_reg[16]_i_2__2_n_1 ,\converge_cnt_reg[16]_i_2__2_n_2 ,\converge_cnt_reg[16]_i_2__2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[16:13]), + .S(converge_cnt[16:13])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[17]), + .Q(converge_cnt[17]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[18] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[18]), + .Q(converge_cnt[18]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[19] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[19]), + .Q(converge_cnt[19]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[1]), + .Q(converge_cnt[1]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[20] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[20]), + .Q(converge_cnt[20]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[20]_i_2__2 + (.CI(\converge_cnt_reg[16]_i_2__2_n_0 ), + .CO({\converge_cnt_reg[20]_i_2__2_n_0 ,\converge_cnt_reg[20]_i_2__2_n_1 ,\converge_cnt_reg[20]_i_2__2_n_2 ,\converge_cnt_reg[20]_i_2__2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[20:17]), + .S(converge_cnt[20:17])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[21] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[21]), + .Q(converge_cnt[21]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[21]_i_2__2 + (.CI(\converge_cnt_reg[20]_i_2__2_n_0 ), + .CO(\NLW_converge_cnt_reg[21]_i_2__2_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_converge_cnt_reg[21]_i_2__2_O_UNCONNECTED [3:1],converge_cnt0[21]}), + .S({1'b0,1'b0,1'b0,converge_cnt[21]})); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[2]), + .Q(converge_cnt[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[3]), + .Q(converge_cnt[3]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[4]), + .Q(converge_cnt[4]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[4]_i_2__2 + (.CI(1'b0), + .CO({\converge_cnt_reg[4]_i_2__2_n_0 ,\converge_cnt_reg[4]_i_2__2_n_1 ,\converge_cnt_reg[4]_i_2__2_n_2 ,\converge_cnt_reg[4]_i_2__2_n_3 }), + .CYINIT(converge_cnt[0]), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[4:1]), + .S(converge_cnt[4:1])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[5]), + .Q(converge_cnt[5]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[6]), + .Q(converge_cnt[6]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[7]), + .Q(converge_cnt[7]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[8]), + .Q(converge_cnt[8]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[8]_i_2__2 + (.CI(\converge_cnt_reg[4]_i_2__2_n_0 ), + .CO({\converge_cnt_reg[8]_i_2__2_n_0 ,\converge_cnt_reg[8]_i_2__2_n_1 ,\converge_cnt_reg[8]_i_2__2_n_2 ,\converge_cnt_reg[8]_i_2__2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[8:5]), + .S(converge_cnt[8:5])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[9]), + .Q(converge_cnt[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [0]), + .Q(fs_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [1]), + .Q(fs_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [2]), + .Q(fs_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [3]), + .Q(fs_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [4]), + .Q(fs_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [5]), + .Q(fs_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[0]), + .Q(fs_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[1]), + .Q(fs_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[2]), + .Q(fs_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[3]), + .Q(fs_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[4]), + .Q(fs_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[5]), + .Q(fs_reg2[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [0]), + .Q(lf_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [1]), + .Q(lf_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [2]), + .Q(lf_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [3]), + .Q(lf_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [4]), + .Q(lf_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [5]), + .Q(lf_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[0]), + .Q(lf_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[1]), + .Q(lf_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[2]), + .Q(lf_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[3]), + .Q(lf_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[4]), + .Q(lf_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[5]), + .Q(lf_reg2[5]), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + new_txcoeff_done_i_1__2 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(new_txcoeff_req_reg2), + .O(new_txcoeff_done)); + FDRE #( + .INIT(1'b0)) + new_txcoeff_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(new_txcoeff_done), + .Q(rxeqscan_new_txcoeff_done), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE new_txcoeff_req_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(new_txcoeff_req_reg1_reg_0), + .Q(new_txcoeff_req_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE new_txcoeff_req_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(new_txcoeff_req_reg1), + .Q(new_txcoeff_req_reg2), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'hEA)) + preset_done_i_1__2 + (.I0(\FSM_onehot_fsm_reg_n_0_[2] ), + .I1(\FSM_onehot_fsm_reg_n_0_[1] ), + .I2(preset_valid_reg2), + .O(preset_done_1)); + FDRE #( + .INIT(1'b0)) + preset_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_done_1), + .Q(preset_done), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\preset_reg1_reg[2]_0 [0]), + .Q(preset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\preset_reg1_reg[2]_0 [1]), + .Q(preset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\preset_reg1_reg[2]_0 [2]), + .Q(preset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_reg1[0]), + .Q(preset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_reg1[1]), + .Q(preset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_reg1[2]), + .Q(preset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE preset_valid_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_valid), + .Q(preset_valid_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE preset_valid_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_valid_reg1), + .Q(preset_valid_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hA800FFFFA8000000)) + rxeq_adapt_done_i_1__2 + (.I0(rxeqscan_new_txcoeff_done), + .I1(rxeq_adapt_done_reg_reg_1), + .I2(rxeqscan_adapt_done), + .I3(Q[3]), + .I4(rxeq_adapt_done_reg), + .I5(USER_RXEQ_ADAPT_DONE), + .O(new_txcoeff_done_reg_0)); + LUT6 #( + .INIT(64'hFF00FF33AA00A800)) + rxeq_adapt_done_reg_i_1__2 + (.I0(rxeqscan_adapt_done), + .I1(rxeq_adapt_done_reg_reg), + .I2(rxeqscan_new_txcoeff_done), + .I3(Q[3]), + .I4(rxeq_adapt_done_reg_reg_0), + .I5(rxeq_adapt_done_reg_reg_1), + .O(adapt_done_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair182" *) + LUT2 #( + .INIT(4'h2)) + rxeq_new_txcoeff_req_i_1__2 + (.I0(Q[3]), + .I1(rxeqscan_new_txcoeff_done), + .O(rxeq_new_txcoeff_req)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [0]), + .Q(txcoeff_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [10]), + .Q(txcoeff_reg1[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [11]), + .Q(txcoeff_reg1[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [12]), + .Q(txcoeff_reg1[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [13]), + .Q(txcoeff_reg1[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [14]), + .Q(txcoeff_reg1[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [15]), + .Q(txcoeff_reg1[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [16]), + .Q(txcoeff_reg1[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [17]), + .Q(txcoeff_reg1[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [1]), + .Q(txcoeff_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [2]), + .Q(txcoeff_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [3]), + .Q(txcoeff_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [4]), + .Q(txcoeff_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [5]), + .Q(txcoeff_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [6]), + .Q(txcoeff_reg1[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [7]), + .Q(txcoeff_reg1[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [8]), + .Q(txcoeff_reg1[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [9]), + .Q(txcoeff_reg1[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[0]), + .Q(txcoeff_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[10]), + .Q(txcoeff_reg2[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[11]), + .Q(txcoeff_reg2[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[12]), + .Q(txcoeff_reg2[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[13]), + .Q(txcoeff_reg2[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[14]), + .Q(txcoeff_reg2[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[15]), + .Q(txcoeff_reg2[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[16]), + .Q(txcoeff_reg2[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[17]), + .Q(txcoeff_reg2[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[1]), + .Q(txcoeff_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[2]), + .Q(txcoeff_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[3]), + .Q(txcoeff_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[4]), + .Q(txcoeff_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[5]), + .Q(txcoeff_reg2[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[6]), + .Q(txcoeff_reg2[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[7]), + .Q(txcoeff_reg2[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[8]), + .Q(txcoeff_reg2[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[9]), + .Q(txcoeff_reg2[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [0]), + .Q(txpreset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [1]), + .Q(txpreset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [2]), + .Q(txpreset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [3]), + .Q(txpreset_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[0]), + .Q(txpreset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[1]), + .Q(txpreset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[2]), + .Q(txpreset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[3]), + .Q(txpreset_reg2[3]), + .R(RST_CPLLRESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_rxeq_scan" *) +module pcie_7x_0_pcie_7x_0_rxeq_scan_55 + (D, + rxeq_new_txcoeff_req, + adapt_done_reg_0, + new_txcoeff_done_reg_0, + RST_CPLLRESET, + pipe_pclk_in, + new_txcoeff_req_reg1_reg_0, + rxeq_preset_valid, + out, + Q, + \FSM_onehot_fsm_rx_reg[5] , + rxeq_adapt_done_reg_reg, + rxeq_adapt_done_reg_reg_0, + rxeq_adapt_done_reg_reg_1, + rxeq_adapt_done_reg, + USER_RXEQ_ADAPT_DONE, + \preset_reg1_reg[2]_0 , + \txpreset_reg1_reg[3]_0 , + \txcoeff_reg1_reg[17]_0 , + \fs_reg1_reg[5]_0 , + \lf_reg1_reg[5]_0 ); + output [2:0]D; + output rxeq_new_txcoeff_req; + output adapt_done_reg_0; + output new_txcoeff_done_reg_0; + input RST_CPLLRESET; + input pipe_pclk_in; + input new_txcoeff_req_reg1_reg_0; + input rxeq_preset_valid; + input [1:0]out; + input [4:0]Q; + input [2:0]\FSM_onehot_fsm_rx_reg[5] ; + input rxeq_adapt_done_reg_reg; + input rxeq_adapt_done_reg_reg_0; + input rxeq_adapt_done_reg_reg_1; + input rxeq_adapt_done_reg; + input USER_RXEQ_ADAPT_DONE; + input [2:0]\preset_reg1_reg[2]_0 ; + input [3:0]\txpreset_reg1_reg[3]_0 ; + input [17:0]\txcoeff_reg1_reg[17]_0 ; + input [5:0]\fs_reg1_reg[5]_0 ; + input [5:0]\lf_reg1_reg[5]_0 ; + + wire [2:0]D; + wire \FSM_onehot_fsm[1]_i_1__3_n_0 ; + wire \FSM_onehot_fsm[2]_i_1__3_n_0 ; + wire \FSM_onehot_fsm[3]_i_1__3_n_0 ; + wire \FSM_onehot_fsm[3]_i_2__1_n_0 ; + wire \FSM_onehot_fsm[4]_i_10__1_n_0 ; + wire \FSM_onehot_fsm[4]_i_11__1_n_0 ; + wire \FSM_onehot_fsm[4]_i_12__1_n_0 ; + wire \FSM_onehot_fsm[4]_i_13__1_n_0 ; + wire \FSM_onehot_fsm[4]_i_1__3_n_0 ; + wire \FSM_onehot_fsm[4]_i_2__2_n_0 ; + wire \FSM_onehot_fsm[4]_i_3__1_n_0 ; + wire \FSM_onehot_fsm[4]_i_4__1_n_0 ; + wire \FSM_onehot_fsm[4]_i_5__1_n_0 ; + wire \FSM_onehot_fsm[4]_i_6__1_n_0 ; + wire \FSM_onehot_fsm[4]_i_7__1_n_0 ; + wire \FSM_onehot_fsm[4]_i_8__1_n_0 ; + wire \FSM_onehot_fsm[4]_i_9__1_n_0 ; + wire \FSM_onehot_fsm_reg_n_0_[1] ; + wire \FSM_onehot_fsm_reg_n_0_[2] ; + wire \FSM_onehot_fsm_reg_n_0_[3] ; + wire \FSM_onehot_fsm_reg_n_0_[4] ; + wire \FSM_onehot_fsm_rx[6]_i_2__1_n_0 ; + wire [2:0]\FSM_onehot_fsm_rx_reg[5] ; + wire [4:0]Q; + wire RST_CPLLRESET; + wire USER_RXEQ_ADAPT_DONE; + wire adapt_done; + wire adapt_done_cnt_i_1__1_n_0; + wire adapt_done_cnt_i_2__1_n_0; + wire adapt_done_cnt_reg_n_0; + wire adapt_done_reg_0; + wire [21:0]converge_cnt; + wire [21:1]converge_cnt0; + wire [21:0]converge_cnt_0; + wire \converge_cnt_reg[12]_i_2__1_n_0 ; + wire \converge_cnt_reg[12]_i_2__1_n_1 ; + wire \converge_cnt_reg[12]_i_2__1_n_2 ; + wire \converge_cnt_reg[12]_i_2__1_n_3 ; + wire \converge_cnt_reg[16]_i_2__1_n_0 ; + wire \converge_cnt_reg[16]_i_2__1_n_1 ; + wire \converge_cnt_reg[16]_i_2__1_n_2 ; + wire \converge_cnt_reg[16]_i_2__1_n_3 ; + wire \converge_cnt_reg[20]_i_2__1_n_0 ; + wire \converge_cnt_reg[20]_i_2__1_n_1 ; + wire \converge_cnt_reg[20]_i_2__1_n_2 ; + wire \converge_cnt_reg[20]_i_2__1_n_3 ; + wire \converge_cnt_reg[4]_i_2__1_n_0 ; + wire \converge_cnt_reg[4]_i_2__1_n_1 ; + wire \converge_cnt_reg[4]_i_2__1_n_2 ; + wire \converge_cnt_reg[4]_i_2__1_n_3 ; + wire \converge_cnt_reg[8]_i_2__1_n_0 ; + wire \converge_cnt_reg[8]_i_2__1_n_1 ; + wire \converge_cnt_reg[8]_i_2__1_n_2 ; + wire \converge_cnt_reg[8]_i_2__1_n_3 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]fs_reg1; + wire [5:0]\fs_reg1_reg[5]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]fs_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]lf_reg1; + wire [5:0]\lf_reg1_reg[5]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]lf_reg2; + wire new_txcoeff_done; + wire new_txcoeff_done_reg_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire new_txcoeff_req_reg1; + wire new_txcoeff_req_reg1_reg_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire new_txcoeff_req_reg2; + wire [1:0]out; + wire pipe_pclk_in; + wire preset_done; + wire preset_done_1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]preset_reg1; + wire [2:0]\preset_reg1_reg[2]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]preset_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire preset_valid_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire preset_valid_reg2; + wire rxeq_adapt_done_reg; + wire rxeq_adapt_done_reg_reg; + wire rxeq_adapt_done_reg_reg_0; + wire rxeq_adapt_done_reg_reg_1; + wire rxeq_new_txcoeff_req; + wire rxeq_preset_valid; + wire rxeqscan_adapt_done; + wire rxeqscan_new_txcoeff_done; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]txcoeff_reg1; + wire [17:0]\txcoeff_reg1_reg[17]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]txcoeff_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txpreset_reg1; + wire [3:0]\txpreset_reg1_reg[3]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txpreset_reg2; + wire [3:0]\NLW_converge_cnt_reg[21]_i_2__1_CO_UNCONNECTED ; + wire [3:1]\NLW_converge_cnt_reg[21]_i_2__1_O_UNCONNECTED ; + + LUT6 #( + .INIT(64'h0F00AFAF0F11AFBB)) + \FSM_onehot_fsm[1]_i_1__3 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(preset_valid_reg2), + .I3(\FSM_onehot_fsm_reg_n_0_[2] ), + .I4(new_txcoeff_req_reg2), + .I5(\FSM_onehot_fsm_reg_n_0_[1] ), + .O(\FSM_onehot_fsm[1]_i_1__3_n_0 )); + LUT3 #( + .INIT(8'hA8)) + \FSM_onehot_fsm[2]_i_1__3 + (.I0(preset_valid_reg2), + .I1(\FSM_onehot_fsm_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_reg_n_0_[1] ), + .O(\FSM_onehot_fsm[2]_i_1__3_n_0 )); + LUT6 #( + .INIT(64'h04FF040404040404)) + \FSM_onehot_fsm[3]_i_1__3 + (.I0(\FSM_onehot_fsm[3]_i_2__1_n_0 ), + .I1(\FSM_onehot_fsm[4]_i_2__2_n_0 ), + .I2(\FSM_onehot_fsm[4]_i_3__1_n_0 ), + .I3(preset_valid_reg2), + .I4(new_txcoeff_req_reg2), + .I5(\FSM_onehot_fsm_reg_n_0_[1] ), + .O(\FSM_onehot_fsm[3]_i_1__3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair140" *) + LUT4 #( + .INIT(16'h04FF)) + \FSM_onehot_fsm[3]_i_2__1 + (.I0(out[0]), + .I1(out[1]), + .I2(adapt_done_cnt_reg_n_0), + .I3(\FSM_onehot_fsm_reg_n_0_[3] ), + .O(\FSM_onehot_fsm[3]_i_2__1_n_0 )); + LUT5 #( + .INIT(32'hFFBFFFFF)) + \FSM_onehot_fsm[4]_i_10__1 + (.I0(\FSM_onehot_fsm[4]_i_13__1_n_0 ), + .I1(converge_cnt[2]), + .I2(converge_cnt[20]), + .I3(converge_cnt[10]), + .I4(converge_cnt[0]), + .O(\FSM_onehot_fsm[4]_i_10__1_n_0 )); + LUT4 #( + .INIT(16'hEFFF)) + \FSM_onehot_fsm[4]_i_11__1 + (.I0(converge_cnt[2]), + .I1(converge_cnt[6]), + .I2(converge_cnt[8]), + .I3(converge_cnt[3]), + .O(\FSM_onehot_fsm[4]_i_11__1_n_0 )); + LUT5 #( + .INIT(32'hEFFFFFFF)) + \FSM_onehot_fsm[4]_i_12__1 + (.I0(\FSM_onehot_fsm[4]_i_13__1_n_0 ), + .I1(converge_cnt[14]), + .I2(converge_cnt[10]), + .I3(converge_cnt[21]), + .I4(converge_cnt[19]), + .O(\FSM_onehot_fsm[4]_i_12__1_n_0 )); + LUT4 #( + .INIT(16'hFF7F)) + \FSM_onehot_fsm[4]_i_13__1 + (.I0(converge_cnt[16]), + .I1(converge_cnt[11]), + .I2(converge_cnt[9]), + .I3(converge_cnt[5]), + .O(\FSM_onehot_fsm[4]_i_13__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFD0FFD0FFD0)) + \FSM_onehot_fsm[4]_i_1__3 + (.I0(\FSM_onehot_fsm[4]_i_2__2_n_0 ), + .I1(\FSM_onehot_fsm[4]_i_3__1_n_0 ), + .I2(\FSM_onehot_fsm_reg_n_0_[3] ), + .I3(\FSM_onehot_fsm[4]_i_4__1_n_0 ), + .I4(\FSM_onehot_fsm_reg_n_0_[4] ), + .I5(new_txcoeff_req_reg2), + .O(\FSM_onehot_fsm[4]_i_1__3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFBF)) + \FSM_onehot_fsm[4]_i_2__2 + (.I0(\FSM_onehot_fsm[4]_i_5__1_n_0 ), + .I1(converge_cnt[17]), + .I2(converge_cnt[18]), + .I3(converge_cnt[21]), + .I4(converge_cnt[8]), + .I5(\FSM_onehot_fsm[4]_i_6__1_n_0 ), + .O(\FSM_onehot_fsm[4]_i_2__2_n_0 )); + LUT6 #( + .INIT(64'h0000000001000000)) + \FSM_onehot_fsm[4]_i_3__1 + (.I0(\FSM_onehot_fsm[4]_i_7__1_n_0 ), + .I1(converge_cnt[7]), + .I2(converge_cnt[1]), + .I3(converge_cnt[15]), + .I4(converge_cnt[13]), + .I5(\FSM_onehot_fsm[4]_i_8__1_n_0 ), + .O(\FSM_onehot_fsm[4]_i_3__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair139" *) + LUT4 #( + .INIT(16'h0400)) + \FSM_onehot_fsm[4]_i_4__1 + (.I0(out[0]), + .I1(out[1]), + .I2(adapt_done_cnt_reg_n_0), + .I3(\FSM_onehot_fsm_reg_n_0_[3] ), + .O(\FSM_onehot_fsm[4]_i_4__1_n_0 )); + LUT4 #( + .INIT(16'hFFF2)) + \FSM_onehot_fsm[4]_i_5__1 + (.I0(out[1]), + .I1(out[0]), + .I2(converge_cnt[7]), + .I3(converge_cnt[1]), + .O(\FSM_onehot_fsm[4]_i_5__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFB)) + \FSM_onehot_fsm[4]_i_6__1 + (.I0(\FSM_onehot_fsm[4]_i_9__1_n_0 ), + .I1(converge_cnt[19]), + .I2(converge_cnt[6]), + .I3(converge_cnt[3]), + .I4(converge_cnt[4]), + .I5(\FSM_onehot_fsm[4]_i_10__1_n_0 ), + .O(\FSM_onehot_fsm[4]_i_6__1_n_0 )); + LUT4 #( + .INIT(16'hDFFF)) + \FSM_onehot_fsm[4]_i_7__1 + (.I0(out[1]), + .I1(out[0]), + .I2(converge_cnt[17]), + .I3(converge_cnt[18]), + .O(\FSM_onehot_fsm[4]_i_7__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_fsm[4]_i_8__1 + (.I0(\FSM_onehot_fsm[4]_i_11__1_n_0 ), + .I1(converge_cnt[12]), + .I2(converge_cnt[20]), + .I3(converge_cnt[0]), + .I4(converge_cnt[4]), + .I5(\FSM_onehot_fsm[4]_i_12__1_n_0 ), + .O(\FSM_onehot_fsm[4]_i_8__1_n_0 )); + LUT4 #( + .INIT(16'hFFDF)) + \FSM_onehot_fsm[4]_i_9__1 + (.I0(converge_cnt[15]), + .I1(converge_cnt[13]), + .I2(converge_cnt[14]), + .I3(converge_cnt[12]), + .O(\FSM_onehot_fsm[4]_i_9__1_n_0 )); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDSE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[1]_i_1__3_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[2]_i_1__3_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[3]_i_1__3_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[4]_i_1__3_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h40FF4040)) + \FSM_onehot_fsm_rx[2]_i_1__1 + (.I0(out[1]), + .I1(Q[0]), + .I2(out[0]), + .I3(preset_done), + .I4(Q[1]), + .O(D[0])); + LUT6 #( + .INIT(64'hF444444444444444)) + \FSM_onehot_fsm_rx[5]_i_1__1 + (.I0(rxeqscan_new_txcoeff_done), + .I1(Q[3]), + .I2(\FSM_onehot_fsm_rx_reg[5] [2]), + .I3(\FSM_onehot_fsm_rx_reg[5] [0]), + .I4(\FSM_onehot_fsm_rx_reg[5] [1]), + .I5(Q[2]), + .O(D[1])); + LUT6 #( + .INIT(64'hFFFFFFFFFFE0E0E0)) + \FSM_onehot_fsm_rx[6]_i_1__1 + (.I0(out[1]), + .I1(out[0]), + .I2(Q[4]), + .I3(preset_done), + .I4(Q[1]), + .I5(\FSM_onehot_fsm_rx[6]_i_2__1_n_0 ), + .O(D[2])); + (* SOFT_HLUTNM = "soft_lutpair141" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_fsm_rx[6]_i_2__1 + (.I0(rxeqscan_new_txcoeff_done), + .I1(Q[3]), + .O(\FSM_onehot_fsm_rx[6]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h000A0A0AF0F0F8F0)) + adapt_done_cnt_i_1__1 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .I5(adapt_done_cnt_i_2__1_n_0), + .O(adapt_done_cnt_i_1__1_n_0)); + LUT5 #( + .INIT(32'h00FF0101)) + adapt_done_cnt_i_2__1 + (.I0(\FSM_onehot_fsm_reg_n_0_[3] ), + .I1(\FSM_onehot_fsm_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_reg_n_0_[1] ), + .I3(new_txcoeff_req_reg2), + .I4(\FSM_onehot_fsm_reg_n_0_[4] ), + .O(adapt_done_cnt_i_2__1_n_0)); + FDRE #( + .INIT(1'b0)) + adapt_done_cnt_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(adapt_done_cnt_i_1__1_n_0), + .Q(adapt_done_cnt_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hF8000000)) + adapt_done_i_1__1 + (.I0(out[1]), + .I1(out[0]), + .I2(adapt_done_cnt_reg_n_0), + .I3(new_txcoeff_req_reg2), + .I4(\FSM_onehot_fsm_reg_n_0_[4] ), + .O(adapt_done)); + FDRE #( + .INIT(1'b0)) + adapt_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(adapt_done), + .Q(rxeqscan_adapt_done), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h44444044)) + \converge_cnt[0]_i_1__3 + (.I0(converge_cnt[0]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[0])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[10]_i_1__1 + (.I0(converge_cnt0[10]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[10])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[11]_i_1__1 + (.I0(converge_cnt0[11]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[11])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[12]_i_1__1 + (.I0(converge_cnt0[12]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[12])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[13]_i_1__1 + (.I0(converge_cnt0[13]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[13])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[14]_i_1__1 + (.I0(converge_cnt0[14]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[14])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[15]_i_1__1 + (.I0(converge_cnt0[15]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[15])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[16]_i_1__1 + (.I0(converge_cnt0[16]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[16])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[17]_i_1__1 + (.I0(converge_cnt0[17]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[17])); + (* SOFT_HLUTNM = "soft_lutpair139" *) + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[18]_i_1__1 + (.I0(converge_cnt0[18]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[18])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[19]_i_1__1 + (.I0(converge_cnt0[19]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[19])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[1]_i_1__1 + (.I0(converge_cnt0[1]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[1])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[20]_i_1__1 + (.I0(converge_cnt0[20]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[20])); + (* SOFT_HLUTNM = "soft_lutpair140" *) + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[21]_i_1__1 + (.I0(converge_cnt0[21]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[21])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[2]_i_1__1 + (.I0(converge_cnt0[2]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[2])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[3]_i_1__1 + (.I0(converge_cnt0[3]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[3])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[4]_i_1__1 + (.I0(converge_cnt0[4]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[4])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[5]_i_1__1 + (.I0(converge_cnt0[5]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[5])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[6]_i_1__1 + (.I0(converge_cnt0[6]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[6])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[7]_i_1__1 + (.I0(converge_cnt0[7]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[7])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[8]_i_1__1 + (.I0(converge_cnt0[8]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[8])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[9]_i_1__1 + (.I0(converge_cnt0[9]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[9])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[0]), + .Q(converge_cnt[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[10]), + .Q(converge_cnt[10]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[11]), + .Q(converge_cnt[11]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[12]), + .Q(converge_cnt[12]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[12]_i_2__1 + (.CI(\converge_cnt_reg[8]_i_2__1_n_0 ), + .CO({\converge_cnt_reg[12]_i_2__1_n_0 ,\converge_cnt_reg[12]_i_2__1_n_1 ,\converge_cnt_reg[12]_i_2__1_n_2 ,\converge_cnt_reg[12]_i_2__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[12:9]), + .S(converge_cnt[12:9])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[13]), + .Q(converge_cnt[13]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[14]), + .Q(converge_cnt[14]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[15]), + .Q(converge_cnt[15]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[16]), + .Q(converge_cnt[16]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[16]_i_2__1 + (.CI(\converge_cnt_reg[12]_i_2__1_n_0 ), + .CO({\converge_cnt_reg[16]_i_2__1_n_0 ,\converge_cnt_reg[16]_i_2__1_n_1 ,\converge_cnt_reg[16]_i_2__1_n_2 ,\converge_cnt_reg[16]_i_2__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[16:13]), + .S(converge_cnt[16:13])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[17]), + .Q(converge_cnt[17]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[18] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[18]), + .Q(converge_cnt[18]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[19] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[19]), + .Q(converge_cnt[19]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[1]), + .Q(converge_cnt[1]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[20] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[20]), + .Q(converge_cnt[20]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[20]_i_2__1 + (.CI(\converge_cnt_reg[16]_i_2__1_n_0 ), + .CO({\converge_cnt_reg[20]_i_2__1_n_0 ,\converge_cnt_reg[20]_i_2__1_n_1 ,\converge_cnt_reg[20]_i_2__1_n_2 ,\converge_cnt_reg[20]_i_2__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[20:17]), + .S(converge_cnt[20:17])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[21] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[21]), + .Q(converge_cnt[21]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[21]_i_2__1 + (.CI(\converge_cnt_reg[20]_i_2__1_n_0 ), + .CO(\NLW_converge_cnt_reg[21]_i_2__1_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_converge_cnt_reg[21]_i_2__1_O_UNCONNECTED [3:1],converge_cnt0[21]}), + .S({1'b0,1'b0,1'b0,converge_cnt[21]})); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[2]), + .Q(converge_cnt[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[3]), + .Q(converge_cnt[3]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[4]), + .Q(converge_cnt[4]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[4]_i_2__1 + (.CI(1'b0), + .CO({\converge_cnt_reg[4]_i_2__1_n_0 ,\converge_cnt_reg[4]_i_2__1_n_1 ,\converge_cnt_reg[4]_i_2__1_n_2 ,\converge_cnt_reg[4]_i_2__1_n_3 }), + .CYINIT(converge_cnt[0]), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[4:1]), + .S(converge_cnt[4:1])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[5]), + .Q(converge_cnt[5]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[6]), + .Q(converge_cnt[6]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[7]), + .Q(converge_cnt[7]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[8]), + .Q(converge_cnt[8]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[8]_i_2__1 + (.CI(\converge_cnt_reg[4]_i_2__1_n_0 ), + .CO({\converge_cnt_reg[8]_i_2__1_n_0 ,\converge_cnt_reg[8]_i_2__1_n_1 ,\converge_cnt_reg[8]_i_2__1_n_2 ,\converge_cnt_reg[8]_i_2__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[8:5]), + .S(converge_cnt[8:5])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[9]), + .Q(converge_cnt[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [0]), + .Q(fs_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [1]), + .Q(fs_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [2]), + .Q(fs_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [3]), + .Q(fs_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [4]), + .Q(fs_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [5]), + .Q(fs_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[0]), + .Q(fs_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[1]), + .Q(fs_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[2]), + .Q(fs_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[3]), + .Q(fs_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[4]), + .Q(fs_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[5]), + .Q(fs_reg2[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [0]), + .Q(lf_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [1]), + .Q(lf_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [2]), + .Q(lf_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [3]), + .Q(lf_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [4]), + .Q(lf_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [5]), + .Q(lf_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[0]), + .Q(lf_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[1]), + .Q(lf_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[2]), + .Q(lf_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[3]), + .Q(lf_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[4]), + .Q(lf_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[5]), + .Q(lf_reg2[5]), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + new_txcoeff_done_i_1__1 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(new_txcoeff_req_reg2), + .O(new_txcoeff_done)); + FDRE #( + .INIT(1'b0)) + new_txcoeff_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(new_txcoeff_done), + .Q(rxeqscan_new_txcoeff_done), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE new_txcoeff_req_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(new_txcoeff_req_reg1_reg_0), + .Q(new_txcoeff_req_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE new_txcoeff_req_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(new_txcoeff_req_reg1), + .Q(new_txcoeff_req_reg2), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'hEA)) + preset_done_i_1__1 + (.I0(\FSM_onehot_fsm_reg_n_0_[2] ), + .I1(\FSM_onehot_fsm_reg_n_0_[1] ), + .I2(preset_valid_reg2), + .O(preset_done_1)); + FDRE #( + .INIT(1'b0)) + preset_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_done_1), + .Q(preset_done), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\preset_reg1_reg[2]_0 [0]), + .Q(preset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\preset_reg1_reg[2]_0 [1]), + .Q(preset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\preset_reg1_reg[2]_0 [2]), + .Q(preset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_reg1[0]), + .Q(preset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_reg1[1]), + .Q(preset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_reg1[2]), + .Q(preset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE preset_valid_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_valid), + .Q(preset_valid_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE preset_valid_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_valid_reg1), + .Q(preset_valid_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hA800FFFFA8000000)) + rxeq_adapt_done_i_1__1 + (.I0(rxeqscan_new_txcoeff_done), + .I1(rxeq_adapt_done_reg_reg_1), + .I2(rxeqscan_adapt_done), + .I3(Q[3]), + .I4(rxeq_adapt_done_reg), + .I5(USER_RXEQ_ADAPT_DONE), + .O(new_txcoeff_done_reg_0)); + LUT6 #( + .INIT(64'hFF00FF33AA00A800)) + rxeq_adapt_done_reg_i_1__1 + (.I0(rxeqscan_adapt_done), + .I1(rxeq_adapt_done_reg_reg), + .I2(rxeqscan_new_txcoeff_done), + .I3(Q[3]), + .I4(rxeq_adapt_done_reg_reg_0), + .I5(rxeq_adapt_done_reg_reg_1), + .O(adapt_done_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair141" *) + LUT2 #( + .INIT(4'h2)) + rxeq_new_txcoeff_req_i_1__1 + (.I0(Q[3]), + .I1(rxeqscan_new_txcoeff_done), + .O(rxeq_new_txcoeff_req)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [0]), + .Q(txcoeff_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [10]), + .Q(txcoeff_reg1[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [11]), + .Q(txcoeff_reg1[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [12]), + .Q(txcoeff_reg1[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [13]), + .Q(txcoeff_reg1[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [14]), + .Q(txcoeff_reg1[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [15]), + .Q(txcoeff_reg1[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [16]), + .Q(txcoeff_reg1[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [17]), + .Q(txcoeff_reg1[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [1]), + .Q(txcoeff_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [2]), + .Q(txcoeff_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [3]), + .Q(txcoeff_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [4]), + .Q(txcoeff_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [5]), + .Q(txcoeff_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [6]), + .Q(txcoeff_reg1[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [7]), + .Q(txcoeff_reg1[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [8]), + .Q(txcoeff_reg1[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [9]), + .Q(txcoeff_reg1[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[0]), + .Q(txcoeff_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[10]), + .Q(txcoeff_reg2[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[11]), + .Q(txcoeff_reg2[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[12]), + .Q(txcoeff_reg2[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[13]), + .Q(txcoeff_reg2[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[14]), + .Q(txcoeff_reg2[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[15]), + .Q(txcoeff_reg2[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[16]), + .Q(txcoeff_reg2[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[17]), + .Q(txcoeff_reg2[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[1]), + .Q(txcoeff_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[2]), + .Q(txcoeff_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[3]), + .Q(txcoeff_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[4]), + .Q(txcoeff_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[5]), + .Q(txcoeff_reg2[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[6]), + .Q(txcoeff_reg2[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[7]), + .Q(txcoeff_reg2[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[8]), + .Q(txcoeff_reg2[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[9]), + .Q(txcoeff_reg2[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [0]), + .Q(txpreset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [1]), + .Q(txpreset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [2]), + .Q(txpreset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [3]), + .Q(txpreset_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[0]), + .Q(txpreset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[1]), + .Q(txpreset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[2]), + .Q(txpreset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[3]), + .Q(txpreset_reg2[3]), + .R(RST_CPLLRESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_rxeq_scan" *) +module pcie_7x_0_pcie_7x_0_rxeq_scan_57 + (D, + rxeq_new_txcoeff_req, + adapt_done_reg_0, + new_txcoeff_done_reg_0, + RST_CPLLRESET, + pipe_pclk_in, + new_txcoeff_req_reg1_reg_0, + rxeq_preset_valid, + out, + Q, + \FSM_onehot_fsm_rx_reg[5] , + rxeq_adapt_done_reg_reg, + rxeq_adapt_done_reg_reg_0, + rxeq_adapt_done_reg_reg_1, + rxeq_adapt_done_reg, + USER_RXEQ_ADAPT_DONE, + \preset_reg1_reg[2]_0 , + \txpreset_reg1_reg[3]_0 , + \txcoeff_reg1_reg[17]_0 , + \fs_reg1_reg[5]_0 , + \lf_reg1_reg[5]_0 ); + output [2:0]D; + output rxeq_new_txcoeff_req; + output adapt_done_reg_0; + output new_txcoeff_done_reg_0; + input RST_CPLLRESET; + input pipe_pclk_in; + input new_txcoeff_req_reg1_reg_0; + input rxeq_preset_valid; + input [1:0]out; + input [4:0]Q; + input [2:0]\FSM_onehot_fsm_rx_reg[5] ; + input rxeq_adapt_done_reg_reg; + input rxeq_adapt_done_reg_reg_0; + input rxeq_adapt_done_reg_reg_1; + input rxeq_adapt_done_reg; + input USER_RXEQ_ADAPT_DONE; + input [2:0]\preset_reg1_reg[2]_0 ; + input [3:0]\txpreset_reg1_reg[3]_0 ; + input [17:0]\txcoeff_reg1_reg[17]_0 ; + input [5:0]\fs_reg1_reg[5]_0 ; + input [5:0]\lf_reg1_reg[5]_0 ; + + wire [2:0]D; + wire \FSM_onehot_fsm[1]_i_1__2_n_0 ; + wire \FSM_onehot_fsm[2]_i_1__2_n_0 ; + wire \FSM_onehot_fsm[3]_i_1__2_n_0 ; + wire \FSM_onehot_fsm[3]_i_2__0_n_0 ; + wire \FSM_onehot_fsm[4]_i_10__0_n_0 ; + wire \FSM_onehot_fsm[4]_i_11__0_n_0 ; + wire \FSM_onehot_fsm[4]_i_12__0_n_0 ; + wire \FSM_onehot_fsm[4]_i_13__0_n_0 ; + wire \FSM_onehot_fsm[4]_i_1__2_n_0 ; + wire \FSM_onehot_fsm[4]_i_2__1_n_0 ; + wire \FSM_onehot_fsm[4]_i_3__0_n_0 ; + wire \FSM_onehot_fsm[4]_i_4__0_n_0 ; + wire \FSM_onehot_fsm[4]_i_5__0_n_0 ; + wire \FSM_onehot_fsm[4]_i_6__0_n_0 ; + wire \FSM_onehot_fsm[4]_i_7__0_n_0 ; + wire \FSM_onehot_fsm[4]_i_8__0_n_0 ; + wire \FSM_onehot_fsm[4]_i_9__0_n_0 ; + wire \FSM_onehot_fsm_reg_n_0_[1] ; + wire \FSM_onehot_fsm_reg_n_0_[2] ; + wire \FSM_onehot_fsm_reg_n_0_[3] ; + wire \FSM_onehot_fsm_reg_n_0_[4] ; + wire \FSM_onehot_fsm_rx[6]_i_2__0_n_0 ; + wire [2:0]\FSM_onehot_fsm_rx_reg[5] ; + wire [4:0]Q; + wire RST_CPLLRESET; + wire USER_RXEQ_ADAPT_DONE; + wire adapt_done; + wire adapt_done_cnt_i_1__0_n_0; + wire adapt_done_cnt_i_2__0_n_0; + wire adapt_done_cnt_reg_n_0; + wire adapt_done_reg_0; + wire [21:0]converge_cnt; + wire [21:1]converge_cnt0; + wire [21:0]converge_cnt_0; + wire \converge_cnt_reg[12]_i_2__0_n_0 ; + wire \converge_cnt_reg[12]_i_2__0_n_1 ; + wire \converge_cnt_reg[12]_i_2__0_n_2 ; + wire \converge_cnt_reg[12]_i_2__0_n_3 ; + wire \converge_cnt_reg[16]_i_2__0_n_0 ; + wire \converge_cnt_reg[16]_i_2__0_n_1 ; + wire \converge_cnt_reg[16]_i_2__0_n_2 ; + wire \converge_cnt_reg[16]_i_2__0_n_3 ; + wire \converge_cnt_reg[20]_i_2__0_n_0 ; + wire \converge_cnt_reg[20]_i_2__0_n_1 ; + wire \converge_cnt_reg[20]_i_2__0_n_2 ; + wire \converge_cnt_reg[20]_i_2__0_n_3 ; + wire \converge_cnt_reg[4]_i_2__0_n_0 ; + wire \converge_cnt_reg[4]_i_2__0_n_1 ; + wire \converge_cnt_reg[4]_i_2__0_n_2 ; + wire \converge_cnt_reg[4]_i_2__0_n_3 ; + wire \converge_cnt_reg[8]_i_2__0_n_0 ; + wire \converge_cnt_reg[8]_i_2__0_n_1 ; + wire \converge_cnt_reg[8]_i_2__0_n_2 ; + wire \converge_cnt_reg[8]_i_2__0_n_3 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]fs_reg1; + wire [5:0]\fs_reg1_reg[5]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]fs_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]lf_reg1; + wire [5:0]\lf_reg1_reg[5]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]lf_reg2; + wire new_txcoeff_done; + wire new_txcoeff_done_reg_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire new_txcoeff_req_reg1; + wire new_txcoeff_req_reg1_reg_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire new_txcoeff_req_reg2; + wire [1:0]out; + wire pipe_pclk_in; + wire preset_done; + wire preset_done_1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]preset_reg1; + wire [2:0]\preset_reg1_reg[2]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]preset_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire preset_valid_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire preset_valid_reg2; + wire rxeq_adapt_done_reg; + wire rxeq_adapt_done_reg_reg; + wire rxeq_adapt_done_reg_reg_0; + wire rxeq_adapt_done_reg_reg_1; + wire rxeq_new_txcoeff_req; + wire rxeq_preset_valid; + wire rxeqscan_adapt_done; + wire rxeqscan_new_txcoeff_done; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]txcoeff_reg1; + wire [17:0]\txcoeff_reg1_reg[17]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]txcoeff_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txpreset_reg1; + wire [3:0]\txpreset_reg1_reg[3]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txpreset_reg2; + wire [3:0]\NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED ; + wire [3:1]\NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED ; + + LUT6 #( + .INIT(64'h0F00AFAF0F11AFBB)) + \FSM_onehot_fsm[1]_i_1__2 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(preset_valid_reg2), + .I3(\FSM_onehot_fsm_reg_n_0_[2] ), + .I4(new_txcoeff_req_reg2), + .I5(\FSM_onehot_fsm_reg_n_0_[1] ), + .O(\FSM_onehot_fsm[1]_i_1__2_n_0 )); + LUT3 #( + .INIT(8'hA8)) + \FSM_onehot_fsm[2]_i_1__2 + (.I0(preset_valid_reg2), + .I1(\FSM_onehot_fsm_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_reg_n_0_[1] ), + .O(\FSM_onehot_fsm[2]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'h04FF040404040404)) + \FSM_onehot_fsm[3]_i_1__2 + (.I0(\FSM_onehot_fsm[3]_i_2__0_n_0 ), + .I1(\FSM_onehot_fsm[4]_i_2__1_n_0 ), + .I2(\FSM_onehot_fsm[4]_i_3__0_n_0 ), + .I3(preset_valid_reg2), + .I4(new_txcoeff_req_reg2), + .I5(\FSM_onehot_fsm_reg_n_0_[1] ), + .O(\FSM_onehot_fsm[3]_i_1__2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT4 #( + .INIT(16'h04FF)) + \FSM_onehot_fsm[3]_i_2__0 + (.I0(out[0]), + .I1(out[1]), + .I2(adapt_done_cnt_reg_n_0), + .I3(\FSM_onehot_fsm_reg_n_0_[3] ), + .O(\FSM_onehot_fsm[3]_i_2__0_n_0 )); + LUT5 #( + .INIT(32'hFFBFFFFF)) + \FSM_onehot_fsm[4]_i_10__0 + (.I0(\FSM_onehot_fsm[4]_i_13__0_n_0 ), + .I1(converge_cnt[2]), + .I2(converge_cnt[20]), + .I3(converge_cnt[10]), + .I4(converge_cnt[0]), + .O(\FSM_onehot_fsm[4]_i_10__0_n_0 )); + LUT4 #( + .INIT(16'hEFFF)) + \FSM_onehot_fsm[4]_i_11__0 + (.I0(converge_cnt[2]), + .I1(converge_cnt[6]), + .I2(converge_cnt[8]), + .I3(converge_cnt[3]), + .O(\FSM_onehot_fsm[4]_i_11__0_n_0 )); + LUT5 #( + .INIT(32'hEFFFFFFF)) + \FSM_onehot_fsm[4]_i_12__0 + (.I0(\FSM_onehot_fsm[4]_i_13__0_n_0 ), + .I1(converge_cnt[14]), + .I2(converge_cnt[10]), + .I3(converge_cnt[21]), + .I4(converge_cnt[19]), + .O(\FSM_onehot_fsm[4]_i_12__0_n_0 )); + LUT4 #( + .INIT(16'hFF7F)) + \FSM_onehot_fsm[4]_i_13__0 + (.I0(converge_cnt[16]), + .I1(converge_cnt[11]), + .I2(converge_cnt[9]), + .I3(converge_cnt[5]), + .O(\FSM_onehot_fsm[4]_i_13__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFD0FFD0FFD0)) + \FSM_onehot_fsm[4]_i_1__2 + (.I0(\FSM_onehot_fsm[4]_i_2__1_n_0 ), + .I1(\FSM_onehot_fsm[4]_i_3__0_n_0 ), + .I2(\FSM_onehot_fsm_reg_n_0_[3] ), + .I3(\FSM_onehot_fsm[4]_i_4__0_n_0 ), + .I4(\FSM_onehot_fsm_reg_n_0_[4] ), + .I5(new_txcoeff_req_reg2), + .O(\FSM_onehot_fsm[4]_i_1__2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFBF)) + \FSM_onehot_fsm[4]_i_2__1 + (.I0(\FSM_onehot_fsm[4]_i_5__0_n_0 ), + .I1(converge_cnt[17]), + .I2(converge_cnt[18]), + .I3(converge_cnt[21]), + .I4(converge_cnt[8]), + .I5(\FSM_onehot_fsm[4]_i_6__0_n_0 ), + .O(\FSM_onehot_fsm[4]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'h0000000001000000)) + \FSM_onehot_fsm[4]_i_3__0 + (.I0(\FSM_onehot_fsm[4]_i_7__0_n_0 ), + .I1(converge_cnt[7]), + .I2(converge_cnt[1]), + .I3(converge_cnt[15]), + .I4(converge_cnt[13]), + .I5(\FSM_onehot_fsm[4]_i_8__0_n_0 ), + .O(\FSM_onehot_fsm[4]_i_3__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT4 #( + .INIT(16'h0400)) + \FSM_onehot_fsm[4]_i_4__0 + (.I0(out[0]), + .I1(out[1]), + .I2(adapt_done_cnt_reg_n_0), + .I3(\FSM_onehot_fsm_reg_n_0_[3] ), + .O(\FSM_onehot_fsm[4]_i_4__0_n_0 )); + LUT4 #( + .INIT(16'hFFF2)) + \FSM_onehot_fsm[4]_i_5__0 + (.I0(out[1]), + .I1(out[0]), + .I2(converge_cnt[7]), + .I3(converge_cnt[1]), + .O(\FSM_onehot_fsm[4]_i_5__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFB)) + \FSM_onehot_fsm[4]_i_6__0 + (.I0(\FSM_onehot_fsm[4]_i_9__0_n_0 ), + .I1(converge_cnt[19]), + .I2(converge_cnt[6]), + .I3(converge_cnt[3]), + .I4(converge_cnt[4]), + .I5(\FSM_onehot_fsm[4]_i_10__0_n_0 ), + .O(\FSM_onehot_fsm[4]_i_6__0_n_0 )); + LUT4 #( + .INIT(16'hDFFF)) + \FSM_onehot_fsm[4]_i_7__0 + (.I0(out[1]), + .I1(out[0]), + .I2(converge_cnt[17]), + .I3(converge_cnt[18]), + .O(\FSM_onehot_fsm[4]_i_7__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_fsm[4]_i_8__0 + (.I0(\FSM_onehot_fsm[4]_i_11__0_n_0 ), + .I1(converge_cnt[12]), + .I2(converge_cnt[20]), + .I3(converge_cnt[0]), + .I4(converge_cnt[4]), + .I5(\FSM_onehot_fsm[4]_i_12__0_n_0 ), + .O(\FSM_onehot_fsm[4]_i_8__0_n_0 )); + LUT4 #( + .INIT(16'hFFDF)) + \FSM_onehot_fsm[4]_i_9__0 + (.I0(converge_cnt[15]), + .I1(converge_cnt[13]), + .I2(converge_cnt[14]), + .I3(converge_cnt[12]), + .O(\FSM_onehot_fsm[4]_i_9__0_n_0 )); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDSE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[1]_i_1__2_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[2]_i_1__2_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[3]_i_1__2_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[4]_i_1__2_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h40FF4040)) + \FSM_onehot_fsm_rx[2]_i_1__0 + (.I0(out[1]), + .I1(Q[0]), + .I2(out[0]), + .I3(preset_done), + .I4(Q[1]), + .O(D[0])); + LUT6 #( + .INIT(64'hF444444444444444)) + \FSM_onehot_fsm_rx[5]_i_1__0 + (.I0(rxeqscan_new_txcoeff_done), + .I1(Q[3]), + .I2(\FSM_onehot_fsm_rx_reg[5] [2]), + .I3(\FSM_onehot_fsm_rx_reg[5] [0]), + .I4(\FSM_onehot_fsm_rx_reg[5] [1]), + .I5(Q[2]), + .O(D[1])); + LUT6 #( + .INIT(64'hFFFFFFFFFFE0E0E0)) + \FSM_onehot_fsm_rx[6]_i_1__0 + (.I0(out[1]), + .I1(out[0]), + .I2(Q[4]), + .I3(preset_done), + .I4(Q[1]), + .I5(\FSM_onehot_fsm_rx[6]_i_2__0_n_0 ), + .O(D[2])); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_fsm_rx[6]_i_2__0 + (.I0(rxeqscan_new_txcoeff_done), + .I1(Q[3]), + .O(\FSM_onehot_fsm_rx[6]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h000A0A0AF0F0F8F0)) + adapt_done_cnt_i_1__0 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .I5(adapt_done_cnt_i_2__0_n_0), + .O(adapt_done_cnt_i_1__0_n_0)); + LUT5 #( + .INIT(32'h00FF0101)) + adapt_done_cnt_i_2__0 + (.I0(\FSM_onehot_fsm_reg_n_0_[3] ), + .I1(\FSM_onehot_fsm_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_reg_n_0_[1] ), + .I3(new_txcoeff_req_reg2), + .I4(\FSM_onehot_fsm_reg_n_0_[4] ), + .O(adapt_done_cnt_i_2__0_n_0)); + FDRE #( + .INIT(1'b0)) + adapt_done_cnt_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(adapt_done_cnt_i_1__0_n_0), + .Q(adapt_done_cnt_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hF8000000)) + adapt_done_i_1__0 + (.I0(out[1]), + .I1(out[0]), + .I2(adapt_done_cnt_reg_n_0), + .I3(new_txcoeff_req_reg2), + .I4(\FSM_onehot_fsm_reg_n_0_[4] ), + .O(adapt_done)); + FDRE #( + .INIT(1'b0)) + adapt_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(adapt_done), + .Q(rxeqscan_adapt_done), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h44444044)) + \converge_cnt[0]_i_1__1 + (.I0(converge_cnt[0]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[0])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[10]_i_1__0 + (.I0(converge_cnt0[10]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[10])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[11]_i_1__0 + (.I0(converge_cnt0[11]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[11])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[12]_i_1__0 + (.I0(converge_cnt0[12]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[12])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[13]_i_1__0 + (.I0(converge_cnt0[13]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[13])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[14]_i_1__0 + (.I0(converge_cnt0[14]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[14])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[15]_i_1__0 + (.I0(converge_cnt0[15]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[15])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[16]_i_1__0 + (.I0(converge_cnt0[16]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[16])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[17]_i_1__0 + (.I0(converge_cnt0[17]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[17])); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[18]_i_1__0 + (.I0(converge_cnt0[18]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[18])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[19]_i_1__0 + (.I0(converge_cnt0[19]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[19])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[1]_i_1__0 + (.I0(converge_cnt0[1]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[1])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[20]_i_1__0 + (.I0(converge_cnt0[20]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[20])); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[21]_i_1__0 + (.I0(converge_cnt0[21]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[21])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[2]_i_1__0 + (.I0(converge_cnt0[2]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[2])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[3]_i_1__0 + (.I0(converge_cnt0[3]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[3])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[4]_i_1__0 + (.I0(converge_cnt0[4]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[4])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[5]_i_1__0 + (.I0(converge_cnt0[5]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[5])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[6]_i_1__0 + (.I0(converge_cnt0[6]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[6])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[7]_i_1__0 + (.I0(converge_cnt0[7]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[7])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[8]_i_1__0 + (.I0(converge_cnt0[8]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[8])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[9]_i_1__0 + (.I0(converge_cnt0[9]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[9])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[0]), + .Q(converge_cnt[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[10]), + .Q(converge_cnt[10]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[11]), + .Q(converge_cnt[11]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[12]), + .Q(converge_cnt[12]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[12]_i_2__0 + (.CI(\converge_cnt_reg[8]_i_2__0_n_0 ), + .CO({\converge_cnt_reg[12]_i_2__0_n_0 ,\converge_cnt_reg[12]_i_2__0_n_1 ,\converge_cnt_reg[12]_i_2__0_n_2 ,\converge_cnt_reg[12]_i_2__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[12:9]), + .S(converge_cnt[12:9])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[13]), + .Q(converge_cnt[13]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[14]), + .Q(converge_cnt[14]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[15]), + .Q(converge_cnt[15]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[16]), + .Q(converge_cnt[16]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[16]_i_2__0 + (.CI(\converge_cnt_reg[12]_i_2__0_n_0 ), + .CO({\converge_cnt_reg[16]_i_2__0_n_0 ,\converge_cnt_reg[16]_i_2__0_n_1 ,\converge_cnt_reg[16]_i_2__0_n_2 ,\converge_cnt_reg[16]_i_2__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[16:13]), + .S(converge_cnt[16:13])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[17]), + .Q(converge_cnt[17]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[18] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[18]), + .Q(converge_cnt[18]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[19] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[19]), + .Q(converge_cnt[19]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[1]), + .Q(converge_cnt[1]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[20] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[20]), + .Q(converge_cnt[20]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[20]_i_2__0 + (.CI(\converge_cnt_reg[16]_i_2__0_n_0 ), + .CO({\converge_cnt_reg[20]_i_2__0_n_0 ,\converge_cnt_reg[20]_i_2__0_n_1 ,\converge_cnt_reg[20]_i_2__0_n_2 ,\converge_cnt_reg[20]_i_2__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[20:17]), + .S(converge_cnt[20:17])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[21] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[21]), + .Q(converge_cnt[21]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[21]_i_2__0 + (.CI(\converge_cnt_reg[20]_i_2__0_n_0 ), + .CO(\NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED [3:1],converge_cnt0[21]}), + .S({1'b0,1'b0,1'b0,converge_cnt[21]})); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[2]), + .Q(converge_cnt[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[3]), + .Q(converge_cnt[3]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[4]), + .Q(converge_cnt[4]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[4]_i_2__0 + (.CI(1'b0), + .CO({\converge_cnt_reg[4]_i_2__0_n_0 ,\converge_cnt_reg[4]_i_2__0_n_1 ,\converge_cnt_reg[4]_i_2__0_n_2 ,\converge_cnt_reg[4]_i_2__0_n_3 }), + .CYINIT(converge_cnt[0]), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[4:1]), + .S(converge_cnt[4:1])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[5]), + .Q(converge_cnt[5]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[6]), + .Q(converge_cnt[6]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[7]), + .Q(converge_cnt[7]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[8]), + .Q(converge_cnt[8]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[8]_i_2__0 + (.CI(\converge_cnt_reg[4]_i_2__0_n_0 ), + .CO({\converge_cnt_reg[8]_i_2__0_n_0 ,\converge_cnt_reg[8]_i_2__0_n_1 ,\converge_cnt_reg[8]_i_2__0_n_2 ,\converge_cnt_reg[8]_i_2__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[8:5]), + .S(converge_cnt[8:5])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[9]), + .Q(converge_cnt[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [0]), + .Q(fs_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [1]), + .Q(fs_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [2]), + .Q(fs_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [3]), + .Q(fs_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [4]), + .Q(fs_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [5]), + .Q(fs_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[0]), + .Q(fs_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[1]), + .Q(fs_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[2]), + .Q(fs_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[3]), + .Q(fs_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[4]), + .Q(fs_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[5]), + .Q(fs_reg2[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [0]), + .Q(lf_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [1]), + .Q(lf_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [2]), + .Q(lf_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [3]), + .Q(lf_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [4]), + .Q(lf_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [5]), + .Q(lf_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[0]), + .Q(lf_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[1]), + .Q(lf_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[2]), + .Q(lf_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[3]), + .Q(lf_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[4]), + .Q(lf_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[5]), + .Q(lf_reg2[5]), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + new_txcoeff_done_i_1__0 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(new_txcoeff_req_reg2), + .O(new_txcoeff_done)); + FDRE #( + .INIT(1'b0)) + new_txcoeff_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(new_txcoeff_done), + .Q(rxeqscan_new_txcoeff_done), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE new_txcoeff_req_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(new_txcoeff_req_reg1_reg_0), + .Q(new_txcoeff_req_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE new_txcoeff_req_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(new_txcoeff_req_reg1), + .Q(new_txcoeff_req_reg2), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'hEA)) + preset_done_i_1__0 + (.I0(\FSM_onehot_fsm_reg_n_0_[2] ), + .I1(\FSM_onehot_fsm_reg_n_0_[1] ), + .I2(preset_valid_reg2), + .O(preset_done_1)); + FDRE #( + .INIT(1'b0)) + preset_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_done_1), + .Q(preset_done), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\preset_reg1_reg[2]_0 [0]), + .Q(preset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\preset_reg1_reg[2]_0 [1]), + .Q(preset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\preset_reg1_reg[2]_0 [2]), + .Q(preset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_reg1[0]), + .Q(preset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_reg1[1]), + .Q(preset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_reg1[2]), + .Q(preset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE preset_valid_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_valid), + .Q(preset_valid_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE preset_valid_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_valid_reg1), + .Q(preset_valid_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hA800FFFFA8000000)) + rxeq_adapt_done_i_1__0 + (.I0(rxeqscan_new_txcoeff_done), + .I1(rxeq_adapt_done_reg_reg_1), + .I2(rxeqscan_adapt_done), + .I3(Q[3]), + .I4(rxeq_adapt_done_reg), + .I5(USER_RXEQ_ADAPT_DONE), + .O(new_txcoeff_done_reg_0)); + LUT6 #( + .INIT(64'hFF00FF33AA00A800)) + rxeq_adapt_done_reg_i_1__0 + (.I0(rxeqscan_adapt_done), + .I1(rxeq_adapt_done_reg_reg), + .I2(rxeqscan_new_txcoeff_done), + .I3(Q[3]), + .I4(rxeq_adapt_done_reg_reg_0), + .I5(rxeq_adapt_done_reg_reg_1), + .O(adapt_done_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT2 #( + .INIT(4'h2)) + rxeq_new_txcoeff_req_i_1__0 + (.I0(Q[3]), + .I1(rxeqscan_new_txcoeff_done), + .O(rxeq_new_txcoeff_req)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [0]), + .Q(txcoeff_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [10]), + .Q(txcoeff_reg1[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [11]), + .Q(txcoeff_reg1[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [12]), + .Q(txcoeff_reg1[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [13]), + .Q(txcoeff_reg1[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [14]), + .Q(txcoeff_reg1[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [15]), + .Q(txcoeff_reg1[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [16]), + .Q(txcoeff_reg1[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [17]), + .Q(txcoeff_reg1[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [1]), + .Q(txcoeff_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [2]), + .Q(txcoeff_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [3]), + .Q(txcoeff_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [4]), + .Q(txcoeff_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [5]), + .Q(txcoeff_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [6]), + .Q(txcoeff_reg1[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [7]), + .Q(txcoeff_reg1[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [8]), + .Q(txcoeff_reg1[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [9]), + .Q(txcoeff_reg1[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[0]), + .Q(txcoeff_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[10]), + .Q(txcoeff_reg2[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[11]), + .Q(txcoeff_reg2[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[12]), + .Q(txcoeff_reg2[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[13]), + .Q(txcoeff_reg2[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[14]), + .Q(txcoeff_reg2[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[15]), + .Q(txcoeff_reg2[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[16]), + .Q(txcoeff_reg2[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[17]), + .Q(txcoeff_reg2[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[1]), + .Q(txcoeff_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[2]), + .Q(txcoeff_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[3]), + .Q(txcoeff_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[4]), + .Q(txcoeff_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[5]), + .Q(txcoeff_reg2[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[6]), + .Q(txcoeff_reg2[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[7]), + .Q(txcoeff_reg2[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[8]), + .Q(txcoeff_reg2[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[9]), + .Q(txcoeff_reg2[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [0]), + .Q(txpreset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [1]), + .Q(txpreset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [2]), + .Q(txpreset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [3]), + .Q(txpreset_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[0]), + .Q(txpreset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[1]), + .Q(txpreset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[2]), + .Q(txpreset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[3]), + .Q(txpreset_reg2[3]), + .R(RST_CPLLRESET)); +endmodule + +(* ORIG_REF_NAME = "pcie_7x_0_rxeq_scan" *) +module pcie_7x_0_pcie_7x_0_rxeq_scan_59 + (D, + rxeq_new_txcoeff_req, + adapt_done_reg_0, + new_txcoeff_done_reg_0, + RST_CPLLRESET, + pipe_pclk_in, + new_txcoeff_req_reg1_reg_0, + rxeq_preset_valid, + out, + Q, + \FSM_onehot_fsm_rx_reg[5] , + rxeq_adapt_done_reg_reg, + rxeq_adapt_done_reg_reg_0, + rxeq_adapt_done_reg_reg_1, + rxeq_adapt_done_reg, + USER_RXEQ_ADAPT_DONE, + \preset_reg1_reg[2]_0 , + \txpreset_reg1_reg[3]_0 , + \txcoeff_reg1_reg[17]_0 , + \fs_reg1_reg[5]_0 , + \lf_reg1_reg[5]_0 ); + output [2:0]D; + output rxeq_new_txcoeff_req; + output adapt_done_reg_0; + output new_txcoeff_done_reg_0; + input RST_CPLLRESET; + input pipe_pclk_in; + input new_txcoeff_req_reg1_reg_0; + input rxeq_preset_valid; + input [1:0]out; + input [4:0]Q; + input [2:0]\FSM_onehot_fsm_rx_reg[5] ; + input rxeq_adapt_done_reg_reg; + input rxeq_adapt_done_reg_reg_0; + input rxeq_adapt_done_reg_reg_1; + input rxeq_adapt_done_reg; + input USER_RXEQ_ADAPT_DONE; + input [2:0]\preset_reg1_reg[2]_0 ; + input [3:0]\txpreset_reg1_reg[3]_0 ; + input [17:0]\txcoeff_reg1_reg[17]_0 ; + input [5:0]\fs_reg1_reg[5]_0 ; + input [5:0]\lf_reg1_reg[5]_0 ; + + wire [2:0]D; + wire \FSM_onehot_fsm[1]_i_1__1_n_0 ; + wire \FSM_onehot_fsm[2]_i_1__1_n_0 ; + wire \FSM_onehot_fsm[3]_i_1__1_n_0 ; + wire \FSM_onehot_fsm[3]_i_2_n_0 ; + wire \FSM_onehot_fsm[4]_i_10_n_0 ; + wire \FSM_onehot_fsm[4]_i_11_n_0 ; + wire \FSM_onehot_fsm[4]_i_12_n_0 ; + wire \FSM_onehot_fsm[4]_i_13_n_0 ; + wire \FSM_onehot_fsm[4]_i_1__1_n_0 ; + wire \FSM_onehot_fsm[4]_i_2__0_n_0 ; + wire \FSM_onehot_fsm[4]_i_3_n_0 ; + wire \FSM_onehot_fsm[4]_i_4_n_0 ; + wire \FSM_onehot_fsm[4]_i_5_n_0 ; + wire \FSM_onehot_fsm[4]_i_6_n_0 ; + wire \FSM_onehot_fsm[4]_i_7_n_0 ; + wire \FSM_onehot_fsm[4]_i_8_n_0 ; + wire \FSM_onehot_fsm[4]_i_9_n_0 ; + wire \FSM_onehot_fsm_reg_n_0_[1] ; + wire \FSM_onehot_fsm_reg_n_0_[2] ; + wire \FSM_onehot_fsm_reg_n_0_[3] ; + wire \FSM_onehot_fsm_reg_n_0_[4] ; + wire \FSM_onehot_fsm_rx[6]_i_2_n_0 ; + wire [2:0]\FSM_onehot_fsm_rx_reg[5] ; + wire [4:0]Q; + wire RST_CPLLRESET; + wire USER_RXEQ_ADAPT_DONE; + wire adapt_done; + wire adapt_done_cnt_i_1_n_0; + wire adapt_done_cnt_i_2_n_0; + wire adapt_done_cnt_reg_n_0; + wire adapt_done_reg_0; + wire [21:0]converge_cnt; + wire [21:1]converge_cnt0; + wire [21:0]converge_cnt_0; + wire \converge_cnt_reg[12]_i_2_n_0 ; + wire \converge_cnt_reg[12]_i_2_n_1 ; + wire \converge_cnt_reg[12]_i_2_n_2 ; + wire \converge_cnt_reg[12]_i_2_n_3 ; + wire \converge_cnt_reg[16]_i_2_n_0 ; + wire \converge_cnt_reg[16]_i_2_n_1 ; + wire \converge_cnt_reg[16]_i_2_n_2 ; + wire \converge_cnt_reg[16]_i_2_n_3 ; + wire \converge_cnt_reg[20]_i_2_n_0 ; + wire \converge_cnt_reg[20]_i_2_n_1 ; + wire \converge_cnt_reg[20]_i_2_n_2 ; + wire \converge_cnt_reg[20]_i_2_n_3 ; + wire \converge_cnt_reg[4]_i_2_n_0 ; + wire \converge_cnt_reg[4]_i_2_n_1 ; + wire \converge_cnt_reg[4]_i_2_n_2 ; + wire \converge_cnt_reg[4]_i_2_n_3 ; + wire \converge_cnt_reg[8]_i_2_n_0 ; + wire \converge_cnt_reg[8]_i_2_n_1 ; + wire \converge_cnt_reg[8]_i_2_n_2 ; + wire \converge_cnt_reg[8]_i_2_n_3 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]fs_reg1; + wire [5:0]\fs_reg1_reg[5]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]fs_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]lf_reg1; + wire [5:0]\lf_reg1_reg[5]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]lf_reg2; + wire new_txcoeff_done; + wire new_txcoeff_done_reg_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire new_txcoeff_req_reg1; + wire new_txcoeff_req_reg1_reg_0; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire new_txcoeff_req_reg2; + wire [1:0]out; + wire pipe_pclk_in; + wire preset_done; + wire preset_done_1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]preset_reg1; + wire [2:0]\preset_reg1_reg[2]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]preset_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire preset_valid_reg1; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire preset_valid_reg2; + wire rxeq_adapt_done_reg; + wire rxeq_adapt_done_reg_reg; + wire rxeq_adapt_done_reg_reg_0; + wire rxeq_adapt_done_reg_reg_1; + wire rxeq_new_txcoeff_req; + wire rxeq_preset_valid; + wire rxeqscan_adapt_done; + wire rxeqscan_new_txcoeff_done; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]txcoeff_reg1; + wire [17:0]\txcoeff_reg1_reg[17]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]txcoeff_reg2; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txpreset_reg1; + wire [3:0]\txpreset_reg1_reg[3]_0 ; + (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txpreset_reg2; + wire [3:0]\NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED ; + wire [3:1]\NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED ; + + LUT6 #( + .INIT(64'h0F00AFAF0F11AFBB)) + \FSM_onehot_fsm[1]_i_1__1 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(preset_valid_reg2), + .I3(\FSM_onehot_fsm_reg_n_0_[2] ), + .I4(new_txcoeff_req_reg2), + .I5(\FSM_onehot_fsm_reg_n_0_[1] ), + .O(\FSM_onehot_fsm[1]_i_1__1_n_0 )); + LUT3 #( + .INIT(8'hA8)) + \FSM_onehot_fsm[2]_i_1__1 + (.I0(preset_valid_reg2), + .I1(\FSM_onehot_fsm_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_reg_n_0_[1] ), + .O(\FSM_onehot_fsm[2]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'h04FF040404040404)) + \FSM_onehot_fsm[3]_i_1__1 + (.I0(\FSM_onehot_fsm[3]_i_2_n_0 ), + .I1(\FSM_onehot_fsm[4]_i_2__0_n_0 ), + .I2(\FSM_onehot_fsm[4]_i_3_n_0 ), + .I3(preset_valid_reg2), + .I4(new_txcoeff_req_reg2), + .I5(\FSM_onehot_fsm_reg_n_0_[1] ), + .O(\FSM_onehot_fsm[3]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT4 #( + .INIT(16'h04FF)) + \FSM_onehot_fsm[3]_i_2 + (.I0(out[0]), + .I1(out[1]), + .I2(adapt_done_cnt_reg_n_0), + .I3(\FSM_onehot_fsm_reg_n_0_[3] ), + .O(\FSM_onehot_fsm[3]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFBFFFFF)) + \FSM_onehot_fsm[4]_i_10 + (.I0(\FSM_onehot_fsm[4]_i_13_n_0 ), + .I1(converge_cnt[2]), + .I2(converge_cnt[20]), + .I3(converge_cnt[10]), + .I4(converge_cnt[0]), + .O(\FSM_onehot_fsm[4]_i_10_n_0 )); + LUT4 #( + .INIT(16'hEFFF)) + \FSM_onehot_fsm[4]_i_11 + (.I0(converge_cnt[2]), + .I1(converge_cnt[6]), + .I2(converge_cnt[8]), + .I3(converge_cnt[3]), + .O(\FSM_onehot_fsm[4]_i_11_n_0 )); + LUT5 #( + .INIT(32'hEFFFFFFF)) + \FSM_onehot_fsm[4]_i_12 + (.I0(\FSM_onehot_fsm[4]_i_13_n_0 ), + .I1(converge_cnt[14]), + .I2(converge_cnt[10]), + .I3(converge_cnt[21]), + .I4(converge_cnt[19]), + .O(\FSM_onehot_fsm[4]_i_12_n_0 )); + LUT4 #( + .INIT(16'hFF7F)) + \FSM_onehot_fsm[4]_i_13 + (.I0(converge_cnt[16]), + .I1(converge_cnt[11]), + .I2(converge_cnt[9]), + .I3(converge_cnt[5]), + .O(\FSM_onehot_fsm[4]_i_13_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFD0FFD0FFD0)) + \FSM_onehot_fsm[4]_i_1__1 + (.I0(\FSM_onehot_fsm[4]_i_2__0_n_0 ), + .I1(\FSM_onehot_fsm[4]_i_3_n_0 ), + .I2(\FSM_onehot_fsm_reg_n_0_[3] ), + .I3(\FSM_onehot_fsm[4]_i_4_n_0 ), + .I4(\FSM_onehot_fsm_reg_n_0_[4] ), + .I5(new_txcoeff_req_reg2), + .O(\FSM_onehot_fsm[4]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFBF)) + \FSM_onehot_fsm[4]_i_2__0 + (.I0(\FSM_onehot_fsm[4]_i_5_n_0 ), + .I1(converge_cnt[17]), + .I2(converge_cnt[18]), + .I3(converge_cnt[21]), + .I4(converge_cnt[8]), + .I5(\FSM_onehot_fsm[4]_i_6_n_0 ), + .O(\FSM_onehot_fsm[4]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h0000000001000000)) + \FSM_onehot_fsm[4]_i_3 + (.I0(\FSM_onehot_fsm[4]_i_7_n_0 ), + .I1(converge_cnt[7]), + .I2(converge_cnt[1]), + .I3(converge_cnt[15]), + .I4(converge_cnt[13]), + .I5(\FSM_onehot_fsm[4]_i_8_n_0 ), + .O(\FSM_onehot_fsm[4]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT4 #( + .INIT(16'h0400)) + \FSM_onehot_fsm[4]_i_4 + (.I0(out[0]), + .I1(out[1]), + .I2(adapt_done_cnt_reg_n_0), + .I3(\FSM_onehot_fsm_reg_n_0_[3] ), + .O(\FSM_onehot_fsm[4]_i_4_n_0 )); + LUT4 #( + .INIT(16'hFFF2)) + \FSM_onehot_fsm[4]_i_5 + (.I0(out[1]), + .I1(out[0]), + .I2(converge_cnt[7]), + .I3(converge_cnt[1]), + .O(\FSM_onehot_fsm[4]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFB)) + \FSM_onehot_fsm[4]_i_6 + (.I0(\FSM_onehot_fsm[4]_i_9_n_0 ), + .I1(converge_cnt[19]), + .I2(converge_cnt[6]), + .I3(converge_cnt[3]), + .I4(converge_cnt[4]), + .I5(\FSM_onehot_fsm[4]_i_10_n_0 ), + .O(\FSM_onehot_fsm[4]_i_6_n_0 )); + LUT4 #( + .INIT(16'hDFFF)) + \FSM_onehot_fsm[4]_i_7 + (.I0(out[1]), + .I1(out[0]), + .I2(converge_cnt[17]), + .I3(converge_cnt[18]), + .O(\FSM_onehot_fsm[4]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_fsm[4]_i_8 + (.I0(\FSM_onehot_fsm[4]_i_11_n_0 ), + .I1(converge_cnt[12]), + .I2(converge_cnt[20]), + .I3(converge_cnt[0]), + .I4(converge_cnt[4]), + .I5(\FSM_onehot_fsm[4]_i_12_n_0 ), + .O(\FSM_onehot_fsm[4]_i_8_n_0 )); + LUT4 #( + .INIT(16'hFFDF)) + \FSM_onehot_fsm[4]_i_9 + (.I0(converge_cnt[15]), + .I1(converge_cnt[13]), + .I2(converge_cnt[14]), + .I3(converge_cnt[12]), + .O(\FSM_onehot_fsm[4]_i_9_n_0 )); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDSE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[1]_i_1__1_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[1] ), + .S(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[2]_i_1__1_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[2] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[3]_i_1__1_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[3] ), + .R(RST_CPLLRESET)); + (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_fsm_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\FSM_onehot_fsm[4]_i_1__1_n_0 ), + .Q(\FSM_onehot_fsm_reg_n_0_[4] ), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h40FF4040)) + \FSM_onehot_fsm_rx[2]_i_1 + (.I0(out[1]), + .I1(Q[0]), + .I2(out[0]), + .I3(preset_done), + .I4(Q[1]), + .O(D[0])); + LUT6 #( + .INIT(64'hF444444444444444)) + \FSM_onehot_fsm_rx[5]_i_1 + (.I0(rxeqscan_new_txcoeff_done), + .I1(Q[3]), + .I2(\FSM_onehot_fsm_rx_reg[5] [2]), + .I3(\FSM_onehot_fsm_rx_reg[5] [0]), + .I4(\FSM_onehot_fsm_rx_reg[5] [1]), + .I5(Q[2]), + .O(D[1])); + LUT6 #( + .INIT(64'hFFFFFFFFFFE0E0E0)) + \FSM_onehot_fsm_rx[6]_i_1 + (.I0(out[1]), + .I1(out[0]), + .I2(Q[4]), + .I3(preset_done), + .I4(Q[1]), + .I5(\FSM_onehot_fsm_rx[6]_i_2_n_0 ), + .O(D[2])); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_fsm_rx[6]_i_2 + (.I0(rxeqscan_new_txcoeff_done), + .I1(Q[3]), + .O(\FSM_onehot_fsm_rx[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'h000A0A0AF0F0F8F0)) + adapt_done_cnt_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .I5(adapt_done_cnt_i_2_n_0), + .O(adapt_done_cnt_i_1_n_0)); + LUT5 #( + .INIT(32'h00FF0101)) + adapt_done_cnt_i_2 + (.I0(\FSM_onehot_fsm_reg_n_0_[3] ), + .I1(\FSM_onehot_fsm_reg_n_0_[2] ), + .I2(\FSM_onehot_fsm_reg_n_0_[1] ), + .I3(new_txcoeff_req_reg2), + .I4(\FSM_onehot_fsm_reg_n_0_[4] ), + .O(adapt_done_cnt_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + adapt_done_cnt_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(adapt_done_cnt_i_1_n_0), + .Q(adapt_done_cnt_reg_n_0), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'hF8000000)) + adapt_done_i_1 + (.I0(out[1]), + .I1(out[0]), + .I2(adapt_done_cnt_reg_n_0), + .I3(new_txcoeff_req_reg2), + .I4(\FSM_onehot_fsm_reg_n_0_[4] ), + .O(adapt_done)); + FDRE #( + .INIT(1'b0)) + adapt_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(adapt_done), + .Q(rxeqscan_adapt_done), + .R(RST_CPLLRESET)); + LUT5 #( + .INIT(32'h44444044)) + \converge_cnt[0]_i_1 + (.I0(converge_cnt[0]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[0])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[10]_i_1 + (.I0(converge_cnt0[10]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[10])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[11]_i_1 + (.I0(converge_cnt0[11]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[11])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[12]_i_1 + (.I0(converge_cnt0[12]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[12])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[13]_i_1 + (.I0(converge_cnt0[13]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[13])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[14]_i_1 + (.I0(converge_cnt0[14]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[14])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[15]_i_1 + (.I0(converge_cnt0[15]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[15])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[16]_i_1 + (.I0(converge_cnt0[16]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[16])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[17]_i_1 + (.I0(converge_cnt0[17]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[17])); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[18]_i_1 + (.I0(converge_cnt0[18]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[18])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[19]_i_1 + (.I0(converge_cnt0[19]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[19])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[1]_i_1 + (.I0(converge_cnt0[1]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[1])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[20]_i_1 + (.I0(converge_cnt0[20]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[20])); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[21]_i_1 + (.I0(converge_cnt0[21]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[21])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[2]_i_1 + (.I0(converge_cnt0[2]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[2])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[3]_i_1 + (.I0(converge_cnt0[3]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[3])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[4]_i_1 + (.I0(converge_cnt0[4]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[4])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[5]_i_1 + (.I0(converge_cnt0[5]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[5])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[6]_i_1 + (.I0(converge_cnt0[6]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[6])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[7]_i_1 + (.I0(converge_cnt0[7]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[7])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[8]_i_1 + (.I0(converge_cnt0[8]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[8])); + LUT5 #( + .INIT(32'h88888088)) + \converge_cnt[9]_i_1 + (.I0(converge_cnt0[9]), + .I1(\FSM_onehot_fsm_reg_n_0_[3] ), + .I2(adapt_done_cnt_reg_n_0), + .I3(out[1]), + .I4(out[0]), + .O(converge_cnt_0[9])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[0]), + .Q(converge_cnt[0]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[10]), + .Q(converge_cnt[10]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[11]), + .Q(converge_cnt[11]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[12]), + .Q(converge_cnt[12]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[12]_i_2 + (.CI(\converge_cnt_reg[8]_i_2_n_0 ), + .CO({\converge_cnt_reg[12]_i_2_n_0 ,\converge_cnt_reg[12]_i_2_n_1 ,\converge_cnt_reg[12]_i_2_n_2 ,\converge_cnt_reg[12]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[12:9]), + .S(converge_cnt[12:9])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[13]), + .Q(converge_cnt[13]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[14]), + .Q(converge_cnt[14]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[15]), + .Q(converge_cnt[15]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[16]), + .Q(converge_cnt[16]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[16]_i_2 + (.CI(\converge_cnt_reg[12]_i_2_n_0 ), + .CO({\converge_cnt_reg[16]_i_2_n_0 ,\converge_cnt_reg[16]_i_2_n_1 ,\converge_cnt_reg[16]_i_2_n_2 ,\converge_cnt_reg[16]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[16:13]), + .S(converge_cnt[16:13])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[17]), + .Q(converge_cnt[17]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[18] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[18]), + .Q(converge_cnt[18]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[19] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[19]), + .Q(converge_cnt[19]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[1]), + .Q(converge_cnt[1]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[20] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[20]), + .Q(converge_cnt[20]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[20]_i_2 + (.CI(\converge_cnt_reg[16]_i_2_n_0 ), + .CO({\converge_cnt_reg[20]_i_2_n_0 ,\converge_cnt_reg[20]_i_2_n_1 ,\converge_cnt_reg[20]_i_2_n_2 ,\converge_cnt_reg[20]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[20:17]), + .S(converge_cnt[20:17])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[21] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[21]), + .Q(converge_cnt[21]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[21]_i_2 + (.CI(\converge_cnt_reg[20]_i_2_n_0 ), + .CO(\NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED [3:1],converge_cnt0[21]}), + .S({1'b0,1'b0,1'b0,converge_cnt[21]})); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[2]), + .Q(converge_cnt[2]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[3]), + .Q(converge_cnt[3]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[4]), + .Q(converge_cnt[4]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[4]_i_2 + (.CI(1'b0), + .CO({\converge_cnt_reg[4]_i_2_n_0 ,\converge_cnt_reg[4]_i_2_n_1 ,\converge_cnt_reg[4]_i_2_n_2 ,\converge_cnt_reg[4]_i_2_n_3 }), + .CYINIT(converge_cnt[0]), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[4:1]), + .S(converge_cnt[4:1])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[5]), + .Q(converge_cnt[5]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[6]), + .Q(converge_cnt[6]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[7]), + .Q(converge_cnt[7]), + .R(RST_CPLLRESET)); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[8]), + .Q(converge_cnt[8]), + .R(RST_CPLLRESET)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \converge_cnt_reg[8]_i_2 + (.CI(\converge_cnt_reg[4]_i_2_n_0 ), + .CO({\converge_cnt_reg[8]_i_2_n_0 ,\converge_cnt_reg[8]_i_2_n_1 ,\converge_cnt_reg[8]_i_2_n_2 ,\converge_cnt_reg[8]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(converge_cnt0[8:5]), + .S(converge_cnt[8:5])); + FDRE #( + .INIT(1'b0)) + \converge_cnt_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(converge_cnt_0[9]), + .Q(converge_cnt[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [0]), + .Q(fs_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [1]), + .Q(fs_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [2]), + .Q(fs_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [3]), + .Q(fs_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [4]), + .Q(fs_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\fs_reg1_reg[5]_0 [5]), + .Q(fs_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[0]), + .Q(fs_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[1]), + .Q(fs_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[2]), + .Q(fs_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[3]), + .Q(fs_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[4]), + .Q(fs_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \fs_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(fs_reg1[5]), + .Q(fs_reg2[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [0]), + .Q(lf_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [1]), + .Q(lf_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [2]), + .Q(lf_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [3]), + .Q(lf_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [4]), + .Q(lf_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\lf_reg1_reg[5]_0 [5]), + .Q(lf_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[0]), + .Q(lf_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[1]), + .Q(lf_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[2]), + .Q(lf_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[3]), + .Q(lf_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[4]), + .Q(lf_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \lf_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(lf_reg1[5]), + .Q(lf_reg2[5]), + .R(RST_CPLLRESET)); + LUT2 #( + .INIT(4'h8)) + new_txcoeff_done_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[4] ), + .I1(new_txcoeff_req_reg2), + .O(new_txcoeff_done)); + FDRE #( + .INIT(1'b0)) + new_txcoeff_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(new_txcoeff_done), + .Q(rxeqscan_new_txcoeff_done), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE new_txcoeff_req_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(new_txcoeff_req_reg1_reg_0), + .Q(new_txcoeff_req_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE new_txcoeff_req_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(new_txcoeff_req_reg1), + .Q(new_txcoeff_req_reg2), + .R(RST_CPLLRESET)); + LUT3 #( + .INIT(8'hEA)) + preset_done_i_1 + (.I0(\FSM_onehot_fsm_reg_n_0_[2] ), + .I1(\FSM_onehot_fsm_reg_n_0_[1] ), + .I2(preset_valid_reg2), + .O(preset_done_1)); + FDRE #( + .INIT(1'b0)) + preset_done_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_done_1), + .Q(preset_done), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\preset_reg1_reg[2]_0 [0]), + .Q(preset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\preset_reg1_reg[2]_0 [1]), + .Q(preset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\preset_reg1_reg[2]_0 [2]), + .Q(preset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_reg1[0]), + .Q(preset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_reg1[1]), + .Q(preset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \preset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_reg1[2]), + .Q(preset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE preset_valid_reg1_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(rxeq_preset_valid), + .Q(preset_valid_reg1), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE preset_valid_reg2_reg + (.C(pipe_pclk_in), + .CE(1'b1), + .D(preset_valid_reg1), + .Q(preset_valid_reg2), + .R(RST_CPLLRESET)); + LUT6 #( + .INIT(64'hA800FFFFA8000000)) + rxeq_adapt_done_i_1 + (.I0(rxeqscan_new_txcoeff_done), + .I1(rxeq_adapt_done_reg_reg_1), + .I2(rxeqscan_adapt_done), + .I3(Q[3]), + .I4(rxeq_adapt_done_reg), + .I5(USER_RXEQ_ADAPT_DONE), + .O(new_txcoeff_done_reg_0)); + LUT6 #( + .INIT(64'hFF00FF33AA00A800)) + rxeq_adapt_done_reg_i_1 + (.I0(rxeqscan_adapt_done), + .I1(rxeq_adapt_done_reg_reg), + .I2(rxeqscan_new_txcoeff_done), + .I3(Q[3]), + .I4(rxeq_adapt_done_reg_reg_0), + .I5(rxeq_adapt_done_reg_reg_1), + .O(adapt_done_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT2 #( + .INIT(4'h2)) + rxeq_new_txcoeff_req_i_1 + (.I0(Q[3]), + .I1(rxeqscan_new_txcoeff_done), + .O(rxeq_new_txcoeff_req)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [0]), + .Q(txcoeff_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [10]), + .Q(txcoeff_reg1[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [11]), + .Q(txcoeff_reg1[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [12]), + .Q(txcoeff_reg1[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [13]), + .Q(txcoeff_reg1[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [14]), + .Q(txcoeff_reg1[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [15]), + .Q(txcoeff_reg1[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [16]), + .Q(txcoeff_reg1[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [17]), + .Q(txcoeff_reg1[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [1]), + .Q(txcoeff_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [2]), + .Q(txcoeff_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [3]), + .Q(txcoeff_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [4]), + .Q(txcoeff_reg1[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [5]), + .Q(txcoeff_reg1[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [6]), + .Q(txcoeff_reg1[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [7]), + .Q(txcoeff_reg1[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [8]), + .Q(txcoeff_reg1[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg1_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txcoeff_reg1_reg[17]_0 [9]), + .Q(txcoeff_reg1[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[0]), + .Q(txcoeff_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[10] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[10]), + .Q(txcoeff_reg2[10]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[11] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[11]), + .Q(txcoeff_reg2[11]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[12] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[12]), + .Q(txcoeff_reg2[12]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[13] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[13]), + .Q(txcoeff_reg2[13]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[14] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[14]), + .Q(txcoeff_reg2[14]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[15] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[15]), + .Q(txcoeff_reg2[15]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[16] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[16]), + .Q(txcoeff_reg2[16]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[17] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[17]), + .Q(txcoeff_reg2[17]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[1]), + .Q(txcoeff_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[2]), + .Q(txcoeff_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[3]), + .Q(txcoeff_reg2[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[4] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[4]), + .Q(txcoeff_reg2[4]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[5] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[5]), + .Q(txcoeff_reg2[5]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[6] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[6]), + .Q(txcoeff_reg2[6]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[7] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[7]), + .Q(txcoeff_reg2[7]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[8] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[8]), + .Q(txcoeff_reg2[8]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txcoeff_reg2_reg[9] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txcoeff_reg1[9]), + .Q(txcoeff_reg2[9]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [0]), + .Q(txpreset_reg1[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [1]), + .Q(txpreset_reg1[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [2]), + .Q(txpreset_reg1[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg1_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(\txpreset_reg1_reg[3]_0 [3]), + .Q(txpreset_reg1[3]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[0] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[0]), + .Q(txpreset_reg2[0]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[1] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[1]), + .Q(txpreset_reg2[1]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[2] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[2]), + .Q(txpreset_reg2[2]), + .R(RST_CPLLRESET)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHIFT_EXTRACT = "NO" *) + FDRE \txpreset_reg2_reg[3] + (.C(pipe_pclk_in), + .CE(1'b1), + .D(txpreset_reg1[3]), + .Q(txpreset_reg2[3]), + .R(RST_CPLLRESET)); +endmodule + +(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* SIM_ASSERT_CHK = "0" *) +(* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) +(* keep_hierarchy = "true" *) (* xpm_cdc = "SINGLE" *) +module pcie_7x_0_xpm_cdc_single + (src_clk, + src_in, + dest_clk, + dest_out); + input src_clk; + input src_in; + input dest_clk; + output dest_out; + + wire dest_clk; + wire src_in; + (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff; + + assign dest_out = syncstages_ff[1]; + (* ASYNC_REG *) + (* KEEP = "true" *) + (* XPM_CDC = "SINGLE" *) + FDRE \syncstages_ff_reg[0] + (.C(dest_clk), + .CE(1'b1), + .D(src_in), + .Q(syncstages_ff[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "true" *) + (* XPM_CDC = "SINGLE" *) + FDRE \syncstages_ff_reg[1] + (.C(dest_clk), + .CE(1'b1), + .D(syncstages_ff[0]), + .Q(syncstages_ff[1]), + .R(1'b0)); +endmodule + +(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) +(* SIM_ASSERT_CHK = "0" *) (* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) +(* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SINGLE" *) +module pcie_7x_0_xpm_cdc_single__2 + (src_clk, + src_in, + dest_clk, + dest_out); + input src_clk; + input src_in; + input dest_clk; + output dest_out; + + wire dest_clk; + wire src_in; + (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff; + + assign dest_out = syncstages_ff[1]; + (* ASYNC_REG *) + (* KEEP = "true" *) + (* XPM_CDC = "SINGLE" *) + FDRE \syncstages_ff_reg[0] + (.C(dest_clk), + .CE(1'b1), + .D(src_in), + .Q(syncstages_ff[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "true" *) + (* XPM_CDC = "SINGLE" *) + FDRE \syncstages_ff_reg[1] + (.C(dest_clk), + .CE(1'b1), + .D(syncstages_ff[0]), + .Q(syncstages_ff[1]), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_sim_netlist.vhdl b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_sim_netlist.vhdl new file mode 100644 index 0000000..de1f92b --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_sim_netlist.vhdl @@ -0,0 +1,79081 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +-- Date : Wed Jul 20 13:38:01 2022 +-- Host : DESKTOP-4NLVFC8 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top pcie_7x_0 -prefix +-- pcie_7x_0_ pcie_7x_0_sim_netlist.vhdl +-- Design : pcie_7x_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z045ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \pcie_7x_0_BRAM_TDP_MACRO_viv_\ is + port ( + rdata : out STD_LOGIC_VECTOR ( 5 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 5 downto 0 ) + ); +end \pcie_7x_0_BRAM_TDP_MACRO_viv_\; + +architecture STRUCTURE of \pcie_7x_0_BRAM_TDP_MACRO_viv_\ is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_60\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_61\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_75\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE"; +begin +\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 1, + 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMTXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMTXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 6) => B"00", + DIADI(5 downto 0) => wdata(5 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 0) => B"0000", + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_60\, + DOBDO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_61\, + DOBDO(5 downto 0) => rdata(5 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_75\, + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_tx_wen, + ENBWREN => mim_tx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_11 is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_11 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_11; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_11 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE"; +begin +\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + 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=> X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMTXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMTXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => wdata(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => wdata(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => rdata(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => rdata(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_tx_wen, + ENBWREN => mim_tx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_12 is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_12 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_12; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_12 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE"; +begin +\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMTXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMTXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => wdata(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => wdata(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => rdata(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => rdata(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_tx_wen, + ENBWREN => mim_tx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_13 is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_13 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_13; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_13 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + 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IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMTXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMTXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => wdata(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => wdata(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => rdata(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => rdata(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_tx_wen, + ENBWREN => mim_tx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_14 is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_14 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_14; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_14 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE"; +begin +\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMTXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMTXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => wdata(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => wdata(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => rdata(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => rdata(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_tx_wen, + ENBWREN => mim_tx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_15 is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_15 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_15; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_15 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE"; +begin +\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMTXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMTXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => wdata(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => wdata(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => rdata(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => rdata(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_tx_wen, + ENBWREN => mim_tx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_16 is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_16 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_16; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_16 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 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"NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMTXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMTXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => wdata(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => wdata(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => rdata(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => rdata(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_tx_wen, + ENBWREN => mim_tx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_17 is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_17 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_17; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_17 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE"; +begin +\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMTXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMTXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => wdata(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => wdata(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => rdata(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => rdata(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_tx_wen, + ENBWREN => mim_tx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_26 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_26 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_26; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_26 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_60\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_61\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_62\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_75\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMRXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMRXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 5) => B"000", + DIADI(4 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(4 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 0) => B"0000", + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_60\, + DOBDO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_61\, + DOBDO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_62\, + DOBDO(4 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(4 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_75\, + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_rx_wen, + ENBWREN => mim_rx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_27 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_27 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_27; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_27 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMRXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMRXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_rx_wen, + ENBWREN => mim_rx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_28 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_28 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_28; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_28 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE"; +begin +\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMRXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMRXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_rx_wen, + ENBWREN => mim_rx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_29 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_29 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_29; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_29 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE"; +begin +\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMRXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMRXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_rx_wen, + ENBWREN => mim_rx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_30 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_30 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_30; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_30 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMRXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMRXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_rx_wen, + ENBWREN => mim_rx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_31 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_31 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_31; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_31 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMRXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMRXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_rx_wen, + ENBWREN => mim_rx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_32 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_32 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_32; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_32 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMRXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMRXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_rx_wen, + ENBWREN => mim_rx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_BRAM_TDP_MACRO_33 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_BRAM_TDP_MACRO_33 : entity is "BRAM_TDP_MACRO"; +end pcie_7x_0_BRAM_TDP_MACRO_33; + +architecture STRUCTURE of pcie_7x_0_BRAM_TDP_MACRO_33 is + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC; + signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "RSTREG", + RSTREG_PRIORITY_B => "RSTREG", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "NO_CHANGE", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => MIMRXWADDR(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => MIMRXRADDR(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => pipe_userclk1_in, + CLKBWRCLK => pipe_userclk1_in, + DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 8), + DIADI(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(7 downto 0), + DIBDI(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 8), + DIBDI(7 downto 0) => B"00000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 8), + DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\, + DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\, + DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\, + DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\, + DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\, + DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\, + DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\, + DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\, + DOBDO(31 downto 8) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(7 downto 0), + DOPADOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 1), + DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\, + DOPBDOP(3 downto 1) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8), + ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => mim_rx_wen, + ENBWREN => mim_rx_ren, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '1', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"1111", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_axi_basic_rx_null_gen is + port ( + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \reg_tkeep[7]_i_7_0\ : out STD_LOGIC; + \reg_pkt_len_counter_reg[3]_0\ : out STD_LOGIC; + \reg_pkt_len_counter_reg[0]_0\ : out STD_LOGIC; + null_mux_sel_reg : out STD_LOGIC; + null_mux_sel_reg_0 : out STD_LOGIC; + S : out STD_LOGIC_VECTOR ( 1 downto 0 ); + cur_state_reg_0 : in STD_LOGIC; + pipe_userclk2_in : in STD_LOGIC; + null_mux_sel : in STD_LOGIC; + \m_axis_rx_tuser_reg[19]\ : in STD_LOGIC; + new_pkt_len : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axis_rx_tready : in STD_LOGIC; + null_mux_sel_reg_1 : in STD_LOGIC; + cur_state_reg_1 : in STD_LOGIC; + m_axis_rx_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + \m_axis_rx_tuser_reg[21]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_axi_basic_rx_null_gen; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_axi_basic_rx_null_gen is + signal cur_state : STD_LOGIC; + signal next_state : STD_LOGIC; + signal pkt_len_counter : STD_LOGIC_VECTOR ( 11 downto 1 ); + signal pkt_len_counter_0 : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \pkt_len_counter_dec__0_carry__0_i_1_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry__0_i_2_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry__0_i_3_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry__0_i_4_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry__0_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry__0_n_1\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry__0_n_2\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry__0_n_3\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry__1_i_1_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry__1_i_2_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry__1_i_3_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry__1_n_2\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry__1_n_3\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry_i_1_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry_i_2_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry_i_3_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry_i_4_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry_i_5_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry_n_0\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry_n_1\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry_n_2\ : STD_LOGIC; + signal \pkt_len_counter_dec__0_carry_n_3\ : STD_LOGIC; + signal reg_pkt_len_counter : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \reg_pkt_len_counter[11]_i_2_n_0\ : STD_LOGIC; + signal \reg_pkt_len_counter[11]_i_3_n_0\ : STD_LOGIC; + signal \reg_pkt_len_counter[11]_i_4_n_0\ : STD_LOGIC; + signal \^reg_pkt_len_counter_reg[3]_0\ : STD_LOGIC; + signal \reg_tkeep[7]_i_4_n_0\ : STD_LOGIC; + signal \reg_tkeep[7]_i_5_n_0\ : STD_LOGIC; + signal \reg_tkeep[7]_i_6_n_0\ : STD_LOGIC; + signal \^reg_tkeep[7]_i_7_0\ : STD_LOGIC; + signal \reg_tkeep[7]_i_7_n_0\ : STD_LOGIC; + signal sel0 : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \NLW_pkt_len_counter_dec__0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_pkt_len_counter_dec__0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \pkt_len_counter_dec__0_carry\ : label is 35; + attribute ADDER_THRESHOLD of \pkt_len_counter_dec__0_carry__0\ : label is 35; + attribute ADDER_THRESHOLD of \pkt_len_counter_dec__0_carry__1\ : label is 35; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \reg_pkt_len_counter[0]_i_1\ : label is "soft_lutpair214"; + attribute SOFT_HLUTNM of \reg_pkt_len_counter[10]_i_1\ : label is "soft_lutpair211"; + attribute SOFT_HLUTNM of \reg_pkt_len_counter[11]_i_1\ : label is "soft_lutpair211"; + attribute SOFT_HLUTNM of \reg_pkt_len_counter[2]_i_1\ : label is "soft_lutpair210"; + attribute SOFT_HLUTNM of \reg_pkt_len_counter[3]_i_1\ : label is "soft_lutpair214"; + attribute SOFT_HLUTNM of \reg_pkt_len_counter[4]_i_1\ : label is "soft_lutpair208"; + attribute SOFT_HLUTNM of \reg_pkt_len_counter[5]_i_1\ : label is "soft_lutpair212"; + attribute SOFT_HLUTNM of \reg_pkt_len_counter[6]_i_1\ : label is "soft_lutpair209"; + attribute SOFT_HLUTNM of \reg_pkt_len_counter[7]_i_1\ : label is "soft_lutpair213"; + attribute SOFT_HLUTNM of \reg_pkt_len_counter[8]_i_1\ : label is "soft_lutpair207"; + attribute SOFT_HLUTNM of \reg_pkt_len_counter[9]_i_1\ : label is "soft_lutpair212"; + attribute SOFT_HLUTNM of \reg_tkeep[7]_i_3\ : label is "soft_lutpair213"; + attribute SOFT_HLUTNM of \reg_tkeep[7]_i_4\ : label is "soft_lutpair207"; + attribute SOFT_HLUTNM of \reg_tkeep[7]_i_5\ : label is "soft_lutpair209"; + attribute SOFT_HLUTNM of \reg_tkeep[7]_i_6\ : label is "soft_lutpair208"; + attribute SOFT_HLUTNM of \reg_tkeep[7]_i_7\ : label is "soft_lutpair210"; +begin + \reg_pkt_len_counter_reg[3]_0\ <= \^reg_pkt_len_counter_reg[3]_0\; + \reg_tkeep[7]_i_7_0\ <= \^reg_tkeep[7]_i_7_0\; +cur_state_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAAAEA" + ) + port map ( + I0 => \reg_pkt_len_counter[11]_i_2_n_0\, + I1 => m_axis_rx_tready, + I2 => cur_state_reg_1, + I3 => cur_state, + I4 => m_axis_rx_tuser(0), + O => next_state + ); +cur_state_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => next_state, + Q => cur_state, + R => cur_state_reg_0 + ); +\m_axis_rx_tuser[19]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555555500000400" + ) + port map ( + I0 => cur_state_reg_0, + I1 => \^reg_tkeep[7]_i_7_0\, + I2 => \^reg_pkt_len_counter_reg[3]_0\, + I3 => null_mux_sel, + I4 => pkt_len_counter_0(0), + I5 => \m_axis_rx_tuser_reg[19]\, + O => D(0) + ); +\m_axis_rx_tuser[21]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FF80FF08" + ) + port map ( + I0 => \^reg_tkeep[7]_i_7_0\, + I1 => null_mux_sel, + I2 => \^reg_pkt_len_counter_reg[3]_0\, + I3 => \m_axis_rx_tuser_reg[21]\, + I4 => pkt_len_counter_0(0), + I5 => cur_state_reg_0, + O => D(1) + ); +null_mux_sel_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000077F7FFFF" + ) + port map ( + I0 => \^reg_tkeep[7]_i_7_0\, + I1 => null_mux_sel, + I2 => pkt_len_counter_0(0), + I3 => \^reg_pkt_len_counter_reg[3]_0\, + I4 => m_axis_rx_tready, + I5 => null_mux_sel_reg_1, + O => null_mux_sel_reg + ); +\pkt_len_counter_dec__0_carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \pkt_len_counter_dec__0_carry_n_0\, + CO(2) => \pkt_len_counter_dec__0_carry_n_1\, + CO(1) => \pkt_len_counter_dec__0_carry_n_2\, + CO(0) => \pkt_len_counter_dec__0_carry_n_3\, + CYINIT => '0', + DI(3 downto 2) => reg_pkt_len_counter(3 downto 2), + DI(1) => \pkt_len_counter_dec__0_carry_i_1_n_0\, + DI(0) => '0', + O(3 downto 0) => pkt_len_counter(4 downto 1), + S(3) => \pkt_len_counter_dec__0_carry_i_2_n_0\, + S(2) => \pkt_len_counter_dec__0_carry_i_3_n_0\, + S(1) => \pkt_len_counter_dec__0_carry_i_4_n_0\, + S(0) => \pkt_len_counter_dec__0_carry_i_5_n_0\ + ); +\pkt_len_counter_dec__0_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \pkt_len_counter_dec__0_carry_n_0\, + CO(3) => \pkt_len_counter_dec__0_carry__0_n_0\, + CO(2) => \pkt_len_counter_dec__0_carry__0_n_1\, + CO(1) => \pkt_len_counter_dec__0_carry__0_n_2\, + CO(0) => \pkt_len_counter_dec__0_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => reg_pkt_len_counter(7 downto 4), + O(3 downto 0) => pkt_len_counter(8 downto 5), + S(3) => \pkt_len_counter_dec__0_carry__0_i_1_n_0\, + S(2) => \pkt_len_counter_dec__0_carry__0_i_2_n_0\, + S(1) => \pkt_len_counter_dec__0_carry__0_i_3_n_0\, + S(0) => \pkt_len_counter_dec__0_carry__0_i_4_n_0\ + ); +\pkt_len_counter_dec__0_carry__0_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => reg_pkt_len_counter(7), + I1 => reg_pkt_len_counter(8), + O => \pkt_len_counter_dec__0_carry__0_i_1_n_0\ + ); +\pkt_len_counter_dec__0_carry__0_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => reg_pkt_len_counter(6), + I1 => reg_pkt_len_counter(7), + O => \pkt_len_counter_dec__0_carry__0_i_2_n_0\ + ); +\pkt_len_counter_dec__0_carry__0_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => reg_pkt_len_counter(5), + I1 => reg_pkt_len_counter(6), + O => \pkt_len_counter_dec__0_carry__0_i_3_n_0\ + ); +\pkt_len_counter_dec__0_carry__0_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => reg_pkt_len_counter(4), + I1 => reg_pkt_len_counter(5), + O => \pkt_len_counter_dec__0_carry__0_i_4_n_0\ + ); +\pkt_len_counter_dec__0_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \pkt_len_counter_dec__0_carry__0_n_0\, + CO(3 downto 2) => \NLW_pkt_len_counter_dec__0_carry__1_CO_UNCONNECTED\(3 downto 2), + CO(1) => \pkt_len_counter_dec__0_carry__1_n_2\, + CO(0) => \pkt_len_counter_dec__0_carry__1_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1 downto 0) => reg_pkt_len_counter(9 downto 8), + O(3) => \NLW_pkt_len_counter_dec__0_carry__1_O_UNCONNECTED\(3), + O(2 downto 0) => pkt_len_counter(11 downto 9), + S(3) => '0', + S(2) => \pkt_len_counter_dec__0_carry__1_i_1_n_0\, + S(1) => \pkt_len_counter_dec__0_carry__1_i_2_n_0\, + S(0) => \pkt_len_counter_dec__0_carry__1_i_3_n_0\ + ); +\pkt_len_counter_dec__0_carry__1_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => reg_pkt_len_counter(10), + I1 => reg_pkt_len_counter(11), + O => \pkt_len_counter_dec__0_carry__1_i_1_n_0\ + ); +\pkt_len_counter_dec__0_carry__1_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => reg_pkt_len_counter(9), + I1 => reg_pkt_len_counter(10), + O => \pkt_len_counter_dec__0_carry__1_i_2_n_0\ + ); +\pkt_len_counter_dec__0_carry__1_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => reg_pkt_len_counter(8), + I1 => reg_pkt_len_counter(9), + O => \pkt_len_counter_dec__0_carry__1_i_3_n_0\ + ); +\pkt_len_counter_dec__0_carry_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => reg_pkt_len_counter(1), + I1 => m_axis_rx_tready, + O => \pkt_len_counter_dec__0_carry_i_1_n_0\ + ); +\pkt_len_counter_dec__0_carry_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => reg_pkt_len_counter(3), + I1 => reg_pkt_len_counter(4), + O => \pkt_len_counter_dec__0_carry_i_2_n_0\ + ); +\pkt_len_counter_dec__0_carry_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => reg_pkt_len_counter(2), + I1 => reg_pkt_len_counter(3), + O => \pkt_len_counter_dec__0_carry_i_3_n_0\ + ); +\pkt_len_counter_dec__0_carry_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"D2" + ) + port map ( + I0 => m_axis_rx_tready, + I1 => reg_pkt_len_counter(1), + I2 => reg_pkt_len_counter(2), + O => \pkt_len_counter_dec__0_carry_i_4_n_0\ + ); +\pkt_len_counter_dec__0_carry_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => reg_pkt_len_counter(1), + I1 => m_axis_rx_tready, + O => \pkt_len_counter_dec__0_carry_i_5_n_0\ + ); +\reg_pkt_len_counter[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => reg_pkt_len_counter(0), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + I2 => new_pkt_len(0), + O => pkt_len_counter_0(0) + ); +\reg_pkt_len_counter[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => pkt_len_counter(10), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + I2 => new_pkt_len(10), + O => sel0(10) + ); +\reg_pkt_len_counter[11]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => pkt_len_counter(11), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + O => sel0(11) + ); +\reg_pkt_len_counter[11]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAA8AAAAAAAA" + ) + port map ( + I0 => cur_state, + I1 => reg_pkt_len_counter(3), + I2 => reg_pkt_len_counter(8), + I3 => reg_pkt_len_counter(7), + I4 => \reg_pkt_len_counter[11]_i_3_n_0\, + I5 => \reg_pkt_len_counter[11]_i_4_n_0\, + O => \reg_pkt_len_counter[11]_i_2_n_0\ + ); +\reg_pkt_len_counter[11]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => reg_pkt_len_counter(5), + I1 => reg_pkt_len_counter(4), + I2 => m_axis_rx_tready, + I3 => reg_pkt_len_counter(9), + O => \reg_pkt_len_counter[11]_i_3_n_0\ + ); +\reg_pkt_len_counter[11]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000007" + ) + port map ( + I0 => reg_pkt_len_counter(0), + I1 => reg_pkt_len_counter(1), + I2 => reg_pkt_len_counter(2), + I3 => reg_pkt_len_counter(6), + I4 => reg_pkt_len_counter(10), + I5 => reg_pkt_len_counter(11), + O => \reg_pkt_len_counter[11]_i_4_n_0\ + ); +\reg_pkt_len_counter[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E2" + ) + port map ( + I0 => new_pkt_len(1), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + I2 => pkt_len_counter(1), + O => pkt_len_counter_0(1) + ); +\reg_pkt_len_counter[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => pkt_len_counter(2), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + I2 => new_pkt_len(2), + O => sel0(2) + ); +\reg_pkt_len_counter[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => pkt_len_counter(3), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + I2 => new_pkt_len(3), + O => sel0(3) + ); +\reg_pkt_len_counter[3]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1EEE" + ) + port map ( + I0 => Q(2), + I1 => Q(3), + I2 => Q(1), + I3 => Q(4), + O => S(1) + ); +\reg_pkt_len_counter[3]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6999" + ) + port map ( + I0 => Q(3), + I1 => Q(2), + I2 => Q(4), + I3 => Q(0), + O => S(0) + ); +\reg_pkt_len_counter[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => pkt_len_counter(4), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + I2 => new_pkt_len(4), + O => sel0(4) + ); +\reg_pkt_len_counter[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => pkt_len_counter(5), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + I2 => new_pkt_len(5), + O => sel0(5) + ); +\reg_pkt_len_counter[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => pkt_len_counter(6), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + I2 => new_pkt_len(6), + O => sel0(6) + ); +\reg_pkt_len_counter[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => pkt_len_counter(7), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + I2 => new_pkt_len(7), + O => sel0(7) + ); +\reg_pkt_len_counter[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => pkt_len_counter(8), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + I2 => new_pkt_len(8), + O => sel0(8) + ); +\reg_pkt_len_counter[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => pkt_len_counter(9), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + I2 => new_pkt_len(9), + O => sel0(9) + ); +\reg_pkt_len_counter_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => pkt_len_counter_0(0), + Q => reg_pkt_len_counter(0), + R => cur_state_reg_0 + ); +\reg_pkt_len_counter_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => sel0(10), + Q => reg_pkt_len_counter(10), + R => cur_state_reg_0 + ); +\reg_pkt_len_counter_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => sel0(11), + Q => reg_pkt_len_counter(11), + R => cur_state_reg_0 + ); +\reg_pkt_len_counter_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => pkt_len_counter_0(1), + Q => reg_pkt_len_counter(1), + R => cur_state_reg_0 + ); +\reg_pkt_len_counter_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => sel0(2), + Q => reg_pkt_len_counter(2), + R => cur_state_reg_0 + ); +\reg_pkt_len_counter_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => sel0(3), + Q => reg_pkt_len_counter(3), + R => cur_state_reg_0 + ); +\reg_pkt_len_counter_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => sel0(4), + Q => reg_pkt_len_counter(4), + R => cur_state_reg_0 + ); +\reg_pkt_len_counter_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => sel0(5), + Q => reg_pkt_len_counter(5), + R => cur_state_reg_0 + ); +\reg_pkt_len_counter_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => sel0(6), + Q => reg_pkt_len_counter(6), + R => cur_state_reg_0 + ); +\reg_pkt_len_counter_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => sel0(7), + Q => reg_pkt_len_counter(7), + R => cur_state_reg_0 + ); +\reg_pkt_len_counter_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => sel0(8), + Q => reg_pkt_len_counter(8), + R => cur_state_reg_0 + ); +\reg_pkt_len_counter_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => sel0(9), + Q => reg_pkt_len_counter(9), + R => cur_state_reg_0 + ); +\reg_tkeep[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => sel0(11), + I1 => sel0(10), + I2 => \reg_tkeep[7]_i_4_n_0\, + I3 => \reg_tkeep[7]_i_5_n_0\, + I4 => \reg_tkeep[7]_i_6_n_0\, + I5 => \reg_tkeep[7]_i_7_n_0\, + O => \^reg_tkeep[7]_i_7_0\ + ); +\reg_tkeep[7]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"47" + ) + port map ( + I0 => pkt_len_counter(1), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + I2 => new_pkt_len(1), + O => \^reg_pkt_len_counter_reg[3]_0\ + ); +\reg_tkeep[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFACCFA" + ) + port map ( + I0 => new_pkt_len(8), + I1 => pkt_len_counter(8), + I2 => new_pkt_len(9), + I3 => \reg_pkt_len_counter[11]_i_2_n_0\, + I4 => pkt_len_counter(9), + O => \reg_tkeep[7]_i_4_n_0\ + ); +\reg_tkeep[7]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFACCFA" + ) + port map ( + I0 => new_pkt_len(6), + I1 => pkt_len_counter(6), + I2 => new_pkt_len(7), + I3 => \reg_pkt_len_counter[11]_i_2_n_0\, + I4 => pkt_len_counter(7), + O => \reg_tkeep[7]_i_5_n_0\ + ); +\reg_tkeep[7]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFACCFA" + ) + port map ( + I0 => new_pkt_len(4), + I1 => pkt_len_counter(4), + I2 => new_pkt_len(5), + I3 => \reg_pkt_len_counter[11]_i_2_n_0\, + I4 => pkt_len_counter(5), + O => \reg_tkeep[7]_i_6_n_0\ + ); +\reg_tkeep[7]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFACCFA" + ) + port map ( + I0 => new_pkt_len(2), + I1 => pkt_len_counter(2), + I2 => new_pkt_len(3), + I3 => \reg_pkt_len_counter[11]_i_2_n_0\, + I4 => pkt_len_counter(3), + O => \reg_tkeep[7]_i_7_n_0\ + ); +reg_tlast_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFB000" + ) + port map ( + I0 => \^reg_pkt_len_counter_reg[3]_0\, + I1 => pkt_len_counter_0(0), + I2 => null_mux_sel, + I3 => \^reg_tkeep[7]_i_7_0\, + I4 => \m_axis_rx_tuser_reg[21]\, + O => null_mux_sel_reg_0 + ); +trn_rdst_rdy_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"B8308800FFFFFFFF" + ) + port map ( + I0 => pkt_len_counter(1), + I1 => \reg_pkt_len_counter[11]_i_2_n_0\, + I2 => new_pkt_len(1), + I3 => reg_pkt_len_counter(0), + I4 => new_pkt_len(0), + I5 => null_mux_sel, + O => \reg_pkt_len_counter_reg[0]_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_axi_basic_rx_pipeline is + port ( + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + trn_rsrc_dsc_d : out STD_LOGIC; + m_axis_rx_tvalid_reg_0 : out STD_LOGIC; + m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_rx_tlast : out STD_LOGIC; + null_mux_sel : out STD_LOGIC; + trn_in_packet : out STD_LOGIC; + reg_dsc_detect_reg_0 : out STD_LOGIC; + user_reset_out_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 63 downto 0 ); + data_prev_reg_0 : out STD_LOGIC; + data_prev_reg_1 : out STD_LOGIC; + new_pkt_len : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \trn_rbar_hit_prev_reg[0]_0\ : in STD_LOGIC; + pipe_userclk2_in : in STD_LOGIC; + trn_rrem : in STD_LOGIC_VECTOR ( 0 to 0 ); + trn_rsrc_dsc : in STD_LOGIC; + rsrc_rdy_filtered : in STD_LOGIC; + trn_reof : in STD_LOGIC; + reg_tlast_reg_0 : in STD_LOGIC; + trn_rsrc_dsc_prev0 : in STD_LOGIC; + trn_rsof : in STD_LOGIC; + trn_recrc_err : in STD_LOGIC; + trn_rerrfwd : in STD_LOGIC; + null_mux_sel_reg_0 : in STD_LOGIC; + trn_in_packet_reg_0 : in STD_LOGIC; + m_axis_rx_tready : in STD_LOGIC; + dsc_detect : in STD_LOGIC; + trn_rdst_rdy_reg_0 : in STD_LOGIC; + trn_rdst_rdy_reg_1 : in STD_LOGIC; + \reg_tkeep_reg[7]_0\ : in STD_LOGIC; + trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 ); + trn_rbar_hit : in STD_LOGIC_VECTOR ( 6 downto 0 ); + S : in STD_LOGIC_VECTOR ( 1 downto 0 ); + D : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_axi_basic_rx_pipeline; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_axi_basic_rx_pipeline is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^q\ : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal data_hold : STD_LOGIC; + signal data_prev : STD_LOGIC; + signal \m_axis_rx_tdata[63]_i_1_n_0\ : STD_LOGIC; + signal \m_axis_rx_tuser[0]_i_1_n_0\ : STD_LOGIC; + signal \m_axis_rx_tuser[14]_i_1_n_0\ : STD_LOGIC; + signal \m_axis_rx_tuser[14]_i_2_n_0\ : STD_LOGIC; + signal \m_axis_rx_tuser[18]_i_1_n_0\ : STD_LOGIC; + signal \m_axis_rx_tuser[1]_i_1_n_0\ : STD_LOGIC; + signal \m_axis_rx_tuser[21]_i_1_n_0\ : STD_LOGIC; + signal \m_axis_rx_tuser[2]_i_1_n_0\ : STD_LOGIC; + signal \m_axis_rx_tuser[3]_i_1_n_0\ : STD_LOGIC; + signal \m_axis_rx_tuser[4]_i_1_n_0\ : STD_LOGIC; + signal \m_axis_rx_tuser[5]_i_1_n_0\ : STD_LOGIC; + signal \m_axis_rx_tuser[6]_i_1_n_0\ : STD_LOGIC; + signal \m_axis_rx_tuser[7]_i_1_n_0\ : STD_LOGIC; + signal \m_axis_rx_tuser[8]_i_1_n_0\ : STD_LOGIC; + signal m_axis_rx_tvalid_i_1_n_0 : STD_LOGIC; + signal \^m_axis_rx_tvalid_reg_0\ : STD_LOGIC; + signal \^null_mux_sel\ : STD_LOGIC; + signal p_1_in : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal packet_overhead : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal reg_dsc_detect_i_1_n_0 : STD_LOGIC; + signal \^reg_dsc_detect_reg_0\ : STD_LOGIC; + signal \reg_pkt_len_counter[10]_i_3_n_0\ : STD_LOGIC; + signal \reg_pkt_len_counter[10]_i_4_n_0\ : STD_LOGIC; + signal \reg_pkt_len_counter[3]_i_5_n_0\ : STD_LOGIC; + signal \reg_pkt_len_counter[3]_i_6_n_0\ : STD_LOGIC; + signal \reg_pkt_len_counter[7]_i_3_n_0\ : STD_LOGIC; + signal \reg_pkt_len_counter[7]_i_4_n_0\ : STD_LOGIC; + signal \reg_pkt_len_counter[7]_i_5_n_0\ : STD_LOGIC; + signal \reg_pkt_len_counter[7]_i_6_n_0\ : STD_LOGIC; + signal \reg_pkt_len_counter_reg[10]_i_2_n_3\ : STD_LOGIC; + signal \reg_pkt_len_counter_reg[3]_i_2_n_0\ : STD_LOGIC; + signal \reg_pkt_len_counter_reg[3]_i_2_n_1\ : STD_LOGIC; + signal \reg_pkt_len_counter_reg[3]_i_2_n_2\ : STD_LOGIC; + signal \reg_pkt_len_counter_reg[3]_i_2_n_3\ : STD_LOGIC; + signal \reg_pkt_len_counter_reg[7]_i_2_n_0\ : STD_LOGIC; + signal \reg_pkt_len_counter_reg[7]_i_2_n_1\ : STD_LOGIC; + signal \reg_pkt_len_counter_reg[7]_i_2_n_2\ : STD_LOGIC; + signal \reg_pkt_len_counter_reg[7]_i_2_n_3\ : STD_LOGIC; + signal reg_tkeep : STD_LOGIC_VECTOR ( 7 to 7 ); + signal trn_rbar_hit_prev : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal trn_rd_prev : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal trn_rdst_rdy_i_1_n_0 : STD_LOGIC; + signal trn_rdst_rdy_i_2_n_0 : STD_LOGIC; + signal trn_recrc_err_prev : STD_LOGIC; + signal trn_reof_prev : STD_LOGIC; + signal trn_rerrfwd_prev : STD_LOGIC; + signal trn_rrem_prev : STD_LOGIC; + signal trn_rsof_prev : STD_LOGIC; + signal trn_rsrc_dsc_prev : STD_LOGIC; + signal trn_rsrc_rdy_prev : STD_LOGIC; + signal \NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_reg_pkt_len_counter_reg[10]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[0]_i_1\ : label is "soft_lutpair243"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[10]_i_1\ : label is "soft_lutpair246"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[11]_i_1\ : label is "soft_lutpair244"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[12]_i_1\ : label is "soft_lutpair241"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[13]_i_1\ : label is "soft_lutpair239"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[14]_i_1\ : label is "soft_lutpair249"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[15]_i_1\ : label is "soft_lutpair242"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[16]_i_1\ : label is "soft_lutpair238"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[17]_i_1\ : label is "soft_lutpair234"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[18]_i_1\ : label is "soft_lutpair232"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[19]_i_1\ : label is "soft_lutpair246"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[1]_i_1\ : label is "soft_lutpair249"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[20]_i_1\ : label is "soft_lutpair242"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[21]_i_1\ : label is "soft_lutpair237"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[22]_i_1\ : label is "soft_lutpair245"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[23]_i_1\ : label is "soft_lutpair247"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[24]_i_1\ : label is "soft_lutpair240"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[25]_i_1\ : label is "soft_lutpair231"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[26]_i_1\ : label is "soft_lutpair229"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[27]_i_1\ : label is "soft_lutpair232"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[28]_i_1\ : label is "soft_lutpair236"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[29]_i_1\ : label is "soft_lutpair228"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[2]_i_1\ : label is "soft_lutpair240"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[30]_i_1\ : label is "soft_lutpair227"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[31]_i_1\ : label is "soft_lutpair222"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[32]_i_1\ : label is "soft_lutpair226"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[33]_i_1\ : label is "soft_lutpair218"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[34]_i_1\ : label is "soft_lutpair225"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[35]_i_1\ : label is "soft_lutpair219"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[36]_i_1\ : label is "soft_lutpair227"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[37]_i_1\ : label is "soft_lutpair218"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[38]_i_1\ : label is "soft_lutpair225"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[39]_i_1\ : label is "soft_lutpair221"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[3]_i_1\ : label is "soft_lutpair248"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[40]_i_1\ : label is "soft_lutpair223"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[41]_i_1\ : label is "soft_lutpair222"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[42]_i_1\ : label is "soft_lutpair221"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[43]_i_1\ : label is "soft_lutpair223"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[44]_i_1\ : label is "soft_lutpair229"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[45]_i_1\ : label is "soft_lutpair228"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[46]_i_1\ : label is "soft_lutpair220"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[47]_i_1\ : label is "soft_lutpair231"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[48]_i_1\ : label is "soft_lutpair220"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[49]_i_1\ : label is "soft_lutpair235"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[4]_i_1\ : label is "soft_lutpair248"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[50]_i_1\ : label is "soft_lutpair233"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[51]_i_1\ : label is "soft_lutpair230"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[52]_i_1\ : label is "soft_lutpair219"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[53]_i_1\ : label is "soft_lutpair226"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[54]_i_1\ : label is "soft_lutpair224"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[55]_i_1\ : label is "soft_lutpair224"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[56]_i_1\ : label is "soft_lutpair239"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[57]_i_1\ : label is "soft_lutpair236"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[58]_i_1\ : label is "soft_lutpair238"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[59]_i_1\ : label is "soft_lutpair230"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[5]_i_1\ : label is "soft_lutpair237"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[60]_i_1\ : label is "soft_lutpair233"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[61]_i_1\ : label is "soft_lutpair243"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[62]_i_1\ : label is "soft_lutpair234"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[63]_i_2\ : label is "soft_lutpair247"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[6]_i_1\ : label is "soft_lutpair235"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[7]_i_1\ : label is "soft_lutpair245"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[8]_i_1\ : label is "soft_lutpair244"; + attribute SOFT_HLUTNM of \m_axis_rx_tdata[9]_i_1\ : label is "soft_lutpair241"; + attribute SOFT_HLUTNM of \m_axis_rx_tuser[14]_i_2\ : label is "soft_lutpair215"; + attribute SOFT_HLUTNM of \m_axis_rx_tuser[18]_i_1\ : label is "soft_lutpair216"; + attribute SOFT_HLUTNM of \m_axis_rx_tuser[2]_i_1\ : label is "soft_lutpair216"; + attribute SOFT_HLUTNM of \m_axis_rx_tuser[7]_i_1\ : label is "soft_lutpair215"; + attribute SOFT_HLUTNM of reg_dsc_detect_i_1 : label is "soft_lutpair217"; + attribute SOFT_HLUTNM of trn_rdst_rdy_i_2 : label is "soft_lutpair217"; +begin + E(0) <= \^e\(0); + Q(63 downto 0) <= \^q\(63 downto 0); + m_axis_rx_tvalid_reg_0 <= \^m_axis_rx_tvalid_reg_0\; + null_mux_sel <= \^null_mux_sel\; + reg_dsc_detect_reg_0 <= \^reg_dsc_detect_reg_0\; +data_prev_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^m_axis_rx_tvalid_reg_0\, + I1 => m_axis_rx_tready, + O => data_hold + ); +data_prev_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => data_hold, + Q => data_prev, + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(0), + I1 => data_prev, + I2 => trn_rd(32), + O => p_1_in(0) + ); +\m_axis_rx_tdata[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(10), + I1 => data_prev, + I2 => trn_rd(42), + O => p_1_in(10) + ); +\m_axis_rx_tdata[11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(11), + I1 => data_prev, + I2 => trn_rd(43), + O => p_1_in(11) + ); +\m_axis_rx_tdata[12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(12), + I1 => data_prev, + I2 => trn_rd(44), + O => p_1_in(12) + ); +\m_axis_rx_tdata[13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(13), + I1 => data_prev, + I2 => trn_rd(45), + O => p_1_in(13) + ); +\m_axis_rx_tdata[14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(14), + I1 => data_prev, + I2 => trn_rd(46), + O => p_1_in(14) + ); +\m_axis_rx_tdata[15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(15), + I1 => data_prev, + I2 => trn_rd(47), + O => p_1_in(15) + ); +\m_axis_rx_tdata[16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(16), + I1 => data_prev, + I2 => trn_rd(48), + O => p_1_in(16) + ); +\m_axis_rx_tdata[17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(17), + I1 => data_prev, + I2 => trn_rd(49), + O => p_1_in(17) + ); +\m_axis_rx_tdata[18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(18), + I1 => data_prev, + I2 => trn_rd(50), + O => p_1_in(18) + ); +\m_axis_rx_tdata[19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(19), + I1 => data_prev, + I2 => trn_rd(51), + O => p_1_in(19) + ); +\m_axis_rx_tdata[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(1), + I1 => data_prev, + I2 => trn_rd(33), + O => p_1_in(1) + ); +\m_axis_rx_tdata[20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(20), + I1 => data_prev, + I2 => trn_rd(52), + O => p_1_in(20) + ); +\m_axis_rx_tdata[21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(21), + I1 => data_prev, + I2 => trn_rd(53), + O => p_1_in(21) + ); +\m_axis_rx_tdata[22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(22), + I1 => data_prev, + I2 => trn_rd(54), + O => p_1_in(22) + ); +\m_axis_rx_tdata[23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(23), + I1 => data_prev, + I2 => trn_rd(55), + O => p_1_in(23) + ); +\m_axis_rx_tdata[24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(24), + I1 => data_prev, + I2 => trn_rd(56), + O => p_1_in(24) + ); +\m_axis_rx_tdata[25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(25), + I1 => data_prev, + I2 => trn_rd(57), + O => p_1_in(25) + ); +\m_axis_rx_tdata[26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(26), + I1 => data_prev, + I2 => trn_rd(58), + O => p_1_in(26) + ); +\m_axis_rx_tdata[27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(27), + I1 => data_prev, + I2 => trn_rd(59), + O => p_1_in(27) + ); +\m_axis_rx_tdata[28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(28), + I1 => data_prev, + I2 => trn_rd(60), + O => p_1_in(28) + ); +\m_axis_rx_tdata[29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(29), + I1 => data_prev, + I2 => trn_rd(61), + O => p_1_in(29) + ); +\m_axis_rx_tdata[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(2), + I1 => data_prev, + I2 => trn_rd(34), + O => p_1_in(2) + ); +\m_axis_rx_tdata[30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(30), + I1 => data_prev, + I2 => trn_rd(62), + O => p_1_in(30) + ); +\m_axis_rx_tdata[31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(31), + I1 => data_prev, + I2 => trn_rd(63), + O => p_1_in(31) + ); +\m_axis_rx_tdata[32]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(32), + I1 => data_prev, + I2 => trn_rd(0), + O => p_1_in(32) + ); +\m_axis_rx_tdata[33]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(33), + I1 => data_prev, + I2 => trn_rd(1), + O => p_1_in(33) + ); +\m_axis_rx_tdata[34]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(34), + I1 => data_prev, + I2 => trn_rd(2), + O => p_1_in(34) + ); +\m_axis_rx_tdata[35]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(35), + I1 => data_prev, + I2 => trn_rd(3), + O => p_1_in(35) + ); +\m_axis_rx_tdata[36]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(36), + I1 => data_prev, + I2 => trn_rd(4), + O => p_1_in(36) + ); +\m_axis_rx_tdata[37]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(37), + I1 => data_prev, + I2 => trn_rd(5), + O => p_1_in(37) + ); +\m_axis_rx_tdata[38]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(38), + I1 => data_prev, + I2 => trn_rd(6), + O => p_1_in(38) + ); +\m_axis_rx_tdata[39]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(39), + I1 => data_prev, + I2 => trn_rd(7), + O => p_1_in(39) + ); +\m_axis_rx_tdata[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(3), + I1 => data_prev, + I2 => trn_rd(35), + O => p_1_in(3) + ); +\m_axis_rx_tdata[40]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(40), + I1 => data_prev, + I2 => trn_rd(8), + O => p_1_in(40) + ); +\m_axis_rx_tdata[41]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(41), + I1 => data_prev, + I2 => trn_rd(9), + O => p_1_in(41) + ); +\m_axis_rx_tdata[42]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(42), + I1 => data_prev, + I2 => trn_rd(10), + O => p_1_in(42) + ); +\m_axis_rx_tdata[43]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(43), + I1 => data_prev, + I2 => trn_rd(11), + O => p_1_in(43) + ); +\m_axis_rx_tdata[44]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(44), + I1 => data_prev, + I2 => trn_rd(12), + O => p_1_in(44) + ); +\m_axis_rx_tdata[45]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(45), + I1 => data_prev, + I2 => trn_rd(13), + O => p_1_in(45) + ); +\m_axis_rx_tdata[46]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(46), + I1 => data_prev, + I2 => trn_rd(14), + O => p_1_in(46) + ); +\m_axis_rx_tdata[47]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(47), + I1 => data_prev, + I2 => trn_rd(15), + O => p_1_in(47) + ); +\m_axis_rx_tdata[48]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(48), + I1 => data_prev, + I2 => trn_rd(16), + O => p_1_in(48) + ); +\m_axis_rx_tdata[49]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(49), + I1 => data_prev, + I2 => trn_rd(17), + O => p_1_in(49) + ); +\m_axis_rx_tdata[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(4), + I1 => data_prev, + I2 => trn_rd(36), + O => p_1_in(4) + ); +\m_axis_rx_tdata[50]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(50), + I1 => data_prev, + I2 => trn_rd(18), + O => p_1_in(50) + ); +\m_axis_rx_tdata[51]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(51), + I1 => data_prev, + I2 => trn_rd(19), + O => p_1_in(51) + ); +\m_axis_rx_tdata[52]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(52), + I1 => data_prev, + I2 => trn_rd(20), + O => p_1_in(52) + ); +\m_axis_rx_tdata[53]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(53), + I1 => data_prev, + I2 => trn_rd(21), + O => p_1_in(53) + ); +\m_axis_rx_tdata[54]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(54), + I1 => data_prev, + I2 => trn_rd(22), + O => p_1_in(54) + ); +\m_axis_rx_tdata[55]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(55), + I1 => data_prev, + I2 => trn_rd(23), + O => p_1_in(55) + ); +\m_axis_rx_tdata[56]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(56), + I1 => data_prev, + I2 => trn_rd(24), + O => p_1_in(56) + ); +\m_axis_rx_tdata[57]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(57), + I1 => data_prev, + I2 => trn_rd(25), + O => p_1_in(57) + ); +\m_axis_rx_tdata[58]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(58), + I1 => data_prev, + I2 => trn_rd(26), + O => p_1_in(58) + ); +\m_axis_rx_tdata[59]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(59), + I1 => data_prev, + I2 => trn_rd(27), + O => p_1_in(59) + ); +\m_axis_rx_tdata[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(5), + I1 => data_prev, + I2 => trn_rd(37), + O => p_1_in(5) + ); +\m_axis_rx_tdata[60]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(60), + I1 => data_prev, + I2 => trn_rd(28), + O => p_1_in(60) + ); +\m_axis_rx_tdata[61]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(61), + I1 => data_prev, + I2 => trn_rd(29), + O => p_1_in(61) + ); +\m_axis_rx_tdata[62]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(62), + I1 => data_prev, + I2 => trn_rd(30), + O => p_1_in(62) + ); +\m_axis_rx_tdata[63]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => m_axis_rx_tready, + I1 => \^m_axis_rx_tvalid_reg_0\, + O => \m_axis_rx_tdata[63]_i_1_n_0\ + ); +\m_axis_rx_tdata[63]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(63), + I1 => data_prev, + I2 => trn_rd(31), + O => p_1_in(63) + ); +\m_axis_rx_tdata[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(6), + I1 => data_prev, + I2 => trn_rd(38), + O => p_1_in(6) + ); +\m_axis_rx_tdata[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(7), + I1 => data_prev, + I2 => trn_rd(39), + O => p_1_in(7) + ); +\m_axis_rx_tdata[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(8), + I1 => data_prev, + I2 => trn_rd(40), + O => p_1_in(8) + ); +\m_axis_rx_tdata[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => trn_rd_prev(9), + I1 => data_prev, + I2 => trn_rd(41), + O => p_1_in(9) + ); +\m_axis_rx_tdata_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(0), + Q => \^q\(0), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(10), + Q => \^q\(10), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(11), + Q => \^q\(11), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(12), + Q => \^q\(12), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(13), + Q => \^q\(13), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(14), + Q => \^q\(14), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(15), + Q => \^q\(15), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(16), + Q => \^q\(16), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(17), + Q => \^q\(17), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(18), + Q => \^q\(18), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(19), + Q => \^q\(19), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(1), + Q => \^q\(1), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(20), + Q => \^q\(20), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(21), + Q => \^q\(21), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(22), + Q => \^q\(22), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(23), + Q => \^q\(23), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(24), + Q => \^q\(24), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(25), + Q => \^q\(25), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(26), + Q => \^q\(26), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(27), + Q => \^q\(27), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(28), + Q => \^q\(28), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(29), + Q => \^q\(29), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(2), + Q => \^q\(2), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(30), + Q => \^q\(30), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(31), + Q => \^q\(31), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(32), + Q => \^q\(32), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(33), + Q => \^q\(33), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(34), + Q => \^q\(34), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(35), + Q => \^q\(35), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(36), + Q => \^q\(36), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(37), + Q => \^q\(37), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(38), + Q => \^q\(38), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(39), + Q => \^q\(39), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(3), + Q => \^q\(3), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(40), + Q => \^q\(40), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(41), + Q => \^q\(41), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(42), + Q => \^q\(42), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(43), + Q => \^q\(43), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(44), + Q => \^q\(44), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(45), + Q => \^q\(45), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(46), + Q => \^q\(46), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(47), + Q => \^q\(47), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(48), + Q => \^q\(48), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(49), + Q => \^q\(49), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(4), + Q => \^q\(4), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(50), + Q => \^q\(50), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(51), + Q => \^q\(51), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(52), + Q => \^q\(52), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(53), + Q => \^q\(53), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(54), + Q => \^q\(54), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(55), + Q => \^q\(55), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(56), + Q => \^q\(56), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(57), + Q => \^q\(57), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(58), + Q => \^q\(58), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(59), + Q => \^q\(59), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(5), + Q => \^q\(5), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(60), + Q => \^q\(60), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(61), + Q => \^q\(61), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(62), + Q => \^q\(62), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(63), + Q => \^q\(63), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(6), + Q => \^q\(6), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(7), + Q => \^q\(7), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(8), + Q => \^q\(8), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tdata_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => p_1_in(9), + Q => \^q\(9), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\m_axis_rx_tuser[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000E2" + ) + port map ( + I0 => trn_recrc_err, + I1 => data_prev, + I2 => trn_recrc_err_prev, + I3 => \trn_rbar_hit_prev_reg[0]_0\, + I4 => \^null_mux_sel\, + O => \m_axis_rx_tuser[0]_i_1_n_0\ + ); +\m_axis_rx_tuser[14]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000004F40404" + ) + port map ( + I0 => trn_rsrc_dsc, + I1 => trn_rsof, + I2 => data_prev, + I3 => trn_rsrc_dsc_prev, + I4 => trn_rsof_prev, + I5 => \m_axis_rx_tuser[14]_i_2_n_0\, + O => \m_axis_rx_tuser[14]_i_1_n_0\ + ); +\m_axis_rx_tuser[14]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \trn_rbar_hit_prev_reg[0]_0\, + I1 => \^null_mux_sel\, + O => \m_axis_rx_tuser[14]_i_2_n_0\ + ); +\m_axis_rx_tuser[18]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \trn_rbar_hit_prev_reg[0]_0\, + O => \m_axis_rx_tuser[18]_i_1_n_0\ + ); +\m_axis_rx_tuser[19]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => trn_rrem(0), + I1 => data_prev, + I2 => trn_rrem_prev, + I3 => \^null_mux_sel\, + O => data_prev_reg_1 + ); +\m_axis_rx_tuser[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000B8" + ) + port map ( + I0 => trn_rerrfwd_prev, + I1 => data_prev, + I2 => trn_rerrfwd, + I3 => \trn_rbar_hit_prev_reg[0]_0\, + I4 => \^null_mux_sel\, + O => \m_axis_rx_tuser[1]_i_1_n_0\ + ); +\m_axis_rx_tuser[21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EF" + ) + port map ( + I0 => \trn_rbar_hit_prev_reg[0]_0\, + I1 => m_axis_rx_tready, + I2 => \^m_axis_rx_tvalid_reg_0\, + O => \m_axis_rx_tuser[21]_i_1_n_0\ + ); +\m_axis_rx_tuser[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000B8" + ) + port map ( + I0 => trn_rbar_hit_prev(0), + I1 => data_prev, + I2 => trn_rbar_hit(0), + I3 => \trn_rbar_hit_prev_reg[0]_0\, + I4 => \^null_mux_sel\, + O => \m_axis_rx_tuser[2]_i_1_n_0\ + ); +\m_axis_rx_tuser[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000E2" + ) + port map ( + I0 => trn_rbar_hit(1), + I1 => data_prev, + I2 => trn_rbar_hit_prev(1), + I3 => \trn_rbar_hit_prev_reg[0]_0\, + I4 => \^null_mux_sel\, + O => \m_axis_rx_tuser[3]_i_1_n_0\ + ); +\m_axis_rx_tuser[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000E2" + ) + port map ( + I0 => trn_rbar_hit(2), + I1 => data_prev, + I2 => trn_rbar_hit_prev(2), + I3 => \trn_rbar_hit_prev_reg[0]_0\, + I4 => \^null_mux_sel\, + O => \m_axis_rx_tuser[4]_i_1_n_0\ + ); +\m_axis_rx_tuser[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000B8" + ) + port map ( + I0 => trn_rbar_hit_prev(3), + I1 => data_prev, + I2 => trn_rbar_hit(3), + I3 => \trn_rbar_hit_prev_reg[0]_0\, + I4 => \^null_mux_sel\, + O => \m_axis_rx_tuser[5]_i_1_n_0\ + ); +\m_axis_rx_tuser[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000B8" + ) + port map ( + I0 => trn_rbar_hit_prev(4), + I1 => data_prev, + I2 => trn_rbar_hit(4), + I3 => \trn_rbar_hit_prev_reg[0]_0\, + I4 => \^null_mux_sel\, + O => \m_axis_rx_tuser[6]_i_1_n_0\ + ); +\m_axis_rx_tuser[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000E2" + ) + port map ( + I0 => trn_rbar_hit(5), + I1 => data_prev, + I2 => trn_rbar_hit_prev(5), + I3 => \trn_rbar_hit_prev_reg[0]_0\, + I4 => \^null_mux_sel\, + O => \m_axis_rx_tuser[7]_i_1_n_0\ + ); +\m_axis_rx_tuser[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000E2" + ) + port map ( + I0 => trn_rbar_hit(6), + I1 => data_prev, + I2 => trn_rbar_hit_prev(6), + I3 => \trn_rbar_hit_prev_reg[0]_0\, + I4 => \^null_mux_sel\, + O => \m_axis_rx_tuser[8]_i_1_n_0\ + ); +\m_axis_rx_tuser_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tuser[21]_i_1_n_0\, + D => \m_axis_rx_tuser[0]_i_1_n_0\, + Q => m_axis_rx_tuser(0), + R => '0' + ); +\m_axis_rx_tuser_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tuser[21]_i_1_n_0\, + D => \m_axis_rx_tuser[14]_i_1_n_0\, + Q => m_axis_rx_tuser(9), + R => '0' + ); +\m_axis_rx_tuser_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tuser[21]_i_1_n_0\, + D => \m_axis_rx_tuser[18]_i_1_n_0\, + Q => m_axis_rx_tuser(10), + R => '0' + ); +\m_axis_rx_tuser_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tuser[21]_i_1_n_0\, + D => D(0), + Q => m_axis_rx_tuser(11), + R => '0' + ); +\m_axis_rx_tuser_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tuser[21]_i_1_n_0\, + D => \m_axis_rx_tuser[1]_i_1_n_0\, + Q => m_axis_rx_tuser(1), + R => '0' + ); +\m_axis_rx_tuser_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tuser[21]_i_1_n_0\, + D => D(1), + Q => m_axis_rx_tuser(12), + R => '0' + ); +\m_axis_rx_tuser_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tuser[21]_i_1_n_0\, + D => \m_axis_rx_tuser[2]_i_1_n_0\, + Q => m_axis_rx_tuser(2), + R => '0' + ); +\m_axis_rx_tuser_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tuser[21]_i_1_n_0\, + D => \m_axis_rx_tuser[3]_i_1_n_0\, + Q => m_axis_rx_tuser(3), + R => '0' + ); +\m_axis_rx_tuser_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tuser[21]_i_1_n_0\, + D => \m_axis_rx_tuser[4]_i_1_n_0\, + Q => m_axis_rx_tuser(4), + R => '0' + ); +\m_axis_rx_tuser_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tuser[21]_i_1_n_0\, + D => \m_axis_rx_tuser[5]_i_1_n_0\, + Q => m_axis_rx_tuser(5), + R => '0' + ); +\m_axis_rx_tuser_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tuser[21]_i_1_n_0\, + D => \m_axis_rx_tuser[6]_i_1_n_0\, + Q => m_axis_rx_tuser(6), + R => '0' + ); +\m_axis_rx_tuser_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tuser[21]_i_1_n_0\, + D => \m_axis_rx_tuser[7]_i_1_n_0\, + Q => m_axis_rx_tuser(7), + R => '0' + ); +\m_axis_rx_tuser_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tuser[21]_i_1_n_0\, + D => \m_axis_rx_tuser[8]_i_1_n_0\, + Q => m_axis_rx_tuser(8), + R => '0' + ); +m_axis_rx_tvalid_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFECE" + ) + port map ( + I0 => rsrc_rdy_filtered, + I1 => \^null_mux_sel\, + I2 => data_prev, + I3 => trn_rsrc_rdy_prev, + I4 => \^reg_dsc_detect_reg_0\, + I5 => dsc_detect, + O => m_axis_rx_tvalid_i_1_n_0 + ); +m_axis_rx_tvalid_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => m_axis_rx_tvalid_i_1_n_0, + Q => \^m_axis_rx_tvalid_reg_0\, + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +null_mux_sel_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABAAABAAABAABBBB" + ) + port map ( + I0 => \trn_rbar_hit_prev_reg[0]_0\, + I1 => \^null_mux_sel\, + I2 => m_axis_rx_tready, + I3 => \^m_axis_rx_tvalid_reg_0\, + I4 => dsc_detect, + I5 => \^reg_dsc_detect_reg_0\, + O => user_reset_out_reg + ); +null_mux_sel_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => null_mux_sel_reg_0, + Q => \^null_mux_sel\, + R => '0' + ); +reg_dsc_detect_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"DC" + ) + port map ( + I0 => \^null_mux_sel\, + I1 => dsc_detect, + I2 => \^reg_dsc_detect_reg_0\, + O => reg_dsc_detect_i_1_n_0 + ); +reg_dsc_detect_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => reg_dsc_detect_i_1_n_0, + Q => \^reg_dsc_detect_reg_0\, + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\reg_pkt_len_counter[10]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(30), + I1 => \^q\(9), + O => \reg_pkt_len_counter[10]_i_3_n_0\ + ); +\reg_pkt_len_counter[10]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(30), + I1 => \^q\(8), + O => \reg_pkt_len_counter[10]_i_4_n_0\ + ); +\reg_pkt_len_counter[3]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^q\(29), + I1 => \^q\(15), + O => packet_overhead(1) + ); +\reg_pkt_len_counter[3]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(15), + I1 => \^q\(29), + O => packet_overhead(0) + ); +\reg_pkt_len_counter[3]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(30), + I1 => \^q\(3), + O => \reg_pkt_len_counter[3]_i_5_n_0\ + ); +\reg_pkt_len_counter[3]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(30), + I1 => \^q\(2), + O => \reg_pkt_len_counter[3]_i_6_n_0\ + ); +\reg_pkt_len_counter[7]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(30), + I1 => \^q\(7), + O => \reg_pkt_len_counter[7]_i_3_n_0\ + ); +\reg_pkt_len_counter[7]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(30), + I1 => \^q\(6), + O => \reg_pkt_len_counter[7]_i_4_n_0\ + ); +\reg_pkt_len_counter[7]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(30), + I1 => \^q\(5), + O => \reg_pkt_len_counter[7]_i_5_n_0\ + ); +\reg_pkt_len_counter[7]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(30), + I1 => \^q\(4), + O => \reg_pkt_len_counter[7]_i_6_n_0\ + ); +\reg_pkt_len_counter_reg[10]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \reg_pkt_len_counter_reg[7]_i_2_n_0\, + CO(3) => \NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED\(3), + CO(2) => new_pkt_len(10), + CO(1) => \NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED\(1), + CO(0) => \reg_pkt_len_counter_reg[10]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 2) => \NLW_reg_pkt_len_counter_reg[10]_i_2_O_UNCONNECTED\(3 downto 2), + O(1 downto 0) => new_pkt_len(9 downto 8), + S(3 downto 2) => B"01", + S(1) => \reg_pkt_len_counter[10]_i_3_n_0\, + S(0) => \reg_pkt_len_counter[10]_i_4_n_0\ + ); +\reg_pkt_len_counter_reg[3]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \reg_pkt_len_counter_reg[3]_i_2_n_0\, + CO(2) => \reg_pkt_len_counter_reg[3]_i_2_n_1\, + CO(1) => \reg_pkt_len_counter_reg[3]_i_2_n_2\, + CO(0) => \reg_pkt_len_counter_reg[3]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1 downto 0) => packet_overhead(1 downto 0), + O(3 downto 0) => new_pkt_len(3 downto 0), + S(3) => \reg_pkt_len_counter[3]_i_5_n_0\, + S(2) => \reg_pkt_len_counter[3]_i_6_n_0\, + S(1 downto 0) => S(1 downto 0) + ); +\reg_pkt_len_counter_reg[7]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \reg_pkt_len_counter_reg[3]_i_2_n_0\, + CO(3) => \reg_pkt_len_counter_reg[7]_i_2_n_0\, + CO(2) => \reg_pkt_len_counter_reg[7]_i_2_n_1\, + CO(1) => \reg_pkt_len_counter_reg[7]_i_2_n_2\, + CO(0) => \reg_pkt_len_counter_reg[7]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => new_pkt_len(7 downto 4), + S(3) => \reg_pkt_len_counter[7]_i_3_n_0\, + S(2) => \reg_pkt_len_counter[7]_i_4_n_0\, + S(1) => \reg_pkt_len_counter[7]_i_5_n_0\, + S(0) => \reg_pkt_len_counter[7]_i_6_n_0\ + ); +\reg_tkeep[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7F7F7F7070707F70" + ) + port map ( + I0 => trn_rdst_rdy_reg_0, + I1 => \reg_tkeep_reg[7]_0\, + I2 => \^null_mux_sel\, + I3 => trn_rrem(0), + I4 => data_prev, + I5 => trn_rrem_prev, + O => reg_tkeep(7) + ); +\reg_tkeep_reg[7]\: unisim.vcomponents.FDSE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => reg_tkeep(7), + Q => m_axis_rx_tkeep(0), + S => \trn_rbar_hit_prev_reg[0]_0\ + ); +reg_tlast_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => trn_reof, + I1 => data_prev, + I2 => trn_reof_prev, + I3 => \^null_mux_sel\, + O => data_prev_reg_0 + ); +reg_tlast_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \m_axis_rx_tdata[63]_i_1_n_0\, + D => reg_tlast_reg_0, + Q => m_axis_rx_tlast, + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +trn_in_packet_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => trn_in_packet_reg_0, + Q => trn_in_packet, + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rbar_hit_prev_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rbar_hit(0), + Q => trn_rbar_hit_prev(0), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rbar_hit_prev_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rbar_hit(1), + Q => trn_rbar_hit_prev(1), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rbar_hit_prev_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rbar_hit(2), + Q => trn_rbar_hit_prev(2), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rbar_hit_prev_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rbar_hit(3), + Q => trn_rbar_hit_prev(3), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rbar_hit_prev_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rbar_hit(4), + Q => trn_rbar_hit_prev(4), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rbar_hit_prev_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rbar_hit(5), + Q => trn_rbar_hit_prev(5), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rbar_hit_prev_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rbar_hit(6), + Q => trn_rbar_hit_prev(6), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(32), + Q => trn_rd_prev(0), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(42), + Q => trn_rd_prev(10), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(43), + Q => trn_rd_prev(11), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(44), + Q => trn_rd_prev(12), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(45), + Q => trn_rd_prev(13), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(46), + Q => trn_rd_prev(14), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(47), + Q => trn_rd_prev(15), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(48), + Q => trn_rd_prev(16), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(49), + Q => trn_rd_prev(17), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(50), + Q => trn_rd_prev(18), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(51), + Q => trn_rd_prev(19), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(33), + Q => trn_rd_prev(1), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(52), + Q => trn_rd_prev(20), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(53), + Q => trn_rd_prev(21), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(54), + Q => trn_rd_prev(22), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(55), + Q => trn_rd_prev(23), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(56), + Q => trn_rd_prev(24), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(57), + Q => trn_rd_prev(25), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(58), + Q => trn_rd_prev(26), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(59), + Q => trn_rd_prev(27), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(60), + Q => trn_rd_prev(28), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(61), + Q => trn_rd_prev(29), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(34), + Q => trn_rd_prev(2), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(62), + Q => trn_rd_prev(30), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(63), + Q => trn_rd_prev(31), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(0), + Q => trn_rd_prev(32), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(1), + Q => trn_rd_prev(33), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(2), + Q => trn_rd_prev(34), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(3), + Q => trn_rd_prev(35), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(4), + Q => trn_rd_prev(36), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(5), + Q => trn_rd_prev(37), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(6), + Q => trn_rd_prev(38), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(7), + Q => trn_rd_prev(39), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(35), + Q => trn_rd_prev(3), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(8), + Q => trn_rd_prev(40), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(9), + Q => trn_rd_prev(41), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(10), + Q => trn_rd_prev(42), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(11), + Q => trn_rd_prev(43), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(12), + Q => trn_rd_prev(44), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(13), + Q => trn_rd_prev(45), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(14), + Q => trn_rd_prev(46), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(15), + Q => trn_rd_prev(47), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(16), + Q => trn_rd_prev(48), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(17), + Q => trn_rd_prev(49), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(36), + Q => trn_rd_prev(4), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(18), + Q => trn_rd_prev(50), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(19), + Q => trn_rd_prev(51), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(20), + Q => trn_rd_prev(52), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(21), + Q => trn_rd_prev(53), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(22), + Q => trn_rd_prev(54), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(23), + Q => trn_rd_prev(55), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(24), + Q => trn_rd_prev(56), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(25), + Q => trn_rd_prev(57), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(26), + Q => trn_rd_prev(58), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(27), + Q => trn_rd_prev(59), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(37), + Q => trn_rd_prev(5), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(28), + Q => trn_rd_prev(60), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(29), + Q => trn_rd_prev(61), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(30), + Q => trn_rd_prev(62), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(31), + Q => trn_rd_prev(63), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(38), + Q => trn_rd_prev(6), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(39), + Q => trn_rd_prev(7), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(40), + Q => trn_rd_prev(8), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rd_prev_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rd(41), + Q => trn_rd_prev(9), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +trn_rdst_rdy_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"3030FF3050505050" + ) + port map ( + I0 => \^m_axis_rx_tvalid_reg_0\, + I1 => \^null_mux_sel\, + I2 => trn_rdst_rdy_i_2_n_0, + I3 => trn_rdst_rdy_reg_0, + I4 => trn_rdst_rdy_reg_1, + I5 => m_axis_rx_tready, + O => trn_rdst_rdy_i_1_n_0 + ); +trn_rdst_rdy_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^reg_dsc_detect_reg_0\, + I1 => dsc_detect, + O => trn_rdst_rdy_i_2_n_0 + ); +trn_rdst_rdy_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => trn_rdst_rdy_i_1_n_0, + Q => \^e\(0), + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +trn_recrc_err_prev_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_recrc_err, + Q => trn_recrc_err_prev, + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +trn_reof_prev_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_reof, + Q => trn_reof_prev, + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +trn_rerrfwd_prev_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rerrfwd, + Q => trn_rerrfwd_prev, + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +\trn_rrem_prev_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rrem(0), + Q => trn_rrem_prev, + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +trn_rsof_prev_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rsof, + Q => trn_rsof_prev, + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +trn_rsrc_dsc_d_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => trn_rsrc_dsc, + Q => trn_rsrc_dsc_d, + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +trn_rsrc_dsc_prev_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => trn_rsrc_dsc_prev0, + Q => trn_rsrc_dsc_prev, + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +trn_rsrc_rdy_prev_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => \^e\(0), + D => rsrc_rdy_filtered, + Q => trn_rsrc_rdy_prev, + R => \trn_rbar_hit_prev_reg[0]_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_axi_basic_tx_pipeline is + port ( + trn_teof : out STD_LOGIC; + trn_tsrc_rdy : out STD_LOGIC; + trn_trem : out STD_LOGIC_VECTOR ( 0 to 0 ); + axi_in_packet : out STD_LOGIC; + reg_disable_trn : out STD_LOGIC; + trn_tsof : out STD_LOGIC; + \throttle_ctl_pipeline.reg_tdata_reg[63]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 ); + \throttle_ctl_pipeline.reg_tuser_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ : in STD_LOGIC; + s_axis_tx_tlast : in STD_LOGIC; + pipe_userclk2_in : in STD_LOGIC; + reg_tsrc_rdy0 : in STD_LOGIC; + s_axis_tx_tvalid : in STD_LOGIC; + s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); + axi_in_packet_reg_0 : in STD_LOGIC; + \out\ : in STD_LOGIC; + \thrtl_ctl_trn_flush.reg_disable_trn_reg_0\ : in STD_LOGIC; + trn_tdst_rdy : in STD_LOGIC; + s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_axi_basic_tx_pipeline; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_axi_basic_tx_pipeline is + signal \^axi_in_packet\ : STD_LOGIC; + signal \^reg_disable_trn\ : STD_LOGIC; + signal reg_tvalid : STD_LOGIC; + signal \thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0\ : STD_LOGIC; + signal trn_in_packet : STD_LOGIC; + signal \trn_in_packet_i_1__0_n_0\ : STD_LOGIC; + signal \^trn_teof\ : STD_LOGIC; + signal \^trn_tsrc_rdy\ : STD_LOGIC; +begin + axi_in_packet <= \^axi_in_packet\; + reg_disable_trn <= \^reg_disable_trn\; + trn_teof <= \^trn_teof\; + trn_tsrc_rdy <= \^trn_tsrc_rdy\; +axi_in_packet_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => axi_in_packet_reg_0, + Q => \^axi_in_packet\, + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +pcie_block_i_i_31: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => reg_tvalid, + I1 => trn_in_packet, + O => trn_tsof + ); +\throttle_ctl_pipeline.reg_tdata_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(0), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(0), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(10), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(10), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(11), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(11), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(12), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(12), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(13), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(13), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(14), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(14), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(15), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(15), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(16), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(16), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(17), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(17), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(18), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(18), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(19), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(19), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(1), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(1), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(20), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(20), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(21), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(21), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(22), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(22), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(23), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(23), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(24), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(24), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(25), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(25), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(26), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(26), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(27), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(27), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(28), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(28), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(29), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(29), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(2), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(2), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(30), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(30), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(31), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(31), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(32), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(32), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(33), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(33), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(34), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(34), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(35), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(35), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(36), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(36), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(37), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(37), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(38), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(38), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(39), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(39), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(3), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(3), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(40), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(40), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(41), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(41), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(42), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(42), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(43), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(43), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(44), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(44), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(45), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(45), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(46), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(46), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(47), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(47), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(48), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(48), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(49), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(49), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(4), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(4), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(50), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(50), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(51), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(51), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(52), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(52), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(53), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(53), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(54), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(54), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(55), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(55), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(56), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(56), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(57), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(57), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(58), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(58), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(59), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(59), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(5), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(5), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(60), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(60), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(61), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(61), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(62), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(62), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(63), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(63), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(6), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(6), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(7), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(7), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(8), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(8), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tdata_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tdata(9), + Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(9), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tkeep_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tkeep(0), + Q => trn_trem(0), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tlast_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tlast, + Q => \^trn_teof\, + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tsrc_rdy_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => reg_tsrc_rdy0, + Q => \^trn_tsrc_rdy\, + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tuser_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tuser(0), + Q => \throttle_ctl_pipeline.reg_tuser_reg[3]_0\(0), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tuser_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tuser(1), + Q => \throttle_ctl_pipeline.reg_tuser_reg[3]_0\(1), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tuser_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tuser(2), + Q => \throttle_ctl_pipeline.reg_tuser_reg[3]_0\(2), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tuser_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tuser(3), + Q => \throttle_ctl_pipeline.reg_tuser_reg[3]_0\(3), + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\throttle_ctl_pipeline.reg_tvalid_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => s_axis_tx_tvalid, + Q => reg_tvalid, + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\thrtl_ctl_trn_flush.reg_disable_trn_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0FFFFFFF04444444" + ) + port map ( + I0 => \out\, + I1 => \^axi_in_packet\, + I2 => \thrtl_ctl_trn_flush.reg_disable_trn_reg_0\, + I3 => s_axis_tx_tvalid, + I4 => s_axis_tx_tlast, + I5 => \^reg_disable_trn\, + O => \thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0\ + ); +\thrtl_ctl_trn_flush.reg_disable_trn_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => \thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0\, + Q => \^reg_disable_trn\, + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +\trn_in_packet_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000F088F000F000" + ) + port map ( + I0 => trn_tdst_rdy, + I1 => reg_tvalid, + I2 => \out\, + I3 => trn_in_packet, + I4 => \^trn_teof\, + I5 => \^trn_tsrc_rdy\, + O => \trn_in_packet_i_1__0_n_0\ + ); +trn_in_packet_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => \trn_in_packet_i_1__0_n_0\, + Q => trn_in_packet, + R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_axi_basic_tx_thrtl_ctl is + port ( + reg_tcfg_gnt : out STD_LOGIC; + tready_thrtl_reg_0 : out STD_LOGIC; + ppm_L1_thrtl : out STD_LOGIC; + lnk_up_thrtl : out STD_LOGIC; + s_axis_tx_tlast_0 : out STD_LOGIC; + ppm_L1_trig : out STD_LOGIC; + cfg_pm_turnoff_ok_n : out STD_LOGIC; + trn_tcfg_gnt : out STD_LOGIC; + reg_tsrc_rdy0 : out STD_LOGIC; + \tbuf_gap_cnt_reg[0]_0\ : in STD_LOGIC; + tx_cfg_gnt : in STD_LOGIC; + pipe_userclk2_in : in STD_LOGIC; + trn_tcfg_req : in STD_LOGIC; + trn_tdst_rdy : in STD_LOGIC; + tbuf_av_min_trig : in STD_LOGIC; + cfg_turnoff_ok : in STD_LOGIC; + ppm_L1_thrtl_reg_0 : in STD_LOGIC; + lnk_up_thrtl_reg_0 : in STD_LOGIC; + s_axis_tx_tlast : in STD_LOGIC; + s_axis_tx_tvalid : in STD_LOGIC; + axi_in_packet : in STD_LOGIC; + \out\ : in STD_LOGIC; + tcfg_req_trig : in STD_LOGIC; + tready_thrtl_i_5_0 : in STD_LOGIC; + cfg_pcie_link_state : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + reg_disable_trn : in STD_LOGIC; + trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 ); + cfg_to_turnoff : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_axi_basic_tx_thrtl_ctl; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_axi_basic_tx_thrtl_ctl is + signal \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff\ : STD_LOGIC; + signal \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1_n_0\ : STD_LOGIC; + signal cfg_pcie_link_state_d : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^cfg_pm_turnoff_ok_n\ : STD_LOGIC; + signal cfg_turnoff_ok_pending : STD_LOGIC; + signal cfg_turnoff_ok_pending_i_1_n_0 : STD_LOGIC; + signal cur_state : STD_LOGIC; + signal cur_state_i_2_n_0 : STD_LOGIC; + signal \ecrc_pause_enabled.reg_tx_ecrc_pkt\ : STD_LOGIC; + signal \ecrc_pause_enabled.reg_tx_ecrc_pkt021_out\ : STD_LOGIC; + signal \ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1_n_0\ : STD_LOGIC; + signal \^lnk_up_thrtl\ : STD_LOGIC; + signal next_state : STD_LOGIC; + signal p_2_in : STD_LOGIC; + signal pcie_block_i_i_36_n_0 : STD_LOGIC; + signal \^ppm_l1_thrtl\ : STD_LOGIC; + signal \^ppm_l1_trig\ : STD_LOGIC; + signal ppm_L23_thrtl : STD_LOGIC; + signal ppm_L23_thrtl_i_1_n_0 : STD_LOGIC; + signal ppm_L23_trig : STD_LOGIC; + signal reg_axi_in_pkt : STD_LOGIC; + signal reg_axi_in_pkt_i_1_n_0 : STD_LOGIC; + signal \^reg_tcfg_gnt\ : STD_LOGIC; + signal reg_turnoff_ok : STD_LOGIC; + signal tbuf_av_d : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal tbuf_av_gap_thrtl : STD_LOGIC; + signal tbuf_av_gap_thrtl_i_1_n_0 : STD_LOGIC; + signal tbuf_av_gap_trig : STD_LOGIC; + signal tbuf_av_min_thrtl : STD_LOGIC; + signal \tbuf_gap_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \tbuf_gap_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal tcfg_gnt_pending : STD_LOGIC; + signal tcfg_gnt_pending_i_1_n_0 : STD_LOGIC; + signal tcfg_req_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \tcfg_req_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \tcfg_req_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal tcfg_req_thrtl : STD_LOGIC; + signal tcfg_req_thrtl_i_1_n_0 : STD_LOGIC; + signal tready_thrtl0 : STD_LOGIC; + signal tready_thrtl_i_10_n_0 : STD_LOGIC; + signal tready_thrtl_i_12_n_0 : STD_LOGIC; + signal tready_thrtl_i_2_n_0 : STD_LOGIC; + signal tready_thrtl_i_3_n_0 : STD_LOGIC; + signal tready_thrtl_i_4_n_0 : STD_LOGIC; + signal tready_thrtl_i_6_n_0 : STD_LOGIC; + signal tready_thrtl_i_7_n_0 : STD_LOGIC; + signal \^tready_thrtl_reg_0\ : STD_LOGIC; + signal trn_tcfg_req_d : STD_LOGIC; + signal trn_tdst_rdy_d : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1\ : label is "soft_lutpair255"; + attribute SOFT_HLUTNM of cfg_turnoff_ok_pending_i_1 : label is "soft_lutpair252"; + attribute SOFT_HLUTNM of \ecrc_pause_enabled.reg_tx_ecrc_pkt_i_2\ : label is "soft_lutpair253"; + attribute SOFT_HLUTNM of pcie_block_i_i_30 : label is "soft_lutpair254"; + attribute SOFT_HLUTNM of pcie_block_i_i_36 : label is "soft_lutpair250"; + attribute SOFT_HLUTNM of ppm_L23_thrtl_i_1 : label is "soft_lutpair252"; + attribute SOFT_HLUTNM of \tbuf_gap_cnt[0]_i_1\ : label is "soft_lutpair254"; + attribute SOFT_HLUTNM of \tcfg_req_cnt[1]_i_1\ : label is "soft_lutpair251"; + attribute SOFT_HLUTNM of tcfg_req_thrtl_i_2 : label is "soft_lutpair251"; + attribute SOFT_HLUTNM of tready_thrtl_i_2 : label is "soft_lutpair253"; + attribute SOFT_HLUTNM of tready_thrtl_i_3 : label is "soft_lutpair250"; + attribute SOFT_HLUTNM of tready_thrtl_i_8 : label is "soft_lutpair255"; +begin + cfg_pm_turnoff_ok_n <= \^cfg_pm_turnoff_ok_n\; + lnk_up_thrtl <= \^lnk_up_thrtl\; + ppm_L1_thrtl <= \^ppm_l1_thrtl\; + ppm_L1_trig <= \^ppm_l1_trig\; + reg_tcfg_gnt <= \^reg_tcfg_gnt\; + tready_thrtl_reg_0 <= \^tready_thrtl_reg_0\; +\L23_thrtl_ep.reg_turnoff_ok_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => cfg_turnoff_ok, + Q => reg_turnoff_ok, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => cfg_to_turnoff, + I1 => \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff\, + O => \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1_n_0\ + ); +\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1_n_0\, + Q => \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff\, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +axi_in_packet_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F40" + ) + port map ( + I0 => s_axis_tx_tlast, + I1 => s_axis_tx_tvalid, + I2 => \^tready_thrtl_reg_0\, + I3 => axi_in_packet, + O => s_axis_tx_tlast_0 + ); +\cfg_pcie_link_state_d_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => cfg_pcie_link_state(0), + Q => cfg_pcie_link_state_d(0), + R => \tbuf_gap_cnt_reg[0]_0\ + ); +\cfg_pcie_link_state_d_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => cfg_pcie_link_state(1), + Q => cfg_pcie_link_state_d(1), + R => \tbuf_gap_cnt_reg[0]_0\ + ); +\cfg_pcie_link_state_d_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => cfg_pcie_link_state(2), + Q => cfg_pcie_link_state_d(2), + R => \tbuf_gap_cnt_reg[0]_0\ + ); +cfg_turnoff_ok_pending_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"75553000" + ) + port map ( + I0 => \^cfg_pm_turnoff_ok_n\, + I1 => ppm_L23_thrtl, + I2 => reg_turnoff_ok, + I3 => \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff\, + I4 => cfg_turnoff_ok_pending, + O => cfg_turnoff_ok_pending_i_1_n_0 + ); +cfg_turnoff_ok_pending_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => cfg_turnoff_ok_pending_i_1_n_0, + Q => cfg_turnoff_ok_pending, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +\cur_state_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5455445554555555" + ) + port map ( + I0 => cur_state_i_2_n_0, + I1 => cur_state, + I2 => s_axis_tx_tlast, + I3 => \^tready_thrtl_reg_0\, + I4 => s_axis_tx_tvalid, + I5 => reg_axi_in_pkt, + O => next_state + ); +cur_state_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \^ppm_l1_thrtl\, + I1 => \^lnk_up_thrtl\, + I2 => tcfg_req_thrtl, + I3 => ppm_L23_thrtl, + I4 => tbuf_av_gap_thrtl, + I5 => tbuf_av_min_thrtl, + O => cur_state_i_2_n_0 + ); +cur_state_reg: unisim.vcomponents.FDSE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => next_state, + Q => cur_state, + S => \tbuf_gap_cnt_reg[0]_0\ + ); +\ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFFAAAA" + ) + port map ( + I0 => \ecrc_pause_enabled.reg_tx_ecrc_pkt021_out\, + I1 => \^tready_thrtl_reg_0\, + I2 => s_axis_tx_tvalid, + I3 => s_axis_tx_tlast, + I4 => \ecrc_pause_enabled.reg_tx_ecrc_pkt\, + O => \ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1_n_0\ + ); +\ecrc_pause_enabled.reg_tx_ecrc_pkt_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001444" + ) + port map ( + I0 => tready_thrtl_i_7_n_0, + I1 => s_axis_tx_tdata(2), + I2 => s_axis_tx_tdata(3), + I3 => s_axis_tx_tdata(0), + I4 => s_axis_tx_tlast, + O => \ecrc_pause_enabled.reg_tx_ecrc_pkt021_out\ + ); +\ecrc_pause_enabled.reg_tx_ecrc_pkt_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => \ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1_n_0\, + Q => \ecrc_pause_enabled.reg_tx_ecrc_pkt\, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +lnk_up_thrtl_reg: unisim.vcomponents.FDSE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => lnk_up_thrtl_reg_0, + Q => \^lnk_up_thrtl\, + S => \tbuf_gap_cnt_reg[0]_0\ + ); +pcie_block_i_i_26: unisim.vcomponents.LUT6 + generic map( + INIT => X"20202020A0AFA0A0" + ) + port map ( + I0 => cfg_turnoff_ok_pending, + I1 => tcfg_gnt_pending, + I2 => cur_state, + I3 => pcie_block_i_i_36_n_0, + I4 => ppm_L23_thrtl, + I5 => tcfg_req_thrtl, + O => \^cfg_pm_turnoff_ok_n\ + ); +pcie_block_i_i_30: unisim.vcomponents.LUT4 + generic map( + INIT => X"A202" + ) + port map ( + I0 => tcfg_req_thrtl, + I1 => pcie_block_i_i_36_n_0, + I2 => cur_state, + I3 => tcfg_gnt_pending, + O => trn_tcfg_gnt + ); +pcie_block_i_i_36: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF20E0" + ) + port map ( + I0 => reg_axi_in_pkt, + I1 => s_axis_tx_tvalid, + I2 => \^tready_thrtl_reg_0\, + I3 => s_axis_tx_tlast, + I4 => cur_state_i_2_n_0, + O => pcie_block_i_i_36_n_0 + ); +ppm_L1_thrtl_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000010000000000" + ) + port map ( + I0 => cfg_pcie_link_state_d(1), + I1 => cfg_pcie_link_state_d(2), + I2 => cfg_pcie_link_state_d(0), + I3 => cfg_pcie_link_state(0), + I4 => cfg_pcie_link_state(1), + I5 => cfg_pcie_link_state(2), + O => \^ppm_l1_trig\ + ); +ppm_L1_thrtl_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => ppm_L1_thrtl_reg_0, + Q => \^ppm_l1_thrtl\, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +ppm_L23_thrtl_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"F8" + ) + port map ( + I0 => \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff\, + I1 => reg_turnoff_ok, + I2 => ppm_L23_thrtl, + O => ppm_L23_thrtl_i_1_n_0 + ); +ppm_L23_thrtl_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => ppm_L23_thrtl_i_1_n_0, + Q => ppm_L23_thrtl, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +reg_axi_in_pkt_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00005F40" + ) + port map ( + I0 => s_axis_tx_tlast, + I1 => \^tready_thrtl_reg_0\, + I2 => s_axis_tx_tvalid, + I3 => reg_axi_in_pkt, + I4 => \tbuf_gap_cnt_reg[0]_0\, + O => reg_axi_in_pkt_i_1_n_0 + ); +reg_axi_in_pkt_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => reg_axi_in_pkt_i_1_n_0, + Q => reg_axi_in_pkt, + R => '0' + ); +reg_tcfg_gnt_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => tx_cfg_gnt, + Q => \^reg_tcfg_gnt\, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +\tbuf_av_d_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => trn_tbuf_av(0), + Q => tbuf_av_d(0), + R => \tbuf_gap_cnt_reg[0]_0\ + ); +\tbuf_av_d_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => trn_tbuf_av(1), + Q => tbuf_av_d(1), + R => \tbuf_gap_cnt_reg[0]_0\ + ); +\tbuf_av_d_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => trn_tbuf_av(2), + Q => tbuf_av_d(2), + R => \tbuf_gap_cnt_reg[0]_0\ + ); +\tbuf_av_d_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => trn_tbuf_av(3), + Q => tbuf_av_d(3), + R => \tbuf_gap_cnt_reg[0]_0\ + ); +\tbuf_av_d_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => trn_tbuf_av(4), + Q => tbuf_av_d(4), + R => \tbuf_gap_cnt_reg[0]_0\ + ); +\tbuf_av_d_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => trn_tbuf_av(5), + Q => tbuf_av_d(5), + R => \tbuf_gap_cnt_reg[0]_0\ + ); +tbuf_av_gap_thrtl_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => tbuf_av_gap_trig, + I1 => \tbuf_gap_cnt_reg_n_0_[0]\, + I2 => tbuf_av_gap_thrtl, + O => tbuf_av_gap_thrtl_i_1_n_0 + ); +tbuf_av_gap_thrtl_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => tbuf_av_gap_thrtl_i_1_n_0, + Q => tbuf_av_gap_thrtl, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +tbuf_av_min_thrtl_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => tbuf_av_min_trig, + Q => tbuf_av_min_thrtl, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +\tbuf_gap_cnt[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => tbuf_av_gap_thrtl, + I1 => cur_state, + O => \tbuf_gap_cnt[0]_i_1_n_0\ + ); +\tbuf_gap_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => \tbuf_gap_cnt[0]_i_1_n_0\, + Q => \tbuf_gap_cnt_reg_n_0_[0]\, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +tcfg_gnt_pending_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F44444F4F4F4F4" + ) + port map ( + I0 => trn_tcfg_req_d, + I1 => trn_tcfg_req, + I2 => tcfg_gnt_pending, + I3 => cur_state, + I4 => pcie_block_i_i_36_n_0, + I5 => tcfg_req_thrtl, + O => tcfg_gnt_pending_i_1_n_0 + ); +tcfg_gnt_pending_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => tcfg_gnt_pending_i_1_n_0, + Q => tcfg_gnt_pending, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +\tcfg_req_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000D00" + ) + port map ( + I0 => trn_tcfg_req, + I1 => trn_tcfg_req_d, + I2 => tcfg_gnt_pending, + I3 => tcfg_req_cnt(1), + I4 => tcfg_req_cnt(0), + I5 => \tbuf_gap_cnt_reg[0]_0\, + O => \tcfg_req_cnt[0]_i_1_n_0\ + ); +\tcfg_req_cnt[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF88F8" + ) + port map ( + I0 => tcfg_req_cnt(0), + I1 => tcfg_req_cnt(1), + I2 => trn_tcfg_req, + I3 => trn_tcfg_req_d, + I4 => tcfg_gnt_pending, + O => \tcfg_req_cnt[1]_i_1_n_0\ + ); +\tcfg_req_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => \tcfg_req_cnt[0]_i_1_n_0\, + Q => tcfg_req_cnt(0), + R => '0' + ); +\tcfg_req_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => \tcfg_req_cnt[1]_i_1_n_0\, + Q => tcfg_req_cnt(1), + R => \tbuf_gap_cnt_reg[0]_0\ + ); +tcfg_req_thrtl_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF8FF88888888" + ) + port map ( + I0 => \^reg_tcfg_gnt\, + I1 => trn_tcfg_req, + I2 => trn_tdst_rdy_d, + I3 => trn_tdst_rdy, + I4 => p_2_in, + I5 => tcfg_req_thrtl, + O => tcfg_req_thrtl_i_1_n_0 + ); +tcfg_req_thrtl_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => tcfg_req_cnt(1), + I1 => tcfg_req_cnt(0), + O => p_2_in + ); +tcfg_req_thrtl_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => tcfg_req_thrtl_i_1_n_0, + Q => tcfg_req_thrtl, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +\throttle_ctl_pipeline.reg_tsrc_rdy_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => \^tready_thrtl_reg_0\, + I1 => s_axis_tx_tvalid, + I2 => \out\, + I3 => reg_disable_trn, + O => reg_tsrc_rdy0 + ); +tready_thrtl_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"F1F1F1F10000F100" + ) + port map ( + I0 => \ecrc_pause_enabled.reg_tx_ecrc_pkt\, + I1 => tready_thrtl_i_2_n_0, + I2 => tready_thrtl_i_3_n_0, + I3 => tready_thrtl_i_4_n_0, + I4 => tbuf_av_gap_trig, + I5 => tready_thrtl_i_6_n_0, + O => tready_thrtl0 + ); +tready_thrtl_i_10: unisim.vcomponents.LUT6 + generic map( + INIT => X"00002000AAAAAAAA" + ) + port map ( + I0 => tready_thrtl_i_5_0, + I1 => tbuf_av_d(4), + I2 => tbuf_av_d(0), + I3 => tbuf_av_d(1), + I4 => tready_thrtl_i_12_n_0, + I5 => tready_thrtl_i_3_n_0, + O => tready_thrtl_i_10_n_0 + ); +tready_thrtl_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => tbuf_av_d(5), + I1 => tbuf_av_d(2), + I2 => trn_tbuf_av(1), + I3 => tbuf_av_d(3), + O => tready_thrtl_i_12_n_0 + ); +tready_thrtl_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0078" + ) + port map ( + I0 => s_axis_tx_tdata(0), + I1 => s_axis_tx_tdata(3), + I2 => s_axis_tx_tdata(2), + I3 => tready_thrtl_i_7_n_0, + O => tready_thrtl_i_2_n_0 + ); +tready_thrtl_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"7F" + ) + port map ( + I0 => s_axis_tx_tlast, + I1 => s_axis_tx_tvalid, + I2 => \^tready_thrtl_reg_0\, + O => tready_thrtl_i_3_n_0 + ); +tready_thrtl_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000040000" + ) + port map ( + I0 => ppm_L23_trig, + I1 => \out\, + I2 => tcfg_req_trig, + I3 => \^ppm_l1_trig\, + I4 => cur_state_i_2_n_0, + I5 => tbuf_av_min_trig, + O => tready_thrtl_i_4_n_0 + ); +tready_thrtl_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00100000" + ) + port map ( + I0 => tcfg_req_cnt(0), + I1 => tcfg_req_cnt(1), + I2 => trn_tdst_rdy, + I3 => trn_tdst_rdy_d, + I4 => tcfg_req_thrtl, + I5 => tready_thrtl_i_10_n_0, + O => tbuf_av_gap_trig + ); +tready_thrtl_i_6: unisim.vcomponents.LUT5 + generic map( + INIT => X"000020E0" + ) + port map ( + I0 => reg_axi_in_pkt, + I1 => s_axis_tx_tvalid, + I2 => \^tready_thrtl_reg_0\, + I3 => s_axis_tx_tlast, + I4 => cur_state, + O => tready_thrtl_i_6_n_0 + ); +tready_thrtl_i_7: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFDFFF" + ) + port map ( + I0 => s_axis_tx_tuser(0), + I1 => s_axis_tx_tdata(1), + I2 => s_axis_tx_tvalid, + I3 => \^tready_thrtl_reg_0\, + I4 => reg_axi_in_pkt, + O => tready_thrtl_i_7_n_0 + ); +tready_thrtl_i_8: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => reg_turnoff_ok, + I1 => \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff\, + O => ppm_L23_trig + ); +tready_thrtl_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => tready_thrtl0, + Q => \^tready_thrtl_reg_0\, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +trn_tcfg_req_d_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => trn_tcfg_req, + Q => trn_tcfg_req_d, + R => \tbuf_gap_cnt_reg[0]_0\ + ); +trn_tdst_rdy_d_reg: unisim.vcomponents.FDSE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => trn_tdst_rdy, + Q => trn_tdst_rdy_d, + S => \tbuf_gap_cnt_reg[0]_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x is + port ( + gt_rxvalid_q_reg_0 : out STD_LOGIC; + gt_rx_phy_status_q : out STD_LOGIC; + gt_rxelecidle_q : out STD_LOGIC; + \pl_ltssm_state_q_reg[5]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 15 downto 0 ); + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gt_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_pclk_in : in STD_LOGIC; + gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 ); + gt_rxvalid_q_reg_1 : in STD_LOGIC; + PIPE_RXSTATUS : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \gt_rx_status_q_reg[0]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + PIPE_RXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + PIPE_RXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x is + signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \gt_rx_status_q[0]_i_1__2_n_0\ : STD_LOGIC; + signal \gt_rx_status_q[1]_i_1__2_n_0\ : STD_LOGIC; + signal \gt_rx_status_q[2]_i_1__2_n_0\ : STD_LOGIC; + signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC; + signal \gt_rxvalid_q__0\ : STD_LOGIC; + signal gt_rxvalid_q_i_2_n_0 : STD_LOGIC; + signal gt_rxvalid_q_n_0 : STD_LOGIC; + signal \^gt_rxvalid_q_reg_0\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \^pl_ltssm_state_q_reg[5]\ : STD_LOGIC; + signal \reg_state_eios_det[0]_i_2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[0]_i_3_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[0]_i_4_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[0]_i_5_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[1]_i_2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[1]_i_3_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[2]_i_2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[2]_i_3_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[3]_i_2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[4]_i_1_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[4]_i_3_n_0\ : STD_LOGIC; + signal reg_symbol_after_eios : STD_LOGIC; + signal reg_symbol_after_eios_i_2_n_0 : STD_LOGIC; + signal state_eios_det : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal symbol_after_eios : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gt_rx_status_q[0]_i_1__2\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \gt_rx_status_q[1]_i_1__2\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \gt_rx_status_q[2]_i_1__2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of gt_rxvalid_q : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \reg_state_eios_det[0]_i_3\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \reg_state_eios_det[1]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \reg_state_eios_det[1]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \reg_state_eios_det[2]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \reg_state_eios_det[3]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \reg_state_eios_det[3]_i_2\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \reg_state_eios_det[4]_i_3\ : label is "soft_lutpair0"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[0]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[1]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[2]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[3]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[4]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute SOFT_HLUTNM of reg_symbol_after_eios_i_2 : label is "soft_lutpair6"; +begin + Q(15 downto 0) <= \^q\(15 downto 0); + gt_rxvalid_q_reg_0 <= \^gt_rxvalid_q_reg_0\; + \pl_ltssm_state_q_reg[5]\ <= \^pl_ltssm_state_q_reg[5]\; +gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rx_phy_status_wire_filter(0), + Q => gt_rx_phy_status_q, + R => SR(0) + ); +\gt_rx_status_q[0]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \^pl_ltssm_state_q_reg[5]\, + I2 => PIPE_RXSTATUS(0), + O => \gt_rx_status_q[0]_i_1__2_n_0\ + ); +\gt_rx_status_q[1]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \^pl_ltssm_state_q_reg[5]\, + I2 => PIPE_RXSTATUS(1), + O => \gt_rx_status_q[1]_i_1__2_n_0\ + ); +\gt_rx_status_q[2]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \^pl_ltssm_state_q_reg[5]\, + I2 => PIPE_RXSTATUS(2), + O => \gt_rx_status_q[2]_i_1__2_n_0\ + ); +\gt_rx_status_q[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFBFFFFFF" + ) + port map ( + I0 => \gt_rx_status_q_reg[0]_0\(5), + I1 => \gt_rx_status_q_reg[0]_0\(4), + I2 => \gt_rx_status_q_reg[0]_0\(3), + I3 => \gt_rx_status_q_reg[0]_0\(2), + I4 => \gt_rx_status_q_reg[0]_0\(1), + I5 => \gt_rx_status_q_reg[0]_0\(0), + O => \^pl_ltssm_state_q_reg[5]\ + ); +\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rx_status_q[0]_i_1__2_n_0\, + Q => \gt_rx_status_q_reg[2]_0\(0), + R => SR(0) + ); +\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rx_status_q[1]_i_1__2_n_0\, + Q => \gt_rx_status_q_reg[2]_0\(1), + R => SR(0) + ); +\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rx_status_q[2]_i_1__2_n_0\, + Q => \gt_rx_status_q_reg[2]_0\(2), + R => SR(0) + ); +\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATAK(0), + Q => \gt_rxcharisk_q_reg_n_0_[0]\, + R => SR(0) + ); +\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATAK(1), + Q => p_1_in, + R => SR(0) + ); +\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(0), + Q => \^q\(0), + R => SR(0) + ); +\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(10), + Q => \^q\(10), + R => SR(0) + ); +\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(11), + Q => \^q\(11), + R => SR(0) + ); +\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(12), + Q => \^q\(12), + R => SR(0) + ); +\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(13), + Q => \^q\(13), + R => SR(0) + ); +\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(14), + Q => \^q\(14), + R => SR(0) + ); +\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(15), + Q => \^q\(15), + R => SR(0) + ); +\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(1), + Q => \^q\(1), + R => SR(0) + ); +\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(2), + Q => \^q\(2), + R => SR(0) + ); +\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(3), + Q => \^q\(3), + R => SR(0) + ); +\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(4), + Q => \^q\(4), + R => SR(0) + ); +\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(5), + Q => \^q\(5), + R => SR(0) + ); +\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(6), + Q => \^q\(6), + R => SR(0) + ); +\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(7), + Q => \^q\(7), + R => SR(0) + ); +\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(8), + Q => \^q\(8), + R => SR(0) + ); +\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(9), + Q => \^q\(9), + R => SR(0) + ); +gt_rxelecidle_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXELECIDLE(0), + Q => gt_rxelecidle_q, + R => SR(0) + ); +gt_rxvalid_q: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010116" + ) + port map ( + I0 => state_eios_det(0), + I1 => state_eios_det(1), + I2 => state_eios_det(2), + I3 => state_eios_det(3), + I4 => state_eios_det(4), + O => gt_rxvalid_q_n_0 + ); +gt_rxvalid_q_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFAAEAAA" + ) + port map ( + I0 => gt_rxvalid_q_i_2_n_0, + I1 => state_eios_det(2), + I2 => \reg_state_eios_det[3]_i_2_n_0\, + I3 => gt_rxvalid_q_reg_1, + I4 => state_eios_det(0), + O => \gt_rxvalid_q__0\ + ); +gt_rxvalid_q_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF50000CC550000" + ) + port map ( + I0 => gt_rxvalid_q_n_0, + I1 => \^pl_ltssm_state_q_reg[5]\, + I2 => \reg_state_eios_det[4]_i_3_n_0\, + I3 => state_eios_det(4), + I4 => gt_rxvalid_q_reg_1, + I5 => \reg_state_eios_det[0]_i_3_n_0\, + O => gt_rxvalid_q_i_2_n_0 + ); +gt_rxvalid_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rxvalid_q__0\, + Q => \^gt_rxvalid_q_reg_0\, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \gt_rxcharisk_q_reg_n_0_[0]\, + O => D(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => p_1_in, + I2 => symbol_after_eios, + O => D(1) + ); +\reg_state_eios_det[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFEFEFEEE" + ) + port map ( + I0 => state_eios_det(4), + I1 => \reg_state_eios_det[0]_i_2_n_0\, + I2 => \reg_state_eios_det[1]_i_2_n_0\, + I3 => \reg_state_eios_det[0]_i_3_n_0\, + I4 => \reg_state_eios_det[0]_i_4_n_0\, + I5 => \reg_state_eios_det[0]_i_5_n_0\, + O => \p_1_in__0\(0) + ); +\reg_state_eios_det[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF3AAFFAA00AAAA" + ) + port map ( + I0 => state_eios_det(2), + I1 => \^q\(7), + I2 => \^q\(6), + I3 => \^q\(15), + I4 => \^q\(14), + I5 => state_eios_det(0), + O => \reg_state_eios_det[0]_i_2_n_0\ + ); +\reg_state_eios_det[0]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => state_eios_det(3), + I1 => state_eios_det(1), + I2 => state_eios_det(2), + O => \reg_state_eios_det[0]_i_3_n_0\ + ); +\reg_state_eios_det[0]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(14), + I1 => state_eios_det(0), + O => \reg_state_eios_det[0]_i_4_n_0\ + ); +\reg_state_eios_det[0]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFE0E0E0FFE0FFE0" + ) + port map ( + I0 => state_eios_det(0), + I1 => state_eios_det(2), + I2 => \reg_state_eios_det[2]_i_2_n_0\, + I3 => \reg_state_eios_det[0]_i_3_n_0\, + I4 => \^q\(7), + I5 => \^q\(6), + O => \reg_state_eios_det[0]_i_5_n_0\ + ); +\reg_state_eios_det[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => \reg_state_eios_det[1]_i_2_n_0\, + I1 => state_eios_det(0), + I2 => \^q\(7), + I3 => \^q\(6), + I4 => \reg_state_eios_det[3]_i_2_n_0\, + O => \p_1_in__0\(1) + ); +\reg_state_eios_det[1]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFFF" + ) + port map ( + I0 => \reg_state_eios_det[1]_i_3_n_0\, + I1 => \gt_rxcharisk_q_reg_n_0_[0]\, + I2 => \^q\(4), + I3 => \^q\(5), + O => \reg_state_eios_det[1]_i_2_n_0\ + ); +\reg_state_eios_det[1]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(3), + I3 => \^q\(2), + O => \reg_state_eios_det[1]_i_3_n_0\ + ); +\reg_state_eios_det[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => \^q\(14), + I1 => \^q\(15), + I2 => state_eios_det(0), + I3 => \reg_state_eios_det[2]_i_2_n_0\, + O => \p_1_in__0\(2) + ); +\reg_state_eios_det[2]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFFF" + ) + port map ( + I0 => \reg_state_eios_det[2]_i_3_n_0\, + I1 => p_1_in, + I2 => \^q\(12), + I3 => \^q\(13), + O => \reg_state_eios_det[2]_i_2_n_0\ + ); +\reg_state_eios_det[2]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => \^q\(9), + I1 => \^q\(8), + I2 => \^q\(11), + I3 => \^q\(10), + O => \reg_state_eios_det[2]_i_3_n_0\ + ); +\reg_state_eios_det[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \reg_state_eios_det[3]_i_2_n_0\, + I1 => state_eios_det(2), + I2 => \reg_state_eios_det[4]_i_3_n_0\, + O => \p_1_in__0\(3) + ); +\reg_state_eios_det[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FD" + ) + port map ( + I0 => \^q\(14), + I1 => \^q\(15), + I2 => \reg_state_eios_det[2]_i_2_n_0\, + O => \reg_state_eios_det[3]_i_2_n_0\ + ); +\reg_state_eios_det[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010116" + ) + port map ( + I0 => state_eios_det(0), + I1 => state_eios_det(4), + I2 => state_eios_det(2), + I3 => state_eios_det(1), + I4 => state_eios_det(3), + O => \reg_state_eios_det[4]_i_1_n_0\ + ); +\reg_state_eios_det[4]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => state_eios_det(3), + I1 => state_eios_det(1), + I2 => \reg_state_eios_det[4]_i_3_n_0\, + O => \p_1_in__0\(4) + ); +\reg_state_eios_det[4]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FD" + ) + port map ( + I0 => \^q\(6), + I1 => \^q\(7), + I2 => \reg_state_eios_det[1]_i_2_n_0\, + O => \reg_state_eios_det[4]_i_3_n_0\ + ); +\reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1_n_0\, + D => \p_1_in__0\(0), + Q => state_eios_det(0), + S => SR(0) + ); +\reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1_n_0\, + D => \p_1_in__0\(1), + Q => state_eios_det(1), + R => SR(0) + ); +\reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1_n_0\, + D => \p_1_in__0\(2), + Q => state_eios_det(2), + R => SR(0) + ); +\reg_state_eios_det_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1_n_0\, + D => \p_1_in__0\(3), + Q => state_eios_det(3), + R => SR(0) + ); +\reg_state_eios_det_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1_n_0\, + D => \p_1_in__0\(4), + Q => state_eios_det(4), + R => SR(0) + ); +reg_symbol_after_eios_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000010" + ) + port map ( + I0 => \reg_state_eios_det[3]_i_2_n_0\, + I1 => state_eios_det(0), + I2 => state_eios_det(2), + I3 => state_eios_det(3), + I4 => state_eios_det(1), + I5 => reg_symbol_after_eios_i_2_n_0, + O => reg_symbol_after_eios + ); +reg_symbol_after_eios_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \reg_state_eios_det[4]_i_3_n_0\, + I1 => state_eios_det(4), + O => reg_symbol_after_eios_i_2_n_0 + ); +reg_symbol_after_eios_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => reg_symbol_after_eios, + Q => symbol_after_eios, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_34 is + port ( + gt_rxvalid_q_reg_0 : out STD_LOGIC; + gt_rx_phy_status_q_reg_0 : out STD_LOGIC; + gt_rxelecidle_q_reg_0 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 15 downto 0 ); + gt_rxvalid_q_reg_1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gt_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_pclk_in : in STD_LOGIC; + gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 ); + gt_rxvalid_q_reg_2 : in STD_LOGIC; + \gt_rx_status_q_reg[0]_0\ : in STD_LOGIC; + PIPE_RXSTATUS : in STD_LOGIC_VECTOR ( 2 downto 0 ); + PIPE_RXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + PIPE_RXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_34 : entity is "pcie_7x_0_gt_rx_valid_filter_7x"; +end pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_34; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_34 is + signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \gt_rx_status_q[0]_i_1__1_n_0\ : STD_LOGIC; + signal \gt_rx_status_q[1]_i_1__1_n_0\ : STD_LOGIC; + signal \gt_rx_status_q[2]_i_1__1_n_0\ : STD_LOGIC; + signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC; + signal \gt_rxvalid_q__0\ : STD_LOGIC; + signal \gt_rxvalid_q_i_2__0_n_0\ : STD_LOGIC; + signal gt_rxvalid_q_n_0 : STD_LOGIC; + signal \^gt_rxvalid_q_reg_0\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \reg_state_eios_det[0]_i_2__0_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[0]_i_3__0_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[0]_i_4__0_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[0]_i_5__0_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[1]_i_2__0_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[1]_i_3__0_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[2]_i_2__0_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[2]_i_3__0_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[3]_i_2__0_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[4]_i_1__0_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[4]_i_3__0_n_0\ : STD_LOGIC; + signal reg_symbol_after_eios : STD_LOGIC; + signal \reg_symbol_after_eios_i_2__0_n_0\ : STD_LOGIC; + signal state_eios_det : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal symbol_after_eios : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gt_rx_status_q[0]_i_1__1\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \gt_rx_status_q[1]_i_1__1\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \gt_rx_status_q[2]_i_1__1\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of gt_rxvalid_q : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__0\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__0\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \reg_state_eios_det[0]_i_3__0\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \reg_state_eios_det[1]_i_1__0\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \reg_state_eios_det[1]_i_2__0\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \reg_state_eios_det[2]_i_1__0\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \reg_state_eios_det[3]_i_1__0\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \reg_state_eios_det[3]_i_2__0\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \reg_state_eios_det[4]_i_3__0\ : label is "soft_lutpair7"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[0]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[1]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[2]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[3]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[4]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute SOFT_HLUTNM of \reg_symbol_after_eios_i_2__0\ : label is "soft_lutpair13"; +begin + Q(15 downto 0) <= \^q\(15 downto 0); + gt_rxvalid_q_reg_0 <= \^gt_rxvalid_q_reg_0\; +gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rx_phy_status_wire_filter(0), + Q => gt_rx_phy_status_q_reg_0, + R => SR(0) + ); +\gt_rx_status_q[0]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \gt_rx_status_q_reg[0]_0\, + I2 => PIPE_RXSTATUS(0), + O => \gt_rx_status_q[0]_i_1__1_n_0\ + ); +\gt_rx_status_q[1]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \gt_rx_status_q_reg[0]_0\, + I2 => PIPE_RXSTATUS(1), + O => \gt_rx_status_q[1]_i_1__1_n_0\ + ); +\gt_rx_status_q[2]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \gt_rx_status_q_reg[0]_0\, + I2 => PIPE_RXSTATUS(2), + O => \gt_rx_status_q[2]_i_1__1_n_0\ + ); +\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rx_status_q[0]_i_1__1_n_0\, + Q => \gt_rx_status_q_reg[2]_0\(0), + R => SR(0) + ); +\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rx_status_q[1]_i_1__1_n_0\, + Q => \gt_rx_status_q_reg[2]_0\(1), + R => SR(0) + ); +\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rx_status_q[2]_i_1__1_n_0\, + Q => \gt_rx_status_q_reg[2]_0\(2), + R => SR(0) + ); +\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATAK(0), + Q => \gt_rxcharisk_q_reg_n_0_[0]\, + R => SR(0) + ); +\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATAK(1), + Q => p_1_in, + R => SR(0) + ); +\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(0), + Q => \^q\(0), + R => SR(0) + ); +\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(10), + Q => \^q\(10), + R => SR(0) + ); +\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(11), + Q => \^q\(11), + R => SR(0) + ); +\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(12), + Q => \^q\(12), + R => SR(0) + ); +\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(13), + Q => \^q\(13), + R => SR(0) + ); +\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(14), + Q => \^q\(14), + R => SR(0) + ); +\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(15), + Q => \^q\(15), + R => SR(0) + ); +\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(1), + Q => \^q\(1), + R => SR(0) + ); +\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(2), + Q => \^q\(2), + R => SR(0) + ); +\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(3), + Q => \^q\(3), + R => SR(0) + ); +\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(4), + Q => \^q\(4), + R => SR(0) + ); +\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(5), + Q => \^q\(5), + R => SR(0) + ); +\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(6), + Q => \^q\(6), + R => SR(0) + ); +\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(7), + Q => \^q\(7), + R => SR(0) + ); +\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(8), + Q => \^q\(8), + R => SR(0) + ); +\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(9), + Q => \^q\(9), + R => SR(0) + ); +gt_rxelecidle_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXELECIDLE(0), + Q => gt_rxelecidle_q_reg_0, + R => SR(0) + ); +gt_rxvalid_q: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010116" + ) + port map ( + I0 => state_eios_det(0), + I1 => state_eios_det(1), + I2 => state_eios_det(2), + I3 => state_eios_det(3), + I4 => state_eios_det(4), + O => gt_rxvalid_q_n_0 + ); +\gt_rxvalid_q_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFAAEAAA" + ) + port map ( + I0 => \gt_rxvalid_q_i_2__0_n_0\, + I1 => state_eios_det(2), + I2 => \reg_state_eios_det[3]_i_2__0_n_0\, + I3 => gt_rxvalid_q_reg_2, + I4 => state_eios_det(0), + O => \gt_rxvalid_q__0\ + ); +\gt_rxvalid_q_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF50000CC550000" + ) + port map ( + I0 => gt_rxvalid_q_n_0, + I1 => \gt_rx_status_q_reg[0]_0\, + I2 => \reg_state_eios_det[4]_i_3__0_n_0\, + I3 => state_eios_det(4), + I4 => gt_rxvalid_q_reg_2, + I5 => \reg_state_eios_det[0]_i_3__0_n_0\, + O => \gt_rxvalid_q_i_2__0_n_0\ + ); +gt_rxvalid_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rxvalid_q__0\, + Q => \^gt_rxvalid_q_reg_0\, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \gt_rxcharisk_q_reg_n_0_[0]\, + O => gt_rxvalid_q_reg_1(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => p_1_in, + I2 => symbol_after_eios, + O => gt_rxvalid_q_reg_1(1) + ); +\reg_state_eios_det[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFEFEFEEE" + ) + port map ( + I0 => state_eios_det(4), + I1 => \reg_state_eios_det[0]_i_2__0_n_0\, + I2 => \reg_state_eios_det[1]_i_2__0_n_0\, + I3 => \reg_state_eios_det[0]_i_3__0_n_0\, + I4 => \reg_state_eios_det[0]_i_4__0_n_0\, + I5 => \reg_state_eios_det[0]_i_5__0_n_0\, + O => \p_1_in__0\(0) + ); +\reg_state_eios_det[0]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF3AAFFAA00AAAA" + ) + port map ( + I0 => state_eios_det(2), + I1 => \^q\(7), + I2 => \^q\(6), + I3 => \^q\(15), + I4 => \^q\(14), + I5 => state_eios_det(0), + O => \reg_state_eios_det[0]_i_2__0_n_0\ + ); +\reg_state_eios_det[0]_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => state_eios_det(3), + I1 => state_eios_det(1), + I2 => state_eios_det(2), + O => \reg_state_eios_det[0]_i_3__0_n_0\ + ); +\reg_state_eios_det[0]_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(14), + I1 => state_eios_det(0), + O => \reg_state_eios_det[0]_i_4__0_n_0\ + ); +\reg_state_eios_det[0]_i_5__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFE0E0E0FFE0FFE0" + ) + port map ( + I0 => state_eios_det(0), + I1 => state_eios_det(2), + I2 => \reg_state_eios_det[2]_i_2__0_n_0\, + I3 => \reg_state_eios_det[0]_i_3__0_n_0\, + I4 => \^q\(7), + I5 => \^q\(6), + O => \reg_state_eios_det[0]_i_5__0_n_0\ + ); +\reg_state_eios_det[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => \reg_state_eios_det[1]_i_2__0_n_0\, + I1 => state_eios_det(0), + I2 => \^q\(7), + I3 => \^q\(6), + I4 => \reg_state_eios_det[3]_i_2__0_n_0\, + O => \p_1_in__0\(1) + ); +\reg_state_eios_det[1]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFFF" + ) + port map ( + I0 => \reg_state_eios_det[1]_i_3__0_n_0\, + I1 => \gt_rxcharisk_q_reg_n_0_[0]\, + I2 => \^q\(4), + I3 => \^q\(5), + O => \reg_state_eios_det[1]_i_2__0_n_0\ + ); +\reg_state_eios_det[1]_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(3), + I3 => \^q\(2), + O => \reg_state_eios_det[1]_i_3__0_n_0\ + ); +\reg_state_eios_det[2]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => \^q\(14), + I1 => \^q\(15), + I2 => state_eios_det(0), + I3 => \reg_state_eios_det[2]_i_2__0_n_0\, + O => \p_1_in__0\(2) + ); +\reg_state_eios_det[2]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFFF" + ) + port map ( + I0 => \reg_state_eios_det[2]_i_3__0_n_0\, + I1 => p_1_in, + I2 => \^q\(12), + I3 => \^q\(13), + O => \reg_state_eios_det[2]_i_2__0_n_0\ + ); +\reg_state_eios_det[2]_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => \^q\(9), + I1 => \^q\(8), + I2 => \^q\(11), + I3 => \^q\(10), + O => \reg_state_eios_det[2]_i_3__0_n_0\ + ); +\reg_state_eios_det[3]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \reg_state_eios_det[3]_i_2__0_n_0\, + I1 => state_eios_det(2), + I2 => \reg_state_eios_det[4]_i_3__0_n_0\, + O => \p_1_in__0\(3) + ); +\reg_state_eios_det[3]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FD" + ) + port map ( + I0 => \^q\(14), + I1 => \^q\(15), + I2 => \reg_state_eios_det[2]_i_2__0_n_0\, + O => \reg_state_eios_det[3]_i_2__0_n_0\ + ); +\reg_state_eios_det[4]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010116" + ) + port map ( + I0 => state_eios_det(0), + I1 => state_eios_det(4), + I2 => state_eios_det(2), + I3 => state_eios_det(1), + I4 => state_eios_det(3), + O => \reg_state_eios_det[4]_i_1__0_n_0\ + ); +\reg_state_eios_det[4]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => state_eios_det(3), + I1 => state_eios_det(1), + I2 => \reg_state_eios_det[4]_i_3__0_n_0\, + O => \p_1_in__0\(4) + ); +\reg_state_eios_det[4]_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FD" + ) + port map ( + I0 => \^q\(6), + I1 => \^q\(7), + I2 => \reg_state_eios_det[1]_i_2__0_n_0\, + O => \reg_state_eios_det[4]_i_3__0_n_0\ + ); +\reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__0_n_0\, + D => \p_1_in__0\(0), + Q => state_eios_det(0), + S => SR(0) + ); +\reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__0_n_0\, + D => \p_1_in__0\(1), + Q => state_eios_det(1), + R => SR(0) + ); +\reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__0_n_0\, + D => \p_1_in__0\(2), + Q => state_eios_det(2), + R => SR(0) + ); +\reg_state_eios_det_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__0_n_0\, + D => \p_1_in__0\(3), + Q => state_eios_det(3), + R => SR(0) + ); +\reg_state_eios_det_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__0_n_0\, + D => \p_1_in__0\(4), + Q => state_eios_det(4), + R => SR(0) + ); +\reg_symbol_after_eios_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000010" + ) + port map ( + I0 => \reg_state_eios_det[3]_i_2__0_n_0\, + I1 => state_eios_det(0), + I2 => state_eios_det(2), + I3 => state_eios_det(3), + I4 => state_eios_det(1), + I5 => \reg_symbol_after_eios_i_2__0_n_0\, + O => reg_symbol_after_eios + ); +\reg_symbol_after_eios_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \reg_state_eios_det[4]_i_3__0_n_0\, + I1 => state_eios_det(4), + O => \reg_symbol_after_eios_i_2__0_n_0\ + ); +reg_symbol_after_eios_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => reg_symbol_after_eios, + Q => symbol_after_eios, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_35 is + port ( + gt_rxvalid_q_reg_0 : out STD_LOGIC; + gt_rx_phy_status_q_reg_0 : out STD_LOGIC; + gt_rxelecidle_q_reg_0 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 15 downto 0 ); + gt_rxvalid_q_reg_1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gt_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_pclk_in : in STD_LOGIC; + gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 ); + gt_rxvalid_q_reg_2 : in STD_LOGIC; + \gt_rx_status_q_reg[0]_0\ : in STD_LOGIC; + PIPE_RXSTATUS : in STD_LOGIC_VECTOR ( 2 downto 0 ); + PIPE_RXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + PIPE_RXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_35 : entity is "pcie_7x_0_gt_rx_valid_filter_7x"; +end pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_35; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_35 is + signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \gt_rx_status_q[0]_i_1__0_n_0\ : STD_LOGIC; + signal \gt_rx_status_q[1]_i_1__0_n_0\ : STD_LOGIC; + signal \gt_rx_status_q[2]_i_1__0_n_0\ : STD_LOGIC; + signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC; + signal \gt_rxvalid_q__0\ : STD_LOGIC; + signal \gt_rxvalid_q_i_2__1_n_0\ : STD_LOGIC; + signal gt_rxvalid_q_n_0 : STD_LOGIC; + signal \^gt_rxvalid_q_reg_0\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \reg_state_eios_det[0]_i_2__1_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[0]_i_3__1_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[0]_i_4__1_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[0]_i_5__1_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[1]_i_2__1_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[1]_i_3__1_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[2]_i_2__1_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[2]_i_3__1_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[3]_i_2__1_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[4]_i_1__1_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[4]_i_3__1_n_0\ : STD_LOGIC; + signal reg_symbol_after_eios : STD_LOGIC; + signal \reg_symbol_after_eios_i_2__1_n_0\ : STD_LOGIC; + signal state_eios_det : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal symbol_after_eios : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gt_rx_status_q[0]_i_1__0\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \gt_rx_status_q[1]_i_1__0\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \gt_rx_status_q[2]_i_1__0\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of gt_rxvalid_q : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \reg_state_eios_det[0]_i_3__1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \reg_state_eios_det[1]_i_1__1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \reg_state_eios_det[1]_i_2__1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \reg_state_eios_det[2]_i_1__1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \reg_state_eios_det[3]_i_1__1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \reg_state_eios_det[3]_i_2__1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \reg_state_eios_det[4]_i_3__1\ : label is "soft_lutpair14"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[0]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[1]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[2]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[3]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[4]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute SOFT_HLUTNM of \reg_symbol_after_eios_i_2__1\ : label is "soft_lutpair20"; +begin + Q(15 downto 0) <= \^q\(15 downto 0); + gt_rxvalid_q_reg_0 <= \^gt_rxvalid_q_reg_0\; +gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rx_phy_status_wire_filter(0), + Q => gt_rx_phy_status_q_reg_0, + R => SR(0) + ); +\gt_rx_status_q[0]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \gt_rx_status_q_reg[0]_0\, + I2 => PIPE_RXSTATUS(0), + O => \gt_rx_status_q[0]_i_1__0_n_0\ + ); +\gt_rx_status_q[1]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \gt_rx_status_q_reg[0]_0\, + I2 => PIPE_RXSTATUS(1), + O => \gt_rx_status_q[1]_i_1__0_n_0\ + ); +\gt_rx_status_q[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \gt_rx_status_q_reg[0]_0\, + I2 => PIPE_RXSTATUS(2), + O => \gt_rx_status_q[2]_i_1__0_n_0\ + ); +\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rx_status_q[0]_i_1__0_n_0\, + Q => \gt_rx_status_q_reg[2]_0\(0), + R => SR(0) + ); +\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rx_status_q[1]_i_1__0_n_0\, + Q => \gt_rx_status_q_reg[2]_0\(1), + R => SR(0) + ); +\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rx_status_q[2]_i_1__0_n_0\, + Q => \gt_rx_status_q_reg[2]_0\(2), + R => SR(0) + ); +\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATAK(0), + Q => \gt_rxcharisk_q_reg_n_0_[0]\, + R => SR(0) + ); +\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATAK(1), + Q => p_1_in, + R => SR(0) + ); +\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(0), + Q => \^q\(0), + R => SR(0) + ); +\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(10), + Q => \^q\(10), + R => SR(0) + ); +\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(11), + Q => \^q\(11), + R => SR(0) + ); +\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(12), + Q => \^q\(12), + R => SR(0) + ); +\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(13), + Q => \^q\(13), + R => SR(0) + ); +\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(14), + Q => \^q\(14), + R => SR(0) + ); +\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(15), + Q => \^q\(15), + R => SR(0) + ); +\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(1), + Q => \^q\(1), + R => SR(0) + ); +\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(2), + Q => \^q\(2), + R => SR(0) + ); +\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(3), + Q => \^q\(3), + R => SR(0) + ); +\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(4), + Q => \^q\(4), + R => SR(0) + ); +\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(5), + Q => \^q\(5), + R => SR(0) + ); +\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(6), + Q => \^q\(6), + R => SR(0) + ); +\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(7), + Q => \^q\(7), + R => SR(0) + ); +\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(8), + Q => \^q\(8), + R => SR(0) + ); +\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(9), + Q => \^q\(9), + R => SR(0) + ); +gt_rxelecidle_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXELECIDLE(0), + Q => gt_rxelecidle_q_reg_0, + R => SR(0) + ); +gt_rxvalid_q: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010116" + ) + port map ( + I0 => state_eios_det(0), + I1 => state_eios_det(1), + I2 => state_eios_det(2), + I3 => state_eios_det(3), + I4 => state_eios_det(4), + O => gt_rxvalid_q_n_0 + ); +\gt_rxvalid_q_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFAAEAAA" + ) + port map ( + I0 => \gt_rxvalid_q_i_2__1_n_0\, + I1 => state_eios_det(2), + I2 => \reg_state_eios_det[3]_i_2__1_n_0\, + I3 => gt_rxvalid_q_reg_2, + I4 => state_eios_det(0), + O => \gt_rxvalid_q__0\ + ); +\gt_rxvalid_q_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF50000CC550000" + ) + port map ( + I0 => gt_rxvalid_q_n_0, + I1 => \gt_rx_status_q_reg[0]_0\, + I2 => \reg_state_eios_det[4]_i_3__1_n_0\, + I3 => state_eios_det(4), + I4 => gt_rxvalid_q_reg_2, + I5 => \reg_state_eios_det[0]_i_3__1_n_0\, + O => \gt_rxvalid_q_i_2__1_n_0\ + ); +gt_rxvalid_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rxvalid_q__0\, + Q => \^gt_rxvalid_q_reg_0\, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \gt_rxcharisk_q_reg_n_0_[0]\, + O => gt_rxvalid_q_reg_1(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => p_1_in, + I2 => symbol_after_eios, + O => gt_rxvalid_q_reg_1(1) + ); +\reg_state_eios_det[0]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFEFEFEEE" + ) + port map ( + I0 => state_eios_det(4), + I1 => \reg_state_eios_det[0]_i_2__1_n_0\, + I2 => \reg_state_eios_det[1]_i_2__1_n_0\, + I3 => \reg_state_eios_det[0]_i_3__1_n_0\, + I4 => \reg_state_eios_det[0]_i_4__1_n_0\, + I5 => \reg_state_eios_det[0]_i_5__1_n_0\, + O => \p_1_in__0\(0) + ); +\reg_state_eios_det[0]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF3AAFFAA00AAAA" + ) + port map ( + I0 => state_eios_det(2), + I1 => \^q\(7), + I2 => \^q\(6), + I3 => \^q\(15), + I4 => \^q\(14), + I5 => state_eios_det(0), + O => \reg_state_eios_det[0]_i_2__1_n_0\ + ); +\reg_state_eios_det[0]_i_3__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => state_eios_det(3), + I1 => state_eios_det(1), + I2 => state_eios_det(2), + O => \reg_state_eios_det[0]_i_3__1_n_0\ + ); +\reg_state_eios_det[0]_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(14), + I1 => state_eios_det(0), + O => \reg_state_eios_det[0]_i_4__1_n_0\ + ); +\reg_state_eios_det[0]_i_5__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFE0E0E0FFE0FFE0" + ) + port map ( + I0 => state_eios_det(0), + I1 => state_eios_det(2), + I2 => \reg_state_eios_det[2]_i_2__1_n_0\, + I3 => \reg_state_eios_det[0]_i_3__1_n_0\, + I4 => \^q\(7), + I5 => \^q\(6), + O => \reg_state_eios_det[0]_i_5__1_n_0\ + ); +\reg_state_eios_det[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => \reg_state_eios_det[1]_i_2__1_n_0\, + I1 => state_eios_det(0), + I2 => \^q\(7), + I3 => \^q\(6), + I4 => \reg_state_eios_det[3]_i_2__1_n_0\, + O => \p_1_in__0\(1) + ); +\reg_state_eios_det[1]_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFFF" + ) + port map ( + I0 => \reg_state_eios_det[1]_i_3__1_n_0\, + I1 => \gt_rxcharisk_q_reg_n_0_[0]\, + I2 => \^q\(4), + I3 => \^q\(5), + O => \reg_state_eios_det[1]_i_2__1_n_0\ + ); +\reg_state_eios_det[1]_i_3__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(3), + I3 => \^q\(2), + O => \reg_state_eios_det[1]_i_3__1_n_0\ + ); +\reg_state_eios_det[2]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => \^q\(14), + I1 => \^q\(15), + I2 => state_eios_det(0), + I3 => \reg_state_eios_det[2]_i_2__1_n_0\, + O => \p_1_in__0\(2) + ); +\reg_state_eios_det[2]_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFFF" + ) + port map ( + I0 => \reg_state_eios_det[2]_i_3__1_n_0\, + I1 => p_1_in, + I2 => \^q\(12), + I3 => \^q\(13), + O => \reg_state_eios_det[2]_i_2__1_n_0\ + ); +\reg_state_eios_det[2]_i_3__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => \^q\(9), + I1 => \^q\(8), + I2 => \^q\(11), + I3 => \^q\(10), + O => \reg_state_eios_det[2]_i_3__1_n_0\ + ); +\reg_state_eios_det[3]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \reg_state_eios_det[3]_i_2__1_n_0\, + I1 => state_eios_det(2), + I2 => \reg_state_eios_det[4]_i_3__1_n_0\, + O => \p_1_in__0\(3) + ); +\reg_state_eios_det[3]_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FD" + ) + port map ( + I0 => \^q\(14), + I1 => \^q\(15), + I2 => \reg_state_eios_det[2]_i_2__1_n_0\, + O => \reg_state_eios_det[3]_i_2__1_n_0\ + ); +\reg_state_eios_det[4]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010116" + ) + port map ( + I0 => state_eios_det(0), + I1 => state_eios_det(4), + I2 => state_eios_det(2), + I3 => state_eios_det(1), + I4 => state_eios_det(3), + O => \reg_state_eios_det[4]_i_1__1_n_0\ + ); +\reg_state_eios_det[4]_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => state_eios_det(3), + I1 => state_eios_det(1), + I2 => \reg_state_eios_det[4]_i_3__1_n_0\, + O => \p_1_in__0\(4) + ); +\reg_state_eios_det[4]_i_3__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FD" + ) + port map ( + I0 => \^q\(6), + I1 => \^q\(7), + I2 => \reg_state_eios_det[1]_i_2__1_n_0\, + O => \reg_state_eios_det[4]_i_3__1_n_0\ + ); +\reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__1_n_0\, + D => \p_1_in__0\(0), + Q => state_eios_det(0), + S => SR(0) + ); +\reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__1_n_0\, + D => \p_1_in__0\(1), + Q => state_eios_det(1), + R => SR(0) + ); +\reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__1_n_0\, + D => \p_1_in__0\(2), + Q => state_eios_det(2), + R => SR(0) + ); +\reg_state_eios_det_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__1_n_0\, + D => \p_1_in__0\(3), + Q => state_eios_det(3), + R => SR(0) + ); +\reg_state_eios_det_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__1_n_0\, + D => \p_1_in__0\(4), + Q => state_eios_det(4), + R => SR(0) + ); +\reg_symbol_after_eios_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000010" + ) + port map ( + I0 => \reg_state_eios_det[3]_i_2__1_n_0\, + I1 => state_eios_det(0), + I2 => state_eios_det(2), + I3 => state_eios_det(3), + I4 => state_eios_det(1), + I5 => \reg_symbol_after_eios_i_2__1_n_0\, + O => reg_symbol_after_eios + ); +\reg_symbol_after_eios_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \reg_state_eios_det[4]_i_3__1_n_0\, + I1 => state_eios_det(4), + O => \reg_symbol_after_eios_i_2__1_n_0\ + ); +reg_symbol_after_eios_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => reg_symbol_after_eios, + Q => symbol_after_eios, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_36 is + port ( + gt_rxvalid_q_reg_0 : out STD_LOGIC; + gt_rx_phy_status_q_reg_0 : out STD_LOGIC; + gt_rxelecidle_q_reg_0 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 15 downto 0 ); + gt_rxvalid_q_reg_1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gt_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_pclk_in : in STD_LOGIC; + gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 ); + gt_rxvalid_q_reg_2 : in STD_LOGIC; + \gt_rx_status_q_reg[0]_0\ : in STD_LOGIC; + PIPE_RXSTATUS : in STD_LOGIC_VECTOR ( 2 downto 0 ); + PIPE_RXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + PIPE_RXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_36 : entity is "pcie_7x_0_gt_rx_valid_filter_7x"; +end pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_36; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_36 is + signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \gt_rx_status_q[0]_i_1_n_0\ : STD_LOGIC; + signal \gt_rx_status_q[1]_i_1_n_0\ : STD_LOGIC; + signal \gt_rx_status_q[2]_i_1_n_0\ : STD_LOGIC; + signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC; + signal \gt_rxvalid_q__0\ : STD_LOGIC; + signal \gt_rxvalid_q_i_2__2_n_0\ : STD_LOGIC; + signal gt_rxvalid_q_n_0 : STD_LOGIC; + signal \^gt_rxvalid_q_reg_0\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \reg_state_eios_det[0]_i_2__2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[0]_i_3__2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[0]_i_4__2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[0]_i_5__2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[1]_i_2__2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[1]_i_3__2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[2]_i_2__2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[2]_i_3__2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[3]_i_2__2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[4]_i_1__2_n_0\ : STD_LOGIC; + signal \reg_state_eios_det[4]_i_3__2_n_0\ : STD_LOGIC; + signal reg_symbol_after_eios : STD_LOGIC; + signal \reg_symbol_after_eios_i_2__2_n_0\ : STD_LOGIC; + signal state_eios_det : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal symbol_after_eios : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gt_rx_status_q[0]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \gt_rx_status_q[1]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \gt_rx_status_q[2]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of gt_rxvalid_q : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__2\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__2\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \reg_state_eios_det[0]_i_3__2\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \reg_state_eios_det[1]_i_1__2\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \reg_state_eios_det[1]_i_2__2\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \reg_state_eios_det[2]_i_1__2\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \reg_state_eios_det[3]_i_1__2\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \reg_state_eios_det[3]_i_2__2\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \reg_state_eios_det[4]_i_3__2\ : label is "soft_lutpair21"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[0]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[1]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[2]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[3]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[4]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000"; + attribute SOFT_HLUTNM of \reg_symbol_after_eios_i_2__2\ : label is "soft_lutpair27"; +begin + Q(15 downto 0) <= \^q\(15 downto 0); + gt_rxvalid_q_reg_0 <= \^gt_rxvalid_q_reg_0\; +gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rx_phy_status_wire_filter(0), + Q => gt_rx_phy_status_q_reg_0, + R => SR(0) + ); +\gt_rx_status_q[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \gt_rx_status_q_reg[0]_0\, + I2 => PIPE_RXSTATUS(0), + O => \gt_rx_status_q[0]_i_1_n_0\ + ); +\gt_rx_status_q[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \gt_rx_status_q_reg[0]_0\, + I2 => PIPE_RXSTATUS(1), + O => \gt_rx_status_q[1]_i_1_n_0\ + ); +\gt_rx_status_q[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \gt_rx_status_q_reg[0]_0\, + I2 => PIPE_RXSTATUS(2), + O => \gt_rx_status_q[2]_i_1_n_0\ + ); +\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rx_status_q[0]_i_1_n_0\, + Q => \gt_rx_status_q_reg[2]_0\(0), + R => SR(0) + ); +\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rx_status_q[1]_i_1_n_0\, + Q => \gt_rx_status_q_reg[2]_0\(1), + R => SR(0) + ); +\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rx_status_q[2]_i_1_n_0\, + Q => \gt_rx_status_q_reg[2]_0\(2), + R => SR(0) + ); +\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATAK(0), + Q => \gt_rxcharisk_q_reg_n_0_[0]\, + R => SR(0) + ); +\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATAK(1), + Q => p_1_in, + R => SR(0) + ); +\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(0), + Q => \^q\(0), + R => SR(0) + ); +\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(10), + Q => \^q\(10), + R => SR(0) + ); +\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(11), + Q => \^q\(11), + R => SR(0) + ); +\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(12), + Q => \^q\(12), + R => SR(0) + ); +\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(13), + Q => \^q\(13), + R => SR(0) + ); +\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(14), + Q => \^q\(14), + R => SR(0) + ); +\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(15), + Q => \^q\(15), + R => SR(0) + ); +\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(1), + Q => \^q\(1), + R => SR(0) + ); +\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(2), + Q => \^q\(2), + R => SR(0) + ); +\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(3), + Q => \^q\(3), + R => SR(0) + ); +\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(4), + Q => \^q\(4), + R => SR(0) + ); +\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(5), + Q => \^q\(5), + R => SR(0) + ); +\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(6), + Q => \^q\(6), + R => SR(0) + ); +\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(7), + Q => \^q\(7), + R => SR(0) + ); +\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(8), + Q => \^q\(8), + R => SR(0) + ); +\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXDATA(9), + Q => \^q\(9), + R => SR(0) + ); +gt_rxelecidle_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXELECIDLE(0), + Q => gt_rxelecidle_q_reg_0, + R => SR(0) + ); +gt_rxvalid_q: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010116" + ) + port map ( + I0 => state_eios_det(0), + I1 => state_eios_det(1), + I2 => state_eios_det(2), + I3 => state_eios_det(3), + I4 => state_eios_det(4), + O => gt_rxvalid_q_n_0 + ); +\gt_rxvalid_q_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFAAEAAA" + ) + port map ( + I0 => \gt_rxvalid_q_i_2__2_n_0\, + I1 => state_eios_det(2), + I2 => \reg_state_eios_det[3]_i_2__2_n_0\, + I3 => gt_rxvalid_q_reg_2, + I4 => state_eios_det(0), + O => \gt_rxvalid_q__0\ + ); +\gt_rxvalid_q_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF50000CC550000" + ) + port map ( + I0 => gt_rxvalid_q_n_0, + I1 => \gt_rx_status_q_reg[0]_0\, + I2 => \reg_state_eios_det[4]_i_3__2_n_0\, + I3 => state_eios_det(4), + I4 => gt_rxvalid_q_reg_2, + I5 => \reg_state_eios_det[0]_i_3__2_n_0\, + O => \gt_rxvalid_q_i_2__2_n_0\ + ); +gt_rxvalid_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gt_rxvalid_q__0\, + Q => \^gt_rxvalid_q_reg_0\, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => \gt_rxcharisk_q_reg_n_0_[0]\, + O => gt_rxvalid_q_reg_1(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => \^gt_rxvalid_q_reg_0\, + I1 => p_1_in, + I2 => symbol_after_eios, + O => gt_rxvalid_q_reg_1(1) + ); +\reg_state_eios_det[0]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFEFEFEEE" + ) + port map ( + I0 => state_eios_det(4), + I1 => \reg_state_eios_det[0]_i_2__2_n_0\, + I2 => \reg_state_eios_det[1]_i_2__2_n_0\, + I3 => \reg_state_eios_det[0]_i_3__2_n_0\, + I4 => \reg_state_eios_det[0]_i_4__2_n_0\, + I5 => \reg_state_eios_det[0]_i_5__2_n_0\, + O => \p_1_in__0\(0) + ); +\reg_state_eios_det[0]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFAA8A8AFF00FFAA" + ) + port map ( + I0 => state_eios_det(0), + I1 => \^q\(6), + I2 => \^q\(7), + I3 => state_eios_det(2), + I4 => \^q\(15), + I5 => \^q\(14), + O => \reg_state_eios_det[0]_i_2__2_n_0\ + ); +\reg_state_eios_det[0]_i_3__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => state_eios_det(3), + I1 => state_eios_det(1), + I2 => state_eios_det(2), + O => \reg_state_eios_det[0]_i_3__2_n_0\ + ); +\reg_state_eios_det[0]_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => state_eios_det(0), + I1 => \^q\(15), + O => \reg_state_eios_det[0]_i_4__2_n_0\ + ); +\reg_state_eios_det[0]_i_5__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFE0E0E0FFE0FFE0" + ) + port map ( + I0 => state_eios_det(0), + I1 => state_eios_det(2), + I2 => \reg_state_eios_det[2]_i_2__2_n_0\, + I3 => \reg_state_eios_det[0]_i_3__2_n_0\, + I4 => \^q\(7), + I5 => \^q\(6), + O => \reg_state_eios_det[0]_i_5__2_n_0\ + ); +\reg_state_eios_det[1]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => \reg_state_eios_det[1]_i_2__2_n_0\, + I1 => state_eios_det(0), + I2 => \^q\(7), + I3 => \^q\(6), + I4 => \reg_state_eios_det[3]_i_2__2_n_0\, + O => \p_1_in__0\(1) + ); +\reg_state_eios_det[1]_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFFF" + ) + port map ( + I0 => \reg_state_eios_det[1]_i_3__2_n_0\, + I1 => \gt_rxcharisk_q_reg_n_0_[0]\, + I2 => \^q\(4), + I3 => \^q\(5), + O => \reg_state_eios_det[1]_i_2__2_n_0\ + ); +\reg_state_eios_det[1]_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(3), + I3 => \^q\(2), + O => \reg_state_eios_det[1]_i_3__2_n_0\ + ); +\reg_state_eios_det[2]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => \^q\(14), + I1 => \^q\(15), + I2 => state_eios_det(0), + I3 => \reg_state_eios_det[2]_i_2__2_n_0\, + O => \p_1_in__0\(2) + ); +\reg_state_eios_det[2]_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFFF" + ) + port map ( + I0 => \reg_state_eios_det[2]_i_3__2_n_0\, + I1 => p_1_in, + I2 => \^q\(12), + I3 => \^q\(13), + O => \reg_state_eios_det[2]_i_2__2_n_0\ + ); +\reg_state_eios_det[2]_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => \^q\(9), + I1 => \^q\(8), + I2 => \^q\(11), + I3 => \^q\(10), + O => \reg_state_eios_det[2]_i_3__2_n_0\ + ); +\reg_state_eios_det[3]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \reg_state_eios_det[3]_i_2__2_n_0\, + I1 => state_eios_det(2), + I2 => \reg_state_eios_det[4]_i_3__2_n_0\, + O => \p_1_in__0\(3) + ); +\reg_state_eios_det[3]_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FD" + ) + port map ( + I0 => \^q\(14), + I1 => \^q\(15), + I2 => \reg_state_eios_det[2]_i_2__2_n_0\, + O => \reg_state_eios_det[3]_i_2__2_n_0\ + ); +\reg_state_eios_det[4]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010116" + ) + port map ( + I0 => state_eios_det(0), + I1 => state_eios_det(4), + I2 => state_eios_det(2), + I3 => state_eios_det(1), + I4 => state_eios_det(3), + O => \reg_state_eios_det[4]_i_1__2_n_0\ + ); +\reg_state_eios_det[4]_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => state_eios_det(3), + I1 => state_eios_det(1), + I2 => \reg_state_eios_det[4]_i_3__2_n_0\, + O => \p_1_in__0\(4) + ); +\reg_state_eios_det[4]_i_3__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FD" + ) + port map ( + I0 => \^q\(6), + I1 => \^q\(7), + I2 => \reg_state_eios_det[1]_i_2__2_n_0\, + O => \reg_state_eios_det[4]_i_3__2_n_0\ + ); +\reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__2_n_0\, + D => \p_1_in__0\(0), + Q => state_eios_det(0), + S => SR(0) + ); +\reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__2_n_0\, + D => \p_1_in__0\(1), + Q => state_eios_det(1), + R => SR(0) + ); +\reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__2_n_0\, + D => \p_1_in__0\(2), + Q => state_eios_det(2), + R => SR(0) + ); +\reg_state_eios_det_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__2_n_0\, + D => \p_1_in__0\(3), + Q => state_eios_det(3), + R => SR(0) + ); +\reg_state_eios_det_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => \reg_state_eios_det[4]_i_1__2_n_0\, + D => \p_1_in__0\(4), + Q => state_eios_det(4), + R => SR(0) + ); +\reg_symbol_after_eios_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000010" + ) + port map ( + I0 => \reg_state_eios_det[3]_i_2__2_n_0\, + I1 => state_eios_det(0), + I2 => state_eios_det(2), + I3 => state_eios_det(3), + I4 => state_eios_det(1), + I5 => \reg_symbol_after_eios_i_2__2_n_0\, + O => reg_symbol_after_eios + ); +\reg_symbol_after_eios_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \reg_state_eios_det[4]_i_3__2_n_0\, + I1 => state_eios_det(4), + O => \reg_symbol_after_eios_i_2__2_n_0\ + ); +reg_symbol_after_eios_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => reg_symbol_after_eios, + Q => symbol_after_eios, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd is + port ( + cpllpd_2 : out STD_LOGIC; + CPLLRESET0 : out STD_LOGIC; + gt_cpllpdrefclk : in STD_LOGIC; + rate_cpllreset_3 : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd is + signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC; + signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC; + signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC; + signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC; + signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC; + signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC; + signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC; + signal cpllrst : STD_LOGIC; + signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg "; + attribute srl_name : string; + attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 "; + attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg "; + attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 "; + attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg "; + attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 "; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no"; + attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 "; + attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no"; + attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 "; + attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 "; + attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 "; +begin +\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"FFFFFFFF" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => '0', + Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\, + Q31 => \cpllpd_wait_reg[31]_srl32_n_1\ + ); +\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"FFFFFFFF" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllpd_wait_reg[31]_srl32_n_1\, + Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\, + Q31 => \cpllpd_wait_reg[63]_srl32_n_1\ + ); +\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"7FFFFFFF" + ) + port map ( + A(4 downto 0) => B"11110", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllpd_wait_reg[63]_srl32_n_1\, + Q => \cpllpd_wait_reg[94]_srl31_n_0\, + Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ + ); +\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => gt_cpllpdrefclk, + CE => '1', + D => \cpllpd_wait_reg[94]_srl31_n_0\, + Q => cpllpd_2, + R => '0' + ); +\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => B"11110", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllreset_wait_reg[95]_srl32_n_1\, + Q => \cpllreset_wait_reg[126]_srl31_n_0\, + Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ + ); +\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => gt_cpllpdrefclk, + CE => '1', + D => \cpllreset_wait_reg[126]_srl31_n_0\, + Q => cpllrst, + R => '0' + ); +\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"000000FF" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => '0', + Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\, + Q31 => \cpllreset_wait_reg[31]_srl32_n_1\ + ); +\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllreset_wait_reg[31]_srl32_n_1\, + Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\, + Q31 => \cpllreset_wait_reg[63]_srl32_n_1\ + ); +\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllreset_wait_reg[63]_srl32_n_1\, + Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\, + Q31 => \cpllreset_wait_reg[95]_srl32_n_1\ + ); +\gtx_channel.gtxe2_channel_i_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => cpllrst, + I1 => rate_cpllreset_3, + I2 => RST_CPLLRESET, + O => CPLLRESET0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_56 is + port ( + cpllpd_1 : out STD_LOGIC; + CPLLRESET0 : out STD_LOGIC; + gt_cpllpdrefclk : in STD_LOGIC; + rate_cpllreset_2 : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_56 : entity is "pcie_7x_0_gtx_cpllpd_ovrd"; +end pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_56; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_56 is + signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC; + signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC; + signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC; + signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC; + signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC; + signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC; + signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC; + signal cpllrst : STD_LOGIC; + signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg "; + attribute srl_name : string; + attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 "; + attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg "; + attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 "; + attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg "; + attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 "; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no"; + attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 "; + attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no"; + attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 "; + attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 "; + attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 "; +begin +\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"FFFFFFFF" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => '0', + Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\, + Q31 => \cpllpd_wait_reg[31]_srl32_n_1\ + ); +\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"FFFFFFFF" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllpd_wait_reg[31]_srl32_n_1\, + Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\, + Q31 => \cpllpd_wait_reg[63]_srl32_n_1\ + ); +\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"7FFFFFFF" + ) + port map ( + A(4 downto 0) => B"11110", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllpd_wait_reg[63]_srl32_n_1\, + Q => \cpllpd_wait_reg[94]_srl31_n_0\, + Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ + ); +\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => gt_cpllpdrefclk, + CE => '1', + D => \cpllpd_wait_reg[94]_srl31_n_0\, + Q => cpllpd_1, + R => '0' + ); +\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => B"11110", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllreset_wait_reg[95]_srl32_n_1\, + Q => \cpllreset_wait_reg[126]_srl31_n_0\, + Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ + ); +\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => gt_cpllpdrefclk, + CE => '1', + D => \cpllreset_wait_reg[126]_srl31_n_0\, + Q => cpllrst, + R => '0' + ); +\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"000000FF" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => '0', + Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\, + Q31 => \cpllreset_wait_reg[31]_srl32_n_1\ + ); +\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllreset_wait_reg[31]_srl32_n_1\, + Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\, + Q31 => \cpllreset_wait_reg[63]_srl32_n_1\ + ); +\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllreset_wait_reg[63]_srl32_n_1\, + Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\, + Q31 => \cpllreset_wait_reg[95]_srl32_n_1\ + ); +\gtx_channel.gtxe2_channel_i_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => cpllrst, + I1 => rate_cpllreset_2, + I2 => RST_CPLLRESET, + O => CPLLRESET0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_58 is + port ( + cpllpd_0 : out STD_LOGIC; + CPLLRESET0 : out STD_LOGIC; + gt_cpllpdrefclk : in STD_LOGIC; + rate_cpllreset_1 : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_58 : entity is "pcie_7x_0_gtx_cpllpd_ovrd"; +end pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_58; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_58 is + signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC; + signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC; + signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC; + signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC; + signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC; + signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC; + signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC; + signal cpllrst : STD_LOGIC; + signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg "; + attribute srl_name : string; + attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 "; + attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg "; + attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 "; + attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg "; + attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 "; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no"; + attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 "; + attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no"; + attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 "; + attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 "; + attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 "; +begin +\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"FFFFFFFF" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => '0', + Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\, + Q31 => \cpllpd_wait_reg[31]_srl32_n_1\ + ); +\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"FFFFFFFF" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllpd_wait_reg[31]_srl32_n_1\, + Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\, + Q31 => \cpllpd_wait_reg[63]_srl32_n_1\ + ); +\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"7FFFFFFF" + ) + port map ( + A(4 downto 0) => B"11110", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllpd_wait_reg[63]_srl32_n_1\, + Q => \cpllpd_wait_reg[94]_srl31_n_0\, + Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ + ); +\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => gt_cpllpdrefclk, + CE => '1', + D => \cpllpd_wait_reg[94]_srl31_n_0\, + Q => cpllpd_0, + R => '0' + ); +\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => B"11110", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllreset_wait_reg[95]_srl32_n_1\, + Q => \cpllreset_wait_reg[126]_srl31_n_0\, + Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ + ); +\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => gt_cpllpdrefclk, + CE => '1', + D => \cpllreset_wait_reg[126]_srl31_n_0\, + Q => cpllrst, + R => '0' + ); +\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"000000FF" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => '0', + Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\, + Q31 => \cpllreset_wait_reg[31]_srl32_n_1\ + ); +\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllreset_wait_reg[31]_srl32_n_1\, + Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\, + Q31 => \cpllreset_wait_reg[63]_srl32_n_1\ + ); +\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllreset_wait_reg[63]_srl32_n_1\, + Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\, + Q31 => \cpllreset_wait_reg[95]_srl32_n_1\ + ); +\gtx_channel.gtxe2_channel_i_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => cpllrst, + I1 => rate_cpllreset_1, + I2 => RST_CPLLRESET, + O => CPLLRESET0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_60 is + port ( + cpllpd : out STD_LOGIC; + CPLLRESET0 : out STD_LOGIC; + gt_cpllpdrefclk : in STD_LOGIC; + rate_cpllreset_0 : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_60 : entity is "pcie_7x_0_gtx_cpllpd_ovrd"; +end pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_60; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_60 is + signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC; + signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC; + signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC; + signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC; + signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC; + signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC; + signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC; + signal cpllrst : STD_LOGIC; + signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg "; + attribute srl_name : string; + attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 "; + attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg "; + attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 "; + attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg "; + attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 "; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no"; + attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 "; + attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no"; + attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 "; + attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 "; + attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg "; + attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 "; +begin +\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"FFFFFFFF" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => '0', + Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\, + Q31 => \cpllpd_wait_reg[31]_srl32_n_1\ + ); +\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"FFFFFFFF" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllpd_wait_reg[31]_srl32_n_1\, + Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\, + Q31 => \cpllpd_wait_reg[63]_srl32_n_1\ + ); +\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"7FFFFFFF" + ) + port map ( + A(4 downto 0) => B"11110", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllpd_wait_reg[63]_srl32_n_1\, + Q => \cpllpd_wait_reg[94]_srl31_n_0\, + Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ + ); +\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => gt_cpllpdrefclk, + CE => '1', + D => \cpllpd_wait_reg[94]_srl31_n_0\, + Q => cpllpd, + R => '0' + ); +\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => B"11110", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllreset_wait_reg[95]_srl32_n_1\, + Q => \cpllreset_wait_reg[126]_srl31_n_0\, + Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ + ); +\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => gt_cpllpdrefclk, + CE => '1', + D => \cpllreset_wait_reg[126]_srl31_n_0\, + Q => cpllrst, + R => '0' + ); +\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"000000FF" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => '0', + Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\, + Q31 => \cpllreset_wait_reg[31]_srl32_n_1\ + ); +\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllreset_wait_reg[31]_srl32_n_1\, + Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\, + Q31 => \cpllreset_wait_reg[63]_srl32_n_1\ + ); +\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000" + ) + port map ( + A(4 downto 0) => B"11111", + CE => '1', + CLK => gt_cpllpdrefclk, + D => \cpllreset_wait_reg[63]_srl32_n_1\, + Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\, + Q31 => \cpllreset_wait_reg[95]_srl32_n_1\ + ); +\gtx_channel.gtxe2_channel_i_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => cpllrst, + I1 => rate_cpllreset_0, + I2 => RST_CPLLRESET, + O => CPLLRESET0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_pipe_lane is + port ( + pipe_rx1_valid : out STD_LOGIC; + pipe_rx1_chanisaligned : out STD_LOGIC; + pipe_rx1_phy_status : out STD_LOGIC; + pipe_rx1_elec_idle : out STD_LOGIC; + PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + PIPE_TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); + PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 1 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rx1_valid_gt : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 0 to 0 ); + \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ : in STD_LOGIC; + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ : in STD_LOGIC; + pipe_rx1_polarity : in STD_LOGIC; + pipe_tx1_compliance : in STD_LOGIC; + pipe_tx1_elec_idle : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_tx_data_q_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_pcie_pipe_lane; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_pipe_lane is +begin +\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXCHANISALIGNED(0), + Q => pipe_rx1_chanisaligned, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => D(0), + Q => Q(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => D(1), + Q => Q(1), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(0), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(10), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(10), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(11), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(11), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(12), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(12), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(13), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(13), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(14), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(14), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(1), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(1), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(2), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(2), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(3), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(3), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(4), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(4), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(5), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(5), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(6), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(6), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(7), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(7), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(8), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(8), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(9), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(9), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\, + Q => pipe_rx1_elec_idle, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_phy_status_q_reg_0\, + Q => pipe_rx1_phy_status, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_rx1_polarity, + Q => PIPE_RXPOLARITY(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(0), + Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(1), + Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(1), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2), + Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_rx1_valid_gt, + Q => pipe_rx1_valid, + R => SR(0) + ); +\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(0), + Q => PIPE_TXDATAK(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1), + Q => PIPE_TXDATAK(1), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_tx1_compliance, + Q => PIPE_TXCOMPLIANCE(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(0), + Q => PIPE_TXDATA(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(10), + Q => PIPE_TXDATA(10), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(11), + Q => PIPE_TXDATA(11), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(12), + Q => PIPE_TXDATA(12), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(13), + Q => PIPE_TXDATA(13), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(14), + Q => PIPE_TXDATA(14), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15), + Q => PIPE_TXDATA(15), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(1), + Q => PIPE_TXDATA(1), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(2), + Q => PIPE_TXDATA(2), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(3), + Q => PIPE_TXDATA(3), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(4), + Q => PIPE_TXDATA(4), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(5), + Q => PIPE_TXDATA(5), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(6), + Q => PIPE_TXDATA(6), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(7), + Q => PIPE_TXDATA(7), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(8), + Q => PIPE_TXDATA(8), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(9), + Q => PIPE_TXDATA(9), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_tx1_elec_idle, + Q => PIPE_TXELECIDLE(0), + S => SR(0) + ); +\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(0), + Q => PIPE_POWERDOWN(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1), + Q => PIPE_POWERDOWN(1), + S => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_pipe_lane_0 is + port ( + PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rx2_valid : out STD_LOGIC; + pipe_rx2_chanisaligned : out STD_LOGIC; + pipe_rx2_phy_status : out STD_LOGIC; + pipe_rx2_elec_idle : out STD_LOGIC; + PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + PIPE_TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); + PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rx2_polarity : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + pipe_tx2_compliance : in STD_LOGIC; + pipe_tx2_elec_idle : in STD_LOGIC; + pipe_rx2_valid_gt : in STD_LOGIC; + PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 0 to 0 ); + \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ : in STD_LOGIC; + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ : in STD_LOGIC; + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_tx_data_q_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_pipe_lane_0 : entity is "pcie_7x_0_pcie_pipe_lane"; +end pcie_7x_0_pcie_7x_0_pcie_pipe_lane_0; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_pipe_lane_0 is +begin +\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXCHANISALIGNED(0), + Q => pipe_rx2_chanisaligned, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(0), + Q => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1), + Q => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(0), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(10), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(10), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(11), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(11), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(12), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(12), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(13), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(13), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(14), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(14), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(1), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(1), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(2), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(2), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(3), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(3), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(4), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(4), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(5), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(5), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(6), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(6), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(7), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(7), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(8), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(8), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(9), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(9), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\, + Q => pipe_rx2_elec_idle, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_phy_status_q_reg_0\, + Q => pipe_rx2_phy_status, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_rx2_polarity, + Q => PIPE_RXPOLARITY(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(0), + Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(1), + Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(1), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2), + Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_rx2_valid_gt, + Q => pipe_rx2_valid, + R => SR(0) + ); +\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(0), + Q => PIPE_TXDATAK(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1), + Q => PIPE_TXDATAK(1), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_tx2_compliance, + Q => PIPE_TXCOMPLIANCE(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(0), + Q => PIPE_TXDATA(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(10), + Q => PIPE_TXDATA(10), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(11), + Q => PIPE_TXDATA(11), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(12), + Q => PIPE_TXDATA(12), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(13), + Q => PIPE_TXDATA(13), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(14), + Q => PIPE_TXDATA(14), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15), + Q => PIPE_TXDATA(15), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(1), + Q => PIPE_TXDATA(1), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(2), + Q => PIPE_TXDATA(2), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(3), + Q => PIPE_TXDATA(3), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(4), + Q => PIPE_TXDATA(4), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(5), + Q => PIPE_TXDATA(5), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(6), + Q => PIPE_TXDATA(6), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(7), + Q => PIPE_TXDATA(7), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(8), + Q => PIPE_TXDATA(8), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(9), + Q => PIPE_TXDATA(9), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_tx2_elec_idle, + Q => PIPE_TXELECIDLE(0), + S => SR(0) + ); +\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(0), + Q => PIPE_POWERDOWN(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1), + Q => PIPE_POWERDOWN(1), + S => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_pipe_lane_1 is + port ( + PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rx3_valid : out STD_LOGIC; + pipe_rx3_chanisaligned : out STD_LOGIC; + pipe_rx3_phy_status : out STD_LOGIC; + pipe_rx3_elec_idle : out STD_LOGIC; + PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + PIPE_TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); + PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rx3_polarity : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + pipe_tx3_compliance : in STD_LOGIC; + pipe_tx3_elec_idle : in STD_LOGIC; + pipe_rx3_valid_gt : in STD_LOGIC; + PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 0 to 0 ); + \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ : in STD_LOGIC; + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ : in STD_LOGIC; + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_tx_data_q_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_pipe_lane_1 : entity is "pcie_7x_0_pcie_pipe_lane"; +end pcie_7x_0_pcie_7x_0_pcie_pipe_lane_1; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_pipe_lane_1 is +begin +\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXCHANISALIGNED(0), + Q => pipe_rx3_chanisaligned, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(0), + Q => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1), + Q => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(0), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(10), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(10), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(11), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(11), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(12), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(12), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(13), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(13), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(14), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(14), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(1), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(1), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(2), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(2), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(3), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(3), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(4), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(4), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(5), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(5), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(6), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(6), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(7), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(7), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(8), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(8), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(9), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(9), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\, + Q => pipe_rx3_elec_idle, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_phy_status_q_reg_0\, + Q => pipe_rx3_phy_status, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_rx3_polarity, + Q => PIPE_RXPOLARITY(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(0), + Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(1), + Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(1), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2), + Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_rx3_valid_gt, + Q => pipe_rx3_valid, + R => SR(0) + ); +\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(0), + Q => PIPE_TXDATAK(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1), + Q => PIPE_TXDATAK(1), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_tx3_compliance, + Q => PIPE_TXCOMPLIANCE(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(0), + Q => PIPE_TXDATA(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(10), + Q => PIPE_TXDATA(10), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(11), + Q => PIPE_TXDATA(11), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(12), + Q => PIPE_TXDATA(12), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(13), + Q => PIPE_TXDATA(13), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(14), + Q => PIPE_TXDATA(14), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15), + Q => PIPE_TXDATA(15), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(1), + Q => PIPE_TXDATA(1), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(2), + Q => PIPE_TXDATA(2), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(3), + Q => PIPE_TXDATA(3), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(4), + Q => PIPE_TXDATA(4), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(5), + Q => PIPE_TXDATA(5), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(6), + Q => PIPE_TXDATA(6), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(7), + Q => PIPE_TXDATA(7), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(8), + Q => PIPE_TXDATA(8), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(9), + Q => PIPE_TXDATA(9), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_tx3_elec_idle, + Q => PIPE_TXELECIDLE(0), + S => SR(0) + ); +\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(0), + Q => PIPE_POWERDOWN(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1), + Q => PIPE_POWERDOWN(1), + S => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_pipe_lane_2 is + port ( + PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rx0_valid : out STD_LOGIC; + pipe_rx0_chanisaligned : out STD_LOGIC; + pipe_rx0_phy_status : out STD_LOGIC; + pipe_rx0_elec_idle : out STD_LOGIC; + PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + PIPE_TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); + PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rx0_polarity : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + pipe_tx0_compliance : in STD_LOGIC; + pipe_tx0_elec_idle : in STD_LOGIC; + pipe_rx0_valid_gt : in STD_LOGIC; + PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 0 to 0 ); + gt_rx_phy_status_q : in STD_LOGIC; + gt_rxelecidle_q : in STD_LOGIC; + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_tx_data_q_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_pipe_lane_2 : entity is "pcie_7x_0_pcie_pipe_lane"; +end pcie_7x_0_pcie_7x_0_pcie_pipe_lane_2; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_pipe_lane_2 is +begin +\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_RXCHANISALIGNED(0), + Q => pipe_rx0_chanisaligned, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(0), + Q => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1), + Q => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(0), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(10), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(10), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(11), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(11), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(12), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(12), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(13), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(13), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(14), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(14), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(1), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(1), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(2), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(2), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(3), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(3), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(4), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(4), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(5), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(5), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(6), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(6), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(7), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(7), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(8), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(8), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(9), + Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(9), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rxelecidle_q, + Q => pipe_rx0_elec_idle, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rx_phy_status_q, + Q => pipe_rx0_phy_status, + R => SR(0) + ); +\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_rx0_polarity, + Q => PIPE_RXPOLARITY(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(0), + Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(0), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(1), + Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(1), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2), + Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2), + R => SR(0) + ); +\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_rx0_valid_gt, + Q => pipe_rx0_valid, + R => SR(0) + ); +\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(0), + Q => PIPE_TXDATAK(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1), + Q => PIPE_TXDATAK(1), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_tx0_compliance, + Q => PIPE_TXCOMPLIANCE(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(0), + Q => PIPE_TXDATA(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(10), + Q => PIPE_TXDATA(10), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(11), + Q => PIPE_TXDATA(11), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(12), + Q => PIPE_TXDATA(12), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(13), + Q => PIPE_TXDATA(13), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(14), + Q => PIPE_TXDATA(14), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15), + Q => PIPE_TXDATA(15), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(1), + Q => PIPE_TXDATA(1), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(2), + Q => PIPE_TXDATA(2), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(3), + Q => PIPE_TXDATA(3), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(4), + Q => PIPE_TXDATA(4), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(5), + Q => PIPE_TXDATA(5), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(6), + Q => PIPE_TXDATA(6), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(7), + Q => PIPE_TXDATA(7), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(8), + Q => PIPE_TXDATA(8), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(9), + Q => PIPE_TXDATA(9), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_tx0_elec_idle, + Q => PIPE_TXELECIDLE(0), + S => SR(0) + ); +\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(0), + Q => PIPE_POWERDOWN(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1), + Q => PIPE_POWERDOWN(1), + S => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_pipe_misc is + port ( + pipe_tx_rcvr_det_gt : out STD_LOGIC; + \pipe_stages_1.pipe_tx_rate_q_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_tx_deemph_gt : out STD_LOGIC; + \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_tx_rcvr_det : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + pipe_tx_rate : in STD_LOGIC; + pipe_tx_deemph : in STD_LOGIC; + \pipe_stages_1.pipe_tx_margin_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_pcie_pipe_misc; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_pipe_misc is +begin +\pipe_stages_1.pipe_tx_deemph_q_reg\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_tx_deemph, + Q => pipe_tx_deemph_gt, + S => SR(0) + ); +\pipe_stages_1.pipe_tx_margin_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_margin_q_reg[2]_1\(0), + Q => \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_margin_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_margin_q_reg[2]_1\(1), + Q => \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\(1), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_margin_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pipe_stages_1.pipe_tx_margin_q_reg[2]_1\(2), + Q => \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\(2), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_rate_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_tx_rate, + Q => \pipe_stages_1.pipe_tx_rate_q_reg_0\(0), + R => SR(0) + ); +\pipe_stages_1.pipe_tx_rcvr_det_q_reg\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_tx_rcvr_det, + Q => pipe_tx_rcvr_det_gt, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_drp is + port ( + \fsm_reg[1]_0\ : out STD_LOGIC; + \fsm_reg[1]_1\ : out STD_LOGIC; + DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 ); + DRPADDR : out STD_LOGIC_VECTOR ( 7 downto 0 ); + DRP_DONE : out STD_LOGIC; + RST_DCLK_RESET : in STD_LOGIC; + RATE_DRP_X16X20_MODE : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + RATE_DRP_START : in STD_LOGIC; + DRP_RDY : in STD_LOGIC; + \rate_reg1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RATE_DRP_X16 : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 15 downto 0 ); + DRP_GTXRESET : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_pipe_drp; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_drp is + signal addr_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \addr_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \addr_reg[6]_i_1_n_0\ : STD_LOGIC; + signal data_pma_rsv_a : STD_LOGIC_VECTOR ( 15 to 15 ); + signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \di_reg[0]_i_2_n_0\ : STD_LOGIC; + signal \di_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_2_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_3_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_4_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_5_n_0\ : STD_LOGIC; + signal \di_reg[12]_i_2_n_0\ : STD_LOGIC; + signal \di_reg[12]_i_3_n_0\ : STD_LOGIC; + signal \di_reg[13]_i_2_n_0\ : STD_LOGIC; + signal \di_reg[13]_i_3_n_0\ : STD_LOGIC; + signal \di_reg[14]_i_2_n_0\ : STD_LOGIC; + signal \di_reg[15]_i_2_n_0\ : STD_LOGIC; + signal \di_reg[1]_i_2_n_0\ : STD_LOGIC; + signal \di_reg[1]_i_3_n_0\ : STD_LOGIC; + signal \di_reg[2]_i_2_n_0\ : STD_LOGIC; + signal \di_reg[2]_i_3_n_0\ : STD_LOGIC; + signal \di_reg[3]_i_2_n_0\ : STD_LOGIC; + signal \di_reg[3]_i_3_n_0\ : STD_LOGIC; + signal \di_reg[4]_i_2_n_0\ : STD_LOGIC; + signal \di_reg[4]_i_3_n_0\ : STD_LOGIC; + signal \di_reg[4]_i_4_n_0\ : STD_LOGIC; + signal \di_reg[5]_i_2_n_0\ : STD_LOGIC; + signal \di_reg[5]_i_3_n_0\ : STD_LOGIC; + signal \di_reg[6]_i_2_n_0\ : STD_LOGIC; + signal \di_reg[6]_i_3_n_0\ : STD_LOGIC; + signal \di_reg[7]_i_2_n_0\ : STD_LOGIC; + signal \di_reg[7]_i_3_n_0\ : STD_LOGIC; + signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of do_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of do_reg1 : signal is "true"; + signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute SHIFT_EXTRACT of do_reg2 : signal is "NO"; + attribute async_reg of do_reg2 : signal is "true"; + signal \done_i_1__0_n_0\ : STD_LOGIC; + signal drp_addr_0 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal drp_di_0 : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal fsm1 : STD_LOGIC; + signal \fsm[0]_i_2__0_n_0\ : STD_LOGIC; + signal \fsm_reg_n_0_[0]\ : STD_LOGIC; + signal \fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \fsm_reg_n_0_[2]\ : STD_LOGIC; + signal gtxreset_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of gtxreset_reg1 : signal is "NO"; + attribute async_reg of gtxreset_reg1 : signal is "true"; + signal gtxreset_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of gtxreset_reg2 : signal is "NO"; + attribute async_reg of gtxreset_reg2 : signal is "true"; + signal index : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \index[0]_i_1_n_0\ : STD_LOGIC; + signal \index[1]_i_1_n_0\ : STD_LOGIC; + signal \index[2]_i_1_n_0\ : STD_LOGIC; + signal \index[3]_i_1_n_0\ : STD_LOGIC; + signal \index[3]_i_2_n_0\ : STD_LOGIC; + signal \index[4]_i_1_n_0\ : STD_LOGIC; + signal \index[4]_i_2_n_0\ : STD_LOGIC; + signal \index[4]_i_3_n_0\ : STD_LOGIC; + signal load_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \load_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_reg1 : signal is "NO"; + attribute async_reg of rate_reg1 : signal is "true"; + signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_reg2 : signal is "NO"; + attribute async_reg of rate_reg2 : signal is "true"; + signal rdy_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rdy_reg1 : signal is "NO"; + attribute async_reg of rdy_reg1 : signal is "true"; + signal rdy_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rdy_reg2 : signal is "NO"; + attribute async_reg of rdy_reg2 : signal is "true"; + signal start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of start_reg1 : signal is "NO"; + attribute async_reg of start_reg1 : signal is "true"; + signal start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of start_reg2 : signal is "NO"; + attribute async_reg of start_reg2 : signal is "true"; + signal x16_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16_reg1 : signal is "NO"; + attribute async_reg of x16_reg1 : signal is "true"; + signal x16_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16_reg2 : signal is "NO"; + attribute async_reg of x16_reg2 : signal is "true"; + signal x16x20_mode_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16x20_mode_reg1 : signal is "NO"; + attribute async_reg of x16x20_mode_reg1 : signal is "true"; + signal x16x20_mode_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16x20_mode_reg2 : signal is "NO"; + attribute async_reg of x16x20_mode_reg2 : signal is "true"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \addr_reg[1]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \addr_reg[2]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \addr_reg[5]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \addr_reg[6]_i_1\ : label is "soft_lutpair29"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \do_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \do_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[10]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[11]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[12]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[13]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[14]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[15]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[6]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[7]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[8]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[9]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[10]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[11]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[12]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[13]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[14]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[15]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[6]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[7]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[8]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[9]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[9]\ : label is "NO"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_10\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_11\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_12\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_13\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_14\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_15\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_16\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_17\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_18\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_19\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_20\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_21\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_39__0\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_4\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_40\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_41\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_42\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_43\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_44\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_45\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_46\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_6\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_7\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_8\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_9\ : label is "soft_lutpair38"; + attribute ASYNC_REG_boolean of gtxreset_reg1_reg : label is std.standard.true; + attribute KEEP of gtxreset_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of gtxreset_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of gtxreset_reg2_reg : label is std.standard.true; + attribute KEEP of gtxreset_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of gtxreset_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \index[0]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \index[1]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \index[3]_i_2\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \index[4]_i_3\ : label is "soft_lutpair44"; + attribute ASYNC_REG_boolean of \rate_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of rdy_reg1_reg : label is std.standard.true; + attribute KEEP of rdy_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rdy_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rdy_reg2_reg : label is std.standard.true; + attribute KEEP of rdy_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rdy_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of start_reg1_reg : label is std.standard.true; + attribute KEEP of start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of start_reg2_reg : label is std.standard.true; + attribute KEEP of start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16_reg1_reg : label is std.standard.true; + attribute KEEP of x16_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16_reg2_reg : label is std.standard.true; + attribute KEEP of x16_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16x20_mode_reg1_reg : label is std.standard.true; + attribute KEEP of x16x20_mode_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16x20_mode_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16x20_mode_reg2_reg : label is std.standard.true; + attribute KEEP of x16x20_mode_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16x20_mode_reg2_reg : label is "NO"; +begin +\addr_reg[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1736415517364154" + ) + port map ( + I0 => index(4), + I1 => index(3), + I2 => index(2), + I3 => index(1), + I4 => index(0), + I5 => x16x20_mode_reg2, + O => addr_reg(0) + ); +\addr_reg[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40500F00" + ) + port map ( + I0 => index(4), + I1 => index(0), + I2 => index(3), + I3 => index(1), + I4 => index(2), + O => addr_reg(1) + ); +\addr_reg[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"05105A00" + ) + port map ( + I0 => index(4), + I1 => index(0), + I2 => index(3), + I3 => index(2), + I4 => index(1), + O => addr_reg(2) + ); +\addr_reg[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5767576753265327" + ) + port map ( + I0 => index(4), + I1 => index(3), + I2 => index(2), + I3 => index(1), + I4 => x16x20_mode_reg2, + I5 => index(0), + O => addr_reg(3) + ); +\addr_reg[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FAAFFF04" + ) + port map ( + I0 => index(0), + I1 => x16x20_mode_reg2, + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => index(4), + O => \addr_reg[4]_i_1_n_0\ + ); +\addr_reg[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"001A0F0A" + ) + port map ( + I0 => index(4), + I1 => index(0), + I2 => index(3), + I3 => index(1), + I4 => index(2), + O => addr_reg(5) + ); +\addr_reg[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001454" + ) + port map ( + I0 => index(2), + I1 => index(1), + I2 => index(3), + I3 => index(0), + I4 => index(4), + O => \addr_reg[6]_i_1_n_0\ + ); +\addr_reg[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5252424223236263" + ) + port map ( + I0 => index(4), + I1 => index(3), + I2 => index(2), + I3 => x16x20_mode_reg2, + I4 => index(0), + I5 => index(1), + O => addr_reg(7) + ); +\addr_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(0), + Q => drp_addr_0(0), + R => RST_DCLK_RESET + ); +\addr_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(1), + Q => drp_addr_0(1), + R => RST_DCLK_RESET + ); +\addr_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(2), + Q => drp_addr_0(2), + R => RST_DCLK_RESET + ); +\addr_reg_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(3), + Q => drp_addr_0(3), + R => RST_DCLK_RESET + ); +\addr_reg_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \addr_reg[4]_i_1_n_0\, + Q => drp_addr_0(4), + R => RST_DCLK_RESET + ); +\addr_reg_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(5), + Q => drp_addr_0(5), + R => RST_DCLK_RESET + ); +\addr_reg_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \addr_reg[6]_i_1_n_0\, + Q => drp_addr_0(6), + R => RST_DCLK_RESET + ); +\addr_reg_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(7), + Q => drp_addr_0(7), + R => RST_DCLK_RESET + ); +\di_reg[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF5E7F6FA1001000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => index(1), + I3 => data_pma_rsv_a(15), + I4 => index(0), + I5 => do_reg2(0), + O => \di_reg[0]_i_2_n_0\ + ); +\di_reg[0]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000005D0" + ) + port map ( + I0 => index(0), + I1 => do_reg2(0), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[0]_i_3_n_0\ + ); +\di_reg[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"45555F5540000000" + ) + port map ( + I0 => index(4), + I1 => \di_reg[15]_i_2_n_0\, + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(10), + O => di_reg(10) + ); +\di_reg[11]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4F40DDDD4F408888" + ) + port map ( + I0 => index(3), + I1 => do_reg2(11), + I2 => index(1), + I3 => \di_reg[11]_i_4_n_0\, + I4 => index(2), + I5 => \di_reg[11]_i_5_n_0\, + O => \di_reg[11]_i_2_n_0\ + ); +\di_reg[11]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000008080838" + ) + port map ( + I0 => do_reg2(11), + I1 => index(2), + I2 => index(1), + I3 => data_pma_rsv_a(15), + I4 => index(0), + I5 => index(3), + O => \di_reg[11]_i_3_n_0\ + ); +\di_reg[11]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B8BB" + ) + port map ( + I0 => do_reg2(11), + I1 => index(0), + I2 => rate_reg2(0), + I3 => rate_reg2(1), + O => \di_reg[11]_i_4_n_0\ + ); +\di_reg[11]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EFFF0100" + ) + port map ( + I0 => index(1), + I1 => index(0), + I2 => x16_reg2, + I3 => x16x20_mode_reg2, + I4 => do_reg2(11), + O => \di_reg[11]_i_5_n_0\ + ); +\di_reg[12]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"777EFFFF01080000" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => index(0), + I3 => data_pma_rsv_a(15), + I4 => index(2), + I5 => do_reg2(12), + O => \di_reg[12]_i_2_n_0\ + ); +\di_reg[12]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000B08" + ) + port map ( + I0 => do_reg2(12), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => index(3), + O => \di_reg[12]_i_3_n_0\ + ); +\di_reg[13]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"767FFFFF00090000" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => index(0), + I3 => data_pma_rsv_a(15), + I4 => index(2), + I5 => do_reg2(13), + O => \di_reg[13]_i_2_n_0\ + ); +\di_reg[13]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000008380808" + ) + port map ( + I0 => do_reg2(13), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => data_pma_rsv_a(15), + I5 => index(3), + O => \di_reg[13]_i_3_n_0\ + ); +\di_reg[14]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0040FFFF00400000" + ) + port map ( + I0 => index(1), + I1 => index(2), + I2 => do_reg2(14), + I3 => index(3), + I4 => index(4), + I5 => \di_reg[14]_i_2_n_0\, + O => di_reg(14) + ); +\di_reg[14]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"653BFFF721080080" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => data_pma_rsv_a(15), + I3 => index(0), + I4 => index(2), + I5 => do_reg2(14), + O => \di_reg[14]_i_2_n_0\ + ); +\di_reg[14]_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + O => data_pma_rsv_a(15) + ); +\di_reg[15]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"45555F5540000000" + ) + port map ( + I0 => index(4), + I1 => \di_reg[15]_i_2_n_0\, + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(15), + O => di_reg(15) + ); +\di_reg[15]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => rate_reg2(1), + I1 => rate_reg2(0), + I2 => index(0), + O => \di_reg[15]_i_2_n_0\ + ); +\di_reg[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5FEE4E0076FF1000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => data_pma_rsv_a(15), + I3 => index(1), + I4 => do_reg2(1), + I5 => index(0), + O => \di_reg[1]_i_2_n_0\ + ); +\di_reg[1]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000005D0" + ) + port map ( + I0 => index(0), + I1 => do_reg2(1), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[1]_i_3_n_0\ + ); +\di_reg[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5DEE080067FF0100" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => data_pma_rsv_a(15), + I3 => index(1), + I4 => do_reg2(2), + I5 => index(0), + O => \di_reg[2]_i_2_n_0\ + ); +\di_reg[2]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000380" + ) + port map ( + I0 => do_reg2(2), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[2]_i_3_n_0\ + ); +\di_reg[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"43FFFFFF40000000" + ) + port map ( + I0 => data_pma_rsv_a(15), + I1 => index(2), + I2 => index(0), + I3 => index(1), + I4 => index(3), + I5 => do_reg2(3), + O => \di_reg[3]_i_2_n_0\ + ); +\di_reg[3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000033D100" + ) + port map ( + I0 => data_pma_rsv_a(15), + I1 => index(0), + I2 => do_reg2(3), + I3 => index(2), + I4 => index(1), + I5 => index(3), + O => \di_reg[3]_i_3_n_0\ + ); +\di_reg[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \di_reg[4]_i_2_n_0\, + I1 => index(4), + I2 => \di_reg[4]_i_3_n_0\, + I3 => index(3), + I4 => \di_reg[4]_i_4_n_0\, + O => di_reg(4) + ); +\di_reg[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0400F0000400F0" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + I2 => index(1), + I3 => index(2), + I4 => index(0), + I5 => do_reg2(4), + O => \di_reg[4]_i_2_n_0\ + ); +\di_reg[4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"400FFFFF40000000" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + I2 => index(2), + I3 => index(0), + I4 => index(1), + I5 => do_reg2(4), + O => \di_reg[4]_i_3_n_0\ + ); +\di_reg[4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BF00BF01FF40FE40" + ) + port map ( + I0 => index(2), + I1 => index(1), + I2 => index(0), + I3 => do_reg2(4), + I4 => x16x20_mode_reg2, + I5 => data_pma_rsv_a(15), + O => \di_reg[4]_i_4_n_0\ + ); +\di_reg[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7F7F7F7E00000000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => x16x20_mode_reg2, + I5 => do_reg2(5), + O => \di_reg[5]_i_2_n_0\ + ); +\di_reg[5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000038F0380" + ) + port map ( + I0 => do_reg2(5), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => data_pma_rsv_a(15), + I5 => index(3), + O => \di_reg[5]_i_3_n_0\ + ); +\di_reg[6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7D7F7D7E00000000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => x16x20_mode_reg2, + I5 => do_reg2(6), + O => \di_reg[6]_i_2_n_0\ + ); +\di_reg[6]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000380" + ) + port map ( + I0 => do_reg2(6), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[6]_i_3_n_0\ + ); +\di_reg[7]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF0900" + ) + port map ( + I0 => index(2), + I1 => index(1), + I2 => index(0), + I3 => index(3), + I4 => do_reg2(7), + O => \di_reg[7]_i_2_n_0\ + ); +\di_reg[7]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000003800383" + ) + port map ( + I0 => do_reg2(7), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => data_pma_rsv_a(15), + I5 => index(3), + O => \di_reg[7]_i_3_n_0\ + ); +\di_reg[8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"03333F7300000040" + ) + port map ( + I0 => index(0), + I1 => index(4), + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(8), + O => di_reg(8) + ); +\di_reg[9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"03333F7300000040" + ) + port map ( + I0 => index(0), + I1 => index(4), + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(9), + O => di_reg(9) + ); +\di_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(0), + Q => drp_di_0(0), + R => RST_DCLK_RESET + ); +\di_reg_reg[0]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[0]_i_2_n_0\, + I1 => \di_reg[0]_i_3_n_0\, + O => di_reg(0), + S => index(4) + ); +\di_reg_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(10), + Q => drp_di_0(10), + R => RST_DCLK_RESET + ); +\di_reg_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(11), + Q => drp_di_0(11), + R => RST_DCLK_RESET + ); +\di_reg_reg[11]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[11]_i_2_n_0\, + I1 => \di_reg[11]_i_3_n_0\, + O => di_reg(11), + S => index(4) + ); +\di_reg_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(12), + Q => drp_di_0(12), + R => RST_DCLK_RESET + ); +\di_reg_reg[12]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[12]_i_2_n_0\, + I1 => \di_reg[12]_i_3_n_0\, + O => di_reg(12), + S => index(4) + ); +\di_reg_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(13), + Q => drp_di_0(13), + R => RST_DCLK_RESET + ); +\di_reg_reg[13]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[13]_i_2_n_0\, + I1 => \di_reg[13]_i_3_n_0\, + O => di_reg(13), + S => index(4) + ); +\di_reg_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(14), + Q => drp_di_0(14), + R => RST_DCLK_RESET + ); +\di_reg_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(15), + Q => drp_di_0(15), + R => RST_DCLK_RESET + ); +\di_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(1), + Q => drp_di_0(1), + R => RST_DCLK_RESET + ); +\di_reg_reg[1]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[1]_i_2_n_0\, + I1 => \di_reg[1]_i_3_n_0\, + O => di_reg(1), + S => index(4) + ); +\di_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(2), + Q => drp_di_0(2), + R => RST_DCLK_RESET + ); +\di_reg_reg[2]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[2]_i_2_n_0\, + I1 => \di_reg[2]_i_3_n_0\, + O => di_reg(2), + S => index(4) + ); +\di_reg_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(3), + Q => drp_di_0(3), + R => RST_DCLK_RESET + ); +\di_reg_reg[3]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[3]_i_2_n_0\, + I1 => \di_reg[3]_i_3_n_0\, + O => di_reg(3), + S => index(4) + ); +\di_reg_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(4), + Q => drp_di_0(4), + R => RST_DCLK_RESET + ); +\di_reg_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(5), + Q => drp_di_0(5), + R => RST_DCLK_RESET + ); +\di_reg_reg[5]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[5]_i_2_n_0\, + I1 => \di_reg[5]_i_3_n_0\, + O => di_reg(5), + S => index(4) + ); +\di_reg_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(6), + Q => drp_di_0(6), + R => RST_DCLK_RESET + ); +\di_reg_reg[6]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[6]_i_2_n_0\, + I1 => \di_reg[6]_i_3_n_0\, + O => di_reg(6), + S => index(4) + ); +\di_reg_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(7), + Q => drp_di_0(7), + R => RST_DCLK_RESET + ); +\di_reg_reg[7]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[7]_i_2_n_0\, + I1 => \di_reg[7]_i_3_n_0\, + O => di_reg(7), + S => index(4) + ); +\di_reg_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(8), + Q => drp_di_0(8), + R => RST_DCLK_RESET + ); +\di_reg_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(9), + Q => drp_di_0(9), + R => RST_DCLK_RESET + ); +\do_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(0), + Q => do_reg1(0), + R => RST_DCLK_RESET + ); +\do_reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(10), + Q => do_reg1(10), + R => RST_DCLK_RESET + ); +\do_reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(11), + Q => do_reg1(11), + R => RST_DCLK_RESET + ); +\do_reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(12), + Q => do_reg1(12), + R => RST_DCLK_RESET + ); +\do_reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(13), + Q => do_reg1(13), + R => RST_DCLK_RESET + ); +\do_reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(14), + Q => do_reg1(14), + R => RST_DCLK_RESET + ); +\do_reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(15), + Q => do_reg1(15), + R => RST_DCLK_RESET + ); +\do_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(1), + Q => do_reg1(1), + R => RST_DCLK_RESET + ); +\do_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(2), + Q => do_reg1(2), + R => RST_DCLK_RESET + ); +\do_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(3), + Q => do_reg1(3), + R => RST_DCLK_RESET + ); +\do_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(4), + Q => do_reg1(4), + R => RST_DCLK_RESET + ); +\do_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(5), + Q => do_reg1(5), + R => RST_DCLK_RESET + ); +\do_reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(6), + Q => do_reg1(6), + R => RST_DCLK_RESET + ); +\do_reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(7), + Q => do_reg1(7), + R => RST_DCLK_RESET + ); +\do_reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(8), + Q => do_reg1(8), + R => RST_DCLK_RESET + ); +\do_reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(9), + Q => do_reg1(9), + R => RST_DCLK_RESET + ); +\do_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(0), + Q => do_reg2(0), + R => RST_DCLK_RESET + ); +\do_reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(10), + Q => do_reg2(10), + R => RST_DCLK_RESET + ); +\do_reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(11), + Q => do_reg2(11), + R => RST_DCLK_RESET + ); +\do_reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(12), + Q => do_reg2(12), + R => RST_DCLK_RESET + ); +\do_reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(13), + Q => do_reg2(13), + R => RST_DCLK_RESET + ); +\do_reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(14), + Q => do_reg2(14), + R => RST_DCLK_RESET + ); +\do_reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(15), + Q => do_reg2(15), + R => RST_DCLK_RESET + ); +\do_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(1), + Q => do_reg2(1), + R => RST_DCLK_RESET + ); +\do_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(2), + Q => do_reg2(2), + R => RST_DCLK_RESET + ); +\do_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(3), + Q => do_reg2(3), + R => RST_DCLK_RESET + ); +\do_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(4), + Q => do_reg2(4), + R => RST_DCLK_RESET + ); +\do_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(5), + Q => do_reg2(5), + R => RST_DCLK_RESET + ); +\do_reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(6), + Q => do_reg2(6), + R => RST_DCLK_RESET + ); +\do_reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(7), + Q => do_reg2(7), + R => RST_DCLK_RESET + ); +\do_reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(8), + Q => do_reg2(8), + R => RST_DCLK_RESET + ); +\do_reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(9), + Q => do_reg2(9), + R => RST_DCLK_RESET + ); +\done_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => start_reg2, + I3 => \fsm_reg_n_0_[1]\, + O => \done_i_1__0_n_0\ + ); +done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \done_i_1__0_n_0\, + Q => DRP_DONE, + R => RST_DCLK_RESET + ); +\fsm[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0737FFFF07370000" + ) + port map ( + I0 => fsm1, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => rdy_reg2, + I4 => \fsm_reg_n_0_[2]\, + I5 => \fsm[0]_i_2__0_n_0\, + O => fsm(0) + ); +\fsm[0]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"47FF47CC" + ) + port map ( + I0 => rdy_reg2, + I1 => \fsm_reg_n_0_[1]\, + I2 => load_cnt(0), + I3 => \fsm_reg_n_0_[0]\, + I4 => start_reg2, + O => \fsm[0]_i_2__0_n_0\ + ); +\fsm[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"1D501850" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => rdy_reg2, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => load_cnt(0), + O => fsm(1) + ); +\fsm[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6222" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => rdy_reg2, + O => fsm(2) + ); +\fsm_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => fsm(0), + Q => \fsm_reg_n_0_[0]\, + R => RST_DCLK_RESET + ); +\fsm_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => fsm(1), + Q => \fsm_reg_n_0_[1]\, + R => RST_DCLK_RESET + ); +\fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => fsm(2), + Q => \fsm_reg_n_0_[2]\, + R => RST_DCLK_RESET + ); +\gtx_channel.gtxe2_channel_i_i_10\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(11), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(11) + ); +\gtx_channel.gtxe2_channel_i_i_11\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(10), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(10) + ); +\gtx_channel.gtxe2_channel_i_i_12\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(9), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(9) + ); +\gtx_channel.gtxe2_channel_i_i_13\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(8), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(8) + ); +\gtx_channel.gtxe2_channel_i_i_14\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(7), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(7) + ); +\gtx_channel.gtxe2_channel_i_i_15\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(6), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(6) + ); +\gtx_channel.gtxe2_channel_i_i_16\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(5), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(5) + ); +\gtx_channel.gtxe2_channel_i_i_17\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(4), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(4) + ); +\gtx_channel.gtxe2_channel_i_i_18\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(3), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(3) + ); +\gtx_channel.gtxe2_channel_i_i_19\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(2), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(2) + ); +\gtx_channel.gtxe2_channel_i_i_20\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(1), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(1) + ); +\gtx_channel.gtxe2_channel_i_i_21\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(0), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(0) + ); +\gtx_channel.gtxe2_channel_i_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"12" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \fsm_reg[1]_0\ + ); +\gtx_channel.gtxe2_channel_i_i_39__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_0(7), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(7) + ); +\gtx_channel.gtxe2_channel_i_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"10" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \fsm_reg[1]_1\ + ); +\gtx_channel.gtxe2_channel_i_i_40\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_0(6), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(6) + ); +\gtx_channel.gtxe2_channel_i_i_41\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_0(5), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(5) + ); +\gtx_channel.gtxe2_channel_i_i_42\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_0(4), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(4) + ); +\gtx_channel.gtxe2_channel_i_i_43\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_0(3), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(3) + ); +\gtx_channel.gtxe2_channel_i_i_44\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_0(2), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(2) + ); +\gtx_channel.gtxe2_channel_i_i_45\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_0(1), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(1) + ); +\gtx_channel.gtxe2_channel_i_i_46\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_0(0), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(0) + ); +\gtx_channel.gtxe2_channel_i_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(15), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(15) + ); +\gtx_channel.gtxe2_channel_i_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(14), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(14) + ); +\gtx_channel.gtxe2_channel_i_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(13), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(13) + ); +\gtx_channel.gtxe2_channel_i_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_0(12), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(12) + ); +gtxreset_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => DRP_GTXRESET, + Q => gtxreset_reg1, + R => RST_DCLK_RESET + ); +gtxreset_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => gtxreset_reg1, + Q => gtxreset_reg2, + R => RST_DCLK_RESET + ); +\index[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0100" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => fsm1, + I2 => index(0), + I3 => \fsm_reg_n_0_[2]\, + O => \index[0]_i_1_n_0\ + ); +\index[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00140000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(1), + I2 => index(0), + I3 => fsm1, + I4 => \fsm_reg_n_0_[2]\, + O => \index[1]_i_1_n_0\ + ); +\index[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000144400000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => fsm1, + I5 => \fsm_reg_n_0_[2]\, + O => \index[2]_i_1_n_0\ + ); +\index[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000144400000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(3), + I2 => index(2), + I3 => \index[3]_i_2_n_0\, + I4 => fsm1, + I5 => \fsm_reg_n_0_[2]\, + O => \index[3]_i_1_n_0\ + ); +\index[3]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => index(1), + I1 => index(0), + O => \index[3]_i_2_n_0\ + ); +\index[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A1" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \index[4]_i_1_n_0\ + ); +\index[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000144400000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(4), + I2 => index(3), + I3 => \index[4]_i_3_n_0\, + I4 => fsm1, + I5 => \fsm_reg_n_0_[2]\, + O => \index[4]_i_2_n_0\ + ); +\index[4]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => index(2), + I1 => index(0), + I2 => index(1), + O => \index[4]_i_3_n_0\ + ); +\index[4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000000110000000" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => index(0), + I3 => index(4), + I4 => index(2), + I5 => x16x20_mode_reg2, + O => fsm1 + ); +\index_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1_n_0\, + D => \index[0]_i_1_n_0\, + Q => index(0), + R => RST_DCLK_RESET + ); +\index_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1_n_0\, + D => \index[1]_i_1_n_0\, + Q => index(1), + R => RST_DCLK_RESET + ); +\index_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1_n_0\, + D => \index[2]_i_1_n_0\, + Q => index(2), + R => RST_DCLK_RESET + ); +\index_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1_n_0\, + D => \index[3]_i_1_n_0\, + Q => index(3), + R => RST_DCLK_RESET + ); +\index_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1_n_0\, + D => \index[4]_i_2_n_0\, + Q => index(4), + R => RST_DCLK_RESET + ); +\load_cnt[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"10" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + O => \load_cnt[0]_i_1_n_0\ + ); +\load_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \load_cnt[0]_i_1_n_0\, + Q => load_cnt(0), + R => RST_DCLK_RESET + ); +\rate_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => \rate_reg1_reg[0]_0\(0), + Q => rate_reg1(0), + R => RST_DCLK_RESET + ); +\rate_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => '0', + Q => rate_reg1(1), + R => RST_DCLK_RESET + ); +\rate_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => rate_reg1(0), + Q => rate_reg2(0), + R => RST_DCLK_RESET + ); +\rate_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => rate_reg1(1), + Q => rate_reg2(1), + R => RST_DCLK_RESET + ); +rdy_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => DRP_RDY, + Q => rdy_reg1, + R => RST_DCLK_RESET + ); +rdy_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => rdy_reg1, + Q => rdy_reg2, + R => RST_DCLK_RESET + ); +start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => RATE_DRP_START, + Q => start_reg1, + R => RST_DCLK_RESET + ); +start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => start_reg1, + Q => start_reg2, + R => RST_DCLK_RESET + ); +x16_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => RATE_DRP_X16, + Q => x16_reg1, + R => RST_DCLK_RESET + ); +x16_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => x16_reg1, + Q => x16_reg2, + R => RST_DCLK_RESET + ); +x16x20_mode_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => RATE_DRP_X16X20_MODE, + Q => x16x20_mode_reg1, + R => RST_DCLK_RESET + ); +x16x20_mode_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => x16x20_mode_reg1, + Q => x16x20_mode_reg2, + R => RST_DCLK_RESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_drp_38 is + port ( + \fsm_reg[1]_0\ : out STD_LOGIC; + \fsm_reg[1]_1\ : out STD_LOGIC; + DRPADDR : out STD_LOGIC_VECTOR ( 7 downto 0 ); + DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 ); + DRP_DONE : out STD_LOGIC; + RST_DCLK_RESET : in STD_LOGIC; + RATE_DRP_X16X20_MODE : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + RATE_DRP_START : in STD_LOGIC; + DRP_RDY : in STD_LOGIC; + \rate_reg1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RATE_DRP_X16 : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 15 downto 0 ); + DRP_GTXRESET : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_drp_38 : entity is "pcie_7x_0_pipe_drp"; +end pcie_7x_0_pcie_7x_0_pipe_drp_38; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_drp_38 is + signal addr_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \addr_reg[4]_i_1__0_n_0\ : STD_LOGIC; + signal \addr_reg[6]_i_1__0_n_0\ : STD_LOGIC; + signal data_pma_rsv_a : STD_LOGIC_VECTOR ( 15 to 15 ); + signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \di_reg[0]_i_2__0_n_0\ : STD_LOGIC; + signal \di_reg[0]_i_3__0_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_2__0_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_3__0_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_4__0_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_5__0_n_0\ : STD_LOGIC; + signal \di_reg[12]_i_2__0_n_0\ : STD_LOGIC; + signal \di_reg[12]_i_3__0_n_0\ : STD_LOGIC; + signal \di_reg[13]_i_2__0_n_0\ : STD_LOGIC; + signal \di_reg[13]_i_3__0_n_0\ : STD_LOGIC; + signal \di_reg[14]_i_2__0_n_0\ : STD_LOGIC; + signal \di_reg[15]_i_2__0_n_0\ : STD_LOGIC; + signal \di_reg[1]_i_2__0_n_0\ : STD_LOGIC; + signal \di_reg[1]_i_3__0_n_0\ : STD_LOGIC; + signal \di_reg[2]_i_2__0_n_0\ : STD_LOGIC; + signal \di_reg[2]_i_3__0_n_0\ : STD_LOGIC; + signal \di_reg[3]_i_2__0_n_0\ : STD_LOGIC; + signal \di_reg[3]_i_3__0_n_0\ : STD_LOGIC; + signal \di_reg[4]_i_2__0_n_0\ : STD_LOGIC; + signal \di_reg[4]_i_3__0_n_0\ : STD_LOGIC; + signal \di_reg[4]_i_4__0_n_0\ : STD_LOGIC; + signal \di_reg[5]_i_2__0_n_0\ : STD_LOGIC; + signal \di_reg[5]_i_3__0_n_0\ : STD_LOGIC; + signal \di_reg[6]_i_2__0_n_0\ : STD_LOGIC; + signal \di_reg[6]_i_3__0_n_0\ : STD_LOGIC; + signal \di_reg[7]_i_2__0_n_0\ : STD_LOGIC; + signal \di_reg[7]_i_3__0_n_0\ : STD_LOGIC; + signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of do_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of do_reg1 : signal is "true"; + signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute SHIFT_EXTRACT of do_reg2 : signal is "NO"; + attribute async_reg of do_reg2 : signal is "true"; + signal \done_i_1__1_n_0\ : STD_LOGIC; + signal drp_addr_9 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal drp_di_16 : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal fsm1 : STD_LOGIC; + signal \fsm[0]_i_2__3_n_0\ : STD_LOGIC; + signal \fsm_reg_n_0_[0]\ : STD_LOGIC; + signal \fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \fsm_reg_n_0_[2]\ : STD_LOGIC; + signal gtxreset_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of gtxreset_reg1 : signal is "NO"; + attribute async_reg of gtxreset_reg1 : signal is "true"; + signal gtxreset_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of gtxreset_reg2 : signal is "NO"; + attribute async_reg of gtxreset_reg2 : signal is "true"; + signal index : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \index[0]_i_1__0_n_0\ : STD_LOGIC; + signal \index[1]_i_1__0_n_0\ : STD_LOGIC; + signal \index[2]_i_1__0_n_0\ : STD_LOGIC; + signal \index[3]_i_1__0_n_0\ : STD_LOGIC; + signal \index[3]_i_2__0_n_0\ : STD_LOGIC; + signal \index[4]_i_1__0_n_0\ : STD_LOGIC; + signal \index[4]_i_2__0_n_0\ : STD_LOGIC; + signal \index[4]_i_3__0_n_0\ : STD_LOGIC; + signal load_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \load_cnt[0]_i_1__1_n_0\ : STD_LOGIC; + signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_reg1 : signal is "NO"; + attribute async_reg of rate_reg1 : signal is "true"; + signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_reg2 : signal is "NO"; + attribute async_reg of rate_reg2 : signal is "true"; + signal rdy_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rdy_reg1 : signal is "NO"; + attribute async_reg of rdy_reg1 : signal is "true"; + signal rdy_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rdy_reg2 : signal is "NO"; + attribute async_reg of rdy_reg2 : signal is "true"; + signal start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of start_reg1 : signal is "NO"; + attribute async_reg of start_reg1 : signal is "true"; + signal start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of start_reg2 : signal is "NO"; + attribute async_reg of start_reg2 : signal is "true"; + signal x16_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16_reg1 : signal is "NO"; + attribute async_reg of x16_reg1 : signal is "true"; + signal x16_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16_reg2 : signal is "NO"; + attribute async_reg of x16_reg2 : signal is "true"; + signal x16x20_mode_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16x20_mode_reg1 : signal is "NO"; + attribute async_reg of x16x20_mode_reg1 : signal is "true"; + signal x16x20_mode_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16x20_mode_reg2 : signal is "NO"; + attribute async_reg of x16x20_mode_reg2 : signal is "true"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \addr_reg[1]_i_1__0\ : label is "soft_lutpair82"; + attribute SOFT_HLUTNM of \addr_reg[2]_i_1__0\ : label is "soft_lutpair82"; + attribute SOFT_HLUTNM of \addr_reg[5]_i_1__0\ : label is "soft_lutpair81"; + attribute SOFT_HLUTNM of \addr_reg[6]_i_1__0\ : label is "soft_lutpair81"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \do_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \do_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[10]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[11]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[12]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[13]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[14]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[15]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[6]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[7]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[8]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[9]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[10]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[11]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[12]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[13]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[14]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[15]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[6]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[7]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[8]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[9]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[9]\ : label is "NO"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_10__0\ : label is "soft_lutpair93"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_11__0\ : label is "soft_lutpair93"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_12__0\ : label is "soft_lutpair92"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_13__0\ : label is "soft_lutpair92"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_14__0\ : label is "soft_lutpair91"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_15__0\ : label is "soft_lutpair91"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_16__0\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_17__0\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_18__0\ : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_19__0\ : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_20__0\ : label is "soft_lutpair88"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_21__0\ : label is "soft_lutpair88"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_39__1\ : label is "soft_lutpair87"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3__0\ : label is "soft_lutpair83"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_40__0\ : label is "soft_lutpair87"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_41__0\ : label is "soft_lutpair86"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_42__0\ : label is "soft_lutpair86"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_43__0\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_44__0\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_45__0\ : label is "soft_lutpair84"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_46__0\ : label is "soft_lutpair83"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_4__0\ : label is "soft_lutpair84"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_6__0\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_7__0\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_8__0\ : label is "soft_lutpair94"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_9__0\ : label is "soft_lutpair94"; + attribute ASYNC_REG_boolean of gtxreset_reg1_reg : label is std.standard.true; + attribute KEEP of gtxreset_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of gtxreset_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of gtxreset_reg2_reg : label is std.standard.true; + attribute KEEP of gtxreset_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of gtxreset_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \index[0]_i_1__0\ : label is "soft_lutpair80"; + attribute SOFT_HLUTNM of \index[1]_i_1__0\ : label is "soft_lutpair80"; + attribute SOFT_HLUTNM of \index[3]_i_2__0\ : label is "soft_lutpair96"; + attribute SOFT_HLUTNM of \index[4]_i_3__0\ : label is "soft_lutpair96"; + attribute ASYNC_REG_boolean of \rate_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of rdy_reg1_reg : label is std.standard.true; + attribute KEEP of rdy_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rdy_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rdy_reg2_reg : label is std.standard.true; + attribute KEEP of rdy_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rdy_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of start_reg1_reg : label is std.standard.true; + attribute KEEP of start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of start_reg2_reg : label is std.standard.true; + attribute KEEP of start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16_reg1_reg : label is std.standard.true; + attribute KEEP of x16_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16_reg2_reg : label is std.standard.true; + attribute KEEP of x16_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16x20_mode_reg1_reg : label is std.standard.true; + attribute KEEP of x16x20_mode_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16x20_mode_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16x20_mode_reg2_reg : label is std.standard.true; + attribute KEEP of x16x20_mode_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16x20_mode_reg2_reg : label is "NO"; +begin +\addr_reg[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1736415517364154" + ) + port map ( + I0 => index(4), + I1 => index(3), + I2 => index(2), + I3 => index(1), + I4 => index(0), + I5 => x16x20_mode_reg2, + O => addr_reg(0) + ); +\addr_reg[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40500F00" + ) + port map ( + I0 => index(4), + I1 => index(0), + I2 => index(3), + I3 => index(1), + I4 => index(2), + O => addr_reg(1) + ); +\addr_reg[2]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"05105A00" + ) + port map ( + I0 => index(4), + I1 => index(0), + I2 => index(3), + I3 => index(2), + I4 => index(1), + O => addr_reg(2) + ); +\addr_reg[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5767576753265327" + ) + port map ( + I0 => index(4), + I1 => index(3), + I2 => index(2), + I3 => index(1), + I4 => x16x20_mode_reg2, + I5 => index(0), + O => addr_reg(3) + ); +\addr_reg[4]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FAAFFF04" + ) + port map ( + I0 => index(0), + I1 => x16x20_mode_reg2, + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => index(4), + O => \addr_reg[4]_i_1__0_n_0\ + ); +\addr_reg[5]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"001A0F0A" + ) + port map ( + I0 => index(4), + I1 => index(0), + I2 => index(3), + I3 => index(1), + I4 => index(2), + O => addr_reg(5) + ); +\addr_reg[6]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001454" + ) + port map ( + I0 => index(2), + I1 => index(1), + I2 => index(3), + I3 => index(0), + I4 => index(4), + O => \addr_reg[6]_i_1__0_n_0\ + ); +\addr_reg[7]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5252424223236263" + ) + port map ( + I0 => index(4), + I1 => index(3), + I2 => index(2), + I3 => x16x20_mode_reg2, + I4 => index(0), + I5 => index(1), + O => addr_reg(7) + ); +\addr_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(0), + Q => drp_addr_9(0), + R => RST_DCLK_RESET + ); +\addr_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(1), + Q => drp_addr_9(1), + R => RST_DCLK_RESET + ); +\addr_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(2), + Q => drp_addr_9(2), + R => RST_DCLK_RESET + ); +\addr_reg_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(3), + Q => drp_addr_9(3), + R => RST_DCLK_RESET + ); +\addr_reg_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \addr_reg[4]_i_1__0_n_0\, + Q => drp_addr_9(4), + R => RST_DCLK_RESET + ); +\addr_reg_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(5), + Q => drp_addr_9(5), + R => RST_DCLK_RESET + ); +\addr_reg_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \addr_reg[6]_i_1__0_n_0\, + Q => drp_addr_9(6), + R => RST_DCLK_RESET + ); +\addr_reg_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(7), + Q => drp_addr_9(7), + R => RST_DCLK_RESET + ); +\di_reg[0]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF5E7F6FA1001000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => index(1), + I3 => data_pma_rsv_a(15), + I4 => index(0), + I5 => do_reg2(0), + O => \di_reg[0]_i_2__0_n_0\ + ); +\di_reg[0]_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000005D0" + ) + port map ( + I0 => index(0), + I1 => do_reg2(0), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[0]_i_3__0_n_0\ + ); +\di_reg[10]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"45555F5540000000" + ) + port map ( + I0 => index(4), + I1 => \di_reg[15]_i_2__0_n_0\, + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(10), + O => di_reg(10) + ); +\di_reg[11]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4F40DDDD4F408888" + ) + port map ( + I0 => index(3), + I1 => do_reg2(11), + I2 => index(1), + I3 => \di_reg[11]_i_4__0_n_0\, + I4 => index(2), + I5 => \di_reg[11]_i_5__0_n_0\, + O => \di_reg[11]_i_2__0_n_0\ + ); +\di_reg[11]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000008080838" + ) + port map ( + I0 => do_reg2(11), + I1 => index(2), + I2 => index(1), + I3 => data_pma_rsv_a(15), + I4 => index(0), + I5 => index(3), + O => \di_reg[11]_i_3__0_n_0\ + ); +\di_reg[11]_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B8BB" + ) + port map ( + I0 => do_reg2(11), + I1 => index(0), + I2 => rate_reg2(0), + I3 => rate_reg2(1), + O => \di_reg[11]_i_4__0_n_0\ + ); +\di_reg[11]_i_5__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EFFF0100" + ) + port map ( + I0 => index(1), + I1 => index(0), + I2 => x16_reg2, + I3 => x16x20_mode_reg2, + I4 => do_reg2(11), + O => \di_reg[11]_i_5__0_n_0\ + ); +\di_reg[12]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"777EFFFF01080000" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => index(0), + I3 => data_pma_rsv_a(15), + I4 => index(2), + I5 => do_reg2(12), + O => \di_reg[12]_i_2__0_n_0\ + ); +\di_reg[12]_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000B08" + ) + port map ( + I0 => do_reg2(12), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => index(3), + O => \di_reg[12]_i_3__0_n_0\ + ); +\di_reg[13]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"767FFFFF00090000" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => index(0), + I3 => data_pma_rsv_a(15), + I4 => index(2), + I5 => do_reg2(13), + O => \di_reg[13]_i_2__0_n_0\ + ); +\di_reg[13]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000008380808" + ) + port map ( + I0 => do_reg2(13), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => data_pma_rsv_a(15), + I5 => index(3), + O => \di_reg[13]_i_3__0_n_0\ + ); +\di_reg[14]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0040FFFF00400000" + ) + port map ( + I0 => index(1), + I1 => index(2), + I2 => do_reg2(14), + I3 => index(3), + I4 => index(4), + I5 => \di_reg[14]_i_2__0_n_0\, + O => di_reg(14) + ); +\di_reg[14]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"653BFFF721080080" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => data_pma_rsv_a(15), + I3 => index(0), + I4 => index(2), + I5 => do_reg2(14), + O => \di_reg[14]_i_2__0_n_0\ + ); +\di_reg[14]_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + O => data_pma_rsv_a(15) + ); +\di_reg[15]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"45555F5540000000" + ) + port map ( + I0 => index(4), + I1 => \di_reg[15]_i_2__0_n_0\, + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(15), + O => di_reg(15) + ); +\di_reg[15]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => rate_reg2(1), + I1 => rate_reg2(0), + I2 => index(0), + O => \di_reg[15]_i_2__0_n_0\ + ); +\di_reg[1]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5FEE4E0076FF1000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => data_pma_rsv_a(15), + I3 => index(1), + I4 => do_reg2(1), + I5 => index(0), + O => \di_reg[1]_i_2__0_n_0\ + ); +\di_reg[1]_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000005D0" + ) + port map ( + I0 => index(0), + I1 => do_reg2(1), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[1]_i_3__0_n_0\ + ); +\di_reg[2]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5DEE080067FF0100" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => data_pma_rsv_a(15), + I3 => index(1), + I4 => do_reg2(2), + I5 => index(0), + O => \di_reg[2]_i_2__0_n_0\ + ); +\di_reg[2]_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000380" + ) + port map ( + I0 => do_reg2(2), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[2]_i_3__0_n_0\ + ); +\di_reg[3]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"43FFFFFF40000000" + ) + port map ( + I0 => data_pma_rsv_a(15), + I1 => index(2), + I2 => index(0), + I3 => index(1), + I4 => index(3), + I5 => do_reg2(3), + O => \di_reg[3]_i_2__0_n_0\ + ); +\di_reg[3]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000033D100" + ) + port map ( + I0 => data_pma_rsv_a(15), + I1 => index(0), + I2 => do_reg2(3), + I3 => index(2), + I4 => index(1), + I5 => index(3), + O => \di_reg[3]_i_3__0_n_0\ + ); +\di_reg[4]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \di_reg[4]_i_2__0_n_0\, + I1 => index(4), + I2 => \di_reg[4]_i_3__0_n_0\, + I3 => index(3), + I4 => \di_reg[4]_i_4__0_n_0\, + O => di_reg(4) + ); +\di_reg[4]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0400F0000400F0" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + I2 => index(1), + I3 => index(2), + I4 => index(0), + I5 => do_reg2(4), + O => \di_reg[4]_i_2__0_n_0\ + ); +\di_reg[4]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"400FFFFF40000000" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + I2 => index(2), + I3 => index(0), + I4 => index(1), + I5 => do_reg2(4), + O => \di_reg[4]_i_3__0_n_0\ + ); +\di_reg[4]_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BF00BF01FF40FE40" + ) + port map ( + I0 => index(2), + I1 => index(1), + I2 => index(0), + I3 => do_reg2(4), + I4 => x16x20_mode_reg2, + I5 => data_pma_rsv_a(15), + O => \di_reg[4]_i_4__0_n_0\ + ); +\di_reg[5]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7F7F7F7E00000000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => x16x20_mode_reg2, + I5 => do_reg2(5), + O => \di_reg[5]_i_2__0_n_0\ + ); +\di_reg[5]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000038F0380" + ) + port map ( + I0 => do_reg2(5), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => data_pma_rsv_a(15), + I5 => index(3), + O => \di_reg[5]_i_3__0_n_0\ + ); +\di_reg[6]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7D7F7D7E00000000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => x16x20_mode_reg2, + I5 => do_reg2(6), + O => \di_reg[6]_i_2__0_n_0\ + ); +\di_reg[6]_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000380" + ) + port map ( + I0 => do_reg2(6), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[6]_i_3__0_n_0\ + ); +\di_reg[7]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF0900" + ) + port map ( + I0 => index(2), + I1 => index(1), + I2 => index(0), + I3 => index(3), + I4 => do_reg2(7), + O => \di_reg[7]_i_2__0_n_0\ + ); +\di_reg[7]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000003800383" + ) + port map ( + I0 => do_reg2(7), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => data_pma_rsv_a(15), + I5 => index(3), + O => \di_reg[7]_i_3__0_n_0\ + ); +\di_reg[8]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"03333F7300000040" + ) + port map ( + I0 => index(0), + I1 => index(4), + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(8), + O => di_reg(8) + ); +\di_reg[9]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"03333F7300000040" + ) + port map ( + I0 => index(0), + I1 => index(4), + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(9), + O => di_reg(9) + ); +\di_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(0), + Q => drp_di_16(0), + R => RST_DCLK_RESET + ); +\di_reg_reg[0]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[0]_i_2__0_n_0\, + I1 => \di_reg[0]_i_3__0_n_0\, + O => di_reg(0), + S => index(4) + ); +\di_reg_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(10), + Q => drp_di_16(10), + R => RST_DCLK_RESET + ); +\di_reg_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(11), + Q => drp_di_16(11), + R => RST_DCLK_RESET + ); +\di_reg_reg[11]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[11]_i_2__0_n_0\, + I1 => \di_reg[11]_i_3__0_n_0\, + O => di_reg(11), + S => index(4) + ); +\di_reg_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(12), + Q => drp_di_16(12), + R => RST_DCLK_RESET + ); +\di_reg_reg[12]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[12]_i_2__0_n_0\, + I1 => \di_reg[12]_i_3__0_n_0\, + O => di_reg(12), + S => index(4) + ); +\di_reg_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(13), + Q => drp_di_16(13), + R => RST_DCLK_RESET + ); +\di_reg_reg[13]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[13]_i_2__0_n_0\, + I1 => \di_reg[13]_i_3__0_n_0\, + O => di_reg(13), + S => index(4) + ); +\di_reg_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(14), + Q => drp_di_16(14), + R => RST_DCLK_RESET + ); +\di_reg_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(15), + Q => drp_di_16(15), + R => RST_DCLK_RESET + ); +\di_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(1), + Q => drp_di_16(1), + R => RST_DCLK_RESET + ); +\di_reg_reg[1]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[1]_i_2__0_n_0\, + I1 => \di_reg[1]_i_3__0_n_0\, + O => di_reg(1), + S => index(4) + ); +\di_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(2), + Q => drp_di_16(2), + R => RST_DCLK_RESET + ); +\di_reg_reg[2]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[2]_i_2__0_n_0\, + I1 => \di_reg[2]_i_3__0_n_0\, + O => di_reg(2), + S => index(4) + ); +\di_reg_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(3), + Q => drp_di_16(3), + R => RST_DCLK_RESET + ); +\di_reg_reg[3]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[3]_i_2__0_n_0\, + I1 => \di_reg[3]_i_3__0_n_0\, + O => di_reg(3), + S => index(4) + ); +\di_reg_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(4), + Q => drp_di_16(4), + R => RST_DCLK_RESET + ); +\di_reg_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(5), + Q => drp_di_16(5), + R => RST_DCLK_RESET + ); +\di_reg_reg[5]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[5]_i_2__0_n_0\, + I1 => \di_reg[5]_i_3__0_n_0\, + O => di_reg(5), + S => index(4) + ); +\di_reg_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(6), + Q => drp_di_16(6), + R => RST_DCLK_RESET + ); +\di_reg_reg[6]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[6]_i_2__0_n_0\, + I1 => \di_reg[6]_i_3__0_n_0\, + O => di_reg(6), + S => index(4) + ); +\di_reg_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(7), + Q => drp_di_16(7), + R => RST_DCLK_RESET + ); +\di_reg_reg[7]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[7]_i_2__0_n_0\, + I1 => \di_reg[7]_i_3__0_n_0\, + O => di_reg(7), + S => index(4) + ); +\di_reg_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(8), + Q => drp_di_16(8), + R => RST_DCLK_RESET + ); +\di_reg_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(9), + Q => drp_di_16(9), + R => RST_DCLK_RESET + ); +\do_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(0), + Q => do_reg1(0), + R => RST_DCLK_RESET + ); +\do_reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(10), + Q => do_reg1(10), + R => RST_DCLK_RESET + ); +\do_reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(11), + Q => do_reg1(11), + R => RST_DCLK_RESET + ); +\do_reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(12), + Q => do_reg1(12), + R => RST_DCLK_RESET + ); +\do_reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(13), + Q => do_reg1(13), + R => RST_DCLK_RESET + ); +\do_reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(14), + Q => do_reg1(14), + R => RST_DCLK_RESET + ); +\do_reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(15), + Q => do_reg1(15), + R => RST_DCLK_RESET + ); +\do_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(1), + Q => do_reg1(1), + R => RST_DCLK_RESET + ); +\do_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(2), + Q => do_reg1(2), + R => RST_DCLK_RESET + ); +\do_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(3), + Q => do_reg1(3), + R => RST_DCLK_RESET + ); +\do_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(4), + Q => do_reg1(4), + R => RST_DCLK_RESET + ); +\do_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(5), + Q => do_reg1(5), + R => RST_DCLK_RESET + ); +\do_reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(6), + Q => do_reg1(6), + R => RST_DCLK_RESET + ); +\do_reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(7), + Q => do_reg1(7), + R => RST_DCLK_RESET + ); +\do_reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(8), + Q => do_reg1(8), + R => RST_DCLK_RESET + ); +\do_reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(9), + Q => do_reg1(9), + R => RST_DCLK_RESET + ); +\do_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(0), + Q => do_reg2(0), + R => RST_DCLK_RESET + ); +\do_reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(10), + Q => do_reg2(10), + R => RST_DCLK_RESET + ); +\do_reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(11), + Q => do_reg2(11), + R => RST_DCLK_RESET + ); +\do_reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(12), + Q => do_reg2(12), + R => RST_DCLK_RESET + ); +\do_reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(13), + Q => do_reg2(13), + R => RST_DCLK_RESET + ); +\do_reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(14), + Q => do_reg2(14), + R => RST_DCLK_RESET + ); +\do_reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(15), + Q => do_reg2(15), + R => RST_DCLK_RESET + ); +\do_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(1), + Q => do_reg2(1), + R => RST_DCLK_RESET + ); +\do_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(2), + Q => do_reg2(2), + R => RST_DCLK_RESET + ); +\do_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(3), + Q => do_reg2(3), + R => RST_DCLK_RESET + ); +\do_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(4), + Q => do_reg2(4), + R => RST_DCLK_RESET + ); +\do_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(5), + Q => do_reg2(5), + R => RST_DCLK_RESET + ); +\do_reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(6), + Q => do_reg2(6), + R => RST_DCLK_RESET + ); +\do_reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(7), + Q => do_reg2(7), + R => RST_DCLK_RESET + ); +\do_reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(8), + Q => do_reg2(8), + R => RST_DCLK_RESET + ); +\do_reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(9), + Q => do_reg2(9), + R => RST_DCLK_RESET + ); +\done_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => start_reg2, + I3 => \fsm_reg_n_0_[1]\, + O => \done_i_1__1_n_0\ + ); +done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \done_i_1__1_n_0\, + Q => DRP_DONE, + R => RST_DCLK_RESET + ); +\fsm[0]_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0737FFFF07370000" + ) + port map ( + I0 => fsm1, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => rdy_reg2, + I4 => \fsm_reg_n_0_[2]\, + I5 => \fsm[0]_i_2__3_n_0\, + O => fsm(0) + ); +\fsm[0]_i_2__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"47FF47CC" + ) + port map ( + I0 => rdy_reg2, + I1 => \fsm_reg_n_0_[1]\, + I2 => load_cnt(0), + I3 => \fsm_reg_n_0_[0]\, + I4 => start_reg2, + O => \fsm[0]_i_2__3_n_0\ + ); +\fsm[1]_i_1__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"1D501850" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => rdy_reg2, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => load_cnt(0), + O => fsm(1) + ); +\fsm[2]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6222" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => rdy_reg2, + O => fsm(2) + ); +\fsm_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => fsm(0), + Q => \fsm_reg_n_0_[0]\, + R => RST_DCLK_RESET + ); +\fsm_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => fsm(1), + Q => \fsm_reg_n_0_[1]\, + R => RST_DCLK_RESET + ); +\fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => fsm(2), + Q => \fsm_reg_n_0_[2]\, + R => RST_DCLK_RESET + ); +\gtx_channel.gtxe2_channel_i_i_10__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(11), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(11) + ); +\gtx_channel.gtxe2_channel_i_i_11__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(10), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(10) + ); +\gtx_channel.gtxe2_channel_i_i_12__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(9), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(9) + ); +\gtx_channel.gtxe2_channel_i_i_13__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(8), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(8) + ); +\gtx_channel.gtxe2_channel_i_i_14__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(7), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(7) + ); +\gtx_channel.gtxe2_channel_i_i_15__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(6), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(6) + ); +\gtx_channel.gtxe2_channel_i_i_16__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(5), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(5) + ); +\gtx_channel.gtxe2_channel_i_i_17__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(4), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(4) + ); +\gtx_channel.gtxe2_channel_i_i_18__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(3), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(3) + ); +\gtx_channel.gtxe2_channel_i_i_19__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(2), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(2) + ); +\gtx_channel.gtxe2_channel_i_i_20__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(1), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(1) + ); +\gtx_channel.gtxe2_channel_i_i_21__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(0), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(0) + ); +\gtx_channel.gtxe2_channel_i_i_39__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_9(7), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(7) + ); +\gtx_channel.gtxe2_channel_i_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"12" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \fsm_reg[1]_0\ + ); +\gtx_channel.gtxe2_channel_i_i_40__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_9(6), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(6) + ); +\gtx_channel.gtxe2_channel_i_i_41__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_9(5), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(5) + ); +\gtx_channel.gtxe2_channel_i_i_42__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_9(4), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(4) + ); +\gtx_channel.gtxe2_channel_i_i_43__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_9(3), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(3) + ); +\gtx_channel.gtxe2_channel_i_i_44__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_9(2), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(2) + ); +\gtx_channel.gtxe2_channel_i_i_45__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_9(1), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(1) + ); +\gtx_channel.gtxe2_channel_i_i_46__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_9(0), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(0) + ); +\gtx_channel.gtxe2_channel_i_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"10" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \fsm_reg[1]_1\ + ); +\gtx_channel.gtxe2_channel_i_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(15), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(15) + ); +\gtx_channel.gtxe2_channel_i_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(14), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(14) + ); +\gtx_channel.gtxe2_channel_i_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(13), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(13) + ); +\gtx_channel.gtxe2_channel_i_i_9__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_16(12), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(12) + ); +gtxreset_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => DRP_GTXRESET, + Q => gtxreset_reg1, + R => RST_DCLK_RESET + ); +gtxreset_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => gtxreset_reg1, + Q => gtxreset_reg2, + R => RST_DCLK_RESET + ); +\index[0]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0100" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => fsm1, + I2 => index(0), + I3 => \fsm_reg_n_0_[2]\, + O => \index[0]_i_1__0_n_0\ + ); +\index[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00140000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(1), + I2 => index(0), + I3 => fsm1, + I4 => \fsm_reg_n_0_[2]\, + O => \index[1]_i_1__0_n_0\ + ); +\index[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000144400000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => fsm1, + I5 => \fsm_reg_n_0_[2]\, + O => \index[2]_i_1__0_n_0\ + ); +\index[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000144400000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(3), + I2 => index(2), + I3 => \index[3]_i_2__0_n_0\, + I4 => fsm1, + I5 => \fsm_reg_n_0_[2]\, + O => \index[3]_i_1__0_n_0\ + ); +\index[3]_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => index(1), + I1 => index(0), + O => \index[3]_i_2__0_n_0\ + ); +\index[4]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A1" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \index[4]_i_1__0_n_0\ + ); +\index[4]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000144400000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(4), + I2 => index(3), + I3 => \index[4]_i_3__0_n_0\, + I4 => fsm1, + I5 => \fsm_reg_n_0_[2]\, + O => \index[4]_i_2__0_n_0\ + ); +\index[4]_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => index(2), + I1 => index(0), + I2 => index(1), + O => \index[4]_i_3__0_n_0\ + ); +\index[4]_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000000110000000" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => index(0), + I3 => index(4), + I4 => index(2), + I5 => x16x20_mode_reg2, + O => fsm1 + ); +\index_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__0_n_0\, + D => \index[0]_i_1__0_n_0\, + Q => index(0), + R => RST_DCLK_RESET + ); +\index_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__0_n_0\, + D => \index[1]_i_1__0_n_0\, + Q => index(1), + R => RST_DCLK_RESET + ); +\index_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__0_n_0\, + D => \index[2]_i_1__0_n_0\, + Q => index(2), + R => RST_DCLK_RESET + ); +\index_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__0_n_0\, + D => \index[3]_i_1__0_n_0\, + Q => index(3), + R => RST_DCLK_RESET + ); +\index_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__0_n_0\, + D => \index[4]_i_2__0_n_0\, + Q => index(4), + R => RST_DCLK_RESET + ); +\load_cnt[0]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"10" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + O => \load_cnt[0]_i_1__1_n_0\ + ); +\load_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \load_cnt[0]_i_1__1_n_0\, + Q => load_cnt(0), + R => RST_DCLK_RESET + ); +\rate_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => \rate_reg1_reg[0]_0\(0), + Q => rate_reg1(0), + R => RST_DCLK_RESET + ); +\rate_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => '0', + Q => rate_reg1(1), + R => RST_DCLK_RESET + ); +\rate_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => rate_reg1(0), + Q => rate_reg2(0), + R => RST_DCLK_RESET + ); +\rate_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => rate_reg1(1), + Q => rate_reg2(1), + R => RST_DCLK_RESET + ); +rdy_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => DRP_RDY, + Q => rdy_reg1, + R => RST_DCLK_RESET + ); +rdy_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => rdy_reg1, + Q => rdy_reg2, + R => RST_DCLK_RESET + ); +start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => RATE_DRP_START, + Q => start_reg1, + R => RST_DCLK_RESET + ); +start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => start_reg1, + Q => start_reg2, + R => RST_DCLK_RESET + ); +x16_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => RATE_DRP_X16, + Q => x16_reg1, + R => RST_DCLK_RESET + ); +x16_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => x16_reg1, + Q => x16_reg2, + R => RST_DCLK_RESET + ); +x16x20_mode_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => RATE_DRP_X16X20_MODE, + Q => x16x20_mode_reg1, + R => RST_DCLK_RESET + ); +x16x20_mode_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => x16x20_mode_reg1, + Q => x16x20_mode_reg2, + R => RST_DCLK_RESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_drp_44 is + port ( + \fsm_reg[1]_0\ : out STD_LOGIC; + \fsm_reg[1]_1\ : out STD_LOGIC; + DRPADDR : out STD_LOGIC_VECTOR ( 7 downto 0 ); + DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 ); + DRP_DONE : out STD_LOGIC; + RST_DCLK_RESET : in STD_LOGIC; + RATE_DRP_X16X20_MODE : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + RATE_DRP_START : in STD_LOGIC; + DRP_RDY : in STD_LOGIC; + \rate_reg1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RATE_DRP_X16 : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 15 downto 0 ); + DRP_GTXRESET : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_drp_44 : entity is "pcie_7x_0_pipe_drp"; +end pcie_7x_0_pcie_7x_0_pipe_drp_44; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_drp_44 is + signal addr_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \addr_reg[4]_i_1__1_n_0\ : STD_LOGIC; + signal \addr_reg[6]_i_1__1_n_0\ : STD_LOGIC; + signal data_pma_rsv_a : STD_LOGIC_VECTOR ( 15 to 15 ); + signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \di_reg[0]_i_2__1_n_0\ : STD_LOGIC; + signal \di_reg[0]_i_3__1_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_2__1_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_3__1_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_4__1_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_5__1_n_0\ : STD_LOGIC; + signal \di_reg[12]_i_2__1_n_0\ : STD_LOGIC; + signal \di_reg[12]_i_3__1_n_0\ : STD_LOGIC; + signal \di_reg[13]_i_2__1_n_0\ : STD_LOGIC; + signal \di_reg[13]_i_3__1_n_0\ : STD_LOGIC; + signal \di_reg[14]_i_2__1_n_0\ : STD_LOGIC; + signal \di_reg[15]_i_2__1_n_0\ : STD_LOGIC; + signal \di_reg[1]_i_2__1_n_0\ : STD_LOGIC; + signal \di_reg[1]_i_3__1_n_0\ : STD_LOGIC; + signal \di_reg[2]_i_2__1_n_0\ : STD_LOGIC; + signal \di_reg[2]_i_3__1_n_0\ : STD_LOGIC; + signal \di_reg[3]_i_2__1_n_0\ : STD_LOGIC; + signal \di_reg[3]_i_3__1_n_0\ : STD_LOGIC; + signal \di_reg[4]_i_2__1_n_0\ : STD_LOGIC; + signal \di_reg[4]_i_3__1_n_0\ : STD_LOGIC; + signal \di_reg[4]_i_4__1_n_0\ : STD_LOGIC; + signal \di_reg[5]_i_2__1_n_0\ : STD_LOGIC; + signal \di_reg[5]_i_3__1_n_0\ : STD_LOGIC; + signal \di_reg[6]_i_2__1_n_0\ : STD_LOGIC; + signal \di_reg[6]_i_3__1_n_0\ : STD_LOGIC; + signal \di_reg[7]_i_2__1_n_0\ : STD_LOGIC; + signal \di_reg[7]_i_3__1_n_0\ : STD_LOGIC; + signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of do_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of do_reg1 : signal is "true"; + signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute SHIFT_EXTRACT of do_reg2 : signal is "NO"; + attribute async_reg of do_reg2 : signal is "true"; + signal \done_i_1__2_n_0\ : STD_LOGIC; + signal drp_addr_18 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal drp_di_32 : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal fsm1 : STD_LOGIC; + signal \fsm[0]_i_2__5_n_0\ : STD_LOGIC; + signal \fsm_reg_n_0_[0]\ : STD_LOGIC; + signal \fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \fsm_reg_n_0_[2]\ : STD_LOGIC; + signal gtxreset_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of gtxreset_reg1 : signal is "NO"; + attribute async_reg of gtxreset_reg1 : signal is "true"; + signal gtxreset_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of gtxreset_reg2 : signal is "NO"; + attribute async_reg of gtxreset_reg2 : signal is "true"; + signal index : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \index[0]_i_1__1_n_0\ : STD_LOGIC; + signal \index[1]_i_1__1_n_0\ : STD_LOGIC; + signal \index[2]_i_1__1_n_0\ : STD_LOGIC; + signal \index[3]_i_1__1_n_0\ : STD_LOGIC; + signal \index[3]_i_2__1_n_0\ : STD_LOGIC; + signal \index[4]_i_1__1_n_0\ : STD_LOGIC; + signal \index[4]_i_2__1_n_0\ : STD_LOGIC; + signal \index[4]_i_3__1_n_0\ : STD_LOGIC; + signal load_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \load_cnt[0]_i_1__2_n_0\ : STD_LOGIC; + signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_reg1 : signal is "NO"; + attribute async_reg of rate_reg1 : signal is "true"; + signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_reg2 : signal is "NO"; + attribute async_reg of rate_reg2 : signal is "true"; + signal rdy_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rdy_reg1 : signal is "NO"; + attribute async_reg of rdy_reg1 : signal is "true"; + signal rdy_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rdy_reg2 : signal is "NO"; + attribute async_reg of rdy_reg2 : signal is "true"; + signal start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of start_reg1 : signal is "NO"; + attribute async_reg of start_reg1 : signal is "true"; + signal start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of start_reg2 : signal is "NO"; + attribute async_reg of start_reg2 : signal is "true"; + signal x16_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16_reg1 : signal is "NO"; + attribute async_reg of x16_reg1 : signal is "true"; + signal x16_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16_reg2 : signal is "NO"; + attribute async_reg of x16_reg2 : signal is "true"; + signal x16x20_mode_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16x20_mode_reg1 : signal is "NO"; + attribute async_reg of x16x20_mode_reg1 : signal is "true"; + signal x16x20_mode_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16x20_mode_reg2 : signal is "NO"; + attribute async_reg of x16x20_mode_reg2 : signal is "true"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \addr_reg[1]_i_1__1\ : label is "soft_lutpair124"; + attribute SOFT_HLUTNM of \addr_reg[2]_i_1__1\ : label is "soft_lutpair124"; + attribute SOFT_HLUTNM of \addr_reg[5]_i_1__1\ : label is "soft_lutpair123"; + attribute SOFT_HLUTNM of \addr_reg[6]_i_1__1\ : label is "soft_lutpair123"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \do_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \do_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[10]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[11]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[12]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[13]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[14]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[15]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[6]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[7]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[8]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[9]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[10]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[11]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[12]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[13]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[14]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[15]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[6]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[7]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[8]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[9]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[9]\ : label is "NO"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_10__1\ : label is "soft_lutpair135"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_11__1\ : label is "soft_lutpair135"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_12__1\ : label is "soft_lutpair134"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_13__1\ : label is "soft_lutpair134"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_14__1\ : label is "soft_lutpair133"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_15__1\ : label is "soft_lutpair133"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_16__1\ : label is "soft_lutpair132"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_17__1\ : label is "soft_lutpair132"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_18__1\ : label is "soft_lutpair131"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_19__1\ : label is "soft_lutpair131"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_20__1\ : label is "soft_lutpair130"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_21__1\ : label is "soft_lutpair130"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_39__2\ : label is "soft_lutpair129"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3__1\ : label is "soft_lutpair125"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_40__1\ : label is "soft_lutpair129"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_41__1\ : label is "soft_lutpair128"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_42__1\ : label is "soft_lutpair128"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_43__1\ : label is "soft_lutpair127"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_44__1\ : label is "soft_lutpair127"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_45__1\ : label is "soft_lutpair126"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_46__1\ : label is "soft_lutpair125"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_4__1\ : label is "soft_lutpair126"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_6__1\ : label is "soft_lutpair137"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_7__1\ : label is "soft_lutpair137"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_8__1\ : label is "soft_lutpair136"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_9__1\ : label is "soft_lutpair136"; + attribute ASYNC_REG_boolean of gtxreset_reg1_reg : label is std.standard.true; + attribute KEEP of gtxreset_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of gtxreset_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of gtxreset_reg2_reg : label is std.standard.true; + attribute KEEP of gtxreset_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of gtxreset_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \index[0]_i_1__1\ : label is "soft_lutpair122"; + attribute SOFT_HLUTNM of \index[1]_i_1__1\ : label is "soft_lutpair122"; + attribute SOFT_HLUTNM of \index[3]_i_2__1\ : label is "soft_lutpair138"; + attribute SOFT_HLUTNM of \index[4]_i_3__1\ : label is "soft_lutpair138"; + attribute ASYNC_REG_boolean of \rate_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of rdy_reg1_reg : label is std.standard.true; + attribute KEEP of rdy_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rdy_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rdy_reg2_reg : label is std.standard.true; + attribute KEEP of rdy_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rdy_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of start_reg1_reg : label is std.standard.true; + attribute KEEP of start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of start_reg2_reg : label is std.standard.true; + attribute KEEP of start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16_reg1_reg : label is std.standard.true; + attribute KEEP of x16_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16_reg2_reg : label is std.standard.true; + attribute KEEP of x16_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16x20_mode_reg1_reg : label is std.standard.true; + attribute KEEP of x16x20_mode_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16x20_mode_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16x20_mode_reg2_reg : label is std.standard.true; + attribute KEEP of x16x20_mode_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16x20_mode_reg2_reg : label is "NO"; +begin +\addr_reg[0]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1736415517364154" + ) + port map ( + I0 => index(4), + I1 => index(3), + I2 => index(2), + I3 => index(1), + I4 => index(0), + I5 => x16x20_mode_reg2, + O => addr_reg(0) + ); +\addr_reg[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40500F00" + ) + port map ( + I0 => index(4), + I1 => index(0), + I2 => index(3), + I3 => index(1), + I4 => index(2), + O => addr_reg(1) + ); +\addr_reg[2]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"05105A00" + ) + port map ( + I0 => index(4), + I1 => index(0), + I2 => index(3), + I3 => index(2), + I4 => index(1), + O => addr_reg(2) + ); +\addr_reg[3]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5767576753265327" + ) + port map ( + I0 => index(4), + I1 => index(3), + I2 => index(2), + I3 => index(1), + I4 => x16x20_mode_reg2, + I5 => index(0), + O => addr_reg(3) + ); +\addr_reg[4]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FAAFFF04" + ) + port map ( + I0 => index(0), + I1 => x16x20_mode_reg2, + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => index(4), + O => \addr_reg[4]_i_1__1_n_0\ + ); +\addr_reg[5]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"001A0F0A" + ) + port map ( + I0 => index(4), + I1 => index(0), + I2 => index(3), + I3 => index(1), + I4 => index(2), + O => addr_reg(5) + ); +\addr_reg[6]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001454" + ) + port map ( + I0 => index(2), + I1 => index(1), + I2 => index(3), + I3 => index(0), + I4 => index(4), + O => \addr_reg[6]_i_1__1_n_0\ + ); +\addr_reg[7]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5252424223236263" + ) + port map ( + I0 => index(4), + I1 => index(3), + I2 => index(2), + I3 => x16x20_mode_reg2, + I4 => index(0), + I5 => index(1), + O => addr_reg(7) + ); +\addr_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(0), + Q => drp_addr_18(0), + R => RST_DCLK_RESET + ); +\addr_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(1), + Q => drp_addr_18(1), + R => RST_DCLK_RESET + ); +\addr_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(2), + Q => drp_addr_18(2), + R => RST_DCLK_RESET + ); +\addr_reg_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(3), + Q => drp_addr_18(3), + R => RST_DCLK_RESET + ); +\addr_reg_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \addr_reg[4]_i_1__1_n_0\, + Q => drp_addr_18(4), + R => RST_DCLK_RESET + ); +\addr_reg_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(5), + Q => drp_addr_18(5), + R => RST_DCLK_RESET + ); +\addr_reg_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \addr_reg[6]_i_1__1_n_0\, + Q => drp_addr_18(6), + R => RST_DCLK_RESET + ); +\addr_reg_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(7), + Q => drp_addr_18(7), + R => RST_DCLK_RESET + ); +\di_reg[0]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF5E7F6FA1001000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => index(1), + I3 => data_pma_rsv_a(15), + I4 => index(0), + I5 => do_reg2(0), + O => \di_reg[0]_i_2__1_n_0\ + ); +\di_reg[0]_i_3__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000005D0" + ) + port map ( + I0 => index(0), + I1 => do_reg2(0), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[0]_i_3__1_n_0\ + ); +\di_reg[10]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"45555F5540000000" + ) + port map ( + I0 => index(4), + I1 => \di_reg[15]_i_2__1_n_0\, + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(10), + O => di_reg(10) + ); +\di_reg[11]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4F40DDDD4F408888" + ) + port map ( + I0 => index(3), + I1 => do_reg2(11), + I2 => index(1), + I3 => \di_reg[11]_i_4__1_n_0\, + I4 => index(2), + I5 => \di_reg[11]_i_5__1_n_0\, + O => \di_reg[11]_i_2__1_n_0\ + ); +\di_reg[11]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000008080838" + ) + port map ( + I0 => do_reg2(11), + I1 => index(2), + I2 => index(1), + I3 => data_pma_rsv_a(15), + I4 => index(0), + I5 => index(3), + O => \di_reg[11]_i_3__1_n_0\ + ); +\di_reg[11]_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B8BB" + ) + port map ( + I0 => do_reg2(11), + I1 => index(0), + I2 => rate_reg2(0), + I3 => rate_reg2(1), + O => \di_reg[11]_i_4__1_n_0\ + ); +\di_reg[11]_i_5__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EFFF0100" + ) + port map ( + I0 => index(1), + I1 => index(0), + I2 => x16_reg2, + I3 => x16x20_mode_reg2, + I4 => do_reg2(11), + O => \di_reg[11]_i_5__1_n_0\ + ); +\di_reg[12]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"777EFFFF01080000" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => index(0), + I3 => data_pma_rsv_a(15), + I4 => index(2), + I5 => do_reg2(12), + O => \di_reg[12]_i_2__1_n_0\ + ); +\di_reg[12]_i_3__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000B08" + ) + port map ( + I0 => do_reg2(12), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => index(3), + O => \di_reg[12]_i_3__1_n_0\ + ); +\di_reg[13]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"767FFFFF00090000" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => index(0), + I3 => data_pma_rsv_a(15), + I4 => index(2), + I5 => do_reg2(13), + O => \di_reg[13]_i_2__1_n_0\ + ); +\di_reg[13]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000008380808" + ) + port map ( + I0 => do_reg2(13), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => data_pma_rsv_a(15), + I5 => index(3), + O => \di_reg[13]_i_3__1_n_0\ + ); +\di_reg[14]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0040FFFF00400000" + ) + port map ( + I0 => index(1), + I1 => index(2), + I2 => do_reg2(14), + I3 => index(3), + I4 => index(4), + I5 => \di_reg[14]_i_2__1_n_0\, + O => di_reg(14) + ); +\di_reg[14]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"653BFFF721080080" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => data_pma_rsv_a(15), + I3 => index(0), + I4 => index(2), + I5 => do_reg2(14), + O => \di_reg[14]_i_2__1_n_0\ + ); +\di_reg[14]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + O => data_pma_rsv_a(15) + ); +\di_reg[15]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"45555F5540000000" + ) + port map ( + I0 => index(4), + I1 => \di_reg[15]_i_2__1_n_0\, + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(15), + O => di_reg(15) + ); +\di_reg[15]_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => rate_reg2(1), + I1 => rate_reg2(0), + I2 => index(0), + O => \di_reg[15]_i_2__1_n_0\ + ); +\di_reg[1]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5FEE4E0076FF1000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => data_pma_rsv_a(15), + I3 => index(1), + I4 => do_reg2(1), + I5 => index(0), + O => \di_reg[1]_i_2__1_n_0\ + ); +\di_reg[1]_i_3__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000005D0" + ) + port map ( + I0 => index(0), + I1 => do_reg2(1), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[1]_i_3__1_n_0\ + ); +\di_reg[2]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5DEE080067FF0100" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => data_pma_rsv_a(15), + I3 => index(1), + I4 => do_reg2(2), + I5 => index(0), + O => \di_reg[2]_i_2__1_n_0\ + ); +\di_reg[2]_i_3__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000380" + ) + port map ( + I0 => do_reg2(2), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[2]_i_3__1_n_0\ + ); +\di_reg[3]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"43FFFFFF40000000" + ) + port map ( + I0 => data_pma_rsv_a(15), + I1 => index(2), + I2 => index(0), + I3 => index(1), + I4 => index(3), + I5 => do_reg2(3), + O => \di_reg[3]_i_2__1_n_0\ + ); +\di_reg[3]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000033D100" + ) + port map ( + I0 => data_pma_rsv_a(15), + I1 => index(0), + I2 => do_reg2(3), + I3 => index(2), + I4 => index(1), + I5 => index(3), + O => \di_reg[3]_i_3__1_n_0\ + ); +\di_reg[4]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \di_reg[4]_i_2__1_n_0\, + I1 => index(4), + I2 => \di_reg[4]_i_3__1_n_0\, + I3 => index(3), + I4 => \di_reg[4]_i_4__1_n_0\, + O => di_reg(4) + ); +\di_reg[4]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0400F0000400F0" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + I2 => index(1), + I3 => index(2), + I4 => index(0), + I5 => do_reg2(4), + O => \di_reg[4]_i_2__1_n_0\ + ); +\di_reg[4]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"400FFFFF40000000" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + I2 => index(2), + I3 => index(0), + I4 => index(1), + I5 => do_reg2(4), + O => \di_reg[4]_i_3__1_n_0\ + ); +\di_reg[4]_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BF00BF01FF40FE40" + ) + port map ( + I0 => index(2), + I1 => index(1), + I2 => index(0), + I3 => do_reg2(4), + I4 => x16x20_mode_reg2, + I5 => data_pma_rsv_a(15), + O => \di_reg[4]_i_4__1_n_0\ + ); +\di_reg[5]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7F7F7F7E00000000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => x16x20_mode_reg2, + I5 => do_reg2(5), + O => \di_reg[5]_i_2__1_n_0\ + ); +\di_reg[5]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000038F0380" + ) + port map ( + I0 => do_reg2(5), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => data_pma_rsv_a(15), + I5 => index(3), + O => \di_reg[5]_i_3__1_n_0\ + ); +\di_reg[6]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7D7F7D7E00000000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => x16x20_mode_reg2, + I5 => do_reg2(6), + O => \di_reg[6]_i_2__1_n_0\ + ); +\di_reg[6]_i_3__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000380" + ) + port map ( + I0 => do_reg2(6), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[6]_i_3__1_n_0\ + ); +\di_reg[7]_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF0900" + ) + port map ( + I0 => index(2), + I1 => index(1), + I2 => index(0), + I3 => index(3), + I4 => do_reg2(7), + O => \di_reg[7]_i_2__1_n_0\ + ); +\di_reg[7]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000003800383" + ) + port map ( + I0 => do_reg2(7), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => data_pma_rsv_a(15), + I5 => index(3), + O => \di_reg[7]_i_3__1_n_0\ + ); +\di_reg[8]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"03333F7300000040" + ) + port map ( + I0 => index(0), + I1 => index(4), + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(8), + O => di_reg(8) + ); +\di_reg[9]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"03333F7300000040" + ) + port map ( + I0 => index(0), + I1 => index(4), + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(9), + O => di_reg(9) + ); +\di_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(0), + Q => drp_di_32(0), + R => RST_DCLK_RESET + ); +\di_reg_reg[0]_i_1__1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[0]_i_2__1_n_0\, + I1 => \di_reg[0]_i_3__1_n_0\, + O => di_reg(0), + S => index(4) + ); +\di_reg_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(10), + Q => drp_di_32(10), + R => RST_DCLK_RESET + ); +\di_reg_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(11), + Q => drp_di_32(11), + R => RST_DCLK_RESET + ); +\di_reg_reg[11]_i_1__1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[11]_i_2__1_n_0\, + I1 => \di_reg[11]_i_3__1_n_0\, + O => di_reg(11), + S => index(4) + ); +\di_reg_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(12), + Q => drp_di_32(12), + R => RST_DCLK_RESET + ); +\di_reg_reg[12]_i_1__1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[12]_i_2__1_n_0\, + I1 => \di_reg[12]_i_3__1_n_0\, + O => di_reg(12), + S => index(4) + ); +\di_reg_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(13), + Q => drp_di_32(13), + R => RST_DCLK_RESET + ); +\di_reg_reg[13]_i_1__1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[13]_i_2__1_n_0\, + I1 => \di_reg[13]_i_3__1_n_0\, + O => di_reg(13), + S => index(4) + ); +\di_reg_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(14), + Q => drp_di_32(14), + R => RST_DCLK_RESET + ); +\di_reg_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(15), + Q => drp_di_32(15), + R => RST_DCLK_RESET + ); +\di_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(1), + Q => drp_di_32(1), + R => RST_DCLK_RESET + ); +\di_reg_reg[1]_i_1__1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[1]_i_2__1_n_0\, + I1 => \di_reg[1]_i_3__1_n_0\, + O => di_reg(1), + S => index(4) + ); +\di_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(2), + Q => drp_di_32(2), + R => RST_DCLK_RESET + ); +\di_reg_reg[2]_i_1__1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[2]_i_2__1_n_0\, + I1 => \di_reg[2]_i_3__1_n_0\, + O => di_reg(2), + S => index(4) + ); +\di_reg_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(3), + Q => drp_di_32(3), + R => RST_DCLK_RESET + ); +\di_reg_reg[3]_i_1__1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[3]_i_2__1_n_0\, + I1 => \di_reg[3]_i_3__1_n_0\, + O => di_reg(3), + S => index(4) + ); +\di_reg_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(4), + Q => drp_di_32(4), + R => RST_DCLK_RESET + ); +\di_reg_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(5), + Q => drp_di_32(5), + R => RST_DCLK_RESET + ); +\di_reg_reg[5]_i_1__1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[5]_i_2__1_n_0\, + I1 => \di_reg[5]_i_3__1_n_0\, + O => di_reg(5), + S => index(4) + ); +\di_reg_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(6), + Q => drp_di_32(6), + R => RST_DCLK_RESET + ); +\di_reg_reg[6]_i_1__1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[6]_i_2__1_n_0\, + I1 => \di_reg[6]_i_3__1_n_0\, + O => di_reg(6), + S => index(4) + ); +\di_reg_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(7), + Q => drp_di_32(7), + R => RST_DCLK_RESET + ); +\di_reg_reg[7]_i_1__1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[7]_i_2__1_n_0\, + I1 => \di_reg[7]_i_3__1_n_0\, + O => di_reg(7), + S => index(4) + ); +\di_reg_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(8), + Q => drp_di_32(8), + R => RST_DCLK_RESET + ); +\di_reg_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(9), + Q => drp_di_32(9), + R => RST_DCLK_RESET + ); +\do_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(0), + Q => do_reg1(0), + R => RST_DCLK_RESET + ); +\do_reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(10), + Q => do_reg1(10), + R => RST_DCLK_RESET + ); +\do_reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(11), + Q => do_reg1(11), + R => RST_DCLK_RESET + ); +\do_reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(12), + Q => do_reg1(12), + R => RST_DCLK_RESET + ); +\do_reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(13), + Q => do_reg1(13), + R => RST_DCLK_RESET + ); +\do_reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(14), + Q => do_reg1(14), + R => RST_DCLK_RESET + ); +\do_reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(15), + Q => do_reg1(15), + R => RST_DCLK_RESET + ); +\do_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(1), + Q => do_reg1(1), + R => RST_DCLK_RESET + ); +\do_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(2), + Q => do_reg1(2), + R => RST_DCLK_RESET + ); +\do_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(3), + Q => do_reg1(3), + R => RST_DCLK_RESET + ); +\do_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(4), + Q => do_reg1(4), + R => RST_DCLK_RESET + ); +\do_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(5), + Q => do_reg1(5), + R => RST_DCLK_RESET + ); +\do_reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(6), + Q => do_reg1(6), + R => RST_DCLK_RESET + ); +\do_reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(7), + Q => do_reg1(7), + R => RST_DCLK_RESET + ); +\do_reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(8), + Q => do_reg1(8), + R => RST_DCLK_RESET + ); +\do_reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(9), + Q => do_reg1(9), + R => RST_DCLK_RESET + ); +\do_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(0), + Q => do_reg2(0), + R => RST_DCLK_RESET + ); +\do_reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(10), + Q => do_reg2(10), + R => RST_DCLK_RESET + ); +\do_reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(11), + Q => do_reg2(11), + R => RST_DCLK_RESET + ); +\do_reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(12), + Q => do_reg2(12), + R => RST_DCLK_RESET + ); +\do_reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(13), + Q => do_reg2(13), + R => RST_DCLK_RESET + ); +\do_reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(14), + Q => do_reg2(14), + R => RST_DCLK_RESET + ); +\do_reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(15), + Q => do_reg2(15), + R => RST_DCLK_RESET + ); +\do_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(1), + Q => do_reg2(1), + R => RST_DCLK_RESET + ); +\do_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(2), + Q => do_reg2(2), + R => RST_DCLK_RESET + ); +\do_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(3), + Q => do_reg2(3), + R => RST_DCLK_RESET + ); +\do_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(4), + Q => do_reg2(4), + R => RST_DCLK_RESET + ); +\do_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(5), + Q => do_reg2(5), + R => RST_DCLK_RESET + ); +\do_reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(6), + Q => do_reg2(6), + R => RST_DCLK_RESET + ); +\do_reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(7), + Q => do_reg2(7), + R => RST_DCLK_RESET + ); +\do_reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(8), + Q => do_reg2(8), + R => RST_DCLK_RESET + ); +\do_reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(9), + Q => do_reg2(9), + R => RST_DCLK_RESET + ); +\done_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => start_reg2, + I3 => \fsm_reg_n_0_[1]\, + O => \done_i_1__2_n_0\ + ); +done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \done_i_1__2_n_0\, + Q => DRP_DONE, + R => RST_DCLK_RESET + ); +\fsm[0]_i_1__5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0737FFFF07370000" + ) + port map ( + I0 => fsm1, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => rdy_reg2, + I4 => \fsm_reg_n_0_[2]\, + I5 => \fsm[0]_i_2__5_n_0\, + O => fsm(0) + ); +\fsm[0]_i_2__5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"47FF47CC" + ) + port map ( + I0 => rdy_reg2, + I1 => \fsm_reg_n_0_[1]\, + I2 => load_cnt(0), + I3 => \fsm_reg_n_0_[0]\, + I4 => start_reg2, + O => \fsm[0]_i_2__5_n_0\ + ); +\fsm[1]_i_1__5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"1D501850" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => rdy_reg2, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => load_cnt(0), + O => fsm(1) + ); +\fsm[2]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6222" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => rdy_reg2, + O => fsm(2) + ); +\fsm_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => fsm(0), + Q => \fsm_reg_n_0_[0]\, + R => RST_DCLK_RESET + ); +\fsm_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => fsm(1), + Q => \fsm_reg_n_0_[1]\, + R => RST_DCLK_RESET + ); +\fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => fsm(2), + Q => \fsm_reg_n_0_[2]\, + R => RST_DCLK_RESET + ); +\gtx_channel.gtxe2_channel_i_i_10__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(11), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(11) + ); +\gtx_channel.gtxe2_channel_i_i_11__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(10), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(10) + ); +\gtx_channel.gtxe2_channel_i_i_12__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(9), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(9) + ); +\gtx_channel.gtxe2_channel_i_i_13__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(8), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(8) + ); +\gtx_channel.gtxe2_channel_i_i_14__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(7), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(7) + ); +\gtx_channel.gtxe2_channel_i_i_15__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(6), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(6) + ); +\gtx_channel.gtxe2_channel_i_i_16__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(5), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(5) + ); +\gtx_channel.gtxe2_channel_i_i_17__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(4), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(4) + ); +\gtx_channel.gtxe2_channel_i_i_18__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(3), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(3) + ); +\gtx_channel.gtxe2_channel_i_i_19__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(2), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(2) + ); +\gtx_channel.gtxe2_channel_i_i_20__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(1), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(1) + ); +\gtx_channel.gtxe2_channel_i_i_21__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(0), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(0) + ); +\gtx_channel.gtxe2_channel_i_i_39__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_18(7), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(7) + ); +\gtx_channel.gtxe2_channel_i_i_3__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"12" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \fsm_reg[1]_0\ + ); +\gtx_channel.gtxe2_channel_i_i_40__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_18(6), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(6) + ); +\gtx_channel.gtxe2_channel_i_i_41__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_18(5), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(5) + ); +\gtx_channel.gtxe2_channel_i_i_42__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_18(4), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(4) + ); +\gtx_channel.gtxe2_channel_i_i_43__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_18(3), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(3) + ); +\gtx_channel.gtxe2_channel_i_i_44__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_18(2), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(2) + ); +\gtx_channel.gtxe2_channel_i_i_45__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_18(1), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(1) + ); +\gtx_channel.gtxe2_channel_i_i_46__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_18(0), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(0) + ); +\gtx_channel.gtxe2_channel_i_i_4__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"10" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \fsm_reg[1]_1\ + ); +\gtx_channel.gtxe2_channel_i_i_6__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(15), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(15) + ); +\gtx_channel.gtxe2_channel_i_i_7__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(14), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(14) + ); +\gtx_channel.gtxe2_channel_i_i_8__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(13), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(13) + ); +\gtx_channel.gtxe2_channel_i_i_9__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_32(12), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(12) + ); +gtxreset_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => DRP_GTXRESET, + Q => gtxreset_reg1, + R => RST_DCLK_RESET + ); +gtxreset_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => gtxreset_reg1, + Q => gtxreset_reg2, + R => RST_DCLK_RESET + ); +\index[0]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0100" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => fsm1, + I2 => index(0), + I3 => \fsm_reg_n_0_[2]\, + O => \index[0]_i_1__1_n_0\ + ); +\index[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00140000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(1), + I2 => index(0), + I3 => fsm1, + I4 => \fsm_reg_n_0_[2]\, + O => \index[1]_i_1__1_n_0\ + ); +\index[2]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000144400000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => fsm1, + I5 => \fsm_reg_n_0_[2]\, + O => \index[2]_i_1__1_n_0\ + ); +\index[3]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000144400000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(3), + I2 => index(2), + I3 => \index[3]_i_2__1_n_0\, + I4 => fsm1, + I5 => \fsm_reg_n_0_[2]\, + O => \index[3]_i_1__1_n_0\ + ); +\index[3]_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => index(1), + I1 => index(0), + O => \index[3]_i_2__1_n_0\ + ); +\index[4]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A1" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \index[4]_i_1__1_n_0\ + ); +\index[4]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000144400000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(4), + I2 => index(3), + I3 => \index[4]_i_3__1_n_0\, + I4 => fsm1, + I5 => \fsm_reg_n_0_[2]\, + O => \index[4]_i_2__1_n_0\ + ); +\index[4]_i_3__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => index(2), + I1 => index(0), + I2 => index(1), + O => \index[4]_i_3__1_n_0\ + ); +\index[4]_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000000110000000" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => index(0), + I3 => index(4), + I4 => index(2), + I5 => x16x20_mode_reg2, + O => fsm1 + ); +\index_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__1_n_0\, + D => \index[0]_i_1__1_n_0\, + Q => index(0), + R => RST_DCLK_RESET + ); +\index_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__1_n_0\, + D => \index[1]_i_1__1_n_0\, + Q => index(1), + R => RST_DCLK_RESET + ); +\index_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__1_n_0\, + D => \index[2]_i_1__1_n_0\, + Q => index(2), + R => RST_DCLK_RESET + ); +\index_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__1_n_0\, + D => \index[3]_i_1__1_n_0\, + Q => index(3), + R => RST_DCLK_RESET + ); +\index_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__1_n_0\, + D => \index[4]_i_2__1_n_0\, + Q => index(4), + R => RST_DCLK_RESET + ); +\load_cnt[0]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"10" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + O => \load_cnt[0]_i_1__2_n_0\ + ); +\load_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \load_cnt[0]_i_1__2_n_0\, + Q => load_cnt(0), + R => RST_DCLK_RESET + ); +\rate_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => \rate_reg1_reg[0]_0\(0), + Q => rate_reg1(0), + R => RST_DCLK_RESET + ); +\rate_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => '0', + Q => rate_reg1(1), + R => RST_DCLK_RESET + ); +\rate_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => rate_reg1(0), + Q => rate_reg2(0), + R => RST_DCLK_RESET + ); +\rate_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => rate_reg1(1), + Q => rate_reg2(1), + R => RST_DCLK_RESET + ); +rdy_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => DRP_RDY, + Q => rdy_reg1, + R => RST_DCLK_RESET + ); +rdy_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => rdy_reg1, + Q => rdy_reg2, + R => RST_DCLK_RESET + ); +start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => RATE_DRP_START, + Q => start_reg1, + R => RST_DCLK_RESET + ); +start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => start_reg1, + Q => start_reg2, + R => RST_DCLK_RESET + ); +x16_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => RATE_DRP_X16, + Q => x16_reg1, + R => RST_DCLK_RESET + ); +x16_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => x16_reg1, + Q => x16_reg2, + R => RST_DCLK_RESET + ); +x16x20_mode_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => RATE_DRP_X16X20_MODE, + Q => x16x20_mode_reg1, + R => RST_DCLK_RESET + ); +x16x20_mode_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => x16x20_mode_reg1, + Q => x16x20_mode_reg2, + R => RST_DCLK_RESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_drp_50 is + port ( + \fsm_reg[1]_0\ : out STD_LOGIC; + \fsm_reg[1]_1\ : out STD_LOGIC; + DRPADDR : out STD_LOGIC_VECTOR ( 7 downto 0 ); + DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 ); + DRP_DONE : out STD_LOGIC; + RST_DCLK_RESET : in STD_LOGIC; + RATE_DRP_X16X20_MODE : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + RATE_DRP_START : in STD_LOGIC; + DRP_RDY : in STD_LOGIC; + \rate_reg1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RATE_DRP_X16 : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 15 downto 0 ); + DRP_GTXRESET : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_drp_50 : entity is "pcie_7x_0_pipe_drp"; +end pcie_7x_0_pcie_7x_0_pipe_drp_50; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_drp_50 is + signal addr_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \addr_reg[4]_i_1__2_n_0\ : STD_LOGIC; + signal \addr_reg[6]_i_1__2_n_0\ : STD_LOGIC; + signal data_pma_rsv_a : STD_LOGIC_VECTOR ( 15 to 15 ); + signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \di_reg[0]_i_2__2_n_0\ : STD_LOGIC; + signal \di_reg[0]_i_3__2_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_2__2_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_3__2_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_4__2_n_0\ : STD_LOGIC; + signal \di_reg[11]_i_5__2_n_0\ : STD_LOGIC; + signal \di_reg[12]_i_2__2_n_0\ : STD_LOGIC; + signal \di_reg[12]_i_3__2_n_0\ : STD_LOGIC; + signal \di_reg[13]_i_2__2_n_0\ : STD_LOGIC; + signal \di_reg[13]_i_3__2_n_0\ : STD_LOGIC; + signal \di_reg[14]_i_2__2_n_0\ : STD_LOGIC; + signal \di_reg[15]_i_2__2_n_0\ : STD_LOGIC; + signal \di_reg[1]_i_2__2_n_0\ : STD_LOGIC; + signal \di_reg[1]_i_3__2_n_0\ : STD_LOGIC; + signal \di_reg[2]_i_2__2_n_0\ : STD_LOGIC; + signal \di_reg[2]_i_3__2_n_0\ : STD_LOGIC; + signal \di_reg[3]_i_2__2_n_0\ : STD_LOGIC; + signal \di_reg[3]_i_3__2_n_0\ : STD_LOGIC; + signal \di_reg[4]_i_2__2_n_0\ : STD_LOGIC; + signal \di_reg[4]_i_3__2_n_0\ : STD_LOGIC; + signal \di_reg[4]_i_4__2_n_0\ : STD_LOGIC; + signal \di_reg[5]_i_2__2_n_0\ : STD_LOGIC; + signal \di_reg[5]_i_3__2_n_0\ : STD_LOGIC; + signal \di_reg[6]_i_2__2_n_0\ : STD_LOGIC; + signal \di_reg[6]_i_3__2_n_0\ : STD_LOGIC; + signal \di_reg[7]_i_2__2_n_0\ : STD_LOGIC; + signal \di_reg[7]_i_3__2_n_0\ : STD_LOGIC; + signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of do_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of do_reg1 : signal is "true"; + signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute SHIFT_EXTRACT of do_reg2 : signal is "NO"; + attribute async_reg of do_reg2 : signal is "true"; + signal \done_i_1__3_n_0\ : STD_LOGIC; + signal drp_addr_27 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal drp_di_48 : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal fsm1 : STD_LOGIC; + signal \fsm[0]_i_2__7_n_0\ : STD_LOGIC; + signal \fsm_reg_n_0_[0]\ : STD_LOGIC; + signal \fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \fsm_reg_n_0_[2]\ : STD_LOGIC; + signal gtxreset_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of gtxreset_reg1 : signal is "NO"; + attribute async_reg of gtxreset_reg1 : signal is "true"; + signal gtxreset_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of gtxreset_reg2 : signal is "NO"; + attribute async_reg of gtxreset_reg2 : signal is "true"; + signal index : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \index[0]_i_1__2_n_0\ : STD_LOGIC; + signal \index[1]_i_1__2_n_0\ : STD_LOGIC; + signal \index[2]_i_1__2_n_0\ : STD_LOGIC; + signal \index[3]_i_1__2_n_0\ : STD_LOGIC; + signal \index[3]_i_2__2_n_0\ : STD_LOGIC; + signal \index[4]_i_1__2_n_0\ : STD_LOGIC; + signal \index[4]_i_2__2_n_0\ : STD_LOGIC; + signal \index[4]_i_3__2_n_0\ : STD_LOGIC; + signal load_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \load_cnt[0]_i_1__3_n_0\ : STD_LOGIC; + signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_reg1 : signal is "NO"; + attribute async_reg of rate_reg1 : signal is "true"; + signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_reg2 : signal is "NO"; + attribute async_reg of rate_reg2 : signal is "true"; + signal rdy_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rdy_reg1 : signal is "NO"; + attribute async_reg of rdy_reg1 : signal is "true"; + signal rdy_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rdy_reg2 : signal is "NO"; + attribute async_reg of rdy_reg2 : signal is "true"; + signal start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of start_reg1 : signal is "NO"; + attribute async_reg of start_reg1 : signal is "true"; + signal start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of start_reg2 : signal is "NO"; + attribute async_reg of start_reg2 : signal is "true"; + signal x16_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16_reg1 : signal is "NO"; + attribute async_reg of x16_reg1 : signal is "true"; + signal x16_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16_reg2 : signal is "NO"; + attribute async_reg of x16_reg2 : signal is "true"; + signal x16x20_mode_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16x20_mode_reg1 : signal is "NO"; + attribute async_reg of x16x20_mode_reg1 : signal is "true"; + signal x16x20_mode_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of x16x20_mode_reg2 : signal is "NO"; + attribute async_reg of x16x20_mode_reg2 : signal is "true"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \addr_reg[1]_i_1__2\ : label is "soft_lutpair165"; + attribute SOFT_HLUTNM of \addr_reg[2]_i_1__2\ : label is "soft_lutpair165"; + attribute SOFT_HLUTNM of \addr_reg[5]_i_1__2\ : label is "soft_lutpair164"; + attribute SOFT_HLUTNM of \addr_reg[6]_i_1__2\ : label is "soft_lutpair164"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \do_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \do_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[10]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[11]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[12]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[13]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[14]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[15]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[6]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[7]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[8]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[9]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[10]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[11]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[12]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[13]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[14]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[15]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[6]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[7]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[8]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[9]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[9]\ : label is "NO"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_10__2\ : label is "soft_lutpair177"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_11__2\ : label is "soft_lutpair176"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_12__2\ : label is "soft_lutpair176"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_13__2\ : label is "soft_lutpair175"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_14__2\ : label is "soft_lutpair175"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_15__2\ : label is "soft_lutpair174"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_16__2\ : label is "soft_lutpair174"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_17__2\ : label is "soft_lutpair173"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_18__2\ : label is "soft_lutpair173"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_19__2\ : label is "soft_lutpair172"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_20__2\ : label is "soft_lutpair172"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_21__2\ : label is "soft_lutpair171"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_22__2\ : label is "soft_lutpair171"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3__2\ : label is "soft_lutpair166"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_40__2\ : label is "soft_lutpair170"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_41__2\ : label is "soft_lutpair170"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_42__2\ : label is "soft_lutpair169"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_43__2\ : label is "soft_lutpair169"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_44__2\ : label is "soft_lutpair168"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_45__2\ : label is "soft_lutpair168"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_46__2\ : label is "soft_lutpair167"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_47\ : label is "soft_lutpair166"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_4__2\ : label is "soft_lutpair167"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_7__2\ : label is "soft_lutpair178"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_8__2\ : label is "soft_lutpair178"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_9__2\ : label is "soft_lutpair177"; + attribute ASYNC_REG_boolean of gtxreset_reg1_reg : label is std.standard.true; + attribute KEEP of gtxreset_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of gtxreset_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of gtxreset_reg2_reg : label is std.standard.true; + attribute KEEP of gtxreset_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of gtxreset_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \index[0]_i_1__2\ : label is "soft_lutpair163"; + attribute SOFT_HLUTNM of \index[1]_i_1__2\ : label is "soft_lutpair163"; + attribute SOFT_HLUTNM of \index[3]_i_2__2\ : label is "soft_lutpair179"; + attribute SOFT_HLUTNM of \index[4]_i_3__2\ : label is "soft_lutpair179"; + attribute ASYNC_REG_boolean of \rate_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of rdy_reg1_reg : label is std.standard.true; + attribute KEEP of rdy_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rdy_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rdy_reg2_reg : label is std.standard.true; + attribute KEEP of rdy_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rdy_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of start_reg1_reg : label is std.standard.true; + attribute KEEP of start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of start_reg2_reg : label is std.standard.true; + attribute KEEP of start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16_reg1_reg : label is std.standard.true; + attribute KEEP of x16_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16_reg2_reg : label is std.standard.true; + attribute KEEP of x16_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16x20_mode_reg1_reg : label is std.standard.true; + attribute KEEP of x16x20_mode_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16x20_mode_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of x16x20_mode_reg2_reg : label is std.standard.true; + attribute KEEP of x16x20_mode_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of x16x20_mode_reg2_reg : label is "NO"; +begin +\addr_reg[0]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1736415517364154" + ) + port map ( + I0 => index(4), + I1 => index(3), + I2 => index(2), + I3 => index(1), + I4 => index(0), + I5 => x16x20_mode_reg2, + O => addr_reg(0) + ); +\addr_reg[1]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40500F00" + ) + port map ( + I0 => index(4), + I1 => index(0), + I2 => index(3), + I3 => index(1), + I4 => index(2), + O => addr_reg(1) + ); +\addr_reg[2]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"05105A00" + ) + port map ( + I0 => index(4), + I1 => index(0), + I2 => index(3), + I3 => index(2), + I4 => index(1), + O => addr_reg(2) + ); +\addr_reg[3]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5767576753265327" + ) + port map ( + I0 => index(4), + I1 => index(3), + I2 => index(2), + I3 => index(1), + I4 => x16x20_mode_reg2, + I5 => index(0), + O => addr_reg(3) + ); +\addr_reg[4]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FAAFFF04" + ) + port map ( + I0 => index(0), + I1 => x16x20_mode_reg2, + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => index(4), + O => \addr_reg[4]_i_1__2_n_0\ + ); +\addr_reg[5]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"001A0F0A" + ) + port map ( + I0 => index(4), + I1 => index(0), + I2 => index(3), + I3 => index(1), + I4 => index(2), + O => addr_reg(5) + ); +\addr_reg[6]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001454" + ) + port map ( + I0 => index(2), + I1 => index(1), + I2 => index(3), + I3 => index(0), + I4 => index(4), + O => \addr_reg[6]_i_1__2_n_0\ + ); +\addr_reg[7]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5252424223236263" + ) + port map ( + I0 => index(4), + I1 => index(3), + I2 => index(2), + I3 => x16x20_mode_reg2, + I4 => index(0), + I5 => index(1), + O => addr_reg(7) + ); +\addr_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(0), + Q => drp_addr_27(0), + R => RST_DCLK_RESET + ); +\addr_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(1), + Q => drp_addr_27(1), + R => RST_DCLK_RESET + ); +\addr_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(2), + Q => drp_addr_27(2), + R => RST_DCLK_RESET + ); +\addr_reg_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(3), + Q => drp_addr_27(3), + R => RST_DCLK_RESET + ); +\addr_reg_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \addr_reg[4]_i_1__2_n_0\, + Q => drp_addr_27(4), + R => RST_DCLK_RESET + ); +\addr_reg_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(5), + Q => drp_addr_27(5), + R => RST_DCLK_RESET + ); +\addr_reg_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \addr_reg[6]_i_1__2_n_0\, + Q => drp_addr_27(6), + R => RST_DCLK_RESET + ); +\addr_reg_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => addr_reg(7), + Q => drp_addr_27(7), + R => RST_DCLK_RESET + ); +\di_reg[0]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF5E7F6FA1001000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => index(1), + I3 => data_pma_rsv_a(15), + I4 => index(0), + I5 => do_reg2(0), + O => \di_reg[0]_i_2__2_n_0\ + ); +\di_reg[0]_i_3__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000005D0" + ) + port map ( + I0 => index(0), + I1 => do_reg2(0), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[0]_i_3__2_n_0\ + ); +\di_reg[10]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"45555F5540000000" + ) + port map ( + I0 => index(4), + I1 => \di_reg[15]_i_2__2_n_0\, + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(10), + O => di_reg(10) + ); +\di_reg[11]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4F40DDDD4F408888" + ) + port map ( + I0 => index(3), + I1 => do_reg2(11), + I2 => index(1), + I3 => \di_reg[11]_i_4__2_n_0\, + I4 => index(2), + I5 => \di_reg[11]_i_5__2_n_0\, + O => \di_reg[11]_i_2__2_n_0\ + ); +\di_reg[11]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000008080838" + ) + port map ( + I0 => do_reg2(11), + I1 => index(2), + I2 => index(1), + I3 => data_pma_rsv_a(15), + I4 => index(0), + I5 => index(3), + O => \di_reg[11]_i_3__2_n_0\ + ); +\di_reg[11]_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B8BB" + ) + port map ( + I0 => do_reg2(11), + I1 => index(0), + I2 => rate_reg2(0), + I3 => rate_reg2(1), + O => \di_reg[11]_i_4__2_n_0\ + ); +\di_reg[11]_i_5__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EFFF0100" + ) + port map ( + I0 => index(1), + I1 => index(0), + I2 => x16_reg2, + I3 => x16x20_mode_reg2, + I4 => do_reg2(11), + O => \di_reg[11]_i_5__2_n_0\ + ); +\di_reg[12]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"777EFFFF01080000" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => index(0), + I3 => data_pma_rsv_a(15), + I4 => index(2), + I5 => do_reg2(12), + O => \di_reg[12]_i_2__2_n_0\ + ); +\di_reg[12]_i_3__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000B08" + ) + port map ( + I0 => do_reg2(12), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => index(3), + O => \di_reg[12]_i_3__2_n_0\ + ); +\di_reg[13]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"767FFFFF00090000" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => index(0), + I3 => data_pma_rsv_a(15), + I4 => index(2), + I5 => do_reg2(13), + O => \di_reg[13]_i_2__2_n_0\ + ); +\di_reg[13]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000008380808" + ) + port map ( + I0 => do_reg2(13), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => data_pma_rsv_a(15), + I5 => index(3), + O => \di_reg[13]_i_3__2_n_0\ + ); +\di_reg[14]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0040FFFF00400000" + ) + port map ( + I0 => index(1), + I1 => index(2), + I2 => do_reg2(14), + I3 => index(3), + I4 => index(4), + I5 => \di_reg[14]_i_2__2_n_0\, + O => di_reg(14) + ); +\di_reg[14]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"653BFFF721080080" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => data_pma_rsv_a(15), + I3 => index(0), + I4 => index(2), + I5 => do_reg2(14), + O => \di_reg[14]_i_2__2_n_0\ + ); +\di_reg[14]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + O => data_pma_rsv_a(15) + ); +\di_reg[15]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"45555F5540000000" + ) + port map ( + I0 => index(4), + I1 => \di_reg[15]_i_2__2_n_0\, + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(15), + O => di_reg(15) + ); +\di_reg[15]_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => rate_reg2(1), + I1 => rate_reg2(0), + I2 => index(0), + O => \di_reg[15]_i_2__2_n_0\ + ); +\di_reg[1]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5FEE4E0076FF1000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => data_pma_rsv_a(15), + I3 => index(1), + I4 => do_reg2(1), + I5 => index(0), + O => \di_reg[1]_i_2__2_n_0\ + ); +\di_reg[1]_i_3__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000005D0" + ) + port map ( + I0 => index(0), + I1 => do_reg2(1), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[1]_i_3__2_n_0\ + ); +\di_reg[2]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5DEE080067FF0100" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => data_pma_rsv_a(15), + I3 => index(1), + I4 => do_reg2(2), + I5 => index(0), + O => \di_reg[2]_i_2__2_n_0\ + ); +\di_reg[2]_i_3__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000380" + ) + port map ( + I0 => do_reg2(2), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[2]_i_3__2_n_0\ + ); +\di_reg[3]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"43FFFFFF40000000" + ) + port map ( + I0 => data_pma_rsv_a(15), + I1 => index(2), + I2 => index(0), + I3 => index(1), + I4 => index(3), + I5 => do_reg2(3), + O => \di_reg[3]_i_2__2_n_0\ + ); +\di_reg[3]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000033D100" + ) + port map ( + I0 => data_pma_rsv_a(15), + I1 => index(0), + I2 => do_reg2(3), + I3 => index(2), + I4 => index(1), + I5 => index(3), + O => \di_reg[3]_i_3__2_n_0\ + ); +\di_reg[4]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \di_reg[4]_i_2__2_n_0\, + I1 => index(4), + I2 => \di_reg[4]_i_3__2_n_0\, + I3 => index(3), + I4 => \di_reg[4]_i_4__2_n_0\, + O => di_reg(4) + ); +\di_reg[4]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0400F0000400F0" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + I2 => index(1), + I3 => index(2), + I4 => index(0), + I5 => do_reg2(4), + O => \di_reg[4]_i_2__2_n_0\ + ); +\di_reg[4]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"400FFFFF40000000" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + I2 => index(2), + I3 => index(0), + I4 => index(1), + I5 => do_reg2(4), + O => \di_reg[4]_i_3__2_n_0\ + ); +\di_reg[4]_i_4__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BF00BF01FF40FE40" + ) + port map ( + I0 => index(2), + I1 => index(1), + I2 => index(0), + I3 => do_reg2(4), + I4 => x16x20_mode_reg2, + I5 => data_pma_rsv_a(15), + O => \di_reg[4]_i_4__2_n_0\ + ); +\di_reg[5]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7F7F7F7E00000000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => x16x20_mode_reg2, + I5 => do_reg2(5), + O => \di_reg[5]_i_2__2_n_0\ + ); +\di_reg[5]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000038F0380" + ) + port map ( + I0 => do_reg2(5), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => data_pma_rsv_a(15), + I5 => index(3), + O => \di_reg[5]_i_3__2_n_0\ + ); +\di_reg[6]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7D7F7D7E00000000" + ) + port map ( + I0 => index(3), + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => x16x20_mode_reg2, + I5 => do_reg2(6), + O => \di_reg[6]_i_2__2_n_0\ + ); +\di_reg[6]_i_3__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000380" + ) + port map ( + I0 => do_reg2(6), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => index(3), + O => \di_reg[6]_i_3__2_n_0\ + ); +\di_reg[7]_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF0900" + ) + port map ( + I0 => index(2), + I1 => index(1), + I2 => index(0), + I3 => index(3), + I4 => do_reg2(7), + O => \di_reg[7]_i_2__2_n_0\ + ); +\di_reg[7]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000003800383" + ) + port map ( + I0 => do_reg2(7), + I1 => index(0), + I2 => index(2), + I3 => index(1), + I4 => data_pma_rsv_a(15), + I5 => index(3), + O => \di_reg[7]_i_3__2_n_0\ + ); +\di_reg[8]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"03333F7300000040" + ) + port map ( + I0 => index(0), + I1 => index(4), + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(8), + O => di_reg(8) + ); +\di_reg[9]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"03333F7300000040" + ) + port map ( + I0 => index(0), + I1 => index(4), + I2 => index(1), + I3 => index(2), + I4 => index(3), + I5 => do_reg2(9), + O => di_reg(9) + ); +\di_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(0), + Q => drp_di_48(0), + R => RST_DCLK_RESET + ); +\di_reg_reg[0]_i_1__2\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[0]_i_2__2_n_0\, + I1 => \di_reg[0]_i_3__2_n_0\, + O => di_reg(0), + S => index(4) + ); +\di_reg_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(10), + Q => drp_di_48(10), + R => RST_DCLK_RESET + ); +\di_reg_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(11), + Q => drp_di_48(11), + R => RST_DCLK_RESET + ); +\di_reg_reg[11]_i_1__2\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[11]_i_2__2_n_0\, + I1 => \di_reg[11]_i_3__2_n_0\, + O => di_reg(11), + S => index(4) + ); +\di_reg_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(12), + Q => drp_di_48(12), + R => RST_DCLK_RESET + ); +\di_reg_reg[12]_i_1__2\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[12]_i_2__2_n_0\, + I1 => \di_reg[12]_i_3__2_n_0\, + O => di_reg(12), + S => index(4) + ); +\di_reg_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(13), + Q => drp_di_48(13), + R => RST_DCLK_RESET + ); +\di_reg_reg[13]_i_1__2\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[13]_i_2__2_n_0\, + I1 => \di_reg[13]_i_3__2_n_0\, + O => di_reg(13), + S => index(4) + ); +\di_reg_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(14), + Q => drp_di_48(14), + R => RST_DCLK_RESET + ); +\di_reg_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(15), + Q => drp_di_48(15), + R => RST_DCLK_RESET + ); +\di_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(1), + Q => drp_di_48(1), + R => RST_DCLK_RESET + ); +\di_reg_reg[1]_i_1__2\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[1]_i_2__2_n_0\, + I1 => \di_reg[1]_i_3__2_n_0\, + O => di_reg(1), + S => index(4) + ); +\di_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(2), + Q => drp_di_48(2), + R => RST_DCLK_RESET + ); +\di_reg_reg[2]_i_1__2\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[2]_i_2__2_n_0\, + I1 => \di_reg[2]_i_3__2_n_0\, + O => di_reg(2), + S => index(4) + ); +\di_reg_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(3), + Q => drp_di_48(3), + R => RST_DCLK_RESET + ); +\di_reg_reg[3]_i_1__2\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[3]_i_2__2_n_0\, + I1 => \di_reg[3]_i_3__2_n_0\, + O => di_reg(3), + S => index(4) + ); +\di_reg_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(4), + Q => drp_di_48(4), + R => RST_DCLK_RESET + ); +\di_reg_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(5), + Q => drp_di_48(5), + R => RST_DCLK_RESET + ); +\di_reg_reg[5]_i_1__2\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[5]_i_2__2_n_0\, + I1 => \di_reg[5]_i_3__2_n_0\, + O => di_reg(5), + S => index(4) + ); +\di_reg_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(6), + Q => drp_di_48(6), + R => RST_DCLK_RESET + ); +\di_reg_reg[6]_i_1__2\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[6]_i_2__2_n_0\, + I1 => \di_reg[6]_i_3__2_n_0\, + O => di_reg(6), + S => index(4) + ); +\di_reg_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(7), + Q => drp_di_48(7), + R => RST_DCLK_RESET + ); +\di_reg_reg[7]_i_1__2\: unisim.vcomponents.MUXF7 + port map ( + I0 => \di_reg[7]_i_2__2_n_0\, + I1 => \di_reg[7]_i_3__2_n_0\, + O => di_reg(7), + S => index(4) + ); +\di_reg_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(8), + Q => drp_di_48(8), + R => RST_DCLK_RESET + ); +\di_reg_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di_reg(9), + Q => drp_di_48(9), + R => RST_DCLK_RESET + ); +\do_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(0), + Q => do_reg1(0), + R => RST_DCLK_RESET + ); +\do_reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(10), + Q => do_reg1(10), + R => RST_DCLK_RESET + ); +\do_reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(11), + Q => do_reg1(11), + R => RST_DCLK_RESET + ); +\do_reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(12), + Q => do_reg1(12), + R => RST_DCLK_RESET + ); +\do_reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(13), + Q => do_reg1(13), + R => RST_DCLK_RESET + ); +\do_reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(14), + Q => do_reg1(14), + R => RST_DCLK_RESET + ); +\do_reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(15), + Q => do_reg1(15), + R => RST_DCLK_RESET + ); +\do_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(1), + Q => do_reg1(1), + R => RST_DCLK_RESET + ); +\do_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(2), + Q => do_reg1(2), + R => RST_DCLK_RESET + ); +\do_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(3), + Q => do_reg1(3), + R => RST_DCLK_RESET + ); +\do_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(4), + Q => do_reg1(4), + R => RST_DCLK_RESET + ); +\do_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(5), + Q => do_reg1(5), + R => RST_DCLK_RESET + ); +\do_reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(6), + Q => do_reg1(6), + R => RST_DCLK_RESET + ); +\do_reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(7), + Q => do_reg1(7), + R => RST_DCLK_RESET + ); +\do_reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(8), + Q => do_reg1(8), + R => RST_DCLK_RESET + ); +\do_reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(9), + Q => do_reg1(9), + R => RST_DCLK_RESET + ); +\do_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(0), + Q => do_reg2(0), + R => RST_DCLK_RESET + ); +\do_reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(10), + Q => do_reg2(10), + R => RST_DCLK_RESET + ); +\do_reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(11), + Q => do_reg2(11), + R => RST_DCLK_RESET + ); +\do_reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(12), + Q => do_reg2(12), + R => RST_DCLK_RESET + ); +\do_reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(13), + Q => do_reg2(13), + R => RST_DCLK_RESET + ); +\do_reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(14), + Q => do_reg2(14), + R => RST_DCLK_RESET + ); +\do_reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(15), + Q => do_reg2(15), + R => RST_DCLK_RESET + ); +\do_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(1), + Q => do_reg2(1), + R => RST_DCLK_RESET + ); +\do_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(2), + Q => do_reg2(2), + R => RST_DCLK_RESET + ); +\do_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(3), + Q => do_reg2(3), + R => RST_DCLK_RESET + ); +\do_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(4), + Q => do_reg2(4), + R => RST_DCLK_RESET + ); +\do_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(5), + Q => do_reg2(5), + R => RST_DCLK_RESET + ); +\do_reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(6), + Q => do_reg2(6), + R => RST_DCLK_RESET + ); +\do_reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(7), + Q => do_reg2(7), + R => RST_DCLK_RESET + ); +\do_reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(8), + Q => do_reg2(8), + R => RST_DCLK_RESET + ); +\do_reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(9), + Q => do_reg2(9), + R => RST_DCLK_RESET + ); +\done_i_1__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => start_reg2, + I3 => \fsm_reg_n_0_[1]\, + O => \done_i_1__3_n_0\ + ); +done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \done_i_1__3_n_0\, + Q => DRP_DONE, + R => RST_DCLK_RESET + ); +\fsm[0]_i_1__7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0737FFFF07370000" + ) + port map ( + I0 => fsm1, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => rdy_reg2, + I4 => \fsm_reg_n_0_[2]\, + I5 => \fsm[0]_i_2__7_n_0\, + O => fsm(0) + ); +\fsm[0]_i_2__7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"47FF47CC" + ) + port map ( + I0 => rdy_reg2, + I1 => \fsm_reg_n_0_[1]\, + I2 => load_cnt(0), + I3 => \fsm_reg_n_0_[0]\, + I4 => start_reg2, + O => \fsm[0]_i_2__7_n_0\ + ); +\fsm[1]_i_1__7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"1D501850" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => rdy_reg2, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => load_cnt(0), + O => fsm(1) + ); +\fsm[2]_i_1__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6222" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => rdy_reg2, + O => fsm(2) + ); +\fsm_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => fsm(0), + Q => \fsm_reg_n_0_[0]\, + R => RST_DCLK_RESET + ); +\fsm_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => fsm(1), + Q => \fsm_reg_n_0_[1]\, + R => RST_DCLK_RESET + ); +\fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => fsm(2), + Q => \fsm_reg_n_0_[2]\, + R => RST_DCLK_RESET + ); +\gtx_channel.gtxe2_channel_i_i_10__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(12), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(12) + ); +\gtx_channel.gtxe2_channel_i_i_11__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(11), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(11) + ); +\gtx_channel.gtxe2_channel_i_i_12__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(10), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(10) + ); +\gtx_channel.gtxe2_channel_i_i_13__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(9), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(9) + ); +\gtx_channel.gtxe2_channel_i_i_14__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(8), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(8) + ); +\gtx_channel.gtxe2_channel_i_i_15__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(7), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(7) + ); +\gtx_channel.gtxe2_channel_i_i_16__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(6), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(6) + ); +\gtx_channel.gtxe2_channel_i_i_17__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(5), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(5) + ); +\gtx_channel.gtxe2_channel_i_i_18__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(4), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(4) + ); +\gtx_channel.gtxe2_channel_i_i_19__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(3), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(3) + ); +\gtx_channel.gtxe2_channel_i_i_20__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(2), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(2) + ); +\gtx_channel.gtxe2_channel_i_i_21__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(1), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(1) + ); +\gtx_channel.gtxe2_channel_i_i_22__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(0), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(0) + ); +\gtx_channel.gtxe2_channel_i_i_3__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"12" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \fsm_reg[1]_0\ + ); +\gtx_channel.gtxe2_channel_i_i_40__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_27(7), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(7) + ); +\gtx_channel.gtxe2_channel_i_i_41__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_27(6), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(6) + ); +\gtx_channel.gtxe2_channel_i_i_42__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_27(5), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(5) + ); +\gtx_channel.gtxe2_channel_i_i_43__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_27(4), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(4) + ); +\gtx_channel.gtxe2_channel_i_i_44__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_27(3), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(3) + ); +\gtx_channel.gtxe2_channel_i_i_45__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_27(2), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(2) + ); +\gtx_channel.gtxe2_channel_i_i_46__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_27(1), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(1) + ); +\gtx_channel.gtxe2_channel_i_i_47\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_addr_27(0), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPADDR(0) + ); +\gtx_channel.gtxe2_channel_i_i_4__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"10" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \fsm_reg[1]_1\ + ); +\gtx_channel.gtxe2_channel_i_i_7__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(15), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(15) + ); +\gtx_channel.gtxe2_channel_i_i_8__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(14), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(14) + ); +\gtx_channel.gtxe2_channel_i_i_9__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => drp_di_48(13), + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + O => DRPDI(13) + ); +gtxreset_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => DRP_GTXRESET, + Q => gtxreset_reg1, + R => RST_DCLK_RESET + ); +gtxreset_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => gtxreset_reg1, + Q => gtxreset_reg2, + R => RST_DCLK_RESET + ); +\index[0]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0100" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => fsm1, + I2 => index(0), + I3 => \fsm_reg_n_0_[2]\, + O => \index[0]_i_1__2_n_0\ + ); +\index[1]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00140000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(1), + I2 => index(0), + I3 => fsm1, + I4 => \fsm_reg_n_0_[2]\, + O => \index[1]_i_1__2_n_0\ + ); +\index[2]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000144400000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(2), + I2 => index(1), + I3 => index(0), + I4 => fsm1, + I5 => \fsm_reg_n_0_[2]\, + O => \index[2]_i_1__2_n_0\ + ); +\index[3]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000144400000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(3), + I2 => index(2), + I3 => \index[3]_i_2__2_n_0\, + I4 => fsm1, + I5 => \fsm_reg_n_0_[2]\, + O => \index[3]_i_1__2_n_0\ + ); +\index[3]_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => index(1), + I1 => index(0), + O => \index[3]_i_2__2_n_0\ + ); +\index[4]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A1" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \index[4]_i_1__2_n_0\ + ); +\index[4]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000144400000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => index(4), + I2 => index(3), + I3 => \index[4]_i_3__2_n_0\, + I4 => fsm1, + I5 => \fsm_reg_n_0_[2]\, + O => \index[4]_i_2__2_n_0\ + ); +\index[4]_i_3__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => index(2), + I1 => index(0), + I2 => index(1), + O => \index[4]_i_3__2_n_0\ + ); +\index[4]_i_4__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000000110000000" + ) + port map ( + I0 => index(3), + I1 => index(1), + I2 => index(0), + I3 => index(4), + I4 => index(2), + I5 => x16x20_mode_reg2, + O => fsm1 + ); +\index_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__2_n_0\, + D => \index[0]_i_1__2_n_0\, + Q => index(0), + R => RST_DCLK_RESET + ); +\index_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__2_n_0\, + D => \index[1]_i_1__2_n_0\, + Q => index(1), + R => RST_DCLK_RESET + ); +\index_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__2_n_0\, + D => \index[2]_i_1__2_n_0\, + Q => index(2), + R => RST_DCLK_RESET + ); +\index_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__2_n_0\, + D => \index[3]_i_1__2_n_0\, + Q => index(3), + R => RST_DCLK_RESET + ); +\index_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => \index[4]_i_1__2_n_0\, + D => \index[4]_i_2__2_n_0\, + Q => index(4), + R => RST_DCLK_RESET + ); +\load_cnt[0]_i_1__3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"10" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + O => \load_cnt[0]_i_1__3_n_0\ + ); +\load_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \load_cnt[0]_i_1__3_n_0\, + Q => load_cnt(0), + R => RST_DCLK_RESET + ); +\rate_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => \rate_reg1_reg[0]_0\(0), + Q => rate_reg1(0), + R => RST_DCLK_RESET + ); +\rate_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => '0', + Q => rate_reg1(1), + R => RST_DCLK_RESET + ); +\rate_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => rate_reg1(0), + Q => rate_reg2(0), + R => RST_DCLK_RESET + ); +\rate_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => rate_reg1(1), + Q => rate_reg2(1), + R => RST_DCLK_RESET + ); +rdy_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => DRP_RDY, + Q => rdy_reg1, + R => RST_DCLK_RESET + ); +rdy_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => rdy_reg1, + Q => rdy_reg2, + R => RST_DCLK_RESET + ); +start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => RATE_DRP_START, + Q => start_reg1, + R => RST_DCLK_RESET + ); +start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => start_reg1, + Q => start_reg2, + R => RST_DCLK_RESET + ); +x16_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => RATE_DRP_X16, + Q => x16_reg1, + R => RST_DCLK_RESET + ); +x16_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => x16_reg1, + Q => x16_reg2, + R => RST_DCLK_RESET + ); +x16x20_mode_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => RATE_DRP_X16X20_MODE, + Q => x16x20_mode_reg1, + R => RST_DCLK_RESET + ); +x16x20_mode_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => x16x20_mode_reg1, + Q => x16x20_mode_reg2, + R => RST_DCLK_RESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_rate is + port ( + SYNC_TXSYNC_START : out STD_LOGIC; + rxchbonden_0 : out STD_LOGIC; + USER_RATE_GEN3 : out STD_LOGIC; + RATE_DRP_START : out STD_LOGIC; + RATE_DRP_X16X20_MODE : out STD_LOGIC; + RATE_DRP_X16 : out STD_LOGIC; + USER_RATE_RXSYNC : out STD_LOGIC; + SYNC_RXSYNC_START : out STD_LOGIC; + USER_RATE_DONE : out STD_LOGIC; + USER_RESETOVRD_START : out STD_LOGIC; + SYNC_RATE_IDLE : out STD_LOGIC; + rate_txpmareset_0 : out STD_LOGIC; + RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 0 to 0 ); + RXRATE : out STD_LOGIC_VECTOR ( 0 to 0 ); + QRST_QPLLPD_IN : out STD_LOGIC_VECTOR ( 0 to 0 ); + rate_cpllpd_0 : out STD_LOGIC; + QRST_QPLLRESET_IN : out STD_LOGIC_VECTOR ( 0 to 0 ); + rate_cpllreset_0 : out STD_LOGIC; + RST_TXSYNC_START : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + \rate_in_reg1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RST_IDLE : in STD_LOGIC; + QRST_CPLLLOCK : in STD_LOGIC_VECTOR ( 0 to 0 ); + RATE_QPLLLOCK : in STD_LOGIC; + RATE_DRP_DONE : in STD_LOGIC; + pipe_mmcm_lock_in : in STD_LOGIC; + RATE_PHYSTATUS : in STD_LOGIC; + USER_TXRESETDONE : in STD_LOGIC; + USER_RXRESETDONE : in STD_LOGIC; + RATE_TXRATEDONE : in STD_LOGIC; + RATE_RXRATEDONE : in STD_LOGIC; + RATE_TXSYNC_DONE : in STD_LOGIC; + user_active_lane_0 : in STD_LOGIC; + \out\ : in STD_LOGIC; + \fsm[0]_i_9_0\ : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_pipe_rate; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_rate is + signal \^qrst_qpllpd_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^qrst_qpllreset_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^rxrate\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^user_rate_gen3\ : STD_LOGIC; + signal cplllock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of cplllock_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of cplllock_reg1 : signal is "true"; + signal cplllock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of cplllock_reg2 : signal is "NO"; + attribute async_reg of cplllock_reg2 : signal is "true"; + signal cpllpd_i_1_n_0 : STD_LOGIC; + signal \cpllreset_i_1__0_n_0\ : STD_LOGIC; + signal drp_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO"; + attribute async_reg of drp_done_reg1 : signal is "true"; + signal drp_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO"; + attribute async_reg of drp_done_reg2 : signal is "true"; + signal drp_start_i_1_n_0 : STD_LOGIC; + signal drp_x16_i_1_n_0 : STD_LOGIC; + signal drp_x16x20_mode_i_1_n_0 : STD_LOGIC; + signal fsm : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal fsm1 : STD_LOGIC; + signal \fsm[0]_i_10_n_0\ : STD_LOGIC; + signal \fsm[0]_i_11_n_0\ : STD_LOGIC; + signal \fsm[0]_i_12_n_0\ : STD_LOGIC; + signal \fsm[0]_i_2_n_0\ : STD_LOGIC; + signal \fsm[0]_i_3_n_0\ : STD_LOGIC; + signal \fsm[0]_i_4_n_0\ : STD_LOGIC; + signal \fsm[0]_i_5_n_0\ : STD_LOGIC; + signal \fsm[0]_i_7_n_0\ : STD_LOGIC; + signal \fsm[0]_i_8_n_0\ : STD_LOGIC; + signal \fsm[0]_i_9_n_0\ : STD_LOGIC; + signal \fsm[1]_i_2_n_0\ : STD_LOGIC; + signal \fsm[1]_i_3_n_0\ : STD_LOGIC; + signal \fsm[1]_i_4_n_0\ : STD_LOGIC; + signal \fsm[1]_i_5_n_0\ : STD_LOGIC; + signal \fsm[1]_i_6_n_0\ : STD_LOGIC; + signal \fsm[1]_i_7_n_0\ : STD_LOGIC; + signal \fsm[1]_i_8_n_0\ : STD_LOGIC; + signal \fsm[2]_i_2_n_0\ : STD_LOGIC; + signal \fsm[2]_i_3_n_0\ : STD_LOGIC; + signal \fsm[2]_i_4_n_0\ : STD_LOGIC; + signal \fsm[2]_i_5_n_0\ : STD_LOGIC; + signal \fsm[2]_i_6_n_0\ : STD_LOGIC; + signal \fsm[3]_i_2_n_0\ : STD_LOGIC; + signal \fsm[3]_i_3_n_0\ : STD_LOGIC; + signal \fsm[3]_i_4_n_0\ : STD_LOGIC; + signal \fsm[3]_i_6_n_0\ : STD_LOGIC; + signal \fsm[4]_i_2_n_0\ : STD_LOGIC; + signal \fsm[4]_i_3_n_0\ : STD_LOGIC; + signal \fsm_reg_n_0_[0]\ : STD_LOGIC; + signal \fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \fsm_reg_n_0_[2]\ : STD_LOGIC; + signal \fsm_reg_n_0_[3]\ : STD_LOGIC; + signal \fsm_reg_n_0_[4]\ : STD_LOGIC; + signal gen3_exit : STD_LOGIC; + signal gen3_exit_i_1_n_0 : STD_LOGIC; + signal gen3_exit_i_2_n_0 : STD_LOGIC; + signal gen3_i_1_n_0 : STD_LOGIC; + signal gen3_i_2_n_0 : STD_LOGIC; + signal gen3_i_3_n_0 : STD_LOGIC; + signal mmcm_lock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO"; + attribute async_reg of mmcm_lock_reg1 : signal is "true"; + signal mmcm_lock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO"; + attribute async_reg of mmcm_lock_reg2 : signal is "true"; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal pclk_sel_i_1_n_0 : STD_LOGIC; + signal pclk_sel_i_2_n_0 : STD_LOGIC; + signal phystatus : STD_LOGIC; + signal phystatus_i_1_n_0 : STD_LOGIC; + signal phystatus_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of phystatus_reg1 : signal is "NO"; + attribute async_reg of phystatus_reg1 : signal is "true"; + signal phystatus_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of phystatus_reg2 : signal is "NO"; + attribute async_reg of phystatus_reg2 : signal is "true"; + signal \^pipe_pclk_sel_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal pll_lock : STD_LOGIC; + signal qplllock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of qplllock_reg1 : signal is "NO"; + attribute async_reg of qplllock_reg1 : signal is "true"; + signal qplllock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of qplllock_reg2 : signal is "NO"; + attribute async_reg of qplllock_reg2 : signal is "true"; + signal qpllpd : STD_LOGIC; + signal \qpllpd_i_1__0_n_0\ : STD_LOGIC; + signal qpllreset : STD_LOGIC; + signal \qpllreset_i_1__0_n_0\ : STD_LOGIC; + signal \^rate_cpllpd_0\ : STD_LOGIC; + signal \^rate_cpllreset_0\ : STD_LOGIC; + signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_in_reg1 : signal is "NO"; + attribute async_reg of rate_in_reg1 : signal is "true"; + signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_in_reg2 : signal is "NO"; + attribute async_reg of rate_in_reg2 : signal is "true"; + signal \rate_out[0]_i_1_n_0\ : STD_LOGIC; + signal \rate_out[0]_i_2_n_0\ : STD_LOGIC; + signal \^rate_txpmareset_0\ : STD_LOGIC; + signal ratedone : STD_LOGIC; + signal ratedone_i_1_n_0 : STD_LOGIC; + signal ratedone_i_2_n_0 : STD_LOGIC; + signal ratedone_i_3_n_0 : STD_LOGIC; + signal resetovrd_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_done_reg1 : signal is "NO"; + attribute async_reg of resetovrd_done_reg1 : signal is "true"; + signal resetovrd_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_done_reg2 : signal is "NO"; + attribute async_reg of resetovrd_done_reg2 : signal is "true"; + signal rst_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO"; + attribute async_reg of rst_idle_reg1 : signal is "true"; + signal rst_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO"; + attribute async_reg of rst_idle_reg2 : signal is "true"; + signal rxpmaresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg1 : signal is "NO"; + attribute async_reg of rxpmaresetdone_reg1 : signal is "true"; + signal rxpmaresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg2 : signal is "NO"; + attribute async_reg of rxpmaresetdone_reg2 : signal is "true"; + signal rxratedone : STD_LOGIC; + signal rxratedone_i_1_n_0 : STD_LOGIC; + signal rxratedone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxratedone_reg1 : signal is "NO"; + attribute async_reg of rxratedone_reg1 : signal is "true"; + signal rxratedone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxratedone_reg2 : signal is "NO"; + attribute async_reg of rxratedone_reg2 : signal is "true"; + signal rxresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO"; + attribute async_reg of rxresetdone_reg1 : signal is "true"; + signal rxresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO"; + attribute async_reg of rxresetdone_reg2 : signal is "true"; + signal rxsync_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_done_reg1 : signal is "NO"; + attribute async_reg of rxsync_done_reg1 : signal is "true"; + signal rxsync_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_done_reg2 : signal is "NO"; + attribute async_reg of rxsync_done_reg2 : signal is "true"; + signal \sysclksel[0]_i_1_n_0\ : STD_LOGIC; + signal \sysclksel[0]_i_2_n_0\ : STD_LOGIC; + signal \txdata_wait_cnt[3]_i_2_n_0\ : STD_LOGIC; + signal \txdata_wait_cnt[3]_i_3_n_0\ : STD_LOGIC; + signal txdata_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal txpmareset0 : STD_LOGIC; + signal txpmareset_i_1_n_0 : STD_LOGIC; + signal txpmareset_i_2_n_0 : STD_LOGIC; + signal txratedone : STD_LOGIC; + signal txratedone_i_1_n_0 : STD_LOGIC; + signal txratedone_i_2_n_0 : STD_LOGIC; + signal txratedone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txratedone_reg1 : signal is "NO"; + attribute async_reg of txratedone_reg1 : signal is "true"; + signal txratedone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txratedone_reg2 : signal is "NO"; + attribute async_reg of txratedone_reg2 : signal is "true"; + signal txresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO"; + attribute async_reg of txresetdone_reg1 : signal is "true"; + signal txresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO"; + attribute async_reg of txresetdone_reg2 : signal is "true"; + signal txsync_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_done_reg1 : signal is "NO"; + attribute async_reg of txsync_done_reg1 : signal is "true"; + signal txsync_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_done_reg2 : signal is "NO"; + attribute async_reg of txsync_done_reg2 : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of cplllock_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of cplllock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of cplllock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of cplllock_reg2_reg : label is std.standard.true; + attribute KEEP of cplllock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of cplllock_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of cpllpd_i_2 : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of \cpllreset_i_2__0\ : label is "soft_lutpair71"; + attribute ASYNC_REG_boolean of drp_done_reg1_reg : label is std.standard.true; + attribute KEEP of drp_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of drp_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of drp_done_reg2_reg : label is std.standard.true; + attribute KEEP of drp_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of drp_done_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of drp_start_i_1 : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of drp_x16_i_1 : label is "soft_lutpair75"; + attribute SOFT_HLUTNM of drp_x16x20_mode_i_1 : label is "soft_lutpair76"; + attribute SOFT_HLUTNM of \fsm[0]_i_1\ : label is "soft_lutpair69"; + attribute SOFT_HLUTNM of \fsm[4]_i_3\ : label is "soft_lutpair78"; + attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of pclk_sel_i_2 : label is "soft_lutpair70"; + attribute ASYNC_REG_boolean of phystatus_reg1_reg : label is std.standard.true; + attribute KEEP of phystatus_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of phystatus_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of phystatus_reg2_reg : label is std.standard.true; + attribute KEEP of phystatus_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of phystatus_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of qplllock_reg1_reg : label is std.standard.true; + attribute KEEP of qplllock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of qplllock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of qplllock_reg2_reg : label is std.standard.true; + attribute KEEP of qplllock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of qplllock_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of rate_done_reg1_i_1 : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of \rate_idle_reg1[0]_i_1\ : label is "soft_lutpair76"; + attribute ASYNC_REG_boolean of \rate_in_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_in_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_in_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_in_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg2_reg[1]\ : label is "NO"; + attribute SOFT_HLUTNM of rate_rxsync_reg1_i_1 : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of ratedone_i_2 : label is "soft_lutpair72"; + attribute SOFT_HLUTNM of ratedone_i_3 : label is "soft_lutpair72"; + attribute ASYNC_REG_boolean of resetovrd_done_reg1_reg : label is std.standard.true; + attribute KEEP of resetovrd_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of resetovrd_done_reg2_reg : label is std.standard.true; + attribute KEEP of resetovrd_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_done_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of resetovrd_start_reg1_i_1 : label is "soft_lutpair75"; + attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxpmaresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxpmaresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxratedone_reg1_reg : label is std.standard.true; + attribute KEEP of rxratedone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxratedone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxratedone_reg2_reg : label is std.standard.true; + attribute KEEP of rxratedone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxratedone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_done_reg1_reg : label is std.standard.true; + attribute KEEP of rxsync_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_done_reg2_reg : label is std.standard.true; + attribute KEEP of rxsync_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_done_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of rxsync_start_reg1_i_1 : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of \sysclksel[0]_i_2\ : label is "soft_lutpair77"; + attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_2\ : label is "soft_lutpair77"; + attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_3\ : label is "soft_lutpair69"; + attribute SOFT_HLUTNM of txpmareset_i_2 : label is "soft_lutpair71"; + attribute SOFT_HLUTNM of txratedone_i_2 : label is "soft_lutpair78"; + attribute ASYNC_REG_boolean of txratedone_reg1_reg : label is std.standard.true; + attribute KEEP of txratedone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txratedone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txratedone_reg2_reg : label is std.standard.true; + attribute KEEP of txratedone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txratedone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_done_reg1_reg : label is std.standard.true; + attribute KEEP of txsync_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_done_reg2_reg : label is std.standard.true; + attribute KEEP of txsync_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_done_reg2_reg : label is "NO"; +begin + QRST_QPLLPD_IN(0) <= \^qrst_qpllpd_in\(0); + QRST_QPLLRESET_IN(0) <= \^qrst_qpllreset_in\(0); + RXRATE(0) <= \^rxrate\(0); + RXSYSCLKSEL(0) <= \^rxsysclksel\(0); + USER_RATE_GEN3 <= \^user_rate_gen3\; + pipe_pclk_sel_out(0) <= \^pipe_pclk_sel_out\(0); + rate_cpllpd_0 <= \^rate_cpllpd_0\; + rate_cpllreset_0 <= \^rate_cpllreset_0\; + rate_txpmareset_0 <= \^rate_txpmareset_0\; +cplllock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => QRST_CPLLLOCK(0), + Q => cplllock_reg1, + R => RST_CPLLRESET + ); +cplllock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => cplllock_reg1, + Q => cplllock_reg2, + R => RST_CPLLRESET + ); +cpllpd_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0400FFFF04000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllpd, + I5 => \^rate_cpllpd_0\, + O => cpllpd_i_1_n_0 + ); +cpllpd_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000900" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[2]\, + O => qpllpd + ); +cpllpd_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => cpllpd_i_1_n_0, + Q => \^rate_cpllpd_0\, + R => RST_CPLLRESET + ); +\cpllreset_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0400FFFF04000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllreset, + I5 => \^rate_cpllreset_0\, + O => \cpllreset_i_1__0_n_0\ + ); +\cpllreset_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80001004" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm_reg_n_0_[0]\, + O => qpllreset + ); +cpllreset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \cpllreset_i_1__0_n_0\, + Q => \^rate_cpllreset_0\, + R => RST_CPLLRESET + ); +drp_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_DRP_DONE, + Q => drp_done_reg1, + R => RST_CPLLRESET + ); +drp_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => drp_done_reg1, + Q => drp_done_reg2, + R => RST_CPLLRESET + ); +drp_start_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"08420100" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[0]\, + O => drp_start_i_1_n_0 + ); +drp_start_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => drp_start_i_1_n_0, + Q => RATE_DRP_START, + R => RST_CPLLRESET + ); +drp_x16_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"20100014" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + O => drp_x16_i_1_n_0 + ); +drp_x16_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => drp_x16_i_1_n_0, + Q => RATE_DRP_X16, + R => RST_CPLLRESET + ); +drp_x16x20_mode_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"20080074" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[1]\, + O => drp_x16x20_mode_i_1_n_0 + ); +drp_x16x20_mode_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => drp_x16x20_mode_i_1_n_0, + Q => RATE_DRP_X16X20_MODE, + R => RST_CPLLRESET + ); +\fsm[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF3210" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm[0]_i_2_n_0\, + I3 => \fsm[0]_i_3_n_0\, + I4 => \fsm[0]_i_4_n_0\, + O => fsm(0) + ); +\fsm[0]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0901595100000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => rxsync_done_reg2, + I4 => txsync_done_reg2, + I5 => \fsm_reg_n_0_[3]\, + O => \fsm[0]_i_10_n_0\ + ); +\fsm[0]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1101111101000110" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => rxpmaresetdone_reg2, + I5 => drp_done_reg2, + O => \fsm[0]_i_11_n_0\ + ); +\fsm[0]_i_12\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20202320" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => mmcm_lock_reg2, + I4 => rxpmaresetdone_reg2, + O => \fsm[0]_i_12_n_0\ + ); +\fsm[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0F3F3F47444744" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm[0]_i_5_n_0\, + I4 => pll_lock, + I5 => \fsm_reg_n_0_[1]\, + O => \fsm[0]_i_2_n_0\ + ); +\fsm[0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F3F3AAAAFF00AAAA" + ) + port map ( + I0 => \fsm[0]_i_7_n_0\, + I1 => \fsm_reg_n_0_[0]\, + I2 => drp_done_reg2, + I3 => \fsm[0]_i_8_n_0\, + I4 => \fsm_reg_n_0_[2]\, + I5 => \fsm_reg_n_0_[1]\, + O => \fsm[0]_i_3_n_0\ + ); +\fsm[0]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFF4000000000" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm[0]_i_9_n_0\, + I3 => \fsm[0]_i_10_n_0\, + I4 => \fsm[0]_i_11_n_0\, + I5 => \fsm_reg_n_0_[4]\, + O => \fsm[0]_i_4_n_0\ + ); +\fsm[0]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg1(1), + I2 => rate_in_reg2(0), + I3 => rate_in_reg1(0), + O => \fsm[0]_i_5_n_0\ + ); +\fsm[0]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => qplllock_reg2, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => cplllock_reg2, + O => pll_lock + ); +\fsm[0]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAEAAAAAAA" + ) + port map ( + I0 => \fsm[0]_i_12_n_0\, + I1 => pll_lock, + I2 => rst_idle_reg2, + I3 => drp_done_reg2, + I4 => \fsm_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[0]\, + O => \fsm[0]_i_7_n_0\ + ); +\fsm[0]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF5D5500005D55" + ) + port map ( + I0 => user_active_lane_0, + I1 => txresetdone_reg2, + I2 => phystatus_reg2, + I3 => rxresetdone_reg2, + I4 => \fsm_reg_n_0_[0]\, + I5 => \fsm[1]_i_7_n_0\, + O => \fsm[0]_i_8_n_0\ + ); +\fsm[0]_i_9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"33330FAA" + ) + port map ( + I0 => drp_done_reg2, + I1 => resetovrd_done_reg2, + I2 => fsm1, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[1]\, + O => \fsm[0]_i_9_n_0\ + ); +\fsm[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFE4FFE4FFE400E4" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm[1]_i_2_n_0\, + I2 => \fsm[1]_i_3_n_0\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm[1]_i_4_n_0\, + I5 => \fsm[1]_i_5_n_0\, + O => fsm(1) + ); +\fsm[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"3388F0CC" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm[1]_i_6_n_0\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[2]\, + O => \fsm[1]_i_2_n_0\ + ); +\fsm[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CC5500000033F000" + ) + port map ( + I0 => \fsm[1]_i_7_n_0\, + I1 => drp_done_reg2, + I2 => \fsm[1]_i_8_n_0\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[1]_i_3_n_0\ + ); +\fsm[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000005FCF0000" + ) + port map ( + I0 => resetovrd_done_reg2, + I1 => drp_done_reg2, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[3]\, + O => \fsm[1]_i_4_n_0\ + ); +\fsm[1]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"143C547C00000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => rxsync_done_reg2, + I4 => txsync_done_reg2, + I5 => \fsm_reg_n_0_[3]\, + O => \fsm[1]_i_5_n_0\ + ); +\fsm[1]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"34F7FFFFFFFFFFFF" + ) + port map ( + I0 => qplllock_reg2, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => cplllock_reg2, + I4 => rst_idle_reg2, + I5 => \fsm_reg_n_0_[0]\, + O => \fsm[1]_i_6_n_0\ + ); +\fsm[1]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => txdata_wait_cnt_reg(3), + I1 => txdata_wait_cnt_reg(1), + I2 => txdata_wait_cnt_reg(0), + I3 => txdata_wait_cnt_reg(2), + O => \fsm[1]_i_7_n_0\ + ); +\fsm[1]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF04F7FFFF" + ) + port map ( + I0 => qplllock_reg2, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => cplllock_reg2, + I4 => drp_done_reg2, + I5 => rst_idle_reg2, + O => \fsm[1]_i_8_n_0\ + ); +\fsm[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAFFAAAAAAAAAAAA" + ) + port map ( + I0 => \fsm[2]_i_4_n_0\, + I1 => drp_done_reg2, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[2]_i_2_n_0\ + ); +\fsm[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFBAAAAAAAAAAAAA" + ) + port map ( + I0 => \fsm[2]_i_5_n_0\, + I1 => rxsync_done_reg2, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[2]_i_3_n_0\ + ); +\fsm[2]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FA554455005544" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm[3]_i_6_n_0\, + I2 => pll_lock, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[0]\, + O => \fsm[2]_i_4_n_0\ + ); +\fsm[2]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2000FFFF20000000" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => txsync_done_reg2, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm[2]_i_6_n_0\, + O => \fsm[2]_i_5_n_0\ + ); +\fsm[2]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1CDC3C3C1CDCFCFC" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => resetovrd_done_reg2, + I4 => \fsm_reg_n_0_[1]\, + I5 => fsm1, + O => \fsm[2]_i_6_n_0\ + ); +\fsm[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFB0803080" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => drp_done_reg2, + I5 => \fsm[3]_i_4_n_0\, + O => \fsm[3]_i_2_n_0\ + ); +\fsm[3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF8880000F888" + ) + port map ( + I0 => \txdata_wait_cnt[3]_i_2_n_0\, + I1 => fsm1, + I2 => resetovrd_done_reg2, + I3 => \sysclksel[0]_i_2_n_0\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm[4]_i_2_n_0\, + O => \fsm[3]_i_3_n_0\ + ); +\fsm[3]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EEFF00F0" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm[1]_i_8_n_0\, + I2 => \fsm[3]_i_6_n_0\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[3]_i_4_n_0\ + ); +\fsm[3]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF8F8FFF8" + ) + port map ( + I0 => \out\, + I1 => \fsm[0]_i_9_0\, + I2 => ratedone, + I3 => rate_in_reg2(1), + I4 => rate_in_reg2(0), + I5 => gen3_exit, + O => fsm1 + ); +\fsm[3]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00504414" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => rate_in_reg1(0), + I2 => rate_in_reg2(0), + I3 => rate_in_reg1(1), + I4 => rate_in_reg2(1), + O => \fsm[3]_i_6_n_0\ + ); +\fsm[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C5F0CFF0C0F0C0F0" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm[4]_i_2_n_0\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => drp_done_reg2, + I5 => \fsm[4]_i_3_n_0\, + O => fsm(4) + ); +\fsm[4]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"26FF" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => rxsync_done_reg2, + I3 => \fsm_reg_n_0_[2]\, + O => \fsm[4]_i_2_n_0\ + ); +\fsm[4]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[2]\, + O => \fsm[4]_i_3_n_0\ + ); +\fsm_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(0), + Q => \fsm_reg_n_0_[0]\, + S => RST_CPLLRESET + ); +\fsm_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(1), + Q => \fsm_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(2), + Q => \fsm_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\fsm_reg[2]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \fsm[2]_i_2_n_0\, + I1 => \fsm[2]_i_3_n_0\, + O => fsm(2), + S => \fsm_reg_n_0_[4]\ + ); +\fsm_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(3), + Q => \fsm_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\fsm_reg[3]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \fsm[3]_i_2_n_0\, + I1 => \fsm[3]_i_3_n_0\, + O => fsm(3), + S => \fsm_reg_n_0_[4]\ + ); +\fsm_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(4), + Q => \fsm_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +gen3_exit_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"04FF0400" + ) + port map ( + I0 => rate_in_reg2(0), + I1 => rate_in_reg2(1), + I2 => \fsm_reg_n_0_[4]\, + I3 => gen3_exit_i_2_n_0, + I4 => gen3_exit, + O => gen3_exit_i_1_n_0 + ); +gen3_exit_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000180000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[4]\, + I5 => \fsm[0]_i_5_n_0\, + O => gen3_exit_i_2_n_0 + ); +gen3_exit_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => gen3_exit_i_1_n_0, + Q => gen3_exit, + R => RST_CPLLRESET + ); +gen3_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"3FFFFFFB00000008" + ) + port map ( + I0 => gen3_i_2_n_0, + I1 => gen3_i_3_n_0, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[4]\, + I5 => \^user_rate_gen3\, + O => gen3_i_1_n_0 + ); +gen3_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg2(0), + O => gen3_i_2_n_0 + ); +gen3_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[0]\, + O => gen3_i_3_n_0 + ); +gen3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => gen3_i_1_n_0, + Q => \^user_rate_gen3\, + R => RST_CPLLRESET + ); +\gtx_channel.gtxe2_channel_i_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^user_rate_gen3\, + O => rxchbonden_0 + ); +mmcm_lock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_mmcm_lock_in, + Q => mmcm_lock_reg1, + R => RST_CPLLRESET + ); +mmcm_lock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => mmcm_lock_reg1, + Q => mmcm_lock_reg2, + R => RST_CPLLRESET + ); +pclk_sel_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"14FF1400" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => pclk_sel_i_2_n_0, + I4 => \^pipe_pclk_sel_out\(0), + O => pclk_sel_i_1_n_0 + ); +pclk_sel_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"80022000" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + O => pclk_sel_i_2_n_0 + ); +pclk_sel_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => pclk_sel_i_1_n_0, + Q => \^pipe_pclk_sel_out\(0), + R => RST_CPLLRESET + ); +phystatus_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008000000" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => txratedone_i_2_n_0, + I3 => \fsm_reg_n_0_[0]\, + I4 => phystatus_reg2, + I5 => phystatus, + O => phystatus_i_1_n_0 + ); +phystatus_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => phystatus_i_1_n_0, + Q => phystatus, + R => RST_CPLLRESET + ); +phystatus_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_PHYSTATUS, + Q => phystatus_reg1, + R => RST_CPLLRESET + ); +phystatus_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => phystatus_reg1, + Q => phystatus_reg2, + R => RST_CPLLRESET + ); +qplllock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_QPLLLOCK, + Q => qplllock_reg1, + R => RST_CPLLRESET + ); +qplllock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qplllock_reg1, + Q => qplllock_reg2, + R => RST_CPLLRESET + ); +\qpllpd_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF40440000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllpd, + I5 => \^qrst_qpllpd_in\(0), + O => \qpllpd_i_1__0_n_0\ + ); +qpllpd_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \qpllpd_i_1__0_n_0\, + Q => \^qrst_qpllpd_in\(0), + R => RST_CPLLRESET + ); +\qpllreset_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF40440000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllreset, + I5 => \^qrst_qpllreset_in\(0), + O => \qpllreset_i_1__0_n_0\ + ); +qpllreset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \qpllreset_i_1__0_n_0\, + Q => \^qrst_qpllreset_in\(0), + R => RST_CPLLRESET + ); +rate_done_reg1_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000080" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[1]\, + O => USER_RATE_DONE + ); +\rate_idle_reg1[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[3]\, + O => SYNC_RATE_IDLE + ); +\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rate_in_reg1_reg[0]_0\(0), + Q => rate_in_reg1(0), + R => RST_CPLLRESET + ); +\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rate_in_reg1(1), + R => RST_CPLLRESET + ); +\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_in_reg1(0), + Q => rate_in_reg2(0), + R => RST_CPLLRESET + ); +\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_in_reg1(1), + Q => rate_in_reg2(1), + R => RST_CPLLRESET + ); +\rate_out[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0444FFFF04440000" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg2(0), + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \rate_out[0]_i_2_n_0\, + I5 => \^rxrate\(0), + O => \rate_out[0]_i_1_n_0\ + ); +\rate_out[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8002020080000200" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => txpmareset0, + O => \rate_out[0]_i_2_n_0\ + ); +\rate_out[0]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => gen3_exit, + I1 => rate_in_reg2(0), + I2 => rate_in_reg2(1), + O => txpmareset0 + ); +\rate_out_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rate_out[0]_i_1_n_0\, + Q => \^rxrate\(0), + R => RST_CPLLRESET + ); +rate_rxsync_reg1_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"08800000" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[2]\, + O => USER_RATE_RXSYNC + ); +ratedone_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"A3333333A0000000" + ) + port map ( + I0 => ratedone_i_2_n_0, + I1 => ratedone_i_3_n_0, + I2 => rxratedone, + I3 => phystatus, + I4 => txratedone, + I5 => ratedone, + O => ratedone_i_1_n_0 + ); +ratedone_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"00080000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + O => ratedone_i_2_n_0 + ); +ratedone_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"FDFFFFFF" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[4]\, + O => ratedone_i_3_n_0 + ); +ratedone_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => ratedone_i_1_n_0, + Q => ratedone, + R => RST_CPLLRESET + ); +resetovrd_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '1', + Q => resetovrd_done_reg1, + R => RST_CPLLRESET + ); +resetovrd_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => resetovrd_done_reg1, + Q => resetovrd_done_reg2, + R => RST_CPLLRESET + ); +resetovrd_start_reg1_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000080" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[3]\, + O => USER_RESETOVRD_START + ); +rst_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RST_IDLE, + Q => rst_idle_reg1, + R => RST_CPLLRESET + ); +rst_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rst_idle_reg1, + Q => rst_idle_reg2, + R => RST_CPLLRESET + ); +rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxpmaresetdone_reg1, + R => RST_CPLLRESET + ); +rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxpmaresetdone_reg1, + Q => rxpmaresetdone_reg2, + R => RST_CPLLRESET + ); +rxratedone_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008000000" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => txratedone_i_2_n_0, + I3 => \fsm_reg_n_0_[0]\, + I4 => rxratedone_reg2, + I5 => rxratedone, + O => rxratedone_i_1_n_0 + ); +rxratedone_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxratedone_i_1_n_0, + Q => rxratedone, + R => RST_CPLLRESET + ); +rxratedone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_RXRATEDONE, + Q => rxratedone_reg1, + R => RST_CPLLRESET + ); +rxratedone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxratedone_reg1, + Q => rxratedone_reg2, + R => RST_CPLLRESET + ); +rxresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RXRESETDONE, + Q => rxresetdone_reg1, + R => RST_CPLLRESET + ); +rxresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxresetdone_reg1, + Q => rxresetdone_reg2, + R => RST_CPLLRESET + ); +rxsync_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxsync_done_reg1, + R => RST_CPLLRESET + ); +rxsync_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsync_done_reg1, + Q => rxsync_done_reg2, + R => RST_CPLLRESET + ); +rxsync_start_reg1_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"08000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm_reg_n_0_[3]\, + O => SYNC_RXSYNC_START + ); +\sysclksel[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0FFFFF4F00000040" + ) + port map ( + I0 => rate_in_reg2(0), + I1 => rate_in_reg2(1), + I2 => \sysclksel[0]_i_2_n_0\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[4]\, + I5 => \^rxsysclksel\(0), + O => \sysclksel[0]_i_1_n_0\ + ); +\sysclksel[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + O => \sysclksel[0]_i_2_n_0\ + ); +\sysclksel_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \sysclksel[0]_i_1_n_0\, + Q => \^rxsysclksel\(0), + R => RST_CPLLRESET + ); +\txdata_wait_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B333000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2_n_0\, + I5 => \txdata_wait_cnt[3]_i_3_n_0\, + O => \p_0_in__0\(0) + ); +\txdata_wait_cnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"E666000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2_n_0\, + I5 => \txdata_wait_cnt[3]_i_3_n_0\, + O => \p_0_in__0\(1) + ); +\txdata_wait_cnt[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F878000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2_n_0\, + I5 => \txdata_wait_cnt[3]_i_3_n_0\, + O => \p_0_in__0\(2) + ); +\txdata_wait_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF80000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2_n_0\, + I5 => \txdata_wait_cnt[3]_i_3_n_0\, + O => \p_0_in__0\(3) + ); +\txdata_wait_cnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \txdata_wait_cnt[3]_i_2_n_0\ + ); +\txdata_wait_cnt[3]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + O => \txdata_wait_cnt[3]_i_3_n_0\ + ); +\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(0), + Q => txdata_wait_cnt_reg(0), + R => RST_CPLLRESET + ); +\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(1), + Q => txdata_wait_cnt_reg(1), + R => RST_CPLLRESET + ); +\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(2), + Q => txdata_wait_cnt_reg(2), + R => RST_CPLLRESET + ); +\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(3), + Q => txdata_wait_cnt_reg(3), + R => RST_CPLLRESET + ); +txpmareset_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00F2FFFF00F20000" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg2(0), + I2 => gen3_exit, + I3 => \fsm_reg_n_0_[3]\, + I4 => txpmareset_i_2_n_0, + I5 => \^rate_txpmareset_0\, + O => txpmareset_i_1_n_0 + ); +txpmareset_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"80004200" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[4]\, + O => txpmareset_i_2_n_0 + ); +txpmareset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpmareset_i_1_n_0, + Q => \^rate_txpmareset_0\, + R => RST_CPLLRESET + ); +txratedone_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008000000" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => txratedone_i_2_n_0, + I3 => \fsm_reg_n_0_[0]\, + I4 => txratedone_reg2, + I5 => txratedone, + O => txratedone_i_1_n_0 + ); +txratedone_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[1]\, + O => txratedone_i_2_n_0 + ); +txratedone_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => txratedone_i_1_n_0, + Q => txratedone, + R => RST_CPLLRESET + ); +txratedone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_TXRATEDONE, + Q => txratedone_reg1, + R => RST_CPLLRESET + ); +txratedone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txratedone_reg1, + Q => txratedone_reg2, + R => RST_CPLLRESET + ); +txresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_TXRESETDONE, + Q => txresetdone_reg1, + R => RST_CPLLRESET + ); +txresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txresetdone_reg1, + Q => txresetdone_reg2, + R => RST_CPLLRESET + ); +txsync_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_TXSYNC_DONE, + Q => txsync_done_reg1, + R => RST_CPLLRESET + ); +txsync_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_done_reg1, + Q => txsync_done_reg2, + R => RST_CPLLRESET + ); +txsync_start_reg1_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00004000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[2]\, + I5 => RST_TXSYNC_START, + O => SYNC_TXSYNC_START + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_rate_40 is + port ( + SYNC_TXSYNC_START : out STD_LOGIC; + QPLL_DRP_GEN3 : out STD_LOGIC; + rate_gen3_1 : out STD_LOGIC; + rxchbonden_1 : out STD_LOGIC; + RATE_DRP_START : out STD_LOGIC; + RATE_DRP_X16X20_MODE : out STD_LOGIC; + RATE_DRP_X16 : out STD_LOGIC; + USER_RATE_RXSYNC : out STD_LOGIC; + SYNC_RXSYNC_START : out STD_LOGIC; + USER_RATE_DONE : out STD_LOGIC; + USER_RESETOVRD_START : out STD_LOGIC; + SYNC_RATE_IDLE : out STD_LOGIC; + rate_txpmareset_1 : out STD_LOGIC; + RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 0 to 0 ); + RXRATE : out STD_LOGIC_VECTOR ( 0 to 0 ); + QRST_QPLLPD_IN : out STD_LOGIC_VECTOR ( 0 to 0 ); + rate_cpllpd_1 : out STD_LOGIC; + QRST_QPLLRESET_IN : out STD_LOGIC_VECTOR ( 0 to 0 ); + rate_cpllreset_1 : out STD_LOGIC; + RST_TXSYNC_START : in STD_LOGIC; + USER_RATE_GEN3 : in STD_LOGIC; + rate_gen3_3 : in STD_LOGIC; + rate_gen3_2 : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + \rate_in_reg1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RST_IDLE : in STD_LOGIC; + QRST_CPLLLOCK : in STD_LOGIC_VECTOR ( 0 to 0 ); + RATE_QPLLLOCK : in STD_LOGIC; + RATE_DRP_DONE : in STD_LOGIC; + pipe_mmcm_lock_in : in STD_LOGIC; + RATE_PHYSTATUS : in STD_LOGIC; + USER_TXRESETDONE : in STD_LOGIC; + USER_RXRESETDONE : in STD_LOGIC; + RATE_TXRATEDONE : in STD_LOGIC; + RATE_RXRATEDONE : in STD_LOGIC; + RATE_TXSYNC_DONE : in STD_LOGIC; + user_active_lane_1 : in STD_LOGIC; + \out\ : in STD_LOGIC; + \fsm[0]_i_9__0_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_rate_40 : entity is "pcie_7x_0_pipe_rate"; +end pcie_7x_0_pcie_7x_0_pipe_rate_40; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_rate_40 is + signal \^qrst_qpllpd_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^qrst_qpllreset_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^rxrate\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal cplllock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of cplllock_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of cplllock_reg1 : signal is "true"; + signal cplllock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of cplllock_reg2 : signal is "NO"; + attribute async_reg of cplllock_reg2 : signal is "true"; + signal \cpllpd_i_1__0_n_0\ : STD_LOGIC; + signal \cpllreset_i_1__1_n_0\ : STD_LOGIC; + signal drp_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO"; + attribute async_reg of drp_done_reg1 : signal is "true"; + signal drp_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO"; + attribute async_reg of drp_done_reg2 : signal is "true"; + signal \drp_start_i_1__0_n_0\ : STD_LOGIC; + signal \drp_x16_i_1__0_n_0\ : STD_LOGIC; + signal \drp_x16x20_mode_i_1__0_n_0\ : STD_LOGIC; + signal fsm : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal fsm1 : STD_LOGIC; + signal \fsm[0]_i_10__0_n_0\ : STD_LOGIC; + signal \fsm[0]_i_11__0_n_0\ : STD_LOGIC; + signal \fsm[0]_i_12__0_n_0\ : STD_LOGIC; + signal \fsm[0]_i_2__2_n_0\ : STD_LOGIC; + signal \fsm[0]_i_3__0_n_0\ : STD_LOGIC; + signal \fsm[0]_i_4__0_n_0\ : STD_LOGIC; + signal \fsm[0]_i_5__0_n_0\ : STD_LOGIC; + signal \fsm[0]_i_7__0_n_0\ : STD_LOGIC; + signal \fsm[0]_i_8__0_n_0\ : STD_LOGIC; + signal \fsm[0]_i_9__0_n_0\ : STD_LOGIC; + signal \fsm[1]_i_2__1_n_0\ : STD_LOGIC; + signal \fsm[1]_i_3__0_n_0\ : STD_LOGIC; + signal \fsm[1]_i_4__0_n_0\ : STD_LOGIC; + signal \fsm[1]_i_5__0_n_0\ : STD_LOGIC; + signal \fsm[1]_i_6__0_n_0\ : STD_LOGIC; + signal \fsm[1]_i_7__0_n_0\ : STD_LOGIC; + signal \fsm[1]_i_8__0_n_0\ : STD_LOGIC; + signal \fsm[2]_i_2__0_n_0\ : STD_LOGIC; + signal \fsm[2]_i_3__0_n_0\ : STD_LOGIC; + signal \fsm[2]_i_4__0_n_0\ : STD_LOGIC; + signal \fsm[2]_i_5__0_n_0\ : STD_LOGIC; + signal \fsm[2]_i_6__0_n_0\ : STD_LOGIC; + signal \fsm[3]_i_2__0_n_0\ : STD_LOGIC; + signal \fsm[3]_i_3__0_n_0\ : STD_LOGIC; + signal \fsm[3]_i_4__0_n_0\ : STD_LOGIC; + signal \fsm[3]_i_6__0_n_0\ : STD_LOGIC; + signal \fsm[4]_i_2__0_n_0\ : STD_LOGIC; + signal \fsm[4]_i_3__0_n_0\ : STD_LOGIC; + signal \fsm_reg_n_0_[0]\ : STD_LOGIC; + signal \fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \fsm_reg_n_0_[2]\ : STD_LOGIC; + signal \fsm_reg_n_0_[3]\ : STD_LOGIC; + signal \fsm_reg_n_0_[4]\ : STD_LOGIC; + signal gen3_exit : STD_LOGIC; + signal \gen3_exit_i_1__0_n_0\ : STD_LOGIC; + signal \gen3_exit_i_2__0_n_0\ : STD_LOGIC; + signal \gen3_i_1__0_n_0\ : STD_LOGIC; + signal \gen3_i_2__0_n_0\ : STD_LOGIC; + signal \gen3_i_3__0_n_0\ : STD_LOGIC; + signal mmcm_lock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO"; + attribute async_reg of mmcm_lock_reg1 : signal is "true"; + signal mmcm_lock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO"; + attribute async_reg of mmcm_lock_reg2 : signal is "true"; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \pclk_sel_i_1__0_n_0\ : STD_LOGIC; + signal \pclk_sel_i_2__0_n_0\ : STD_LOGIC; + signal phystatus : STD_LOGIC; + signal \phystatus_i_1__0_n_0\ : STD_LOGIC; + signal phystatus_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of phystatus_reg1 : signal is "NO"; + attribute async_reg of phystatus_reg1 : signal is "true"; + signal phystatus_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of phystatus_reg2 : signal is "NO"; + attribute async_reg of phystatus_reg2 : signal is "true"; + signal \^pipe_pclk_sel_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal pll_lock : STD_LOGIC; + signal qplllock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of qplllock_reg1 : signal is "NO"; + attribute async_reg of qplllock_reg1 : signal is "true"; + signal qplllock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of qplllock_reg2 : signal is "NO"; + attribute async_reg of qplllock_reg2 : signal is "true"; + signal qpllpd : STD_LOGIC; + signal \qpllpd_i_1__1_n_0\ : STD_LOGIC; + signal qpllreset : STD_LOGIC; + signal \qpllreset_i_1__1_n_0\ : STD_LOGIC; + signal \^rate_cpllpd_1\ : STD_LOGIC; + signal \^rate_cpllreset_1\ : STD_LOGIC; + signal \^rate_gen3_1\ : STD_LOGIC; + signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_in_reg1 : signal is "NO"; + attribute async_reg of rate_in_reg1 : signal is "true"; + signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_in_reg2 : signal is "NO"; + attribute async_reg of rate_in_reg2 : signal is "true"; + signal \rate_out[0]_i_1__0_n_0\ : STD_LOGIC; + signal \rate_out[0]_i_2__0_n_0\ : STD_LOGIC; + signal \^rate_txpmareset_1\ : STD_LOGIC; + signal ratedone : STD_LOGIC; + signal \ratedone_i_1__0_n_0\ : STD_LOGIC; + signal \ratedone_i_2__0_n_0\ : STD_LOGIC; + signal \ratedone_i_3__0_n_0\ : STD_LOGIC; + signal resetovrd_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_done_reg1 : signal is "NO"; + attribute async_reg of resetovrd_done_reg1 : signal is "true"; + signal resetovrd_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_done_reg2 : signal is "NO"; + attribute async_reg of resetovrd_done_reg2 : signal is "true"; + signal rst_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO"; + attribute async_reg of rst_idle_reg1 : signal is "true"; + signal rst_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO"; + attribute async_reg of rst_idle_reg2 : signal is "true"; + signal rxpmaresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg1 : signal is "NO"; + attribute async_reg of rxpmaresetdone_reg1 : signal is "true"; + signal rxpmaresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg2 : signal is "NO"; + attribute async_reg of rxpmaresetdone_reg2 : signal is "true"; + signal rxratedone : STD_LOGIC; + signal \rxratedone_i_1__0_n_0\ : STD_LOGIC; + signal rxratedone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxratedone_reg1 : signal is "NO"; + attribute async_reg of rxratedone_reg1 : signal is "true"; + signal rxratedone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxratedone_reg2 : signal is "NO"; + attribute async_reg of rxratedone_reg2 : signal is "true"; + signal rxresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO"; + attribute async_reg of rxresetdone_reg1 : signal is "true"; + signal rxresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO"; + attribute async_reg of rxresetdone_reg2 : signal is "true"; + signal rxsync_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_done_reg1 : signal is "NO"; + attribute async_reg of rxsync_done_reg1 : signal is "true"; + signal rxsync_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_done_reg2 : signal is "NO"; + attribute async_reg of rxsync_done_reg2 : signal is "true"; + signal \sysclksel[0]_i_1__0_n_0\ : STD_LOGIC; + signal \sysclksel[0]_i_2__0_n_0\ : STD_LOGIC; + signal \txdata_wait_cnt[3]_i_2__0_n_0\ : STD_LOGIC; + signal \txdata_wait_cnt[3]_i_3__0_n_0\ : STD_LOGIC; + signal txdata_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal txpmareset0 : STD_LOGIC; + signal \txpmareset_i_1__0_n_0\ : STD_LOGIC; + signal \txpmareset_i_2__0_n_0\ : STD_LOGIC; + signal txratedone : STD_LOGIC; + signal \txratedone_i_1__0_n_0\ : STD_LOGIC; + signal \txratedone_i_2__0_n_0\ : STD_LOGIC; + signal txratedone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txratedone_reg1 : signal is "NO"; + attribute async_reg of txratedone_reg1 : signal is "true"; + signal txratedone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txratedone_reg2 : signal is "NO"; + attribute async_reg of txratedone_reg2 : signal is "true"; + signal txresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO"; + attribute async_reg of txresetdone_reg1 : signal is "true"; + signal txresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO"; + attribute async_reg of txresetdone_reg2 : signal is "true"; + signal txsync_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_done_reg1 : signal is "NO"; + attribute async_reg of txsync_done_reg1 : signal is "true"; + signal txsync_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_done_reg2 : signal is "NO"; + attribute async_reg of txsync_done_reg2 : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of cplllock_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of cplllock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of cplllock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of cplllock_reg2_reg : label is std.standard.true; + attribute KEEP of cplllock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of cplllock_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \cpllpd_i_2__0\ : label is "soft_lutpair111"; + attribute SOFT_HLUTNM of \cpllreset_i_2__1\ : label is "soft_lutpair112"; + attribute ASYNC_REG_boolean of drp_done_reg1_reg : label is std.standard.true; + attribute KEEP of drp_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of drp_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of drp_done_reg2_reg : label is std.standard.true; + attribute KEEP of drp_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of drp_done_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \drp_start_i_1__0\ : label is "soft_lutpair115"; + attribute SOFT_HLUTNM of \drp_x16_i_1__0\ : label is "soft_lutpair116"; + attribute SOFT_HLUTNM of \drp_x16x20_mode_i_1__0\ : label is "soft_lutpair117"; + attribute SOFT_HLUTNM of \fsm[0]_i_1__2\ : label is "soft_lutpair110"; + attribute SOFT_HLUTNM of \fsm[4]_i_3__0\ : label is "soft_lutpair120"; + attribute SOFT_HLUTNM of gen3_reg1_i_1 : label is "soft_lutpair118"; + attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_5__0\ : label is "soft_lutpair118"; + attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \pclk_sel_i_2__0\ : label is "soft_lutpair111"; + attribute ASYNC_REG_boolean of phystatus_reg1_reg : label is std.standard.true; + attribute KEEP of phystatus_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of phystatus_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of phystatus_reg2_reg : label is std.standard.true; + attribute KEEP of phystatus_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of phystatus_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of qplllock_reg1_reg : label is std.standard.true; + attribute KEEP of qplllock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of qplllock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of qplllock_reg2_reg : label is std.standard.true; + attribute KEEP of qplllock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of qplllock_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \rate_done_reg1_i_1__0\ : label is "soft_lutpair115"; + attribute SOFT_HLUTNM of \rate_idle_reg1[1]_i_1\ : label is "soft_lutpair117"; + attribute ASYNC_REG_boolean of \rate_in_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_in_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_in_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_in_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg2_reg[1]\ : label is "NO"; + attribute SOFT_HLUTNM of \rate_rxsync_reg1_i_1__0\ : label is "soft_lutpair114"; + attribute SOFT_HLUTNM of \ratedone_i_2__0\ : label is "soft_lutpair113"; + attribute SOFT_HLUTNM of \ratedone_i_3__0\ : label is "soft_lutpair113"; + attribute ASYNC_REG_boolean of resetovrd_done_reg1_reg : label is std.standard.true; + attribute KEEP of resetovrd_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of resetovrd_done_reg2_reg : label is std.standard.true; + attribute KEEP of resetovrd_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_done_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \resetovrd_start_reg1_i_1__0\ : label is "soft_lutpair116"; + attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxpmaresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxpmaresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxratedone_reg1_reg : label is std.standard.true; + attribute KEEP of rxratedone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxratedone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxratedone_reg2_reg : label is std.standard.true; + attribute KEEP of rxratedone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxratedone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_done_reg1_reg : label is std.standard.true; + attribute KEEP of rxsync_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_done_reg2_reg : label is std.standard.true; + attribute KEEP of rxsync_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_done_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \rxsync_start_reg1_i_1__0\ : label is "soft_lutpair114"; + attribute SOFT_HLUTNM of \sysclksel[0]_i_2__0\ : label is "soft_lutpair119"; + attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_2__0\ : label is "soft_lutpair119"; + attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_3__0\ : label is "soft_lutpair110"; + attribute SOFT_HLUTNM of \txpmareset_i_2__0\ : label is "soft_lutpair112"; + attribute SOFT_HLUTNM of \txratedone_i_2__0\ : label is "soft_lutpair120"; + attribute ASYNC_REG_boolean of txratedone_reg1_reg : label is std.standard.true; + attribute KEEP of txratedone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txratedone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txratedone_reg2_reg : label is std.standard.true; + attribute KEEP of txratedone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txratedone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_done_reg1_reg : label is std.standard.true; + attribute KEEP of txsync_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_done_reg2_reg : label is std.standard.true; + attribute KEEP of txsync_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_done_reg2_reg : label is "NO"; +begin + QRST_QPLLPD_IN(0) <= \^qrst_qpllpd_in\(0); + QRST_QPLLRESET_IN(0) <= \^qrst_qpllreset_in\(0); + RXRATE(0) <= \^rxrate\(0); + RXSYSCLKSEL(0) <= \^rxsysclksel\(0); + pipe_pclk_sel_out(0) <= \^pipe_pclk_sel_out\(0); + rate_cpllpd_1 <= \^rate_cpllpd_1\; + rate_cpllreset_1 <= \^rate_cpllreset_1\; + rate_gen3_1 <= \^rate_gen3_1\; + rate_txpmareset_1 <= \^rate_txpmareset_1\; +cplllock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => QRST_CPLLLOCK(0), + Q => cplllock_reg1, + R => RST_CPLLRESET + ); +cplllock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => cplllock_reg1, + Q => cplllock_reg2, + R => RST_CPLLRESET + ); +\cpllpd_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0400FFFF04000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllpd, + I5 => \^rate_cpllpd_1\, + O => \cpllpd_i_1__0_n_0\ + ); +\cpllpd_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000900" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[2]\, + O => qpllpd + ); +cpllpd_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \cpllpd_i_1__0_n_0\, + Q => \^rate_cpllpd_1\, + R => RST_CPLLRESET + ); +\cpllreset_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0400FFFF04000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllreset, + I5 => \^rate_cpllreset_1\, + O => \cpllreset_i_1__1_n_0\ + ); +\cpllreset_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80001004" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm_reg_n_0_[0]\, + O => qpllreset + ); +cpllreset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \cpllreset_i_1__1_n_0\, + Q => \^rate_cpllreset_1\, + R => RST_CPLLRESET + ); +drp_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_DRP_DONE, + Q => drp_done_reg1, + R => RST_CPLLRESET + ); +drp_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => drp_done_reg1, + Q => drp_done_reg2, + R => RST_CPLLRESET + ); +\drp_start_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08420100" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[0]\, + O => \drp_start_i_1__0_n_0\ + ); +drp_start_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \drp_start_i_1__0_n_0\, + Q => RATE_DRP_START, + R => RST_CPLLRESET + ); +\drp_x16_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20100014" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + O => \drp_x16_i_1__0_n_0\ + ); +drp_x16_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \drp_x16_i_1__0_n_0\, + Q => RATE_DRP_X16, + R => RST_CPLLRESET + ); +\drp_x16x20_mode_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20080074" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[1]\, + O => \drp_x16x20_mode_i_1__0_n_0\ + ); +drp_x16x20_mode_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \drp_x16x20_mode_i_1__0_n_0\, + Q => RATE_DRP_X16X20_MODE, + R => RST_CPLLRESET + ); +\fsm[0]_i_10__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0901595100000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => rxsync_done_reg2, + I4 => txsync_done_reg2, + I5 => \fsm_reg_n_0_[3]\, + O => \fsm[0]_i_10__0_n_0\ + ); +\fsm[0]_i_11__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1101111101000110" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => rxpmaresetdone_reg2, + I5 => drp_done_reg2, + O => \fsm[0]_i_11__0_n_0\ + ); +\fsm[0]_i_12__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20202320" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => mmcm_lock_reg2, + I4 => rxpmaresetdone_reg2, + O => \fsm[0]_i_12__0_n_0\ + ); +\fsm[0]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF3210" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm[0]_i_2__2_n_0\, + I3 => \fsm[0]_i_3__0_n_0\, + I4 => \fsm[0]_i_4__0_n_0\, + O => fsm(0) + ); +\fsm[0]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0F3F3F47444744" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm[0]_i_5__0_n_0\, + I4 => pll_lock, + I5 => \fsm_reg_n_0_[1]\, + O => \fsm[0]_i_2__2_n_0\ + ); +\fsm[0]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F3F3AAAAFF00AAAA" + ) + port map ( + I0 => \fsm[0]_i_7__0_n_0\, + I1 => \fsm_reg_n_0_[0]\, + I2 => drp_done_reg2, + I3 => \fsm[0]_i_8__0_n_0\, + I4 => \fsm_reg_n_0_[2]\, + I5 => \fsm_reg_n_0_[1]\, + O => \fsm[0]_i_3__0_n_0\ + ); +\fsm[0]_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFF4000000000" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm[0]_i_9__0_n_0\, + I3 => \fsm[0]_i_10__0_n_0\, + I4 => \fsm[0]_i_11__0_n_0\, + I5 => \fsm_reg_n_0_[4]\, + O => \fsm[0]_i_4__0_n_0\ + ); +\fsm[0]_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg1(1), + I2 => rate_in_reg2(0), + I3 => rate_in_reg1(0), + O => \fsm[0]_i_5__0_n_0\ + ); +\fsm[0]_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => qplllock_reg2, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => cplllock_reg2, + O => pll_lock + ); +\fsm[0]_i_7__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAEAAAAAAA" + ) + port map ( + I0 => \fsm[0]_i_12__0_n_0\, + I1 => pll_lock, + I2 => rst_idle_reg2, + I3 => drp_done_reg2, + I4 => \fsm_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[0]\, + O => \fsm[0]_i_7__0_n_0\ + ); +\fsm[0]_i_8__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF5D5500005D55" + ) + port map ( + I0 => user_active_lane_1, + I1 => txresetdone_reg2, + I2 => phystatus_reg2, + I3 => rxresetdone_reg2, + I4 => \fsm_reg_n_0_[0]\, + I5 => \fsm[1]_i_7__0_n_0\, + O => \fsm[0]_i_8__0_n_0\ + ); +\fsm[0]_i_9__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"33330FAA" + ) + port map ( + I0 => drp_done_reg2, + I1 => resetovrd_done_reg2, + I2 => fsm1, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[1]\, + O => \fsm[0]_i_9__0_n_0\ + ); +\fsm[1]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFE4FFE4FFE400E4" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm[1]_i_2__1_n_0\, + I2 => \fsm[1]_i_3__0_n_0\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm[1]_i_4__0_n_0\, + I5 => \fsm[1]_i_5__0_n_0\, + O => fsm(1) + ); +\fsm[1]_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"3388F0CC" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm[1]_i_6__0_n_0\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[2]\, + O => \fsm[1]_i_2__1_n_0\ + ); +\fsm[1]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CC5500000033F000" + ) + port map ( + I0 => \fsm[1]_i_7__0_n_0\, + I1 => drp_done_reg2, + I2 => \fsm[1]_i_8__0_n_0\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[1]_i_3__0_n_0\ + ); +\fsm[1]_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000005FCF0000" + ) + port map ( + I0 => resetovrd_done_reg2, + I1 => drp_done_reg2, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[3]\, + O => \fsm[1]_i_4__0_n_0\ + ); +\fsm[1]_i_5__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"143C547C00000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => rxsync_done_reg2, + I4 => txsync_done_reg2, + I5 => \fsm_reg_n_0_[3]\, + O => \fsm[1]_i_5__0_n_0\ + ); +\fsm[1]_i_6__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"34F7FFFFFFFFFFFF" + ) + port map ( + I0 => qplllock_reg2, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => cplllock_reg2, + I4 => rst_idle_reg2, + I5 => \fsm_reg_n_0_[0]\, + O => \fsm[1]_i_6__0_n_0\ + ); +\fsm[1]_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => txdata_wait_cnt_reg(3), + I1 => txdata_wait_cnt_reg(1), + I2 => txdata_wait_cnt_reg(0), + I3 => txdata_wait_cnt_reg(2), + O => \fsm[1]_i_7__0_n_0\ + ); +\fsm[1]_i_8__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF04F7FFFF" + ) + port map ( + I0 => qplllock_reg2, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => cplllock_reg2, + I4 => drp_done_reg2, + I5 => rst_idle_reg2, + O => \fsm[1]_i_8__0_n_0\ + ); +\fsm[2]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAFFAAAAAAAAAAAA" + ) + port map ( + I0 => \fsm[2]_i_4__0_n_0\, + I1 => drp_done_reg2, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[2]_i_2__0_n_0\ + ); +\fsm[2]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFBAAAAAAAAAAAAA" + ) + port map ( + I0 => \fsm[2]_i_5__0_n_0\, + I1 => rxsync_done_reg2, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[2]_i_3__0_n_0\ + ); +\fsm[2]_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FA554455005544" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm[3]_i_6__0_n_0\, + I2 => pll_lock, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[0]\, + O => \fsm[2]_i_4__0_n_0\ + ); +\fsm[2]_i_5__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2000FFFF20000000" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => txsync_done_reg2, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm[2]_i_6__0_n_0\, + O => \fsm[2]_i_5__0_n_0\ + ); +\fsm[2]_i_6__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1CDC3C3C1CDCFCFC" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => resetovrd_done_reg2, + I4 => \fsm_reg_n_0_[1]\, + I5 => fsm1, + O => \fsm[2]_i_6__0_n_0\ + ); +\fsm[3]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFB0803080" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => drp_done_reg2, + I5 => \fsm[3]_i_4__0_n_0\, + O => \fsm[3]_i_2__0_n_0\ + ); +\fsm[3]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF8880000F888" + ) + port map ( + I0 => \txdata_wait_cnt[3]_i_2__0_n_0\, + I1 => fsm1, + I2 => resetovrd_done_reg2, + I3 => \sysclksel[0]_i_2__0_n_0\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm[4]_i_2__0_n_0\, + O => \fsm[3]_i_3__0_n_0\ + ); +\fsm[3]_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EEFF00F0" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm[1]_i_8__0_n_0\, + I2 => \fsm[3]_i_6__0_n_0\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[3]_i_4__0_n_0\ + ); +\fsm[3]_i_5__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF8F8FFF8" + ) + port map ( + I0 => \out\, + I1 => \fsm[0]_i_9__0_0\, + I2 => ratedone, + I3 => rate_in_reg2(1), + I4 => rate_in_reg2(0), + I5 => gen3_exit, + O => fsm1 + ); +\fsm[3]_i_6__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00504414" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => rate_in_reg1(0), + I2 => rate_in_reg2(0), + I3 => rate_in_reg1(1), + I4 => rate_in_reg2(1), + O => \fsm[3]_i_6__0_n_0\ + ); +\fsm[4]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C5F0CFF0C0F0C0F0" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm[4]_i_2__0_n_0\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => drp_done_reg2, + I5 => \fsm[4]_i_3__0_n_0\, + O => fsm(4) + ); +\fsm[4]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"26FF" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => rxsync_done_reg2, + I3 => \fsm_reg_n_0_[2]\, + O => \fsm[4]_i_2__0_n_0\ + ); +\fsm[4]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[2]\, + O => \fsm[4]_i_3__0_n_0\ + ); +\fsm_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(0), + Q => \fsm_reg_n_0_[0]\, + S => RST_CPLLRESET + ); +\fsm_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(1), + Q => \fsm_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(2), + Q => \fsm_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\fsm_reg[2]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \fsm[2]_i_2__0_n_0\, + I1 => \fsm[2]_i_3__0_n_0\, + O => fsm(2), + S => \fsm_reg_n_0_[4]\ + ); +\fsm_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(3), + Q => \fsm_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\fsm_reg[3]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \fsm[3]_i_2__0_n_0\, + I1 => \fsm[3]_i_3__0_n_0\, + O => fsm(3), + S => \fsm_reg_n_0_[4]\ + ); +\fsm_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(4), + Q => \fsm_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\gen3_exit_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"04FF0400" + ) + port map ( + I0 => rate_in_reg2(0), + I1 => rate_in_reg2(1), + I2 => \fsm_reg_n_0_[4]\, + I3 => \gen3_exit_i_2__0_n_0\, + I4 => gen3_exit, + O => \gen3_exit_i_1__0_n_0\ + ); +\gen3_exit_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000180000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[4]\, + I5 => \fsm[0]_i_5__0_n_0\, + O => \gen3_exit_i_2__0_n_0\ + ); +gen3_exit_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gen3_exit_i_1__0_n_0\, + Q => gen3_exit, + R => RST_CPLLRESET + ); +\gen3_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3FFFFFFB00000008" + ) + port map ( + I0 => \gen3_i_2__0_n_0\, + I1 => \gen3_i_3__0_n_0\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[4]\, + I5 => \^rate_gen3_1\, + O => \gen3_i_1__0_n_0\ + ); +\gen3_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg2(0), + O => \gen3_i_2__0_n_0\ + ); +\gen3_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[0]\, + O => \gen3_i_3__0_n_0\ + ); +gen3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gen3_i_1__0_n_0\, + Q => \^rate_gen3_1\, + R => RST_CPLLRESET + ); +gen3_reg1_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \^rate_gen3_1\, + I1 => USER_RATE_GEN3, + I2 => rate_gen3_3, + I3 => rate_gen3_2, + O => QPLL_DRP_GEN3 + ); +\gtx_channel.gtxe2_channel_i_i_5__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^rate_gen3_1\, + O => rxchbonden_1 + ); +mmcm_lock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_mmcm_lock_in, + Q => mmcm_lock_reg1, + R => RST_CPLLRESET + ); +mmcm_lock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => mmcm_lock_reg1, + Q => mmcm_lock_reg2, + R => RST_CPLLRESET + ); +\pclk_sel_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"14FF1400" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => \pclk_sel_i_2__0_n_0\, + I4 => \^pipe_pclk_sel_out\(0), + O => \pclk_sel_i_1__0_n_0\ + ); +\pclk_sel_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80022000" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + O => \pclk_sel_i_2__0_n_0\ + ); +pclk_sel_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pclk_sel_i_1__0_n_0\, + Q => \^pipe_pclk_sel_out\(0), + R => RST_CPLLRESET + ); +\phystatus_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008000000" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \txratedone_i_2__0_n_0\, + I3 => \fsm_reg_n_0_[0]\, + I4 => phystatus_reg2, + I5 => phystatus, + O => \phystatus_i_1__0_n_0\ + ); +phystatus_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \phystatus_i_1__0_n_0\, + Q => phystatus, + R => RST_CPLLRESET + ); +phystatus_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_PHYSTATUS, + Q => phystatus_reg1, + R => RST_CPLLRESET + ); +phystatus_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => phystatus_reg1, + Q => phystatus_reg2, + R => RST_CPLLRESET + ); +qplllock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_QPLLLOCK, + Q => qplllock_reg1, + R => RST_CPLLRESET + ); +qplllock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qplllock_reg1, + Q => qplllock_reg2, + R => RST_CPLLRESET + ); +\qpllpd_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF40440000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllpd, + I5 => \^qrst_qpllpd_in\(0), + O => \qpllpd_i_1__1_n_0\ + ); +qpllpd_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \qpllpd_i_1__1_n_0\, + Q => \^qrst_qpllpd_in\(0), + R => RST_CPLLRESET + ); +\qpllreset_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF40440000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllreset, + I5 => \^qrst_qpllreset_in\(0), + O => \qpllreset_i_1__1_n_0\ + ); +qpllreset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \qpllreset_i_1__1_n_0\, + Q => \^qrst_qpllreset_in\(0), + R => RST_CPLLRESET + ); +\rate_done_reg1_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000080" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[1]\, + O => USER_RATE_DONE + ); +\rate_idle_reg1[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[3]\, + O => SYNC_RATE_IDLE + ); +\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rate_in_reg1_reg[0]_0\(0), + Q => rate_in_reg1(0), + R => RST_CPLLRESET + ); +\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rate_in_reg1(1), + R => RST_CPLLRESET + ); +\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_in_reg1(0), + Q => rate_in_reg2(0), + R => RST_CPLLRESET + ); +\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_in_reg1(1), + Q => rate_in_reg2(1), + R => RST_CPLLRESET + ); +\rate_out[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0444FFFF04440000" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg2(0), + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \rate_out[0]_i_2__0_n_0\, + I5 => \^rxrate\(0), + O => \rate_out[0]_i_1__0_n_0\ + ); +\rate_out[0]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8002020080000200" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => txpmareset0, + O => \rate_out[0]_i_2__0_n_0\ + ); +\rate_out[0]_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => gen3_exit, + I1 => rate_in_reg2(0), + I2 => rate_in_reg2(1), + O => txpmareset0 + ); +\rate_out_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rate_out[0]_i_1__0_n_0\, + Q => \^rxrate\(0), + R => RST_CPLLRESET + ); +\rate_rxsync_reg1_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08800000" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[2]\, + O => USER_RATE_RXSYNC + ); +\ratedone_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A3333333A0000000" + ) + port map ( + I0 => \ratedone_i_2__0_n_0\, + I1 => \ratedone_i_3__0_n_0\, + I2 => rxratedone, + I3 => phystatus, + I4 => txratedone, + I5 => ratedone, + O => \ratedone_i_1__0_n_0\ + ); +\ratedone_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00080000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + O => \ratedone_i_2__0_n_0\ + ); +\ratedone_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FDFFFFFF" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[4]\, + O => \ratedone_i_3__0_n_0\ + ); +ratedone_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \ratedone_i_1__0_n_0\, + Q => ratedone, + R => RST_CPLLRESET + ); +resetovrd_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '1', + Q => resetovrd_done_reg1, + R => RST_CPLLRESET + ); +resetovrd_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => resetovrd_done_reg1, + Q => resetovrd_done_reg2, + R => RST_CPLLRESET + ); +\resetovrd_start_reg1_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000080" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[3]\, + O => USER_RESETOVRD_START + ); +rst_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RST_IDLE, + Q => rst_idle_reg1, + R => RST_CPLLRESET + ); +rst_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rst_idle_reg1, + Q => rst_idle_reg2, + R => RST_CPLLRESET + ); +rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxpmaresetdone_reg1, + R => RST_CPLLRESET + ); +rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxpmaresetdone_reg1, + Q => rxpmaresetdone_reg2, + R => RST_CPLLRESET + ); +\rxratedone_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008000000" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \txratedone_i_2__0_n_0\, + I3 => \fsm_reg_n_0_[0]\, + I4 => rxratedone_reg2, + I5 => rxratedone, + O => \rxratedone_i_1__0_n_0\ + ); +rxratedone_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxratedone_i_1__0_n_0\, + Q => rxratedone, + R => RST_CPLLRESET + ); +rxratedone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_RXRATEDONE, + Q => rxratedone_reg1, + R => RST_CPLLRESET + ); +rxratedone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxratedone_reg1, + Q => rxratedone_reg2, + R => RST_CPLLRESET + ); +rxresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RXRESETDONE, + Q => rxresetdone_reg1, + R => RST_CPLLRESET + ); +rxresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxresetdone_reg1, + Q => rxresetdone_reg2, + R => RST_CPLLRESET + ); +rxsync_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxsync_done_reg1, + R => RST_CPLLRESET + ); +rxsync_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsync_done_reg1, + Q => rxsync_done_reg2, + R => RST_CPLLRESET + ); +\rxsync_start_reg1_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm_reg_n_0_[3]\, + O => SYNC_RXSYNC_START + ); +\sysclksel[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0FFFFF4F00000040" + ) + port map ( + I0 => rate_in_reg2(0), + I1 => rate_in_reg2(1), + I2 => \sysclksel[0]_i_2__0_n_0\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[4]\, + I5 => \^rxsysclksel\(0), + O => \sysclksel[0]_i_1__0_n_0\ + ); +\sysclksel[0]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + O => \sysclksel[0]_i_2__0_n_0\ + ); +\sysclksel_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \sysclksel[0]_i_1__0_n_0\, + Q => \^rxsysclksel\(0), + R => RST_CPLLRESET + ); +\txdata_wait_cnt[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B333000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2__0_n_0\, + I5 => \txdata_wait_cnt[3]_i_3__0_n_0\, + O => \p_0_in__0\(0) + ); +\txdata_wait_cnt[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"E666000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2__0_n_0\, + I5 => \txdata_wait_cnt[3]_i_3__0_n_0\, + O => \p_0_in__0\(1) + ); +\txdata_wait_cnt[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F878000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2__0_n_0\, + I5 => \txdata_wait_cnt[3]_i_3__0_n_0\, + O => \p_0_in__0\(2) + ); +\txdata_wait_cnt[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF80000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2__0_n_0\, + I5 => \txdata_wait_cnt[3]_i_3__0_n_0\, + O => \p_0_in__0\(3) + ); +\txdata_wait_cnt[3]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \txdata_wait_cnt[3]_i_2__0_n_0\ + ); +\txdata_wait_cnt[3]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + O => \txdata_wait_cnt[3]_i_3__0_n_0\ + ); +\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(0), + Q => txdata_wait_cnt_reg(0), + R => RST_CPLLRESET + ); +\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(1), + Q => txdata_wait_cnt_reg(1), + R => RST_CPLLRESET + ); +\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(2), + Q => txdata_wait_cnt_reg(2), + R => RST_CPLLRESET + ); +\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(3), + Q => txdata_wait_cnt_reg(3), + R => RST_CPLLRESET + ); +\txpmareset_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00F2FFFF00F20000" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg2(0), + I2 => gen3_exit, + I3 => \fsm_reg_n_0_[3]\, + I4 => \txpmareset_i_2__0_n_0\, + I5 => \^rate_txpmareset_1\, + O => \txpmareset_i_1__0_n_0\ + ); +\txpmareset_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80004200" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[4]\, + O => \txpmareset_i_2__0_n_0\ + ); +txpmareset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpmareset_i_1__0_n_0\, + Q => \^rate_txpmareset_1\, + R => RST_CPLLRESET + ); +\txratedone_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008000000" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \txratedone_i_2__0_n_0\, + I3 => \fsm_reg_n_0_[0]\, + I4 => txratedone_reg2, + I5 => txratedone, + O => \txratedone_i_1__0_n_0\ + ); +\txratedone_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[1]\, + O => \txratedone_i_2__0_n_0\ + ); +txratedone_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txratedone_i_1__0_n_0\, + Q => txratedone, + R => RST_CPLLRESET + ); +txratedone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_TXRATEDONE, + Q => txratedone_reg1, + R => RST_CPLLRESET + ); +txratedone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txratedone_reg1, + Q => txratedone_reg2, + R => RST_CPLLRESET + ); +txresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_TXRESETDONE, + Q => txresetdone_reg1, + R => RST_CPLLRESET + ); +txresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txresetdone_reg1, + Q => txresetdone_reg2, + R => RST_CPLLRESET + ); +txsync_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_TXSYNC_DONE, + Q => txsync_done_reg1, + R => RST_CPLLRESET + ); +txsync_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_done_reg1, + Q => txsync_done_reg2, + R => RST_CPLLRESET + ); +\txsync_start_reg1_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00004000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[2]\, + I5 => RST_TXSYNC_START, + O => SYNC_TXSYNC_START + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_rate_46 is + port ( + SYNC_TXSYNC_START : out STD_LOGIC; + rxchbonden_2 : out STD_LOGIC; + rate_gen3_2 : out STD_LOGIC; + RATE_DRP_START : out STD_LOGIC; + RATE_DRP_X16X20_MODE : out STD_LOGIC; + RATE_DRP_X16 : out STD_LOGIC; + USER_RATE_RXSYNC : out STD_LOGIC; + SYNC_RXSYNC_START : out STD_LOGIC; + USER_RATE_DONE : out STD_LOGIC; + USER_RESETOVRD_START : out STD_LOGIC; + SYNC_RATE_IDLE : out STD_LOGIC; + rate_txpmareset_2 : out STD_LOGIC; + RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 0 to 0 ); + RXRATE : out STD_LOGIC_VECTOR ( 0 to 0 ); + QRST_QPLLPD_IN : out STD_LOGIC_VECTOR ( 0 to 0 ); + rate_cpllpd_2 : out STD_LOGIC; + QRST_QPLLRESET_IN : out STD_LOGIC_VECTOR ( 0 to 0 ); + rate_cpllreset_2 : out STD_LOGIC; + RST_TXSYNC_START : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + \rate_in_reg1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RST_IDLE : in STD_LOGIC; + QRST_CPLLLOCK : in STD_LOGIC_VECTOR ( 0 to 0 ); + RATE_QPLLLOCK : in STD_LOGIC; + RATE_DRP_DONE : in STD_LOGIC; + pipe_mmcm_lock_in : in STD_LOGIC; + RATE_PHYSTATUS : in STD_LOGIC; + USER_TXRESETDONE : in STD_LOGIC; + USER_RXRESETDONE : in STD_LOGIC; + RATE_TXRATEDONE : in STD_LOGIC; + RATE_RXRATEDONE : in STD_LOGIC; + RATE_TXSYNC_DONE : in STD_LOGIC; + user_active_lane_2 : in STD_LOGIC; + \out\ : in STD_LOGIC; + \fsm[0]_i_9__1_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_rate_46 : entity is "pcie_7x_0_pipe_rate"; +end pcie_7x_0_pcie_7x_0_pipe_rate_46; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_rate_46 is + signal \^qrst_qpllpd_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^qrst_qpllreset_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^rxrate\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal cplllock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of cplllock_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of cplllock_reg1 : signal is "true"; + signal cplllock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of cplllock_reg2 : signal is "NO"; + attribute async_reg of cplllock_reg2 : signal is "true"; + signal \cpllpd_i_1__1_n_0\ : STD_LOGIC; + signal \cpllreset_i_1__2_n_0\ : STD_LOGIC; + signal drp_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO"; + attribute async_reg of drp_done_reg1 : signal is "true"; + signal drp_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO"; + attribute async_reg of drp_done_reg2 : signal is "true"; + signal \drp_start_i_1__1_n_0\ : STD_LOGIC; + signal \drp_x16_i_1__1_n_0\ : STD_LOGIC; + signal \drp_x16x20_mode_i_1__1_n_0\ : STD_LOGIC; + signal fsm : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal fsm1 : STD_LOGIC; + signal \fsm[0]_i_10__1_n_0\ : STD_LOGIC; + signal \fsm[0]_i_11__1_n_0\ : STD_LOGIC; + signal \fsm[0]_i_12__1_n_0\ : STD_LOGIC; + signal \fsm[0]_i_2__4_n_0\ : STD_LOGIC; + signal \fsm[0]_i_3__1_n_0\ : STD_LOGIC; + signal \fsm[0]_i_4__1_n_0\ : STD_LOGIC; + signal \fsm[0]_i_5__1_n_0\ : STD_LOGIC; + signal \fsm[0]_i_7__1_n_0\ : STD_LOGIC; + signal \fsm[0]_i_8__1_n_0\ : STD_LOGIC; + signal \fsm[0]_i_9__1_n_0\ : STD_LOGIC; + signal \fsm[1]_i_2__2_n_0\ : STD_LOGIC; + signal \fsm[1]_i_3__1_n_0\ : STD_LOGIC; + signal \fsm[1]_i_4__1_n_0\ : STD_LOGIC; + signal \fsm[1]_i_5__1_n_0\ : STD_LOGIC; + signal \fsm[1]_i_6__1_n_0\ : STD_LOGIC; + signal \fsm[1]_i_7__1_n_0\ : STD_LOGIC; + signal \fsm[1]_i_8__1_n_0\ : STD_LOGIC; + signal \fsm[2]_i_2__1_n_0\ : STD_LOGIC; + signal \fsm[2]_i_3__1_n_0\ : STD_LOGIC; + signal \fsm[2]_i_4__1_n_0\ : STD_LOGIC; + signal \fsm[2]_i_5__1_n_0\ : STD_LOGIC; + signal \fsm[2]_i_6__1_n_0\ : STD_LOGIC; + signal \fsm[3]_i_2__1_n_0\ : STD_LOGIC; + signal \fsm[3]_i_3__1_n_0\ : STD_LOGIC; + signal \fsm[3]_i_4__1_n_0\ : STD_LOGIC; + signal \fsm[3]_i_6__1_n_0\ : STD_LOGIC; + signal \fsm[4]_i_2__1_n_0\ : STD_LOGIC; + signal \fsm[4]_i_3__1_n_0\ : STD_LOGIC; + signal \fsm_reg_n_0_[0]\ : STD_LOGIC; + signal \fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \fsm_reg_n_0_[2]\ : STD_LOGIC; + signal \fsm_reg_n_0_[3]\ : STD_LOGIC; + signal \fsm_reg_n_0_[4]\ : STD_LOGIC; + signal gen3_exit : STD_LOGIC; + signal \gen3_exit_i_1__1_n_0\ : STD_LOGIC; + signal \gen3_exit_i_2__1_n_0\ : STD_LOGIC; + signal \gen3_i_1__1_n_0\ : STD_LOGIC; + signal \gen3_i_2__1_n_0\ : STD_LOGIC; + signal \gen3_i_3__1_n_0\ : STD_LOGIC; + signal mmcm_lock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO"; + attribute async_reg of mmcm_lock_reg1 : signal is "true"; + signal mmcm_lock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO"; + attribute async_reg of mmcm_lock_reg2 : signal is "true"; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \pclk_sel_i_1__1_n_0\ : STD_LOGIC; + signal \pclk_sel_i_2__1_n_0\ : STD_LOGIC; + signal phystatus : STD_LOGIC; + signal \phystatus_i_1__1_n_0\ : STD_LOGIC; + signal phystatus_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of phystatus_reg1 : signal is "NO"; + attribute async_reg of phystatus_reg1 : signal is "true"; + signal phystatus_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of phystatus_reg2 : signal is "NO"; + attribute async_reg of phystatus_reg2 : signal is "true"; + signal \^pipe_pclk_sel_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal pll_lock : STD_LOGIC; + signal qplllock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of qplllock_reg1 : signal is "NO"; + attribute async_reg of qplllock_reg1 : signal is "true"; + signal qplllock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of qplllock_reg2 : signal is "NO"; + attribute async_reg of qplllock_reg2 : signal is "true"; + signal qpllpd : STD_LOGIC; + signal \qpllpd_i_1__2_n_0\ : STD_LOGIC; + signal qpllreset : STD_LOGIC; + signal \qpllreset_i_1__2_n_0\ : STD_LOGIC; + signal \^rate_cpllpd_2\ : STD_LOGIC; + signal \^rate_cpllreset_2\ : STD_LOGIC; + signal \^rate_gen3_2\ : STD_LOGIC; + signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_in_reg1 : signal is "NO"; + attribute async_reg of rate_in_reg1 : signal is "true"; + signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_in_reg2 : signal is "NO"; + attribute async_reg of rate_in_reg2 : signal is "true"; + signal \rate_out[0]_i_1__1_n_0\ : STD_LOGIC; + signal \rate_out[0]_i_2__1_n_0\ : STD_LOGIC; + signal \^rate_txpmareset_2\ : STD_LOGIC; + signal ratedone : STD_LOGIC; + signal \ratedone_i_1__1_n_0\ : STD_LOGIC; + signal \ratedone_i_2__1_n_0\ : STD_LOGIC; + signal \ratedone_i_3__1_n_0\ : STD_LOGIC; + signal resetovrd_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_done_reg1 : signal is "NO"; + attribute async_reg of resetovrd_done_reg1 : signal is "true"; + signal resetovrd_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_done_reg2 : signal is "NO"; + attribute async_reg of resetovrd_done_reg2 : signal is "true"; + signal rst_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO"; + attribute async_reg of rst_idle_reg1 : signal is "true"; + signal rst_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO"; + attribute async_reg of rst_idle_reg2 : signal is "true"; + signal rxpmaresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg1 : signal is "NO"; + attribute async_reg of rxpmaresetdone_reg1 : signal is "true"; + signal rxpmaresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg2 : signal is "NO"; + attribute async_reg of rxpmaresetdone_reg2 : signal is "true"; + signal rxratedone : STD_LOGIC; + signal \rxratedone_i_1__1_n_0\ : STD_LOGIC; + signal rxratedone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxratedone_reg1 : signal is "NO"; + attribute async_reg of rxratedone_reg1 : signal is "true"; + signal rxratedone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxratedone_reg2 : signal is "NO"; + attribute async_reg of rxratedone_reg2 : signal is "true"; + signal rxresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO"; + attribute async_reg of rxresetdone_reg1 : signal is "true"; + signal rxresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO"; + attribute async_reg of rxresetdone_reg2 : signal is "true"; + signal rxsync_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_done_reg1 : signal is "NO"; + attribute async_reg of rxsync_done_reg1 : signal is "true"; + signal rxsync_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_done_reg2 : signal is "NO"; + attribute async_reg of rxsync_done_reg2 : signal is "true"; + signal \sysclksel[0]_i_1__1_n_0\ : STD_LOGIC; + signal \sysclksel[0]_i_2__1_n_0\ : STD_LOGIC; + signal \txdata_wait_cnt[3]_i_2__1_n_0\ : STD_LOGIC; + signal \txdata_wait_cnt[3]_i_3__1_n_0\ : STD_LOGIC; + signal txdata_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal txpmareset0 : STD_LOGIC; + signal \txpmareset_i_1__1_n_0\ : STD_LOGIC; + signal \txpmareset_i_2__1_n_0\ : STD_LOGIC; + signal txratedone : STD_LOGIC; + signal \txratedone_i_1__1_n_0\ : STD_LOGIC; + signal \txratedone_i_2__1_n_0\ : STD_LOGIC; + signal txratedone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txratedone_reg1 : signal is "NO"; + attribute async_reg of txratedone_reg1 : signal is "true"; + signal txratedone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txratedone_reg2 : signal is "NO"; + attribute async_reg of txratedone_reg2 : signal is "true"; + signal txresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO"; + attribute async_reg of txresetdone_reg1 : signal is "true"; + signal txresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO"; + attribute async_reg of txresetdone_reg2 : signal is "true"; + signal txsync_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_done_reg1 : signal is "NO"; + attribute async_reg of txsync_done_reg1 : signal is "true"; + signal txsync_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_done_reg2 : signal is "NO"; + attribute async_reg of txsync_done_reg2 : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of cplllock_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of cplllock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of cplllock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of cplllock_reg2_reg : label is std.standard.true; + attribute KEEP of cplllock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of cplllock_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \cpllpd_i_2__1\ : label is "soft_lutpair153"; + attribute SOFT_HLUTNM of \cpllreset_i_2__2\ : label is "soft_lutpair154"; + attribute ASYNC_REG_boolean of drp_done_reg1_reg : label is std.standard.true; + attribute KEEP of drp_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of drp_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of drp_done_reg2_reg : label is std.standard.true; + attribute KEEP of drp_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of drp_done_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \drp_start_i_1__1\ : label is "soft_lutpair157"; + attribute SOFT_HLUTNM of \drp_x16_i_1__1\ : label is "soft_lutpair158"; + attribute SOFT_HLUTNM of \drp_x16x20_mode_i_1__1\ : label is "soft_lutpair159"; + attribute SOFT_HLUTNM of \fsm[0]_i_1__4\ : label is "soft_lutpair152"; + attribute SOFT_HLUTNM of \fsm[4]_i_3__1\ : label is "soft_lutpair161"; + attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \pclk_sel_i_2__1\ : label is "soft_lutpair153"; + attribute ASYNC_REG_boolean of phystatus_reg1_reg : label is std.standard.true; + attribute KEEP of phystatus_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of phystatus_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of phystatus_reg2_reg : label is std.standard.true; + attribute KEEP of phystatus_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of phystatus_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of qplllock_reg1_reg : label is std.standard.true; + attribute KEEP of qplllock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of qplllock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of qplllock_reg2_reg : label is std.standard.true; + attribute KEEP of qplllock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of qplllock_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \rate_done_reg1_i_1__1\ : label is "soft_lutpair157"; + attribute SOFT_HLUTNM of \rate_idle_reg1[2]_i_1\ : label is "soft_lutpair159"; + attribute ASYNC_REG_boolean of \rate_in_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_in_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_in_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_in_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg2_reg[1]\ : label is "NO"; + attribute SOFT_HLUTNM of \rate_rxsync_reg1_i_1__1\ : label is "soft_lutpair156"; + attribute SOFT_HLUTNM of \ratedone_i_2__1\ : label is "soft_lutpair155"; + attribute SOFT_HLUTNM of \ratedone_i_3__1\ : label is "soft_lutpair155"; + attribute ASYNC_REG_boolean of resetovrd_done_reg1_reg : label is std.standard.true; + attribute KEEP of resetovrd_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of resetovrd_done_reg2_reg : label is std.standard.true; + attribute KEEP of resetovrd_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_done_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \resetovrd_start_reg1_i_1__1\ : label is "soft_lutpair158"; + attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxpmaresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxpmaresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxratedone_reg1_reg : label is std.standard.true; + attribute KEEP of rxratedone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxratedone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxratedone_reg2_reg : label is std.standard.true; + attribute KEEP of rxratedone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxratedone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_done_reg1_reg : label is std.standard.true; + attribute KEEP of rxsync_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_done_reg2_reg : label is std.standard.true; + attribute KEEP of rxsync_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_done_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \rxsync_start_reg1_i_1__1\ : label is "soft_lutpair156"; + attribute SOFT_HLUTNM of \sysclksel[0]_i_2__1\ : label is "soft_lutpair160"; + attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_2__1\ : label is "soft_lutpair160"; + attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_3__1\ : label is "soft_lutpair152"; + attribute SOFT_HLUTNM of \txpmareset_i_2__1\ : label is "soft_lutpair154"; + attribute SOFT_HLUTNM of \txratedone_i_2__1\ : label is "soft_lutpair161"; + attribute ASYNC_REG_boolean of txratedone_reg1_reg : label is std.standard.true; + attribute KEEP of txratedone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txratedone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txratedone_reg2_reg : label is std.standard.true; + attribute KEEP of txratedone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txratedone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_done_reg1_reg : label is std.standard.true; + attribute KEEP of txsync_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_done_reg2_reg : label is std.standard.true; + attribute KEEP of txsync_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_done_reg2_reg : label is "NO"; +begin + QRST_QPLLPD_IN(0) <= \^qrst_qpllpd_in\(0); + QRST_QPLLRESET_IN(0) <= \^qrst_qpllreset_in\(0); + RXRATE(0) <= \^rxrate\(0); + RXSYSCLKSEL(0) <= \^rxsysclksel\(0); + pipe_pclk_sel_out(0) <= \^pipe_pclk_sel_out\(0); + rate_cpllpd_2 <= \^rate_cpllpd_2\; + rate_cpllreset_2 <= \^rate_cpllreset_2\; + rate_gen3_2 <= \^rate_gen3_2\; + rate_txpmareset_2 <= \^rate_txpmareset_2\; +cplllock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => QRST_CPLLLOCK(0), + Q => cplllock_reg1, + R => RST_CPLLRESET + ); +cplllock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => cplllock_reg1, + Q => cplllock_reg2, + R => RST_CPLLRESET + ); +\cpllpd_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0400FFFF04000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllpd, + I5 => \^rate_cpllpd_2\, + O => \cpllpd_i_1__1_n_0\ + ); +\cpllpd_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000900" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[2]\, + O => qpllpd + ); +cpllpd_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \cpllpd_i_1__1_n_0\, + Q => \^rate_cpllpd_2\, + R => RST_CPLLRESET + ); +\cpllreset_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0400FFFF04000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllreset, + I5 => \^rate_cpllreset_2\, + O => \cpllreset_i_1__2_n_0\ + ); +\cpllreset_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80001004" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm_reg_n_0_[0]\, + O => qpllreset + ); +cpllreset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \cpllreset_i_1__2_n_0\, + Q => \^rate_cpllreset_2\, + R => RST_CPLLRESET + ); +drp_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_DRP_DONE, + Q => drp_done_reg1, + R => RST_CPLLRESET + ); +drp_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => drp_done_reg1, + Q => drp_done_reg2, + R => RST_CPLLRESET + ); +\drp_start_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08420100" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[0]\, + O => \drp_start_i_1__1_n_0\ + ); +drp_start_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \drp_start_i_1__1_n_0\, + Q => RATE_DRP_START, + R => RST_CPLLRESET + ); +\drp_x16_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20100014" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + O => \drp_x16_i_1__1_n_0\ + ); +drp_x16_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \drp_x16_i_1__1_n_0\, + Q => RATE_DRP_X16, + R => RST_CPLLRESET + ); +\drp_x16x20_mode_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20080074" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[1]\, + O => \drp_x16x20_mode_i_1__1_n_0\ + ); +drp_x16x20_mode_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \drp_x16x20_mode_i_1__1_n_0\, + Q => RATE_DRP_X16X20_MODE, + R => RST_CPLLRESET + ); +\fsm[0]_i_10__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0901595100000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => rxsync_done_reg2, + I4 => txsync_done_reg2, + I5 => \fsm_reg_n_0_[3]\, + O => \fsm[0]_i_10__1_n_0\ + ); +\fsm[0]_i_11__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1101111101000110" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => rxpmaresetdone_reg2, + I5 => drp_done_reg2, + O => \fsm[0]_i_11__1_n_0\ + ); +\fsm[0]_i_12__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20202320" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => mmcm_lock_reg2, + I4 => rxpmaresetdone_reg2, + O => \fsm[0]_i_12__1_n_0\ + ); +\fsm[0]_i_1__4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF3210" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm[0]_i_2__4_n_0\, + I3 => \fsm[0]_i_3__1_n_0\, + I4 => \fsm[0]_i_4__1_n_0\, + O => fsm(0) + ); +\fsm[0]_i_2__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0F3F3F47444744" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm[0]_i_5__1_n_0\, + I4 => pll_lock, + I5 => \fsm_reg_n_0_[1]\, + O => \fsm[0]_i_2__4_n_0\ + ); +\fsm[0]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F3F3AAAAFF00AAAA" + ) + port map ( + I0 => \fsm[0]_i_7__1_n_0\, + I1 => \fsm_reg_n_0_[0]\, + I2 => drp_done_reg2, + I3 => \fsm[0]_i_8__1_n_0\, + I4 => \fsm_reg_n_0_[2]\, + I5 => \fsm_reg_n_0_[1]\, + O => \fsm[0]_i_3__1_n_0\ + ); +\fsm[0]_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFF4000000000" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm[0]_i_9__1_n_0\, + I3 => \fsm[0]_i_10__1_n_0\, + I4 => \fsm[0]_i_11__1_n_0\, + I5 => \fsm_reg_n_0_[4]\, + O => \fsm[0]_i_4__1_n_0\ + ); +\fsm[0]_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg1(1), + I2 => rate_in_reg2(0), + I3 => rate_in_reg1(0), + O => \fsm[0]_i_5__1_n_0\ + ); +\fsm[0]_i_6__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => qplllock_reg2, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => cplllock_reg2, + O => pll_lock + ); +\fsm[0]_i_7__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAEAAAAAAA" + ) + port map ( + I0 => \fsm[0]_i_12__1_n_0\, + I1 => pll_lock, + I2 => rst_idle_reg2, + I3 => drp_done_reg2, + I4 => \fsm_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[0]\, + O => \fsm[0]_i_7__1_n_0\ + ); +\fsm[0]_i_8__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF5D5500005D55" + ) + port map ( + I0 => user_active_lane_2, + I1 => txresetdone_reg2, + I2 => phystatus_reg2, + I3 => rxresetdone_reg2, + I4 => \fsm_reg_n_0_[0]\, + I5 => \fsm[1]_i_7__1_n_0\, + O => \fsm[0]_i_8__1_n_0\ + ); +\fsm[0]_i_9__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"33330FAA" + ) + port map ( + I0 => drp_done_reg2, + I1 => resetovrd_done_reg2, + I2 => fsm1, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[1]\, + O => \fsm[0]_i_9__1_n_0\ + ); +\fsm[1]_i_1__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFE4FFE4FFE400E4" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm[1]_i_2__2_n_0\, + I2 => \fsm[1]_i_3__1_n_0\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm[1]_i_4__1_n_0\, + I5 => \fsm[1]_i_5__1_n_0\, + O => fsm(1) + ); +\fsm[1]_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"3388F0CC" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm[1]_i_6__1_n_0\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[2]\, + O => \fsm[1]_i_2__2_n_0\ + ); +\fsm[1]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CC5500000033F000" + ) + port map ( + I0 => \fsm[1]_i_7__1_n_0\, + I1 => drp_done_reg2, + I2 => \fsm[1]_i_8__1_n_0\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[1]_i_3__1_n_0\ + ); +\fsm[1]_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000005FCF0000" + ) + port map ( + I0 => resetovrd_done_reg2, + I1 => drp_done_reg2, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[3]\, + O => \fsm[1]_i_4__1_n_0\ + ); +\fsm[1]_i_5__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"143C547C00000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => rxsync_done_reg2, + I4 => txsync_done_reg2, + I5 => \fsm_reg_n_0_[3]\, + O => \fsm[1]_i_5__1_n_0\ + ); +\fsm[1]_i_6__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"34F7FFFFFFFFFFFF" + ) + port map ( + I0 => qplllock_reg2, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => cplllock_reg2, + I4 => rst_idle_reg2, + I5 => \fsm_reg_n_0_[0]\, + O => \fsm[1]_i_6__1_n_0\ + ); +\fsm[1]_i_7__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => txdata_wait_cnt_reg(3), + I1 => txdata_wait_cnt_reg(1), + I2 => txdata_wait_cnt_reg(0), + I3 => txdata_wait_cnt_reg(2), + O => \fsm[1]_i_7__1_n_0\ + ); +\fsm[1]_i_8__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF04F7FFFF" + ) + port map ( + I0 => qplllock_reg2, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => cplllock_reg2, + I4 => drp_done_reg2, + I5 => rst_idle_reg2, + O => \fsm[1]_i_8__1_n_0\ + ); +\fsm[2]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAFFAAAAAAAAAAAA" + ) + port map ( + I0 => \fsm[2]_i_4__1_n_0\, + I1 => drp_done_reg2, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[2]_i_2__1_n_0\ + ); +\fsm[2]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFBAAAAAAAAAAAAA" + ) + port map ( + I0 => \fsm[2]_i_5__1_n_0\, + I1 => rxsync_done_reg2, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[2]_i_3__1_n_0\ + ); +\fsm[2]_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FA554455005544" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm[3]_i_6__1_n_0\, + I2 => pll_lock, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[0]\, + O => \fsm[2]_i_4__1_n_0\ + ); +\fsm[2]_i_5__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2000FFFF20000000" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => txsync_done_reg2, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm[2]_i_6__1_n_0\, + O => \fsm[2]_i_5__1_n_0\ + ); +\fsm[2]_i_6__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1CDC3C3C1CDCFCFC" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => resetovrd_done_reg2, + I4 => \fsm_reg_n_0_[1]\, + I5 => fsm1, + O => \fsm[2]_i_6__1_n_0\ + ); +\fsm[3]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFB0803080" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => drp_done_reg2, + I5 => \fsm[3]_i_4__1_n_0\, + O => \fsm[3]_i_2__1_n_0\ + ); +\fsm[3]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF8880000F888" + ) + port map ( + I0 => \txdata_wait_cnt[3]_i_2__1_n_0\, + I1 => fsm1, + I2 => resetovrd_done_reg2, + I3 => \sysclksel[0]_i_2__1_n_0\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm[4]_i_2__1_n_0\, + O => \fsm[3]_i_3__1_n_0\ + ); +\fsm[3]_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EEFF00F0" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm[1]_i_8__1_n_0\, + I2 => \fsm[3]_i_6__1_n_0\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[3]_i_4__1_n_0\ + ); +\fsm[3]_i_5__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF8F8FFF8" + ) + port map ( + I0 => \out\, + I1 => \fsm[0]_i_9__1_0\, + I2 => ratedone, + I3 => rate_in_reg2(1), + I4 => rate_in_reg2(0), + I5 => gen3_exit, + O => fsm1 + ); +\fsm[3]_i_6__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00504414" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => rate_in_reg1(0), + I2 => rate_in_reg2(0), + I3 => rate_in_reg1(1), + I4 => rate_in_reg2(1), + O => \fsm[3]_i_6__1_n_0\ + ); +\fsm[4]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C5F0CFF0C0F0C0F0" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm[4]_i_2__1_n_0\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => drp_done_reg2, + I5 => \fsm[4]_i_3__1_n_0\, + O => fsm(4) + ); +\fsm[4]_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"26FF" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => rxsync_done_reg2, + I3 => \fsm_reg_n_0_[2]\, + O => \fsm[4]_i_2__1_n_0\ + ); +\fsm[4]_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[2]\, + O => \fsm[4]_i_3__1_n_0\ + ); +\fsm_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(0), + Q => \fsm_reg_n_0_[0]\, + S => RST_CPLLRESET + ); +\fsm_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(1), + Q => \fsm_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(2), + Q => \fsm_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\fsm_reg[2]_i_1__1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \fsm[2]_i_2__1_n_0\, + I1 => \fsm[2]_i_3__1_n_0\, + O => fsm(2), + S => \fsm_reg_n_0_[4]\ + ); +\fsm_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(3), + Q => \fsm_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\fsm_reg[3]_i_1__1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \fsm[3]_i_2__1_n_0\, + I1 => \fsm[3]_i_3__1_n_0\, + O => fsm(3), + S => \fsm_reg_n_0_[4]\ + ); +\fsm_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(4), + Q => \fsm_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\gen3_exit_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"04FF0400" + ) + port map ( + I0 => rate_in_reg2(0), + I1 => rate_in_reg2(1), + I2 => \fsm_reg_n_0_[4]\, + I3 => \gen3_exit_i_2__1_n_0\, + I4 => gen3_exit, + O => \gen3_exit_i_1__1_n_0\ + ); +\gen3_exit_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000180000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[4]\, + I5 => \fsm[0]_i_5__1_n_0\, + O => \gen3_exit_i_2__1_n_0\ + ); +gen3_exit_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gen3_exit_i_1__1_n_0\, + Q => gen3_exit, + R => RST_CPLLRESET + ); +\gen3_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3FFFFFFB00000008" + ) + port map ( + I0 => \gen3_i_2__1_n_0\, + I1 => \gen3_i_3__1_n_0\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[4]\, + I5 => \^rate_gen3_2\, + O => \gen3_i_1__1_n_0\ + ); +\gen3_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg2(0), + O => \gen3_i_2__1_n_0\ + ); +\gen3_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[0]\, + O => \gen3_i_3__1_n_0\ + ); +gen3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gen3_i_1__1_n_0\, + Q => \^rate_gen3_2\, + R => RST_CPLLRESET + ); +\gtx_channel.gtxe2_channel_i_i_5__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^rate_gen3_2\, + O => rxchbonden_2 + ); +mmcm_lock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_mmcm_lock_in, + Q => mmcm_lock_reg1, + R => RST_CPLLRESET + ); +mmcm_lock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => mmcm_lock_reg1, + Q => mmcm_lock_reg2, + R => RST_CPLLRESET + ); +\pclk_sel_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"14FF1400" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => \pclk_sel_i_2__1_n_0\, + I4 => \^pipe_pclk_sel_out\(0), + O => \pclk_sel_i_1__1_n_0\ + ); +\pclk_sel_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80022000" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + O => \pclk_sel_i_2__1_n_0\ + ); +pclk_sel_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pclk_sel_i_1__1_n_0\, + Q => \^pipe_pclk_sel_out\(0), + R => RST_CPLLRESET + ); +\phystatus_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008000000" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \txratedone_i_2__1_n_0\, + I3 => \fsm_reg_n_0_[0]\, + I4 => phystatus_reg2, + I5 => phystatus, + O => \phystatus_i_1__1_n_0\ + ); +phystatus_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \phystatus_i_1__1_n_0\, + Q => phystatus, + R => RST_CPLLRESET + ); +phystatus_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_PHYSTATUS, + Q => phystatus_reg1, + R => RST_CPLLRESET + ); +phystatus_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => phystatus_reg1, + Q => phystatus_reg2, + R => RST_CPLLRESET + ); +qplllock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_QPLLLOCK, + Q => qplllock_reg1, + R => RST_CPLLRESET + ); +qplllock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qplllock_reg1, + Q => qplllock_reg2, + R => RST_CPLLRESET + ); +\qpllpd_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF40440000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllpd, + I5 => \^qrst_qpllpd_in\(0), + O => \qpllpd_i_1__2_n_0\ + ); +qpllpd_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \qpllpd_i_1__2_n_0\, + Q => \^qrst_qpllpd_in\(0), + R => RST_CPLLRESET + ); +\qpllreset_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF40440000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllreset, + I5 => \^qrst_qpllreset_in\(0), + O => \qpllreset_i_1__2_n_0\ + ); +qpllreset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \qpllreset_i_1__2_n_0\, + Q => \^qrst_qpllreset_in\(0), + R => RST_CPLLRESET + ); +\rate_done_reg1_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000080" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[1]\, + O => USER_RATE_DONE + ); +\rate_idle_reg1[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[3]\, + O => SYNC_RATE_IDLE + ); +\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rate_in_reg1_reg[0]_0\(0), + Q => rate_in_reg1(0), + R => RST_CPLLRESET + ); +\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rate_in_reg1(1), + R => RST_CPLLRESET + ); +\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_in_reg1(0), + Q => rate_in_reg2(0), + R => RST_CPLLRESET + ); +\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_in_reg1(1), + Q => rate_in_reg2(1), + R => RST_CPLLRESET + ); +\rate_out[0]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0444FFFF04440000" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg2(0), + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \rate_out[0]_i_2__1_n_0\, + I5 => \^rxrate\(0), + O => \rate_out[0]_i_1__1_n_0\ + ); +\rate_out[0]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8002020080000200" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => txpmareset0, + O => \rate_out[0]_i_2__1_n_0\ + ); +\rate_out[0]_i_3__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => gen3_exit, + I1 => rate_in_reg2(0), + I2 => rate_in_reg2(1), + O => txpmareset0 + ); +\rate_out_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rate_out[0]_i_1__1_n_0\, + Q => \^rxrate\(0), + R => RST_CPLLRESET + ); +\rate_rxsync_reg1_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08800000" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[2]\, + O => USER_RATE_RXSYNC + ); +\ratedone_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A3333333A0000000" + ) + port map ( + I0 => \ratedone_i_2__1_n_0\, + I1 => \ratedone_i_3__1_n_0\, + I2 => rxratedone, + I3 => phystatus, + I4 => txratedone, + I5 => ratedone, + O => \ratedone_i_1__1_n_0\ + ); +\ratedone_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00080000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + O => \ratedone_i_2__1_n_0\ + ); +\ratedone_i_3__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FDFFFFFF" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[4]\, + O => \ratedone_i_3__1_n_0\ + ); +ratedone_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \ratedone_i_1__1_n_0\, + Q => ratedone, + R => RST_CPLLRESET + ); +resetovrd_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '1', + Q => resetovrd_done_reg1, + R => RST_CPLLRESET + ); +resetovrd_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => resetovrd_done_reg1, + Q => resetovrd_done_reg2, + R => RST_CPLLRESET + ); +\resetovrd_start_reg1_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000080" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[3]\, + O => USER_RESETOVRD_START + ); +rst_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RST_IDLE, + Q => rst_idle_reg1, + R => RST_CPLLRESET + ); +rst_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rst_idle_reg1, + Q => rst_idle_reg2, + R => RST_CPLLRESET + ); +rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxpmaresetdone_reg1, + R => RST_CPLLRESET + ); +rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxpmaresetdone_reg1, + Q => rxpmaresetdone_reg2, + R => RST_CPLLRESET + ); +\rxratedone_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008000000" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \txratedone_i_2__1_n_0\, + I3 => \fsm_reg_n_0_[0]\, + I4 => rxratedone_reg2, + I5 => rxratedone, + O => \rxratedone_i_1__1_n_0\ + ); +rxratedone_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxratedone_i_1__1_n_0\, + Q => rxratedone, + R => RST_CPLLRESET + ); +rxratedone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_RXRATEDONE, + Q => rxratedone_reg1, + R => RST_CPLLRESET + ); +rxratedone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxratedone_reg1, + Q => rxratedone_reg2, + R => RST_CPLLRESET + ); +rxresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RXRESETDONE, + Q => rxresetdone_reg1, + R => RST_CPLLRESET + ); +rxresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxresetdone_reg1, + Q => rxresetdone_reg2, + R => RST_CPLLRESET + ); +rxsync_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxsync_done_reg1, + R => RST_CPLLRESET + ); +rxsync_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsync_done_reg1, + Q => rxsync_done_reg2, + R => RST_CPLLRESET + ); +\rxsync_start_reg1_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm_reg_n_0_[3]\, + O => SYNC_RXSYNC_START + ); +\sysclksel[0]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0FFFFF4F00000040" + ) + port map ( + I0 => rate_in_reg2(0), + I1 => rate_in_reg2(1), + I2 => \sysclksel[0]_i_2__1_n_0\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[4]\, + I5 => \^rxsysclksel\(0), + O => \sysclksel[0]_i_1__1_n_0\ + ); +\sysclksel[0]_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + O => \sysclksel[0]_i_2__1_n_0\ + ); +\sysclksel_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \sysclksel[0]_i_1__1_n_0\, + Q => \^rxsysclksel\(0), + R => RST_CPLLRESET + ); +\txdata_wait_cnt[0]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B333000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2__1_n_0\, + I5 => \txdata_wait_cnt[3]_i_3__1_n_0\, + O => \p_0_in__0\(0) + ); +\txdata_wait_cnt[1]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"E666000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2__1_n_0\, + I5 => \txdata_wait_cnt[3]_i_3__1_n_0\, + O => \p_0_in__0\(1) + ); +\txdata_wait_cnt[2]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F878000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2__1_n_0\, + I5 => \txdata_wait_cnt[3]_i_3__1_n_0\, + O => \p_0_in__0\(2) + ); +\txdata_wait_cnt[3]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF80000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2__1_n_0\, + I5 => \txdata_wait_cnt[3]_i_3__1_n_0\, + O => \p_0_in__0\(3) + ); +\txdata_wait_cnt[3]_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \txdata_wait_cnt[3]_i_2__1_n_0\ + ); +\txdata_wait_cnt[3]_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + O => \txdata_wait_cnt[3]_i_3__1_n_0\ + ); +\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(0), + Q => txdata_wait_cnt_reg(0), + R => RST_CPLLRESET + ); +\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(1), + Q => txdata_wait_cnt_reg(1), + R => RST_CPLLRESET + ); +\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(2), + Q => txdata_wait_cnt_reg(2), + R => RST_CPLLRESET + ); +\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(3), + Q => txdata_wait_cnt_reg(3), + R => RST_CPLLRESET + ); +\txpmareset_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00F2FFFF00F20000" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg2(0), + I2 => gen3_exit, + I3 => \fsm_reg_n_0_[3]\, + I4 => \txpmareset_i_2__1_n_0\, + I5 => \^rate_txpmareset_2\, + O => \txpmareset_i_1__1_n_0\ + ); +\txpmareset_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80004200" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[4]\, + O => \txpmareset_i_2__1_n_0\ + ); +txpmareset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpmareset_i_1__1_n_0\, + Q => \^rate_txpmareset_2\, + R => RST_CPLLRESET + ); +\txratedone_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008000000" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \txratedone_i_2__1_n_0\, + I3 => \fsm_reg_n_0_[0]\, + I4 => txratedone_reg2, + I5 => txratedone, + O => \txratedone_i_1__1_n_0\ + ); +\txratedone_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[1]\, + O => \txratedone_i_2__1_n_0\ + ); +txratedone_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txratedone_i_1__1_n_0\, + Q => txratedone, + R => RST_CPLLRESET + ); +txratedone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_TXRATEDONE, + Q => txratedone_reg1, + R => RST_CPLLRESET + ); +txratedone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txratedone_reg1, + Q => txratedone_reg2, + R => RST_CPLLRESET + ); +txresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_TXRESETDONE, + Q => txresetdone_reg1, + R => RST_CPLLRESET + ); +txresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txresetdone_reg1, + Q => txresetdone_reg2, + R => RST_CPLLRESET + ); +txsync_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_TXSYNC_DONE, + Q => txsync_done_reg1, + R => RST_CPLLRESET + ); +txsync_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_done_reg1, + Q => txsync_done_reg2, + R => RST_CPLLRESET + ); +\txsync_start_reg1_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00004000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[2]\, + I5 => RST_TXSYNC_START, + O => SYNC_TXSYNC_START + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_rate_52 is + port ( + SYNC_TXSYNC_START : out STD_LOGIC; + rxchbonden_3 : out STD_LOGIC; + rate_gen3_3 : out STD_LOGIC; + RATE_DRP_START : out STD_LOGIC; + RATE_DRP_X16X20_MODE : out STD_LOGIC; + RATE_DRP_X16 : out STD_LOGIC; + USER_RATE_RXSYNC : out STD_LOGIC; + SYNC_RXSYNC_START : out STD_LOGIC; + USER_RATE_DONE : out STD_LOGIC; + USER_RESETOVRD_START : out STD_LOGIC; + SYNC_RATE_IDLE : out STD_LOGIC; + rate_txpmareset_3 : out STD_LOGIC; + RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 0 to 0 ); + RXRATE : out STD_LOGIC_VECTOR ( 0 to 0 ); + QRST_QPLLPD_IN : out STD_LOGIC_VECTOR ( 0 to 0 ); + rate_cpllpd_3 : out STD_LOGIC; + QRST_QPLLRESET_IN : out STD_LOGIC_VECTOR ( 0 to 0 ); + rate_cpllreset_3 : out STD_LOGIC; + RST_TXSYNC_START : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + \rate_in_reg1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RST_IDLE : in STD_LOGIC; + QRST_CPLLLOCK : in STD_LOGIC_VECTOR ( 0 to 0 ); + QPLL_QPLLLOCK : in STD_LOGIC; + RATE_DRP_DONE : in STD_LOGIC; + pipe_mmcm_lock_in : in STD_LOGIC; + RATE_PHYSTATUS : in STD_LOGIC; + USER_TXRESETDONE : in STD_LOGIC; + USER_RXRESETDONE : in STD_LOGIC; + RATE_TXRATEDONE : in STD_LOGIC; + RATE_RXRATEDONE : in STD_LOGIC; + RATE_TXSYNC_DONE : in STD_LOGIC; + user_active_lane_3 : in STD_LOGIC; + \out\ : in STD_LOGIC; + \fsm[0]_i_9__2_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_rate_52 : entity is "pcie_7x_0_pipe_rate"; +end pcie_7x_0_pcie_7x_0_pipe_rate_52; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_rate_52 is + signal \^qrst_qpllpd_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^qrst_qpllreset_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^rxrate\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal cplllock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of cplllock_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of cplllock_reg1 : signal is "true"; + signal cplllock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of cplllock_reg2 : signal is "NO"; + attribute async_reg of cplllock_reg2 : signal is "true"; + signal \cpllpd_i_1__2_n_0\ : STD_LOGIC; + signal \cpllreset_i_1__3_n_0\ : STD_LOGIC; + signal drp_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO"; + attribute async_reg of drp_done_reg1 : signal is "true"; + signal drp_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO"; + attribute async_reg of drp_done_reg2 : signal is "true"; + signal \drp_start_i_1__2_n_0\ : STD_LOGIC; + signal \drp_x16_i_1__2_n_0\ : STD_LOGIC; + signal \drp_x16x20_mode_i_1__2_n_0\ : STD_LOGIC; + signal fsm : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal fsm1 : STD_LOGIC; + signal \fsm[0]_i_10__2_n_0\ : STD_LOGIC; + signal \fsm[0]_i_11__2_n_0\ : STD_LOGIC; + signal \fsm[0]_i_12__2_n_0\ : STD_LOGIC; + signal \fsm[0]_i_2__6_n_0\ : STD_LOGIC; + signal \fsm[0]_i_3__2_n_0\ : STD_LOGIC; + signal \fsm[0]_i_4__2_n_0\ : STD_LOGIC; + signal \fsm[0]_i_5__2_n_0\ : STD_LOGIC; + signal \fsm[0]_i_7__2_n_0\ : STD_LOGIC; + signal \fsm[0]_i_8__2_n_0\ : STD_LOGIC; + signal \fsm[0]_i_9__2_n_0\ : STD_LOGIC; + signal \fsm[1]_i_2__3_n_0\ : STD_LOGIC; + signal \fsm[1]_i_3__2_n_0\ : STD_LOGIC; + signal \fsm[1]_i_4__2_n_0\ : STD_LOGIC; + signal \fsm[1]_i_5__2_n_0\ : STD_LOGIC; + signal \fsm[1]_i_6__2_n_0\ : STD_LOGIC; + signal \fsm[1]_i_7__2_n_0\ : STD_LOGIC; + signal \fsm[1]_i_8__2_n_0\ : STD_LOGIC; + signal \fsm[2]_i_2__2_n_0\ : STD_LOGIC; + signal \fsm[2]_i_3__2_n_0\ : STD_LOGIC; + signal \fsm[2]_i_4__2_n_0\ : STD_LOGIC; + signal \fsm[2]_i_5__2_n_0\ : STD_LOGIC; + signal \fsm[2]_i_6__2_n_0\ : STD_LOGIC; + signal \fsm[3]_i_2__2_n_0\ : STD_LOGIC; + signal \fsm[3]_i_3__2_n_0\ : STD_LOGIC; + signal \fsm[3]_i_4__2_n_0\ : STD_LOGIC; + signal \fsm[3]_i_6__2_n_0\ : STD_LOGIC; + signal \fsm[4]_i_2__2_n_0\ : STD_LOGIC; + signal \fsm[4]_i_3__2_n_0\ : STD_LOGIC; + signal \fsm_reg_n_0_[0]\ : STD_LOGIC; + signal \fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \fsm_reg_n_0_[2]\ : STD_LOGIC; + signal \fsm_reg_n_0_[3]\ : STD_LOGIC; + signal \fsm_reg_n_0_[4]\ : STD_LOGIC; + signal gen3_exit : STD_LOGIC; + signal \gen3_exit_i_1__2_n_0\ : STD_LOGIC; + signal \gen3_exit_i_2__2_n_0\ : STD_LOGIC; + signal \gen3_i_1__2_n_0\ : STD_LOGIC; + signal \gen3_i_2__2_n_0\ : STD_LOGIC; + signal \gen3_i_3__2_n_0\ : STD_LOGIC; + signal mmcm_lock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO"; + attribute async_reg of mmcm_lock_reg1 : signal is "true"; + signal mmcm_lock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO"; + attribute async_reg of mmcm_lock_reg2 : signal is "true"; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \pclk_sel_i_1__2_n_0\ : STD_LOGIC; + signal \pclk_sel_i_2__2_n_0\ : STD_LOGIC; + signal phystatus : STD_LOGIC; + signal \phystatus_i_1__2_n_0\ : STD_LOGIC; + signal phystatus_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of phystatus_reg1 : signal is "NO"; + attribute async_reg of phystatus_reg1 : signal is "true"; + signal phystatus_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of phystatus_reg2 : signal is "NO"; + attribute async_reg of phystatus_reg2 : signal is "true"; + signal \^pipe_pclk_sel_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal pll_lock : STD_LOGIC; + signal qplllock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of qplllock_reg1 : signal is "NO"; + attribute async_reg of qplllock_reg1 : signal is "true"; + signal qplllock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of qplllock_reg2 : signal is "NO"; + attribute async_reg of qplllock_reg2 : signal is "true"; + signal qpllpd : STD_LOGIC; + signal \qpllpd_i_1__3_n_0\ : STD_LOGIC; + signal qpllreset : STD_LOGIC; + signal \qpllreset_i_1__3_n_0\ : STD_LOGIC; + signal \^rate_cpllpd_3\ : STD_LOGIC; + signal \^rate_cpllreset_3\ : STD_LOGIC; + signal \^rate_gen3_3\ : STD_LOGIC; + signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_in_reg1 : signal is "NO"; + attribute async_reg of rate_in_reg1 : signal is "true"; + signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_in_reg2 : signal is "NO"; + attribute async_reg of rate_in_reg2 : signal is "true"; + signal \rate_out[0]_i_1__2_n_0\ : STD_LOGIC; + signal \rate_out[0]_i_2__2_n_0\ : STD_LOGIC; + signal \^rate_txpmareset_3\ : STD_LOGIC; + signal ratedone : STD_LOGIC; + signal \ratedone_i_1__2_n_0\ : STD_LOGIC; + signal \ratedone_i_2__2_n_0\ : STD_LOGIC; + signal \ratedone_i_3__2_n_0\ : STD_LOGIC; + signal resetovrd_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_done_reg1 : signal is "NO"; + attribute async_reg of resetovrd_done_reg1 : signal is "true"; + signal resetovrd_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_done_reg2 : signal is "NO"; + attribute async_reg of resetovrd_done_reg2 : signal is "true"; + signal rst_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO"; + attribute async_reg of rst_idle_reg1 : signal is "true"; + signal rst_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO"; + attribute async_reg of rst_idle_reg2 : signal is "true"; + signal rxpmaresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg1 : signal is "NO"; + attribute async_reg of rxpmaresetdone_reg1 : signal is "true"; + signal rxpmaresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg2 : signal is "NO"; + attribute async_reg of rxpmaresetdone_reg2 : signal is "true"; + signal rxratedone : STD_LOGIC; + signal \rxratedone_i_1__2_n_0\ : STD_LOGIC; + signal rxratedone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxratedone_reg1 : signal is "NO"; + attribute async_reg of rxratedone_reg1 : signal is "true"; + signal rxratedone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxratedone_reg2 : signal is "NO"; + attribute async_reg of rxratedone_reg2 : signal is "true"; + signal rxresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO"; + attribute async_reg of rxresetdone_reg1 : signal is "true"; + signal rxresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO"; + attribute async_reg of rxresetdone_reg2 : signal is "true"; + signal rxsync_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_done_reg1 : signal is "NO"; + attribute async_reg of rxsync_done_reg1 : signal is "true"; + signal rxsync_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_done_reg2 : signal is "NO"; + attribute async_reg of rxsync_done_reg2 : signal is "true"; + signal \sysclksel[0]_i_1__2_n_0\ : STD_LOGIC; + signal \sysclksel[0]_i_2__2_n_0\ : STD_LOGIC; + signal \txdata_wait_cnt[3]_i_2__2_n_0\ : STD_LOGIC; + signal \txdata_wait_cnt[3]_i_3__2_n_0\ : STD_LOGIC; + signal txdata_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal txpmareset0 : STD_LOGIC; + signal \txpmareset_i_1__2_n_0\ : STD_LOGIC; + signal \txpmareset_i_2__2_n_0\ : STD_LOGIC; + signal txratedone : STD_LOGIC; + signal \txratedone_i_1__2_n_0\ : STD_LOGIC; + signal \txratedone_i_2__2_n_0\ : STD_LOGIC; + signal txratedone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txratedone_reg1 : signal is "NO"; + attribute async_reg of txratedone_reg1 : signal is "true"; + signal txratedone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txratedone_reg2 : signal is "NO"; + attribute async_reg of txratedone_reg2 : signal is "true"; + signal txresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO"; + attribute async_reg of txresetdone_reg1 : signal is "true"; + signal txresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO"; + attribute async_reg of txresetdone_reg2 : signal is "true"; + signal txsync_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_done_reg1 : signal is "NO"; + attribute async_reg of txsync_done_reg1 : signal is "true"; + signal txsync_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_done_reg2 : signal is "NO"; + attribute async_reg of txsync_done_reg2 : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of cplllock_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of cplllock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of cplllock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of cplllock_reg2_reg : label is std.standard.true; + attribute KEEP of cplllock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of cplllock_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \cpllpd_i_2__2\ : label is "soft_lutpair194"; + attribute SOFT_HLUTNM of \cpllreset_i_2__3\ : label is "soft_lutpair195"; + attribute ASYNC_REG_boolean of drp_done_reg1_reg : label is std.standard.true; + attribute KEEP of drp_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of drp_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of drp_done_reg2_reg : label is std.standard.true; + attribute KEEP of drp_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of drp_done_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \drp_start_i_1__2\ : label is "soft_lutpair198"; + attribute SOFT_HLUTNM of \drp_x16_i_1__2\ : label is "soft_lutpair199"; + attribute SOFT_HLUTNM of \drp_x16x20_mode_i_1__2\ : label is "soft_lutpair200"; + attribute SOFT_HLUTNM of \fsm[0]_i_1__6\ : label is "soft_lutpair193"; + attribute SOFT_HLUTNM of \fsm[4]_i_3__2\ : label is "soft_lutpair202"; + attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \pclk_sel_i_2__2\ : label is "soft_lutpair194"; + attribute ASYNC_REG_boolean of phystatus_reg1_reg : label is std.standard.true; + attribute KEEP of phystatus_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of phystatus_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of phystatus_reg2_reg : label is std.standard.true; + attribute KEEP of phystatus_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of phystatus_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of qplllock_reg1_reg : label is std.standard.true; + attribute KEEP of qplllock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of qplllock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of qplllock_reg2_reg : label is std.standard.true; + attribute KEEP of qplllock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of qplllock_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \rate_done_reg1_i_1__2\ : label is "soft_lutpair198"; + attribute SOFT_HLUTNM of \rate_idle_reg1[3]_i_1\ : label is "soft_lutpair200"; + attribute ASYNC_REG_boolean of \rate_in_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_in_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_in_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_in_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_in_reg2_reg[1]\ : label is "NO"; + attribute SOFT_HLUTNM of \rate_rxsync_reg1_i_1__2\ : label is "soft_lutpair197"; + attribute SOFT_HLUTNM of \ratedone_i_2__2\ : label is "soft_lutpair196"; + attribute SOFT_HLUTNM of \ratedone_i_3__2\ : label is "soft_lutpair196"; + attribute ASYNC_REG_boolean of resetovrd_done_reg1_reg : label is std.standard.true; + attribute KEEP of resetovrd_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of resetovrd_done_reg2_reg : label is std.standard.true; + attribute KEEP of resetovrd_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_done_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \resetovrd_start_reg1_i_1__2\ : label is "soft_lutpair199"; + attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxpmaresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxpmaresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxpmaresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxratedone_reg1_reg : label is std.standard.true; + attribute KEEP of rxratedone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxratedone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxratedone_reg2_reg : label is std.standard.true; + attribute KEEP of rxratedone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxratedone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_done_reg1_reg : label is std.standard.true; + attribute KEEP of rxsync_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_done_reg2_reg : label is std.standard.true; + attribute KEEP of rxsync_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_done_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \rxsync_start_reg1_i_1__2\ : label is "soft_lutpair197"; + attribute SOFT_HLUTNM of \sysclksel[0]_i_2__2\ : label is "soft_lutpair201"; + attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_2__2\ : label is "soft_lutpair201"; + attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_3__2\ : label is "soft_lutpair193"; + attribute SOFT_HLUTNM of \txpmareset_i_2__2\ : label is "soft_lutpair195"; + attribute SOFT_HLUTNM of \txratedone_i_2__2\ : label is "soft_lutpair202"; + attribute ASYNC_REG_boolean of txratedone_reg1_reg : label is std.standard.true; + attribute KEEP of txratedone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txratedone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txratedone_reg2_reg : label is std.standard.true; + attribute KEEP of txratedone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txratedone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_done_reg1_reg : label is std.standard.true; + attribute KEEP of txsync_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_done_reg2_reg : label is std.standard.true; + attribute KEEP of txsync_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_done_reg2_reg : label is "NO"; +begin + QRST_QPLLPD_IN(0) <= \^qrst_qpllpd_in\(0); + QRST_QPLLRESET_IN(0) <= \^qrst_qpllreset_in\(0); + RXRATE(0) <= \^rxrate\(0); + RXSYSCLKSEL(0) <= \^rxsysclksel\(0); + pipe_pclk_sel_out(0) <= \^pipe_pclk_sel_out\(0); + rate_cpllpd_3 <= \^rate_cpllpd_3\; + rate_cpllreset_3 <= \^rate_cpllreset_3\; + rate_gen3_3 <= \^rate_gen3_3\; + rate_txpmareset_3 <= \^rate_txpmareset_3\; +cplllock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => QRST_CPLLLOCK(0), + Q => cplllock_reg1, + R => RST_CPLLRESET + ); +cplllock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => cplllock_reg1, + Q => cplllock_reg2, + R => RST_CPLLRESET + ); +\cpllpd_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0400FFFF04000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllpd, + I5 => \^rate_cpllpd_3\, + O => \cpllpd_i_1__2_n_0\ + ); +\cpllpd_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000900" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[2]\, + O => qpllpd + ); +cpllpd_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \cpllpd_i_1__2_n_0\, + Q => \^rate_cpllpd_3\, + R => RST_CPLLRESET + ); +\cpllreset_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0400FFFF04000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllreset, + I5 => \^rate_cpllreset_3\, + O => \cpllreset_i_1__3_n_0\ + ); +\cpllreset_i_2__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80001004" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm_reg_n_0_[0]\, + O => qpllreset + ); +cpllreset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \cpllreset_i_1__3_n_0\, + Q => \^rate_cpllreset_3\, + R => RST_CPLLRESET + ); +drp_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_DRP_DONE, + Q => drp_done_reg1, + R => RST_CPLLRESET + ); +drp_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => drp_done_reg1, + Q => drp_done_reg2, + R => RST_CPLLRESET + ); +\drp_start_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08420100" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[0]\, + O => \drp_start_i_1__2_n_0\ + ); +drp_start_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \drp_start_i_1__2_n_0\, + Q => RATE_DRP_START, + R => RST_CPLLRESET + ); +\drp_x16_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20100014" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + O => \drp_x16_i_1__2_n_0\ + ); +drp_x16_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \drp_x16_i_1__2_n_0\, + Q => RATE_DRP_X16, + R => RST_CPLLRESET + ); +\drp_x16x20_mode_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20080074" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[1]\, + O => \drp_x16x20_mode_i_1__2_n_0\ + ); +drp_x16x20_mode_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \drp_x16x20_mode_i_1__2_n_0\, + Q => RATE_DRP_X16X20_MODE, + R => RST_CPLLRESET + ); +\fsm[0]_i_10__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0901595100000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => rxsync_done_reg2, + I4 => txsync_done_reg2, + I5 => \fsm_reg_n_0_[3]\, + O => \fsm[0]_i_10__2_n_0\ + ); +\fsm[0]_i_11__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1101111101000110" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => rxpmaresetdone_reg2, + I5 => drp_done_reg2, + O => \fsm[0]_i_11__2_n_0\ + ); +\fsm[0]_i_12__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20202320" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => mmcm_lock_reg2, + I4 => rxpmaresetdone_reg2, + O => \fsm[0]_i_12__2_n_0\ + ); +\fsm[0]_i_1__6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF3210" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm[0]_i_2__6_n_0\, + I3 => \fsm[0]_i_3__2_n_0\, + I4 => \fsm[0]_i_4__2_n_0\, + O => fsm(0) + ); +\fsm[0]_i_2__6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0F3F3F47444744" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm[0]_i_5__2_n_0\, + I4 => pll_lock, + I5 => \fsm_reg_n_0_[1]\, + O => \fsm[0]_i_2__6_n_0\ + ); +\fsm[0]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F3F3AAAAFF00AAAA" + ) + port map ( + I0 => \fsm[0]_i_7__2_n_0\, + I1 => \fsm_reg_n_0_[0]\, + I2 => drp_done_reg2, + I3 => \fsm[0]_i_8__2_n_0\, + I4 => \fsm_reg_n_0_[2]\, + I5 => \fsm_reg_n_0_[1]\, + O => \fsm[0]_i_3__2_n_0\ + ); +\fsm[0]_i_4__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFF4000000000" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm[0]_i_9__2_n_0\, + I3 => \fsm[0]_i_10__2_n_0\, + I4 => \fsm[0]_i_11__2_n_0\, + I5 => \fsm_reg_n_0_[4]\, + O => \fsm[0]_i_4__2_n_0\ + ); +\fsm[0]_i_5__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg1(1), + I2 => rate_in_reg2(0), + I3 => rate_in_reg1(0), + O => \fsm[0]_i_5__2_n_0\ + ); +\fsm[0]_i_6__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => qplllock_reg2, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => cplllock_reg2, + O => pll_lock + ); +\fsm[0]_i_7__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAEAAAAAAA" + ) + port map ( + I0 => \fsm[0]_i_12__2_n_0\, + I1 => pll_lock, + I2 => rst_idle_reg2, + I3 => drp_done_reg2, + I4 => \fsm_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[0]\, + O => \fsm[0]_i_7__2_n_0\ + ); +\fsm[0]_i_8__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF5D5500005D55" + ) + port map ( + I0 => user_active_lane_3, + I1 => txresetdone_reg2, + I2 => phystatus_reg2, + I3 => rxresetdone_reg2, + I4 => \fsm_reg_n_0_[0]\, + I5 => \fsm[1]_i_7__2_n_0\, + O => \fsm[0]_i_8__2_n_0\ + ); +\fsm[0]_i_9__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"33330FAA" + ) + port map ( + I0 => drp_done_reg2, + I1 => resetovrd_done_reg2, + I2 => fsm1, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[1]\, + O => \fsm[0]_i_9__2_n_0\ + ); +\fsm[1]_i_1__6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFE4FFE4FFE400E4" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm[1]_i_2__3_n_0\, + I2 => \fsm[1]_i_3__2_n_0\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm[1]_i_4__2_n_0\, + I5 => \fsm[1]_i_5__2_n_0\, + O => fsm(1) + ); +\fsm[1]_i_2__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"3388F0CC" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm[1]_i_6__2_n_0\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[2]\, + O => \fsm[1]_i_2__3_n_0\ + ); +\fsm[1]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CC5500000033F000" + ) + port map ( + I0 => \fsm[1]_i_7__2_n_0\, + I1 => drp_done_reg2, + I2 => \fsm[1]_i_8__2_n_0\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[1]_i_3__2_n_0\ + ); +\fsm[1]_i_4__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000005FCF0000" + ) + port map ( + I0 => resetovrd_done_reg2, + I1 => drp_done_reg2, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[3]\, + O => \fsm[1]_i_4__2_n_0\ + ); +\fsm[1]_i_5__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"143C547C00000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => rxsync_done_reg2, + I4 => txsync_done_reg2, + I5 => \fsm_reg_n_0_[3]\, + O => \fsm[1]_i_5__2_n_0\ + ); +\fsm[1]_i_6__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"34F7FFFFFFFFFFFF" + ) + port map ( + I0 => qplllock_reg2, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => cplllock_reg2, + I4 => rst_idle_reg2, + I5 => \fsm_reg_n_0_[0]\, + O => \fsm[1]_i_6__2_n_0\ + ); +\fsm[1]_i_7__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => txdata_wait_cnt_reg(3), + I1 => txdata_wait_cnt_reg(1), + I2 => txdata_wait_cnt_reg(0), + I3 => txdata_wait_cnt_reg(2), + O => \fsm[1]_i_7__2_n_0\ + ); +\fsm[1]_i_8__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF04F7FFFF" + ) + port map ( + I0 => qplllock_reg2, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => cplllock_reg2, + I4 => drp_done_reg2, + I5 => rst_idle_reg2, + O => \fsm[1]_i_8__2_n_0\ + ); +\fsm[2]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAFFAAAAAAAAAAAA" + ) + port map ( + I0 => \fsm[2]_i_4__2_n_0\, + I1 => drp_done_reg2, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[2]_i_2__2_n_0\ + ); +\fsm[2]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFBAAAAAAAAAAAAA" + ) + port map ( + I0 => \fsm[2]_i_5__2_n_0\, + I1 => rxsync_done_reg2, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[2]_i_3__2_n_0\ + ); +\fsm[2]_i_4__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FA554455005544" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm[3]_i_6__2_n_0\, + I2 => pll_lock, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[0]\, + O => \fsm[2]_i_4__2_n_0\ + ); +\fsm[2]_i_5__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2000FFFF20000000" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => txsync_done_reg2, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm[2]_i_6__2_n_0\, + O => \fsm[2]_i_5__2_n_0\ + ); +\fsm[2]_i_6__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1CDC3C3C1CDCFCFC" + ) + port map ( + I0 => drp_done_reg2, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => resetovrd_done_reg2, + I4 => \fsm_reg_n_0_[1]\, + I5 => fsm1, + O => \fsm[2]_i_6__2_n_0\ + ); +\fsm[3]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFB0803080" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => drp_done_reg2, + I5 => \fsm[3]_i_4__2_n_0\, + O => \fsm[3]_i_2__2_n_0\ + ); +\fsm[3]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF8880000F888" + ) + port map ( + I0 => \txdata_wait_cnt[3]_i_2__2_n_0\, + I1 => fsm1, + I2 => resetovrd_done_reg2, + I3 => \sysclksel[0]_i_2__2_n_0\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm[4]_i_2__2_n_0\, + O => \fsm[3]_i_3__2_n_0\ + ); +\fsm[3]_i_4__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EEFF00F0" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm[1]_i_8__2_n_0\, + I2 => \fsm[3]_i_6__2_n_0\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => \fsm_reg_n_0_[2]\, + O => \fsm[3]_i_4__2_n_0\ + ); +\fsm[3]_i_5__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF8F8FFF8" + ) + port map ( + I0 => \out\, + I1 => \fsm[0]_i_9__2_0\, + I2 => ratedone, + I3 => rate_in_reg2(1), + I4 => rate_in_reg2(0), + I5 => gen3_exit, + O => fsm1 + ); +\fsm[3]_i_6__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00504414" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => rate_in_reg1(0), + I2 => rate_in_reg2(0), + I3 => rate_in_reg1(1), + I4 => rate_in_reg2(1), + O => \fsm[3]_i_6__2_n_0\ + ); +\fsm[4]_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C5F0CFF0C0F0C0F0" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm[4]_i_2__2_n_0\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => drp_done_reg2, + I5 => \fsm[4]_i_3__2_n_0\, + O => fsm(4) + ); +\fsm[4]_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"26FF" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => rxsync_done_reg2, + I3 => \fsm_reg_n_0_[2]\, + O => \fsm[4]_i_2__2_n_0\ + ); +\fsm[4]_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[2]\, + O => \fsm[4]_i_3__2_n_0\ + ); +\fsm_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(0), + Q => \fsm_reg_n_0_[0]\, + S => RST_CPLLRESET + ); +\fsm_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(1), + Q => \fsm_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(2), + Q => \fsm_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\fsm_reg[2]_i_1__2\: unisim.vcomponents.MUXF7 + port map ( + I0 => \fsm[2]_i_2__2_n_0\, + I1 => \fsm[2]_i_3__2_n_0\, + O => fsm(2), + S => \fsm_reg_n_0_[4]\ + ); +\fsm_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(3), + Q => \fsm_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\fsm_reg[3]_i_1__2\: unisim.vcomponents.MUXF7 + port map ( + I0 => \fsm[3]_i_2__2_n_0\, + I1 => \fsm[3]_i_3__2_n_0\, + O => fsm(3), + S => \fsm_reg_n_0_[4]\ + ); +\fsm_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => fsm(4), + Q => \fsm_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\gen3_exit_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"04FF0400" + ) + port map ( + I0 => rate_in_reg2(0), + I1 => rate_in_reg2(1), + I2 => \fsm_reg_n_0_[4]\, + I3 => \gen3_exit_i_2__2_n_0\, + I4 => gen3_exit, + O => \gen3_exit_i_1__2_n_0\ + ); +\gen3_exit_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000180000000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[4]\, + I5 => \fsm[0]_i_5__2_n_0\, + O => \gen3_exit_i_2__2_n_0\ + ); +gen3_exit_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gen3_exit_i_1__2_n_0\, + Q => gen3_exit, + R => RST_CPLLRESET + ); +\gen3_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3FFFFFFB00000008" + ) + port map ( + I0 => \gen3_i_2__2_n_0\, + I1 => \gen3_i_3__2_n_0\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[4]\, + I5 => \^rate_gen3_3\, + O => \gen3_i_1__2_n_0\ + ); +\gen3_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg2(0), + O => \gen3_i_2__2_n_0\ + ); +\gen3_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[0]\, + O => \gen3_i_3__2_n_0\ + ); +gen3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \gen3_i_1__2_n_0\, + Q => \^rate_gen3_3\, + R => RST_CPLLRESET + ); +\gtx_channel.gtxe2_channel_i_i_5__2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^rate_gen3_3\, + O => rxchbonden_3 + ); +mmcm_lock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_mmcm_lock_in, + Q => mmcm_lock_reg1, + R => RST_CPLLRESET + ); +mmcm_lock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => mmcm_lock_reg1, + Q => mmcm_lock_reg2, + R => RST_CPLLRESET + ); +\pclk_sel_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"14FF1400" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => rate_in_reg2(1), + I2 => rate_in_reg2(0), + I3 => \pclk_sel_i_2__2_n_0\, + I4 => \^pipe_pclk_sel_out\(0), + O => \pclk_sel_i_1__2_n_0\ + ); +\pclk_sel_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80022000" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + O => \pclk_sel_i_2__2_n_0\ + ); +pclk_sel_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \pclk_sel_i_1__2_n_0\, + Q => \^pipe_pclk_sel_out\(0), + R => RST_CPLLRESET + ); +\phystatus_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008000000" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \txratedone_i_2__2_n_0\, + I3 => \fsm_reg_n_0_[0]\, + I4 => phystatus_reg2, + I5 => phystatus, + O => \phystatus_i_1__2_n_0\ + ); +phystatus_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \phystatus_i_1__2_n_0\, + Q => phystatus, + R => RST_CPLLRESET + ); +phystatus_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_PHYSTATUS, + Q => phystatus_reg1, + R => RST_CPLLRESET + ); +phystatus_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => phystatus_reg1, + Q => phystatus_reg2, + R => RST_CPLLRESET + ); +qplllock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => QPLL_QPLLLOCK, + Q => qplllock_reg1, + R => RST_CPLLRESET + ); +qplllock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qplllock_reg1, + Q => qplllock_reg2, + R => RST_CPLLRESET + ); +\qpllpd_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF40440000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllpd, + I5 => \^qrst_qpllpd_in\(0), + O => \qpllpd_i_1__3_n_0\ + ); +qpllpd_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \qpllpd_i_1__3_n_0\, + Q => \^qrst_qpllpd_in\(0), + R => RST_CPLLRESET + ); +\qpllreset_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044FFFF40440000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => rate_in_reg2(0), + I3 => rate_in_reg2(1), + I4 => qpllreset, + I5 => \^qrst_qpllreset_in\(0), + O => \qpllreset_i_1__3_n_0\ + ); +qpllreset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \qpllreset_i_1__3_n_0\, + Q => \^qrst_qpllreset_in\(0), + R => RST_CPLLRESET + ); +\rate_done_reg1_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000080" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[1]\, + O => USER_RATE_DONE + ); +\rate_idle_reg1[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[3]\, + O => SYNC_RATE_IDLE + ); +\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rate_in_reg1_reg[0]_0\(0), + Q => rate_in_reg1(0), + R => RST_CPLLRESET + ); +\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rate_in_reg1(1), + R => RST_CPLLRESET + ); +\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_in_reg1(0), + Q => rate_in_reg2(0), + R => RST_CPLLRESET + ); +\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_in_reg1(1), + Q => rate_in_reg2(1), + R => RST_CPLLRESET + ); +\rate_out[0]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0444FFFF04440000" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg2(0), + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \rate_out[0]_i_2__2_n_0\, + I5 => \^rxrate\(0), + O => \rate_out[0]_i_1__2_n_0\ + ); +\rate_out[0]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8002020080000200" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm_reg_n_0_[3]\, + I5 => txpmareset0, + O => \rate_out[0]_i_2__2_n_0\ + ); +\rate_out[0]_i_3__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => gen3_exit, + I1 => rate_in_reg2(0), + I2 => rate_in_reg2(1), + O => txpmareset0 + ); +\rate_out_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rate_out[0]_i_1__2_n_0\, + Q => \^rxrate\(0), + R => RST_CPLLRESET + ); +\rate_rxsync_reg1_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08800000" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[2]\, + O => USER_RATE_RXSYNC + ); +\ratedone_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A3333333A0000000" + ) + port map ( + I0 => \ratedone_i_2__2_n_0\, + I1 => \ratedone_i_3__2_n_0\, + I2 => rxratedone, + I3 => phystatus, + I4 => txratedone, + I5 => ratedone, + O => \ratedone_i_1__2_n_0\ + ); +\ratedone_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00080000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[4]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[0]\, + O => \ratedone_i_2__2_n_0\ + ); +\ratedone_i_3__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FDFFFFFF" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[4]\, + O => \ratedone_i_3__2_n_0\ + ); +ratedone_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \ratedone_i_1__2_n_0\, + Q => ratedone, + R => RST_CPLLRESET + ); +resetovrd_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '1', + Q => resetovrd_done_reg1, + R => RST_CPLLRESET + ); +resetovrd_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => resetovrd_done_reg1, + Q => resetovrd_done_reg2, + R => RST_CPLLRESET + ); +\resetovrd_start_reg1_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000080" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[0]\, + I4 => \fsm_reg_n_0_[3]\, + O => USER_RESETOVRD_START + ); +rst_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RST_IDLE, + Q => rst_idle_reg1, + R => RST_CPLLRESET + ); +rst_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rst_idle_reg1, + Q => rst_idle_reg2, + R => RST_CPLLRESET + ); +rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxpmaresetdone_reg1, + R => RST_CPLLRESET + ); +rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxpmaresetdone_reg1, + Q => rxpmaresetdone_reg2, + R => RST_CPLLRESET + ); +\rxratedone_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008000000" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \txratedone_i_2__2_n_0\, + I3 => \fsm_reg_n_0_[0]\, + I4 => rxratedone_reg2, + I5 => rxratedone, + O => \rxratedone_i_1__2_n_0\ + ); +rxratedone_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxratedone_i_1__2_n_0\, + Q => rxratedone, + R => RST_CPLLRESET + ); +rxratedone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_RXRATEDONE, + Q => rxratedone_reg1, + R => RST_CPLLRESET + ); +rxratedone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxratedone_reg1, + Q => rxratedone_reg2, + R => RST_CPLLRESET + ); +rxresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RXRESETDONE, + Q => rxresetdone_reg1, + R => RST_CPLLRESET + ); +rxresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxresetdone_reg1, + Q => rxresetdone_reg2, + R => RST_CPLLRESET + ); +rxsync_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxsync_done_reg1, + R => RST_CPLLRESET + ); +rxsync_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsync_done_reg1, + Q => rxsync_done_reg2, + R => RST_CPLLRESET + ); +\rxsync_start_reg1_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08000000" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm_reg_n_0_[3]\, + O => SYNC_RXSYNC_START + ); +\sysclksel[0]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0FFFFF4F00000040" + ) + port map ( + I0 => rate_in_reg2(0), + I1 => rate_in_reg2(1), + I2 => \sysclksel[0]_i_2__2_n_0\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[4]\, + I5 => \^rxsysclksel\(0), + O => \sysclksel[0]_i_1__2_n_0\ + ); +\sysclksel[0]_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[0]\, + O => \sysclksel[0]_i_2__2_n_0\ + ); +\sysclksel_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \sysclksel[0]_i_1__2_n_0\, + Q => \^rxsysclksel\(0), + R => RST_CPLLRESET + ); +\txdata_wait_cnt[0]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B333000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2__2_n_0\, + I5 => \txdata_wait_cnt[3]_i_3__2_n_0\, + O => \p_0_in__0\(0) + ); +\txdata_wait_cnt[1]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"E666000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2__2_n_0\, + I5 => \txdata_wait_cnt[3]_i_3__2_n_0\, + O => \p_0_in__0\(1) + ); +\txdata_wait_cnt[2]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F878000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2__2_n_0\, + I5 => \txdata_wait_cnt[3]_i_3__2_n_0\, + O => \p_0_in__0\(2) + ); +\txdata_wait_cnt[3]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF80000000000000" + ) + port map ( + I0 => txdata_wait_cnt_reg(1), + I1 => txdata_wait_cnt_reg(0), + I2 => txdata_wait_cnt_reg(2), + I3 => txdata_wait_cnt_reg(3), + I4 => \txdata_wait_cnt[3]_i_2__2_n_0\, + I5 => \txdata_wait_cnt[3]_i_3__2_n_0\, + O => \p_0_in__0\(3) + ); +\txdata_wait_cnt[3]_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[2]\, + O => \txdata_wait_cnt[3]_i_2__2_n_0\ + ); +\txdata_wait_cnt[3]_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[4]\, + O => \txdata_wait_cnt[3]_i_3__2_n_0\ + ); +\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(0), + Q => txdata_wait_cnt_reg(0), + R => RST_CPLLRESET + ); +\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(1), + Q => txdata_wait_cnt_reg(1), + R => RST_CPLLRESET + ); +\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(2), + Q => txdata_wait_cnt_reg(2), + R => RST_CPLLRESET + ); +\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(3), + Q => txdata_wait_cnt_reg(3), + R => RST_CPLLRESET + ); +\txpmareset_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00F2FFFF00F20000" + ) + port map ( + I0 => rate_in_reg2(1), + I1 => rate_in_reg2(0), + I2 => gen3_exit, + I3 => \fsm_reg_n_0_[3]\, + I4 => \txpmareset_i_2__2_n_0\, + I5 => \^rate_txpmareset_3\, + O => \txpmareset_i_1__2_n_0\ + ); +\txpmareset_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80004200" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[4]\, + O => \txpmareset_i_2__2_n_0\ + ); +txpmareset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpmareset_i_1__2_n_0\, + Q => \^rate_txpmareset_3\, + R => RST_CPLLRESET + ); +\txratedone_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008000000" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[2]\, + I2 => \txratedone_i_2__2_n_0\, + I3 => \fsm_reg_n_0_[0]\, + I4 => txratedone_reg2, + I5 => txratedone, + O => \txratedone_i_1__2_n_0\ + ); +\txratedone_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[1]\, + O => \txratedone_i_2__2_n_0\ + ); +txratedone_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txratedone_i_1__2_n_0\, + Q => txratedone, + R => RST_CPLLRESET + ); +txratedone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_TXRATEDONE, + Q => txratedone_reg1, + R => RST_CPLLRESET + ); +txratedone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txratedone_reg1, + Q => txratedone_reg2, + R => RST_CPLLRESET + ); +txresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_TXRESETDONE, + Q => txresetdone_reg1, + R => RST_CPLLRESET + ); +txresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txresetdone_reg1, + Q => txresetdone_reg2, + R => RST_CPLLRESET + ); +txsync_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => RATE_TXSYNC_DONE, + Q => txsync_done_reg1, + R => RST_CPLLRESET + ); +txsync_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_done_reg1, + Q => txsync_done_reg2, + R => RST_CPLLRESET + ); +\txsync_start_reg1_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00004000" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[3]\, + I4 => \fsm_reg_n_0_[2]\, + I5 => RST_TXSYNC_START, + O => SYNC_TXSYNC_START + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_reset is + port ( + SS : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + RST_CPLLRESET : out STD_LOGIC; + RST_RXUSRCLK_RESET : out STD_LOGIC; + RST_DCLK_RESET : out STD_LOGIC; + DRP_GTXRESET : out STD_LOGIC; + rst_userrdy : out STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + pipe_mmcm_lock_in : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 3 downto 0 ); + QRST_CPLLLOCK : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rate_idle_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \drp_done_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \phystatus_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \txsync_done_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_rxusrclk_in : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + QRST_IDLE : in STD_LOGIC; + \rxcdrlock_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \out\ : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_pipe_reset; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_reset is + signal \^drp_gtxreset\ : STD_LOGIC; + signal \FSM_onehot_fsm[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[10]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[13]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[14]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[14]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[14]_i_4_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[1]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[2]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[3]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[5]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[8]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[8]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[8]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[9]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[13]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[14]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[8]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[9]\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \cfg_wait_cnt[5]_i_2_n_0\ : STD_LOGIC; + signal cfg_wait_cnt_reg : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal cplllock_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of cplllock_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of cplllock_reg1 : signal is "true"; + signal cplllock_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of cplllock_reg2 : signal is "NO"; + attribute async_reg of cplllock_reg2 : signal is "true"; + signal cpllpd : STD_LOGIC; + signal cpllreset : STD_LOGIC; + signal cpllreset_i_1_n_0 : STD_LOGIC; + signal cpllreset_i_2_n_0 : STD_LOGIC; + signal dclk_rst : STD_LOGIC; + signal dclk_rst_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of dclk_rst_reg1 : signal is "NO"; + attribute async_reg of dclk_rst_reg1 : signal is "true"; + signal dclk_rst_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of dclk_rst_reg2 : signal is "NO"; + attribute async_reg of dclk_rst_reg2 : signal is "true"; + signal drp_done_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO"; + attribute async_reg of drp_done_reg1 : signal is "true"; + signal drp_done_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO"; + attribute async_reg of drp_done_reg2 : signal is "true"; + signal gtreset_i_1_n_0 : STD_LOGIC; + signal mmcm_lock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO"; + attribute async_reg of mmcm_lock_reg1 : signal is "true"; + signal mmcm_lock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO"; + attribute async_reg of mmcm_lock_reg2 : signal is "true"; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal phystatus_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of phystatus_reg1 : signal is "NO"; + attribute async_reg of phystatus_reg1 : signal is "true"; + signal phystatus_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of phystatus_reg2 : signal is "NO"; + attribute async_reg of phystatus_reg2 : signal is "true"; + signal qpll_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of qpll_idle_reg1 : signal is "NO"; + attribute async_reg of qpll_idle_reg1 : signal is "true"; + signal qpll_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of qpll_idle_reg2 : signal is "NO"; + attribute async_reg of qpll_idle_reg2 : signal is "true"; + signal rate_idle_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO"; + attribute async_reg of rate_idle_reg1 : signal is "true"; + signal rate_idle_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO"; + attribute async_reg of rate_idle_reg2 : signal is "true"; + signal resetdone_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of resetdone_reg1 : signal is "NO"; + attribute async_reg of resetdone_reg1 : signal is "true"; + signal resetdone_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of resetdone_reg2 : signal is "NO"; + attribute async_reg of resetdone_reg2 : signal is "true"; + signal \^rst_userrdy\ : STD_LOGIC; + signal rxcdrlock_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO"; + attribute async_reg of rxcdrlock_reg1 : signal is "true"; + signal rxcdrlock_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO"; + attribute async_reg of rxcdrlock_reg2 : signal is "true"; + signal rxpmaresetdone_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rxpmaresetdone_reg1 : signal is "NO"; + attribute async_reg of rxpmaresetdone_reg1 : signal is "true"; + signal rxpmaresetdone_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rxpmaresetdone_reg2 : signal is "NO"; + attribute async_reg of rxpmaresetdone_reg2 : signal is "true"; + signal rxusrclk_rst_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxusrclk_rst_reg1 : signal is "NO"; + attribute async_reg of rxusrclk_rst_reg1 : signal is "true"; + signal rxusrclk_rst_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxusrclk_rst_reg2 : signal is "NO"; + attribute async_reg of rxusrclk_rst_reg2 : signal is "true"; + signal txsync_done_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txsync_done_reg1 : signal is "NO"; + attribute async_reg of txsync_done_reg1 : signal is "true"; + signal txsync_done_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txsync_done_reg2 : signal is "NO"; + attribute async_reg of txsync_done_reg2 : signal is "true"; + signal userrdy : STD_LOGIC; + signal userrdy_i_1_n_0 : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_fsm[0]_i_1\ : label is "soft_lutpair206"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[0]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[10]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[13]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[14]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[5]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[8]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[9]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000"; + attribute SOFT_HLUTNM of \cfg_wait_cnt[0]_i_1\ : label is "soft_lutpair206"; + attribute SOFT_HLUTNM of \cfg_wait_cnt[1]_i_1\ : label is "soft_lutpair204"; + attribute SOFT_HLUTNM of \cfg_wait_cnt[2]_i_1\ : label is "soft_lutpair204"; + attribute SOFT_HLUTNM of \cfg_wait_cnt[4]_i_1\ : label is "soft_lutpair205"; + attribute SOFT_HLUTNM of \cfg_wait_cnt[5]_i_1\ : label is "soft_lutpair205"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \cplllock_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \cplllock_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of dclk_rst_reg1_reg : label is std.standard.true; + attribute KEEP of dclk_rst_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of dclk_rst_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of dclk_rst_reg2_reg : label is std.standard.true; + attribute KEEP of dclk_rst_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of dclk_rst_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of \drp_done_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \drp_done_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \drp_done_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \drp_done_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \drp_done_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \drp_done_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \drp_done_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \drp_done_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \drp_done_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \drp_done_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \drp_done_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \drp_done_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \drp_done_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \drp_done_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \drp_done_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \drp_done_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \drp_done_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \drp_done_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \drp_done_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \drp_done_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \drp_done_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \drp_done_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \drp_done_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \drp_done_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of \phystatus_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \phystatus_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \phystatus_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \phystatus_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \phystatus_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \phystatus_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \phystatus_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \phystatus_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \phystatus_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \phystatus_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \phystatus_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \phystatus_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \phystatus_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \phystatus_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \phystatus_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \phystatus_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \phystatus_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \phystatus_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \phystatus_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \phystatus_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \phystatus_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \phystatus_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \phystatus_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \phystatus_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of qpll_idle_reg1_reg : label is std.standard.true; + attribute KEEP of qpll_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of qpll_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of qpll_idle_reg2_reg : label is std.standard.true; + attribute KEEP of qpll_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of qpll_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of \rate_idle_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_idle_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_idle_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_idle_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_idle_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_idle_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_idle_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rate_idle_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_idle_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_idle_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rate_idle_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_idle_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_idle_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_idle_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_idle_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_idle_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_idle_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_idle_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_idle_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rate_idle_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_idle_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_idle_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rate_idle_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_idle_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \resetdone_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \resetdone_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \resetdone_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \resetdone_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \resetdone_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \resetdone_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \resetdone_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \resetdone_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \resetdone_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \resetdone_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \resetdone_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \resetdone_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \resetdone_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \resetdone_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \resetdone_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \resetdone_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \resetdone_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \resetdone_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \resetdone_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \resetdone_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \resetdone_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \resetdone_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \resetdone_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \resetdone_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxcdrlock_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxcdrlock_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxcdrlock_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxcdrlock_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxcdrlock_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxcdrlock_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxcdrlock_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxcdrlock_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxcdrlock_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxcdrlock_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxcdrlock_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxcdrlock_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxcdrlock_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxcdrlock_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxcdrlock_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxcdrlock_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxcdrlock_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxcdrlock_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxcdrlock_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxcdrlock_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxcdrlock_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxcdrlock_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxcdrlock_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxcdrlock_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxpmaresetdone_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxpmaresetdone_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxpmaresetdone_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxpmaresetdone_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxpmaresetdone_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxpmaresetdone_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxpmaresetdone_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxpmaresetdone_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxpmaresetdone_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxpmaresetdone_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxpmaresetdone_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxpmaresetdone_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxpmaresetdone_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxpmaresetdone_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxpmaresetdone_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxpmaresetdone_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxpmaresetdone_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxpmaresetdone_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxpmaresetdone_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxpmaresetdone_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxpmaresetdone_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxpmaresetdone_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxpmaresetdone_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxpmaresetdone_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of rxusrclk_rst_reg1_reg : label is std.standard.true; + attribute KEEP of rxusrclk_rst_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxusrclk_rst_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxusrclk_rst_reg2_reg : label is std.standard.true; + attribute KEEP of rxusrclk_rst_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxusrclk_rst_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of \txsync_done_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txsync_done_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txsync_done_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txsync_done_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txsync_done_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txsync_done_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txsync_done_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txsync_done_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txsync_done_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txsync_done_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txsync_done_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txsync_done_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txsync_done_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txsync_done_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txsync_done_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txsync_done_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txsync_done_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txsync_done_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txsync_done_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txsync_done_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txsync_done_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txsync_done_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txsync_done_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txsync_done_reg2_reg[3]\ : label is "NO"; +begin + DRP_GTXRESET <= \^drp_gtxreset\; + Q(1 downto 0) <= \^q\(1 downto 0); + RST_CPLLRESET <= cpllreset; + RST_DCLK_RESET <= dclk_rst_reg2; + RST_RXUSRCLK_RESET <= rxusrclk_rst_reg2; + SS(0) <= \^ss\(0); + rst_userrdy <= \^rst_userrdy\; +\FSM_onehot_fsm[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4F44" + ) + port map ( + I0 => \FSM_onehot_fsm[1]_i_2_n_0\, + I1 => \FSM_onehot_fsm_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm[8]_i_2_n_0\, + I3 => \FSM_onehot_fsm_reg_n_0_[0]\, + O => \FSM_onehot_fsm[0]_i_1_n_0\ + ); +\FSM_onehot_fsm[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAAAAAAAAAAAAA" + ) + port map ( + I0 => \^q\(1), + I1 => txsync_done_reg2(3), + I2 => txsync_done_reg2(0), + I3 => txsync_done_reg2(2), + I4 => txsync_done_reg2(1), + I5 => \FSM_onehot_fsm_reg_n_0_[9]\, + O => \FSM_onehot_fsm[10]_i_1_n_0\ + ); +\FSM_onehot_fsm[13]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[14]\, + I1 => rate_idle_reg2(3), + I2 => rate_idle_reg2(0), + I3 => rate_idle_reg2(2), + I4 => rate_idle_reg2(1), + O => \FSM_onehot_fsm[13]_i_1_n_0\ + ); +\FSM_onehot_fsm[14]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \out\, + O => \^ss\(0) + ); +\FSM_onehot_fsm[14]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => \FSM_onehot_fsm[14]_i_3_n_0\, + I1 => \FSM_onehot_fsm_reg_n_0_[14]\, + I2 => \FSM_onehot_fsm[14]_i_4_n_0\, + I3 => \FSM_onehot_fsm_reg_n_0_[8]\, + O => \FSM_onehot_fsm[14]_i_2_n_0\ + ); +\FSM_onehot_fsm[14]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => rate_idle_reg2(1), + I1 => rate_idle_reg2(2), + I2 => rate_idle_reg2(0), + I3 => rate_idle_reg2(3), + O => \FSM_onehot_fsm[14]_i_3_n_0\ + ); +\FSM_onehot_fsm[14]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => cplllock_reg2(3), + I1 => cplllock_reg2(0), + I2 => cplllock_reg2(2), + I3 => cplllock_reg2(1), + O => \FSM_onehot_fsm[14]_i_4_n_0\ + ); +\FSM_onehot_fsm[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[1]\, + I1 => \FSM_onehot_fsm[1]_i_2_n_0\, + O => \FSM_onehot_fsm[1]_i_1_n_0\ + ); +\FSM_onehot_fsm[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFFFFFFFFFF" + ) + port map ( + I0 => cfg_wait_cnt_reg(4), + I1 => cfg_wait_cnt_reg(3), + I2 => cfg_wait_cnt_reg(5), + I3 => cfg_wait_cnt_reg(0), + I4 => cfg_wait_cnt_reg(1), + I5 => cfg_wait_cnt_reg(2), + O => \FSM_onehot_fsm[1]_i_2_n_0\ + ); +\FSM_onehot_fsm[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0008000000000000" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => \FSM_onehot_fsm[2]_i_2_n_0\, + I2 => phystatus_reg2(1), + I3 => phystatus_reg2(0), + I4 => resetdone_reg2(1), + I5 => resetdone_reg2(0), + O => \FSM_onehot_fsm[2]_i_1_n_0\ + ); +\FSM_onehot_fsm[2]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1000" + ) + port map ( + I0 => phystatus_reg2(3), + I1 => phystatus_reg2(2), + I2 => resetdone_reg2(3), + I3 => resetdone_reg2(2), + O => \FSM_onehot_fsm[2]_i_2_n_0\ + ); +\FSM_onehot_fsm[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEAAAAAAAA" + ) + port map ( + I0 => cpllpd, + I1 => txsync_done_reg2(3), + I2 => txsync_done_reg2(0), + I3 => txsync_done_reg2(2), + I4 => txsync_done_reg2(1), + I5 => \^q\(0), + O => \FSM_onehot_fsm[3]_i_1_n_0\ + ); +\FSM_onehot_fsm[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => userrdy, + I1 => mmcm_lock_reg2, + I2 => \FSM_onehot_fsm[4]_i_2_n_0\, + I3 => \FSM_onehot_fsm_reg_n_0_[4]\, + O => \FSM_onehot_fsm[4]_i_1_n_0\ + ); +\FSM_onehot_fsm[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFF7FFFF" + ) + port map ( + I0 => resetdone_reg2(0), + I1 => resetdone_reg2(1), + I2 => phystatus_reg2(0), + I3 => phystatus_reg2(1), + I4 => \FSM_onehot_fsm[2]_i_2_n_0\, + O => \FSM_onehot_fsm[4]_i_2_n_0\ + ); +\FSM_onehot_fsm[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[13]\, + I1 => mmcm_lock_reg2, + I2 => userrdy, + O => \FSM_onehot_fsm[5]_i_1_n_0\ + ); +\FSM_onehot_fsm[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F444" + ) + port map ( + I0 => \FSM_onehot_fsm[14]_i_4_n_0\, + I1 => \FSM_onehot_fsm_reg_n_0_[8]\, + I2 => \FSM_onehot_fsm[8]_i_2_n_0\, + I3 => \FSM_onehot_fsm_reg_n_0_[0]\, + O => \FSM_onehot_fsm[8]_i_1_n_0\ + ); +\FSM_onehot_fsm[8]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => resetdone_reg2(1), + I1 => resetdone_reg2(2), + I2 => resetdone_reg2(0), + I3 => resetdone_reg2(3), + I4 => \FSM_onehot_fsm[8]_i_3_n_0\, + O => \FSM_onehot_fsm[8]_i_2_n_0\ + ); +\FSM_onehot_fsm[8]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => cplllock_reg2(3), + I1 => cplllock_reg2(1), + I2 => cplllock_reg2(2), + I3 => cplllock_reg2(0), + O => \FSM_onehot_fsm[8]_i_3_n_0\ + ); +\FSM_onehot_fsm[9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2AAAAAAB2AAAAAAA" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[9]\, + I1 => txsync_done_reg2(3), + I2 => txsync_done_reg2(0), + I3 => txsync_done_reg2(2), + I4 => txsync_done_reg2(1), + I5 => \^q\(0), + O => \FSM_onehot_fsm[9]_i_1_n_0\ + ); +\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[0]_i_1_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[0]\, + R => \^ss\(0) + ); +\FSM_onehot_fsm_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[10]_i_1_n_0\, + Q => \^q\(1), + R => \^ss\(0) + ); +\FSM_onehot_fsm_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[13]_i_1_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[13]\, + R => \^ss\(0) + ); +\FSM_onehot_fsm_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[14]_i_2_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[14]\, + R => \^ss\(0) + ); +\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[1]_i_1_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[1]\, + S => \^ss\(0) + ); +\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[2]_i_1_n_0\, + Q => cpllpd, + R => \^ss\(0) + ); +\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[3]_i_1_n_0\, + Q => \^q\(0), + R => \^ss\(0) + ); +\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[4]_i_1_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[4]\, + R => \^ss\(0) + ); +\FSM_onehot_fsm_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[5]_i_1_n_0\, + Q => userrdy, + R => \^ss\(0) + ); +\FSM_onehot_fsm_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[8]_i_1_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[8]\, + R => \^ss\(0) + ); +\FSM_onehot_fsm_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[9]_i_1_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[9]\, + R => \^ss\(0) + ); +\cfg_wait_cnt[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"2A" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[1]\, + I1 => \FSM_onehot_fsm[1]_i_2_n_0\, + I2 => cfg_wait_cnt_reg(0), + O => \p_0_in__0\(0) + ); +\cfg_wait_cnt[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"28AA" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[1]\, + I1 => cfg_wait_cnt_reg(0), + I2 => cfg_wait_cnt_reg(1), + I3 => \FSM_onehot_fsm[1]_i_2_n_0\, + O => \p_0_in__0\(1) + ); +\cfg_wait_cnt[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"2888AAAA" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[1]\, + I1 => cfg_wait_cnt_reg(2), + I2 => cfg_wait_cnt_reg(1), + I3 => cfg_wait_cnt_reg(0), + I4 => \FSM_onehot_fsm[1]_i_2_n_0\, + O => \p_0_in__0\(2) + ); +\cfg_wait_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"28888888AAAAAAAA" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[1]\, + I1 => cfg_wait_cnt_reg(3), + I2 => cfg_wait_cnt_reg(0), + I3 => cfg_wait_cnt_reg(1), + I4 => cfg_wait_cnt_reg(2), + I5 => \FSM_onehot_fsm[1]_i_2_n_0\, + O => \p_0_in__0\(3) + ); +\cfg_wait_cnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EA006A00" + ) + port map ( + I0 => cfg_wait_cnt_reg(4), + I1 => \cfg_wait_cnt[5]_i_2_n_0\, + I2 => cfg_wait_cnt_reg(3), + I3 => \FSM_onehot_fsm_reg_n_0_[1]\, + I4 => cfg_wait_cnt_reg(5), + O => \p_0_in__0\(4) + ); +\cfg_wait_cnt[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8888888" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[1]\, + I1 => cfg_wait_cnt_reg(5), + I2 => \cfg_wait_cnt[5]_i_2_n_0\, + I3 => cfg_wait_cnt_reg(3), + I4 => cfg_wait_cnt_reg(4), + O => \p_0_in__0\(5) + ); +\cfg_wait_cnt[5]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => cfg_wait_cnt_reg(2), + I1 => cfg_wait_cnt_reg(1), + I2 => cfg_wait_cnt_reg(0), + O => \cfg_wait_cnt[5]_i_2_n_0\ + ); +\cfg_wait_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(0), + Q => cfg_wait_cnt_reg(0), + R => \^ss\(0) + ); +\cfg_wait_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(1), + Q => cfg_wait_cnt_reg(1), + R => \^ss\(0) + ); +\cfg_wait_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(2), + Q => cfg_wait_cnt_reg(2), + R => \^ss\(0) + ); +\cfg_wait_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(3), + Q => cfg_wait_cnt_reg(3), + R => \^ss\(0) + ); +\cfg_wait_cnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(4), + Q => cfg_wait_cnt_reg(4), + R => \^ss\(0) + ); +\cfg_wait_cnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(5), + Q => cfg_wait_cnt_reg(5), + R => \^ss\(0) + ); +\cplllock_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => QRST_CPLLLOCK(0), + Q => cplllock_reg1(0), + R => \^ss\(0) + ); +\cplllock_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => QRST_CPLLLOCK(1), + Q => cplllock_reg1(1), + R => \^ss\(0) + ); +\cplllock_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => QRST_CPLLLOCK(2), + Q => cplllock_reg1(2), + R => \^ss\(0) + ); +\cplllock_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => QRST_CPLLLOCK(3), + Q => cplllock_reg1(3), + R => \^ss\(0) + ); +\cplllock_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => cplllock_reg1(0), + Q => cplllock_reg2(0), + R => \^ss\(0) + ); +\cplllock_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => cplllock_reg1(1), + Q => cplllock_reg2(1), + R => \^ss\(0) + ); +\cplllock_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => cplllock_reg1(2), + Q => cplllock_reg2(2), + R => \^ss\(0) + ); +\cplllock_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => cplllock_reg1(3), + Q => cplllock_reg2(3), + R => \^ss\(0) + ); +cpllreset_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEAAAAAAAA" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[0]\, + I1 => \^q\(1), + I2 => userrdy, + I3 => \FSM_onehot_fsm_reg_n_0_[1]\, + I4 => cpllreset_i_2_n_0, + I5 => cpllreset, + O => cpllreset_i_1_n_0 + ); +cpllreset_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \^q\(0), + I1 => cpllpd, + I2 => \FSM_onehot_fsm_reg_n_0_[9]\, + I3 => \FSM_onehot_fsm_reg_n_0_[14]\, + I4 => \FSM_onehot_fsm_reg_n_0_[13]\, + I5 => \FSM_onehot_fsm_reg_n_0_[4]\, + O => cpllreset_i_2_n_0 + ); +cpllreset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => cpllreset_i_1_n_0, + Q => cpllreset, + R => \^ss\(0) + ); +dclk_rst_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_reg_n_0_[1]\, + Q => dclk_rst, + R => '0' + ); +dclk_rst_reg1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => dclk_rst, + Q => dclk_rst_reg1, + R => '0' + ); +dclk_rst_reg2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => dclk_rst_reg1, + Q => dclk_rst_reg2, + R => '0' + ); +\drp_done_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \drp_done_reg1_reg[3]_0\(0), + Q => drp_done_reg1(0), + R => \^ss\(0) + ); +\drp_done_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \drp_done_reg1_reg[3]_0\(1), + Q => drp_done_reg1(1), + R => \^ss\(0) + ); +\drp_done_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \drp_done_reg1_reg[3]_0\(2), + Q => drp_done_reg1(2), + R => \^ss\(0) + ); +\drp_done_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \drp_done_reg1_reg[3]_0\(3), + Q => drp_done_reg1(3), + R => \^ss\(0) + ); +\drp_done_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => drp_done_reg1(0), + Q => drp_done_reg2(0), + R => \^ss\(0) + ); +\drp_done_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => drp_done_reg1(1), + Q => drp_done_reg2(1), + R => \^ss\(0) + ); +\drp_done_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => drp_done_reg1(2), + Q => drp_done_reg2(2), + R => \^ss\(0) + ); +\drp_done_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => drp_done_reg1(3), + Q => drp_done_reg2(3), + R => \^ss\(0) + ); +gtreset_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"DC" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[13]\, + I1 => \FSM_onehot_fsm_reg_n_0_[0]\, + I2 => \^drp_gtxreset\, + O => gtreset_i_1_n_0 + ); +gtreset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => gtreset_i_1_n_0, + Q => \^drp_gtxreset\, + R => \^ss\(0) + ); +mmcm_lock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_mmcm_lock_in, + Q => mmcm_lock_reg1, + R => \^ss\(0) + ); +mmcm_lock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => mmcm_lock_reg1, + Q => mmcm_lock_reg2, + R => \^ss\(0) + ); +\phystatus_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \phystatus_reg1_reg[3]_0\(0), + Q => phystatus_reg1(0), + R => \^ss\(0) + ); +\phystatus_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \phystatus_reg1_reg[3]_0\(1), + Q => phystatus_reg1(1), + R => \^ss\(0) + ); +\phystatus_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \phystatus_reg1_reg[3]_0\(2), + Q => phystatus_reg1(2), + R => \^ss\(0) + ); +\phystatus_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \phystatus_reg1_reg[3]_0\(3), + Q => phystatus_reg1(3), + R => \^ss\(0) + ); +\phystatus_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => phystatus_reg1(0), + Q => phystatus_reg2(0), + R => \^ss\(0) + ); +\phystatus_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => phystatus_reg1(1), + Q => phystatus_reg2(1), + R => \^ss\(0) + ); +\phystatus_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => phystatus_reg1(2), + Q => phystatus_reg2(2), + R => \^ss\(0) + ); +\phystatus_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => phystatus_reg1(3), + Q => phystatus_reg2(3), + R => \^ss\(0) + ); +qpll_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => QRST_IDLE, + Q => qpll_idle_reg1, + R => \^ss\(0) + ); +qpll_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qpll_idle_reg1, + Q => qpll_idle_reg2, + R => \^ss\(0) + ); +\rate_idle_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rate_idle_reg1_reg[3]_0\(0), + Q => rate_idle_reg1(0), + R => \^ss\(0) + ); +\rate_idle_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rate_idle_reg1_reg[3]_0\(1), + Q => rate_idle_reg1(1), + R => \^ss\(0) + ); +\rate_idle_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rate_idle_reg1_reg[3]_0\(2), + Q => rate_idle_reg1(2), + R => \^ss\(0) + ); +\rate_idle_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rate_idle_reg1_reg[3]_0\(3), + Q => rate_idle_reg1(3), + R => \^ss\(0) + ); +\rate_idle_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_idle_reg1(0), + Q => rate_idle_reg2(0), + R => \^ss\(0) + ); +\rate_idle_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_idle_reg1(1), + Q => rate_idle_reg2(1), + R => \^ss\(0) + ); +\rate_idle_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_idle_reg1(2), + Q => rate_idle_reg2(2), + R => \^ss\(0) + ); +\rate_idle_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_idle_reg1(3), + Q => rate_idle_reg2(3), + R => \^ss\(0) + ); +\resetdone_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => D(0), + Q => resetdone_reg1(0), + R => \^ss\(0) + ); +\resetdone_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => D(1), + Q => resetdone_reg1(1), + R => \^ss\(0) + ); +\resetdone_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => D(2), + Q => resetdone_reg1(2), + R => \^ss\(0) + ); +\resetdone_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => D(3), + Q => resetdone_reg1(3), + R => \^ss\(0) + ); +\resetdone_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => resetdone_reg1(0), + Q => resetdone_reg2(0), + R => \^ss\(0) + ); +\resetdone_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => resetdone_reg1(1), + Q => resetdone_reg2(1), + R => \^ss\(0) + ); +\resetdone_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => resetdone_reg1(2), + Q => resetdone_reg2(2), + R => \^ss\(0) + ); +\resetdone_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => resetdone_reg1(3), + Q => resetdone_reg2(3), + R => \^ss\(0) + ); +\rxcdrlock_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxcdrlock_reg1_reg[3]_0\(0), + Q => rxcdrlock_reg1(0), + R => \^ss\(0) + ); +\rxcdrlock_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxcdrlock_reg1_reg[3]_0\(1), + Q => rxcdrlock_reg1(1), + R => \^ss\(0) + ); +\rxcdrlock_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxcdrlock_reg1_reg[3]_0\(2), + Q => rxcdrlock_reg1(2), + R => \^ss\(0) + ); +\rxcdrlock_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxcdrlock_reg1_reg[3]_0\(3), + Q => rxcdrlock_reg1(3), + R => \^ss\(0) + ); +\rxcdrlock_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxcdrlock_reg1(0), + Q => rxcdrlock_reg2(0), + R => \^ss\(0) + ); +\rxcdrlock_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxcdrlock_reg1(1), + Q => rxcdrlock_reg2(1), + R => \^ss\(0) + ); +\rxcdrlock_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxcdrlock_reg1(2), + Q => rxcdrlock_reg2(2), + R => \^ss\(0) + ); +\rxcdrlock_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxcdrlock_reg1(3), + Q => rxcdrlock_reg2(3), + R => \^ss\(0) + ); +\rxpmaresetdone_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxpmaresetdone_reg1(0), + R => \^ss\(0) + ); +\rxpmaresetdone_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxpmaresetdone_reg1(1), + R => \^ss\(0) + ); +\rxpmaresetdone_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxpmaresetdone_reg1(2), + R => \^ss\(0) + ); +\rxpmaresetdone_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxpmaresetdone_reg1(3), + R => \^ss\(0) + ); +\rxpmaresetdone_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxpmaresetdone_reg1(0), + Q => rxpmaresetdone_reg2(0), + R => \^ss\(0) + ); +\rxpmaresetdone_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxpmaresetdone_reg1(1), + Q => rxpmaresetdone_reg2(1), + R => \^ss\(0) + ); +\rxpmaresetdone_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxpmaresetdone_reg1(2), + Q => rxpmaresetdone_reg2(2), + R => \^ss\(0) + ); +\rxpmaresetdone_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxpmaresetdone_reg1(3), + Q => rxpmaresetdone_reg2(3), + R => \^ss\(0) + ); +rxusrclk_rst_reg1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => cpllreset, + Q => rxusrclk_rst_reg1, + R => '0' + ); +rxusrclk_rst_reg2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rxusrclk_rst_reg1, + Q => rxusrclk_rst_reg2, + R => '0' + ); +\txsync_done_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txsync_done_reg1_reg[3]_0\(0), + Q => txsync_done_reg1(0), + R => \^ss\(0) + ); +\txsync_done_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txsync_done_reg1_reg[3]_0\(1), + Q => txsync_done_reg1(1), + R => \^ss\(0) + ); +\txsync_done_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txsync_done_reg1_reg[3]_0\(2), + Q => txsync_done_reg1(2), + R => \^ss\(0) + ); +\txsync_done_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txsync_done_reg1_reg[3]_0\(3), + Q => txsync_done_reg1(3), + R => \^ss\(0) + ); +\txsync_done_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_done_reg1(0), + Q => txsync_done_reg2(0), + R => \^ss\(0) + ); +\txsync_done_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_done_reg1(1), + Q => txsync_done_reg2(1), + R => \^ss\(0) + ); +\txsync_done_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_done_reg1(2), + Q => txsync_done_reg2(2), + R => \^ss\(0) + ); +\txsync_done_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_done_reg1(3), + Q => txsync_done_reg2(3), + R => \^ss\(0) + ); +userrdy_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => mmcm_lock_reg2, + I1 => userrdy, + I2 => \^rst_userrdy\, + O => userrdy_i_1_n_0 + ); +userrdy_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => userrdy_i_1_n_0, + Q => \^rst_userrdy\, + R => \^ss\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_sync is + port ( + \out\ : out STD_LOGIC; + txphaligndone_reg3_reg_0 : out STD_LOGIC; + sync_txdlyen_0 : out STD_LOGIC; + RST_TXSYNC_DONE : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + RST_CPLLRESET : in STD_LOGIC; + SYNC_TXPHALIGNDONE : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + SYNC_TXSYNC_START : in STD_LOGIC; + pipe_mmcm_lock_in : in STD_LOGIC; + SYNC_TXDLYSRESETDONE : in STD_LOGIC; + SYNC_TXPHINITDONE : in STD_LOGIC; + USER_RATE_GEN3 : in STD_LOGIC; + SYNC_RATE_IDLE : in STD_LOGIC; + gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 ); + SYNC_RXCDRLOCK : in STD_LOGIC; + SYNC_RXSYNC_START : in STD_LOGIC; + SYNC_RXDLYSRESETDONE : in STD_LOGIC; + SYNC_RXPHALIGNDONE_M : in STD_LOGIC; + SYNC_RXPHALIGNDONE_S : in STD_LOGIC; + \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\ : in STD_LOGIC; + user_active_lane_0 : in STD_LOGIC; + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ : in STD_LOGIC; + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\ : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_pipe_sync; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_sync is + signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[4]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^rst_txsync_done\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal gen3_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of gen3_reg1 : signal is "true"; + signal gen3_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO"; + attribute async_reg of gen3_reg2 : signal is "true"; + signal mmcm_lock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO"; + attribute async_reg of mmcm_lock_reg1 : signal is "true"; + signal mmcm_lock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO"; + attribute async_reg of mmcm_lock_reg2 : signal is "true"; + signal rate_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO"; + attribute async_reg of rate_idle_reg1 : signal is "true"; + signal rate_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO"; + attribute async_reg of rate_idle_reg2 : signal is "true"; + signal rxcdrlock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO"; + attribute async_reg of rxcdrlock_reg1 : signal is "true"; + signal rxcdrlock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO"; + attribute async_reg of rxcdrlock_reg2 : signal is "true"; + signal rxdlysresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg1 : signal is "NO"; + attribute async_reg of rxdlysresetdone_reg1 : signal is "true"; + signal rxdlysresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg2 : signal is "NO"; + attribute async_reg of rxdlysresetdone_reg2 : signal is "true"; + signal rxelecidle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxelecidle_reg1 : signal is "NO"; + attribute async_reg of rxelecidle_reg1 : signal is "true"; + signal rxelecidle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxelecidle_reg2 : signal is "NO"; + attribute async_reg of rxelecidle_reg2 : signal is "true"; + signal rxphaligndone_m_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg1 : signal is "NO"; + attribute async_reg of rxphaligndone_m_reg1 : signal is "true"; + signal rxphaligndone_m_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg2 : signal is "NO"; + attribute async_reg of rxphaligndone_m_reg2 : signal is "true"; + signal rxphaligndone_s_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg1 : signal is "NO"; + attribute async_reg of rxphaligndone_s_reg1 : signal is "true"; + signal rxphaligndone_s_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg2 : signal is "NO"; + attribute async_reg of rxphaligndone_s_reg2 : signal is "true"; + signal rxsync_donem_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_donem_reg1 : signal is "NO"; + attribute async_reg of rxsync_donem_reg1 : signal is "true"; + signal rxsync_donem_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_donem_reg2 : signal is "NO"; + attribute async_reg of rxsync_donem_reg2 : signal is "true"; + signal rxsync_start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_start_reg1 : signal is "NO"; + attribute async_reg of rxsync_start_reg1 : signal is "true"; + signal rxsync_start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_start_reg2 : signal is "NO"; + attribute async_reg of rxsync_start_reg2 : signal is "true"; + signal rxsyncdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsyncdone_reg1 : signal is "NO"; + attribute async_reg of rxsyncdone_reg1 : signal is "true"; + signal rxsyncdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsyncdone_reg2 : signal is "NO"; + attribute async_reg of rxsyncdone_reg2 : signal is "true"; + signal \^sync_txdlyen_0\ : STD_LOGIC; + signal txdlysresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txdlysresetdone_reg1 : signal is "NO"; + attribute async_reg of txdlysresetdone_reg1 : signal is "true"; + signal txdlysresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txdlysresetdone_reg2 : signal is "NO"; + attribute async_reg of txdlysresetdone_reg2 : signal is "true"; + signal txdlysresetdone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txdlysresetdone_reg3 : signal is "NO"; + attribute async_reg of txdlysresetdone_reg3 : signal is "true"; + signal txphaligndone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphaligndone_reg1 : signal is "NO"; + attribute async_reg of txphaligndone_reg1 : signal is "true"; + signal txphaligndone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphaligndone_reg2 : signal is "NO"; + attribute async_reg of txphaligndone_reg2 : signal is "true"; + signal txphaligndone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphaligndone_reg3 : signal is "NO"; + attribute async_reg of txphaligndone_reg3 : signal is "true"; + signal txphinitdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphinitdone_reg1 : signal is "NO"; + attribute async_reg of txphinitdone_reg1 : signal is "true"; + signal txphinitdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphinitdone_reg2 : signal is "NO"; + attribute async_reg of txphinitdone_reg2 : signal is "true"; + signal txphinitdone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphinitdone_reg3 : signal is "NO"; + attribute async_reg of txphinitdone_reg3 : signal is "true"; + signal \txsync_fsm.txdlyen_i_1_n_0\ : STD_LOGIC; + signal \txsync_fsm.txsync_done_i_1_n_0\ : STD_LOGIC; + signal txsync_start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_start_reg1 : signal is "NO"; + attribute async_reg of txsync_start_reg1 : signal is "true"; + signal txsync_start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_start_reg2 : signal is "NO"; + attribute async_reg of txsync_start_reg2 : signal is "true"; + signal txsync_start_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_start_reg3 : signal is "NO"; + attribute async_reg of txsync_start_reg3 : signal is "true"; + signal txsyncdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsyncdone_reg1 : signal is "NO"; + attribute async_reg of txsyncdone_reg1 : signal is "true"; + signal txsyncdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsyncdone_reg2 : signal is "NO"; + attribute async_reg of txsyncdone_reg2 : signal is "true"; + signal txsyncdone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsyncdone_reg3 : signal is "NO"; + attribute async_reg of txsyncdone_reg3 : signal is "true"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[1]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[2]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[3]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[5]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of gen3_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true; + attribute KEEP of gen3_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxdlysresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxdlysresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxelecidle_reg1_reg : label is std.standard.true; + attribute KEEP of rxelecidle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxelecidle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxelecidle_reg2_reg : label is std.standard.true; + attribute KEEP of rxelecidle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxelecidle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_m_reg1_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_m_reg2_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_s_reg1_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_s_reg2_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_donem_reg1_reg : label is std.standard.true; + attribute KEEP of rxsync_donem_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_donem_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_donem_reg2_reg : label is std.standard.true; + attribute KEEP of rxsync_donem_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_donem_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_start_reg1_reg : label is std.standard.true; + attribute KEEP of rxsync_start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_start_reg2_reg : label is std.standard.true; + attribute KEEP of rxsync_start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsyncdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxsyncdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsyncdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsyncdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxsyncdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsyncdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txdlysresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of txdlysresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txdlysresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txdlysresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of txdlysresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txdlysresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txdlysresetdone_reg3_reg : label is std.standard.true; + attribute KEEP of txdlysresetdone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txdlysresetdone_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphaligndone_reg1_reg : label is std.standard.true; + attribute KEEP of txphaligndone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphaligndone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphaligndone_reg2_reg : label is std.standard.true; + attribute KEEP of txphaligndone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphaligndone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphaligndone_reg3_reg : label is std.standard.true; + attribute KEEP of txphaligndone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphaligndone_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphinitdone_reg1_reg : label is std.standard.true; + attribute KEEP of txphinitdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphinitdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphinitdone_reg2_reg : label is std.standard.true; + attribute KEEP of txphinitdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphinitdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphinitdone_reg3_reg : label is std.standard.true; + attribute KEEP of txphinitdone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphinitdone_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_start_reg1_reg : label is std.standard.true; + attribute KEEP of txsync_start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_start_reg2_reg : label is std.standard.true; + attribute KEEP of txsync_start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_start_reg3_reg : label is std.standard.true; + attribute KEEP of txsync_start_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_start_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsyncdone_reg1_reg : label is std.standard.true; + attribute KEEP of txsyncdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsyncdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsyncdone_reg2_reg : label is std.standard.true; + attribute KEEP of txsyncdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsyncdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsyncdone_reg3_reg : label is std.standard.true; + attribute KEEP of txsyncdone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsyncdone_reg3_reg : label is "NO"; +begin + Q(2 downto 0) <= \^q\(2 downto 0); + RST_TXSYNC_DONE(0) <= \^rst_txsync_done\(0); + \out\ <= txphaligndone_reg2; + sync_txdlyen_0 <= \^sync_txdlyen_0\; + txphaligndone_reg3_reg_0 <= txphaligndone_reg3; +\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"1D1DFF1D" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\, + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + I2 => txsync_start_reg2, + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\, + O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \^q\(1), + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + I3 => \^q\(0), + I4 => \^q\(2), + O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F444" + ) + port map ( + I0 => mmcm_lock_reg2, + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + I3 => txsync_start_reg2, + O => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFD0D0D0" + ) + port map ( + I0 => txdlysresetdone_reg2, + I1 => txdlysresetdone_reg3, + I2 => \^q\(0), + I3 => mmcm_lock_reg2, + I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + O => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44F44444" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_2_n_0\, + I1 => \^q\(1), + I2 => txdlysresetdone_reg2, + I3 => txdlysresetdone_reg3, + I4 => \^q\(0), + O => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[4]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F444" + ) + port map ( + I0 => txphinitdone_reg3, + I1 => txphinitdone_reg2, + I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\, + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\, + O => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_2_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8F88FFFF88888888" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\, + I1 => \^q\(2), + I2 => txphinitdone_reg3, + I3 => txphinitdone_reg2, + I4 => user_active_lane_0, + I5 => \^q\(1), + O => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAFFEAEA2A002A2A" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\, + I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\, + I3 => txphaligndone_reg3, + I4 => txphaligndone_reg2, + I5 => \^q\(2), + O => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0\, + Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0\, + Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0\, + Q => \^q\(0), + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0\, + Q => \^q\(1), + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0\, + Q => \^q\(2), + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0\, + Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +gen3_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RATE_GEN3, + Q => gen3_reg1, + R => RST_CPLLRESET + ); +gen3_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gen3_reg1, + Q => gen3_reg2, + R => RST_CPLLRESET + ); +mmcm_lock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_mmcm_lock_in, + Q => mmcm_lock_reg1, + R => RST_CPLLRESET + ); +mmcm_lock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => mmcm_lock_reg1, + Q => mmcm_lock_reg2, + R => RST_CPLLRESET + ); +rate_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RATE_IDLE, + Q => rate_idle_reg1, + R => RST_CPLLRESET + ); +rate_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_idle_reg1, + Q => rate_idle_reg2, + R => RST_CPLLRESET + ); +rxcdrlock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXCDRLOCK, + Q => rxcdrlock_reg1, + R => RST_CPLLRESET + ); +rxcdrlock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxcdrlock_reg1, + Q => rxcdrlock_reg2, + R => RST_CPLLRESET + ); +rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXDLYSRESETDONE, + Q => rxdlysresetdone_reg1, + R => RST_CPLLRESET + ); +rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxdlysresetdone_reg1, + Q => rxdlysresetdone_reg2, + R => RST_CPLLRESET + ); +rxelecidle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rx_elec_idle_wire_filter(0), + Q => rxelecidle_reg1, + R => RST_CPLLRESET + ); +rxelecidle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxelecidle_reg1, + Q => rxelecidle_reg2, + R => RST_CPLLRESET + ); +rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXPHALIGNDONE_M, + Q => rxphaligndone_m_reg1, + R => RST_CPLLRESET + ); +rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxphaligndone_m_reg1, + Q => rxphaligndone_m_reg2, + R => RST_CPLLRESET + ); +rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXPHALIGNDONE_S, + Q => rxphaligndone_s_reg1, + R => RST_CPLLRESET + ); +rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxphaligndone_s_reg1, + Q => rxphaligndone_s_reg2, + R => RST_CPLLRESET + ); +rxsync_donem_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxsync_donem_reg1, + R => RST_CPLLRESET + ); +rxsync_donem_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsync_donem_reg1, + Q => rxsync_donem_reg2, + R => RST_CPLLRESET + ); +rxsync_start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXSYNC_START, + Q => rxsync_start_reg1, + R => RST_CPLLRESET + ); +rxsync_start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsync_start_reg1, + Q => rxsync_start_reg2, + R => RST_CPLLRESET + ); +rxsyncdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxsyncdone_reg1, + R => RST_CPLLRESET + ); +rxsyncdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsyncdone_reg1, + Q => rxsyncdone_reg2, + R => RST_CPLLRESET + ); +txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXDLYSRESETDONE, + Q => txdlysresetdone_reg1, + R => RST_CPLLRESET + ); +txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txdlysresetdone_reg1, + Q => txdlysresetdone_reg2, + R => RST_CPLLRESET + ); +txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txdlysresetdone_reg2, + Q => txdlysresetdone_reg3, + R => RST_CPLLRESET + ); +txphaligndone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXPHALIGNDONE, + Q => txphaligndone_reg1, + R => RST_CPLLRESET + ); +txphaligndone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphaligndone_reg1, + Q => txphaligndone_reg2, + R => RST_CPLLRESET + ); +txphaligndone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphaligndone_reg2, + Q => txphaligndone_reg3, + R => RST_CPLLRESET + ); +txphinitdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXPHINITDONE, + Q => txphinitdone_reg1, + R => RST_CPLLRESET + ); +txphinitdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphinitdone_reg1, + Q => txphinitdone_reg2, + R => RST_CPLLRESET + ); +txphinitdone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphinitdone_reg2, + Q => txphinitdone_reg3, + R => RST_CPLLRESET + ); +\txsync_fsm.txdlyen_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABAAA8AA" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + I1 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\, + I2 => txsync_start_reg2, + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + I4 => \^sync_txdlyen_0\, + O => \txsync_fsm.txdlyen_i_1_n_0\ + ); +\txsync_fsm.txdlyen_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txsync_fsm.txdlyen_i_1_n_0\, + Q => \^sync_txdlyen_0\, + R => RST_CPLLRESET + ); +\txsync_fsm.txsync_done_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"222F222222202222" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\, + I2 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\, + I3 => txsync_start_reg2, + I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + I5 => \^rst_txsync_done\(0), + O => \txsync_fsm.txsync_done_i_1_n_0\ + ); +\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txsync_fsm.txsync_done_i_1_n_0\, + Q => \^rst_txsync_done\(0), + R => RST_CPLLRESET + ); +txsync_start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXSYNC_START, + Q => txsync_start_reg1, + R => RST_CPLLRESET + ); +txsync_start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_start_reg1, + Q => txsync_start_reg2, + R => RST_CPLLRESET + ); +txsync_start_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_start_reg2, + Q => txsync_start_reg3, + R => RST_CPLLRESET + ); +txsyncdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txsyncdone_reg1, + R => RST_CPLLRESET + ); +txsyncdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsyncdone_reg1, + Q => txsyncdone_reg2, + R => RST_CPLLRESET + ); +txsyncdone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsyncdone_reg2, + Q => txsyncdone_reg3, + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_sync_41 is + port ( + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + RST_TXSYNC_DONE : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC; + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + SYNC_TXPHALIGNDONE : in STD_LOGIC; + SYNC_TXSYNC_START : in STD_LOGIC; + pipe_mmcm_lock_in : in STD_LOGIC; + SYNC_TXDLYSRESETDONE : in STD_LOGIC; + SYNC_TXPHINITDONE : in STD_LOGIC; + SYNC_GEN3 : in STD_LOGIC; + SYNC_RATE_IDLE : in STD_LOGIC; + gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 ); + SYNC_RXCDRLOCK : in STD_LOGIC; + SYNC_RXSYNC_START : in STD_LOGIC; + SYNC_RXDLYSRESETDONE : in STD_LOGIC; + SYNC_RXPHALIGNDONE_M : in STD_LOGIC; + SYNC_RXPHALIGNDONE_S : in STD_LOGIC; + user_active_lane_1 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_sync_41 : entity is "pcie_7x_0_pipe_sync"; +end pcie_7x_0_pcie_7x_0_pipe_sync_41; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_sync_41 is + signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^rst_txsync_done\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal gen3_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of gen3_reg1 : signal is "true"; + signal gen3_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO"; + attribute async_reg of gen3_reg2 : signal is "true"; + signal mmcm_lock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO"; + attribute async_reg of mmcm_lock_reg1 : signal is "true"; + signal mmcm_lock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO"; + attribute async_reg of mmcm_lock_reg2 : signal is "true"; + signal rate_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO"; + attribute async_reg of rate_idle_reg1 : signal is "true"; + signal rate_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO"; + attribute async_reg of rate_idle_reg2 : signal is "true"; + signal rxcdrlock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO"; + attribute async_reg of rxcdrlock_reg1 : signal is "true"; + signal rxcdrlock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO"; + attribute async_reg of rxcdrlock_reg2 : signal is "true"; + signal rxdlysresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg1 : signal is "NO"; + attribute async_reg of rxdlysresetdone_reg1 : signal is "true"; + signal rxdlysresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg2 : signal is "NO"; + attribute async_reg of rxdlysresetdone_reg2 : signal is "true"; + signal rxelecidle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxelecidle_reg1 : signal is "NO"; + attribute async_reg of rxelecidle_reg1 : signal is "true"; + signal rxelecidle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxelecidle_reg2 : signal is "NO"; + attribute async_reg of rxelecidle_reg2 : signal is "true"; + signal rxphaligndone_m_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg1 : signal is "NO"; + attribute async_reg of rxphaligndone_m_reg1 : signal is "true"; + signal rxphaligndone_m_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg2 : signal is "NO"; + attribute async_reg of rxphaligndone_m_reg2 : signal is "true"; + signal rxphaligndone_s_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg1 : signal is "NO"; + attribute async_reg of rxphaligndone_s_reg1 : signal is "true"; + signal rxphaligndone_s_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg2 : signal is "NO"; + attribute async_reg of rxphaligndone_s_reg2 : signal is "true"; + signal rxsync_donem_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_donem_reg1 : signal is "NO"; + attribute async_reg of rxsync_donem_reg1 : signal is "true"; + signal rxsync_donem_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_donem_reg2 : signal is "NO"; + attribute async_reg of rxsync_donem_reg2 : signal is "true"; + signal rxsync_start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_start_reg1 : signal is "NO"; + attribute async_reg of rxsync_start_reg1 : signal is "true"; + signal rxsync_start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_start_reg2 : signal is "NO"; + attribute async_reg of rxsync_start_reg2 : signal is "true"; + signal rxsyncdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsyncdone_reg1 : signal is "NO"; + attribute async_reg of rxsyncdone_reg1 : signal is "true"; + signal rxsyncdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsyncdone_reg2 : signal is "NO"; + attribute async_reg of rxsyncdone_reg2 : signal is "true"; + signal txdlysresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txdlysresetdone_reg1 : signal is "NO"; + attribute async_reg of txdlysresetdone_reg1 : signal is "true"; + signal txdlysresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txdlysresetdone_reg2 : signal is "NO"; + attribute async_reg of txdlysresetdone_reg2 : signal is "true"; + signal txdlysresetdone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txdlysresetdone_reg3 : signal is "NO"; + attribute async_reg of txdlysresetdone_reg3 : signal is "true"; + signal txphaligndone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphaligndone_reg1 : signal is "NO"; + attribute async_reg of txphaligndone_reg1 : signal is "true"; + signal txphaligndone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphaligndone_reg2 : signal is "NO"; + attribute async_reg of txphaligndone_reg2 : signal is "true"; + signal txphaligndone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphaligndone_reg3 : signal is "NO"; + attribute async_reg of txphaligndone_reg3 : signal is "true"; + signal txphinitdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphinitdone_reg1 : signal is "NO"; + attribute async_reg of txphinitdone_reg1 : signal is "true"; + signal txphinitdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphinitdone_reg2 : signal is "NO"; + attribute async_reg of txphinitdone_reg2 : signal is "true"; + signal txphinitdone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphinitdone_reg3 : signal is "NO"; + attribute async_reg of txphinitdone_reg3 : signal is "true"; + signal \txsync_fsm.txsync_done_i_1__0_n_0\ : STD_LOGIC; + signal txsync_start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_start_reg1 : signal is "NO"; + attribute async_reg of txsync_start_reg1 : signal is "true"; + signal txsync_start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_start_reg2 : signal is "NO"; + attribute async_reg of txsync_start_reg2 : signal is "true"; + signal txsync_start_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_start_reg3 : signal is "NO"; + attribute async_reg of txsync_start_reg3 : signal is "true"; + signal txsyncdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsyncdone_reg1 : signal is "NO"; + attribute async_reg of txsyncdone_reg1 : signal is "true"; + signal txsyncdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsyncdone_reg2 : signal is "NO"; + attribute async_reg of txsyncdone_reg2 : signal is "true"; + signal txsyncdone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsyncdone_reg3 : signal is "NO"; + attribute async_reg of txsyncdone_reg3 : signal is "true"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[1]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[2]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[3]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[5]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of gen3_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true; + attribute KEEP of gen3_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxdlysresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxdlysresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxelecidle_reg1_reg : label is std.standard.true; + attribute KEEP of rxelecidle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxelecidle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxelecidle_reg2_reg : label is std.standard.true; + attribute KEEP of rxelecidle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxelecidle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_m_reg1_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_m_reg2_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_s_reg1_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_s_reg2_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_donem_reg1_reg : label is std.standard.true; + attribute KEEP of rxsync_donem_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_donem_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_donem_reg2_reg : label is std.standard.true; + attribute KEEP of rxsync_donem_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_donem_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_start_reg1_reg : label is std.standard.true; + attribute KEEP of rxsync_start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_start_reg2_reg : label is std.standard.true; + attribute KEEP of rxsync_start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsyncdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxsyncdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsyncdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsyncdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxsyncdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsyncdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txdlysresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of txdlysresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txdlysresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txdlysresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of txdlysresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txdlysresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txdlysresetdone_reg3_reg : label is std.standard.true; + attribute KEEP of txdlysresetdone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txdlysresetdone_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphaligndone_reg1_reg : label is std.standard.true; + attribute KEEP of txphaligndone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphaligndone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphaligndone_reg2_reg : label is std.standard.true; + attribute KEEP of txphaligndone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphaligndone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphaligndone_reg3_reg : label is std.standard.true; + attribute KEEP of txphaligndone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphaligndone_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphinitdone_reg1_reg : label is std.standard.true; + attribute KEEP of txphinitdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphinitdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphinitdone_reg2_reg : label is std.standard.true; + attribute KEEP of txphinitdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphinitdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphinitdone_reg3_reg : label is std.standard.true; + attribute KEEP of txphinitdone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphinitdone_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_start_reg1_reg : label is std.standard.true; + attribute KEEP of txsync_start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_start_reg2_reg : label is std.standard.true; + attribute KEEP of txsync_start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_start_reg3_reg : label is std.standard.true; + attribute KEEP of txsync_start_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_start_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsyncdone_reg1_reg : label is std.standard.true; + attribute KEEP of txsyncdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsyncdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsyncdone_reg2_reg : label is std.standard.true; + attribute KEEP of txsyncdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsyncdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsyncdone_reg3_reg : label is std.standard.true; + attribute KEEP of txsyncdone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsyncdone_reg3_reg : label is "NO"; +begin + Q(2 downto 0) <= \^q\(2 downto 0); + RST_TXSYNC_DONE(0) <= \^rst_txsync_done\(0); +\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF1D" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0\, + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + I2 => txsync_start_reg2, + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F444" + ) + port map ( + I0 => mmcm_lock_reg2, + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + I3 => txsync_start_reg2, + O => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFD0D0D0" + ) + port map ( + I0 => txdlysresetdone_reg2, + I1 => txdlysresetdone_reg3, + I2 => \^q\(0), + I3 => mmcm_lock_reg2, + I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + O => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44F44444" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__2_n_0\, + I1 => \^q\(1), + I2 => txdlysresetdone_reg2, + I3 => txdlysresetdone_reg3, + I4 => \^q\(0), + O => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFB000B000B000" + ) + port map ( + I0 => txphaligndone_reg3, + I1 => txphaligndone_reg2, + I2 => user_active_lane_1, + I3 => \^q\(2), + I4 => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__2_n_0\, + I5 => \^q\(1), + O => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F444" + ) + port map ( + I0 => txphinitdone_reg3, + I1 => txphinitdone_reg2, + I2 => \out\, + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\, + O => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__2_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8080AA80" + ) + port map ( + I0 => \^q\(2), + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\, + I2 => \out\, + I3 => txphaligndone_reg2, + I4 => txphaligndone_reg3, + O => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0\, + Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0\, + Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0\, + Q => \^q\(0), + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0\, + Q => \^q\(1), + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0\, + Q => \^q\(2), + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0\, + Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +gen3_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_GEN3, + Q => gen3_reg1, + R => RST_CPLLRESET + ); +gen3_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gen3_reg1, + Q => gen3_reg2, + R => RST_CPLLRESET + ); +mmcm_lock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_mmcm_lock_in, + Q => mmcm_lock_reg1, + R => RST_CPLLRESET + ); +mmcm_lock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => mmcm_lock_reg1, + Q => mmcm_lock_reg2, + R => RST_CPLLRESET + ); +rate_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RATE_IDLE, + Q => rate_idle_reg1, + R => RST_CPLLRESET + ); +rate_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_idle_reg1, + Q => rate_idle_reg2, + R => RST_CPLLRESET + ); +rxcdrlock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXCDRLOCK, + Q => rxcdrlock_reg1, + R => RST_CPLLRESET + ); +rxcdrlock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxcdrlock_reg1, + Q => rxcdrlock_reg2, + R => RST_CPLLRESET + ); +rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXDLYSRESETDONE, + Q => rxdlysresetdone_reg1, + R => RST_CPLLRESET + ); +rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxdlysresetdone_reg1, + Q => rxdlysresetdone_reg2, + R => RST_CPLLRESET + ); +rxelecidle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rx_elec_idle_wire_filter(0), + Q => rxelecidle_reg1, + R => RST_CPLLRESET + ); +rxelecidle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxelecidle_reg1, + Q => rxelecidle_reg2, + R => RST_CPLLRESET + ); +rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXPHALIGNDONE_M, + Q => rxphaligndone_m_reg1, + R => RST_CPLLRESET + ); +rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxphaligndone_m_reg1, + Q => rxphaligndone_m_reg2, + R => RST_CPLLRESET + ); +rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXPHALIGNDONE_S, + Q => rxphaligndone_s_reg1, + R => RST_CPLLRESET + ); +rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxphaligndone_s_reg1, + Q => rxphaligndone_s_reg2, + R => RST_CPLLRESET + ); +rxsync_donem_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxsync_donem_reg1, + R => RST_CPLLRESET + ); +rxsync_donem_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsync_donem_reg1, + Q => rxsync_donem_reg2, + R => RST_CPLLRESET + ); +rxsync_start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXSYNC_START, + Q => rxsync_start_reg1, + R => RST_CPLLRESET + ); +rxsync_start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsync_start_reg1, + Q => rxsync_start_reg2, + R => RST_CPLLRESET + ); +rxsyncdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxsyncdone_reg1, + R => RST_CPLLRESET + ); +rxsyncdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsyncdone_reg1, + Q => rxsyncdone_reg2, + R => RST_CPLLRESET + ); +txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXDLYSRESETDONE, + Q => txdlysresetdone_reg1, + R => RST_CPLLRESET + ); +txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txdlysresetdone_reg1, + Q => txdlysresetdone_reg2, + R => RST_CPLLRESET + ); +txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txdlysresetdone_reg2, + Q => txdlysresetdone_reg3, + R => RST_CPLLRESET + ); +txphaligndone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXPHALIGNDONE, + Q => txphaligndone_reg1, + R => RST_CPLLRESET + ); +txphaligndone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphaligndone_reg1, + Q => txphaligndone_reg2, + R => RST_CPLLRESET + ); +txphaligndone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphaligndone_reg2, + Q => txphaligndone_reg3, + R => RST_CPLLRESET + ); +txphinitdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXPHINITDONE, + Q => txphinitdone_reg1, + R => RST_CPLLRESET + ); +txphinitdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphinitdone_reg1, + Q => txphinitdone_reg2, + R => RST_CPLLRESET + ); +txphinitdone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphinitdone_reg2, + Q => txphinitdone_reg3, + R => RST_CPLLRESET + ); +\txsync_fsm.txsync_done_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABAAA8AA" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + I1 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0\, + I2 => txsync_start_reg2, + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + I4 => \^rst_txsync_done\(0), + O => \txsync_fsm.txsync_done_i_1__0_n_0\ + ); +\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txsync_fsm.txsync_done_i_1__0_n_0\, + Q => \^rst_txsync_done\(0), + R => RST_CPLLRESET + ); +txsync_start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXSYNC_START, + Q => txsync_start_reg1, + R => RST_CPLLRESET + ); +txsync_start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_start_reg1, + Q => txsync_start_reg2, + R => RST_CPLLRESET + ); +txsync_start_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_start_reg2, + Q => txsync_start_reg3, + R => RST_CPLLRESET + ); +txsyncdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txsyncdone_reg1, + R => RST_CPLLRESET + ); +txsyncdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsyncdone_reg1, + Q => txsyncdone_reg2, + R => RST_CPLLRESET + ); +txsyncdone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsyncdone_reg2, + Q => txsyncdone_reg3, + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_sync_47 is + port ( + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + RST_TXSYNC_DONE : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC; + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + SYNC_TXPHALIGNDONE : in STD_LOGIC; + SYNC_TXSYNC_START : in STD_LOGIC; + pipe_mmcm_lock_in : in STD_LOGIC; + SYNC_TXDLYSRESETDONE : in STD_LOGIC; + SYNC_TXPHINITDONE : in STD_LOGIC; + SYNC_GEN3 : in STD_LOGIC; + SYNC_RATE_IDLE : in STD_LOGIC; + gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 ); + SYNC_RXCDRLOCK : in STD_LOGIC; + SYNC_RXSYNC_START : in STD_LOGIC; + SYNC_RXDLYSRESETDONE : in STD_LOGIC; + SYNC_RXPHALIGNDONE_M : in STD_LOGIC; + SYNC_RXPHALIGNDONE_S : in STD_LOGIC; + user_active_lane_2 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_sync_47 : entity is "pcie_7x_0_pipe_sync"; +end pcie_7x_0_pcie_7x_0_pipe_sync_47; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_sync_47 is + signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^rst_txsync_done\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal gen3_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of gen3_reg1 : signal is "true"; + signal gen3_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO"; + attribute async_reg of gen3_reg2 : signal is "true"; + signal mmcm_lock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO"; + attribute async_reg of mmcm_lock_reg1 : signal is "true"; + signal mmcm_lock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO"; + attribute async_reg of mmcm_lock_reg2 : signal is "true"; + signal rate_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO"; + attribute async_reg of rate_idle_reg1 : signal is "true"; + signal rate_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO"; + attribute async_reg of rate_idle_reg2 : signal is "true"; + signal rxcdrlock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO"; + attribute async_reg of rxcdrlock_reg1 : signal is "true"; + signal rxcdrlock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO"; + attribute async_reg of rxcdrlock_reg2 : signal is "true"; + signal rxdlysresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg1 : signal is "NO"; + attribute async_reg of rxdlysresetdone_reg1 : signal is "true"; + signal rxdlysresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg2 : signal is "NO"; + attribute async_reg of rxdlysresetdone_reg2 : signal is "true"; + signal rxelecidle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxelecidle_reg1 : signal is "NO"; + attribute async_reg of rxelecidle_reg1 : signal is "true"; + signal rxelecidle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxelecidle_reg2 : signal is "NO"; + attribute async_reg of rxelecidle_reg2 : signal is "true"; + signal rxphaligndone_m_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg1 : signal is "NO"; + attribute async_reg of rxphaligndone_m_reg1 : signal is "true"; + signal rxphaligndone_m_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg2 : signal is "NO"; + attribute async_reg of rxphaligndone_m_reg2 : signal is "true"; + signal rxphaligndone_s_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg1 : signal is "NO"; + attribute async_reg of rxphaligndone_s_reg1 : signal is "true"; + signal rxphaligndone_s_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg2 : signal is "NO"; + attribute async_reg of rxphaligndone_s_reg2 : signal is "true"; + signal rxsync_donem_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_donem_reg1 : signal is "NO"; + attribute async_reg of rxsync_donem_reg1 : signal is "true"; + signal rxsync_donem_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_donem_reg2 : signal is "NO"; + attribute async_reg of rxsync_donem_reg2 : signal is "true"; + signal rxsync_start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_start_reg1 : signal is "NO"; + attribute async_reg of rxsync_start_reg1 : signal is "true"; + signal rxsync_start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_start_reg2 : signal is "NO"; + attribute async_reg of rxsync_start_reg2 : signal is "true"; + signal rxsyncdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsyncdone_reg1 : signal is "NO"; + attribute async_reg of rxsyncdone_reg1 : signal is "true"; + signal rxsyncdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsyncdone_reg2 : signal is "NO"; + attribute async_reg of rxsyncdone_reg2 : signal is "true"; + signal txdlysresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txdlysresetdone_reg1 : signal is "NO"; + attribute async_reg of txdlysresetdone_reg1 : signal is "true"; + signal txdlysresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txdlysresetdone_reg2 : signal is "NO"; + attribute async_reg of txdlysresetdone_reg2 : signal is "true"; + signal txdlysresetdone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txdlysresetdone_reg3 : signal is "NO"; + attribute async_reg of txdlysresetdone_reg3 : signal is "true"; + signal txphaligndone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphaligndone_reg1 : signal is "NO"; + attribute async_reg of txphaligndone_reg1 : signal is "true"; + signal txphaligndone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphaligndone_reg2 : signal is "NO"; + attribute async_reg of txphaligndone_reg2 : signal is "true"; + signal txphaligndone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphaligndone_reg3 : signal is "NO"; + attribute async_reg of txphaligndone_reg3 : signal is "true"; + signal txphinitdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphinitdone_reg1 : signal is "NO"; + attribute async_reg of txphinitdone_reg1 : signal is "true"; + signal txphinitdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphinitdone_reg2 : signal is "NO"; + attribute async_reg of txphinitdone_reg2 : signal is "true"; + signal txphinitdone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphinitdone_reg3 : signal is "NO"; + attribute async_reg of txphinitdone_reg3 : signal is "true"; + signal \txsync_fsm.txsync_done_i_1__1_n_0\ : STD_LOGIC; + signal txsync_start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_start_reg1 : signal is "NO"; + attribute async_reg of txsync_start_reg1 : signal is "true"; + signal txsync_start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_start_reg2 : signal is "NO"; + attribute async_reg of txsync_start_reg2 : signal is "true"; + signal txsync_start_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_start_reg3 : signal is "NO"; + attribute async_reg of txsync_start_reg3 : signal is "true"; + signal txsyncdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsyncdone_reg1 : signal is "NO"; + attribute async_reg of txsyncdone_reg1 : signal is "true"; + signal txsyncdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsyncdone_reg2 : signal is "NO"; + attribute async_reg of txsyncdone_reg2 : signal is "true"; + signal txsyncdone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsyncdone_reg3 : signal is "NO"; + attribute async_reg of txsyncdone_reg3 : signal is "true"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[1]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[2]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[3]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[5]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of gen3_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true; + attribute KEEP of gen3_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxdlysresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxdlysresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxelecidle_reg1_reg : label is std.standard.true; + attribute KEEP of rxelecidle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxelecidle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxelecidle_reg2_reg : label is std.standard.true; + attribute KEEP of rxelecidle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxelecidle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_m_reg1_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_m_reg2_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_s_reg1_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_s_reg2_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_donem_reg1_reg : label is std.standard.true; + attribute KEEP of rxsync_donem_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_donem_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_donem_reg2_reg : label is std.standard.true; + attribute KEEP of rxsync_donem_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_donem_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_start_reg1_reg : label is std.standard.true; + attribute KEEP of rxsync_start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_start_reg2_reg : label is std.standard.true; + attribute KEEP of rxsync_start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsyncdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxsyncdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsyncdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsyncdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxsyncdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsyncdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txdlysresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of txdlysresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txdlysresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txdlysresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of txdlysresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txdlysresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txdlysresetdone_reg3_reg : label is std.standard.true; + attribute KEEP of txdlysresetdone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txdlysresetdone_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphaligndone_reg1_reg : label is std.standard.true; + attribute KEEP of txphaligndone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphaligndone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphaligndone_reg2_reg : label is std.standard.true; + attribute KEEP of txphaligndone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphaligndone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphaligndone_reg3_reg : label is std.standard.true; + attribute KEEP of txphaligndone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphaligndone_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphinitdone_reg1_reg : label is std.standard.true; + attribute KEEP of txphinitdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphinitdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphinitdone_reg2_reg : label is std.standard.true; + attribute KEEP of txphinitdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphinitdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphinitdone_reg3_reg : label is std.standard.true; + attribute KEEP of txphinitdone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphinitdone_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_start_reg1_reg : label is std.standard.true; + attribute KEEP of txsync_start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_start_reg2_reg : label is std.standard.true; + attribute KEEP of txsync_start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_start_reg3_reg : label is std.standard.true; + attribute KEEP of txsync_start_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_start_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsyncdone_reg1_reg : label is std.standard.true; + attribute KEEP of txsyncdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsyncdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsyncdone_reg2_reg : label is std.standard.true; + attribute KEEP of txsyncdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsyncdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsyncdone_reg3_reg : label is std.standard.true; + attribute KEEP of txsyncdone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsyncdone_reg3_reg : label is "NO"; +begin + Q(2 downto 0) <= \^q\(2 downto 0); + RST_TXSYNC_DONE(0) <= \^rst_txsync_done\(0); +\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF1D" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__1_n_0\, + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + I2 => txsync_start_reg2, + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F444" + ) + port map ( + I0 => mmcm_lock_reg2, + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + I3 => txsync_start_reg2, + O => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFD0D0D0" + ) + port map ( + I0 => txdlysresetdone_reg2, + I1 => txdlysresetdone_reg3, + I2 => \^q\(0), + I3 => mmcm_lock_reg2, + I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + O => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44F44444" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__0_n_0\, + I1 => \^q\(1), + I2 => txdlysresetdone_reg2, + I3 => txdlysresetdone_reg3, + I4 => \^q\(0), + O => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFB000B000B000" + ) + port map ( + I0 => txphaligndone_reg3, + I1 => txphaligndone_reg2, + I2 => user_active_lane_2, + I3 => \^q\(2), + I4 => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__0_n_0\, + I5 => \^q\(1), + O => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F444" + ) + port map ( + I0 => txphinitdone_reg3, + I1 => txphinitdone_reg2, + I2 => \out\, + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\, + O => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__0_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8080AA80" + ) + port map ( + I0 => \^q\(2), + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\, + I2 => \out\, + I3 => txphaligndone_reg2, + I4 => txphaligndone_reg3, + O => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__1_n_0\, + Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__1_n_0\, + Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__1_n_0\, + Q => \^q\(0), + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__1_n_0\, + Q => \^q\(1), + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__1_n_0\, + Q => \^q\(2), + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__1_n_0\, + Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +gen3_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_GEN3, + Q => gen3_reg1, + R => RST_CPLLRESET + ); +gen3_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gen3_reg1, + Q => gen3_reg2, + R => RST_CPLLRESET + ); +mmcm_lock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_mmcm_lock_in, + Q => mmcm_lock_reg1, + R => RST_CPLLRESET + ); +mmcm_lock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => mmcm_lock_reg1, + Q => mmcm_lock_reg2, + R => RST_CPLLRESET + ); +rate_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RATE_IDLE, + Q => rate_idle_reg1, + R => RST_CPLLRESET + ); +rate_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_idle_reg1, + Q => rate_idle_reg2, + R => RST_CPLLRESET + ); +rxcdrlock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXCDRLOCK, + Q => rxcdrlock_reg1, + R => RST_CPLLRESET + ); +rxcdrlock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxcdrlock_reg1, + Q => rxcdrlock_reg2, + R => RST_CPLLRESET + ); +rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXDLYSRESETDONE, + Q => rxdlysresetdone_reg1, + R => RST_CPLLRESET + ); +rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxdlysresetdone_reg1, + Q => rxdlysresetdone_reg2, + R => RST_CPLLRESET + ); +rxelecidle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rx_elec_idle_wire_filter(0), + Q => rxelecidle_reg1, + R => RST_CPLLRESET + ); +rxelecidle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxelecidle_reg1, + Q => rxelecidle_reg2, + R => RST_CPLLRESET + ); +rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXPHALIGNDONE_M, + Q => rxphaligndone_m_reg1, + R => RST_CPLLRESET + ); +rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxphaligndone_m_reg1, + Q => rxphaligndone_m_reg2, + R => RST_CPLLRESET + ); +rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXPHALIGNDONE_S, + Q => rxphaligndone_s_reg1, + R => RST_CPLLRESET + ); +rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxphaligndone_s_reg1, + Q => rxphaligndone_s_reg2, + R => RST_CPLLRESET + ); +rxsync_donem_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxsync_donem_reg1, + R => RST_CPLLRESET + ); +rxsync_donem_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsync_donem_reg1, + Q => rxsync_donem_reg2, + R => RST_CPLLRESET + ); +rxsync_start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXSYNC_START, + Q => rxsync_start_reg1, + R => RST_CPLLRESET + ); +rxsync_start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsync_start_reg1, + Q => rxsync_start_reg2, + R => RST_CPLLRESET + ); +rxsyncdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxsyncdone_reg1, + R => RST_CPLLRESET + ); +rxsyncdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsyncdone_reg1, + Q => rxsyncdone_reg2, + R => RST_CPLLRESET + ); +txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXDLYSRESETDONE, + Q => txdlysresetdone_reg1, + R => RST_CPLLRESET + ); +txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txdlysresetdone_reg1, + Q => txdlysresetdone_reg2, + R => RST_CPLLRESET + ); +txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txdlysresetdone_reg2, + Q => txdlysresetdone_reg3, + R => RST_CPLLRESET + ); +txphaligndone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXPHALIGNDONE, + Q => txphaligndone_reg1, + R => RST_CPLLRESET + ); +txphaligndone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphaligndone_reg1, + Q => txphaligndone_reg2, + R => RST_CPLLRESET + ); +txphaligndone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphaligndone_reg2, + Q => txphaligndone_reg3, + R => RST_CPLLRESET + ); +txphinitdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXPHINITDONE, + Q => txphinitdone_reg1, + R => RST_CPLLRESET + ); +txphinitdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphinitdone_reg1, + Q => txphinitdone_reg2, + R => RST_CPLLRESET + ); +txphinitdone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphinitdone_reg2, + Q => txphinitdone_reg3, + R => RST_CPLLRESET + ); +\txsync_fsm.txsync_done_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABAAA8AA" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + I1 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__1_n_0\, + I2 => txsync_start_reg2, + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + I4 => \^rst_txsync_done\(0), + O => \txsync_fsm.txsync_done_i_1__1_n_0\ + ); +\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txsync_fsm.txsync_done_i_1__1_n_0\, + Q => \^rst_txsync_done\(0), + R => RST_CPLLRESET + ); +txsync_start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXSYNC_START, + Q => txsync_start_reg1, + R => RST_CPLLRESET + ); +txsync_start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_start_reg1, + Q => txsync_start_reg2, + R => RST_CPLLRESET + ); +txsync_start_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_start_reg2, + Q => txsync_start_reg3, + R => RST_CPLLRESET + ); +txsyncdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txsyncdone_reg1, + R => RST_CPLLRESET + ); +txsyncdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsyncdone_reg1, + Q => txsyncdone_reg2, + R => RST_CPLLRESET + ); +txsyncdone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsyncdone_reg2, + Q => txsyncdone_reg3, + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_sync_53 is + port ( + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + RST_TXSYNC_DONE : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC; + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + SYNC_TXPHALIGNDONE : in STD_LOGIC; + SYNC_TXSYNC_START : in STD_LOGIC; + pipe_mmcm_lock_in : in STD_LOGIC; + SYNC_TXDLYSRESETDONE : in STD_LOGIC; + SYNC_TXPHINITDONE : in STD_LOGIC; + SYNC_GEN3 : in STD_LOGIC; + SYNC_RATE_IDLE : in STD_LOGIC; + gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 ); + SYNC_RXCDRLOCK : in STD_LOGIC; + SYNC_RXSYNC_START : in STD_LOGIC; + SYNC_RXDLYSRESETDONE : in STD_LOGIC; + SYNC_RXPHALIGNDONE_M : in STD_LOGIC; + SYNC_RXPHALIGNDONE_S : in STD_LOGIC; + user_active_lane_3 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_sync_53 : entity is "pcie_7x_0_pipe_sync"; +end pcie_7x_0_pcie_7x_0_pipe_sync_53; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_sync_53 is + signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^rst_txsync_done\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal gen3_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of gen3_reg1 : signal is "true"; + signal gen3_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO"; + attribute async_reg of gen3_reg2 : signal is "true"; + signal mmcm_lock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO"; + attribute async_reg of mmcm_lock_reg1 : signal is "true"; + signal mmcm_lock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO"; + attribute async_reg of mmcm_lock_reg2 : signal is "true"; + signal rate_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO"; + attribute async_reg of rate_idle_reg1 : signal is "true"; + signal rate_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO"; + attribute async_reg of rate_idle_reg2 : signal is "true"; + signal rxcdrlock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO"; + attribute async_reg of rxcdrlock_reg1 : signal is "true"; + signal rxcdrlock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO"; + attribute async_reg of rxcdrlock_reg2 : signal is "true"; + signal rxdlysresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg1 : signal is "NO"; + attribute async_reg of rxdlysresetdone_reg1 : signal is "true"; + signal rxdlysresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg2 : signal is "NO"; + attribute async_reg of rxdlysresetdone_reg2 : signal is "true"; + signal rxelecidle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxelecidle_reg1 : signal is "NO"; + attribute async_reg of rxelecidle_reg1 : signal is "true"; + signal rxelecidle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxelecidle_reg2 : signal is "NO"; + attribute async_reg of rxelecidle_reg2 : signal is "true"; + signal rxphaligndone_m_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg1 : signal is "NO"; + attribute async_reg of rxphaligndone_m_reg1 : signal is "true"; + signal rxphaligndone_m_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg2 : signal is "NO"; + attribute async_reg of rxphaligndone_m_reg2 : signal is "true"; + signal rxphaligndone_s_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg1 : signal is "NO"; + attribute async_reg of rxphaligndone_s_reg1 : signal is "true"; + signal rxphaligndone_s_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg2 : signal is "NO"; + attribute async_reg of rxphaligndone_s_reg2 : signal is "true"; + signal rxsync_donem_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_donem_reg1 : signal is "NO"; + attribute async_reg of rxsync_donem_reg1 : signal is "true"; + signal rxsync_donem_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_donem_reg2 : signal is "NO"; + attribute async_reg of rxsync_donem_reg2 : signal is "true"; + signal rxsync_start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_start_reg1 : signal is "NO"; + attribute async_reg of rxsync_start_reg1 : signal is "true"; + signal rxsync_start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsync_start_reg2 : signal is "NO"; + attribute async_reg of rxsync_start_reg2 : signal is "true"; + signal rxsyncdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsyncdone_reg1 : signal is "NO"; + attribute async_reg of rxsyncdone_reg1 : signal is "true"; + signal rxsyncdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxsyncdone_reg2 : signal is "NO"; + attribute async_reg of rxsyncdone_reg2 : signal is "true"; + signal txdlysresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txdlysresetdone_reg1 : signal is "NO"; + attribute async_reg of txdlysresetdone_reg1 : signal is "true"; + signal txdlysresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txdlysresetdone_reg2 : signal is "NO"; + attribute async_reg of txdlysresetdone_reg2 : signal is "true"; + signal txdlysresetdone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txdlysresetdone_reg3 : signal is "NO"; + attribute async_reg of txdlysresetdone_reg3 : signal is "true"; + signal txphaligndone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphaligndone_reg1 : signal is "NO"; + attribute async_reg of txphaligndone_reg1 : signal is "true"; + signal txphaligndone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphaligndone_reg2 : signal is "NO"; + attribute async_reg of txphaligndone_reg2 : signal is "true"; + signal txphaligndone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphaligndone_reg3 : signal is "NO"; + attribute async_reg of txphaligndone_reg3 : signal is "true"; + signal txphinitdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphinitdone_reg1 : signal is "NO"; + attribute async_reg of txphinitdone_reg1 : signal is "true"; + signal txphinitdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphinitdone_reg2 : signal is "NO"; + attribute async_reg of txphinitdone_reg2 : signal is "true"; + signal txphinitdone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txphinitdone_reg3 : signal is "NO"; + attribute async_reg of txphinitdone_reg3 : signal is "true"; + signal \txsync_fsm.txsync_done_i_1__2_n_0\ : STD_LOGIC; + signal txsync_start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_start_reg1 : signal is "NO"; + attribute async_reg of txsync_start_reg1 : signal is "true"; + signal txsync_start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_start_reg2 : signal is "NO"; + attribute async_reg of txsync_start_reg2 : signal is "true"; + signal txsync_start_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsync_start_reg3 : signal is "NO"; + attribute async_reg of txsync_start_reg3 : signal is "true"; + signal txsyncdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsyncdone_reg1 : signal is "NO"; + attribute async_reg of txsyncdone_reg1 : signal is "true"; + signal txsyncdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsyncdone_reg2 : signal is "NO"; + attribute async_reg of txsyncdone_reg2 : signal is "true"; + signal txsyncdone_reg3 : STD_LOGIC; + attribute SHIFT_EXTRACT of txsyncdone_reg3 : signal is "NO"; + attribute async_reg of txsyncdone_reg3 : signal is "true"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[1]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[2]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[3]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[5]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of gen3_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true; + attribute KEEP of gen3_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxdlysresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxdlysresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxdlysresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxelecidle_reg1_reg : label is std.standard.true; + attribute KEEP of rxelecidle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxelecidle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxelecidle_reg2_reg : label is std.standard.true; + attribute KEEP of rxelecidle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxelecidle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_m_reg1_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_m_reg2_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_m_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_s_reg1_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxphaligndone_s_reg2_reg : label is std.standard.true; + attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxphaligndone_s_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_donem_reg1_reg : label is std.standard.true; + attribute KEEP of rxsync_donem_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_donem_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_donem_reg2_reg : label is std.standard.true; + attribute KEEP of rxsync_donem_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_donem_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_start_reg1_reg : label is std.standard.true; + attribute KEEP of rxsync_start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsync_start_reg2_reg : label is std.standard.true; + attribute KEEP of rxsync_start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsync_start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsyncdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxsyncdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsyncdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxsyncdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxsyncdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxsyncdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txdlysresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of txdlysresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txdlysresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txdlysresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of txdlysresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txdlysresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txdlysresetdone_reg3_reg : label is std.standard.true; + attribute KEEP of txdlysresetdone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txdlysresetdone_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphaligndone_reg1_reg : label is std.standard.true; + attribute KEEP of txphaligndone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphaligndone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphaligndone_reg2_reg : label is std.standard.true; + attribute KEEP of txphaligndone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphaligndone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphaligndone_reg3_reg : label is std.standard.true; + attribute KEEP of txphaligndone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphaligndone_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphinitdone_reg1_reg : label is std.standard.true; + attribute KEEP of txphinitdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphinitdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphinitdone_reg2_reg : label is std.standard.true; + attribute KEEP of txphinitdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphinitdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txphinitdone_reg3_reg : label is std.standard.true; + attribute KEEP of txphinitdone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txphinitdone_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_start_reg1_reg : label is std.standard.true; + attribute KEEP of txsync_start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_start_reg2_reg : label is std.standard.true; + attribute KEEP of txsync_start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsync_start_reg3_reg : label is std.standard.true; + attribute KEEP of txsync_start_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsync_start_reg3_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsyncdone_reg1_reg : label is std.standard.true; + attribute KEEP of txsyncdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsyncdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsyncdone_reg2_reg : label is std.standard.true; + attribute KEEP of txsyncdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsyncdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txsyncdone_reg3_reg : label is std.standard.true; + attribute KEEP of txsyncdone_reg3_reg : label is "yes"; + attribute SHIFT_EXTRACT of txsyncdone_reg3_reg : label is "NO"; +begin + Q(2 downto 0) <= \^q\(2 downto 0); + RST_TXSYNC_DONE(0) <= \^rst_txsync_done\(0); +\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF1D" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__2_n_0\, + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + I2 => txsync_start_reg2, + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__2_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__2_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F444" + ) + port map ( + I0 => mmcm_lock_reg2, + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + I3 => txsync_start_reg2, + O => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__2_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFD0D0D0" + ) + port map ( + I0 => txdlysresetdone_reg2, + I1 => txdlysresetdone_reg3, + I2 => \^q\(0), + I3 => mmcm_lock_reg2, + I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + O => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__2_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44F44444" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__1_n_0\, + I1 => \^q\(1), + I2 => txdlysresetdone_reg2, + I3 => txdlysresetdone_reg3, + I4 => \^q\(0), + O => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__2_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFB000B000B000" + ) + port map ( + I0 => txphaligndone_reg3, + I1 => txphaligndone_reg2, + I2 => user_active_lane_3, + I3 => \^q\(2), + I4 => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__1_n_0\, + I5 => \^q\(1), + O => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__2_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F444" + ) + port map ( + I0 => txphinitdone_reg3, + I1 => txphinitdone_reg2, + I2 => \out\, + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\, + O => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__1_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8080AA80" + ) + port map ( + I0 => \^q\(2), + I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\, + I2 => \out\, + I3 => txphaligndone_reg2, + I4 => txphaligndone_reg3, + O => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__2_n_0\ + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__2_n_0\, + Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__2_n_0\, + Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__2_n_0\, + Q => \^q\(0), + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__2_n_0\, + Q => \^q\(1), + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__2_n_0\, + Q => \^q\(2), + R => RST_CPLLRESET + ); +\FSM_onehot_txsync_fsm.fsm_tx_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__2_n_0\, + Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +gen3_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_GEN3, + Q => gen3_reg1, + R => RST_CPLLRESET + ); +gen3_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gen3_reg1, + Q => gen3_reg2, + R => RST_CPLLRESET + ); +mmcm_lock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_mmcm_lock_in, + Q => mmcm_lock_reg1, + R => RST_CPLLRESET + ); +mmcm_lock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => mmcm_lock_reg1, + Q => mmcm_lock_reg2, + R => RST_CPLLRESET + ); +rate_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RATE_IDLE, + Q => rate_idle_reg1, + R => RST_CPLLRESET + ); +rate_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_idle_reg1, + Q => rate_idle_reg2, + R => RST_CPLLRESET + ); +rxcdrlock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXCDRLOCK, + Q => rxcdrlock_reg1, + R => RST_CPLLRESET + ); +rxcdrlock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxcdrlock_reg1, + Q => rxcdrlock_reg2, + R => RST_CPLLRESET + ); +rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXDLYSRESETDONE, + Q => rxdlysresetdone_reg1, + R => RST_CPLLRESET + ); +rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxdlysresetdone_reg1, + Q => rxdlysresetdone_reg2, + R => RST_CPLLRESET + ); +rxelecidle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rx_elec_idle_wire_filter(0), + Q => rxelecidle_reg1, + R => RST_CPLLRESET + ); +rxelecidle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxelecidle_reg1, + Q => rxelecidle_reg2, + R => RST_CPLLRESET + ); +rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXPHALIGNDONE_M, + Q => rxphaligndone_m_reg1, + R => RST_CPLLRESET + ); +rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxphaligndone_m_reg1, + Q => rxphaligndone_m_reg2, + R => RST_CPLLRESET + ); +rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXPHALIGNDONE_S, + Q => rxphaligndone_s_reg1, + R => RST_CPLLRESET + ); +rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxphaligndone_s_reg1, + Q => rxphaligndone_s_reg2, + R => RST_CPLLRESET + ); +rxsync_donem_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxsync_donem_reg1, + R => RST_CPLLRESET + ); +rxsync_donem_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsync_donem_reg1, + Q => rxsync_donem_reg2, + R => RST_CPLLRESET + ); +rxsync_start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_RXSYNC_START, + Q => rxsync_start_reg1, + R => RST_CPLLRESET + ); +rxsync_start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsync_start_reg1, + Q => rxsync_start_reg2, + R => RST_CPLLRESET + ); +rxsyncdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxsyncdone_reg1, + R => RST_CPLLRESET + ); +rxsyncdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxsyncdone_reg1, + Q => rxsyncdone_reg2, + R => RST_CPLLRESET + ); +txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXDLYSRESETDONE, + Q => txdlysresetdone_reg1, + R => RST_CPLLRESET + ); +txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txdlysresetdone_reg1, + Q => txdlysresetdone_reg2, + R => RST_CPLLRESET + ); +txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txdlysresetdone_reg2, + Q => txdlysresetdone_reg3, + R => RST_CPLLRESET + ); +txphaligndone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXPHALIGNDONE, + Q => txphaligndone_reg1, + R => RST_CPLLRESET + ); +txphaligndone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphaligndone_reg1, + Q => txphaligndone_reg2, + R => RST_CPLLRESET + ); +txphaligndone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphaligndone_reg2, + Q => txphaligndone_reg3, + R => RST_CPLLRESET + ); +txphinitdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXPHINITDONE, + Q => txphinitdone_reg1, + R => RST_CPLLRESET + ); +txphinitdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphinitdone_reg1, + Q => txphinitdone_reg2, + R => RST_CPLLRESET + ); +txphinitdone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txphinitdone_reg2, + Q => txphinitdone_reg3, + R => RST_CPLLRESET + ); +\txsync_fsm.txsync_done_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABAAA8AA" + ) + port map ( + I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\, + I1 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__2_n_0\, + I2 => txsync_start_reg2, + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\, + I4 => \^rst_txsync_done\(0), + O => \txsync_fsm.txsync_done_i_1__2_n_0\ + ); +\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txsync_fsm.txsync_done_i_1__2_n_0\, + Q => \^rst_txsync_done\(0), + R => RST_CPLLRESET + ); +txsync_start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => SYNC_TXSYNC_START, + Q => txsync_start_reg1, + R => RST_CPLLRESET + ); +txsync_start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_start_reg1, + Q => txsync_start_reg2, + R => RST_CPLLRESET + ); +txsync_start_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsync_start_reg2, + Q => txsync_start_reg3, + R => RST_CPLLRESET + ); +txsyncdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txsyncdone_reg1, + R => RST_CPLLRESET + ); +txsyncdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsyncdone_reg1, + Q => txsyncdone_reg2, + R => RST_CPLLRESET + ); +txsyncdone_reg3_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txsyncdone_reg2, + Q => txsyncdone_reg3, + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_user is + port ( + gt_rxvalid_q_reg : out STD_LOGIC; + \out\ : out STD_LOGIC; + SYNC_TXPHALIGNDONE : out STD_LOGIC; + txelecidle_reg2_reg_0 : out STD_LOGIC; + txcompliance_reg2_reg_0 : out STD_LOGIC; + SYNC_TXPHINITDONE : out STD_LOGIC; + txelecidle_reg2_reg_1 : out STD_LOGIC; + USER_OOBCLK : out STD_LOGIC; + RST_RXCDRLOCK : out STD_LOGIC_VECTOR ( 0 to 0 ); + gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 ); + \converge_cnt_reg[15]_0\ : out STD_LOGIC; + \converge_cnt_reg[1]_0\ : out STD_LOGIC; + \converge_cnt_reg[6]_0\ : out STD_LOGIC; + RST_RESETDONE : out STD_LOGIC_VECTOR ( 0 to 0 ); + user_active_lane_0 : out STD_LOGIC; + converge_gen3_reg_0 : out STD_LOGIC; + gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rx0_valid_gt : in STD_LOGIC; + gt_rxvalid_0 : in STD_LOGIC; + txphaligndone_reg1_reg : in STD_LOGIC; + user_active_lane_1 : in STD_LOGIC; + txphaligndone_reg1_reg_0 : in STD_LOGIC; + txphaligndone_reg1_reg_1 : in STD_LOGIC; + txphinitdone_reg1_reg : in STD_LOGIC; + txphinitdone_reg1_reg_0 : in STD_LOGIC; + txphinitdone_reg1_reg_1 : in STD_LOGIC; + \FSM_onehot_txsync_fsm.fsm_tx_reg[5]\ : in STD_LOGIC; + \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\ : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_sel_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_pclk_in : in STD_LOGIC; + pipe_oobclk_in : in STD_LOGIC; + USER_TXRESETDONE : in STD_LOGIC; + USER_RXRESETDONE : in STD_LOGIC; + PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 ); + gt_rxcdrlock_0 : in STD_LOGIC; + RST_RXUSRCLK_RESET : in STD_LOGIC; + pipe_rxusrclk_in : in STD_LOGIC; + PIPE_RXSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 ); + RST_IDLE : in STD_LOGIC; + USER_RATE_IDLE : in STD_LOGIC; + USER_RATE_RXSYNC : in STD_LOGIC; + USER_RATE_DONE : in STD_LOGIC; + USER_RATE_GEN3 : in STD_LOGIC; + USER_RXEQ_ADAPT_DONE : in STD_LOGIC; + USER_RESETOVRD_START : in STD_LOGIC; + RST_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end pcie_7x_0_pcie_7x_0_pipe_user; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_user is + signal \converge_cnt[0]_i_1__0_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_4_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_5_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_6_n_0\ : STD_LOGIC; + signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal \converge_cnt_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \^converge_cnt_reg[15]_0\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1_n_7\ : STD_LOGIC; + signal converge_gen3_i_1_n_0 : STD_LOGIC; + signal \^converge_gen3_reg_0\ : STD_LOGIC; + signal gt_rxvalid_q_i_4_n_0 : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_i_58_n_0\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_i_59_n_0\ : STD_LOGIC; + signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \oobclk_div.oobclk_i_1_n_0\ : STD_LOGIC; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pclk_sel_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of pclk_sel_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of pclk_sel_reg1 : signal is "true"; + signal pclk_sel_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of pclk_sel_reg2 : signal is "NO"; + attribute async_reg of pclk_sel_reg2 : signal is "true"; + signal rate_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_done_reg1 : signal is "NO"; + attribute async_reg of rate_done_reg1 : signal is "true"; + signal rate_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_done_reg2 : signal is "NO"; + attribute async_reg of rate_done_reg2 : signal is "true"; + signal rate_gen3_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_gen3_reg1 : signal is "NO"; + attribute async_reg of rate_gen3_reg1 : signal is "true"; + signal rate_gen3_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_gen3_reg2 : signal is "NO"; + attribute async_reg of rate_gen3_reg2 : signal is "true"; + signal rate_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO"; + attribute async_reg of rate_idle_reg1 : signal is "true"; + signal rate_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO"; + attribute async_reg of rate_idle_reg2 : signal is "true"; + signal rate_rxsync_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_rxsync_reg1 : signal is "NO"; + attribute async_reg of rate_rxsync_reg1 : signal is "true"; + signal rate_rxsync_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_rxsync_reg2 : signal is "NO"; + attribute async_reg of rate_rxsync_reg2 : signal is "true"; + signal resetovrd_start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_start_reg1 : signal is "NO"; + attribute async_reg of resetovrd_start_reg1 : signal is "true"; + signal resetovrd_start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_start_reg2 : signal is "NO"; + attribute async_reg of resetovrd_start_reg2 : signal is "true"; + signal rst_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO"; + attribute async_reg of rst_idle_reg1 : signal is "true"; + signal rst_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO"; + attribute async_reg of rst_idle_reg2 : signal is "true"; + signal rxcdrlock_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rxcdrlock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO"; + attribute async_reg of rxcdrlock_reg1 : signal is "true"; + signal rxcdrlock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO"; + attribute async_reg of rxcdrlock_reg2 : signal is "true"; + signal rxeq_adapt_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1 : signal is "NO"; + attribute async_reg of rxeq_adapt_done_reg1 : signal is "true"; + signal rxeq_adapt_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2 : signal is "NO"; + attribute async_reg of rxeq_adapt_done_reg2 : signal is "true"; + signal rxresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO"; + attribute async_reg of rxresetdone_reg1 : signal is "true"; + signal rxresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO"; + attribute async_reg of rxresetdone_reg2 : signal is "true"; + signal rxstatus_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxstatus_reg1 : signal is "NO"; + attribute async_reg of rxstatus_reg1 : signal is "true"; + signal rxstatus_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxstatus_reg2 : signal is "NO"; + attribute async_reg of rxstatus_reg2 : signal is "true"; + signal rxvalid_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rxvalid_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxvalid_reg1 : signal is "NO"; + attribute async_reg of rxvalid_reg1 : signal is "true"; + signal rxvalid_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxvalid_reg2 : signal is "NO"; + attribute async_reg of rxvalid_reg2 : signal is "true"; + signal sel : STD_LOGIC; + signal txcompliance_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txcompliance_reg1 : signal is "NO"; + attribute async_reg of txcompliance_reg1 : signal is "true"; + signal txcompliance_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txcompliance_reg2 : signal is "NO"; + attribute async_reg of txcompliance_reg2 : signal is "true"; + signal txelecidle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txelecidle_reg1 : signal is "NO"; + attribute async_reg of txelecidle_reg1 : signal is "true"; + signal txelecidle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txelecidle_reg2 : signal is "NO"; + attribute async_reg of txelecidle_reg2 : signal is "true"; + signal txresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO"; + attribute async_reg of txresetdone_reg1 : signal is "true"; + signal txresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO"; + attribute async_reg of txresetdone_reg2 : signal is "true"; + signal \NLW_converge_cnt_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_converge_cnt_reg[20]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \converge_cnt_reg[0]_i_3\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[12]_i_1\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[16]_i_1\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[20]_i_1\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[4]_i_1\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[8]_i_1\ : label is 11; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1\ : label is "soft_lutpair79"; + attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1\ : label is "soft_lutpair79"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of pclk_sel_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of pclk_sel_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of pclk_sel_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of pclk_sel_reg2_reg : label is std.standard.true; + attribute KEEP of pclk_sel_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of pclk_sel_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_done_reg1_reg : label is std.standard.true; + attribute KEEP of rate_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_done_reg2_reg : label is std.standard.true; + attribute KEEP of rate_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_done_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_gen3_reg1_reg : label is std.standard.true; + attribute KEEP of rate_gen3_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_gen3_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_gen3_reg2_reg : label is std.standard.true; + attribute KEEP of rate_gen3_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_gen3_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_rxsync_reg1_reg : label is std.standard.true; + attribute KEEP of rate_rxsync_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_rxsync_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_rxsync_reg2_reg : label is std.standard.true; + attribute KEEP of rate_rxsync_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_rxsync_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of resetovrd_start_reg1_reg : label is std.standard.true; + attribute KEEP of resetovrd_start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of resetovrd_start_reg2_reg : label is std.standard.true; + attribute KEEP of resetovrd_start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_adapt_done_reg1_reg : label is std.standard.true; + attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_adapt_done_reg2_reg : label is std.standard.true; + attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxstatus_reg1_reg : label is std.standard.true; + attribute KEEP of rxstatus_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxstatus_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxstatus_reg2_reg : label is std.standard.true; + attribute KEEP of rxstatus_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxstatus_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxvalid_reg1_reg : label is std.standard.true; + attribute KEEP of rxvalid_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxvalid_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxvalid_reg2_reg : label is std.standard.true; + attribute KEEP of rxvalid_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxvalid_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txcompliance_reg1_reg : label is std.standard.true; + attribute KEEP of txcompliance_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txcompliance_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txcompliance_reg2_reg : label is std.standard.true; + attribute KEEP of txcompliance_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txcompliance_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txelecidle_reg1_reg : label is std.standard.true; + attribute KEEP of txelecidle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txelecidle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txelecidle_reg2_reg : label is std.standard.true; + attribute KEEP of txelecidle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txelecidle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO"; +begin + \converge_cnt_reg[15]_0\ <= \^converge_cnt_reg[15]_0\; + converge_gen3_reg_0 <= \^converge_gen3_reg_0\; + \out\ <= rst_idle_reg2; + txcompliance_reg2_reg_0 <= txcompliance_reg2; + txelecidle_reg2_reg_0 <= txelecidle_reg2; +\FSM_onehot_txsync_fsm.fsm_tx[5]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7077" + ) + port map ( + I0 => txelecidle_reg2, + I1 => txcompliance_reg2, + I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg[5]\, + I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\, + O => txelecidle_reg2_reg_1 + ); +\FSM_onehot_txsync_fsm.fsm_tx[5]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => txcompliance_reg2, + I1 => txelecidle_reg2, + O => user_active_lane_0 + ); +\converge_cnt[0]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => rate_gen3_reg2, + I1 => RST_CPLLRESET, + I2 => rst_idle_reg2, + I3 => rate_idle_reg2, + O => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF5555555D" + ) + port map ( + I0 => converge_cnt_reg(21), + I1 => \converge_cnt[0]_i_4_n_0\, + I2 => converge_cnt_reg(12), + I3 => converge_cnt_reg(14), + I4 => converge_cnt_reg(20), + I5 => \converge_cnt[0]_i_5_n_0\, + O => sel + ); +\converge_cnt[0]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => converge_cnt_reg(3), + I1 => converge_cnt_reg(4), + I2 => converge_cnt_reg(5), + I3 => converge_cnt_reg(7), + I4 => converge_cnt_reg(6), + O => \converge_cnt[0]_i_4_n_0\ + ); +\converge_cnt[0]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0A0B0A0F0A0B0A0B" + ) + port map ( + I0 => \^converge_cnt_reg[15]_0\, + I1 => converge_cnt_reg(13), + I2 => converge_cnt_reg(20), + I3 => converge_cnt_reg(14), + I4 => converge_cnt_reg(12), + I5 => \gtx_channel.gtxe2_channel_i_i_59_n_0\, + O => \converge_cnt[0]_i_5_n_0\ + ); +\converge_cnt[0]_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => converge_cnt_reg(0), + O => \converge_cnt[0]_i_6_n_0\ + ); +\converge_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3_n_7\, + Q => converge_cnt_reg(0), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \converge_cnt_reg[0]_i_3_n_0\, + CO(2) => \converge_cnt_reg[0]_i_3_n_1\, + CO(1) => \converge_cnt_reg[0]_i_3_n_2\, + CO(0) => \converge_cnt_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \converge_cnt_reg[0]_i_3_n_4\, + O(2) => \converge_cnt_reg[0]_i_3_n_5\, + O(1) => \converge_cnt_reg[0]_i_3_n_6\, + O(0) => \converge_cnt_reg[0]_i_3_n_7\, + S(3 downto 1) => converge_cnt_reg(3 downto 1), + S(0) => \converge_cnt[0]_i_6_n_0\ + ); +\converge_cnt_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1_n_5\, + Q => converge_cnt_reg(10), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1_n_4\, + Q => converge_cnt_reg(11), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1_n_7\, + Q => converge_cnt_reg(12), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[8]_i_1_n_0\, + CO(3) => \converge_cnt_reg[12]_i_1_n_0\, + CO(2) => \converge_cnt_reg[12]_i_1_n_1\, + CO(1) => \converge_cnt_reg[12]_i_1_n_2\, + CO(0) => \converge_cnt_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[12]_i_1_n_4\, + O(2) => \converge_cnt_reg[12]_i_1_n_5\, + O(1) => \converge_cnt_reg[12]_i_1_n_6\, + O(0) => \converge_cnt_reg[12]_i_1_n_7\, + S(3 downto 0) => converge_cnt_reg(15 downto 12) + ); +\converge_cnt_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1_n_6\, + Q => converge_cnt_reg(13), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1_n_5\, + Q => converge_cnt_reg(14), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1_n_4\, + Q => converge_cnt_reg(15), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1_n_7\, + Q => converge_cnt_reg(16), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[12]_i_1_n_0\, + CO(3) => \converge_cnt_reg[16]_i_1_n_0\, + CO(2) => \converge_cnt_reg[16]_i_1_n_1\, + CO(1) => \converge_cnt_reg[16]_i_1_n_2\, + CO(0) => \converge_cnt_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[16]_i_1_n_4\, + O(2) => \converge_cnt_reg[16]_i_1_n_5\, + O(1) => \converge_cnt_reg[16]_i_1_n_6\, + O(0) => \converge_cnt_reg[16]_i_1_n_7\, + S(3 downto 0) => converge_cnt_reg(19 downto 16) + ); +\converge_cnt_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1_n_6\, + Q => converge_cnt_reg(17), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1_n_5\, + Q => converge_cnt_reg(18), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1_n_4\, + Q => converge_cnt_reg(19), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3_n_6\, + Q => converge_cnt_reg(1), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[20]_i_1_n_7\, + Q => converge_cnt_reg(20), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[16]_i_1_n_0\, + CO(3 downto 1) => \NLW_converge_cnt_reg[20]_i_1_CO_UNCONNECTED\(3 downto 1), + CO(0) => \converge_cnt_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 2) => \NLW_converge_cnt_reg[20]_i_1_O_UNCONNECTED\(3 downto 2), + O(1) => \converge_cnt_reg[20]_i_1_n_6\, + O(0) => \converge_cnt_reg[20]_i_1_n_7\, + S(3 downto 2) => B"00", + S(1 downto 0) => converge_cnt_reg(21 downto 20) + ); +\converge_cnt_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[20]_i_1_n_6\, + Q => converge_cnt_reg(21), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3_n_5\, + Q => converge_cnt_reg(2), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3_n_4\, + Q => converge_cnt_reg(3), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1_n_7\, + Q => converge_cnt_reg(4), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[0]_i_3_n_0\, + CO(3) => \converge_cnt_reg[4]_i_1_n_0\, + CO(2) => \converge_cnt_reg[4]_i_1_n_1\, + CO(1) => \converge_cnt_reg[4]_i_1_n_2\, + CO(0) => \converge_cnt_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[4]_i_1_n_4\, + O(2) => \converge_cnt_reg[4]_i_1_n_5\, + O(1) => \converge_cnt_reg[4]_i_1_n_6\, + O(0) => \converge_cnt_reg[4]_i_1_n_7\, + S(3 downto 0) => converge_cnt_reg(7 downto 4) + ); +\converge_cnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1_n_6\, + Q => converge_cnt_reg(5), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1_n_5\, + Q => converge_cnt_reg(6), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1_n_4\, + Q => converge_cnt_reg(7), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1_n_7\, + Q => converge_cnt_reg(8), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +\converge_cnt_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[4]_i_1_n_0\, + CO(3) => \converge_cnt_reg[8]_i_1_n_0\, + CO(2) => \converge_cnt_reg[8]_i_1_n_1\, + CO(1) => \converge_cnt_reg[8]_i_1_n_2\, + CO(0) => \converge_cnt_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[8]_i_1_n_4\, + O(2) => \converge_cnt_reg[8]_i_1_n_5\, + O(1) => \converge_cnt_reg[8]_i_1_n_6\, + O(0) => \converge_cnt_reg[8]_i_1_n_7\, + S(3 downto 0) => converge_cnt_reg(11 downto 8) + ); +\converge_cnt_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1_n_6\, + Q => converge_cnt_reg(9), + R => \converge_cnt[0]_i_1__0_n_0\ + ); +converge_gen3_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"C8" + ) + port map ( + I0 => rxeq_adapt_done_reg2, + I1 => rate_gen3_reg2, + I2 => \^converge_gen3_reg_0\, + O => converge_gen3_i_1_n_0 + ); +converge_gen3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_gen3_i_1_n_0, + Q => \^converge_gen3_reg_0\, + R => RST_CPLLRESET + ); +gt_rx_phy_status_q_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFA8FF" + ) + port map ( + I0 => RST_PHYSTATUS(0), + I1 => rate_idle_reg2, + I2 => rate_rxsync_reg2, + I3 => rst_idle_reg2, + I4 => rate_done_reg2, + O => gt_rx_phy_status_wire_filter(0) + ); +gt_rxvalid_q_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000000000000000" + ) + port map ( + I0 => gt_rx_elec_idle_wire_filter(0), + I1 => pipe_rx0_valid_gt, + I2 => gt_rxvalid_q_i_4_n_0, + I3 => gt_rxvalid_0, + I4 => rst_idle_reg2, + I5 => rate_idle_reg2, + O => gt_rxvalid_q_reg + ); +gt_rxvalid_q_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => rxvalid_cnt_reg(0), + I1 => rxvalid_cnt_reg(1), + I2 => rxvalid_cnt_reg(2), + I3 => rxvalid_cnt_reg(3), + O => gt_rxvalid_q_i_4_n_0 + ); +\gtx_channel.gtxe2_channel_i_i_49\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000020000" + ) + port map ( + I0 => \gtx_channel.gtxe2_channel_i_i_58_n_0\, + I1 => converge_cnt_reg(1), + I2 => converge_cnt_reg(0), + I3 => converge_cnt_reg(2), + I4 => converge_cnt_reg(3), + I5 => \gtx_channel.gtxe2_channel_i_i_59_n_0\, + O => \converge_cnt_reg[1]_0\ + ); +\gtx_channel.gtxe2_channel_i_i_50\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0001000000000000" + ) + port map ( + I0 => converge_cnt_reg(6), + I1 => converge_cnt_reg(7), + I2 => converge_cnt_reg(4), + I3 => converge_cnt_reg(5), + I4 => converge_cnt_reg(21), + I5 => converge_cnt_reg(13), + O => \converge_cnt_reg[6]_0\ + ); +\gtx_channel.gtxe2_channel_i_i_51\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFFFFFF" + ) + port map ( + I0 => converge_cnt_reg(15), + I1 => converge_cnt_reg(18), + I2 => converge_cnt_reg(19), + I3 => converge_cnt_reg(17), + I4 => converge_cnt_reg(16), + O => \^converge_cnt_reg[15]_0\ + ); +\gtx_channel.gtxe2_channel_i_i_58\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => converge_cnt_reg(20), + I1 => converge_cnt_reg(14), + I2 => converge_cnt_reg(12), + O => \gtx_channel.gtxe2_channel_i_i_58_n_0\ + ); +\gtx_channel.gtxe2_channel_i_i_59\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => converge_cnt_reg(9), + I1 => converge_cnt_reg(8), + I2 => converge_cnt_reg(11), + I3 => converge_cnt_reg(10), + O => \gtx_channel.gtxe2_channel_i_i_59_n_0\ + ); +\oobclk_div.oobclk_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => oobclk_cnt(0), + O => \p_1_in__0\(0) + ); +\oobclk_div.oobclk_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => oobclk_cnt(0), + I1 => oobclk_cnt(1), + O => \p_1_in__0\(1) + ); +\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_oobclk_in, + CE => '1', + D => \p_1_in__0\(0), + Q => oobclk_cnt(0), + R => RST_CPLLRESET + ); +\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_oobclk_in, + CE => '1', + D => \p_1_in__0\(1), + Q => oobclk_cnt(1), + R => RST_CPLLRESET + ); +\oobclk_div.oobclk_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => oobclk_cnt(1), + I1 => pclk_sel_reg2, + I2 => oobclk_cnt(0), + O => \oobclk_div.oobclk_i_1_n_0\ + ); +\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_oobclk_in, + CE => '1', + D => \oobclk_div.oobclk_i_1_n_0\, + Q => USER_OOBCLK, + R => RST_CPLLRESET + ); +pclk_sel_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_pclk_sel_out(0), + Q => pclk_sel_reg1, + R => RST_CPLLRESET + ); +pclk_sel_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pclk_sel_reg1, + Q => pclk_sel_reg2, + R => RST_CPLLRESET + ); +rate_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_DONE, + Q => rate_done_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_done_reg1, + Q => rate_done_reg2, + R => RST_RXUSRCLK_RESET + ); +rate_gen3_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_GEN3, + Q => rate_gen3_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_gen3_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_gen3_reg1, + Q => rate_gen3_reg2, + R => RST_RXUSRCLK_RESET + ); +rate_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_IDLE, + Q => rate_idle_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_idle_reg1, + Q => rate_idle_reg2, + R => RST_RXUSRCLK_RESET + ); +rate_rxsync_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_RXSYNC, + Q => rate_rxsync_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_rxsync_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_rxsync_reg1, + Q => rate_rxsync_reg2, + R => RST_RXUSRCLK_RESET + ); +\resetdone_reg1[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => rxresetdone_reg2, + I1 => txresetdone_reg2, + O => RST_RESETDONE(0) + ); +resetovrd_start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RESETOVRD_START, + Q => resetovrd_start_reg1, + R => RST_CPLLRESET + ); +resetovrd_start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => resetovrd_start_reg1, + Q => resetovrd_start_reg2, + R => RST_CPLLRESET + ); +rst_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => RST_IDLE, + Q => rst_idle_reg1, + R => RST_RXUSRCLK_RESET + ); +rst_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rst_idle_reg1, + Q => rst_idle_reg2, + R => RST_RXUSRCLK_RESET + ); +\rxcdrlock_cnt[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D0505050" + ) + port map ( + I0 => rxcdrlock_cnt_reg(0), + I1 => rxcdrlock_cnt_reg(2), + I2 => rxcdrlock_reg2, + I3 => rxcdrlock_cnt_reg(1), + I4 => rxcdrlock_cnt_reg(3), + O => \p_0_in__0\(0) + ); +\rxcdrlock_cnt[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8FF00000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(3), + I1 => rxcdrlock_cnt_reg(2), + I2 => rxcdrlock_cnt_reg(0), + I3 => rxcdrlock_cnt_reg(1), + I4 => rxcdrlock_reg2, + O => \p_0_in__0\(1) + ); +\rxcdrlock_cnt[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F8780000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(0), + I1 => rxcdrlock_cnt_reg(1), + I2 => rxcdrlock_cnt_reg(2), + I3 => rxcdrlock_cnt_reg(3), + I4 => rxcdrlock_reg2, + O => \p_0_in__0\(2) + ); +\rxcdrlock_cnt[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF008000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(0), + I1 => rxcdrlock_cnt_reg(1), + I2 => rxcdrlock_cnt_reg(2), + I3 => rxcdrlock_reg2, + I4 => rxcdrlock_cnt_reg(3), + O => \p_0_in__0\(3) + ); +\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(0), + Q => rxcdrlock_cnt_reg(0), + R => RST_CPLLRESET + ); +\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(1), + Q => rxcdrlock_cnt_reg(1), + R => RST_CPLLRESET + ); +\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(2), + Q => rxcdrlock_cnt_reg(2), + R => RST_CPLLRESET + ); +\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(3), + Q => rxcdrlock_cnt_reg(3), + R => RST_CPLLRESET + ); +\rxcdrlock_reg1[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(2), + I1 => rxcdrlock_cnt_reg(3), + I2 => gt_rxcdrlock_0, + I3 => rxcdrlock_cnt_reg(1), + I4 => rxcdrlock_cnt_reg(0), + O => RST_RXCDRLOCK(0) + ); +rxcdrlock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rxcdrlock_0, + Q => rxcdrlock_reg1, + R => RST_CPLLRESET + ); +rxcdrlock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxcdrlock_reg1, + Q => rxcdrlock_reg2, + R => RST_CPLLRESET + ); +rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RXEQ_ADAPT_DONE, + Q => rxeq_adapt_done_reg1, + R => RST_CPLLRESET + ); +rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_adapt_done_reg1, + Q => rxeq_adapt_done_reg2, + R => RST_CPLLRESET + ); +rxresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RXRESETDONE, + Q => rxresetdone_reg1, + R => RST_CPLLRESET + ); +rxresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxresetdone_reg1, + Q => rxresetdone_reg2, + R => RST_CPLLRESET + ); +rxstatus_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => PIPE_RXSTATUS(0), + Q => rxstatus_reg1, + R => RST_RXUSRCLK_RESET + ); +rxstatus_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rxstatus_reg1, + Q => rxstatus_reg2, + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C404040404040404" + ) + port map ( + I0 => rxstatus_reg2, + I1 => rxvalid_reg2, + I2 => rxvalid_cnt_reg(0), + I3 => rxvalid_cnt_reg(1), + I4 => rxvalid_cnt_reg(2), + I5 => rxvalid_cnt_reg(3), + O => \p_0_in__0__0\(0) + ); +\rxvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"808000F000F00000" + ) + port map ( + I0 => rxvalid_cnt_reg(3), + I1 => rxvalid_cnt_reg(2), + I2 => rxvalid_reg2, + I3 => rxstatus_reg2, + I4 => rxvalid_cnt_reg(1), + I5 => rxvalid_cnt_reg(0), + O => \p_0_in__0__0\(1) + ); +\rxvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"80BF000000C00000" + ) + port map ( + I0 => rxvalid_cnt_reg(3), + I1 => rxvalid_cnt_reg(0), + I2 => rxvalid_cnt_reg(1), + I3 => rxstatus_reg2, + I4 => rxvalid_reg2, + I5 => rxvalid_cnt_reg(2), + O => \p_0_in__0__0\(2) + ); +\rxvalid_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8C08080808080808" + ) + port map ( + I0 => rxvalid_cnt_reg(3), + I1 => rxvalid_reg2, + I2 => rxstatus_reg2, + I3 => rxvalid_cnt_reg(2), + I4 => rxvalid_cnt_reg(1), + I5 => rxvalid_cnt_reg(0), + O => \p_0_in__0__0\(3) + ); +\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(0), + Q => rxvalid_cnt_reg(0), + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(1), + Q => rxvalid_cnt_reg(1), + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(2), + Q => rxvalid_cnt_reg(2), + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(3), + Q => rxvalid_cnt_reg(3), + R => RST_RXUSRCLK_RESET + ); +rxvalid_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => gt_rxvalid_0, + Q => rxvalid_reg1, + R => RST_RXUSRCLK_RESET + ); +rxvalid_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rxvalid_reg1, + Q => rxvalid_reg2, + R => RST_RXUSRCLK_RESET + ); +txcompliance_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_TXCOMPLIANCE(0), + Q => txcompliance_reg1, + R => RST_CPLLRESET + ); +txcompliance_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcompliance_reg1, + Q => txcompliance_reg2, + R => RST_CPLLRESET + ); +txelecidle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_TXELECIDLE(0), + Q => txelecidle_reg1, + R => RST_CPLLRESET + ); +txelecidle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txelecidle_reg1, + Q => txelecidle_reg2, + R => RST_CPLLRESET + ); +txphaligndone_reg1_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000BBB0B0B0" + ) + port map ( + I0 => txphaligndone_reg1_reg, + I1 => user_active_lane_1, + I2 => txphaligndone_reg1_reg_0, + I3 => txelecidle_reg2, + I4 => txcompliance_reg2, + I5 => txphaligndone_reg1_reg_1, + O => SYNC_TXPHALIGNDONE + ); +txphinitdone_reg1_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000BBB0B0B0" + ) + port map ( + I0 => txphinitdone_reg1_reg, + I1 => user_active_lane_1, + I2 => txphinitdone_reg1_reg_0, + I3 => txelecidle_reg2, + I4 => txcompliance_reg2, + I5 => txphinitdone_reg1_reg_1, + O => SYNC_TXPHINITDONE + ); +txresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_TXRESETDONE, + Q => txresetdone_reg1, + R => RST_CPLLRESET + ); +txresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txresetdone_reg1, + Q => txresetdone_reg2, + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_user_42 is + port ( + gt_rxvalid_q_reg : out STD_LOGIC; + \out\ : out STD_LOGIC; + txelecidle_reg2_reg_0 : out STD_LOGIC; + txcompliance_reg2_reg_0 : out STD_LOGIC; + USER_OOBCLK : out STD_LOGIC; + RST_RXCDRLOCK : out STD_LOGIC_VECTOR ( 0 to 0 ); + gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 ); + user_rx_converge : out STD_LOGIC_VECTOR ( 0 to 0 ); + RST_RESETDONE : out STD_LOGIC_VECTOR ( 0 to 0 ); + user_active_lane_1 : out STD_LOGIC; + gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rx1_valid_gt : in STD_LOGIC; + gt_rxvalid_1 : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_sel_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_pclk_in : in STD_LOGIC; + pipe_oobclk_in : in STD_LOGIC; + USER_TXRESETDONE : in STD_LOGIC; + USER_RXRESETDONE : in STD_LOGIC; + PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 ); + gt_rxcdrlock_1 : in STD_LOGIC; + RST_RXUSRCLK_RESET : in STD_LOGIC; + pipe_rxusrclk_in : in STD_LOGIC; + rxstatus_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + RST_IDLE : in STD_LOGIC; + USER_RATE_IDLE : in STD_LOGIC; + USER_RATE_RXSYNC : in STD_LOGIC; + USER_RATE_DONE : in STD_LOGIC; + USER_RATE_GEN3 : in STD_LOGIC; + USER_RXEQ_ADAPT_DONE : in STD_LOGIC; + USER_RESETOVRD_START : in STD_LOGIC; + RST_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_user_42 : entity is "pcie_7x_0_pipe_user"; +end pcie_7x_0_pcie_7x_0_pipe_user_42; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_user_42 is + signal \converge_cnt[0]_i_1__2_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_4__0_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_5__0_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_6__0_n_0\ : STD_LOGIC; + signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal \converge_cnt_reg[0]_i_3__0_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__0_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__0_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__0_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__0_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__0_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__0_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__0_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__0_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__0_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__0_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__0_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__0_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__0_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__0_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__0_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__0_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__0_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__0_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__0_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__0_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__0_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__0_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__0_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_1__0_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_1__0_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_1__0_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__0_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__0_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__0_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__0_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__0_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__0_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__0_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__0_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__0_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__0_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__0_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__0_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__0_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__0_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__0_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__0_n_7\ : STD_LOGIC; + signal \converge_gen3_i_1__0_n_0\ : STD_LOGIC; + signal converge_gen3_reg_n_0 : STD_LOGIC; + signal \gt_rxvalid_q_i_4__0_n_0\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_i_53_n_0\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_i_54_n_0\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_i_55_n_0\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_i_56_n_0\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_i_57_n_0\ : STD_LOGIC; + signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \oobclk_div.oobclk_i_1__0_n_0\ : STD_LOGIC; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pclk_sel_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of pclk_sel_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of pclk_sel_reg1 : signal is "true"; + signal pclk_sel_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of pclk_sel_reg2 : signal is "NO"; + attribute async_reg of pclk_sel_reg2 : signal is "true"; + signal rate_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_done_reg1 : signal is "NO"; + attribute async_reg of rate_done_reg1 : signal is "true"; + signal rate_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_done_reg2 : signal is "NO"; + attribute async_reg of rate_done_reg2 : signal is "true"; + signal rate_gen3_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_gen3_reg1 : signal is "NO"; + attribute async_reg of rate_gen3_reg1 : signal is "true"; + signal rate_gen3_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_gen3_reg2 : signal is "NO"; + attribute async_reg of rate_gen3_reg2 : signal is "true"; + signal rate_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO"; + attribute async_reg of rate_idle_reg1 : signal is "true"; + signal rate_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO"; + attribute async_reg of rate_idle_reg2 : signal is "true"; + signal rate_rxsync_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_rxsync_reg1 : signal is "NO"; + attribute async_reg of rate_rxsync_reg1 : signal is "true"; + signal rate_rxsync_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_rxsync_reg2 : signal is "NO"; + attribute async_reg of rate_rxsync_reg2 : signal is "true"; + signal resetovrd_start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_start_reg1 : signal is "NO"; + attribute async_reg of resetovrd_start_reg1 : signal is "true"; + signal resetovrd_start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_start_reg2 : signal is "NO"; + attribute async_reg of resetovrd_start_reg2 : signal is "true"; + signal rst_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO"; + attribute async_reg of rst_idle_reg1 : signal is "true"; + signal rst_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO"; + attribute async_reg of rst_idle_reg2 : signal is "true"; + signal rxcdrlock_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rxcdrlock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO"; + attribute async_reg of rxcdrlock_reg1 : signal is "true"; + signal rxcdrlock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO"; + attribute async_reg of rxcdrlock_reg2 : signal is "true"; + signal rxeq_adapt_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1 : signal is "NO"; + attribute async_reg of rxeq_adapt_done_reg1 : signal is "true"; + signal rxeq_adapt_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2 : signal is "NO"; + attribute async_reg of rxeq_adapt_done_reg2 : signal is "true"; + signal rxresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO"; + attribute async_reg of rxresetdone_reg1 : signal is "true"; + signal rxresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO"; + attribute async_reg of rxresetdone_reg2 : signal is "true"; + signal rxstatus_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxstatus_reg1 : signal is "NO"; + attribute async_reg of rxstatus_reg1 : signal is "true"; + signal rxstatus_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxstatus_reg2 : signal is "NO"; + attribute async_reg of rxstatus_reg2 : signal is "true"; + signal rxvalid_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rxvalid_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxvalid_reg1 : signal is "NO"; + attribute async_reg of rxvalid_reg1 : signal is "true"; + signal rxvalid_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxvalid_reg2 : signal is "NO"; + attribute async_reg of rxvalid_reg2 : signal is "true"; + signal sel : STD_LOGIC; + signal txcompliance_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txcompliance_reg1 : signal is "NO"; + attribute async_reg of txcompliance_reg1 : signal is "true"; + signal txcompliance_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txcompliance_reg2 : signal is "NO"; + attribute async_reg of txcompliance_reg2 : signal is "true"; + signal txelecidle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txelecidle_reg1 : signal is "NO"; + attribute async_reg of txelecidle_reg1 : signal is "true"; + signal txelecidle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txelecidle_reg2 : signal is "NO"; + attribute async_reg of txelecidle_reg2 : signal is "true"; + signal txresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO"; + attribute async_reg of txresetdone_reg1 : signal is "true"; + signal txresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO"; + attribute async_reg of txresetdone_reg2 : signal is "true"; + signal \NLW_converge_cnt_reg[20]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_converge_cnt_reg[20]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \converge_cnt_reg[0]_i_3__0\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[12]_i_1__0\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[16]_i_1__0\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[20]_i_1__0\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[4]_i_1__0\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[8]_i_1__0\ : label is 11; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1__0\ : label is "soft_lutpair121"; + attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1__0\ : label is "soft_lutpair121"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of pclk_sel_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of pclk_sel_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of pclk_sel_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of pclk_sel_reg2_reg : label is std.standard.true; + attribute KEEP of pclk_sel_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of pclk_sel_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_done_reg1_reg : label is std.standard.true; + attribute KEEP of rate_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_done_reg2_reg : label is std.standard.true; + attribute KEEP of rate_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_done_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_gen3_reg1_reg : label is std.standard.true; + attribute KEEP of rate_gen3_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_gen3_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_gen3_reg2_reg : label is std.standard.true; + attribute KEEP of rate_gen3_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_gen3_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_rxsync_reg1_reg : label is std.standard.true; + attribute KEEP of rate_rxsync_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_rxsync_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_rxsync_reg2_reg : label is std.standard.true; + attribute KEEP of rate_rxsync_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_rxsync_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of resetovrd_start_reg1_reg : label is std.standard.true; + attribute KEEP of resetovrd_start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of resetovrd_start_reg2_reg : label is std.standard.true; + attribute KEEP of resetovrd_start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_adapt_done_reg1_reg : label is std.standard.true; + attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_adapt_done_reg2_reg : label is std.standard.true; + attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxstatus_reg1_reg : label is std.standard.true; + attribute KEEP of rxstatus_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxstatus_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxstatus_reg2_reg : label is std.standard.true; + attribute KEEP of rxstatus_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxstatus_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxvalid_reg1_reg : label is std.standard.true; + attribute KEEP of rxvalid_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxvalid_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxvalid_reg2_reg : label is std.standard.true; + attribute KEEP of rxvalid_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxvalid_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txcompliance_reg1_reg : label is std.standard.true; + attribute KEEP of txcompliance_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txcompliance_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txcompliance_reg2_reg : label is std.standard.true; + attribute KEEP of txcompliance_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txcompliance_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txelecidle_reg1_reg : label is std.standard.true; + attribute KEEP of txelecidle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txelecidle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txelecidle_reg2_reg : label is std.standard.true; + attribute KEEP of txelecidle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txelecidle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO"; +begin + \out\ <= rst_idle_reg2; + txcompliance_reg2_reg_0 <= txcompliance_reg2; + txelecidle_reg2_reg_0 <= txelecidle_reg2; +\converge_cnt[0]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => rate_gen3_reg2, + I1 => RST_CPLLRESET, + I2 => rst_idle_reg2, + I3 => rate_idle_reg2, + O => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt[0]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF5555555D" + ) + port map ( + I0 => converge_cnt_reg(21), + I1 => \converge_cnt[0]_i_4__0_n_0\, + I2 => converge_cnt_reg(12), + I3 => converge_cnt_reg(14), + I4 => converge_cnt_reg(20), + I5 => \converge_cnt[0]_i_5__0_n_0\, + O => sel + ); +\converge_cnt[0]_i_4__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => converge_cnt_reg(3), + I1 => converge_cnt_reg(4), + I2 => converge_cnt_reg(5), + I3 => converge_cnt_reg(7), + I4 => converge_cnt_reg(6), + O => \converge_cnt[0]_i_4__0_n_0\ + ); +\converge_cnt[0]_i_5__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0A0B0A0F0A0B0A0B" + ) + port map ( + I0 => \gtx_channel.gtxe2_channel_i_i_57_n_0\, + I1 => converge_cnt_reg(13), + I2 => converge_cnt_reg(20), + I3 => converge_cnt_reg(14), + I4 => converge_cnt_reg(12), + I5 => \gtx_channel.gtxe2_channel_i_i_55_n_0\, + O => \converge_cnt[0]_i_5__0_n_0\ + ); +\converge_cnt[0]_i_6__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => converge_cnt_reg(0), + O => \converge_cnt[0]_i_6__0_n_0\ + ); +\converge_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3__0_n_7\, + Q => converge_cnt_reg(0), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[0]_i_3__0\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \converge_cnt_reg[0]_i_3__0_n_0\, + CO(2) => \converge_cnt_reg[0]_i_3__0_n_1\, + CO(1) => \converge_cnt_reg[0]_i_3__0_n_2\, + CO(0) => \converge_cnt_reg[0]_i_3__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \converge_cnt_reg[0]_i_3__0_n_4\, + O(2) => \converge_cnt_reg[0]_i_3__0_n_5\, + O(1) => \converge_cnt_reg[0]_i_3__0_n_6\, + O(0) => \converge_cnt_reg[0]_i_3__0_n_7\, + S(3 downto 1) => converge_cnt_reg(3 downto 1), + S(0) => \converge_cnt[0]_i_6__0_n_0\ + ); +\converge_cnt_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1__0_n_5\, + Q => converge_cnt_reg(10), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1__0_n_4\, + Q => converge_cnt_reg(11), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1__0_n_7\, + Q => converge_cnt_reg(12), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[12]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[8]_i_1__0_n_0\, + CO(3) => \converge_cnt_reg[12]_i_1__0_n_0\, + CO(2) => \converge_cnt_reg[12]_i_1__0_n_1\, + CO(1) => \converge_cnt_reg[12]_i_1__0_n_2\, + CO(0) => \converge_cnt_reg[12]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[12]_i_1__0_n_4\, + O(2) => \converge_cnt_reg[12]_i_1__0_n_5\, + O(1) => \converge_cnt_reg[12]_i_1__0_n_6\, + O(0) => \converge_cnt_reg[12]_i_1__0_n_7\, + S(3 downto 0) => converge_cnt_reg(15 downto 12) + ); +\converge_cnt_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1__0_n_6\, + Q => converge_cnt_reg(13), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1__0_n_5\, + Q => converge_cnt_reg(14), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1__0_n_4\, + Q => converge_cnt_reg(15), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1__0_n_7\, + Q => converge_cnt_reg(16), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[16]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[12]_i_1__0_n_0\, + CO(3) => \converge_cnt_reg[16]_i_1__0_n_0\, + CO(2) => \converge_cnt_reg[16]_i_1__0_n_1\, + CO(1) => \converge_cnt_reg[16]_i_1__0_n_2\, + CO(0) => \converge_cnt_reg[16]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[16]_i_1__0_n_4\, + O(2) => \converge_cnt_reg[16]_i_1__0_n_5\, + O(1) => \converge_cnt_reg[16]_i_1__0_n_6\, + O(0) => \converge_cnt_reg[16]_i_1__0_n_7\, + S(3 downto 0) => converge_cnt_reg(19 downto 16) + ); +\converge_cnt_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1__0_n_6\, + Q => converge_cnt_reg(17), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1__0_n_5\, + Q => converge_cnt_reg(18), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1__0_n_4\, + Q => converge_cnt_reg(19), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3__0_n_6\, + Q => converge_cnt_reg(1), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[20]_i_1__0_n_7\, + Q => converge_cnt_reg(20), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[20]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[16]_i_1__0_n_0\, + CO(3 downto 1) => \NLW_converge_cnt_reg[20]_i_1__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => \converge_cnt_reg[20]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 2) => \NLW_converge_cnt_reg[20]_i_1__0_O_UNCONNECTED\(3 downto 2), + O(1) => \converge_cnt_reg[20]_i_1__0_n_6\, + O(0) => \converge_cnt_reg[20]_i_1__0_n_7\, + S(3 downto 2) => B"00", + S(1 downto 0) => converge_cnt_reg(21 downto 20) + ); +\converge_cnt_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[20]_i_1__0_n_6\, + Q => converge_cnt_reg(21), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3__0_n_5\, + Q => converge_cnt_reg(2), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3__0_n_4\, + Q => converge_cnt_reg(3), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1__0_n_7\, + Q => converge_cnt_reg(4), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[4]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[0]_i_3__0_n_0\, + CO(3) => \converge_cnt_reg[4]_i_1__0_n_0\, + CO(2) => \converge_cnt_reg[4]_i_1__0_n_1\, + CO(1) => \converge_cnt_reg[4]_i_1__0_n_2\, + CO(0) => \converge_cnt_reg[4]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[4]_i_1__0_n_4\, + O(2) => \converge_cnt_reg[4]_i_1__0_n_5\, + O(1) => \converge_cnt_reg[4]_i_1__0_n_6\, + O(0) => \converge_cnt_reg[4]_i_1__0_n_7\, + S(3 downto 0) => converge_cnt_reg(7 downto 4) + ); +\converge_cnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1__0_n_6\, + Q => converge_cnt_reg(5), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1__0_n_5\, + Q => converge_cnt_reg(6), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1__0_n_4\, + Q => converge_cnt_reg(7), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1__0_n_7\, + Q => converge_cnt_reg(8), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_cnt_reg[8]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[4]_i_1__0_n_0\, + CO(3) => \converge_cnt_reg[8]_i_1__0_n_0\, + CO(2) => \converge_cnt_reg[8]_i_1__0_n_1\, + CO(1) => \converge_cnt_reg[8]_i_1__0_n_2\, + CO(0) => \converge_cnt_reg[8]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[8]_i_1__0_n_4\, + O(2) => \converge_cnt_reg[8]_i_1__0_n_5\, + O(1) => \converge_cnt_reg[8]_i_1__0_n_6\, + O(0) => \converge_cnt_reg[8]_i_1__0_n_7\, + S(3 downto 0) => converge_cnt_reg(11 downto 8) + ); +\converge_cnt_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1__0_n_6\, + Q => converge_cnt_reg(9), + R => \converge_cnt[0]_i_1__2_n_0\ + ); +\converge_gen3_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C8" + ) + port map ( + I0 => rxeq_adapt_done_reg2, + I1 => rate_gen3_reg2, + I2 => converge_gen3_reg_n_0, + O => \converge_gen3_i_1__0_n_0\ + ); +converge_gen3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \converge_gen3_i_1__0_n_0\, + Q => converge_gen3_reg_n_0, + R => RST_CPLLRESET + ); +\gt_rx_phy_status_q_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFA8FF" + ) + port map ( + I0 => RST_PHYSTATUS(0), + I1 => rate_idle_reg2, + I2 => rate_rxsync_reg2, + I3 => rst_idle_reg2, + I4 => rate_done_reg2, + O => gt_rx_phy_status_wire_filter(0) + ); +\gt_rxvalid_q_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000000000000000" + ) + port map ( + I0 => gt_rx_elec_idle_wire_filter(0), + I1 => pipe_rx1_valid_gt, + I2 => \gt_rxvalid_q_i_4__0_n_0\, + I3 => gt_rxvalid_1, + I4 => rst_idle_reg2, + I5 => rate_idle_reg2, + O => gt_rxvalid_q_reg + ); +\gt_rxvalid_q_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => rxvalid_cnt_reg(0), + I1 => rxvalid_cnt_reg(1), + I2 => rxvalid_cnt_reg(2), + I3 => rxvalid_cnt_reg(3), + O => \gt_rxvalid_q_i_4__0_n_0\ + ); +\gtx_channel.gtxe2_channel_i_i_48\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00000800" + ) + port map ( + I0 => \gtx_channel.gtxe2_channel_i_i_53_n_0\, + I1 => \gtx_channel.gtxe2_channel_i_i_54_n_0\, + I2 => \gtx_channel.gtxe2_channel_i_i_55_n_0\, + I3 => \gtx_channel.gtxe2_channel_i_i_56_n_0\, + I4 => \gtx_channel.gtxe2_channel_i_i_57_n_0\, + I5 => converge_gen3_reg_n_0, + O => user_rx_converge(0) + ); +\gtx_channel.gtxe2_channel_i_i_53\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => converge_cnt_reg(20), + I1 => converge_cnt_reg(14), + I2 => converge_cnt_reg(12), + O => \gtx_channel.gtxe2_channel_i_i_53_n_0\ + ); +\gtx_channel.gtxe2_channel_i_i_54\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0100" + ) + port map ( + I0 => converge_cnt_reg(1), + I1 => converge_cnt_reg(0), + I2 => converge_cnt_reg(2), + I3 => converge_cnt_reg(3), + O => \gtx_channel.gtxe2_channel_i_i_54_n_0\ + ); +\gtx_channel.gtxe2_channel_i_i_55\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => converge_cnt_reg(9), + I1 => converge_cnt_reg(8), + I2 => converge_cnt_reg(11), + I3 => converge_cnt_reg(10), + O => \gtx_channel.gtxe2_channel_i_i_55_n_0\ + ); +\gtx_channel.gtxe2_channel_i_i_56\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0001000000000000" + ) + port map ( + I0 => converge_cnt_reg(6), + I1 => converge_cnt_reg(7), + I2 => converge_cnt_reg(4), + I3 => converge_cnt_reg(5), + I4 => converge_cnt_reg(21), + I5 => converge_cnt_reg(13), + O => \gtx_channel.gtxe2_channel_i_i_56_n_0\ + ); +\gtx_channel.gtxe2_channel_i_i_57\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFFFFFF" + ) + port map ( + I0 => converge_cnt_reg(15), + I1 => converge_cnt_reg(18), + I2 => converge_cnt_reg(19), + I3 => converge_cnt_reg(17), + I4 => converge_cnt_reg(16), + O => \gtx_channel.gtxe2_channel_i_i_57_n_0\ + ); +\oobclk_div.oobclk_cnt[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => oobclk_cnt(0), + O => \p_1_in__0\(0) + ); +\oobclk_div.oobclk_cnt[1]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => oobclk_cnt(0), + I1 => oobclk_cnt(1), + O => \p_1_in__0\(1) + ); +\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_oobclk_in, + CE => '1', + D => \p_1_in__0\(0), + Q => oobclk_cnt(0), + R => RST_CPLLRESET + ); +\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_oobclk_in, + CE => '1', + D => \p_1_in__0\(1), + Q => oobclk_cnt(1), + R => RST_CPLLRESET + ); +\oobclk_div.oobclk_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => oobclk_cnt(1), + I1 => pclk_sel_reg2, + I2 => oobclk_cnt(0), + O => \oobclk_div.oobclk_i_1__0_n_0\ + ); +\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_oobclk_in, + CE => '1', + D => \oobclk_div.oobclk_i_1__0_n_0\, + Q => USER_OOBCLK, + R => RST_CPLLRESET + ); +pclk_sel_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_pclk_sel_out(0), + Q => pclk_sel_reg1, + R => RST_CPLLRESET + ); +pclk_sel_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pclk_sel_reg1, + Q => pclk_sel_reg2, + R => RST_CPLLRESET + ); +rate_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_DONE, + Q => rate_done_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_done_reg1, + Q => rate_done_reg2, + R => RST_RXUSRCLK_RESET + ); +rate_gen3_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_GEN3, + Q => rate_gen3_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_gen3_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_gen3_reg1, + Q => rate_gen3_reg2, + R => RST_RXUSRCLK_RESET + ); +rate_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_IDLE, + Q => rate_idle_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_idle_reg1, + Q => rate_idle_reg2, + R => RST_RXUSRCLK_RESET + ); +rate_rxsync_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_RXSYNC, + Q => rate_rxsync_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_rxsync_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_rxsync_reg1, + Q => rate_rxsync_reg2, + R => RST_RXUSRCLK_RESET + ); +\resetdone_reg1[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => rxresetdone_reg2, + I1 => txresetdone_reg2, + O => RST_RESETDONE(0) + ); +resetovrd_start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RESETOVRD_START, + Q => resetovrd_start_reg1, + R => RST_CPLLRESET + ); +resetovrd_start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => resetovrd_start_reg1, + Q => resetovrd_start_reg2, + R => RST_CPLLRESET + ); +rst_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => RST_IDLE, + Q => rst_idle_reg1, + R => RST_RXUSRCLK_RESET + ); +rst_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rst_idle_reg1, + Q => rst_idle_reg2, + R => RST_RXUSRCLK_RESET + ); +\rxcdrlock_cnt[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D0505050" + ) + port map ( + I0 => rxcdrlock_cnt_reg(0), + I1 => rxcdrlock_cnt_reg(2), + I2 => rxcdrlock_reg2, + I3 => rxcdrlock_cnt_reg(1), + I4 => rxcdrlock_cnt_reg(3), + O => \p_0_in__0\(0) + ); +\rxcdrlock_cnt[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8FF00000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(3), + I1 => rxcdrlock_cnt_reg(2), + I2 => rxcdrlock_cnt_reg(0), + I3 => rxcdrlock_cnt_reg(1), + I4 => rxcdrlock_reg2, + O => \p_0_in__0\(1) + ); +\rxcdrlock_cnt[2]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F8780000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(0), + I1 => rxcdrlock_cnt_reg(1), + I2 => rxcdrlock_cnt_reg(2), + I3 => rxcdrlock_cnt_reg(3), + I4 => rxcdrlock_reg2, + O => \p_0_in__0\(2) + ); +\rxcdrlock_cnt[3]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF008000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(0), + I1 => rxcdrlock_cnt_reg(1), + I2 => rxcdrlock_cnt_reg(2), + I3 => rxcdrlock_reg2, + I4 => rxcdrlock_cnt_reg(3), + O => \p_0_in__0\(3) + ); +\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(0), + Q => rxcdrlock_cnt_reg(0), + R => RST_CPLLRESET + ); +\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(1), + Q => rxcdrlock_cnt_reg(1), + R => RST_CPLLRESET + ); +\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(2), + Q => rxcdrlock_cnt_reg(2), + R => RST_CPLLRESET + ); +\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(3), + Q => rxcdrlock_cnt_reg(3), + R => RST_CPLLRESET + ); +\rxcdrlock_reg1[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(2), + I1 => rxcdrlock_cnt_reg(3), + I2 => gt_rxcdrlock_1, + I3 => rxcdrlock_cnt_reg(1), + I4 => rxcdrlock_cnt_reg(0), + O => RST_RXCDRLOCK(0) + ); +rxcdrlock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rxcdrlock_1, + Q => rxcdrlock_reg1, + R => RST_CPLLRESET + ); +rxcdrlock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxcdrlock_reg1, + Q => rxcdrlock_reg2, + R => RST_CPLLRESET + ); +rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RXEQ_ADAPT_DONE, + Q => rxeq_adapt_done_reg1, + R => RST_CPLLRESET + ); +rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_adapt_done_reg1, + Q => rxeq_adapt_done_reg2, + R => RST_CPLLRESET + ); +rxresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RXRESETDONE, + Q => rxresetdone_reg1, + R => RST_CPLLRESET + ); +rxresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxresetdone_reg1, + Q => rxresetdone_reg2, + R => RST_CPLLRESET + ); +rxstatus_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rxstatus_reg1_reg_0(0), + Q => rxstatus_reg1, + R => RST_RXUSRCLK_RESET + ); +rxstatus_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rxstatus_reg1, + Q => rxstatus_reg2, + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C404040404040404" + ) + port map ( + I0 => rxstatus_reg2, + I1 => rxvalid_reg2, + I2 => rxvalid_cnt_reg(0), + I3 => rxvalid_cnt_reg(1), + I4 => rxvalid_cnt_reg(2), + I5 => rxvalid_cnt_reg(3), + O => \p_0_in__0__0\(0) + ); +\rxvalid_cnt[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"808000F000F00000" + ) + port map ( + I0 => rxvalid_cnt_reg(3), + I1 => rxvalid_cnt_reg(2), + I2 => rxvalid_reg2, + I3 => rxstatus_reg2, + I4 => rxvalid_cnt_reg(1), + I5 => rxvalid_cnt_reg(0), + O => \p_0_in__0__0\(1) + ); +\rxvalid_cnt[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"80BF000000C00000" + ) + port map ( + I0 => rxvalid_cnt_reg(3), + I1 => rxvalid_cnt_reg(0), + I2 => rxvalid_cnt_reg(1), + I3 => rxstatus_reg2, + I4 => rxvalid_reg2, + I5 => rxvalid_cnt_reg(2), + O => \p_0_in__0__0\(2) + ); +\rxvalid_cnt[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8C08080808080808" + ) + port map ( + I0 => rxvalid_cnt_reg(3), + I1 => rxvalid_reg2, + I2 => rxstatus_reg2, + I3 => rxvalid_cnt_reg(2), + I4 => rxvalid_cnt_reg(1), + I5 => rxvalid_cnt_reg(0), + O => \p_0_in__0__0\(3) + ); +\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(0), + Q => rxvalid_cnt_reg(0), + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(1), + Q => rxvalid_cnt_reg(1), + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(2), + Q => rxvalid_cnt_reg(2), + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(3), + Q => rxvalid_cnt_reg(3), + R => RST_RXUSRCLK_RESET + ); +rxvalid_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => gt_rxvalid_1, + Q => rxvalid_reg1, + R => RST_RXUSRCLK_RESET + ); +rxvalid_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rxvalid_reg1, + Q => rxvalid_reg2, + R => RST_RXUSRCLK_RESET + ); +txcompliance_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_TXCOMPLIANCE(0), + Q => txcompliance_reg1, + R => RST_CPLLRESET + ); +txcompliance_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcompliance_reg1, + Q => txcompliance_reg2, + R => RST_CPLLRESET + ); +txelecidle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_TXELECIDLE(0), + Q => txelecidle_reg1, + R => RST_CPLLRESET + ); +txelecidle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txelecidle_reg1, + Q => txelecidle_reg2, + R => RST_CPLLRESET + ); +txphaligndone_reg1_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => txcompliance_reg2, + I1 => txelecidle_reg2, + O => user_active_lane_1 + ); +txresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_TXRESETDONE, + Q => txresetdone_reg1, + R => RST_CPLLRESET + ); +txresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txresetdone_reg1, + Q => txresetdone_reg2, + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_user_48 is + port ( + reg_clock_locked_reg : out STD_LOGIC; + gt_rxvalid_q_reg : out STD_LOGIC; + txcompliance_reg2_reg_0 : out STD_LOGIC; + txcompliance_reg2_reg_1 : out STD_LOGIC; + txelecidle_reg2_reg_0 : out STD_LOGIC; + txcompliance_reg2_reg_2 : out STD_LOGIC; + USER_OOBCLK : out STD_LOGIC; + RST_RXCDRLOCK : out STD_LOGIC_VECTOR ( 0 to 0 ); + gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 ); + \converge_cnt_reg[15]_0\ : out STD_LOGIC; + \converge_cnt_reg[1]_0\ : out STD_LOGIC; + \converge_cnt_reg[6]_0\ : out STD_LOGIC; + RST_RESETDONE : out STD_LOGIC_VECTOR ( 0 to 0 ); + user_active_lane_2 : out STD_LOGIC; + converge_gen3_reg_0 : out STD_LOGIC; + reg_clock_locked : in STD_LOGIC; + \out\ : in STD_LOGIC; + phy_rdy_n_int_reg : in STD_LOGIC; + phy_rdy_n_int_reg_0 : in STD_LOGIC; + gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rx2_valid_gt : in STD_LOGIC; + gt_rxvalid_2 : in STD_LOGIC; + txphaligndone_reg1_reg : in STD_LOGIC; + txphaligndone_reg1_reg_0 : in STD_LOGIC; + txphaligndone_reg1_reg_1 : in STD_LOGIC; + txphaligndone_reg1_reg_2 : in STD_LOGIC; + txphinitdone_reg1_reg : in STD_LOGIC; + txphinitdone_reg1_reg_0 : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_sel_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_pclk_in : in STD_LOGIC; + pipe_oobclk_in : in STD_LOGIC; + USER_TXRESETDONE : in STD_LOGIC; + USER_RXRESETDONE : in STD_LOGIC; + PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 ); + gt_rxcdrlock_2 : in STD_LOGIC; + RST_RXUSRCLK_RESET : in STD_LOGIC; + pipe_rxusrclk_in : in STD_LOGIC; + rxstatus_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + RST_IDLE : in STD_LOGIC; + USER_RATE_IDLE : in STD_LOGIC; + USER_RATE_RXSYNC : in STD_LOGIC; + USER_RATE_DONE : in STD_LOGIC; + rate_gen3_2 : in STD_LOGIC; + USER_RXEQ_ADAPT_DONE : in STD_LOGIC; + USER_RESETOVRD_START : in STD_LOGIC; + RST_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_user_48 : entity is "pcie_7x_0_pipe_user"; +end pcie_7x_0_pcie_7x_0_pipe_user_48; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_user_48 is + signal \converge_cnt[0]_i_1__4_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_4__1_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_5__1_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_6__1_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_7_n_0\ : STD_LOGIC; + signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal \converge_cnt_reg[0]_i_3__1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__1_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__1_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__1_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__1_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__1_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__1_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__1_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__1_n_7\ : STD_LOGIC; + signal \^converge_cnt_reg[15]_0\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__1_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__1_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__1_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__1_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_1__1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_1__1_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_1__1_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__1_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__1_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__1_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__1_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__1_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__1_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__1_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__1_n_7\ : STD_LOGIC; + signal \converge_gen3_i_1__1_n_0\ : STD_LOGIC; + signal \^converge_gen3_reg_0\ : STD_LOGIC; + signal \gt_rxvalid_q_i_4__1_n_0\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_i_64_n_0\ : STD_LOGIC; + signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \oobclk_div.oobclk_i_1__1_n_0\ : STD_LOGIC; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pclk_sel_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of pclk_sel_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of pclk_sel_reg1 : signal is "true"; + signal pclk_sel_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of pclk_sel_reg2 : signal is "NO"; + attribute async_reg of pclk_sel_reg2 : signal is "true"; + signal rate_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_done_reg1 : signal is "NO"; + attribute async_reg of rate_done_reg1 : signal is "true"; + signal rate_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_done_reg2 : signal is "NO"; + attribute async_reg of rate_done_reg2 : signal is "true"; + signal rate_gen3_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_gen3_reg1 : signal is "NO"; + attribute async_reg of rate_gen3_reg1 : signal is "true"; + signal rate_gen3_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_gen3_reg2 : signal is "NO"; + attribute async_reg of rate_gen3_reg2 : signal is "true"; + signal rate_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO"; + attribute async_reg of rate_idle_reg1 : signal is "true"; + signal rate_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO"; + attribute async_reg of rate_idle_reg2 : signal is "true"; + signal rate_rxsync_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_rxsync_reg1 : signal is "NO"; + attribute async_reg of rate_rxsync_reg1 : signal is "true"; + signal rate_rxsync_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_rxsync_reg2 : signal is "NO"; + attribute async_reg of rate_rxsync_reg2 : signal is "true"; + signal resetovrd_start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_start_reg1 : signal is "NO"; + attribute async_reg of resetovrd_start_reg1 : signal is "true"; + signal resetovrd_start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_start_reg2 : signal is "NO"; + attribute async_reg of resetovrd_start_reg2 : signal is "true"; + signal rst_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO"; + attribute async_reg of rst_idle_reg1 : signal is "true"; + signal rst_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO"; + attribute async_reg of rst_idle_reg2 : signal is "true"; + signal rxcdrlock_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rxcdrlock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO"; + attribute async_reg of rxcdrlock_reg1 : signal is "true"; + signal rxcdrlock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO"; + attribute async_reg of rxcdrlock_reg2 : signal is "true"; + signal rxeq_adapt_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1 : signal is "NO"; + attribute async_reg of rxeq_adapt_done_reg1 : signal is "true"; + signal rxeq_adapt_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2 : signal is "NO"; + attribute async_reg of rxeq_adapt_done_reg2 : signal is "true"; + signal rxresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO"; + attribute async_reg of rxresetdone_reg1 : signal is "true"; + signal rxresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO"; + attribute async_reg of rxresetdone_reg2 : signal is "true"; + signal rxstatus_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxstatus_reg1 : signal is "NO"; + attribute async_reg of rxstatus_reg1 : signal is "true"; + signal rxstatus_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxstatus_reg2 : signal is "NO"; + attribute async_reg of rxstatus_reg2 : signal is "true"; + signal rxvalid_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rxvalid_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxvalid_reg1 : signal is "NO"; + attribute async_reg of rxvalid_reg1 : signal is "true"; + signal rxvalid_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxvalid_reg2 : signal is "NO"; + attribute async_reg of rxvalid_reg2 : signal is "true"; + signal sel : STD_LOGIC; + signal txcompliance_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txcompliance_reg1 : signal is "NO"; + attribute async_reg of txcompliance_reg1 : signal is "true"; + signal txcompliance_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txcompliance_reg2 : signal is "NO"; + attribute async_reg of txcompliance_reg2 : signal is "true"; + signal txelecidle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txelecidle_reg1 : signal is "NO"; + attribute async_reg of txelecidle_reg1 : signal is "true"; + signal txelecidle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txelecidle_reg2 : signal is "NO"; + attribute async_reg of txelecidle_reg2 : signal is "true"; + signal txresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO"; + attribute async_reg of txresetdone_reg1 : signal is "true"; + signal txresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO"; + attribute async_reg of txresetdone_reg2 : signal is "true"; + signal \NLW_converge_cnt_reg[20]_i_1__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_converge_cnt_reg[20]_i_1__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \converge_cnt_reg[0]_i_3__1\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[12]_i_1__1\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[16]_i_1__1\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[20]_i_1__1\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[4]_i_1__1\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[8]_i_1__1\ : label is 11; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1__1\ : label is "soft_lutpair162"; + attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1__1\ : label is "soft_lutpair162"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of pclk_sel_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of pclk_sel_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of pclk_sel_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of pclk_sel_reg2_reg : label is std.standard.true; + attribute KEEP of pclk_sel_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of pclk_sel_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_done_reg1_reg : label is std.standard.true; + attribute KEEP of rate_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_done_reg2_reg : label is std.standard.true; + attribute KEEP of rate_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_done_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_gen3_reg1_reg : label is std.standard.true; + attribute KEEP of rate_gen3_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_gen3_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_gen3_reg2_reg : label is std.standard.true; + attribute KEEP of rate_gen3_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_gen3_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_rxsync_reg1_reg : label is std.standard.true; + attribute KEEP of rate_rxsync_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_rxsync_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_rxsync_reg2_reg : label is std.standard.true; + attribute KEEP of rate_rxsync_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_rxsync_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of resetovrd_start_reg1_reg : label is std.standard.true; + attribute KEEP of resetovrd_start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of resetovrd_start_reg2_reg : label is std.standard.true; + attribute KEEP of resetovrd_start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_adapt_done_reg1_reg : label is std.standard.true; + attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_adapt_done_reg2_reg : label is std.standard.true; + attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxstatus_reg1_reg : label is std.standard.true; + attribute KEEP of rxstatus_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxstatus_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxstatus_reg2_reg : label is std.standard.true; + attribute KEEP of rxstatus_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxstatus_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxvalid_reg1_reg : label is std.standard.true; + attribute KEEP of rxvalid_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxvalid_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxvalid_reg2_reg : label is std.standard.true; + attribute KEEP of rxvalid_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxvalid_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txcompliance_reg1_reg : label is std.standard.true; + attribute KEEP of txcompliance_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txcompliance_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txcompliance_reg2_reg : label is std.standard.true; + attribute KEEP of txcompliance_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txcompliance_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txelecidle_reg1_reg : label is std.standard.true; + attribute KEEP of txelecidle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txelecidle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txelecidle_reg2_reg : label is std.standard.true; + attribute KEEP of txelecidle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txelecidle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO"; +begin + \converge_cnt_reg[15]_0\ <= \^converge_cnt_reg[15]_0\; + converge_gen3_reg_0 <= \^converge_gen3_reg_0\; + txcompliance_reg2_reg_1 <= txcompliance_reg2; + txelecidle_reg2_reg_0 <= txelecidle_reg2; +\FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => txcompliance_reg2, + I1 => txelecidle_reg2, + O => user_active_lane_2 + ); +\converge_cnt[0]_i_1__4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => rate_gen3_reg2, + I1 => RST_CPLLRESET, + I2 => rst_idle_reg2, + I3 => rate_idle_reg2, + O => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt[0]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF5555555D" + ) + port map ( + I0 => converge_cnt_reg(21), + I1 => \converge_cnt[0]_i_4__1_n_0\, + I2 => converge_cnt_reg(12), + I3 => converge_cnt_reg(14), + I4 => converge_cnt_reg(20), + I5 => \converge_cnt[0]_i_5__1_n_0\, + O => sel + ); +\converge_cnt[0]_i_4__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => converge_cnt_reg(3), + I1 => converge_cnt_reg(4), + I2 => converge_cnt_reg(5), + I3 => converge_cnt_reg(7), + I4 => converge_cnt_reg(6), + O => \converge_cnt[0]_i_4__1_n_0\ + ); +\converge_cnt[0]_i_5__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0A0B0A0F0A0B0A0B" + ) + port map ( + I0 => \^converge_cnt_reg[15]_0\, + I1 => converge_cnt_reg(13), + I2 => converge_cnt_reg(20), + I3 => converge_cnt_reg(14), + I4 => converge_cnt_reg(12), + I5 => \converge_cnt[0]_i_7_n_0\, + O => \converge_cnt[0]_i_5__1_n_0\ + ); +\converge_cnt[0]_i_6__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => converge_cnt_reg(0), + O => \converge_cnt[0]_i_6__1_n_0\ + ); +\converge_cnt[0]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => converge_cnt_reg(9), + I1 => converge_cnt_reg(8), + I2 => converge_cnt_reg(11), + I3 => converge_cnt_reg(10), + O => \converge_cnt[0]_i_7_n_0\ + ); +\converge_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3__1_n_7\, + Q => converge_cnt_reg(0), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[0]_i_3__1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \converge_cnt_reg[0]_i_3__1_n_0\, + CO(2) => \converge_cnt_reg[0]_i_3__1_n_1\, + CO(1) => \converge_cnt_reg[0]_i_3__1_n_2\, + CO(0) => \converge_cnt_reg[0]_i_3__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \converge_cnt_reg[0]_i_3__1_n_4\, + O(2) => \converge_cnt_reg[0]_i_3__1_n_5\, + O(1) => \converge_cnt_reg[0]_i_3__1_n_6\, + O(0) => \converge_cnt_reg[0]_i_3__1_n_7\, + S(3 downto 1) => converge_cnt_reg(3 downto 1), + S(0) => \converge_cnt[0]_i_6__1_n_0\ + ); +\converge_cnt_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1__1_n_5\, + Q => converge_cnt_reg(10), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1__1_n_4\, + Q => converge_cnt_reg(11), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1__1_n_7\, + Q => converge_cnt_reg(12), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[12]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[8]_i_1__1_n_0\, + CO(3) => \converge_cnt_reg[12]_i_1__1_n_0\, + CO(2) => \converge_cnt_reg[12]_i_1__1_n_1\, + CO(1) => \converge_cnt_reg[12]_i_1__1_n_2\, + CO(0) => \converge_cnt_reg[12]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[12]_i_1__1_n_4\, + O(2) => \converge_cnt_reg[12]_i_1__1_n_5\, + O(1) => \converge_cnt_reg[12]_i_1__1_n_6\, + O(0) => \converge_cnt_reg[12]_i_1__1_n_7\, + S(3 downto 0) => converge_cnt_reg(15 downto 12) + ); +\converge_cnt_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1__1_n_6\, + Q => converge_cnt_reg(13), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1__1_n_5\, + Q => converge_cnt_reg(14), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1__1_n_4\, + Q => converge_cnt_reg(15), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1__1_n_7\, + Q => converge_cnt_reg(16), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[16]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[12]_i_1__1_n_0\, + CO(3) => \converge_cnt_reg[16]_i_1__1_n_0\, + CO(2) => \converge_cnt_reg[16]_i_1__1_n_1\, + CO(1) => \converge_cnt_reg[16]_i_1__1_n_2\, + CO(0) => \converge_cnt_reg[16]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[16]_i_1__1_n_4\, + O(2) => \converge_cnt_reg[16]_i_1__1_n_5\, + O(1) => \converge_cnt_reg[16]_i_1__1_n_6\, + O(0) => \converge_cnt_reg[16]_i_1__1_n_7\, + S(3 downto 0) => converge_cnt_reg(19 downto 16) + ); +\converge_cnt_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1__1_n_6\, + Q => converge_cnt_reg(17), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1__1_n_5\, + Q => converge_cnt_reg(18), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1__1_n_4\, + Q => converge_cnt_reg(19), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3__1_n_6\, + Q => converge_cnt_reg(1), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[20]_i_1__1_n_7\, + Q => converge_cnt_reg(20), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[20]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[16]_i_1__1_n_0\, + CO(3 downto 1) => \NLW_converge_cnt_reg[20]_i_1__1_CO_UNCONNECTED\(3 downto 1), + CO(0) => \converge_cnt_reg[20]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 2) => \NLW_converge_cnt_reg[20]_i_1__1_O_UNCONNECTED\(3 downto 2), + O(1) => \converge_cnt_reg[20]_i_1__1_n_6\, + O(0) => \converge_cnt_reg[20]_i_1__1_n_7\, + S(3 downto 2) => B"00", + S(1 downto 0) => converge_cnt_reg(21 downto 20) + ); +\converge_cnt_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[20]_i_1__1_n_6\, + Q => converge_cnt_reg(21), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3__1_n_5\, + Q => converge_cnt_reg(2), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3__1_n_4\, + Q => converge_cnt_reg(3), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1__1_n_7\, + Q => converge_cnt_reg(4), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[4]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[0]_i_3__1_n_0\, + CO(3) => \converge_cnt_reg[4]_i_1__1_n_0\, + CO(2) => \converge_cnt_reg[4]_i_1__1_n_1\, + CO(1) => \converge_cnt_reg[4]_i_1__1_n_2\, + CO(0) => \converge_cnt_reg[4]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[4]_i_1__1_n_4\, + O(2) => \converge_cnt_reg[4]_i_1__1_n_5\, + O(1) => \converge_cnt_reg[4]_i_1__1_n_6\, + O(0) => \converge_cnt_reg[4]_i_1__1_n_7\, + S(3 downto 0) => converge_cnt_reg(7 downto 4) + ); +\converge_cnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1__1_n_6\, + Q => converge_cnt_reg(5), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1__1_n_5\, + Q => converge_cnt_reg(6), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1__1_n_4\, + Q => converge_cnt_reg(7), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1__1_n_7\, + Q => converge_cnt_reg(8), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_cnt_reg[8]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[4]_i_1__1_n_0\, + CO(3) => \converge_cnt_reg[8]_i_1__1_n_0\, + CO(2) => \converge_cnt_reg[8]_i_1__1_n_1\, + CO(1) => \converge_cnt_reg[8]_i_1__1_n_2\, + CO(0) => \converge_cnt_reg[8]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[8]_i_1__1_n_4\, + O(2) => \converge_cnt_reg[8]_i_1__1_n_5\, + O(1) => \converge_cnt_reg[8]_i_1__1_n_6\, + O(0) => \converge_cnt_reg[8]_i_1__1_n_7\, + S(3 downto 0) => converge_cnt_reg(11 downto 8) + ); +\converge_cnt_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1__1_n_6\, + Q => converge_cnt_reg(9), + R => \converge_cnt[0]_i_1__4_n_0\ + ); +\converge_gen3_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C8" + ) + port map ( + I0 => rxeq_adapt_done_reg2, + I1 => rate_gen3_reg2, + I2 => \^converge_gen3_reg_0\, + O => \converge_gen3_i_1__1_n_0\ + ); +converge_gen3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \converge_gen3_i_1__1_n_0\, + Q => \^converge_gen3_reg_0\, + R => RST_CPLLRESET + ); +\gt_rx_phy_status_q_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFA8FF" + ) + port map ( + I0 => RST_PHYSTATUS(0), + I1 => rate_idle_reg2, + I2 => rate_rxsync_reg2, + I3 => rst_idle_reg2, + I4 => rate_done_reg2, + O => gt_rx_phy_status_wire_filter(0) + ); +\gt_rxvalid_q_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000000000000000" + ) + port map ( + I0 => gt_rx_elec_idle_wire_filter(0), + I1 => pipe_rx2_valid_gt, + I2 => \gt_rxvalid_q_i_4__1_n_0\, + I3 => gt_rxvalid_2, + I4 => rst_idle_reg2, + I5 => rate_idle_reg2, + O => gt_rxvalid_q_reg + ); +\gt_rxvalid_q_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => rxvalid_cnt_reg(0), + I1 => rxvalid_cnt_reg(1), + I2 => rxvalid_cnt_reg(2), + I3 => rxvalid_cnt_reg(3), + O => \gt_rxvalid_q_i_4__1_n_0\ + ); +\gtx_channel.gtxe2_channel_i_i_60\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFFFFFF" + ) + port map ( + I0 => converge_cnt_reg(15), + I1 => converge_cnt_reg(18), + I2 => converge_cnt_reg(19), + I3 => converge_cnt_reg(17), + I4 => converge_cnt_reg(16), + O => \^converge_cnt_reg[15]_0\ + ); +\gtx_channel.gtxe2_channel_i_i_61\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0001000000000000" + ) + port map ( + I0 => converge_cnt_reg(6), + I1 => converge_cnt_reg(7), + I2 => converge_cnt_reg(4), + I3 => converge_cnt_reg(5), + I4 => converge_cnt_reg(21), + I5 => converge_cnt_reg(13), + O => \converge_cnt_reg[6]_0\ + ); +\gtx_channel.gtxe2_channel_i_i_62\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000020000" + ) + port map ( + I0 => \gtx_channel.gtxe2_channel_i_i_64_n_0\, + I1 => converge_cnt_reg(1), + I2 => converge_cnt_reg(0), + I3 => converge_cnt_reg(2), + I4 => converge_cnt_reg(3), + I5 => \converge_cnt[0]_i_7_n_0\, + O => \converge_cnt_reg[1]_0\ + ); +\gtx_channel.gtxe2_channel_i_i_64\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => converge_cnt_reg(20), + I1 => converge_cnt_reg(14), + I2 => converge_cnt_reg(12), + O => \gtx_channel.gtxe2_channel_i_i_64_n_0\ + ); +\oobclk_div.oobclk_cnt[0]_i_1__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => oobclk_cnt(0), + O => \p_1_in__0\(0) + ); +\oobclk_div.oobclk_cnt[1]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => oobclk_cnt(0), + I1 => oobclk_cnt(1), + O => \p_1_in__0\(1) + ); +\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_oobclk_in, + CE => '1', + D => \p_1_in__0\(0), + Q => oobclk_cnt(0), + R => RST_CPLLRESET + ); +\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_oobclk_in, + CE => '1', + D => \p_1_in__0\(1), + Q => oobclk_cnt(1), + R => RST_CPLLRESET + ); +\oobclk_div.oobclk_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => oobclk_cnt(1), + I1 => pclk_sel_reg2, + I2 => oobclk_cnt(0), + O => \oobclk_div.oobclk_i_1__1_n_0\ + ); +\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_oobclk_in, + CE => '1', + D => \oobclk_div.oobclk_i_1__1_n_0\, + Q => USER_OOBCLK, + R => RST_CPLLRESET + ); +pclk_sel_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_pclk_sel_out(0), + Q => pclk_sel_reg1, + R => RST_CPLLRESET + ); +pclk_sel_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pclk_sel_reg1, + Q => pclk_sel_reg2, + R => RST_CPLLRESET + ); +phy_rdy_n_int_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000002" + ) + port map ( + I0 => reg_clock_locked, + I1 => rst_idle_reg2, + I2 => \out\, + I3 => phy_rdy_n_int_reg, + I4 => phy_rdy_n_int_reg_0, + O => reg_clock_locked_reg + ); +rate_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_DONE, + Q => rate_done_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_done_reg1, + Q => rate_done_reg2, + R => RST_RXUSRCLK_RESET + ); +rate_gen3_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_gen3_2, + Q => rate_gen3_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_gen3_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_gen3_reg1, + Q => rate_gen3_reg2, + R => RST_RXUSRCLK_RESET + ); +rate_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_IDLE, + Q => rate_idle_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_idle_reg1, + Q => rate_idle_reg2, + R => RST_RXUSRCLK_RESET + ); +rate_rxsync_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_RXSYNC, + Q => rate_rxsync_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_rxsync_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_rxsync_reg1, + Q => rate_rxsync_reg2, + R => RST_RXUSRCLK_RESET + ); +\resetdone_reg1[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => rxresetdone_reg2, + I1 => txresetdone_reg2, + O => RST_RESETDONE(0) + ); +resetovrd_start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RESETOVRD_START, + Q => resetovrd_start_reg1, + R => RST_CPLLRESET + ); +resetovrd_start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => resetovrd_start_reg1, + Q => resetovrd_start_reg2, + R => RST_CPLLRESET + ); +rst_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => RST_IDLE, + Q => rst_idle_reg1, + R => RST_RXUSRCLK_RESET + ); +rst_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rst_idle_reg1, + Q => rst_idle_reg2, + R => RST_RXUSRCLK_RESET + ); +\rxcdrlock_cnt[0]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D0505050" + ) + port map ( + I0 => rxcdrlock_cnt_reg(0), + I1 => rxcdrlock_cnt_reg(2), + I2 => rxcdrlock_reg2, + I3 => rxcdrlock_cnt_reg(1), + I4 => rxcdrlock_cnt_reg(3), + O => \p_0_in__0\(0) + ); +\rxcdrlock_cnt[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8FF00000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(3), + I1 => rxcdrlock_cnt_reg(2), + I2 => rxcdrlock_cnt_reg(0), + I3 => rxcdrlock_cnt_reg(1), + I4 => rxcdrlock_reg2, + O => \p_0_in__0\(1) + ); +\rxcdrlock_cnt[2]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F8780000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(0), + I1 => rxcdrlock_cnt_reg(1), + I2 => rxcdrlock_cnt_reg(2), + I3 => rxcdrlock_cnt_reg(3), + I4 => rxcdrlock_reg2, + O => \p_0_in__0\(2) + ); +\rxcdrlock_cnt[3]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF008000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(0), + I1 => rxcdrlock_cnt_reg(1), + I2 => rxcdrlock_cnt_reg(2), + I3 => rxcdrlock_reg2, + I4 => rxcdrlock_cnt_reg(3), + O => \p_0_in__0\(3) + ); +\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(0), + Q => rxcdrlock_cnt_reg(0), + R => RST_CPLLRESET + ); +\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(1), + Q => rxcdrlock_cnt_reg(1), + R => RST_CPLLRESET + ); +\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(2), + Q => rxcdrlock_cnt_reg(2), + R => RST_CPLLRESET + ); +\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(3), + Q => rxcdrlock_cnt_reg(3), + R => RST_CPLLRESET + ); +\rxcdrlock_reg1[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(2), + I1 => rxcdrlock_cnt_reg(3), + I2 => gt_rxcdrlock_2, + I3 => rxcdrlock_cnt_reg(1), + I4 => rxcdrlock_cnt_reg(0), + O => RST_RXCDRLOCK(0) + ); +rxcdrlock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rxcdrlock_2, + Q => rxcdrlock_reg1, + R => RST_CPLLRESET + ); +rxcdrlock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxcdrlock_reg1, + Q => rxcdrlock_reg2, + R => RST_CPLLRESET + ); +rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RXEQ_ADAPT_DONE, + Q => rxeq_adapt_done_reg1, + R => RST_CPLLRESET + ); +rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_adapt_done_reg1, + Q => rxeq_adapt_done_reg2, + R => RST_CPLLRESET + ); +rxresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RXRESETDONE, + Q => rxresetdone_reg1, + R => RST_CPLLRESET + ); +rxresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxresetdone_reg1, + Q => rxresetdone_reg2, + R => RST_CPLLRESET + ); +rxstatus_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rxstatus_reg1_reg_0(0), + Q => rxstatus_reg1, + R => RST_RXUSRCLK_RESET + ); +rxstatus_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rxstatus_reg1, + Q => rxstatus_reg2, + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt[0]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C404040404040404" + ) + port map ( + I0 => rxstatus_reg2, + I1 => rxvalid_reg2, + I2 => rxvalid_cnt_reg(0), + I3 => rxvalid_cnt_reg(1), + I4 => rxvalid_cnt_reg(2), + I5 => rxvalid_cnt_reg(3), + O => \p_0_in__0__0\(0) + ); +\rxvalid_cnt[1]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"808000F000F00000" + ) + port map ( + I0 => rxvalid_cnt_reg(3), + I1 => rxvalid_cnt_reg(2), + I2 => rxvalid_reg2, + I3 => rxstatus_reg2, + I4 => rxvalid_cnt_reg(1), + I5 => rxvalid_cnt_reg(0), + O => \p_0_in__0__0\(1) + ); +\rxvalid_cnt[2]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"80BF000000C00000" + ) + port map ( + I0 => rxvalid_cnt_reg(3), + I1 => rxvalid_cnt_reg(0), + I2 => rxvalid_cnt_reg(1), + I3 => rxstatus_reg2, + I4 => rxvalid_reg2, + I5 => rxvalid_cnt_reg(2), + O => \p_0_in__0__0\(2) + ); +\rxvalid_cnt[3]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8C08080808080808" + ) + port map ( + I0 => rxvalid_cnt_reg(3), + I1 => rxvalid_reg2, + I2 => rxstatus_reg2, + I3 => rxvalid_cnt_reg(2), + I4 => rxvalid_cnt_reg(1), + I5 => rxvalid_cnt_reg(0), + O => \p_0_in__0__0\(3) + ); +\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(0), + Q => rxvalid_cnt_reg(0), + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(1), + Q => rxvalid_cnt_reg(1), + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(2), + Q => rxvalid_cnt_reg(2), + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(3), + Q => rxvalid_cnt_reg(3), + R => RST_RXUSRCLK_RESET + ); +rxvalid_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => gt_rxvalid_2, + Q => rxvalid_reg1, + R => RST_RXUSRCLK_RESET + ); +rxvalid_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rxvalid_reg1, + Q => rxvalid_reg2, + R => RST_RXUSRCLK_RESET + ); +txcompliance_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_TXCOMPLIANCE(0), + Q => txcompliance_reg1, + R => RST_CPLLRESET + ); +txcompliance_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcompliance_reg1, + Q => txcompliance_reg2, + R => RST_CPLLRESET + ); +txelecidle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_TXELECIDLE(0), + Q => txelecidle_reg1, + R => RST_CPLLRESET + ); +txelecidle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txelecidle_reg1, + Q => txelecidle_reg2, + R => RST_CPLLRESET + ); +txphaligndone_reg1_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0707070707FFFFFF" + ) + port map ( + I0 => txcompliance_reg2, + I1 => txelecidle_reg2, + I2 => txphaligndone_reg1_reg, + I3 => txphaligndone_reg1_reg_0, + I4 => txphaligndone_reg1_reg_1, + I5 => txphaligndone_reg1_reg_2, + O => txcompliance_reg2_reg_0 + ); +txphinitdone_reg1_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0707070707FFFFFF" + ) + port map ( + I0 => txcompliance_reg2, + I1 => txelecidle_reg2, + I2 => txphinitdone_reg1_reg, + I3 => txphaligndone_reg1_reg_0, + I4 => txphaligndone_reg1_reg_1, + I5 => txphinitdone_reg1_reg_0, + O => txcompliance_reg2_reg_2 + ); +txresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_TXRESETDONE, + Q => txresetdone_reg1, + R => RST_CPLLRESET + ); +txresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txresetdone_reg1, + Q => txresetdone_reg2, + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_user_54 is + port ( + gt_rxvalid_q_reg : out STD_LOGIC; + \out\ : out STD_LOGIC; + txelecidle_reg2_reg_0 : out STD_LOGIC; + txcompliance_reg2_reg_0 : out STD_LOGIC; + USER_OOBCLK : out STD_LOGIC; + RST_RXCDRLOCK : out STD_LOGIC_VECTOR ( 0 to 0 ); + gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 ); + user_rx_converge : out STD_LOGIC_VECTOR ( 0 to 0 ); + RST_RESETDONE : out STD_LOGIC_VECTOR ( 0 to 0 ); + user_active_lane_3 : out STD_LOGIC; + gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rx3_valid_gt : in STD_LOGIC; + gt_rxvalid_3 : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_sel_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_pclk_in : in STD_LOGIC; + pipe_oobclk_in : in STD_LOGIC; + USER_TXRESETDONE : in STD_LOGIC; + USER_RXRESETDONE : in STD_LOGIC; + PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 ); + gt_rxcdrlock_3 : in STD_LOGIC; + RST_RXUSRCLK_RESET : in STD_LOGIC; + pipe_rxusrclk_in : in STD_LOGIC; + rxstatus_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + RST_IDLE : in STD_LOGIC; + USER_RATE_IDLE : in STD_LOGIC; + USER_RATE_RXSYNC : in STD_LOGIC; + USER_RATE_DONE : in STD_LOGIC; + rate_gen3_3 : in STD_LOGIC; + USER_RXEQ_ADAPT_DONE : in STD_LOGIC; + USER_RESETOVRD_START : in STD_LOGIC; + RST_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_user_54 : entity is "pcie_7x_0_pipe_user"; +end pcie_7x_0_pcie_7x_0_pipe_user_54; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_user_54 is + signal \converge_cnt[0]_i_1__6_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_4__2_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_5__2_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_6__2_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_7__0_n_0\ : STD_LOGIC; + signal \converge_cnt[0]_i_8_n_0\ : STD_LOGIC; + signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal \converge_cnt_reg[0]_i_3__2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__2_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__2_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__2_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[0]_i_3__2_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__2_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__2_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__2_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_1__2_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__2_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__2_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__2_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_1__2_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_1__2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_1__2_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_1__2_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__2_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__2_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__2_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_1__2_n_7\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__2_n_4\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__2_n_5\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__2_n_6\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_1__2_n_7\ : STD_LOGIC; + signal \converge_gen3_i_1__2_n_0\ : STD_LOGIC; + signal converge_gen3_reg_n_0 : STD_LOGIC; + signal \gt_rxvalid_q_i_4__2_n_0\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_i_65_n_0\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_i_66_n_0\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_i_67_n_0\ : STD_LOGIC; + signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \oobclk_div.oobclk_i_1__2_n_0\ : STD_LOGIC; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pclk_sel_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of pclk_sel_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of pclk_sel_reg1 : signal is "true"; + signal pclk_sel_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of pclk_sel_reg2 : signal is "NO"; + attribute async_reg of pclk_sel_reg2 : signal is "true"; + signal rate_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_done_reg1 : signal is "NO"; + attribute async_reg of rate_done_reg1 : signal is "true"; + signal rate_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_done_reg2 : signal is "NO"; + attribute async_reg of rate_done_reg2 : signal is "true"; + signal rate_gen3_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_gen3_reg1 : signal is "NO"; + attribute async_reg of rate_gen3_reg1 : signal is "true"; + signal rate_gen3_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_gen3_reg2 : signal is "NO"; + attribute async_reg of rate_gen3_reg2 : signal is "true"; + signal rate_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO"; + attribute async_reg of rate_idle_reg1 : signal is "true"; + signal rate_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO"; + attribute async_reg of rate_idle_reg2 : signal is "true"; + signal rate_rxsync_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_rxsync_reg1 : signal is "NO"; + attribute async_reg of rate_rxsync_reg1 : signal is "true"; + signal rate_rxsync_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rate_rxsync_reg2 : signal is "NO"; + attribute async_reg of rate_rxsync_reg2 : signal is "true"; + signal resetovrd_start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_start_reg1 : signal is "NO"; + attribute async_reg of resetovrd_start_reg1 : signal is "true"; + signal resetovrd_start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of resetovrd_start_reg2 : signal is "NO"; + attribute async_reg of resetovrd_start_reg2 : signal is "true"; + signal rst_idle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO"; + attribute async_reg of rst_idle_reg1 : signal is "true"; + signal rst_idle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO"; + attribute async_reg of rst_idle_reg2 : signal is "true"; + signal rxcdrlock_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rxcdrlock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO"; + attribute async_reg of rxcdrlock_reg1 : signal is "true"; + signal rxcdrlock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO"; + attribute async_reg of rxcdrlock_reg2 : signal is "true"; + signal rxeq_adapt_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1 : signal is "NO"; + attribute async_reg of rxeq_adapt_done_reg1 : signal is "true"; + signal rxeq_adapt_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2 : signal is "NO"; + attribute async_reg of rxeq_adapt_done_reg2 : signal is "true"; + signal rxresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO"; + attribute async_reg of rxresetdone_reg1 : signal is "true"; + signal rxresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO"; + attribute async_reg of rxresetdone_reg2 : signal is "true"; + signal rxstatus_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxstatus_reg1 : signal is "NO"; + attribute async_reg of rxstatus_reg1 : signal is "true"; + signal rxstatus_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxstatus_reg2 : signal is "NO"; + attribute async_reg of rxstatus_reg2 : signal is "true"; + signal rxvalid_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rxvalid_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxvalid_reg1 : signal is "NO"; + attribute async_reg of rxvalid_reg1 : signal is "true"; + signal rxvalid_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxvalid_reg2 : signal is "NO"; + attribute async_reg of rxvalid_reg2 : signal is "true"; + signal sel : STD_LOGIC; + signal txcompliance_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txcompliance_reg1 : signal is "NO"; + attribute async_reg of txcompliance_reg1 : signal is "true"; + signal txcompliance_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txcompliance_reg2 : signal is "NO"; + attribute async_reg of txcompliance_reg2 : signal is "true"; + signal txelecidle_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txelecidle_reg1 : signal is "NO"; + attribute async_reg of txelecidle_reg1 : signal is "true"; + signal txelecidle_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txelecidle_reg2 : signal is "NO"; + attribute async_reg of txelecidle_reg2 : signal is "true"; + signal txresetdone_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO"; + attribute async_reg of txresetdone_reg1 : signal is "true"; + signal txresetdone_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO"; + attribute async_reg of txresetdone_reg2 : signal is "true"; + signal \NLW_converge_cnt_reg[20]_i_1__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_converge_cnt_reg[20]_i_1__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \converge_cnt_reg[0]_i_3__2\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[12]_i_1__2\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[16]_i_1__2\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[20]_i_1__2\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[4]_i_1__2\ : label is 11; + attribute ADDER_THRESHOLD of \converge_cnt_reg[8]_i_1__2\ : label is 11; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1__2\ : label is "soft_lutpair203"; + attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1__2\ : label is "soft_lutpair203"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of pclk_sel_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of pclk_sel_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of pclk_sel_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of pclk_sel_reg2_reg : label is std.standard.true; + attribute KEEP of pclk_sel_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of pclk_sel_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_done_reg1_reg : label is std.standard.true; + attribute KEEP of rate_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_done_reg2_reg : label is std.standard.true; + attribute KEEP of rate_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_done_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_gen3_reg1_reg : label is std.standard.true; + attribute KEEP of rate_gen3_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_gen3_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_gen3_reg2_reg : label is std.standard.true; + attribute KEEP of rate_gen3_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_gen3_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rate_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_rxsync_reg1_reg : label is std.standard.true; + attribute KEEP of rate_rxsync_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_rxsync_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rate_rxsync_reg2_reg : label is std.standard.true; + attribute KEEP of rate_rxsync_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rate_rxsync_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of resetovrd_start_reg1_reg : label is std.standard.true; + attribute KEEP of resetovrd_start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of resetovrd_start_reg2_reg : label is std.standard.true; + attribute KEEP of resetovrd_start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of resetovrd_start_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true; + attribute KEEP of rst_idle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true; + attribute KEEP of rxcdrlock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_adapt_done_reg1_reg : label is std.standard.true; + attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_adapt_done_reg2_reg : label is std.standard.true; + attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of rxresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxstatus_reg1_reg : label is std.standard.true; + attribute KEEP of rxstatus_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxstatus_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxstatus_reg2_reg : label is std.standard.true; + attribute KEEP of rxstatus_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxstatus_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxvalid_reg1_reg : label is std.standard.true; + attribute KEEP of rxvalid_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxvalid_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxvalid_reg2_reg : label is std.standard.true; + attribute KEEP of rxvalid_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxvalid_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txcompliance_reg1_reg : label is std.standard.true; + attribute KEEP of txcompliance_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txcompliance_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txcompliance_reg2_reg : label is std.standard.true; + attribute KEEP of txcompliance_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txcompliance_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txelecidle_reg1_reg : label is std.standard.true; + attribute KEEP of txelecidle_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txelecidle_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txelecidle_reg2_reg : label is std.standard.true; + attribute KEEP of txelecidle_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txelecidle_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true; + attribute KEEP of txresetdone_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO"; +begin + \out\ <= rst_idle_reg2; + txcompliance_reg2_reg_0 <= txcompliance_reg2; + txelecidle_reg2_reg_0 <= txelecidle_reg2; +\FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => txcompliance_reg2, + I1 => txelecidle_reg2, + O => user_active_lane_3 + ); +\converge_cnt[0]_i_1__6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => rate_gen3_reg2, + I1 => RST_CPLLRESET, + I2 => rst_idle_reg2, + I3 => rate_idle_reg2, + O => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt[0]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF5555555D" + ) + port map ( + I0 => converge_cnt_reg(21), + I1 => \converge_cnt[0]_i_4__2_n_0\, + I2 => converge_cnt_reg(12), + I3 => converge_cnt_reg(14), + I4 => converge_cnt_reg(20), + I5 => \converge_cnt[0]_i_5__2_n_0\, + O => sel + ); +\converge_cnt[0]_i_4__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => converge_cnt_reg(3), + I1 => converge_cnt_reg(4), + I2 => converge_cnt_reg(5), + I3 => converge_cnt_reg(7), + I4 => converge_cnt_reg(6), + O => \converge_cnt[0]_i_4__2_n_0\ + ); +\converge_cnt[0]_i_5__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0A0B0A0F0A0B0A0B" + ) + port map ( + I0 => \converge_cnt[0]_i_7__0_n_0\, + I1 => converge_cnt_reg(13), + I2 => converge_cnt_reg(20), + I3 => converge_cnt_reg(14), + I4 => converge_cnt_reg(12), + I5 => \converge_cnt[0]_i_8_n_0\, + O => \converge_cnt[0]_i_5__2_n_0\ + ); +\converge_cnt[0]_i_6__2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => converge_cnt_reg(0), + O => \converge_cnt[0]_i_6__2_n_0\ + ); +\converge_cnt[0]_i_7__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFFFFFF" + ) + port map ( + I0 => converge_cnt_reg(15), + I1 => converge_cnt_reg(18), + I2 => converge_cnt_reg(19), + I3 => converge_cnt_reg(17), + I4 => converge_cnt_reg(16), + O => \converge_cnt[0]_i_7__0_n_0\ + ); +\converge_cnt[0]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => converge_cnt_reg(9), + I1 => converge_cnt_reg(8), + I2 => converge_cnt_reg(11), + I3 => converge_cnt_reg(10), + O => \converge_cnt[0]_i_8_n_0\ + ); +\converge_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3__2_n_7\, + Q => converge_cnt_reg(0), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[0]_i_3__2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \converge_cnt_reg[0]_i_3__2_n_0\, + CO(2) => \converge_cnt_reg[0]_i_3__2_n_1\, + CO(1) => \converge_cnt_reg[0]_i_3__2_n_2\, + CO(0) => \converge_cnt_reg[0]_i_3__2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \converge_cnt_reg[0]_i_3__2_n_4\, + O(2) => \converge_cnt_reg[0]_i_3__2_n_5\, + O(1) => \converge_cnt_reg[0]_i_3__2_n_6\, + O(0) => \converge_cnt_reg[0]_i_3__2_n_7\, + S(3 downto 1) => converge_cnt_reg(3 downto 1), + S(0) => \converge_cnt[0]_i_6__2_n_0\ + ); +\converge_cnt_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1__2_n_5\, + Q => converge_cnt_reg(10), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1__2_n_4\, + Q => converge_cnt_reg(11), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1__2_n_7\, + Q => converge_cnt_reg(12), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[12]_i_1__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[8]_i_1__2_n_0\, + CO(3) => \converge_cnt_reg[12]_i_1__2_n_0\, + CO(2) => \converge_cnt_reg[12]_i_1__2_n_1\, + CO(1) => \converge_cnt_reg[12]_i_1__2_n_2\, + CO(0) => \converge_cnt_reg[12]_i_1__2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[12]_i_1__2_n_4\, + O(2) => \converge_cnt_reg[12]_i_1__2_n_5\, + O(1) => \converge_cnt_reg[12]_i_1__2_n_6\, + O(0) => \converge_cnt_reg[12]_i_1__2_n_7\, + S(3 downto 0) => converge_cnt_reg(15 downto 12) + ); +\converge_cnt_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1__2_n_6\, + Q => converge_cnt_reg(13), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1__2_n_5\, + Q => converge_cnt_reg(14), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[12]_i_1__2_n_4\, + Q => converge_cnt_reg(15), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1__2_n_7\, + Q => converge_cnt_reg(16), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[16]_i_1__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[12]_i_1__2_n_0\, + CO(3) => \converge_cnt_reg[16]_i_1__2_n_0\, + CO(2) => \converge_cnt_reg[16]_i_1__2_n_1\, + CO(1) => \converge_cnt_reg[16]_i_1__2_n_2\, + CO(0) => \converge_cnt_reg[16]_i_1__2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[16]_i_1__2_n_4\, + O(2) => \converge_cnt_reg[16]_i_1__2_n_5\, + O(1) => \converge_cnt_reg[16]_i_1__2_n_6\, + O(0) => \converge_cnt_reg[16]_i_1__2_n_7\, + S(3 downto 0) => converge_cnt_reg(19 downto 16) + ); +\converge_cnt_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1__2_n_6\, + Q => converge_cnt_reg(17), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1__2_n_5\, + Q => converge_cnt_reg(18), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[16]_i_1__2_n_4\, + Q => converge_cnt_reg(19), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3__2_n_6\, + Q => converge_cnt_reg(1), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[20]_i_1__2_n_7\, + Q => converge_cnt_reg(20), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[20]_i_1__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[16]_i_1__2_n_0\, + CO(3 downto 1) => \NLW_converge_cnt_reg[20]_i_1__2_CO_UNCONNECTED\(3 downto 1), + CO(0) => \converge_cnt_reg[20]_i_1__2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 2) => \NLW_converge_cnt_reg[20]_i_1__2_O_UNCONNECTED\(3 downto 2), + O(1) => \converge_cnt_reg[20]_i_1__2_n_6\, + O(0) => \converge_cnt_reg[20]_i_1__2_n_7\, + S(3 downto 2) => B"00", + S(1 downto 0) => converge_cnt_reg(21 downto 20) + ); +\converge_cnt_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[20]_i_1__2_n_6\, + Q => converge_cnt_reg(21), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3__2_n_5\, + Q => converge_cnt_reg(2), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[0]_i_3__2_n_4\, + Q => converge_cnt_reg(3), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1__2_n_7\, + Q => converge_cnt_reg(4), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[4]_i_1__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[0]_i_3__2_n_0\, + CO(3) => \converge_cnt_reg[4]_i_1__2_n_0\, + CO(2) => \converge_cnt_reg[4]_i_1__2_n_1\, + CO(1) => \converge_cnt_reg[4]_i_1__2_n_2\, + CO(0) => \converge_cnt_reg[4]_i_1__2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[4]_i_1__2_n_4\, + O(2) => \converge_cnt_reg[4]_i_1__2_n_5\, + O(1) => \converge_cnt_reg[4]_i_1__2_n_6\, + O(0) => \converge_cnt_reg[4]_i_1__2_n_7\, + S(3 downto 0) => converge_cnt_reg(7 downto 4) + ); +\converge_cnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1__2_n_6\, + Q => converge_cnt_reg(5), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1__2_n_5\, + Q => converge_cnt_reg(6), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[4]_i_1__2_n_4\, + Q => converge_cnt_reg(7), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1__2_n_7\, + Q => converge_cnt_reg(8), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_cnt_reg[8]_i_1__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[4]_i_1__2_n_0\, + CO(3) => \converge_cnt_reg[8]_i_1__2_n_0\, + CO(2) => \converge_cnt_reg[8]_i_1__2_n_1\, + CO(1) => \converge_cnt_reg[8]_i_1__2_n_2\, + CO(0) => \converge_cnt_reg[8]_i_1__2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \converge_cnt_reg[8]_i_1__2_n_4\, + O(2) => \converge_cnt_reg[8]_i_1__2_n_5\, + O(1) => \converge_cnt_reg[8]_i_1__2_n_6\, + O(0) => \converge_cnt_reg[8]_i_1__2_n_7\, + S(3 downto 0) => converge_cnt_reg(11 downto 8) + ); +\converge_cnt_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => sel, + D => \converge_cnt_reg[8]_i_1__2_n_6\, + Q => converge_cnt_reg(9), + R => \converge_cnt[0]_i_1__6_n_0\ + ); +\converge_gen3_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C8" + ) + port map ( + I0 => rxeq_adapt_done_reg2, + I1 => rate_gen3_reg2, + I2 => converge_gen3_reg_n_0, + O => \converge_gen3_i_1__2_n_0\ + ); +converge_gen3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \converge_gen3_i_1__2_n_0\, + Q => converge_gen3_reg_n_0, + R => RST_CPLLRESET + ); +\gt_rx_phy_status_q_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFA8FF" + ) + port map ( + I0 => RST_PHYSTATUS(0), + I1 => rate_idle_reg2, + I2 => rate_rxsync_reg2, + I3 => rst_idle_reg2, + I4 => rate_done_reg2, + O => gt_rx_phy_status_wire_filter(0) + ); +\gt_rxvalid_q_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000000000000000" + ) + port map ( + I0 => gt_rx_elec_idle_wire_filter(0), + I1 => pipe_rx3_valid_gt, + I2 => \gt_rxvalid_q_i_4__2_n_0\, + I3 => gt_rxvalid_3, + I4 => rst_idle_reg2, + I5 => rate_idle_reg2, + O => gt_rxvalid_q_reg + ); +\gt_rxvalid_q_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => rxvalid_cnt_reg(0), + I1 => rxvalid_cnt_reg(1), + I2 => rxvalid_cnt_reg(2), + I3 => rxvalid_cnt_reg(3), + O => \gt_rxvalid_q_i_4__2_n_0\ + ); +\gtx_channel.gtxe2_channel_i_i_63\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00000800" + ) + port map ( + I0 => \gtx_channel.gtxe2_channel_i_i_65_n_0\, + I1 => \gtx_channel.gtxe2_channel_i_i_66_n_0\, + I2 => \converge_cnt[0]_i_8_n_0\, + I3 => \gtx_channel.gtxe2_channel_i_i_67_n_0\, + I4 => \converge_cnt[0]_i_7__0_n_0\, + I5 => converge_gen3_reg_n_0, + O => user_rx_converge(0) + ); +\gtx_channel.gtxe2_channel_i_i_65\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => converge_cnt_reg(20), + I1 => converge_cnt_reg(14), + I2 => converge_cnt_reg(12), + O => \gtx_channel.gtxe2_channel_i_i_65_n_0\ + ); +\gtx_channel.gtxe2_channel_i_i_66\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0100" + ) + port map ( + I0 => converge_cnt_reg(1), + I1 => converge_cnt_reg(0), + I2 => converge_cnt_reg(2), + I3 => converge_cnt_reg(3), + O => \gtx_channel.gtxe2_channel_i_i_66_n_0\ + ); +\gtx_channel.gtxe2_channel_i_i_67\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0001000000000000" + ) + port map ( + I0 => converge_cnt_reg(6), + I1 => converge_cnt_reg(7), + I2 => converge_cnt_reg(4), + I3 => converge_cnt_reg(5), + I4 => converge_cnt_reg(21), + I5 => converge_cnt_reg(13), + O => \gtx_channel.gtxe2_channel_i_i_67_n_0\ + ); +\oobclk_div.oobclk_cnt[0]_i_1__2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => oobclk_cnt(0), + O => \p_1_in__0\(0) + ); +\oobclk_div.oobclk_cnt[1]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => oobclk_cnt(0), + I1 => oobclk_cnt(1), + O => \p_1_in__0\(1) + ); +\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_oobclk_in, + CE => '1', + D => \p_1_in__0\(0), + Q => oobclk_cnt(0), + R => RST_CPLLRESET + ); +\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_oobclk_in, + CE => '1', + D => \p_1_in__0\(1), + Q => oobclk_cnt(1), + R => RST_CPLLRESET + ); +\oobclk_div.oobclk_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => oobclk_cnt(1), + I1 => pclk_sel_reg2, + I2 => oobclk_cnt(0), + O => \oobclk_div.oobclk_i_1__2_n_0\ + ); +\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_oobclk_in, + CE => '1', + D => \oobclk_div.oobclk_i_1__2_n_0\, + Q => USER_OOBCLK, + R => RST_CPLLRESET + ); +pclk_sel_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_pclk_sel_out(0), + Q => pclk_sel_reg1, + R => RST_CPLLRESET + ); +pclk_sel_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pclk_sel_reg1, + Q => pclk_sel_reg2, + R => RST_CPLLRESET + ); +rate_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_DONE, + Q => rate_done_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_done_reg1, + Q => rate_done_reg2, + R => RST_RXUSRCLK_RESET + ); +rate_gen3_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_gen3_3, + Q => rate_gen3_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_gen3_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_gen3_reg1, + Q => rate_gen3_reg2, + R => RST_RXUSRCLK_RESET + ); +rate_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_IDLE, + Q => rate_idle_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_idle_reg1, + Q => rate_idle_reg2, + R => RST_RXUSRCLK_RESET + ); +rate_rxsync_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => USER_RATE_RXSYNC, + Q => rate_rxsync_reg1, + R => RST_RXUSRCLK_RESET + ); +rate_rxsync_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rate_rxsync_reg1, + Q => rate_rxsync_reg2, + R => RST_RXUSRCLK_RESET + ); +\resetdone_reg1[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => rxresetdone_reg2, + I1 => txresetdone_reg2, + O => RST_RESETDONE(0) + ); +resetovrd_start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RESETOVRD_START, + Q => resetovrd_start_reg1, + R => RST_CPLLRESET + ); +resetovrd_start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => resetovrd_start_reg1, + Q => resetovrd_start_reg2, + R => RST_CPLLRESET + ); +rst_idle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => RST_IDLE, + Q => rst_idle_reg1, + R => RST_RXUSRCLK_RESET + ); +rst_idle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rst_idle_reg1, + Q => rst_idle_reg2, + R => RST_RXUSRCLK_RESET + ); +\rxcdrlock_cnt[0]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D0505050" + ) + port map ( + I0 => rxcdrlock_cnt_reg(0), + I1 => rxcdrlock_cnt_reg(2), + I2 => rxcdrlock_reg2, + I3 => rxcdrlock_cnt_reg(1), + I4 => rxcdrlock_cnt_reg(3), + O => \p_0_in__0\(0) + ); +\rxcdrlock_cnt[1]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8FF00000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(3), + I1 => rxcdrlock_cnt_reg(2), + I2 => rxcdrlock_cnt_reg(0), + I3 => rxcdrlock_cnt_reg(1), + I4 => rxcdrlock_reg2, + O => \p_0_in__0\(1) + ); +\rxcdrlock_cnt[2]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F8780000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(0), + I1 => rxcdrlock_cnt_reg(1), + I2 => rxcdrlock_cnt_reg(2), + I3 => rxcdrlock_cnt_reg(3), + I4 => rxcdrlock_reg2, + O => \p_0_in__0\(2) + ); +\rxcdrlock_cnt[3]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF008000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(0), + I1 => rxcdrlock_cnt_reg(1), + I2 => rxcdrlock_cnt_reg(2), + I3 => rxcdrlock_reg2, + I4 => rxcdrlock_cnt_reg(3), + O => \p_0_in__0\(3) + ); +\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(0), + Q => rxcdrlock_cnt_reg(0), + R => RST_CPLLRESET + ); +\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(1), + Q => rxcdrlock_cnt_reg(1), + R => RST_CPLLRESET + ); +\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(2), + Q => rxcdrlock_cnt_reg(2), + R => RST_CPLLRESET + ); +\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \p_0_in__0\(3), + Q => rxcdrlock_cnt_reg(3), + R => RST_CPLLRESET + ); +\rxcdrlock_reg1[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => rxcdrlock_cnt_reg(2), + I1 => rxcdrlock_cnt_reg(3), + I2 => gt_rxcdrlock_3, + I3 => rxcdrlock_cnt_reg(1), + I4 => rxcdrlock_cnt_reg(0), + O => RST_RXCDRLOCK(0) + ); +rxcdrlock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gt_rxcdrlock_3, + Q => rxcdrlock_reg1, + R => RST_CPLLRESET + ); +rxcdrlock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxcdrlock_reg1, + Q => rxcdrlock_reg2, + R => RST_CPLLRESET + ); +rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RXEQ_ADAPT_DONE, + Q => rxeq_adapt_done_reg1, + R => RST_CPLLRESET + ); +rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_adapt_done_reg1, + Q => rxeq_adapt_done_reg2, + R => RST_CPLLRESET + ); +rxresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RXRESETDONE, + Q => rxresetdone_reg1, + R => RST_CPLLRESET + ); +rxresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxresetdone_reg1, + Q => rxresetdone_reg2, + R => RST_CPLLRESET + ); +rxstatus_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rxstatus_reg1_reg_0(0), + Q => rxstatus_reg1, + R => RST_RXUSRCLK_RESET + ); +rxstatus_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rxstatus_reg1, + Q => rxstatus_reg2, + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt[0]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C404040404040404" + ) + port map ( + I0 => rxstatus_reg2, + I1 => rxvalid_reg2, + I2 => rxvalid_cnt_reg(0), + I3 => rxvalid_cnt_reg(1), + I4 => rxvalid_cnt_reg(2), + I5 => rxvalid_cnt_reg(3), + O => \p_0_in__0__0\(0) + ); +\rxvalid_cnt[1]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"808000F000F00000" + ) + port map ( + I0 => rxvalid_cnt_reg(3), + I1 => rxvalid_cnt_reg(2), + I2 => rxvalid_reg2, + I3 => rxstatus_reg2, + I4 => rxvalid_cnt_reg(1), + I5 => rxvalid_cnt_reg(0), + O => \p_0_in__0__0\(1) + ); +\rxvalid_cnt[2]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"80BF000000C00000" + ) + port map ( + I0 => rxvalid_cnt_reg(3), + I1 => rxvalid_cnt_reg(0), + I2 => rxvalid_cnt_reg(1), + I3 => rxstatus_reg2, + I4 => rxvalid_reg2, + I5 => rxvalid_cnt_reg(2), + O => \p_0_in__0__0\(2) + ); +\rxvalid_cnt[3]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8C08080808080808" + ) + port map ( + I0 => rxvalid_cnt_reg(3), + I1 => rxvalid_reg2, + I2 => rxstatus_reg2, + I3 => rxvalid_cnt_reg(2), + I4 => rxvalid_cnt_reg(1), + I5 => rxvalid_cnt_reg(0), + O => \p_0_in__0__0\(3) + ); +\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(0), + Q => rxvalid_cnt_reg(0), + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(1), + Q => rxvalid_cnt_reg(1), + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(2), + Q => rxvalid_cnt_reg(2), + R => RST_RXUSRCLK_RESET + ); +\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => \p_0_in__0__0\(3), + Q => rxvalid_cnt_reg(3), + R => RST_RXUSRCLK_RESET + ); +rxvalid_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => gt_rxvalid_3, + Q => rxvalid_reg1, + R => RST_RXUSRCLK_RESET + ); +rxvalid_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_rxusrclk_in, + CE => '1', + D => rxvalid_reg1, + Q => rxvalid_reg2, + R => RST_RXUSRCLK_RESET + ); +txcompliance_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_TXCOMPLIANCE(0), + Q => txcompliance_reg1, + R => RST_CPLLRESET + ); +txcompliance_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcompliance_reg1, + Q => txcompliance_reg2, + R => RST_CPLLRESET + ); +txelecidle_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => PIPE_TXELECIDLE(0), + Q => txelecidle_reg1, + R => RST_CPLLRESET + ); +txelecidle_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txelecidle_reg1, + Q => txelecidle_reg2, + R => RST_CPLLRESET + ); +txresetdone_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_TXRESETDONE, + Q => txresetdone_reg1, + R => RST_CPLLRESET + ); +txresetdone_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txresetdone_reg1, + Q => txresetdone_reg2, + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_qpll_drp is + port ( + QPLL_DRP_DONE : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \di_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + qpll_drp_en : out STD_LOGIC; + qpll_drp_we : out STD_LOGIC; + RST_DCLK_RESET : in STD_LOGIC; + QRST_DRP_START : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + qpll_drp_rdy : in STD_LOGIC; + QPLL_QPLLLOCK : in STD_LOGIC; + QPLL_DRP_GEN3 : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_qpll_drp; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_qpll_drp is + signal \addr[0]_i_1_n_0\ : STD_LOGIC; + signal \addr[1]_i_1_n_0\ : STD_LOGIC; + signal \addr[2]_i_1_n_0\ : STD_LOGIC; + signal \addr[5]_i_1_n_0\ : STD_LOGIC; + signal \addr[7]_i_1_n_0\ : STD_LOGIC; + signal \crscode_reg_n_0_[0]\ : STD_LOGIC; + signal \crscode_reg_n_0_[1]\ : STD_LOGIC; + signal \crscode_reg_n_0_[2]\ : STD_LOGIC; + signal \crscode_reg_n_0_[3]\ : STD_LOGIC; + signal \crscode_reg_n_0_[4]\ : STD_LOGIC; + signal \crscode_reg_n_0_[5]\ : STD_LOGIC; + signal di : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \di[11]_i_2_n_0\ : STD_LOGIC; + signal \di[12]_i_2_n_0\ : STD_LOGIC; + signal \di[13]_i_2_n_0\ : STD_LOGIC; + signal \di[14]_i_2_n_0\ : STD_LOGIC; + signal \di[15]_i_2_n_0\ : STD_LOGIC; + signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of do_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of do_reg1 : signal is "true"; + signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute SHIFT_EXTRACT of do_reg2 : signal is "NO"; + attribute async_reg of do_reg2 : signal is "true"; + signal done : STD_LOGIC; + signal \fsm[0]_i_2__1_n_0\ : STD_LOGIC; + signal \fsm[1]_i_2__0_n_0\ : STD_LOGIC; + signal \fsm_inferred__1/i___0_n_0\ : STD_LOGIC; + signal \fsm_inferred__1/i___1_n_0\ : STD_LOGIC; + signal \fsm_inferred__1/i__n_0\ : STD_LOGIC; + signal \fsm_reg_n_0_[0]\ : STD_LOGIC; + signal \fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \fsm_reg_n_0_[2]\ : STD_LOGIC; + signal \fsm_reg_n_0_[3]\ : STD_LOGIC; + signal \fsm_reg_n_0_[4]\ : STD_LOGIC; + signal \fsm_reg_n_0_[5]\ : STD_LOGIC; + signal \fsm_reg_n_0_[6]\ : STD_LOGIC; + signal gen3_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO"; + attribute async_reg of gen3_reg1 : signal is "true"; + signal gen3_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO"; + attribute async_reg of gen3_reg2 : signal is "true"; + signal \gtx_common.gtxe2_common_i_i_3_n_0\ : STD_LOGIC; + signal \gtx_common.gtxe2_common_i_i_4_n_0\ : STD_LOGIC; + signal index : STD_LOGIC; + signal \index[0]_i_1_n_0\ : STD_LOGIC; + signal \index[1]_i_1_n_0\ : STD_LOGIC; + signal \index[2]_i_1_n_0\ : STD_LOGIC; + signal \index[2]_i_2_n_0\ : STD_LOGIC; + signal \index[2]_i_4_n_0\ : STD_LOGIC; + signal \index_reg_n_0_[0]\ : STD_LOGIC; + signal \index_reg_n_0_[1]\ : STD_LOGIC; + signal \index_reg_n_0_[2]\ : STD_LOGIC; + signal load_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \load_cnt[0]_i_1__0_n_0\ : STD_LOGIC; + signal \load_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \load_cnt[1]_i_2_n_0\ : STD_LOGIC; + signal ovrd_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of ovrd_reg1 : signal is "NO"; + attribute async_reg of ovrd_reg1 : signal is "true"; + signal ovrd_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of ovrd_reg2 : signal is "NO"; + attribute async_reg of ovrd_reg2 : signal is "true"; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal p_1_in : STD_LOGIC; + signal p_2_in : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal qplllock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of qplllock_reg1 : signal is "NO"; + attribute async_reg of qplllock_reg1 : signal is "true"; + signal qplllock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of qplllock_reg2 : signal is "NO"; + attribute async_reg of qplllock_reg2 : signal is "true"; + signal rdy_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rdy_reg1 : signal is "NO"; + attribute async_reg of rdy_reg1 : signal is "true"; + signal rdy_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rdy_reg2 : signal is "NO"; + attribute async_reg of rdy_reg2 : signal is "true"; + signal start_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of start_reg1 : signal is "NO"; + attribute async_reg of start_reg1 : signal is "true"; + signal start_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of start_reg2 : signal is "NO"; + attribute async_reg of start_reg2 : signal is "true"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \addr[0]_i_1\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \addr[1]_i_1\ : label is "soft_lutpair67"; + attribute SOFT_HLUTNM of \addr[2]_i_1\ : label is "soft_lutpair67"; + attribute SOFT_HLUTNM of \addr[5]_i_1\ : label is "soft_lutpair68"; + attribute SOFT_HLUTNM of \addr[7]_i_1\ : label is "soft_lutpair68"; + attribute SOFT_HLUTNM of \di[12]_i_2\ : label is "soft_lutpair66"; + attribute SOFT_HLUTNM of \di[13]_i_2\ : label is "soft_lutpair66"; + attribute SOFT_HLUTNM of \di[14]_i_2\ : label is "soft_lutpair64"; + attribute SOFT_HLUTNM of \di[15]_i_2\ : label is "soft_lutpair64"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \do_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \do_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[10]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[11]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[12]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[13]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[14]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[15]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[6]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[7]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[8]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg1_reg[9]\ : label is std.standard.true; + attribute KEEP of \do_reg1_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg1_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[10]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[11]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[12]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[13]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[14]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[15]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[6]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[7]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[8]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \do_reg2_reg[9]\ : label is std.standard.true; + attribute KEEP of \do_reg2_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \do_reg2_reg[9]\ : label is "NO"; + attribute SOFT_HLUTNM of \fsm[1]_i_1__1\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \fsm[2]_i_1__0\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \fsm_inferred__1/i_\ : label is "soft_lutpair65"; + attribute SOFT_HLUTNM of \fsm_inferred__1/i___0\ : label is "soft_lutpair65"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \fsm_reg[0]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000"; + attribute FSM_ENCODED_STATES of \fsm_reg[1]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000"; + attribute FSM_ENCODED_STATES of \fsm_reg[2]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000"; + attribute FSM_ENCODED_STATES of \fsm_reg[3]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000"; + attribute FSM_ENCODED_STATES of \fsm_reg[4]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000"; + attribute FSM_ENCODED_STATES of \fsm_reg[5]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000"; + attribute FSM_ENCODED_STATES of \fsm_reg[6]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000"; + attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true; + attribute KEEP of gen3_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true; + attribute KEEP of gen3_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \gtx_common.gtxe2_common_i_i_2\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \gtx_common.gtxe2_common_i_i_4\ : label is "soft_lutpair63"; + attribute SOFT_HLUTNM of \index[0]_i_1\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \index[1]_i_1\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \index[2]_i_1\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \index[2]_i_2\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \load_cnt[0]_i_1__0\ : label is "soft_lutpair62"; + attribute SOFT_HLUTNM of \load_cnt[1]_i_1\ : label is "soft_lutpair62"; + attribute SOFT_HLUTNM of \load_cnt[1]_i_2\ : label is "soft_lutpair63"; + attribute ASYNC_REG_boolean of ovrd_reg1_reg : label is std.standard.true; + attribute KEEP of ovrd_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of ovrd_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of ovrd_reg2_reg : label is std.standard.true; + attribute KEEP of ovrd_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of ovrd_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of qplllock_reg1_reg : label is std.standard.true; + attribute KEEP of qplllock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of qplllock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of qplllock_reg2_reg : label is std.standard.true; + attribute KEEP of qplllock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of qplllock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rdy_reg1_reg : label is std.standard.true; + attribute KEEP of rdy_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rdy_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rdy_reg2_reg : label is std.standard.true; + attribute KEEP of rdy_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rdy_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of start_reg1_reg : label is std.standard.true; + attribute KEEP of start_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of start_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of start_reg2_reg : label is std.standard.true; + attribute KEEP of start_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of start_reg2_reg : label is "NO"; +begin +\addr[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"12" + ) + port map ( + I0 => \index_reg_n_0_[1]\, + I1 => \index_reg_n_0_[0]\, + I2 => \index_reg_n_0_[2]\, + O => \addr[0]_i_1_n_0\ + ); +\addr[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => \index_reg_n_0_[2]\, + I1 => \index_reg_n_0_[0]\, + I2 => \index_reg_n_0_[1]\, + O => \addr[1]_i_1_n_0\ + ); +\addr[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"4D" + ) + port map ( + I0 => \index_reg_n_0_[1]\, + I1 => \index_reg_n_0_[2]\, + I2 => \index_reg_n_0_[0]\, + O => \addr[2]_i_1_n_0\ + ); +\addr[5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \index_reg_n_0_[1]\, + I1 => \index_reg_n_0_[0]\, + O => \addr[5]_i_1_n_0\ + ); +\addr[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => \index_reg_n_0_[1]\, + I1 => \index_reg_n_0_[0]\, + I2 => \index_reg_n_0_[2]\, + O => \addr[7]_i_1_n_0\ + ); +\addr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \addr[0]_i_1_n_0\, + Q => Q(0), + R => RST_DCLK_RESET + ); +\addr_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \addr[1]_i_1_n_0\, + Q => Q(1), + R => RST_DCLK_RESET + ); +\addr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \addr[2]_i_1_n_0\, + Q => Q(2), + R => RST_DCLK_RESET + ); +\addr_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \addr[5]_i_1_n_0\, + Q => Q(3), + R => RST_DCLK_RESET + ); +\addr_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \addr[7]_i_1_n_0\, + Q => Q(4), + R => RST_DCLK_RESET + ); +\crscode[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => do_reg2(1), + I1 => \index_reg_n_0_[2]\, + O => p_2_in(0) + ); +\crscode[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => do_reg2(2), + I1 => \index_reg_n_0_[2]\, + O => p_2_in(1) + ); +\crscode[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => do_reg2(3), + I1 => \index_reg_n_0_[2]\, + O => p_2_in(2) + ); +\crscode[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => do_reg2(4), + I1 => \index_reg_n_0_[2]\, + O => p_2_in(3) + ); +\crscode[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => do_reg2(5), + I1 => \index_reg_n_0_[2]\, + O => p_2_in(4) + ); +\crscode[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"C080" + ) + port map ( + I0 => ovrd_reg2, + I1 => \index_reg_n_0_[0]\, + I2 => \index_reg_n_0_[1]\, + I3 => \index_reg_n_0_[2]\, + O => p_1_in + ); +\crscode[5]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => do_reg2(6), + I1 => \index_reg_n_0_[2]\, + O => p_2_in(5) + ); +\crscode_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => p_1_in, + D => p_2_in(0), + Q => \crscode_reg_n_0_[0]\, + R => RST_DCLK_RESET + ); +\crscode_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => p_1_in, + D => p_2_in(1), + Q => \crscode_reg_n_0_[1]\, + R => RST_DCLK_RESET + ); +\crscode_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => p_1_in, + D => p_2_in(2), + Q => \crscode_reg_n_0_[2]\, + R => RST_DCLK_RESET + ); +\crscode_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => p_1_in, + D => p_2_in(3), + Q => \crscode_reg_n_0_[3]\, + R => RST_DCLK_RESET + ); +\crscode_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => p_1_in, + D => p_2_in(4), + Q => \crscode_reg_n_0_[4]\, + R => RST_DCLK_RESET + ); +\crscode_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => p_1_in, + D => p_2_in(5), + Q => \crscode_reg_n_0_[5]\, + R => RST_DCLK_RESET + ); +\di[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7E00" + ) + port map ( + I0 => \index_reg_n_0_[0]\, + I1 => \index_reg_n_0_[2]\, + I2 => \index_reg_n_0_[1]\, + I3 => do_reg2(0), + O => di(0) + ); +\di[10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0CC5CCCC" + ) + port map ( + I0 => \crscode_reg_n_0_[0]\, + I1 => do_reg2(10), + I2 => \index_reg_n_0_[1]\, + I3 => \index_reg_n_0_[0]\, + I4 => \index_reg_n_0_[2]\, + O => di(10) + ); +\di[11]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAEBAA" + ) + port map ( + I0 => \di[11]_i_2_n_0\, + I1 => \crscode_reg_n_0_[0]\, + I2 => \crscode_reg_n_0_[1]\, + I3 => \index_reg_n_0_[2]\, + I4 => \index_reg_n_0_[0]\, + I5 => \index_reg_n_0_[1]\, + O => di(11) + ); +\di[11]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20FF2044" + ) + port map ( + I0 => \index_reg_n_0_[0]\, + I1 => \index_reg_n_0_[1]\, + I2 => ovrd_reg2, + I3 => \index_reg_n_0_[2]\, + I4 => do_reg2(11), + O => \di[11]_i_2_n_0\ + ); +\di[12]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00AA0000AAAAC3AA" + ) + port map ( + I0 => do_reg2(12), + I1 => \di[12]_i_2_n_0\, + I2 => \crscode_reg_n_0_[2]\, + I3 => \index_reg_n_0_[2]\, + I4 => \index_reg_n_0_[0]\, + I5 => \index_reg_n_0_[1]\, + O => di(12) + ); +\di[12]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \crscode_reg_n_0_[0]\, + I1 => \crscode_reg_n_0_[1]\, + O => \di[12]_i_2_n_0\ + ); +\di[13]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00F0F099F0F0FFF0" + ) + port map ( + I0 => \crscode_reg_n_0_[3]\, + I1 => \di[13]_i_2_n_0\, + I2 => do_reg2(13), + I3 => \index_reg_n_0_[1]\, + I4 => \index_reg_n_0_[0]\, + I5 => \index_reg_n_0_[2]\, + O => di(13) + ); +\di[13]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \crscode_reg_n_0_[1]\, + I1 => \crscode_reg_n_0_[0]\, + I2 => \crscode_reg_n_0_[2]\, + O => \di[13]_i_2_n_0\ + ); +\di[14]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00F0F099F0F0FFF0" + ) + port map ( + I0 => \crscode_reg_n_0_[4]\, + I1 => \di[14]_i_2_n_0\, + I2 => do_reg2(14), + I3 => \index_reg_n_0_[1]\, + I4 => \index_reg_n_0_[0]\, + I5 => \index_reg_n_0_[2]\, + O => di(14) + ); +\di[14]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \crscode_reg_n_0_[2]\, + I1 => \crscode_reg_n_0_[0]\, + I2 => \crscode_reg_n_0_[1]\, + I3 => \crscode_reg_n_0_[3]\, + O => \di[14]_i_2_n_0\ + ); +\di[15]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0AACAAAA0AA3AAAA" + ) + port map ( + I0 => do_reg2(15), + I1 => \di[15]_i_2_n_0\, + I2 => \index_reg_n_0_[1]\, + I3 => \index_reg_n_0_[0]\, + I4 => \index_reg_n_0_[2]\, + I5 => \crscode_reg_n_0_[5]\, + O => di(15) + ); +\di[15]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \crscode_reg_n_0_[3]\, + I1 => \crscode_reg_n_0_[1]\, + I2 => \crscode_reg_n_0_[0]\, + I3 => \crscode_reg_n_0_[2]\, + I4 => \crscode_reg_n_0_[4]\, + O => \di[15]_i_2_n_0\ + ); +\di[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7E00" + ) + port map ( + I0 => \index_reg_n_0_[0]\, + I1 => \index_reg_n_0_[2]\, + I2 => \index_reg_n_0_[1]\, + I3 => do_reg2(1), + O => di(1) + ); +\di[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7E00" + ) + port map ( + I0 => \index_reg_n_0_[0]\, + I1 => \index_reg_n_0_[2]\, + I2 => \index_reg_n_0_[1]\, + I3 => do_reg2(2), + O => di(2) + ); +\di[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7E00" + ) + port map ( + I0 => \index_reg_n_0_[0]\, + I1 => \index_reg_n_0_[2]\, + I2 => \index_reg_n_0_[1]\, + I3 => do_reg2(3), + O => di(3) + ); +\di[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7E00" + ) + port map ( + I0 => \index_reg_n_0_[0]\, + I1 => \index_reg_n_0_[2]\, + I2 => \index_reg_n_0_[1]\, + I3 => do_reg2(4), + O => di(4) + ); +\di[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2AAB" + ) + port map ( + I0 => do_reg2(5), + I1 => \index_reg_n_0_[1]\, + I2 => \index_reg_n_0_[0]\, + I3 => \index_reg_n_0_[2]\, + O => di(5) + ); +\di[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2BA8" + ) + port map ( + I0 => do_reg2(6), + I1 => \index_reg_n_0_[1]\, + I2 => \index_reg_n_0_[2]\, + I3 => \index_reg_n_0_[0]\, + O => di(6) + ); +\di[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7E00" + ) + port map ( + I0 => \index_reg_n_0_[0]\, + I1 => \index_reg_n_0_[2]\, + I2 => \index_reg_n_0_[1]\, + I3 => do_reg2(7), + O => di(7) + ); +\di[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2AAB" + ) + port map ( + I0 => do_reg2(8), + I1 => \index_reg_n_0_[1]\, + I2 => \index_reg_n_0_[0]\, + I3 => \index_reg_n_0_[2]\, + O => di(8) + ); +\di[9]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7E00" + ) + port map ( + I0 => \index_reg_n_0_[0]\, + I1 => \index_reg_n_0_[2]\, + I2 => \index_reg_n_0_[1]\, + I3 => do_reg2(9), + O => di(9) + ); +\di_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(0), + Q => \di_reg[15]_0\(0), + R => RST_DCLK_RESET + ); +\di_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(10), + Q => \di_reg[15]_0\(10), + R => RST_DCLK_RESET + ); +\di_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(11), + Q => \di_reg[15]_0\(11), + R => RST_DCLK_RESET + ); +\di_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(12), + Q => \di_reg[15]_0\(12), + R => RST_DCLK_RESET + ); +\di_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(13), + Q => \di_reg[15]_0\(13), + R => RST_DCLK_RESET + ); +\di_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(14), + Q => \di_reg[15]_0\(14), + R => RST_DCLK_RESET + ); +\di_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(15), + Q => \di_reg[15]_0\(15), + R => RST_DCLK_RESET + ); +\di_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(1), + Q => \di_reg[15]_0\(1), + R => RST_DCLK_RESET + ); +\di_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(2), + Q => \di_reg[15]_0\(2), + R => RST_DCLK_RESET + ); +\di_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(3), + Q => \di_reg[15]_0\(3), + R => RST_DCLK_RESET + ); +\di_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(4), + Q => \di_reg[15]_0\(4), + R => RST_DCLK_RESET + ); +\di_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(5), + Q => \di_reg[15]_0\(5), + R => RST_DCLK_RESET + ); +\di_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(6), + Q => \di_reg[15]_0\(6), + R => RST_DCLK_RESET + ); +\di_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(7), + Q => \di_reg[15]_0\(7), + R => RST_DCLK_RESET + ); +\di_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(8), + Q => \di_reg[15]_0\(8), + R => RST_DCLK_RESET + ); +\di_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => di(9), + Q => \di_reg[15]_0\(9), + R => RST_DCLK_RESET + ); +\do_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(0), + Q => do_reg1(0), + R => RST_DCLK_RESET + ); +\do_reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(10), + Q => do_reg1(10), + R => RST_DCLK_RESET + ); +\do_reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(11), + Q => do_reg1(11), + R => RST_DCLK_RESET + ); +\do_reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(12), + Q => do_reg1(12), + R => RST_DCLK_RESET + ); +\do_reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(13), + Q => do_reg1(13), + R => RST_DCLK_RESET + ); +\do_reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(14), + Q => do_reg1(14), + R => RST_DCLK_RESET + ); +\do_reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(15), + Q => do_reg1(15), + R => RST_DCLK_RESET + ); +\do_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(1), + Q => do_reg1(1), + R => RST_DCLK_RESET + ); +\do_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(2), + Q => do_reg1(2), + R => RST_DCLK_RESET + ); +\do_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(3), + Q => do_reg1(3), + R => RST_DCLK_RESET + ); +\do_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(4), + Q => do_reg1(4), + R => RST_DCLK_RESET + ); +\do_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(5), + Q => do_reg1(5), + R => RST_DCLK_RESET + ); +\do_reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(6), + Q => do_reg1(6), + R => RST_DCLK_RESET + ); +\do_reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(7), + Q => do_reg1(7), + R => RST_DCLK_RESET + ); +\do_reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(8), + Q => do_reg1(8), + R => RST_DCLK_RESET + ); +\do_reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => D(9), + Q => do_reg1(9), + R => RST_DCLK_RESET + ); +\do_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(0), + Q => do_reg2(0), + R => RST_DCLK_RESET + ); +\do_reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(10), + Q => do_reg2(10), + R => RST_DCLK_RESET + ); +\do_reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(11), + Q => do_reg2(11), + R => RST_DCLK_RESET + ); +\do_reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(12), + Q => do_reg2(12), + R => RST_DCLK_RESET + ); +\do_reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(13), + Q => do_reg2(13), + R => RST_DCLK_RESET + ); +\do_reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(14), + Q => do_reg2(14), + R => RST_DCLK_RESET + ); +\do_reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(15), + Q => do_reg2(15), + R => RST_DCLK_RESET + ); +\do_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(1), + Q => do_reg2(1), + R => RST_DCLK_RESET + ); +\do_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(2), + Q => do_reg2(2), + R => RST_DCLK_RESET + ); +\do_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(3), + Q => do_reg2(3), + R => RST_DCLK_RESET + ); +\do_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(4), + Q => do_reg2(4), + R => RST_DCLK_RESET + ); +\do_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(5), + Q => do_reg2(5), + R => RST_DCLK_RESET + ); +\do_reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(6), + Q => do_reg2(6), + R => RST_DCLK_RESET + ); +\do_reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(7), + Q => do_reg2(7), + R => RST_DCLK_RESET + ); +\do_reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(8), + Q => do_reg2(8), + R => RST_DCLK_RESET + ); +\do_reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => do_reg1(9), + Q => do_reg2(9), + R => RST_DCLK_RESET + ); +done_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000010" + ) + port map ( + I0 => \fsm_reg_n_0_[6]\, + I1 => start_reg2, + I2 => \fsm_reg_n_0_[0]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm_reg_n_0_[4]\, + I5 => \gtx_common.gtxe2_common_i_i_4_n_0\, + O => done + ); +done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => done, + Q => QPLL_DRP_DONE, + R => RST_DCLK_RESET + ); +\fsm[0]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5DFF5D5D5D5D5D5D" + ) + port map ( + I0 => \fsm_inferred__1/i___1_n_0\, + I1 => \fsm_reg_n_0_[0]\, + I2 => start_reg2, + I3 => \fsm[0]_i_2__1_n_0\, + I4 => \index_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[6]\, + O => \p_0_in__0\(0) + ); +\fsm[0]_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \index_reg_n_0_[0]\, + I1 => \index_reg_n_0_[2]\, + O => \fsm[0]_i_2__1_n_0\ + ); +\fsm[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7000" + ) + port map ( + I0 => load_cnt(0), + I1 => load_cnt(1), + I2 => \fsm_inferred__1/i___1_n_0\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \fsm[1]_i_2__0_n_0\, + O => \p_0_in__0\(1) + ); +\fsm[1]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF00B000B000B000" + ) + port map ( + I0 => \fsm[0]_i_2__1_n_0\, + I1 => \index_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[6]\, + I3 => \fsm_inferred__1/i___1_n_0\, + I4 => \fsm_reg_n_0_[0]\, + I5 => start_reg2, + O => \fsm[1]_i_2__0_n_0\ + ); +\fsm[2]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_inferred__1/i___1_n_0\, + I2 => load_cnt(1), + I3 => load_cnt(0), + O => \p_0_in__0\(2) + ); +\fsm[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88C8" + ) + port map ( + I0 => \fsm_reg_n_0_[2]\, + I1 => \fsm_inferred__1/i___1_n_0\, + I2 => \fsm_reg_n_0_[3]\, + I3 => rdy_reg2, + O => \p_0_in__0\(3) + ); +\fsm[4]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => rdy_reg2, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_inferred__1/i___1_n_0\, + O => \p_0_in__0\(4) + ); +\fsm[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88C8" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_inferred__1/i___1_n_0\, + I2 => \fsm_reg_n_0_[5]\, + I3 => rdy_reg2, + O => \p_0_in__0\(5) + ); +\fsm[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => rdy_reg2, + I1 => \fsm_reg_n_0_[5]\, + I2 => \fsm_inferred__1/i___1_n_0\, + O => \p_0_in__0\(6) + ); +\fsm_inferred__1/i_\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0116" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + O => \fsm_inferred__1/i__n_0\ + ); +\fsm_inferred__1/i___0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEE8" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[1]\, + I2 => \fsm_reg_n_0_[2]\, + I3 => \fsm_reg_n_0_[3]\, + O => \fsm_inferred__1/i___0_n_0\ + ); +\fsm_inferred__1/i___1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000116" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[5]\, + I2 => \fsm_reg_n_0_[6]\, + I3 => \fsm_inferred__1/i__n_0\, + I4 => \fsm_inferred__1/i___0_n_0\, + O => \fsm_inferred__1/i___1_n_0\ + ); +\fsm_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \p_0_in__0\(0), + Q => \fsm_reg_n_0_[0]\, + S => RST_DCLK_RESET + ); +\fsm_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \p_0_in__0\(1), + Q => \fsm_reg_n_0_[1]\, + R => RST_DCLK_RESET + ); +\fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \p_0_in__0\(2), + Q => \fsm_reg_n_0_[2]\, + R => RST_DCLK_RESET + ); +\fsm_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \p_0_in__0\(3), + Q => \fsm_reg_n_0_[3]\, + R => RST_DCLK_RESET + ); +\fsm_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \p_0_in__0\(4), + Q => \fsm_reg_n_0_[4]\, + R => RST_DCLK_RESET + ); +\fsm_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \p_0_in__0\(5), + Q => \fsm_reg_n_0_[5]\, + R => RST_DCLK_RESET + ); +\fsm_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \p_0_in__0\(6), + Q => \fsm_reg_n_0_[6]\, + R => RST_DCLK_RESET + ); +gen3_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => QPLL_DRP_GEN3, + Q => gen3_reg1, + R => RST_DCLK_RESET + ); +gen3_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => gen3_reg1, + Q => gen3_reg2, + R => RST_DCLK_RESET + ); +\gtx_common.gtxe2_common_i_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000010100" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[0]\, + I2 => \fsm_reg_n_0_[6]\, + I3 => \fsm_reg_n_0_[4]\, + I4 => \fsm_reg_n_0_[2]\, + I5 => \gtx_common.gtxe2_common_i_i_3_n_0\, + O => qpll_drp_en + ); +\gtx_common.gtxe2_common_i_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000010" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[6]\, + I2 => \fsm_reg_n_0_[4]\, + I3 => \fsm_reg_n_0_[1]\, + I4 => \gtx_common.gtxe2_common_i_i_4_n_0\, + O => qpll_drp_we + ); +\gtx_common.gtxe2_common_i_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \fsm_reg_n_0_[3]\, + I1 => \fsm_reg_n_0_[5]\, + O => \gtx_common.gtxe2_common_i_i_3_n_0\ + ); +\gtx_common.gtxe2_common_i_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \fsm_reg_n_0_[5]\, + I1 => \fsm_reg_n_0_[3]\, + I2 => \fsm_reg_n_0_[2]\, + O => \gtx_common.gtxe2_common_i_i_4_n_0\ + ); +\index[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00FF7000" + ) + port map ( + I0 => \index_reg_n_0_[1]\, + I1 => \index_reg_n_0_[2]\, + I2 => \index[2]_i_2_n_0\, + I3 => index, + I4 => \index_reg_n_0_[0]\, + O => \index[0]_i_1_n_0\ + ); +\index[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"10FFC000" + ) + port map ( + I0 => \index_reg_n_0_[2]\, + I1 => \index_reg_n_0_[0]\, + I2 => \index[2]_i_2_n_0\, + I3 => index, + I4 => \index_reg_n_0_[1]\, + O => \index[1]_i_1_n_0\ + ); +\index[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"22FF8000" + ) + port map ( + I0 => \index[2]_i_2_n_0\, + I1 => \index_reg_n_0_[1]\, + I2 => \index_reg_n_0_[0]\, + I3 => index, + I4 => \index_reg_n_0_[2]\, + O => \index[2]_i_1_n_0\ + ); +\index[2]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000004" + ) + port map ( + I0 => \fsm_reg_n_0_[1]\, + I1 => \fsm_reg_n_0_[6]\, + I2 => \fsm_reg_n_0_[0]\, + I3 => \gtx_common.gtxe2_common_i_i_4_n_0\, + I4 => \fsm_reg_n_0_[4]\, + O => \index[2]_i_2_n_0\ + ); +\index[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFEFEEB" + ) + port map ( + I0 => \index[2]_i_4_n_0\, + I1 => \fsm_reg_n_0_[5]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[1]\, + I5 => \fsm_reg_n_0_[4]\, + O => index + ); +\index[2]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \fsm_reg_n_0_[0]\, + I1 => \fsm_reg_n_0_[6]\, + O => \index[2]_i_4_n_0\ + ); +\index_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \index[0]_i_1_n_0\, + Q => \index_reg_n_0_[0]\, + R => RST_DCLK_RESET + ); +\index_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \index[1]_i_1_n_0\, + Q => \index_reg_n_0_[1]\, + R => RST_DCLK_RESET + ); +\index_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \index[2]_i_1_n_0\, + Q => \index_reg_n_0_[2]\, + R => RST_DCLK_RESET + ); +\load_cnt[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00B00000" + ) + port map ( + I0 => load_cnt(1), + I1 => load_cnt(0), + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[6]\, + I4 => \load_cnt[1]_i_2_n_0\, + O => \load_cnt[0]_i_1__0_n_0\ + ); +\load_cnt[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00E00000" + ) + port map ( + I0 => load_cnt(0), + I1 => load_cnt(1), + I2 => \fsm_reg_n_0_[1]\, + I3 => \fsm_reg_n_0_[6]\, + I4 => \load_cnt[1]_i_2_n_0\, + O => \load_cnt[1]_i_1_n_0\ + ); +\load_cnt[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \fsm_reg_n_0_[4]\, + I1 => \fsm_reg_n_0_[5]\, + I2 => \fsm_reg_n_0_[3]\, + I3 => \fsm_reg_n_0_[2]\, + I4 => \fsm_reg_n_0_[0]\, + O => \load_cnt[1]_i_2_n_0\ + ); +\load_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \load_cnt[0]_i_1__0_n_0\, + Q => load_cnt(0), + R => RST_DCLK_RESET + ); +\load_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_dclk_in, + CE => '1', + D => \load_cnt[1]_i_1_n_0\, + Q => load_cnt(1), + R => RST_DCLK_RESET + ); +ovrd_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => '0', + Q => ovrd_reg1, + R => RST_DCLK_RESET + ); +ovrd_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => ovrd_reg1, + Q => ovrd_reg2, + R => RST_DCLK_RESET + ); +qplllock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => QPLL_QPLLLOCK, + Q => qplllock_reg1, + R => RST_DCLK_RESET + ); +qplllock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => qplllock_reg1, + Q => qplllock_reg2, + R => RST_DCLK_RESET + ); +rdy_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => qpll_drp_rdy, + Q => rdy_reg1, + R => RST_DCLK_RESET + ); +rdy_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => rdy_reg1, + Q => rdy_reg2, + R => RST_DCLK_RESET + ); +start_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => QRST_DRP_START, + Q => start_reg1, + R => RST_DCLK_RESET + ); +start_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_dclk_in, + CE => '1', + D => start_reg1, + Q => start_reg2, + R => RST_DCLK_RESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_qpll_reset is + port ( + Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + QPLL_QPLLRESET : out STD_LOGIC; + QPLL_QPLLPD : out STD_LOGIC; + SS : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_pclk_in : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rate_reg1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + QRST_DRP_DONE : in STD_LOGIC_VECTOR ( 0 to 0 ); + \qpllreset_in_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + QPLL_QPLLLOCK : in STD_LOGIC; + \cplllock_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_mmcm_lock_in : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_qpll_reset; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_qpll_reset is + signal \FSM_onehot_fsm[0]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[1]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[1]_i_2__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[2]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[3]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[5]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[5]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[6]\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^qpll_qpllpd\ : STD_LOGIC; + signal \^qpll_qpllreset\ : STD_LOGIC; + signal cplllock_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of cplllock_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of cplllock_reg1 : signal is "true"; + signal cplllock_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of cplllock_reg2 : signal is "NO"; + attribute async_reg of cplllock_reg2 : signal is "true"; + signal drp_done_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO"; + attribute async_reg of drp_done_reg1 : signal is "true"; + signal drp_done_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO"; + attribute async_reg of drp_done_reg2 : signal is "true"; + signal fsm2 : STD_LOGIC; + signal mmcm_lock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO"; + attribute async_reg of mmcm_lock_reg1 : signal is "true"; + signal mmcm_lock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO"; + attribute async_reg of mmcm_lock_reg2 : signal is "true"; + signal qplllock_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of qplllock_reg1 : signal is "NO"; + attribute async_reg of qplllock_reg1 : signal is "true"; + signal qplllock_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of qplllock_reg2 : signal is "NO"; + attribute async_reg of qplllock_reg2 : signal is "true"; + signal qpllpd : STD_LOGIC; + signal qpllpd_i_1_n_0 : STD_LOGIC; + signal qpllpd_i_2_n_0 : STD_LOGIC; + signal qpllpd_in_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of qpllpd_in_reg1 : signal is "NO"; + attribute async_reg of qpllpd_in_reg1 : signal is "true"; + signal qpllpd_in_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of qpllpd_in_reg2 : signal is "NO"; + attribute async_reg of qpllpd_in_reg2 : signal is "true"; + signal qpllreset_i_1_n_0 : STD_LOGIC; + signal qpllreset_i_2_n_0 : STD_LOGIC; + signal qpllreset_i_3_n_0 : STD_LOGIC; + signal qpllreset_in_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of qpllreset_in_reg1 : signal is "NO"; + attribute async_reg of qpllreset_in_reg1 : signal is "true"; + signal qpllreset_in_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of qpllreset_in_reg2 : signal is "NO"; + attribute async_reg of qpllreset_in_reg2 : signal is "true"; + signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_reg1 : signal is "NO"; + attribute async_reg of rate_reg1 : signal is "true"; + signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rate_reg2 : signal is "NO"; + attribute async_reg of rate_reg2 : signal is "true"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[0]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[5]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[6]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[7]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \cplllock_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \cplllock_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \cplllock_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \cplllock_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \cplllock_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \drp_done_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \drp_done_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \drp_done_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \drp_done_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \drp_done_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \drp_done_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true; + attribute KEEP of mmcm_lock_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of \qplllock_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \qplllock_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qplllock_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qplllock_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \qplllock_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qplllock_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllpd_in_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \qpllpd_in_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllpd_in_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllpd_in_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \qpllpd_in_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllpd_in_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllpd_in_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \qpllpd_in_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllpd_in_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllpd_in_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \qpllpd_in_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllpd_in_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllpd_in_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \qpllpd_in_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllpd_in_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllpd_in_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \qpllpd_in_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllpd_in_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllpd_in_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \qpllpd_in_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllpd_in_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllpd_in_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \qpllpd_in_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllpd_in_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllreset_in_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \qpllreset_in_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllreset_in_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllreset_in_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \qpllreset_in_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllreset_in_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllreset_in_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \qpllreset_in_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllreset_in_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllreset_in_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \qpllreset_in_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllreset_in_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllreset_in_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \qpllreset_in_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllreset_in_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllreset_in_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \qpllreset_in_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllreset_in_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllreset_in_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \qpllreset_in_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllreset_in_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \qpllreset_in_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \qpllreset_in_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \qpllreset_in_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rate_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rate_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rate_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rate_reg2_reg[1]\ : label is "NO"; +begin + Q(1 downto 0) <= \^q\(1 downto 0); + QPLL_QPLLPD <= \^qpll_qpllpd\; + QPLL_QPLLRESET <= \^qpll_qpllreset\; +\FSM_onehot_fsm[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAAAA8" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[0]\, + I1 => qplllock_reg2, + I2 => cplllock_reg2(1), + I3 => cplllock_reg2(0), + I4 => cplllock_reg2(3), + I5 => cplllock_reg2(2), + O => \FSM_onehot_fsm[0]_i_1__0_n_0\ + ); +\FSM_onehot_fsm[1]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8F88" + ) + port map ( + I0 => \FSM_onehot_fsm[1]_i_2__0_n_0\, + I1 => \FSM_onehot_fsm_reg_n_0_[0]\, + I2 => fsm2, + I3 => \FSM_onehot_fsm_reg_n_0_[1]\, + O => \FSM_onehot_fsm[1]_i_1__0_n_0\ + ); +\FSM_onehot_fsm[1]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => cplllock_reg2(2), + I1 => cplllock_reg2(3), + I2 => cplllock_reg2(0), + I3 => cplllock_reg2(1), + I4 => qplllock_reg2, + O => \FSM_onehot_fsm[1]_i_2__0_n_0\ + ); +\FSM_onehot_fsm[2]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => fsm2, + I1 => \FSM_onehot_fsm_reg_n_0_[1]\, + I2 => drp_done_reg2, + I3 => \^q\(0), + O => \FSM_onehot_fsm[2]_i_1__0_n_0\ + ); +\FSM_onehot_fsm[2]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => mmcm_lock_reg2, + I1 => cplllock_reg2(2), + I2 => cplllock_reg2(3), + I3 => cplllock_reg2(0), + I4 => cplllock_reg2(1), + O => fsm2 + ); +\FSM_onehot_fsm[3]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"32" + ) + port map ( + I0 => \^q\(0), + I1 => drp_done_reg2, + I2 => \FSM_onehot_fsm_reg_n_0_[3]\, + O => \FSM_onehot_fsm[3]_i_1__0_n_0\ + ); +\FSM_onehot_fsm[4]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8F88" + ) + port map ( + I0 => drp_done_reg2, + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => qplllock_reg2, + I3 => \FSM_onehot_fsm_reg_n_0_[4]\, + O => \FSM_onehot_fsm[4]_i_1__0_n_0\ + ); +\FSM_onehot_fsm[5]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => qplllock_reg2, + O => \FSM_onehot_fsm[5]_i_1__0_n_0\ + ); +\FSM_onehot_fsm[7]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[6]\, + I1 => \^q\(1), + O => qpllpd + ); +\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[0]_i_1__0_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[0]\, + S => SS(0) + ); +\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[1]_i_1__0_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[1]\, + R => SS(0) + ); +\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[2]_i_1__0_n_0\, + Q => \^q\(0), + R => SS(0) + ); +\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[3]_i_1__0_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[3]\, + R => SS(0) + ); +\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[4]_i_1__0_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[4]\, + R => SS(0) + ); +\FSM_onehot_fsm_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[5]_i_1__0_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[5]\, + R => SS(0) + ); +\FSM_onehot_fsm_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_reg_n_0_[5]\, + Q => \FSM_onehot_fsm_reg_n_0_[6]\, + R => SS(0) + ); +\FSM_onehot_fsm_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => qpllpd, + Q => \^q\(1), + R => SS(0) + ); +\cplllock_reg1_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \cplllock_reg1_reg[3]_0\(0), + Q => cplllock_reg1(0), + S => SS(0) + ); +\cplllock_reg1_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \cplllock_reg1_reg[3]_0\(1), + Q => cplllock_reg1(1), + S => SS(0) + ); +\cplllock_reg1_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \cplllock_reg1_reg[3]_0\(2), + Q => cplllock_reg1(2), + S => SS(0) + ); +\cplllock_reg1_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \cplllock_reg1_reg[3]_0\(3), + Q => cplllock_reg1(3), + S => SS(0) + ); +\cplllock_reg2_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => cplllock_reg1(0), + Q => cplllock_reg2(0), + S => SS(0) + ); +\cplllock_reg2_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => cplllock_reg1(1), + Q => cplllock_reg2(1), + S => SS(0) + ); +\cplllock_reg2_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => cplllock_reg1(2), + Q => cplllock_reg2(2), + S => SS(0) + ); +\cplllock_reg2_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => cplllock_reg1(3), + Q => cplllock_reg2(3), + S => SS(0) + ); +\drp_done_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => QRST_DRP_DONE(0), + Q => drp_done_reg1, + R => SS(0) + ); +\drp_done_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => drp_done_reg1, + Q => drp_done_reg2, + R => SS(0) + ); +mmcm_lock_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_mmcm_lock_in, + Q => mmcm_lock_reg1, + R => SS(0) + ); +mmcm_lock_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => mmcm_lock_reg1, + Q => mmcm_lock_reg2, + R => SS(0) + ); +\qplllock_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => QPLL_QPLLLOCK, + Q => qplllock_reg1, + R => SS(0) + ); +\qplllock_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qplllock_reg1, + Q => qplllock_reg2, + R => SS(0) + ); +qpllpd_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBF0FBFFFBF0FB00" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + I2 => qpllpd_i_2_n_0, + I3 => \FSM_onehot_fsm_reg_n_0_[6]\, + I4 => \^q\(1), + I5 => \^qpll_qpllpd\, + O => qpllpd_i_1_n_0 + ); +qpllpd_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \^q\(1), + I1 => qpllpd_in_reg2(2), + I2 => qpllpd_in_reg2(3), + I3 => qpllpd_in_reg2(0), + I4 => qpllpd_in_reg2(1), + O => qpllpd_i_2_n_0 + ); +\qpllpd_in_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => D(0), + Q => qpllpd_in_reg1(0), + R => SS(0) + ); +\qpllpd_in_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => D(1), + Q => qpllpd_in_reg1(1), + R => SS(0) + ); +\qpllpd_in_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => D(2), + Q => qpllpd_in_reg1(2), + R => SS(0) + ); +\qpllpd_in_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => D(3), + Q => qpllpd_in_reg1(3), + R => SS(0) + ); +\qpllpd_in_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qpllpd_in_reg1(0), + Q => qpllpd_in_reg2(0), + R => SS(0) + ); +\qpllpd_in_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qpllpd_in_reg1(1), + Q => qpllpd_in_reg2(1), + R => SS(0) + ); +\qpllpd_in_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qpllpd_in_reg1(2), + Q => qpllpd_in_reg2(2), + R => SS(0) + ); +\qpllpd_in_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qpllpd_in_reg1(3), + Q => qpllpd_in_reg2(3), + R => SS(0) + ); +qpllpd_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => qpllpd_i_1_n_0, + Q => \^qpll_qpllpd\, + R => SS(0) + ); +qpllreset_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"ECECECEFECECECE0" + ) + port map ( + I0 => qpllreset_i_2_n_0, + I1 => qpllreset_i_3_n_0, + I2 => \FSM_onehot_fsm_reg_n_0_[5]\, + I3 => \FSM_onehot_fsm_reg_n_0_[4]\, + I4 => \^q\(1), + I5 => \^qpll_qpllreset\, + O => qpllreset_i_1_n_0 + ); +qpllreset_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => rate_reg2(0), + I1 => rate_reg2(1), + O => qpllreset_i_2_n_0 + ); +qpllreset_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \^q\(1), + I1 => qpllreset_in_reg2(2), + I2 => qpllreset_in_reg2(3), + I3 => qpllreset_in_reg2(0), + I4 => qpllreset_in_reg2(1), + O => qpllreset_i_3_n_0 + ); +\qpllreset_in_reg1_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \qpllreset_in_reg1_reg[3]_0\(0), + Q => qpllreset_in_reg1(0), + S => SS(0) + ); +\qpllreset_in_reg1_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \qpllreset_in_reg1_reg[3]_0\(1), + Q => qpllreset_in_reg1(1), + S => SS(0) + ); +\qpllreset_in_reg1_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \qpllreset_in_reg1_reg[3]_0\(2), + Q => qpllreset_in_reg1(2), + S => SS(0) + ); +\qpllreset_in_reg1_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \qpllreset_in_reg1_reg[3]_0\(3), + Q => qpllreset_in_reg1(3), + S => SS(0) + ); +\qpllreset_in_reg2_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qpllreset_in_reg1(0), + Q => qpllreset_in_reg2(0), + S => SS(0) + ); +\qpllreset_in_reg2_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qpllreset_in_reg1(1), + Q => qpllreset_in_reg2(1), + S => SS(0) + ); +\qpllreset_in_reg2_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qpllreset_in_reg1(2), + Q => qpllreset_in_reg2(2), + S => SS(0) + ); +\qpllreset_in_reg2_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => qpllreset_in_reg1(3), + Q => qpllreset_in_reg2(3), + S => SS(0) + ); +qpllreset_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => qpllreset_i_1_n_0, + Q => \^qpll_qpllreset\, + S => SS(0) + ); +\rate_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rate_reg1_reg[0]_0\(0), + Q => rate_reg1(0), + R => SS(0) + ); +\rate_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rate_reg1(1), + R => SS(0) + ); +\rate_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_reg1(0), + Q => rate_reg2(0), + R => SS(0) + ); +\rate_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_reg1(1), + Q => rate_reg2(1), + R => SS(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_qpll_wrapper is + port ( + qpll_drp_rdy : out STD_LOGIC; + QPLL_QPLLLOCK : out STD_LOGIC; + QPLL_QPLLOUTCLK : out STD_LOGIC; + QPLL_QPLLOUTREFCLK : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 15 downto 0 ); + pipe_dclk_in : in STD_LOGIC; + qpll_drp_en : in STD_LOGIC; + qpll_drp_we : in STD_LOGIC; + sys_clk : in STD_LOGIC; + QPLL_QPLLPD : in STD_LOGIC; + QPLL_QPLLRESET : in STD_LOGIC; + rdy_reg1_reg : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_qpll_wrapper; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_qpll_wrapper is + signal \NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \gtx_common.gtxe2_common_i\ : label is "PRIMITIVE"; +begin +\gtx_common.gtxe2_common_i\: unisim.vcomponents.GTXE2_COMMON + generic map( + BIAS_CFG => X"0000040000001000", + COMMON_CFG => X"00000000", + IS_DRPCLK_INVERTED => '0', + IS_GTGREFCLK_INVERTED => '0', + IS_QPLLLOCKDETCLK_INVERTED => '0', + QPLL_CFG => X"06801C1", + QPLL_CLKOUT_CFG => B"0000", + QPLL_COARSE_FREQ_OVRD => B"010000", + QPLL_COARSE_FREQ_OVRD_EN => '0', + QPLL_CP => B"0000011111", + QPLL_CP_MONITOR_EN => '0', + QPLL_DMONITOR_SEL => '0', + QPLL_FBDIV => B"0100100000", + QPLL_FBDIV_MONITOR_EN => '0', + QPLL_FBDIV_RATIO => '1', + QPLL_INIT_CFG => X"000006", + QPLL_LOCK_CFG => X"21E8", + QPLL_LPF => B"1101", + QPLL_REFCLK_DIV => 1, + SIM_QPLLREFCLK_SEL => B"001", + SIM_RESET_SPEEDUP => "FALSE", + SIM_VERSION => "3.0" + ) + port map ( + BGBYPASSB => '1', + BGMONITORENB => '1', + BGPDB => '1', + BGRCALOVRD(4 downto 0) => B"11111", + DRPADDR(7) => Q(4), + DRPADDR(6) => '0', + DRPADDR(5) => Q(3), + DRPADDR(4) => Q(3), + DRPADDR(3) => Q(4), + DRPADDR(2 downto 0) => Q(2 downto 0), + DRPCLK => pipe_dclk_in, + DRPDI(15 downto 0) => rdy_reg1_reg(15 downto 0), + DRPDO(15 downto 0) => D(15 downto 0), + DRPEN => qpll_drp_en, + DRPRDY => qpll_drp_rdy, + DRPWE => qpll_drp_we, + GTGREFCLK => '0', + GTNORTHREFCLK0 => '0', + GTNORTHREFCLK1 => '0', + GTREFCLK0 => sys_clk, + GTREFCLK1 => '0', + GTSOUTHREFCLK0 => '0', + GTSOUTHREFCLK1 => '0', + PMARSVD(7 downto 0) => B"00000000", + QPLLDMONITOR(7 downto 0) => \NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED\(7 downto 0), + QPLLFBCLKLOST => \NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED\, + QPLLLOCK => QPLL_QPLLLOCK, + QPLLLOCKDETCLK => '0', + QPLLLOCKEN => '1', + QPLLOUTCLK => QPLL_QPLLOUTCLK, + QPLLOUTREFCLK => QPLL_QPLLOUTREFCLK, + QPLLOUTRESET => '0', + QPLLPD => QPLL_QPLLPD, + QPLLREFCLKLOST => \NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED\, + QPLLREFCLKSEL(2 downto 0) => B"001", + QPLLRESET => QPLL_QPLLRESET, + QPLLRSVD1(15 downto 0) => B"0000000000000000", + QPLLRSVD2(4 downto 0) => B"11111", + RCALENB => '1', + REFCLKOUTMONITOR => \NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_rxeq_scan is + port ( + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + rxeq_new_txcoeff_req : out STD_LOGIC; + adapt_done_reg_0 : out STD_LOGIC; + new_txcoeff_done_reg_0 : out STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + new_txcoeff_req_reg1_reg_0 : in STD_LOGIC; + rxeq_preset_valid : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \FSM_onehot_fsm_rx_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + rxeq_adapt_done_reg_reg : in STD_LOGIC; + rxeq_adapt_done_reg_reg_0 : in STD_LOGIC; + rxeq_adapt_done_reg_reg_1 : in STD_LOGIC; + rxeq_adapt_done_reg : in STD_LOGIC; + USER_RXEQ_ADAPT_DONE : in STD_LOGIC; + \preset_reg1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \txpreset_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \txcoeff_reg1_reg[17]_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 ); + \fs_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \lf_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_rxeq_scan; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_rxeq_scan is + signal \FSM_onehot_fsm[1]_i_1__4_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[2]_i_1__4_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[3]_i_1__4_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[3]_i_2__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_10__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_11__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_12__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_13__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_1__4_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_2__3_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_3__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_4__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_5__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_6__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_7__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_8__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_9__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[6]_i_2__2_n_0\ : STD_LOGIC; + signal adapt_done : STD_LOGIC; + signal \adapt_done_cnt_i_1__2_n_0\ : STD_LOGIC; + signal \adapt_done_cnt_i_2__2_n_0\ : STD_LOGIC; + signal adapt_done_cnt_reg_n_0 : STD_LOGIC; + signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 1 ); + signal converge_cnt_0 : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal \converge_cnt_reg[12]_i_2__2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_2__2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_2__2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_2__2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2__2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2__2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2__2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2__2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2__2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2__2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2__2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2__2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2__2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2__2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2__2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2__2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2__2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2__2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2__2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2__2_n_3\ : STD_LOGIC; + signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of fs_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of fs_reg1 : signal is "true"; + signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of fs_reg2 : signal is "NO"; + attribute async_reg of fs_reg2 : signal is "true"; + signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of lf_reg1 : signal is "NO"; + attribute async_reg of lf_reg1 : signal is "true"; + signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of lf_reg2 : signal is "NO"; + attribute async_reg of lf_reg2 : signal is "true"; + signal new_txcoeff_done : STD_LOGIC; + signal new_txcoeff_req_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg1 : signal is "NO"; + attribute async_reg of new_txcoeff_req_reg1 : signal is "true"; + signal new_txcoeff_req_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg2 : signal is "NO"; + attribute async_reg of new_txcoeff_req_reg2 : signal is "true"; + signal preset_done : STD_LOGIC; + signal preset_done_1 : STD_LOGIC; + signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of preset_reg1 : signal is "NO"; + attribute async_reg of preset_reg1 : signal is "true"; + signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of preset_reg2 : signal is "NO"; + attribute async_reg of preset_reg2 : signal is "true"; + signal preset_valid_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of preset_valid_reg1 : signal is "NO"; + attribute async_reg of preset_valid_reg1 : signal is "true"; + signal preset_valid_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of preset_valid_reg2 : signal is "NO"; + attribute async_reg of preset_valid_reg2 : signal is "true"; + signal rxeqscan_adapt_done : STD_LOGIC; + signal rxeqscan_new_txcoeff_done : STD_LOGIC; + signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of txcoeff_reg1 : signal is "NO"; + attribute async_reg of txcoeff_reg1 : signal is "true"; + signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of txcoeff_reg2 : signal is "NO"; + attribute async_reg of txcoeff_reg2 : signal is "true"; + signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txpreset_reg1 : signal is "NO"; + attribute async_reg of txpreset_reg1 : signal is "true"; + signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txpreset_reg2 : signal is "NO"; + attribute async_reg of txpreset_reg2 : signal is "true"; + signal \NLW_converge_cnt_reg[21]_i_2__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_converge_cnt_reg[21]_i_2__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_fsm[3]_i_2__2\ : label is "soft_lutpair181"; + attribute SOFT_HLUTNM of \FSM_onehot_fsm[4]_i_4__2\ : label is "soft_lutpair180"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[6]_i_2__2\ : label is "soft_lutpair182"; + attribute SOFT_HLUTNM of \converge_cnt[18]_i_1__2\ : label is "soft_lutpair180"; + attribute SOFT_HLUTNM of \converge_cnt[21]_i_1__2\ : label is "soft_lutpair181"; + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \converge_cnt_reg[12]_i_2__2\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[16]_i_2__2\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[20]_i_2__2\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[21]_i_2__2\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[4]_i_2__2\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[8]_i_2__2\ : label is 35; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \fs_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \fs_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of new_txcoeff_req_reg1_reg : label is std.standard.true; + attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of new_txcoeff_req_reg2_reg : label is std.standard.true; + attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \preset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \preset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \preset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \preset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \preset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \preset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of preset_valid_reg1_reg : label is std.standard.true; + attribute KEEP of preset_valid_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of preset_valid_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of preset_valid_reg2_reg : label is std.standard.true; + attribute KEEP of preset_valid_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of preset_valid_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_new_txcoeff_req_i_1__2\ : label is "soft_lutpair182"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[10]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[11]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[12]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[13]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[14]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[15]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[16]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[17]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[6]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[7]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[8]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[9]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[10]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[11]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[12]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[13]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[14]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[15]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[16]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[17]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[6]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[7]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[8]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[9]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[3]\ : label is "NO"; +begin +\FSM_onehot_fsm[1]_i_1__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F00AFAF0F11AFBB" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => preset_valid_reg2, + I3 => \FSM_onehot_fsm_reg_n_0_[2]\, + I4 => new_txcoeff_req_reg2, + I5 => \FSM_onehot_fsm_reg_n_0_[1]\, + O => \FSM_onehot_fsm[1]_i_1__4_n_0\ + ); +\FSM_onehot_fsm[2]_i_1__4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => preset_valid_reg2, + I1 => \FSM_onehot_fsm_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_reg_n_0_[1]\, + O => \FSM_onehot_fsm[2]_i_1__4_n_0\ + ); +\FSM_onehot_fsm[3]_i_1__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"04FF040404040404" + ) + port map ( + I0 => \FSM_onehot_fsm[3]_i_2__2_n_0\, + I1 => \FSM_onehot_fsm[4]_i_2__3_n_0\, + I2 => \FSM_onehot_fsm[4]_i_3__2_n_0\, + I3 => preset_valid_reg2, + I4 => new_txcoeff_req_reg2, + I5 => \FSM_onehot_fsm_reg_n_0_[1]\, + O => \FSM_onehot_fsm[3]_i_1__4_n_0\ + ); +\FSM_onehot_fsm[3]_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"04FF" + ) + port map ( + I0 => \out\(0), + I1 => \out\(1), + I2 => adapt_done_cnt_reg_n_0, + I3 => \FSM_onehot_fsm_reg_n_0_[3]\, + O => \FSM_onehot_fsm[3]_i_2__2_n_0\ + ); +\FSM_onehot_fsm[4]_i_10__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFBFFFFF" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_13__2_n_0\, + I1 => converge_cnt(2), + I2 => converge_cnt(20), + I3 => converge_cnt(10), + I4 => converge_cnt(0), + O => \FSM_onehot_fsm[4]_i_10__2_n_0\ + ); +\FSM_onehot_fsm[4]_i_11__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => converge_cnt(2), + I1 => converge_cnt(6), + I2 => converge_cnt(8), + I3 => converge_cnt(3), + O => \FSM_onehot_fsm[4]_i_11__2_n_0\ + ); +\FSM_onehot_fsm[4]_i_12__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EFFFFFFF" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_13__2_n_0\, + I1 => converge_cnt(14), + I2 => converge_cnt(10), + I3 => converge_cnt(21), + I4 => converge_cnt(19), + O => \FSM_onehot_fsm[4]_i_12__2_n_0\ + ); +\FSM_onehot_fsm[4]_i_13__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF7F" + ) + port map ( + I0 => converge_cnt(16), + I1 => converge_cnt(11), + I2 => converge_cnt(9), + I3 => converge_cnt(5), + O => \FSM_onehot_fsm[4]_i_13__2_n_0\ + ); +\FSM_onehot_fsm[4]_i_1__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFD0FFD0FFD0" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_2__3_n_0\, + I1 => \FSM_onehot_fsm[4]_i_3__2_n_0\, + I2 => \FSM_onehot_fsm_reg_n_0_[3]\, + I3 => \FSM_onehot_fsm[4]_i_4__2_n_0\, + I4 => \FSM_onehot_fsm_reg_n_0_[4]\, + I5 => new_txcoeff_req_reg2, + O => \FSM_onehot_fsm[4]_i_1__4_n_0\ + ); +\FSM_onehot_fsm[4]_i_2__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFBF" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_5__2_n_0\, + I1 => converge_cnt(17), + I2 => converge_cnt(18), + I3 => converge_cnt(21), + I4 => converge_cnt(8), + I5 => \FSM_onehot_fsm[4]_i_6__2_n_0\, + O => \FSM_onehot_fsm[4]_i_2__3_n_0\ + ); +\FSM_onehot_fsm[4]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000001000000" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_7__2_n_0\, + I1 => converge_cnt(7), + I2 => converge_cnt(1), + I3 => converge_cnt(15), + I4 => converge_cnt(13), + I5 => \FSM_onehot_fsm[4]_i_8__2_n_0\, + O => \FSM_onehot_fsm[4]_i_3__2_n_0\ + ); +\FSM_onehot_fsm[4]_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0400" + ) + port map ( + I0 => \out\(0), + I1 => \out\(1), + I2 => adapt_done_cnt_reg_n_0, + I3 => \FSM_onehot_fsm_reg_n_0_[3]\, + O => \FSM_onehot_fsm[4]_i_4__2_n_0\ + ); +\FSM_onehot_fsm[4]_i_5__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF2" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => converge_cnt(7), + I3 => converge_cnt(1), + O => \FSM_onehot_fsm[4]_i_5__2_n_0\ + ); +\FSM_onehot_fsm[4]_i_6__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFB" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_9__2_n_0\, + I1 => converge_cnt(19), + I2 => converge_cnt(6), + I3 => converge_cnt(3), + I4 => converge_cnt(4), + I5 => \FSM_onehot_fsm[4]_i_10__2_n_0\, + O => \FSM_onehot_fsm[4]_i_6__2_n_0\ + ); +\FSM_onehot_fsm[4]_i_7__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"DFFF" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => converge_cnt(17), + I3 => converge_cnt(18), + O => \FSM_onehot_fsm[4]_i_7__2_n_0\ + ); +\FSM_onehot_fsm[4]_i_8__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_11__2_n_0\, + I1 => converge_cnt(12), + I2 => converge_cnt(20), + I3 => converge_cnt(0), + I4 => converge_cnt(4), + I5 => \FSM_onehot_fsm[4]_i_12__2_n_0\, + O => \FSM_onehot_fsm[4]_i_8__2_n_0\ + ); +\FSM_onehot_fsm[4]_i_9__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFDF" + ) + port map ( + I0 => converge_cnt(15), + I1 => converge_cnt(13), + I2 => converge_cnt(14), + I3 => converge_cnt(12), + O => \FSM_onehot_fsm[4]_i_9__2_n_0\ + ); +\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[1]_i_1__4_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[2]_i_1__4_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[3]_i_1__4_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[4]_i_1__4_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx[2]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40FF4040" + ) + port map ( + I0 => \out\(1), + I1 => Q(0), + I2 => \out\(0), + I3 => preset_done, + I4 => Q(1), + O => D(0) + ); +\FSM_onehot_fsm_rx[5]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F444444444444444" + ) + port map ( + I0 => rxeqscan_new_txcoeff_done, + I1 => Q(3), + I2 => \FSM_onehot_fsm_rx_reg[5]\(2), + I3 => \FSM_onehot_fsm_rx_reg[5]\(0), + I4 => \FSM_onehot_fsm_rx_reg[5]\(1), + I5 => Q(2), + O => D(1) + ); +\FSM_onehot_fsm_rx[6]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFE0E0E0" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => Q(4), + I3 => preset_done, + I4 => Q(1), + I5 => \FSM_onehot_fsm_rx[6]_i_2__2_n_0\, + O => D(2) + ); +\FSM_onehot_fsm_rx[6]_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => rxeqscan_new_txcoeff_done, + I1 => Q(3), + O => \FSM_onehot_fsm_rx[6]_i_2__2_n_0\ + ); +\adapt_done_cnt_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000A0A0AF0F0F8F0" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + I5 => \adapt_done_cnt_i_2__2_n_0\, + O => \adapt_done_cnt_i_1__2_n_0\ + ); +\adapt_done_cnt_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00FF0101" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[3]\, + I1 => \FSM_onehot_fsm_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_reg_n_0_[1]\, + I3 => new_txcoeff_req_reg2, + I4 => \FSM_onehot_fsm_reg_n_0_[4]\, + O => \adapt_done_cnt_i_2__2_n_0\ + ); +adapt_done_cnt_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \adapt_done_cnt_i_1__2_n_0\, + Q => adapt_done_cnt_reg_n_0, + R => RST_CPLLRESET + ); +\adapt_done_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F8000000" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => adapt_done_cnt_reg_n_0, + I3 => new_txcoeff_req_reg2, + I4 => \FSM_onehot_fsm_reg_n_0_[4]\, + O => adapt_done + ); +adapt_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => adapt_done, + Q => rxeqscan_adapt_done, + R => RST_CPLLRESET + ); +\converge_cnt[0]_i_1__5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44444044" + ) + port map ( + I0 => converge_cnt(0), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(0) + ); +\converge_cnt[10]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(10), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(10) + ); +\converge_cnt[11]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(11), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(11) + ); +\converge_cnt[12]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(12), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(12) + ); +\converge_cnt[13]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(13), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(13) + ); +\converge_cnt[14]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(14), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(14) + ); +\converge_cnt[15]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(15), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(15) + ); +\converge_cnt[16]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(16), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(16) + ); +\converge_cnt[17]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(17), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(17) + ); +\converge_cnt[18]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(18), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(18) + ); +\converge_cnt[19]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(19), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(19) + ); +\converge_cnt[1]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(1), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(1) + ); +\converge_cnt[20]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(20), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(20) + ); +\converge_cnt[21]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(21), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(21) + ); +\converge_cnt[2]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(2), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(2) + ); +\converge_cnt[3]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(3), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(3) + ); +\converge_cnt[4]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(4), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(4) + ); +\converge_cnt[5]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(5), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(5) + ); +\converge_cnt[6]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(6), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(6) + ); +\converge_cnt[7]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(7), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(7) + ); +\converge_cnt[8]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(8), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(8) + ); +\converge_cnt[9]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(9), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(9) + ); +\converge_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(0), + Q => converge_cnt(0), + R => RST_CPLLRESET + ); +\converge_cnt_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(10), + Q => converge_cnt(10), + R => RST_CPLLRESET + ); +\converge_cnt_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(11), + Q => converge_cnt(11), + R => RST_CPLLRESET + ); +\converge_cnt_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(12), + Q => converge_cnt(12), + R => RST_CPLLRESET + ); +\converge_cnt_reg[12]_i_2__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[8]_i_2__2_n_0\, + CO(3) => \converge_cnt_reg[12]_i_2__2_n_0\, + CO(2) => \converge_cnt_reg[12]_i_2__2_n_1\, + CO(1) => \converge_cnt_reg[12]_i_2__2_n_2\, + CO(0) => \converge_cnt_reg[12]_i_2__2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(12 downto 9), + S(3 downto 0) => converge_cnt(12 downto 9) + ); +\converge_cnt_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(13), + Q => converge_cnt(13), + R => RST_CPLLRESET + ); +\converge_cnt_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(14), + Q => converge_cnt(14), + R => RST_CPLLRESET + ); +\converge_cnt_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(15), + Q => converge_cnt(15), + R => RST_CPLLRESET + ); +\converge_cnt_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(16), + Q => converge_cnt(16), + R => RST_CPLLRESET + ); +\converge_cnt_reg[16]_i_2__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[12]_i_2__2_n_0\, + CO(3) => \converge_cnt_reg[16]_i_2__2_n_0\, + CO(2) => \converge_cnt_reg[16]_i_2__2_n_1\, + CO(1) => \converge_cnt_reg[16]_i_2__2_n_2\, + CO(0) => \converge_cnt_reg[16]_i_2__2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(16 downto 13), + S(3 downto 0) => converge_cnt(16 downto 13) + ); +\converge_cnt_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(17), + Q => converge_cnt(17), + R => RST_CPLLRESET + ); +\converge_cnt_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(18), + Q => converge_cnt(18), + R => RST_CPLLRESET + ); +\converge_cnt_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(19), + Q => converge_cnt(19), + R => RST_CPLLRESET + ); +\converge_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(1), + Q => converge_cnt(1), + R => RST_CPLLRESET + ); +\converge_cnt_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(20), + Q => converge_cnt(20), + R => RST_CPLLRESET + ); +\converge_cnt_reg[20]_i_2__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[16]_i_2__2_n_0\, + CO(3) => \converge_cnt_reg[20]_i_2__2_n_0\, + CO(2) => \converge_cnt_reg[20]_i_2__2_n_1\, + CO(1) => \converge_cnt_reg[20]_i_2__2_n_2\, + CO(0) => \converge_cnt_reg[20]_i_2__2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(20 downto 17), + S(3 downto 0) => converge_cnt(20 downto 17) + ); +\converge_cnt_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(21), + Q => converge_cnt(21), + R => RST_CPLLRESET + ); +\converge_cnt_reg[21]_i_2__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[20]_i_2__2_n_0\, + CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2__2_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__2_O_UNCONNECTED\(3 downto 1), + O(0) => converge_cnt0(21), + S(3 downto 1) => B"000", + S(0) => converge_cnt(21) + ); +\converge_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(2), + Q => converge_cnt(2), + R => RST_CPLLRESET + ); +\converge_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(3), + Q => converge_cnt(3), + R => RST_CPLLRESET + ); +\converge_cnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(4), + Q => converge_cnt(4), + R => RST_CPLLRESET + ); +\converge_cnt_reg[4]_i_2__2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \converge_cnt_reg[4]_i_2__2_n_0\, + CO(2) => \converge_cnt_reg[4]_i_2__2_n_1\, + CO(1) => \converge_cnt_reg[4]_i_2__2_n_2\, + CO(0) => \converge_cnt_reg[4]_i_2__2_n_3\, + CYINIT => converge_cnt(0), + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(4 downto 1), + S(3 downto 0) => converge_cnt(4 downto 1) + ); +\converge_cnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(5), + Q => converge_cnt(5), + R => RST_CPLLRESET + ); +\converge_cnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(6), + Q => converge_cnt(6), + R => RST_CPLLRESET + ); +\converge_cnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(7), + Q => converge_cnt(7), + R => RST_CPLLRESET + ); +\converge_cnt_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(8), + Q => converge_cnt(8), + R => RST_CPLLRESET + ); +\converge_cnt_reg[8]_i_2__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[4]_i_2__2_n_0\, + CO(3) => \converge_cnt_reg[8]_i_2__2_n_0\, + CO(2) => \converge_cnt_reg[8]_i_2__2_n_1\, + CO(1) => \converge_cnt_reg[8]_i_2__2_n_2\, + CO(0) => \converge_cnt_reg[8]_i_2__2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(8 downto 5), + S(3 downto 0) => converge_cnt(8 downto 5) + ); +\converge_cnt_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(9), + Q => converge_cnt(9), + R => RST_CPLLRESET + ); +\fs_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(0), + Q => fs_reg1(0), + R => RST_CPLLRESET + ); +\fs_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(1), + Q => fs_reg1(1), + R => RST_CPLLRESET + ); +\fs_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(2), + Q => fs_reg1(2), + R => RST_CPLLRESET + ); +\fs_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(3), + Q => fs_reg1(3), + R => RST_CPLLRESET + ); +\fs_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(4), + Q => fs_reg1(4), + R => RST_CPLLRESET + ); +\fs_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(5), + Q => fs_reg1(5), + R => RST_CPLLRESET + ); +\fs_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(0), + Q => fs_reg2(0), + R => RST_CPLLRESET + ); +\fs_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(1), + Q => fs_reg2(1), + R => RST_CPLLRESET + ); +\fs_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(2), + Q => fs_reg2(2), + R => RST_CPLLRESET + ); +\fs_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(3), + Q => fs_reg2(3), + R => RST_CPLLRESET + ); +\fs_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(4), + Q => fs_reg2(4), + R => RST_CPLLRESET + ); +\fs_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(5), + Q => fs_reg2(5), + R => RST_CPLLRESET + ); +\lf_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(0), + Q => lf_reg1(0), + R => RST_CPLLRESET + ); +\lf_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(1), + Q => lf_reg1(1), + R => RST_CPLLRESET + ); +\lf_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(2), + Q => lf_reg1(2), + R => RST_CPLLRESET + ); +\lf_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(3), + Q => lf_reg1(3), + R => RST_CPLLRESET + ); +\lf_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(4), + Q => lf_reg1(4), + R => RST_CPLLRESET + ); +\lf_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(5), + Q => lf_reg1(5), + R => RST_CPLLRESET + ); +\lf_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(0), + Q => lf_reg2(0), + R => RST_CPLLRESET + ); +\lf_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(1), + Q => lf_reg2(1), + R => RST_CPLLRESET + ); +\lf_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(2), + Q => lf_reg2(2), + R => RST_CPLLRESET + ); +\lf_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(3), + Q => lf_reg2(3), + R => RST_CPLLRESET + ); +\lf_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(4), + Q => lf_reg2(4), + R => RST_CPLLRESET + ); +\lf_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(5), + Q => lf_reg2(5), + R => RST_CPLLRESET + ); +\new_txcoeff_done_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => new_txcoeff_req_reg2, + O => new_txcoeff_done + ); +new_txcoeff_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => new_txcoeff_done, + Q => rxeqscan_new_txcoeff_done, + R => RST_CPLLRESET + ); +new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => new_txcoeff_req_reg1_reg_0, + Q => new_txcoeff_req_reg1, + R => RST_CPLLRESET + ); +new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => new_txcoeff_req_reg1, + Q => new_txcoeff_req_reg2, + R => RST_CPLLRESET + ); +\preset_done_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[2]\, + I1 => \FSM_onehot_fsm_reg_n_0_[1]\, + I2 => preset_valid_reg2, + O => preset_done_1 + ); +preset_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_done_1, + Q => preset_done, + R => RST_CPLLRESET + ); +\preset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \preset_reg1_reg[2]_0\(0), + Q => preset_reg1(0), + R => RST_CPLLRESET + ); +\preset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \preset_reg1_reg[2]_0\(1), + Q => preset_reg1(1), + R => RST_CPLLRESET + ); +\preset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \preset_reg1_reg[2]_0\(2), + Q => preset_reg1(2), + R => RST_CPLLRESET + ); +\preset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_reg1(0), + Q => preset_reg2(0), + R => RST_CPLLRESET + ); +\preset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_reg1(1), + Q => preset_reg2(1), + R => RST_CPLLRESET + ); +\preset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_reg1(2), + Q => preset_reg2(2), + R => RST_CPLLRESET + ); +preset_valid_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_valid, + Q => preset_valid_reg1, + R => RST_CPLLRESET + ); +preset_valid_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_valid_reg1, + Q => preset_valid_reg2, + R => RST_CPLLRESET + ); +\rxeq_adapt_done_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A800FFFFA8000000" + ) + port map ( + I0 => rxeqscan_new_txcoeff_done, + I1 => rxeq_adapt_done_reg_reg_1, + I2 => rxeqscan_adapt_done, + I3 => Q(3), + I4 => rxeq_adapt_done_reg, + I5 => USER_RXEQ_ADAPT_DONE, + O => new_txcoeff_done_reg_0 + ); +\rxeq_adapt_done_reg_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF00FF33AA00A800" + ) + port map ( + I0 => rxeqscan_adapt_done, + I1 => rxeq_adapt_done_reg_reg, + I2 => rxeqscan_new_txcoeff_done, + I3 => Q(3), + I4 => rxeq_adapt_done_reg_reg_0, + I5 => rxeq_adapt_done_reg_reg_1, + O => adapt_done_reg_0 + ); +\rxeq_new_txcoeff_req_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => Q(3), + I1 => rxeqscan_new_txcoeff_done, + O => rxeq_new_txcoeff_req + ); +\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(0), + Q => txcoeff_reg1(0), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(10), + Q => txcoeff_reg1(10), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(11), + Q => txcoeff_reg1(11), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(12), + Q => txcoeff_reg1(12), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(13), + Q => txcoeff_reg1(13), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(14), + Q => txcoeff_reg1(14), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(15), + Q => txcoeff_reg1(15), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(16), + Q => txcoeff_reg1(16), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(17), + Q => txcoeff_reg1(17), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(1), + Q => txcoeff_reg1(1), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(2), + Q => txcoeff_reg1(2), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(3), + Q => txcoeff_reg1(3), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(4), + Q => txcoeff_reg1(4), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(5), + Q => txcoeff_reg1(5), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(6), + Q => txcoeff_reg1(6), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(7), + Q => txcoeff_reg1(7), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(8), + Q => txcoeff_reg1(8), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(9), + Q => txcoeff_reg1(9), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(0), + Q => txcoeff_reg2(0), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(10), + Q => txcoeff_reg2(10), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(11), + Q => txcoeff_reg2(11), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(12), + Q => txcoeff_reg2(12), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(13), + Q => txcoeff_reg2(13), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(14), + Q => txcoeff_reg2(14), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(15), + Q => txcoeff_reg2(15), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(16), + Q => txcoeff_reg2(16), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(17), + Q => txcoeff_reg2(17), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(1), + Q => txcoeff_reg2(1), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(2), + Q => txcoeff_reg2(2), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(3), + Q => txcoeff_reg2(3), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(4), + Q => txcoeff_reg2(4), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(5), + Q => txcoeff_reg2(5), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(6), + Q => txcoeff_reg2(6), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(7), + Q => txcoeff_reg2(7), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(8), + Q => txcoeff_reg2(8), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(9), + Q => txcoeff_reg2(9), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(0), + Q => txpreset_reg1(0), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(1), + Q => txpreset_reg1(1), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(2), + Q => txpreset_reg1(2), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(3), + Q => txpreset_reg1(3), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(0), + Q => txpreset_reg2(0), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(1), + Q => txpreset_reg2(1), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(2), + Q => txpreset_reg2(2), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(3), + Q => txpreset_reg2(3), + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_rxeq_scan_55 is + port ( + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + rxeq_new_txcoeff_req : out STD_LOGIC; + adapt_done_reg_0 : out STD_LOGIC; + new_txcoeff_done_reg_0 : out STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + new_txcoeff_req_reg1_reg_0 : in STD_LOGIC; + rxeq_preset_valid : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \FSM_onehot_fsm_rx_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + rxeq_adapt_done_reg_reg : in STD_LOGIC; + rxeq_adapt_done_reg_reg_0 : in STD_LOGIC; + rxeq_adapt_done_reg_reg_1 : in STD_LOGIC; + rxeq_adapt_done_reg : in STD_LOGIC; + USER_RXEQ_ADAPT_DONE : in STD_LOGIC; + \preset_reg1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \txpreset_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \txcoeff_reg1_reg[17]_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 ); + \fs_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \lf_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_rxeq_scan_55 : entity is "pcie_7x_0_rxeq_scan"; +end pcie_7x_0_pcie_7x_0_rxeq_scan_55; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_rxeq_scan_55 is + signal \FSM_onehot_fsm[1]_i_1__3_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[2]_i_1__3_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[3]_i_1__3_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[3]_i_2__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_10__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_11__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_12__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_13__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_1__3_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_2__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_3__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_4__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_5__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_6__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_7__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_8__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_9__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[6]_i_2__1_n_0\ : STD_LOGIC; + signal adapt_done : STD_LOGIC; + signal \adapt_done_cnt_i_1__1_n_0\ : STD_LOGIC; + signal \adapt_done_cnt_i_2__1_n_0\ : STD_LOGIC; + signal adapt_done_cnt_reg_n_0 : STD_LOGIC; + signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 1 ); + signal converge_cnt_0 : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal \converge_cnt_reg[12]_i_2__1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_2__1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_2__1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_2__1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2__1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2__1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2__1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2__1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2__1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2__1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2__1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2__1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2__1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2__1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2__1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2__1_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2__1_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2__1_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2__1_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2__1_n_3\ : STD_LOGIC; + signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of fs_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of fs_reg1 : signal is "true"; + signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of fs_reg2 : signal is "NO"; + attribute async_reg of fs_reg2 : signal is "true"; + signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of lf_reg1 : signal is "NO"; + attribute async_reg of lf_reg1 : signal is "true"; + signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of lf_reg2 : signal is "NO"; + attribute async_reg of lf_reg2 : signal is "true"; + signal new_txcoeff_done : STD_LOGIC; + signal new_txcoeff_req_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg1 : signal is "NO"; + attribute async_reg of new_txcoeff_req_reg1 : signal is "true"; + signal new_txcoeff_req_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg2 : signal is "NO"; + attribute async_reg of new_txcoeff_req_reg2 : signal is "true"; + signal preset_done : STD_LOGIC; + signal preset_done_1 : STD_LOGIC; + signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of preset_reg1 : signal is "NO"; + attribute async_reg of preset_reg1 : signal is "true"; + signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of preset_reg2 : signal is "NO"; + attribute async_reg of preset_reg2 : signal is "true"; + signal preset_valid_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of preset_valid_reg1 : signal is "NO"; + attribute async_reg of preset_valid_reg1 : signal is "true"; + signal preset_valid_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of preset_valid_reg2 : signal is "NO"; + attribute async_reg of preset_valid_reg2 : signal is "true"; + signal rxeqscan_adapt_done : STD_LOGIC; + signal rxeqscan_new_txcoeff_done : STD_LOGIC; + signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of txcoeff_reg1 : signal is "NO"; + attribute async_reg of txcoeff_reg1 : signal is "true"; + signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of txcoeff_reg2 : signal is "NO"; + attribute async_reg of txcoeff_reg2 : signal is "true"; + signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txpreset_reg1 : signal is "NO"; + attribute async_reg of txpreset_reg1 : signal is "true"; + signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txpreset_reg2 : signal is "NO"; + attribute async_reg of txpreset_reg2 : signal is "true"; + signal \NLW_converge_cnt_reg[21]_i_2__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_converge_cnt_reg[21]_i_2__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_fsm[3]_i_2__1\ : label is "soft_lutpair140"; + attribute SOFT_HLUTNM of \FSM_onehot_fsm[4]_i_4__1\ : label is "soft_lutpair139"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[6]_i_2__1\ : label is "soft_lutpair141"; + attribute SOFT_HLUTNM of \converge_cnt[18]_i_1__1\ : label is "soft_lutpair139"; + attribute SOFT_HLUTNM of \converge_cnt[21]_i_1__1\ : label is "soft_lutpair140"; + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \converge_cnt_reg[12]_i_2__1\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[16]_i_2__1\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[20]_i_2__1\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[21]_i_2__1\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[4]_i_2__1\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[8]_i_2__1\ : label is 35; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \fs_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \fs_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of new_txcoeff_req_reg1_reg : label is std.standard.true; + attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of new_txcoeff_req_reg2_reg : label is std.standard.true; + attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \preset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \preset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \preset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \preset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \preset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \preset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of preset_valid_reg1_reg : label is std.standard.true; + attribute KEEP of preset_valid_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of preset_valid_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of preset_valid_reg2_reg : label is std.standard.true; + attribute KEEP of preset_valid_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of preset_valid_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_new_txcoeff_req_i_1__1\ : label is "soft_lutpair141"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[10]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[11]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[12]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[13]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[14]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[15]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[16]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[17]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[6]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[7]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[8]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[9]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[10]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[11]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[12]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[13]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[14]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[15]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[16]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[17]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[6]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[7]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[8]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[9]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[3]\ : label is "NO"; +begin +\FSM_onehot_fsm[1]_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F00AFAF0F11AFBB" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => preset_valid_reg2, + I3 => \FSM_onehot_fsm_reg_n_0_[2]\, + I4 => new_txcoeff_req_reg2, + I5 => \FSM_onehot_fsm_reg_n_0_[1]\, + O => \FSM_onehot_fsm[1]_i_1__3_n_0\ + ); +\FSM_onehot_fsm[2]_i_1__3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => preset_valid_reg2, + I1 => \FSM_onehot_fsm_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_reg_n_0_[1]\, + O => \FSM_onehot_fsm[2]_i_1__3_n_0\ + ); +\FSM_onehot_fsm[3]_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"04FF040404040404" + ) + port map ( + I0 => \FSM_onehot_fsm[3]_i_2__1_n_0\, + I1 => \FSM_onehot_fsm[4]_i_2__2_n_0\, + I2 => \FSM_onehot_fsm[4]_i_3__1_n_0\, + I3 => preset_valid_reg2, + I4 => new_txcoeff_req_reg2, + I5 => \FSM_onehot_fsm_reg_n_0_[1]\, + O => \FSM_onehot_fsm[3]_i_1__3_n_0\ + ); +\FSM_onehot_fsm[3]_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"04FF" + ) + port map ( + I0 => \out\(0), + I1 => \out\(1), + I2 => adapt_done_cnt_reg_n_0, + I3 => \FSM_onehot_fsm_reg_n_0_[3]\, + O => \FSM_onehot_fsm[3]_i_2__1_n_0\ + ); +\FSM_onehot_fsm[4]_i_10__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFBFFFFF" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_13__1_n_0\, + I1 => converge_cnt(2), + I2 => converge_cnt(20), + I3 => converge_cnt(10), + I4 => converge_cnt(0), + O => \FSM_onehot_fsm[4]_i_10__1_n_0\ + ); +\FSM_onehot_fsm[4]_i_11__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => converge_cnt(2), + I1 => converge_cnt(6), + I2 => converge_cnt(8), + I3 => converge_cnt(3), + O => \FSM_onehot_fsm[4]_i_11__1_n_0\ + ); +\FSM_onehot_fsm[4]_i_12__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EFFFFFFF" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_13__1_n_0\, + I1 => converge_cnt(14), + I2 => converge_cnt(10), + I3 => converge_cnt(21), + I4 => converge_cnt(19), + O => \FSM_onehot_fsm[4]_i_12__1_n_0\ + ); +\FSM_onehot_fsm[4]_i_13__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF7F" + ) + port map ( + I0 => converge_cnt(16), + I1 => converge_cnt(11), + I2 => converge_cnt(9), + I3 => converge_cnt(5), + O => \FSM_onehot_fsm[4]_i_13__1_n_0\ + ); +\FSM_onehot_fsm[4]_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFD0FFD0FFD0" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_2__2_n_0\, + I1 => \FSM_onehot_fsm[4]_i_3__1_n_0\, + I2 => \FSM_onehot_fsm_reg_n_0_[3]\, + I3 => \FSM_onehot_fsm[4]_i_4__1_n_0\, + I4 => \FSM_onehot_fsm_reg_n_0_[4]\, + I5 => new_txcoeff_req_reg2, + O => \FSM_onehot_fsm[4]_i_1__3_n_0\ + ); +\FSM_onehot_fsm[4]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFBF" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_5__1_n_0\, + I1 => converge_cnt(17), + I2 => converge_cnt(18), + I3 => converge_cnt(21), + I4 => converge_cnt(8), + I5 => \FSM_onehot_fsm[4]_i_6__1_n_0\, + O => \FSM_onehot_fsm[4]_i_2__2_n_0\ + ); +\FSM_onehot_fsm[4]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000001000000" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_7__1_n_0\, + I1 => converge_cnt(7), + I2 => converge_cnt(1), + I3 => converge_cnt(15), + I4 => converge_cnt(13), + I5 => \FSM_onehot_fsm[4]_i_8__1_n_0\, + O => \FSM_onehot_fsm[4]_i_3__1_n_0\ + ); +\FSM_onehot_fsm[4]_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0400" + ) + port map ( + I0 => \out\(0), + I1 => \out\(1), + I2 => adapt_done_cnt_reg_n_0, + I3 => \FSM_onehot_fsm_reg_n_0_[3]\, + O => \FSM_onehot_fsm[4]_i_4__1_n_0\ + ); +\FSM_onehot_fsm[4]_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF2" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => converge_cnt(7), + I3 => converge_cnt(1), + O => \FSM_onehot_fsm[4]_i_5__1_n_0\ + ); +\FSM_onehot_fsm[4]_i_6__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFB" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_9__1_n_0\, + I1 => converge_cnt(19), + I2 => converge_cnt(6), + I3 => converge_cnt(3), + I4 => converge_cnt(4), + I5 => \FSM_onehot_fsm[4]_i_10__1_n_0\, + O => \FSM_onehot_fsm[4]_i_6__1_n_0\ + ); +\FSM_onehot_fsm[4]_i_7__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"DFFF" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => converge_cnt(17), + I3 => converge_cnt(18), + O => \FSM_onehot_fsm[4]_i_7__1_n_0\ + ); +\FSM_onehot_fsm[4]_i_8__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_11__1_n_0\, + I1 => converge_cnt(12), + I2 => converge_cnt(20), + I3 => converge_cnt(0), + I4 => converge_cnt(4), + I5 => \FSM_onehot_fsm[4]_i_12__1_n_0\, + O => \FSM_onehot_fsm[4]_i_8__1_n_0\ + ); +\FSM_onehot_fsm[4]_i_9__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFDF" + ) + port map ( + I0 => converge_cnt(15), + I1 => converge_cnt(13), + I2 => converge_cnt(14), + I3 => converge_cnt(12), + O => \FSM_onehot_fsm[4]_i_9__1_n_0\ + ); +\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[1]_i_1__3_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[2]_i_1__3_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[3]_i_1__3_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[4]_i_1__3_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx[2]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40FF4040" + ) + port map ( + I0 => \out\(1), + I1 => Q(0), + I2 => \out\(0), + I3 => preset_done, + I4 => Q(1), + O => D(0) + ); +\FSM_onehot_fsm_rx[5]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F444444444444444" + ) + port map ( + I0 => rxeqscan_new_txcoeff_done, + I1 => Q(3), + I2 => \FSM_onehot_fsm_rx_reg[5]\(2), + I3 => \FSM_onehot_fsm_rx_reg[5]\(0), + I4 => \FSM_onehot_fsm_rx_reg[5]\(1), + I5 => Q(2), + O => D(1) + ); +\FSM_onehot_fsm_rx[6]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFE0E0E0" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => Q(4), + I3 => preset_done, + I4 => Q(1), + I5 => \FSM_onehot_fsm_rx[6]_i_2__1_n_0\, + O => D(2) + ); +\FSM_onehot_fsm_rx[6]_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => rxeqscan_new_txcoeff_done, + I1 => Q(3), + O => \FSM_onehot_fsm_rx[6]_i_2__1_n_0\ + ); +\adapt_done_cnt_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000A0A0AF0F0F8F0" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + I5 => \adapt_done_cnt_i_2__1_n_0\, + O => \adapt_done_cnt_i_1__1_n_0\ + ); +\adapt_done_cnt_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00FF0101" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[3]\, + I1 => \FSM_onehot_fsm_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_reg_n_0_[1]\, + I3 => new_txcoeff_req_reg2, + I4 => \FSM_onehot_fsm_reg_n_0_[4]\, + O => \adapt_done_cnt_i_2__1_n_0\ + ); +adapt_done_cnt_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \adapt_done_cnt_i_1__1_n_0\, + Q => adapt_done_cnt_reg_n_0, + R => RST_CPLLRESET + ); +\adapt_done_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F8000000" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => adapt_done_cnt_reg_n_0, + I3 => new_txcoeff_req_reg2, + I4 => \FSM_onehot_fsm_reg_n_0_[4]\, + O => adapt_done + ); +adapt_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => adapt_done, + Q => rxeqscan_adapt_done, + R => RST_CPLLRESET + ); +\converge_cnt[0]_i_1__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44444044" + ) + port map ( + I0 => converge_cnt(0), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(0) + ); +\converge_cnt[10]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(10), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(10) + ); +\converge_cnt[11]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(11), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(11) + ); +\converge_cnt[12]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(12), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(12) + ); +\converge_cnt[13]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(13), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(13) + ); +\converge_cnt[14]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(14), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(14) + ); +\converge_cnt[15]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(15), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(15) + ); +\converge_cnt[16]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(16), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(16) + ); +\converge_cnt[17]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(17), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(17) + ); +\converge_cnt[18]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(18), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(18) + ); +\converge_cnt[19]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(19), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(19) + ); +\converge_cnt[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(1), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(1) + ); +\converge_cnt[20]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(20), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(20) + ); +\converge_cnt[21]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(21), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(21) + ); +\converge_cnt[2]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(2), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(2) + ); +\converge_cnt[3]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(3), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(3) + ); +\converge_cnt[4]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(4), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(4) + ); +\converge_cnt[5]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(5), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(5) + ); +\converge_cnt[6]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(6), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(6) + ); +\converge_cnt[7]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(7), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(7) + ); +\converge_cnt[8]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(8), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(8) + ); +\converge_cnt[9]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(9), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(9) + ); +\converge_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(0), + Q => converge_cnt(0), + R => RST_CPLLRESET + ); +\converge_cnt_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(10), + Q => converge_cnt(10), + R => RST_CPLLRESET + ); +\converge_cnt_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(11), + Q => converge_cnt(11), + R => RST_CPLLRESET + ); +\converge_cnt_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(12), + Q => converge_cnt(12), + R => RST_CPLLRESET + ); +\converge_cnt_reg[12]_i_2__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[8]_i_2__1_n_0\, + CO(3) => \converge_cnt_reg[12]_i_2__1_n_0\, + CO(2) => \converge_cnt_reg[12]_i_2__1_n_1\, + CO(1) => \converge_cnt_reg[12]_i_2__1_n_2\, + CO(0) => \converge_cnt_reg[12]_i_2__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(12 downto 9), + S(3 downto 0) => converge_cnt(12 downto 9) + ); +\converge_cnt_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(13), + Q => converge_cnt(13), + R => RST_CPLLRESET + ); +\converge_cnt_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(14), + Q => converge_cnt(14), + R => RST_CPLLRESET + ); +\converge_cnt_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(15), + Q => converge_cnt(15), + R => RST_CPLLRESET + ); +\converge_cnt_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(16), + Q => converge_cnt(16), + R => RST_CPLLRESET + ); +\converge_cnt_reg[16]_i_2__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[12]_i_2__1_n_0\, + CO(3) => \converge_cnt_reg[16]_i_2__1_n_0\, + CO(2) => \converge_cnt_reg[16]_i_2__1_n_1\, + CO(1) => \converge_cnt_reg[16]_i_2__1_n_2\, + CO(0) => \converge_cnt_reg[16]_i_2__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(16 downto 13), + S(3 downto 0) => converge_cnt(16 downto 13) + ); +\converge_cnt_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(17), + Q => converge_cnt(17), + R => RST_CPLLRESET + ); +\converge_cnt_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(18), + Q => converge_cnt(18), + R => RST_CPLLRESET + ); +\converge_cnt_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(19), + Q => converge_cnt(19), + R => RST_CPLLRESET + ); +\converge_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(1), + Q => converge_cnt(1), + R => RST_CPLLRESET + ); +\converge_cnt_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(20), + Q => converge_cnt(20), + R => RST_CPLLRESET + ); +\converge_cnt_reg[20]_i_2__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[16]_i_2__1_n_0\, + CO(3) => \converge_cnt_reg[20]_i_2__1_n_0\, + CO(2) => \converge_cnt_reg[20]_i_2__1_n_1\, + CO(1) => \converge_cnt_reg[20]_i_2__1_n_2\, + CO(0) => \converge_cnt_reg[20]_i_2__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(20 downto 17), + S(3 downto 0) => converge_cnt(20 downto 17) + ); +\converge_cnt_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(21), + Q => converge_cnt(21), + R => RST_CPLLRESET + ); +\converge_cnt_reg[21]_i_2__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[20]_i_2__1_n_0\, + CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2__1_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__1_O_UNCONNECTED\(3 downto 1), + O(0) => converge_cnt0(21), + S(3 downto 1) => B"000", + S(0) => converge_cnt(21) + ); +\converge_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(2), + Q => converge_cnt(2), + R => RST_CPLLRESET + ); +\converge_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(3), + Q => converge_cnt(3), + R => RST_CPLLRESET + ); +\converge_cnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(4), + Q => converge_cnt(4), + R => RST_CPLLRESET + ); +\converge_cnt_reg[4]_i_2__1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \converge_cnt_reg[4]_i_2__1_n_0\, + CO(2) => \converge_cnt_reg[4]_i_2__1_n_1\, + CO(1) => \converge_cnt_reg[4]_i_2__1_n_2\, + CO(0) => \converge_cnt_reg[4]_i_2__1_n_3\, + CYINIT => converge_cnt(0), + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(4 downto 1), + S(3 downto 0) => converge_cnt(4 downto 1) + ); +\converge_cnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(5), + Q => converge_cnt(5), + R => RST_CPLLRESET + ); +\converge_cnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(6), + Q => converge_cnt(6), + R => RST_CPLLRESET + ); +\converge_cnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(7), + Q => converge_cnt(7), + R => RST_CPLLRESET + ); +\converge_cnt_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(8), + Q => converge_cnt(8), + R => RST_CPLLRESET + ); +\converge_cnt_reg[8]_i_2__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[4]_i_2__1_n_0\, + CO(3) => \converge_cnt_reg[8]_i_2__1_n_0\, + CO(2) => \converge_cnt_reg[8]_i_2__1_n_1\, + CO(1) => \converge_cnt_reg[8]_i_2__1_n_2\, + CO(0) => \converge_cnt_reg[8]_i_2__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(8 downto 5), + S(3 downto 0) => converge_cnt(8 downto 5) + ); +\converge_cnt_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(9), + Q => converge_cnt(9), + R => RST_CPLLRESET + ); +\fs_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(0), + Q => fs_reg1(0), + R => RST_CPLLRESET + ); +\fs_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(1), + Q => fs_reg1(1), + R => RST_CPLLRESET + ); +\fs_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(2), + Q => fs_reg1(2), + R => RST_CPLLRESET + ); +\fs_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(3), + Q => fs_reg1(3), + R => RST_CPLLRESET + ); +\fs_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(4), + Q => fs_reg1(4), + R => RST_CPLLRESET + ); +\fs_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(5), + Q => fs_reg1(5), + R => RST_CPLLRESET + ); +\fs_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(0), + Q => fs_reg2(0), + R => RST_CPLLRESET + ); +\fs_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(1), + Q => fs_reg2(1), + R => RST_CPLLRESET + ); +\fs_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(2), + Q => fs_reg2(2), + R => RST_CPLLRESET + ); +\fs_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(3), + Q => fs_reg2(3), + R => RST_CPLLRESET + ); +\fs_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(4), + Q => fs_reg2(4), + R => RST_CPLLRESET + ); +\fs_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(5), + Q => fs_reg2(5), + R => RST_CPLLRESET + ); +\lf_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(0), + Q => lf_reg1(0), + R => RST_CPLLRESET + ); +\lf_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(1), + Q => lf_reg1(1), + R => RST_CPLLRESET + ); +\lf_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(2), + Q => lf_reg1(2), + R => RST_CPLLRESET + ); +\lf_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(3), + Q => lf_reg1(3), + R => RST_CPLLRESET + ); +\lf_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(4), + Q => lf_reg1(4), + R => RST_CPLLRESET + ); +\lf_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(5), + Q => lf_reg1(5), + R => RST_CPLLRESET + ); +\lf_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(0), + Q => lf_reg2(0), + R => RST_CPLLRESET + ); +\lf_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(1), + Q => lf_reg2(1), + R => RST_CPLLRESET + ); +\lf_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(2), + Q => lf_reg2(2), + R => RST_CPLLRESET + ); +\lf_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(3), + Q => lf_reg2(3), + R => RST_CPLLRESET + ); +\lf_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(4), + Q => lf_reg2(4), + R => RST_CPLLRESET + ); +\lf_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(5), + Q => lf_reg2(5), + R => RST_CPLLRESET + ); +\new_txcoeff_done_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => new_txcoeff_req_reg2, + O => new_txcoeff_done + ); +new_txcoeff_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => new_txcoeff_done, + Q => rxeqscan_new_txcoeff_done, + R => RST_CPLLRESET + ); +new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => new_txcoeff_req_reg1_reg_0, + Q => new_txcoeff_req_reg1, + R => RST_CPLLRESET + ); +new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => new_txcoeff_req_reg1, + Q => new_txcoeff_req_reg2, + R => RST_CPLLRESET + ); +\preset_done_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[2]\, + I1 => \FSM_onehot_fsm_reg_n_0_[1]\, + I2 => preset_valid_reg2, + O => preset_done_1 + ); +preset_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_done_1, + Q => preset_done, + R => RST_CPLLRESET + ); +\preset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \preset_reg1_reg[2]_0\(0), + Q => preset_reg1(0), + R => RST_CPLLRESET + ); +\preset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \preset_reg1_reg[2]_0\(1), + Q => preset_reg1(1), + R => RST_CPLLRESET + ); +\preset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \preset_reg1_reg[2]_0\(2), + Q => preset_reg1(2), + R => RST_CPLLRESET + ); +\preset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_reg1(0), + Q => preset_reg2(0), + R => RST_CPLLRESET + ); +\preset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_reg1(1), + Q => preset_reg2(1), + R => RST_CPLLRESET + ); +\preset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_reg1(2), + Q => preset_reg2(2), + R => RST_CPLLRESET + ); +preset_valid_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_valid, + Q => preset_valid_reg1, + R => RST_CPLLRESET + ); +preset_valid_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_valid_reg1, + Q => preset_valid_reg2, + R => RST_CPLLRESET + ); +\rxeq_adapt_done_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A800FFFFA8000000" + ) + port map ( + I0 => rxeqscan_new_txcoeff_done, + I1 => rxeq_adapt_done_reg_reg_1, + I2 => rxeqscan_adapt_done, + I3 => Q(3), + I4 => rxeq_adapt_done_reg, + I5 => USER_RXEQ_ADAPT_DONE, + O => new_txcoeff_done_reg_0 + ); +\rxeq_adapt_done_reg_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF00FF33AA00A800" + ) + port map ( + I0 => rxeqscan_adapt_done, + I1 => rxeq_adapt_done_reg_reg, + I2 => rxeqscan_new_txcoeff_done, + I3 => Q(3), + I4 => rxeq_adapt_done_reg_reg_0, + I5 => rxeq_adapt_done_reg_reg_1, + O => adapt_done_reg_0 + ); +\rxeq_new_txcoeff_req_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => Q(3), + I1 => rxeqscan_new_txcoeff_done, + O => rxeq_new_txcoeff_req + ); +\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(0), + Q => txcoeff_reg1(0), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(10), + Q => txcoeff_reg1(10), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(11), + Q => txcoeff_reg1(11), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(12), + Q => txcoeff_reg1(12), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(13), + Q => txcoeff_reg1(13), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(14), + Q => txcoeff_reg1(14), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(15), + Q => txcoeff_reg1(15), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(16), + Q => txcoeff_reg1(16), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(17), + Q => txcoeff_reg1(17), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(1), + Q => txcoeff_reg1(1), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(2), + Q => txcoeff_reg1(2), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(3), + Q => txcoeff_reg1(3), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(4), + Q => txcoeff_reg1(4), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(5), + Q => txcoeff_reg1(5), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(6), + Q => txcoeff_reg1(6), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(7), + Q => txcoeff_reg1(7), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(8), + Q => txcoeff_reg1(8), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(9), + Q => txcoeff_reg1(9), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(0), + Q => txcoeff_reg2(0), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(10), + Q => txcoeff_reg2(10), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(11), + Q => txcoeff_reg2(11), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(12), + Q => txcoeff_reg2(12), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(13), + Q => txcoeff_reg2(13), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(14), + Q => txcoeff_reg2(14), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(15), + Q => txcoeff_reg2(15), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(16), + Q => txcoeff_reg2(16), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(17), + Q => txcoeff_reg2(17), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(1), + Q => txcoeff_reg2(1), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(2), + Q => txcoeff_reg2(2), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(3), + Q => txcoeff_reg2(3), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(4), + Q => txcoeff_reg2(4), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(5), + Q => txcoeff_reg2(5), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(6), + Q => txcoeff_reg2(6), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(7), + Q => txcoeff_reg2(7), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(8), + Q => txcoeff_reg2(8), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(9), + Q => txcoeff_reg2(9), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(0), + Q => txpreset_reg1(0), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(1), + Q => txpreset_reg1(1), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(2), + Q => txpreset_reg1(2), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(3), + Q => txpreset_reg1(3), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(0), + Q => txpreset_reg2(0), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(1), + Q => txpreset_reg2(1), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(2), + Q => txpreset_reg2(2), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(3), + Q => txpreset_reg2(3), + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_rxeq_scan_57 is + port ( + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + rxeq_new_txcoeff_req : out STD_LOGIC; + adapt_done_reg_0 : out STD_LOGIC; + new_txcoeff_done_reg_0 : out STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + new_txcoeff_req_reg1_reg_0 : in STD_LOGIC; + rxeq_preset_valid : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \FSM_onehot_fsm_rx_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + rxeq_adapt_done_reg_reg : in STD_LOGIC; + rxeq_adapt_done_reg_reg_0 : in STD_LOGIC; + rxeq_adapt_done_reg_reg_1 : in STD_LOGIC; + rxeq_adapt_done_reg : in STD_LOGIC; + USER_RXEQ_ADAPT_DONE : in STD_LOGIC; + \preset_reg1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \txpreset_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \txcoeff_reg1_reg[17]_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 ); + \fs_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \lf_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_rxeq_scan_57 : entity is "pcie_7x_0_rxeq_scan"; +end pcie_7x_0_pcie_7x_0_rxeq_scan_57; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_rxeq_scan_57 is + signal \FSM_onehot_fsm[1]_i_1__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[2]_i_1__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[3]_i_1__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[3]_i_2__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_10__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_11__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_12__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_13__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_1__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_2__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_3__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_4__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_5__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_6__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_7__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_8__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_9__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[6]_i_2__0_n_0\ : STD_LOGIC; + signal adapt_done : STD_LOGIC; + signal \adapt_done_cnt_i_1__0_n_0\ : STD_LOGIC; + signal \adapt_done_cnt_i_2__0_n_0\ : STD_LOGIC; + signal adapt_done_cnt_reg_n_0 : STD_LOGIC; + signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 1 ); + signal converge_cnt_0 : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal \converge_cnt_reg[12]_i_2__0_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_2__0_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_2__0_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_2__0_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2__0_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2__0_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2__0_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2__0_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2__0_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2__0_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2__0_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2__0_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2__0_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2__0_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2__0_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2__0_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2__0_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2__0_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2__0_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2__0_n_3\ : STD_LOGIC; + signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of fs_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of fs_reg1 : signal is "true"; + signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of fs_reg2 : signal is "NO"; + attribute async_reg of fs_reg2 : signal is "true"; + signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of lf_reg1 : signal is "NO"; + attribute async_reg of lf_reg1 : signal is "true"; + signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of lf_reg2 : signal is "NO"; + attribute async_reg of lf_reg2 : signal is "true"; + signal new_txcoeff_done : STD_LOGIC; + signal new_txcoeff_req_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg1 : signal is "NO"; + attribute async_reg of new_txcoeff_req_reg1 : signal is "true"; + signal new_txcoeff_req_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg2 : signal is "NO"; + attribute async_reg of new_txcoeff_req_reg2 : signal is "true"; + signal preset_done : STD_LOGIC; + signal preset_done_1 : STD_LOGIC; + signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of preset_reg1 : signal is "NO"; + attribute async_reg of preset_reg1 : signal is "true"; + signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of preset_reg2 : signal is "NO"; + attribute async_reg of preset_reg2 : signal is "true"; + signal preset_valid_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of preset_valid_reg1 : signal is "NO"; + attribute async_reg of preset_valid_reg1 : signal is "true"; + signal preset_valid_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of preset_valid_reg2 : signal is "NO"; + attribute async_reg of preset_valid_reg2 : signal is "true"; + signal rxeqscan_adapt_done : STD_LOGIC; + signal rxeqscan_new_txcoeff_done : STD_LOGIC; + signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of txcoeff_reg1 : signal is "NO"; + attribute async_reg of txcoeff_reg1 : signal is "true"; + signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of txcoeff_reg2 : signal is "NO"; + attribute async_reg of txcoeff_reg2 : signal is "true"; + signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txpreset_reg1 : signal is "NO"; + attribute async_reg of txpreset_reg1 : signal is "true"; + signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txpreset_reg2 : signal is "NO"; + attribute async_reg of txpreset_reg2 : signal is "true"; + signal \NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_fsm[3]_i_2__0\ : label is "soft_lutpair98"; + attribute SOFT_HLUTNM of \FSM_onehot_fsm[4]_i_4__0\ : label is "soft_lutpair97"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[6]_i_2__0\ : label is "soft_lutpair99"; + attribute SOFT_HLUTNM of \converge_cnt[18]_i_1__0\ : label is "soft_lutpair97"; + attribute SOFT_HLUTNM of \converge_cnt[21]_i_1__0\ : label is "soft_lutpair98"; + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \converge_cnt_reg[12]_i_2__0\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[16]_i_2__0\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[20]_i_2__0\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[21]_i_2__0\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[4]_i_2__0\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[8]_i_2__0\ : label is 35; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \fs_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \fs_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of new_txcoeff_req_reg1_reg : label is std.standard.true; + attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of new_txcoeff_req_reg2_reg : label is std.standard.true; + attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \preset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \preset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \preset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \preset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \preset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \preset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of preset_valid_reg1_reg : label is std.standard.true; + attribute KEEP of preset_valid_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of preset_valid_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of preset_valid_reg2_reg : label is std.standard.true; + attribute KEEP of preset_valid_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of preset_valid_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_new_txcoeff_req_i_1__0\ : label is "soft_lutpair99"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[10]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[11]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[12]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[13]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[14]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[15]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[16]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[17]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[6]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[7]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[8]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[9]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[10]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[11]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[12]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[13]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[14]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[15]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[16]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[17]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[6]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[7]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[8]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[9]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[3]\ : label is "NO"; +begin +\FSM_onehot_fsm[1]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F00AFAF0F11AFBB" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => preset_valid_reg2, + I3 => \FSM_onehot_fsm_reg_n_0_[2]\, + I4 => new_txcoeff_req_reg2, + I5 => \FSM_onehot_fsm_reg_n_0_[1]\, + O => \FSM_onehot_fsm[1]_i_1__2_n_0\ + ); +\FSM_onehot_fsm[2]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => preset_valid_reg2, + I1 => \FSM_onehot_fsm_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_reg_n_0_[1]\, + O => \FSM_onehot_fsm[2]_i_1__2_n_0\ + ); +\FSM_onehot_fsm[3]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"04FF040404040404" + ) + port map ( + I0 => \FSM_onehot_fsm[3]_i_2__0_n_0\, + I1 => \FSM_onehot_fsm[4]_i_2__1_n_0\, + I2 => \FSM_onehot_fsm[4]_i_3__0_n_0\, + I3 => preset_valid_reg2, + I4 => new_txcoeff_req_reg2, + I5 => \FSM_onehot_fsm_reg_n_0_[1]\, + O => \FSM_onehot_fsm[3]_i_1__2_n_0\ + ); +\FSM_onehot_fsm[3]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"04FF" + ) + port map ( + I0 => \out\(0), + I1 => \out\(1), + I2 => adapt_done_cnt_reg_n_0, + I3 => \FSM_onehot_fsm_reg_n_0_[3]\, + O => \FSM_onehot_fsm[3]_i_2__0_n_0\ + ); +\FSM_onehot_fsm[4]_i_10__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFBFFFFF" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_13__0_n_0\, + I1 => converge_cnt(2), + I2 => converge_cnt(20), + I3 => converge_cnt(10), + I4 => converge_cnt(0), + O => \FSM_onehot_fsm[4]_i_10__0_n_0\ + ); +\FSM_onehot_fsm[4]_i_11__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => converge_cnt(2), + I1 => converge_cnt(6), + I2 => converge_cnt(8), + I3 => converge_cnt(3), + O => \FSM_onehot_fsm[4]_i_11__0_n_0\ + ); +\FSM_onehot_fsm[4]_i_12__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EFFFFFFF" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_13__0_n_0\, + I1 => converge_cnt(14), + I2 => converge_cnt(10), + I3 => converge_cnt(21), + I4 => converge_cnt(19), + O => \FSM_onehot_fsm[4]_i_12__0_n_0\ + ); +\FSM_onehot_fsm[4]_i_13__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF7F" + ) + port map ( + I0 => converge_cnt(16), + I1 => converge_cnt(11), + I2 => converge_cnt(9), + I3 => converge_cnt(5), + O => \FSM_onehot_fsm[4]_i_13__0_n_0\ + ); +\FSM_onehot_fsm[4]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFD0FFD0FFD0" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_2__1_n_0\, + I1 => \FSM_onehot_fsm[4]_i_3__0_n_0\, + I2 => \FSM_onehot_fsm_reg_n_0_[3]\, + I3 => \FSM_onehot_fsm[4]_i_4__0_n_0\, + I4 => \FSM_onehot_fsm_reg_n_0_[4]\, + I5 => new_txcoeff_req_reg2, + O => \FSM_onehot_fsm[4]_i_1__2_n_0\ + ); +\FSM_onehot_fsm[4]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFBF" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_5__0_n_0\, + I1 => converge_cnt(17), + I2 => converge_cnt(18), + I3 => converge_cnt(21), + I4 => converge_cnt(8), + I5 => \FSM_onehot_fsm[4]_i_6__0_n_0\, + O => \FSM_onehot_fsm[4]_i_2__1_n_0\ + ); +\FSM_onehot_fsm[4]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000001000000" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_7__0_n_0\, + I1 => converge_cnt(7), + I2 => converge_cnt(1), + I3 => converge_cnt(15), + I4 => converge_cnt(13), + I5 => \FSM_onehot_fsm[4]_i_8__0_n_0\, + O => \FSM_onehot_fsm[4]_i_3__0_n_0\ + ); +\FSM_onehot_fsm[4]_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0400" + ) + port map ( + I0 => \out\(0), + I1 => \out\(1), + I2 => adapt_done_cnt_reg_n_0, + I3 => \FSM_onehot_fsm_reg_n_0_[3]\, + O => \FSM_onehot_fsm[4]_i_4__0_n_0\ + ); +\FSM_onehot_fsm[4]_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF2" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => converge_cnt(7), + I3 => converge_cnt(1), + O => \FSM_onehot_fsm[4]_i_5__0_n_0\ + ); +\FSM_onehot_fsm[4]_i_6__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFB" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_9__0_n_0\, + I1 => converge_cnt(19), + I2 => converge_cnt(6), + I3 => converge_cnt(3), + I4 => converge_cnt(4), + I5 => \FSM_onehot_fsm[4]_i_10__0_n_0\, + O => \FSM_onehot_fsm[4]_i_6__0_n_0\ + ); +\FSM_onehot_fsm[4]_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"DFFF" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => converge_cnt(17), + I3 => converge_cnt(18), + O => \FSM_onehot_fsm[4]_i_7__0_n_0\ + ); +\FSM_onehot_fsm[4]_i_8__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_11__0_n_0\, + I1 => converge_cnt(12), + I2 => converge_cnt(20), + I3 => converge_cnt(0), + I4 => converge_cnt(4), + I5 => \FSM_onehot_fsm[4]_i_12__0_n_0\, + O => \FSM_onehot_fsm[4]_i_8__0_n_0\ + ); +\FSM_onehot_fsm[4]_i_9__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFDF" + ) + port map ( + I0 => converge_cnt(15), + I1 => converge_cnt(13), + I2 => converge_cnt(14), + I3 => converge_cnt(12), + O => \FSM_onehot_fsm[4]_i_9__0_n_0\ + ); +\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[1]_i_1__2_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[2]_i_1__2_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[3]_i_1__2_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[4]_i_1__2_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx[2]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40FF4040" + ) + port map ( + I0 => \out\(1), + I1 => Q(0), + I2 => \out\(0), + I3 => preset_done, + I4 => Q(1), + O => D(0) + ); +\FSM_onehot_fsm_rx[5]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F444444444444444" + ) + port map ( + I0 => rxeqscan_new_txcoeff_done, + I1 => Q(3), + I2 => \FSM_onehot_fsm_rx_reg[5]\(2), + I3 => \FSM_onehot_fsm_rx_reg[5]\(0), + I4 => \FSM_onehot_fsm_rx_reg[5]\(1), + I5 => Q(2), + O => D(1) + ); +\FSM_onehot_fsm_rx[6]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFE0E0E0" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => Q(4), + I3 => preset_done, + I4 => Q(1), + I5 => \FSM_onehot_fsm_rx[6]_i_2__0_n_0\, + O => D(2) + ); +\FSM_onehot_fsm_rx[6]_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => rxeqscan_new_txcoeff_done, + I1 => Q(3), + O => \FSM_onehot_fsm_rx[6]_i_2__0_n_0\ + ); +\adapt_done_cnt_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000A0A0AF0F0F8F0" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + I5 => \adapt_done_cnt_i_2__0_n_0\, + O => \adapt_done_cnt_i_1__0_n_0\ + ); +\adapt_done_cnt_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00FF0101" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[3]\, + I1 => \FSM_onehot_fsm_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_reg_n_0_[1]\, + I3 => new_txcoeff_req_reg2, + I4 => \FSM_onehot_fsm_reg_n_0_[4]\, + O => \adapt_done_cnt_i_2__0_n_0\ + ); +adapt_done_cnt_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \adapt_done_cnt_i_1__0_n_0\, + Q => adapt_done_cnt_reg_n_0, + R => RST_CPLLRESET + ); +\adapt_done_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F8000000" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => adapt_done_cnt_reg_n_0, + I3 => new_txcoeff_req_reg2, + I4 => \FSM_onehot_fsm_reg_n_0_[4]\, + O => adapt_done + ); +adapt_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => adapt_done, + Q => rxeqscan_adapt_done, + R => RST_CPLLRESET + ); +\converge_cnt[0]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44444044" + ) + port map ( + I0 => converge_cnt(0), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(0) + ); +\converge_cnt[10]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(10), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(10) + ); +\converge_cnt[11]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(11), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(11) + ); +\converge_cnt[12]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(12), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(12) + ); +\converge_cnt[13]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(13), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(13) + ); +\converge_cnt[14]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(14), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(14) + ); +\converge_cnt[15]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(15), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(15) + ); +\converge_cnt[16]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(16), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(16) + ); +\converge_cnt[17]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(17), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(17) + ); +\converge_cnt[18]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(18), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(18) + ); +\converge_cnt[19]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(19), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(19) + ); +\converge_cnt[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(1), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(1) + ); +\converge_cnt[20]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(20), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(20) + ); +\converge_cnt[21]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(21), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(21) + ); +\converge_cnt[2]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(2), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(2) + ); +\converge_cnt[3]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(3), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(3) + ); +\converge_cnt[4]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(4), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(4) + ); +\converge_cnt[5]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(5), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(5) + ); +\converge_cnt[6]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(6), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(6) + ); +\converge_cnt[7]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(7), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(7) + ); +\converge_cnt[8]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(8), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(8) + ); +\converge_cnt[9]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(9), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(9) + ); +\converge_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(0), + Q => converge_cnt(0), + R => RST_CPLLRESET + ); +\converge_cnt_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(10), + Q => converge_cnt(10), + R => RST_CPLLRESET + ); +\converge_cnt_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(11), + Q => converge_cnt(11), + R => RST_CPLLRESET + ); +\converge_cnt_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(12), + Q => converge_cnt(12), + R => RST_CPLLRESET + ); +\converge_cnt_reg[12]_i_2__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[8]_i_2__0_n_0\, + CO(3) => \converge_cnt_reg[12]_i_2__0_n_0\, + CO(2) => \converge_cnt_reg[12]_i_2__0_n_1\, + CO(1) => \converge_cnt_reg[12]_i_2__0_n_2\, + CO(0) => \converge_cnt_reg[12]_i_2__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(12 downto 9), + S(3 downto 0) => converge_cnt(12 downto 9) + ); +\converge_cnt_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(13), + Q => converge_cnt(13), + R => RST_CPLLRESET + ); +\converge_cnt_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(14), + Q => converge_cnt(14), + R => RST_CPLLRESET + ); +\converge_cnt_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(15), + Q => converge_cnt(15), + R => RST_CPLLRESET + ); +\converge_cnt_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(16), + Q => converge_cnt(16), + R => RST_CPLLRESET + ); +\converge_cnt_reg[16]_i_2__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[12]_i_2__0_n_0\, + CO(3) => \converge_cnt_reg[16]_i_2__0_n_0\, + CO(2) => \converge_cnt_reg[16]_i_2__0_n_1\, + CO(1) => \converge_cnt_reg[16]_i_2__0_n_2\, + CO(0) => \converge_cnt_reg[16]_i_2__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(16 downto 13), + S(3 downto 0) => converge_cnt(16 downto 13) + ); +\converge_cnt_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(17), + Q => converge_cnt(17), + R => RST_CPLLRESET + ); +\converge_cnt_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(18), + Q => converge_cnt(18), + R => RST_CPLLRESET + ); +\converge_cnt_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(19), + Q => converge_cnt(19), + R => RST_CPLLRESET + ); +\converge_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(1), + Q => converge_cnt(1), + R => RST_CPLLRESET + ); +\converge_cnt_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(20), + Q => converge_cnt(20), + R => RST_CPLLRESET + ); +\converge_cnt_reg[20]_i_2__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[16]_i_2__0_n_0\, + CO(3) => \converge_cnt_reg[20]_i_2__0_n_0\, + CO(2) => \converge_cnt_reg[20]_i_2__0_n_1\, + CO(1) => \converge_cnt_reg[20]_i_2__0_n_2\, + CO(0) => \converge_cnt_reg[20]_i_2__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(20 downto 17), + S(3 downto 0) => converge_cnt(20 downto 17) + ); +\converge_cnt_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(21), + Q => converge_cnt(21), + R => RST_CPLLRESET + ); +\converge_cnt_reg[21]_i_2__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[20]_i_2__0_n_0\, + CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED\(3 downto 1), + O(0) => converge_cnt0(21), + S(3 downto 1) => B"000", + S(0) => converge_cnt(21) + ); +\converge_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(2), + Q => converge_cnt(2), + R => RST_CPLLRESET + ); +\converge_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(3), + Q => converge_cnt(3), + R => RST_CPLLRESET + ); +\converge_cnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(4), + Q => converge_cnt(4), + R => RST_CPLLRESET + ); +\converge_cnt_reg[4]_i_2__0\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \converge_cnt_reg[4]_i_2__0_n_0\, + CO(2) => \converge_cnt_reg[4]_i_2__0_n_1\, + CO(1) => \converge_cnt_reg[4]_i_2__0_n_2\, + CO(0) => \converge_cnt_reg[4]_i_2__0_n_3\, + CYINIT => converge_cnt(0), + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(4 downto 1), + S(3 downto 0) => converge_cnt(4 downto 1) + ); +\converge_cnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(5), + Q => converge_cnt(5), + R => RST_CPLLRESET + ); +\converge_cnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(6), + Q => converge_cnt(6), + R => RST_CPLLRESET + ); +\converge_cnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(7), + Q => converge_cnt(7), + R => RST_CPLLRESET + ); +\converge_cnt_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(8), + Q => converge_cnt(8), + R => RST_CPLLRESET + ); +\converge_cnt_reg[8]_i_2__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[4]_i_2__0_n_0\, + CO(3) => \converge_cnt_reg[8]_i_2__0_n_0\, + CO(2) => \converge_cnt_reg[8]_i_2__0_n_1\, + CO(1) => \converge_cnt_reg[8]_i_2__0_n_2\, + CO(0) => \converge_cnt_reg[8]_i_2__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(8 downto 5), + S(3 downto 0) => converge_cnt(8 downto 5) + ); +\converge_cnt_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(9), + Q => converge_cnt(9), + R => RST_CPLLRESET + ); +\fs_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(0), + Q => fs_reg1(0), + R => RST_CPLLRESET + ); +\fs_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(1), + Q => fs_reg1(1), + R => RST_CPLLRESET + ); +\fs_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(2), + Q => fs_reg1(2), + R => RST_CPLLRESET + ); +\fs_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(3), + Q => fs_reg1(3), + R => RST_CPLLRESET + ); +\fs_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(4), + Q => fs_reg1(4), + R => RST_CPLLRESET + ); +\fs_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(5), + Q => fs_reg1(5), + R => RST_CPLLRESET + ); +\fs_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(0), + Q => fs_reg2(0), + R => RST_CPLLRESET + ); +\fs_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(1), + Q => fs_reg2(1), + R => RST_CPLLRESET + ); +\fs_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(2), + Q => fs_reg2(2), + R => RST_CPLLRESET + ); +\fs_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(3), + Q => fs_reg2(3), + R => RST_CPLLRESET + ); +\fs_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(4), + Q => fs_reg2(4), + R => RST_CPLLRESET + ); +\fs_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(5), + Q => fs_reg2(5), + R => RST_CPLLRESET + ); +\lf_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(0), + Q => lf_reg1(0), + R => RST_CPLLRESET + ); +\lf_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(1), + Q => lf_reg1(1), + R => RST_CPLLRESET + ); +\lf_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(2), + Q => lf_reg1(2), + R => RST_CPLLRESET + ); +\lf_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(3), + Q => lf_reg1(3), + R => RST_CPLLRESET + ); +\lf_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(4), + Q => lf_reg1(4), + R => RST_CPLLRESET + ); +\lf_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(5), + Q => lf_reg1(5), + R => RST_CPLLRESET + ); +\lf_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(0), + Q => lf_reg2(0), + R => RST_CPLLRESET + ); +\lf_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(1), + Q => lf_reg2(1), + R => RST_CPLLRESET + ); +\lf_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(2), + Q => lf_reg2(2), + R => RST_CPLLRESET + ); +\lf_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(3), + Q => lf_reg2(3), + R => RST_CPLLRESET + ); +\lf_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(4), + Q => lf_reg2(4), + R => RST_CPLLRESET + ); +\lf_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(5), + Q => lf_reg2(5), + R => RST_CPLLRESET + ); +\new_txcoeff_done_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => new_txcoeff_req_reg2, + O => new_txcoeff_done + ); +new_txcoeff_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => new_txcoeff_done, + Q => rxeqscan_new_txcoeff_done, + R => RST_CPLLRESET + ); +new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => new_txcoeff_req_reg1_reg_0, + Q => new_txcoeff_req_reg1, + R => RST_CPLLRESET + ); +new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => new_txcoeff_req_reg1, + Q => new_txcoeff_req_reg2, + R => RST_CPLLRESET + ); +\preset_done_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[2]\, + I1 => \FSM_onehot_fsm_reg_n_0_[1]\, + I2 => preset_valid_reg2, + O => preset_done_1 + ); +preset_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_done_1, + Q => preset_done, + R => RST_CPLLRESET + ); +\preset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \preset_reg1_reg[2]_0\(0), + Q => preset_reg1(0), + R => RST_CPLLRESET + ); +\preset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \preset_reg1_reg[2]_0\(1), + Q => preset_reg1(1), + R => RST_CPLLRESET + ); +\preset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \preset_reg1_reg[2]_0\(2), + Q => preset_reg1(2), + R => RST_CPLLRESET + ); +\preset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_reg1(0), + Q => preset_reg2(0), + R => RST_CPLLRESET + ); +\preset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_reg1(1), + Q => preset_reg2(1), + R => RST_CPLLRESET + ); +\preset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_reg1(2), + Q => preset_reg2(2), + R => RST_CPLLRESET + ); +preset_valid_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_valid, + Q => preset_valid_reg1, + R => RST_CPLLRESET + ); +preset_valid_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_valid_reg1, + Q => preset_valid_reg2, + R => RST_CPLLRESET + ); +\rxeq_adapt_done_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A800FFFFA8000000" + ) + port map ( + I0 => rxeqscan_new_txcoeff_done, + I1 => rxeq_adapt_done_reg_reg_1, + I2 => rxeqscan_adapt_done, + I3 => Q(3), + I4 => rxeq_adapt_done_reg, + I5 => USER_RXEQ_ADAPT_DONE, + O => new_txcoeff_done_reg_0 + ); +\rxeq_adapt_done_reg_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF00FF33AA00A800" + ) + port map ( + I0 => rxeqscan_adapt_done, + I1 => rxeq_adapt_done_reg_reg, + I2 => rxeqscan_new_txcoeff_done, + I3 => Q(3), + I4 => rxeq_adapt_done_reg_reg_0, + I5 => rxeq_adapt_done_reg_reg_1, + O => adapt_done_reg_0 + ); +\rxeq_new_txcoeff_req_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => Q(3), + I1 => rxeqscan_new_txcoeff_done, + O => rxeq_new_txcoeff_req + ); +\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(0), + Q => txcoeff_reg1(0), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(10), + Q => txcoeff_reg1(10), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(11), + Q => txcoeff_reg1(11), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(12), + Q => txcoeff_reg1(12), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(13), + Q => txcoeff_reg1(13), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(14), + Q => txcoeff_reg1(14), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(15), + Q => txcoeff_reg1(15), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(16), + Q => txcoeff_reg1(16), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(17), + Q => txcoeff_reg1(17), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(1), + Q => txcoeff_reg1(1), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(2), + Q => txcoeff_reg1(2), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(3), + Q => txcoeff_reg1(3), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(4), + Q => txcoeff_reg1(4), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(5), + Q => txcoeff_reg1(5), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(6), + Q => txcoeff_reg1(6), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(7), + Q => txcoeff_reg1(7), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(8), + Q => txcoeff_reg1(8), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(9), + Q => txcoeff_reg1(9), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(0), + Q => txcoeff_reg2(0), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(10), + Q => txcoeff_reg2(10), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(11), + Q => txcoeff_reg2(11), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(12), + Q => txcoeff_reg2(12), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(13), + Q => txcoeff_reg2(13), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(14), + Q => txcoeff_reg2(14), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(15), + Q => txcoeff_reg2(15), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(16), + Q => txcoeff_reg2(16), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(17), + Q => txcoeff_reg2(17), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(1), + Q => txcoeff_reg2(1), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(2), + Q => txcoeff_reg2(2), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(3), + Q => txcoeff_reg2(3), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(4), + Q => txcoeff_reg2(4), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(5), + Q => txcoeff_reg2(5), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(6), + Q => txcoeff_reg2(6), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(7), + Q => txcoeff_reg2(7), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(8), + Q => txcoeff_reg2(8), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(9), + Q => txcoeff_reg2(9), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(0), + Q => txpreset_reg1(0), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(1), + Q => txpreset_reg1(1), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(2), + Q => txpreset_reg1(2), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(3), + Q => txpreset_reg1(3), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(0), + Q => txpreset_reg2(0), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(1), + Q => txpreset_reg2(1), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(2), + Q => txpreset_reg2(2), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(3), + Q => txpreset_reg2(3), + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_rxeq_scan_59 is + port ( + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + rxeq_new_txcoeff_req : out STD_LOGIC; + adapt_done_reg_0 : out STD_LOGIC; + new_txcoeff_done_reg_0 : out STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + new_txcoeff_req_reg1_reg_0 : in STD_LOGIC; + rxeq_preset_valid : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \FSM_onehot_fsm_rx_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + rxeq_adapt_done_reg_reg : in STD_LOGIC; + rxeq_adapt_done_reg_reg_0 : in STD_LOGIC; + rxeq_adapt_done_reg_reg_1 : in STD_LOGIC; + rxeq_adapt_done_reg : in STD_LOGIC; + USER_RXEQ_ADAPT_DONE : in STD_LOGIC; + \preset_reg1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \txpreset_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \txcoeff_reg1_reg[17]_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 ); + \fs_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \lf_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_rxeq_scan_59 : entity is "pcie_7x_0_rxeq_scan"; +end pcie_7x_0_pcie_7x_0_rxeq_scan_59; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_rxeq_scan_59 is + signal \FSM_onehot_fsm[1]_i_1__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[2]_i_1__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[3]_i_1__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[3]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_10_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_11_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_12_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_13_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_1__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_2__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_4_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_5_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_6_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_7_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_8_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm[4]_i_9_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[6]_i_2_n_0\ : STD_LOGIC; + signal adapt_done : STD_LOGIC; + signal adapt_done_cnt_i_1_n_0 : STD_LOGIC; + signal adapt_done_cnt_i_2_n_0 : STD_LOGIC; + signal adapt_done_cnt_reg_n_0 : STD_LOGIC; + signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 1 ); + signal converge_cnt_0 : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal \converge_cnt_reg[12]_i_2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[12]_i_2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[16]_i_2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[20]_i_2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[4]_i_2_n_3\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2_n_0\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2_n_1\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2_n_2\ : STD_LOGIC; + signal \converge_cnt_reg[8]_i_2_n_3\ : STD_LOGIC; + signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of fs_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of fs_reg1 : signal is "true"; + signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of fs_reg2 : signal is "NO"; + attribute async_reg of fs_reg2 : signal is "true"; + signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of lf_reg1 : signal is "NO"; + attribute async_reg of lf_reg1 : signal is "true"; + signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of lf_reg2 : signal is "NO"; + attribute async_reg of lf_reg2 : signal is "true"; + signal new_txcoeff_done : STD_LOGIC; + signal new_txcoeff_req_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg1 : signal is "NO"; + attribute async_reg of new_txcoeff_req_reg1 : signal is "true"; + signal new_txcoeff_req_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg2 : signal is "NO"; + attribute async_reg of new_txcoeff_req_reg2 : signal is "true"; + signal preset_done : STD_LOGIC; + signal preset_done_1 : STD_LOGIC; + signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of preset_reg1 : signal is "NO"; + attribute async_reg of preset_reg1 : signal is "true"; + signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of preset_reg2 : signal is "NO"; + attribute async_reg of preset_reg2 : signal is "true"; + signal preset_valid_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of preset_valid_reg1 : signal is "NO"; + attribute async_reg of preset_valid_reg1 : signal is "true"; + signal preset_valid_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of preset_valid_reg2 : signal is "NO"; + attribute async_reg of preset_valid_reg2 : signal is "true"; + signal rxeqscan_adapt_done : STD_LOGIC; + signal rxeqscan_new_txcoeff_done : STD_LOGIC; + signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of txcoeff_reg1 : signal is "NO"; + attribute async_reg of txcoeff_reg1 : signal is "true"; + signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of txcoeff_reg2 : signal is "NO"; + attribute async_reg of txcoeff_reg2 : signal is "true"; + signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txpreset_reg1 : signal is "NO"; + attribute async_reg of txpreset_reg1 : signal is "true"; + signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txpreset_reg2 : signal is "NO"; + attribute async_reg of txpreset_reg2 : signal is "true"; + signal \NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_fsm[3]_i_2\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \FSM_onehot_fsm[4]_i_4\ : label is "soft_lutpair45"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001"; + attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[6]_i_2\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \converge_cnt[18]_i_1\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \converge_cnt[21]_i_1\ : label is "soft_lutpair46"; + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \converge_cnt_reg[12]_i_2\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[16]_i_2\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[20]_i_2\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[21]_i_2\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[4]_i_2\ : label is 35; + attribute ADDER_THRESHOLD of \converge_cnt_reg[8]_i_2\ : label is 35; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \fs_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \fs_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \fs_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \fs_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \fs_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \fs_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \lf_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \lf_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \lf_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \lf_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of new_txcoeff_req_reg1_reg : label is std.standard.true; + attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of new_txcoeff_req_reg2_reg : label is std.standard.true; + attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of new_txcoeff_req_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \preset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \preset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \preset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \preset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \preset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \preset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \preset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \preset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of preset_valid_reg1_reg : label is std.standard.true; + attribute KEEP of preset_valid_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of preset_valid_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of preset_valid_reg2_reg : label is std.standard.true; + attribute KEEP of preset_valid_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of preset_valid_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of rxeq_new_txcoeff_req_i_1 : label is "soft_lutpair47"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[10]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[11]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[12]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[13]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[14]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[15]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[16]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[17]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[6]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[7]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[8]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[9]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[10]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[11]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[12]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[13]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[14]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[15]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[16]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[17]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[6]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[7]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[8]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[9]\ : label is std.standard.true; + attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txpreset_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txpreset_reg2_reg[3]\ : label is "NO"; +begin +\FSM_onehot_fsm[1]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F00AFAF0F11AFBB" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => preset_valid_reg2, + I3 => \FSM_onehot_fsm_reg_n_0_[2]\, + I4 => new_txcoeff_req_reg2, + I5 => \FSM_onehot_fsm_reg_n_0_[1]\, + O => \FSM_onehot_fsm[1]_i_1__1_n_0\ + ); +\FSM_onehot_fsm[2]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => preset_valid_reg2, + I1 => \FSM_onehot_fsm_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_reg_n_0_[1]\, + O => \FSM_onehot_fsm[2]_i_1__1_n_0\ + ); +\FSM_onehot_fsm[3]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"04FF040404040404" + ) + port map ( + I0 => \FSM_onehot_fsm[3]_i_2_n_0\, + I1 => \FSM_onehot_fsm[4]_i_2__0_n_0\, + I2 => \FSM_onehot_fsm[4]_i_3_n_0\, + I3 => preset_valid_reg2, + I4 => new_txcoeff_req_reg2, + I5 => \FSM_onehot_fsm_reg_n_0_[1]\, + O => \FSM_onehot_fsm[3]_i_1__1_n_0\ + ); +\FSM_onehot_fsm[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"04FF" + ) + port map ( + I0 => \out\(0), + I1 => \out\(1), + I2 => adapt_done_cnt_reg_n_0, + I3 => \FSM_onehot_fsm_reg_n_0_[3]\, + O => \FSM_onehot_fsm[3]_i_2_n_0\ + ); +\FSM_onehot_fsm[4]_i_10\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFBFFFFF" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_13_n_0\, + I1 => converge_cnt(2), + I2 => converge_cnt(20), + I3 => converge_cnt(10), + I4 => converge_cnt(0), + O => \FSM_onehot_fsm[4]_i_10_n_0\ + ); +\FSM_onehot_fsm[4]_i_11\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFFF" + ) + port map ( + I0 => converge_cnt(2), + I1 => converge_cnt(6), + I2 => converge_cnt(8), + I3 => converge_cnt(3), + O => \FSM_onehot_fsm[4]_i_11_n_0\ + ); +\FSM_onehot_fsm[4]_i_12\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EFFFFFFF" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_13_n_0\, + I1 => converge_cnt(14), + I2 => converge_cnt(10), + I3 => converge_cnt(21), + I4 => converge_cnt(19), + O => \FSM_onehot_fsm[4]_i_12_n_0\ + ); +\FSM_onehot_fsm[4]_i_13\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF7F" + ) + port map ( + I0 => converge_cnt(16), + I1 => converge_cnt(11), + I2 => converge_cnt(9), + I3 => converge_cnt(5), + O => \FSM_onehot_fsm[4]_i_13_n_0\ + ); +\FSM_onehot_fsm[4]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFD0FFD0FFD0" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_2__0_n_0\, + I1 => \FSM_onehot_fsm[4]_i_3_n_0\, + I2 => \FSM_onehot_fsm_reg_n_0_[3]\, + I3 => \FSM_onehot_fsm[4]_i_4_n_0\, + I4 => \FSM_onehot_fsm_reg_n_0_[4]\, + I5 => new_txcoeff_req_reg2, + O => \FSM_onehot_fsm[4]_i_1__1_n_0\ + ); +\FSM_onehot_fsm[4]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFBF" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_5_n_0\, + I1 => converge_cnt(17), + I2 => converge_cnt(18), + I3 => converge_cnt(21), + I4 => converge_cnt(8), + I5 => \FSM_onehot_fsm[4]_i_6_n_0\, + O => \FSM_onehot_fsm[4]_i_2__0_n_0\ + ); +\FSM_onehot_fsm[4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000001000000" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_7_n_0\, + I1 => converge_cnt(7), + I2 => converge_cnt(1), + I3 => converge_cnt(15), + I4 => converge_cnt(13), + I5 => \FSM_onehot_fsm[4]_i_8_n_0\, + O => \FSM_onehot_fsm[4]_i_3_n_0\ + ); +\FSM_onehot_fsm[4]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0400" + ) + port map ( + I0 => \out\(0), + I1 => \out\(1), + I2 => adapt_done_cnt_reg_n_0, + I3 => \FSM_onehot_fsm_reg_n_0_[3]\, + O => \FSM_onehot_fsm[4]_i_4_n_0\ + ); +\FSM_onehot_fsm[4]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF2" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => converge_cnt(7), + I3 => converge_cnt(1), + O => \FSM_onehot_fsm[4]_i_5_n_0\ + ); +\FSM_onehot_fsm[4]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFB" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_9_n_0\, + I1 => converge_cnt(19), + I2 => converge_cnt(6), + I3 => converge_cnt(3), + I4 => converge_cnt(4), + I5 => \FSM_onehot_fsm[4]_i_10_n_0\, + O => \FSM_onehot_fsm[4]_i_6_n_0\ + ); +\FSM_onehot_fsm[4]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"DFFF" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => converge_cnt(17), + I3 => converge_cnt(18), + O => \FSM_onehot_fsm[4]_i_7_n_0\ + ); +\FSM_onehot_fsm[4]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \FSM_onehot_fsm[4]_i_11_n_0\, + I1 => converge_cnt(12), + I2 => converge_cnt(20), + I3 => converge_cnt(0), + I4 => converge_cnt(4), + I5 => \FSM_onehot_fsm[4]_i_12_n_0\, + O => \FSM_onehot_fsm[4]_i_8_n_0\ + ); +\FSM_onehot_fsm[4]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFDF" + ) + port map ( + I0 => converge_cnt(15), + I1 => converge_cnt(13), + I2 => converge_cnt(14), + I3 => converge_cnt(12), + O => \FSM_onehot_fsm[4]_i_9_n_0\ + ); +\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[1]_i_1__1_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[2]_i_1__1_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[3]_i_1__1_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm[4]_i_1__1_n_0\, + Q => \FSM_onehot_fsm_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40FF4040" + ) + port map ( + I0 => \out\(1), + I1 => Q(0), + I2 => \out\(0), + I3 => preset_done, + I4 => Q(1), + O => D(0) + ); +\FSM_onehot_fsm_rx[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F444444444444444" + ) + port map ( + I0 => rxeqscan_new_txcoeff_done, + I1 => Q(3), + I2 => \FSM_onehot_fsm_rx_reg[5]\(2), + I3 => \FSM_onehot_fsm_rx_reg[5]\(0), + I4 => \FSM_onehot_fsm_rx_reg[5]\(1), + I5 => Q(2), + O => D(1) + ); +\FSM_onehot_fsm_rx[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFE0E0E0" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => Q(4), + I3 => preset_done, + I4 => Q(1), + I5 => \FSM_onehot_fsm_rx[6]_i_2_n_0\, + O => D(2) + ); +\FSM_onehot_fsm_rx[6]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => rxeqscan_new_txcoeff_done, + I1 => Q(3), + O => \FSM_onehot_fsm_rx[6]_i_2_n_0\ + ); +adapt_done_cnt_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"000A0A0AF0F0F8F0" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + I5 => adapt_done_cnt_i_2_n_0, + O => adapt_done_cnt_i_1_n_0 + ); +adapt_done_cnt_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"00FF0101" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[3]\, + I1 => \FSM_onehot_fsm_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_reg_n_0_[1]\, + I3 => new_txcoeff_req_reg2, + I4 => \FSM_onehot_fsm_reg_n_0_[4]\, + O => adapt_done_cnt_i_2_n_0 + ); +adapt_done_cnt_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => adapt_done_cnt_i_1_n_0, + Q => adapt_done_cnt_reg_n_0, + R => RST_CPLLRESET + ); +adapt_done_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"F8000000" + ) + port map ( + I0 => \out\(1), + I1 => \out\(0), + I2 => adapt_done_cnt_reg_n_0, + I3 => new_txcoeff_req_reg2, + I4 => \FSM_onehot_fsm_reg_n_0_[4]\, + O => adapt_done + ); +adapt_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => adapt_done, + Q => rxeqscan_adapt_done, + R => RST_CPLLRESET + ); +\converge_cnt[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44444044" + ) + port map ( + I0 => converge_cnt(0), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(0) + ); +\converge_cnt[10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(10), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(10) + ); +\converge_cnt[11]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(11), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(11) + ); +\converge_cnt[12]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(12), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(12) + ); +\converge_cnt[13]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(13), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(13) + ); +\converge_cnt[14]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(14), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(14) + ); +\converge_cnt[15]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(15), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(15) + ); +\converge_cnt[16]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(16), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(16) + ); +\converge_cnt[17]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(17), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(17) + ); +\converge_cnt[18]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(18), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(18) + ); +\converge_cnt[19]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(19), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(19) + ); +\converge_cnt[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(1), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(1) + ); +\converge_cnt[20]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(20), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(20) + ); +\converge_cnt[21]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(21), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(21) + ); +\converge_cnt[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(2), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(2) + ); +\converge_cnt[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(3), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(3) + ); +\converge_cnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(4), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(4) + ); +\converge_cnt[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(5), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(5) + ); +\converge_cnt[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(6), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(6) + ); +\converge_cnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(7), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(7) + ); +\converge_cnt[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(8), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(8) + ); +\converge_cnt[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888088" + ) + port map ( + I0 => converge_cnt0(9), + I1 => \FSM_onehot_fsm_reg_n_0_[3]\, + I2 => adapt_done_cnt_reg_n_0, + I3 => \out\(1), + I4 => \out\(0), + O => converge_cnt_0(9) + ); +\converge_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(0), + Q => converge_cnt(0), + R => RST_CPLLRESET + ); +\converge_cnt_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(10), + Q => converge_cnt(10), + R => RST_CPLLRESET + ); +\converge_cnt_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(11), + Q => converge_cnt(11), + R => RST_CPLLRESET + ); +\converge_cnt_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(12), + Q => converge_cnt(12), + R => RST_CPLLRESET + ); +\converge_cnt_reg[12]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[8]_i_2_n_0\, + CO(3) => \converge_cnt_reg[12]_i_2_n_0\, + CO(2) => \converge_cnt_reg[12]_i_2_n_1\, + CO(1) => \converge_cnt_reg[12]_i_2_n_2\, + CO(0) => \converge_cnt_reg[12]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(12 downto 9), + S(3 downto 0) => converge_cnt(12 downto 9) + ); +\converge_cnt_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(13), + Q => converge_cnt(13), + R => RST_CPLLRESET + ); +\converge_cnt_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(14), + Q => converge_cnt(14), + R => RST_CPLLRESET + ); +\converge_cnt_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(15), + Q => converge_cnt(15), + R => RST_CPLLRESET + ); +\converge_cnt_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(16), + Q => converge_cnt(16), + R => RST_CPLLRESET + ); +\converge_cnt_reg[16]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[12]_i_2_n_0\, + CO(3) => \converge_cnt_reg[16]_i_2_n_0\, + CO(2) => \converge_cnt_reg[16]_i_2_n_1\, + CO(1) => \converge_cnt_reg[16]_i_2_n_2\, + CO(0) => \converge_cnt_reg[16]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(16 downto 13), + S(3 downto 0) => converge_cnt(16 downto 13) + ); +\converge_cnt_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(17), + Q => converge_cnt(17), + R => RST_CPLLRESET + ); +\converge_cnt_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(18), + Q => converge_cnt(18), + R => RST_CPLLRESET + ); +\converge_cnt_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(19), + Q => converge_cnt(19), + R => RST_CPLLRESET + ); +\converge_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(1), + Q => converge_cnt(1), + R => RST_CPLLRESET + ); +\converge_cnt_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(20), + Q => converge_cnt(20), + R => RST_CPLLRESET + ); +\converge_cnt_reg[20]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[16]_i_2_n_0\, + CO(3) => \converge_cnt_reg[20]_i_2_n_0\, + CO(2) => \converge_cnt_reg[20]_i_2_n_1\, + CO(1) => \converge_cnt_reg[20]_i_2_n_2\, + CO(0) => \converge_cnt_reg[20]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(20 downto 17), + S(3 downto 0) => converge_cnt(20 downto 17) + ); +\converge_cnt_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(21), + Q => converge_cnt(21), + R => RST_CPLLRESET + ); +\converge_cnt_reg[21]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[20]_i_2_n_0\, + CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED\(3 downto 1), + O(0) => converge_cnt0(21), + S(3 downto 1) => B"000", + S(0) => converge_cnt(21) + ); +\converge_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(2), + Q => converge_cnt(2), + R => RST_CPLLRESET + ); +\converge_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(3), + Q => converge_cnt(3), + R => RST_CPLLRESET + ); +\converge_cnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(4), + Q => converge_cnt(4), + R => RST_CPLLRESET + ); +\converge_cnt_reg[4]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \converge_cnt_reg[4]_i_2_n_0\, + CO(2) => \converge_cnt_reg[4]_i_2_n_1\, + CO(1) => \converge_cnt_reg[4]_i_2_n_2\, + CO(0) => \converge_cnt_reg[4]_i_2_n_3\, + CYINIT => converge_cnt(0), + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(4 downto 1), + S(3 downto 0) => converge_cnt(4 downto 1) + ); +\converge_cnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(5), + Q => converge_cnt(5), + R => RST_CPLLRESET + ); +\converge_cnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(6), + Q => converge_cnt(6), + R => RST_CPLLRESET + ); +\converge_cnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(7), + Q => converge_cnt(7), + R => RST_CPLLRESET + ); +\converge_cnt_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(8), + Q => converge_cnt(8), + R => RST_CPLLRESET + ); +\converge_cnt_reg[8]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \converge_cnt_reg[4]_i_2_n_0\, + CO(3) => \converge_cnt_reg[8]_i_2_n_0\, + CO(2) => \converge_cnt_reg[8]_i_2_n_1\, + CO(1) => \converge_cnt_reg[8]_i_2_n_2\, + CO(0) => \converge_cnt_reg[8]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => converge_cnt0(8 downto 5), + S(3 downto 0) => converge_cnt(8 downto 5) + ); +\converge_cnt_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => converge_cnt_0(9), + Q => converge_cnt(9), + R => RST_CPLLRESET + ); +\fs_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(0), + Q => fs_reg1(0), + R => RST_CPLLRESET + ); +\fs_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(1), + Q => fs_reg1(1), + R => RST_CPLLRESET + ); +\fs_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(2), + Q => fs_reg1(2), + R => RST_CPLLRESET + ); +\fs_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(3), + Q => fs_reg1(3), + R => RST_CPLLRESET + ); +\fs_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(4), + Q => fs_reg1(4), + R => RST_CPLLRESET + ); +\fs_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fs_reg1_reg[5]_0\(5), + Q => fs_reg1(5), + R => RST_CPLLRESET + ); +\fs_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(0), + Q => fs_reg2(0), + R => RST_CPLLRESET + ); +\fs_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(1), + Q => fs_reg2(1), + R => RST_CPLLRESET + ); +\fs_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(2), + Q => fs_reg2(2), + R => RST_CPLLRESET + ); +\fs_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(3), + Q => fs_reg2(3), + R => RST_CPLLRESET + ); +\fs_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(4), + Q => fs_reg2(4), + R => RST_CPLLRESET + ); +\fs_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => fs_reg1(5), + Q => fs_reg2(5), + R => RST_CPLLRESET + ); +\lf_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(0), + Q => lf_reg1(0), + R => RST_CPLLRESET + ); +\lf_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(1), + Q => lf_reg1(1), + R => RST_CPLLRESET + ); +\lf_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(2), + Q => lf_reg1(2), + R => RST_CPLLRESET + ); +\lf_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(3), + Q => lf_reg1(3), + R => RST_CPLLRESET + ); +\lf_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(4), + Q => lf_reg1(4), + R => RST_CPLLRESET + ); +\lf_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \lf_reg1_reg[5]_0\(5), + Q => lf_reg1(5), + R => RST_CPLLRESET + ); +\lf_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(0), + Q => lf_reg2(0), + R => RST_CPLLRESET + ); +\lf_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(1), + Q => lf_reg2(1), + R => RST_CPLLRESET + ); +\lf_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(2), + Q => lf_reg2(2), + R => RST_CPLLRESET + ); +\lf_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(3), + Q => lf_reg2(3), + R => RST_CPLLRESET + ); +\lf_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(4), + Q => lf_reg2(4), + R => RST_CPLLRESET + ); +\lf_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => lf_reg1(5), + Q => lf_reg2(5), + R => RST_CPLLRESET + ); +new_txcoeff_done_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[4]\, + I1 => new_txcoeff_req_reg2, + O => new_txcoeff_done + ); +new_txcoeff_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => new_txcoeff_done, + Q => rxeqscan_new_txcoeff_done, + R => RST_CPLLRESET + ); +new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => new_txcoeff_req_reg1_reg_0, + Q => new_txcoeff_req_reg1, + R => RST_CPLLRESET + ); +new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => new_txcoeff_req_reg1, + Q => new_txcoeff_req_reg2, + R => RST_CPLLRESET + ); +preset_done_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => \FSM_onehot_fsm_reg_n_0_[2]\, + I1 => \FSM_onehot_fsm_reg_n_0_[1]\, + I2 => preset_valid_reg2, + O => preset_done_1 + ); +preset_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_done_1, + Q => preset_done, + R => RST_CPLLRESET + ); +\preset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \preset_reg1_reg[2]_0\(0), + Q => preset_reg1(0), + R => RST_CPLLRESET + ); +\preset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \preset_reg1_reg[2]_0\(1), + Q => preset_reg1(1), + R => RST_CPLLRESET + ); +\preset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \preset_reg1_reg[2]_0\(2), + Q => preset_reg1(2), + R => RST_CPLLRESET + ); +\preset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_reg1(0), + Q => preset_reg2(0), + R => RST_CPLLRESET + ); +\preset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_reg1(1), + Q => preset_reg2(1), + R => RST_CPLLRESET + ); +\preset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_reg1(2), + Q => preset_reg2(2), + R => RST_CPLLRESET + ); +preset_valid_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_valid, + Q => preset_valid_reg1, + R => RST_CPLLRESET + ); +preset_valid_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => preset_valid_reg1, + Q => preset_valid_reg2, + R => RST_CPLLRESET + ); +rxeq_adapt_done_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"A800FFFFA8000000" + ) + port map ( + I0 => rxeqscan_new_txcoeff_done, + I1 => rxeq_adapt_done_reg_reg_1, + I2 => rxeqscan_adapt_done, + I3 => Q(3), + I4 => rxeq_adapt_done_reg, + I5 => USER_RXEQ_ADAPT_DONE, + O => new_txcoeff_done_reg_0 + ); +rxeq_adapt_done_reg_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF00FF33AA00A800" + ) + port map ( + I0 => rxeqscan_adapt_done, + I1 => rxeq_adapt_done_reg_reg, + I2 => rxeqscan_new_txcoeff_done, + I3 => Q(3), + I4 => rxeq_adapt_done_reg_reg_0, + I5 => rxeq_adapt_done_reg_reg_1, + O => adapt_done_reg_0 + ); +rxeq_new_txcoeff_req_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => Q(3), + I1 => rxeqscan_new_txcoeff_done, + O => rxeq_new_txcoeff_req + ); +\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(0), + Q => txcoeff_reg1(0), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(10), + Q => txcoeff_reg1(10), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(11), + Q => txcoeff_reg1(11), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(12), + Q => txcoeff_reg1(12), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(13), + Q => txcoeff_reg1(13), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(14), + Q => txcoeff_reg1(14), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(15), + Q => txcoeff_reg1(15), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(16), + Q => txcoeff_reg1(16), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(17), + Q => txcoeff_reg1(17), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(1), + Q => txcoeff_reg1(1), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(2), + Q => txcoeff_reg1(2), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(3), + Q => txcoeff_reg1(3), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(4), + Q => txcoeff_reg1(4), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(5), + Q => txcoeff_reg1(5), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(6), + Q => txcoeff_reg1(6), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(7), + Q => txcoeff_reg1(7), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(8), + Q => txcoeff_reg1(8), + R => RST_CPLLRESET + ); +\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txcoeff_reg1_reg[17]_0\(9), + Q => txcoeff_reg1(9), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(0), + Q => txcoeff_reg2(0), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(10), + Q => txcoeff_reg2(10), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(11), + Q => txcoeff_reg2(11), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(12), + Q => txcoeff_reg2(12), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(13), + Q => txcoeff_reg2(13), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(14), + Q => txcoeff_reg2(14), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(15), + Q => txcoeff_reg2(15), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(16), + Q => txcoeff_reg2(16), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(17), + Q => txcoeff_reg2(17), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(1), + Q => txcoeff_reg2(1), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(2), + Q => txcoeff_reg2(2), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(3), + Q => txcoeff_reg2(3), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(4), + Q => txcoeff_reg2(4), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(5), + Q => txcoeff_reg2(5), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(6), + Q => txcoeff_reg2(6), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(7), + Q => txcoeff_reg2(7), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(8), + Q => txcoeff_reg2(8), + R => RST_CPLLRESET + ); +\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txcoeff_reg1(9), + Q => txcoeff_reg2(9), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(0), + Q => txpreset_reg1(0), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(1), + Q => txpreset_reg1(1), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(2), + Q => txpreset_reg1(2), + R => RST_CPLLRESET + ); +\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txpreset_reg1_reg[3]_0\(3), + Q => txpreset_reg1(3), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(0), + Q => txpreset_reg2(0), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(1), + Q => txpreset_reg2(1), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(2), + Q => txpreset_reg2(2), + R => RST_CPLLRESET + ); +\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txpreset_reg1(3), + Q => txpreset_reg2(3), + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_xpm_cdc_single is + port ( + src_clk : in STD_LOGIC; + src_in : in STD_LOGIC; + dest_clk : in STD_LOGIC; + dest_out : out STD_LOGIC + ); + attribute DEST_SYNC_FF : integer; + attribute DEST_SYNC_FF of pcie_7x_0_xpm_cdc_single : entity is 2; + attribute INIT_SYNC_FF : integer; + attribute INIT_SYNC_FF of pcie_7x_0_xpm_cdc_single : entity is 0; + attribute SIM_ASSERT_CHK : integer; + attribute SIM_ASSERT_CHK of pcie_7x_0_xpm_cdc_single : entity is 0; + attribute SRC_INPUT_REG : integer; + attribute SRC_INPUT_REG of pcie_7x_0_xpm_cdc_single : entity is 0; + attribute VERSION : integer; + attribute VERSION of pcie_7x_0_xpm_cdc_single : entity is 0; + attribute XPM_MODULE : string; + attribute XPM_MODULE of pcie_7x_0_xpm_cdc_single : entity is "TRUE"; + attribute keep_hierarchy : string; + attribute keep_hierarchy of pcie_7x_0_xpm_cdc_single : entity is "true"; + attribute xpm_cdc : string; + attribute xpm_cdc of pcie_7x_0_xpm_cdc_single : entity is "SINGLE"; +end pcie_7x_0_xpm_cdc_single; + +architecture STRUCTURE of pcie_7x_0_xpm_cdc_single is + signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of syncstages_ff : signal is "true"; + attribute async_reg : string; + attribute async_reg of syncstages_ff : signal is "true"; + attribute xpm_cdc of syncstages_ff : signal is "SINGLE"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; + attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE"; + attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; + attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; + attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE"; +begin + dest_out <= syncstages_ff(1); +\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => dest_clk, + CE => '1', + D => src_in, + Q => syncstages_ff(0), + R => '0' + ); +\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => dest_clk, + CE => '1', + D => syncstages_ff(0), + Q => syncstages_ff(1), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \pcie_7x_0_xpm_cdc_single__2\ is + port ( + src_clk : in STD_LOGIC; + src_in : in STD_LOGIC; + dest_clk : in STD_LOGIC; + dest_out : out STD_LOGIC + ); + attribute DEST_SYNC_FF : integer; + attribute DEST_SYNC_FF of \pcie_7x_0_xpm_cdc_single__2\ : entity is 2; + attribute INIT_SYNC_FF : integer; + attribute INIT_SYNC_FF of \pcie_7x_0_xpm_cdc_single__2\ : entity is 0; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \pcie_7x_0_xpm_cdc_single__2\ : entity is "xpm_cdc_single"; + attribute SIM_ASSERT_CHK : integer; + attribute SIM_ASSERT_CHK of \pcie_7x_0_xpm_cdc_single__2\ : entity is 0; + attribute SRC_INPUT_REG : integer; + attribute SRC_INPUT_REG of \pcie_7x_0_xpm_cdc_single__2\ : entity is 0; + attribute VERSION : integer; + attribute VERSION of \pcie_7x_0_xpm_cdc_single__2\ : entity is 0; + attribute XPM_MODULE : string; + attribute XPM_MODULE of \pcie_7x_0_xpm_cdc_single__2\ : entity is "TRUE"; + attribute keep_hierarchy : string; + attribute keep_hierarchy of \pcie_7x_0_xpm_cdc_single__2\ : entity is "true"; + attribute xpm_cdc : string; + attribute xpm_cdc of \pcie_7x_0_xpm_cdc_single__2\ : entity is "SINGLE"; +end \pcie_7x_0_xpm_cdc_single__2\; + +architecture STRUCTURE of \pcie_7x_0_xpm_cdc_single__2\ is + signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of syncstages_ff : signal is "true"; + attribute async_reg : string; + attribute async_reg of syncstages_ff : signal is "true"; + attribute xpm_cdc of syncstages_ff : signal is "SINGLE"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; + attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE"; + attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; + attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; + attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE"; +begin + dest_out <= syncstages_ff(1); +\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => dest_clk, + CE => '1', + D => src_in, + Q => syncstages_ff(0), + R => '0' + ); +\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => dest_clk, + CE => '1', + D => syncstages_ff(0), + Q => syncstages_ff(1), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_axi_basic_rx is + port ( + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + trn_rsrc_dsc_d : out STD_LOGIC; + m_axis_rx_tvalid_reg : out STD_LOGIC; + m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_rx_tlast : out STD_LOGIC; + trn_in_packet : out STD_LOGIC; + reg_dsc_detect_reg : out STD_LOGIC; + m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 63 downto 0 ); + \trn_rbar_hit_prev_reg[0]\ : in STD_LOGIC; + pipe_userclk2_in : in STD_LOGIC; + trn_rrem : in STD_LOGIC_VECTOR ( 0 to 0 ); + trn_rsrc_dsc : in STD_LOGIC; + rsrc_rdy_filtered : in STD_LOGIC; + trn_reof : in STD_LOGIC; + trn_rsrc_dsc_prev0 : in STD_LOGIC; + trn_rsof : in STD_LOGIC; + trn_recrc_err : in STD_LOGIC; + trn_rerrfwd : in STD_LOGIC; + trn_in_packet_reg : in STD_LOGIC; + m_axis_rx_tready : in STD_LOGIC; + dsc_detect : in STD_LOGIC; + trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 ); + trn_rbar_hit : in STD_LOGIC_VECTOR ( 6 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_axi_basic_rx; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_axi_basic_rx is + signal \^q\ : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal \^m_axis_rx_tuser\ : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal \^m_axis_rx_tvalid_reg\ : STD_LOGIC; + signal new_pkt_len : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal null_mux_sel : STD_LOGIC; + signal rx_null_gen_inst_n_0 : STD_LOGIC; + signal rx_null_gen_inst_n_1 : STD_LOGIC; + signal rx_null_gen_inst_n_2 : STD_LOGIC; + signal rx_null_gen_inst_n_3 : STD_LOGIC; + signal rx_null_gen_inst_n_4 : STD_LOGIC; + signal rx_null_gen_inst_n_5 : STD_LOGIC; + signal rx_null_gen_inst_n_6 : STD_LOGIC; + signal rx_null_gen_inst_n_7 : STD_LOGIC; + signal rx_null_gen_inst_n_8 : STD_LOGIC; + signal rx_pipeline_inst_n_73 : STD_LOGIC; + signal rx_pipeline_inst_n_74 : STD_LOGIC; + signal rx_pipeline_inst_n_8 : STD_LOGIC; +begin + Q(63 downto 0) <= \^q\(63 downto 0); + m_axis_rx_tuser(12 downto 0) <= \^m_axis_rx_tuser\(12 downto 0); + m_axis_rx_tvalid_reg <= \^m_axis_rx_tvalid_reg\; +rx_null_gen_inst: entity work.pcie_7x_0_pcie_7x_0_axi_basic_rx_null_gen + port map ( + D(1) => rx_null_gen_inst_n_0, + D(0) => rx_null_gen_inst_n_1, + Q(4 downto 3) => \^q\(30 downto 29), + Q(2) => \^q\(15), + Q(1 downto 0) => \^q\(1 downto 0), + S(1) => rx_null_gen_inst_n_7, + S(0) => rx_null_gen_inst_n_8, + cur_state_reg_0 => \trn_rbar_hit_prev_reg[0]\, + cur_state_reg_1 => \^m_axis_rx_tvalid_reg\, + m_axis_rx_tready => m_axis_rx_tready, + m_axis_rx_tuser(0) => \^m_axis_rx_tuser\(12), + \m_axis_rx_tuser_reg[19]\ => rx_pipeline_inst_n_74, + \m_axis_rx_tuser_reg[21]\ => rx_pipeline_inst_n_73, + new_pkt_len(10 downto 0) => new_pkt_len(10 downto 0), + null_mux_sel => null_mux_sel, + null_mux_sel_reg => rx_null_gen_inst_n_5, + null_mux_sel_reg_0 => rx_null_gen_inst_n_6, + null_mux_sel_reg_1 => rx_pipeline_inst_n_8, + pipe_userclk2_in => pipe_userclk2_in, + \reg_pkt_len_counter_reg[0]_0\ => rx_null_gen_inst_n_4, + \reg_pkt_len_counter_reg[3]_0\ => rx_null_gen_inst_n_3, + \reg_tkeep[7]_i_7_0\ => rx_null_gen_inst_n_2 + ); +rx_pipeline_inst: entity work.pcie_7x_0_pcie_7x_0_axi_basic_rx_pipeline + port map ( + D(1) => rx_null_gen_inst_n_0, + D(0) => rx_null_gen_inst_n_1, + E(0) => E(0), + Q(63 downto 0) => \^q\(63 downto 0), + S(1) => rx_null_gen_inst_n_7, + S(0) => rx_null_gen_inst_n_8, + data_prev_reg_0 => rx_pipeline_inst_n_73, + data_prev_reg_1 => rx_pipeline_inst_n_74, + dsc_detect => dsc_detect, + m_axis_rx_tkeep(0) => m_axis_rx_tkeep(0), + m_axis_rx_tlast => m_axis_rx_tlast, + m_axis_rx_tready => m_axis_rx_tready, + m_axis_rx_tuser(12 downto 0) => \^m_axis_rx_tuser\(12 downto 0), + m_axis_rx_tvalid_reg_0 => \^m_axis_rx_tvalid_reg\, + new_pkt_len(10 downto 0) => new_pkt_len(10 downto 0), + null_mux_sel => null_mux_sel, + null_mux_sel_reg_0 => rx_null_gen_inst_n_5, + pipe_userclk2_in => pipe_userclk2_in, + reg_dsc_detect_reg_0 => reg_dsc_detect_reg, + \reg_tkeep_reg[7]_0\ => rx_null_gen_inst_n_3, + reg_tlast_reg_0 => rx_null_gen_inst_n_6, + rsrc_rdy_filtered => rsrc_rdy_filtered, + trn_in_packet => trn_in_packet, + trn_in_packet_reg_0 => trn_in_packet_reg, + trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0), + \trn_rbar_hit_prev_reg[0]_0\ => \trn_rbar_hit_prev_reg[0]\, + trn_rd(63 downto 0) => trn_rd(63 downto 0), + trn_rdst_rdy_reg_0 => rx_null_gen_inst_n_2, + trn_rdst_rdy_reg_1 => rx_null_gen_inst_n_4, + trn_recrc_err => trn_recrc_err, + trn_reof => trn_reof, + trn_rerrfwd => trn_rerrfwd, + trn_rrem(0) => trn_rrem(0), + trn_rsof => trn_rsof, + trn_rsrc_dsc => trn_rsrc_dsc, + trn_rsrc_dsc_d => trn_rsrc_dsc_d, + trn_rsrc_dsc_prev0 => trn_rsrc_dsc_prev0, + user_reset_out_reg => rx_pipeline_inst_n_8 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_axi_basic_tx is + port ( + reg_tcfg_gnt : out STD_LOGIC; + tready_thrtl_reg : out STD_LOGIC; + trn_teof : out STD_LOGIC; + trn_tsrc_rdy : out STD_LOGIC; + trn_trem : out STD_LOGIC_VECTOR ( 0 to 0 ); + ppm_L1_thrtl : out STD_LOGIC; + lnk_up_thrtl : out STD_LOGIC; + ppm_L1_trig : out STD_LOGIC; + cfg_pm_turnoff_ok_n : out STD_LOGIC; + trn_tcfg_gnt : out STD_LOGIC; + trn_tsof : out STD_LOGIC; + \throttle_ctl_pipeline.reg_tdata_reg[63]\ : out STD_LOGIC_VECTOR ( 63 downto 0 ); + \throttle_ctl_pipeline.reg_tuser_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \throttle_ctl_pipeline.reg_tkeep_reg[7]\ : in STD_LOGIC; + tx_cfg_gnt : in STD_LOGIC; + pipe_userclk2_in : in STD_LOGIC; + trn_tcfg_req : in STD_LOGIC; + trn_tdst_rdy : in STD_LOGIC; + tbuf_av_min_trig : in STD_LOGIC; + cfg_turnoff_ok : in STD_LOGIC; + s_axis_tx_tlast : in STD_LOGIC; + s_axis_tx_tvalid : in STD_LOGIC; + s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); + ppm_L1_thrtl_reg : in STD_LOGIC; + lnk_up_thrtl_reg : in STD_LOGIC; + \out\ : in STD_LOGIC; + tcfg_req_trig : in STD_LOGIC; + tready_thrtl_i_5 : in STD_LOGIC; + cfg_pcie_link_state : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ); + trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 ); + cfg_to_turnoff : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_axi_basic_tx; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_axi_basic_tx is + signal axi_in_packet : STD_LOGIC; + signal reg_disable_trn : STD_LOGIC; + signal reg_tsrc_rdy0 : STD_LOGIC; + signal \thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4\ : STD_LOGIC; + signal \^tready_thrtl_reg\ : STD_LOGIC; +begin + tready_thrtl_reg <= \^tready_thrtl_reg\; +\thrtl_ctl_enabled.tx_thrl_ctl_inst\: entity work.pcie_7x_0_pcie_7x_0_axi_basic_tx_thrtl_ctl + port map ( + axi_in_packet => axi_in_packet, + cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0), + cfg_pm_turnoff_ok_n => cfg_pm_turnoff_ok_n, + cfg_to_turnoff => cfg_to_turnoff, + cfg_turnoff_ok => cfg_turnoff_ok, + lnk_up_thrtl => lnk_up_thrtl, + lnk_up_thrtl_reg_0 => lnk_up_thrtl_reg, + \out\ => \out\, + pipe_userclk2_in => pipe_userclk2_in, + ppm_L1_thrtl => ppm_L1_thrtl, + ppm_L1_thrtl_reg_0 => ppm_L1_thrtl_reg, + ppm_L1_trig => ppm_L1_trig, + reg_disable_trn => reg_disable_trn, + reg_tcfg_gnt => reg_tcfg_gnt, + reg_tsrc_rdy0 => reg_tsrc_rdy0, + s_axis_tx_tdata(3 downto 2) => s_axis_tx_tdata(30 downto 29), + s_axis_tx_tdata(1) => s_axis_tx_tdata(15), + s_axis_tx_tdata(0) => s_axis_tx_tdata(0), + s_axis_tx_tlast => s_axis_tx_tlast, + s_axis_tx_tlast_0 => \thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4\, + s_axis_tx_tuser(0) => s_axis_tx_tuser(0), + s_axis_tx_tvalid => s_axis_tx_tvalid, + tbuf_av_min_trig => tbuf_av_min_trig, + \tbuf_gap_cnt_reg[0]_0\ => \throttle_ctl_pipeline.reg_tkeep_reg[7]\, + tcfg_req_trig => tcfg_req_trig, + tready_thrtl_i_5_0 => tready_thrtl_i_5, + tready_thrtl_reg_0 => \^tready_thrtl_reg\, + trn_tbuf_av(5 downto 0) => trn_tbuf_av(5 downto 0), + trn_tcfg_gnt => trn_tcfg_gnt, + trn_tcfg_req => trn_tcfg_req, + trn_tdst_rdy => trn_tdst_rdy, + tx_cfg_gnt => tx_cfg_gnt + ); +tx_pipeline_inst: entity work.pcie_7x_0_pcie_7x_0_axi_basic_tx_pipeline + port map ( + axi_in_packet => axi_in_packet, + axi_in_packet_reg_0 => \thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4\, + \out\ => \out\, + pipe_userclk2_in => pipe_userclk2_in, + reg_disable_trn => reg_disable_trn, + reg_tsrc_rdy0 => reg_tsrc_rdy0, + s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0), + s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0), + s_axis_tx_tlast => s_axis_tx_tlast, + s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0), + s_axis_tx_tvalid => s_axis_tx_tvalid, + \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(63 downto 0) => \throttle_ctl_pipeline.reg_tdata_reg[63]\(63 downto 0), + \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ => \throttle_ctl_pipeline.reg_tkeep_reg[7]\, + \throttle_ctl_pipeline.reg_tuser_reg[3]_0\(3 downto 0) => \throttle_ctl_pipeline.reg_tuser_reg[3]\(3 downto 0), + \thrtl_ctl_trn_flush.reg_disable_trn_reg_0\ => \^tready_thrtl_reg\, + trn_tdst_rdy => trn_tdst_rdy, + trn_teof => trn_teof, + trn_trem(0) => trn_trem(0), + trn_tsof => trn_tsof, + trn_tsrc_rdy => trn_tsrc_rdy + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gt_common is + port ( + QPLL_QPLLLOCK : out STD_LOGIC; + QPLL_QPLLOUTCLK : out STD_LOGIC; + QPLL_QPLLOUTREFCLK : out STD_LOGIC; + QPLL_DRP_DONE : out STD_LOGIC; + RST_DCLK_RESET : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + sys_clk : in STD_LOGIC; + QPLL_QPLLPD : in STD_LOGIC; + QPLL_QPLLRESET : in STD_LOGIC; + QRST_DRP_START : in STD_LOGIC; + QPLL_DRP_GEN3 : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_gt_common; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gt_common is + signal \^qpll_qplllock\ : STD_LOGIC; + signal qpll_drp_addr : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal qpll_drp_di : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal qpll_drp_do : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal qpll_drp_en : STD_LOGIC; + signal qpll_drp_rdy : STD_LOGIC; + signal qpll_drp_we : STD_LOGIC; +begin + QPLL_QPLLLOCK <= \^qpll_qplllock\; +qpll_drp_i: entity work.pcie_7x_0_pcie_7x_0_qpll_drp + port map ( + D(15 downto 0) => qpll_drp_do(15 downto 0), + Q(4) => qpll_drp_addr(7), + Q(3) => qpll_drp_addr(5), + Q(2 downto 0) => qpll_drp_addr(2 downto 0), + QPLL_DRP_DONE => QPLL_DRP_DONE, + QPLL_DRP_GEN3 => QPLL_DRP_GEN3, + QPLL_QPLLLOCK => \^qpll_qplllock\, + QRST_DRP_START => QRST_DRP_START, + RST_DCLK_RESET => RST_DCLK_RESET, + \di_reg[15]_0\(15 downto 0) => qpll_drp_di(15 downto 0), + pipe_dclk_in => pipe_dclk_in, + qpll_drp_en => qpll_drp_en, + qpll_drp_rdy => qpll_drp_rdy, + qpll_drp_we => qpll_drp_we + ); +qpll_wrapper_i: entity work.pcie_7x_0_pcie_7x_0_qpll_wrapper + port map ( + D(15 downto 0) => qpll_drp_do(15 downto 0), + Q(4) => qpll_drp_addr(7), + Q(3) => qpll_drp_addr(5), + Q(2 downto 0) => qpll_drp_addr(2 downto 0), + QPLL_QPLLLOCK => \^qpll_qplllock\, + QPLL_QPLLOUTCLK => QPLL_QPLLOUTCLK, + QPLL_QPLLOUTREFCLK => QPLL_QPLLOUTREFCLK, + QPLL_QPLLPD => QPLL_QPLLPD, + QPLL_QPLLRESET => QPLL_QPLLRESET, + pipe_dclk_in => pipe_dclk_in, + qpll_drp_en => qpll_drp_en, + qpll_drp_rdy => qpll_drp_rdy, + qpll_drp_we => qpll_drp_we, + rdy_reg1_reg(15 downto 0) => qpll_drp_di(15 downto 0), + sys_clk => sys_clk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gt_wrapper is + port ( + cpllpd : out STD_LOGIC; + QRST_CPLLLOCK : out STD_LOGIC_VECTOR ( 0 to 0 ); + DRP_RDY : out STD_LOGIC; + pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 ); + pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 ); + RATE_PHYSTATUS : out STD_LOGIC; + gt_rxcdrlock_0 : out STD_LOGIC; + PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_dclk_in_0 : out STD_LOGIC; + gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); + SYNC_RXPHALIGNDONE_M : out STD_LOGIC; + RATE_RXRATEDONE : out STD_LOGIC; + USER_RXRESETDONE : out STD_LOGIC; + gt_rxvalid_0 : out STD_LOGIC; + pipe_dclk_in_1 : out STD_LOGIC; + pipe_txoutclk_out : out STD_LOGIC; + pipe_dclk_in_2 : out STD_LOGIC; + pipe_dclk_in_3 : out STD_LOGIC; + RATE_TXRATEDONE : out STD_LOGIC; + USER_TXRESETDONE : out STD_LOGIC; + DRP_DO : out STD_LOGIC_VECTOR ( 15 downto 0 ); + PIPE_RXSTATUS : out STD_LOGIC_VECTOR ( 2 downto 0 ); + RXCHBONDO : out STD_LOGIC_VECTOR ( 4 downto 0 ); + gt_rx_data_wire_filter : out STD_LOGIC_VECTOR ( 15 downto 0 ); + gt_rx_data_k_wire_filter : out STD_LOGIC_VECTOR ( 1 downto 0 ); + gt_cpllpdrefclk : in STD_LOGIC; + CPLLPD0 : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + \cplllock_reg1_reg[0]\ : in STD_LOGIC; + \cplllock_reg1_reg[0]_0\ : in STD_LOGIC; + sys_clk : in STD_LOGIC; + DRP_GTXRESET : in STD_LOGIC; + pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 ); + pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 ); + QPLL_QPLLOUTCLK : in STD_LOGIC; + QPLL_QPLLOUTREFCLK : in STD_LOGIC; + rxchbonden_0 : in STD_LOGIC; + \cplllock_reg1_reg[0]_1\ : in STD_LOGIC; + rate_txpmareset_0 : in STD_LOGIC; + PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 0 to 0 ); + rst_userrdy : in STD_LOGIC; + pipe_rxusrclk_in : in STD_LOGIC; + pipe_tx_deemph_gt : in STD_LOGIC; + pipe_tx_rcvr_det_gt : in STD_LOGIC; + sync_txdlyen_0 : in STD_LOGIC; + SYNC_TXDLYSRESET : in STD_LOGIC; + PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 ); + SYNC_TXPHALIGN : in STD_LOGIC; + SYNC_TXPHINIT : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 ); + PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 1 downto 0 ); + RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 0 to 0 ); + RXRATE : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cplllock_reg1_reg[0]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + USER_OOBCLK : in STD_LOGIC; + TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 ); + TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 ); + PIPE_TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); + TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 ); + PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DRPADDR : in STD_LOGIC_VECTOR ( 7 downto 0 ); + rate_cpllreset_0 : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_gt_wrapper; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gt_wrapper is + signal CPLLRESET0 : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_138\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_139\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_140\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_141\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_142\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_143\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_144\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_145\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_146\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_147\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_148\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_149\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_150\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_151\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_152\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_153\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_16\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_177\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_178\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_179\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_180\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_181\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_182\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_183\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_184\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_197\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_198\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_201\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_202\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_203\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_204\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_205\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_206\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_207\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_208\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_209\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_210\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_211\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_212\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_213\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_214\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_215\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_216\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_27\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_4\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_82\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_83\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_84\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE"; +begin +cpllPDInst: entity work.pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_60 + port map ( + CPLLRESET0 => CPLLRESET0, + RST_CPLLRESET => RST_CPLLRESET, + cpllpd => cpllpd, + gt_cpllpdrefclk => gt_cpllpdrefclk, + rate_cpllreset_0 => rate_cpllreset_0 + ); +\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL + generic map( + ALIGN_COMMA_DOUBLE => "FALSE", + ALIGN_COMMA_ENABLE => B"1111111111", + ALIGN_COMMA_WORD => 1, + ALIGN_MCOMMA_DET => "TRUE", + ALIGN_MCOMMA_VALUE => B"1010000011", + ALIGN_PCOMMA_DET => "TRUE", + ALIGN_PCOMMA_VALUE => B"0101111100", + CBCC_DATA_SOURCE_SEL => "DECODED", + CHAN_BOND_KEEP_ALIGN => "TRUE", + CHAN_BOND_MAX_SKEW => 7, + CHAN_BOND_SEQ_1_1 => B"0001001010", + CHAN_BOND_SEQ_1_2 => B"0001001010", + CHAN_BOND_SEQ_1_3 => B"0001001010", + CHAN_BOND_SEQ_1_4 => B"0110111100", + CHAN_BOND_SEQ_1_ENABLE => B"1111", + CHAN_BOND_SEQ_2_1 => B"0001000101", + CHAN_BOND_SEQ_2_2 => B"0001000101", + CHAN_BOND_SEQ_2_3 => B"0001000101", + CHAN_BOND_SEQ_2_4 => B"0110111100", + CHAN_BOND_SEQ_2_ENABLE => B"1111", + CHAN_BOND_SEQ_2_USE => "TRUE", + CHAN_BOND_SEQ_LEN => 4, + CLK_CORRECT_USE => "TRUE", + CLK_COR_KEEP_IDLE => "TRUE", + CLK_COR_MAX_LAT => 20, + CLK_COR_MIN_LAT => 18, + CLK_COR_PRECEDENCE => "TRUE", + CLK_COR_REPEAT_WAIT => 0, + CLK_COR_SEQ_1_1 => B"0100011100", + CLK_COR_SEQ_1_2 => B"0000000000", + CLK_COR_SEQ_1_3 => B"0000000000", + CLK_COR_SEQ_1_4 => B"0000000000", + CLK_COR_SEQ_1_ENABLE => B"1111", + CLK_COR_SEQ_2_1 => B"0000000000", + CLK_COR_SEQ_2_2 => B"0000000000", + CLK_COR_SEQ_2_3 => B"0000000000", + CLK_COR_SEQ_2_4 => B"0000000000", + CLK_COR_SEQ_2_ENABLE => B"0000", + CLK_COR_SEQ_2_USE => "FALSE", + CLK_COR_SEQ_LEN => 1, + CPLL_CFG => X"A407CC", + CPLL_FBDIV => 5, + CPLL_FBDIV_45 => 5, + CPLL_INIT_CFG => X"00001E", + CPLL_LOCK_CFG => X"01E8", + CPLL_REFCLK_DIV => 1, + DEC_MCOMMA_DETECT => "TRUE", + DEC_PCOMMA_DETECT => "TRUE", + DEC_VALID_COMMA_ONLY => "FALSE", + DMONITOR_CFG => X"000B01", + ES_CONTROL => B"000000", + ES_ERRDET_EN => "FALSE", + ES_EYE_SCAN_EN => "FALSE", + ES_HORZ_OFFSET => X"000", + ES_PMA_CFG => B"0000000000", + ES_PRESCALE => B"00000", + ES_QUALIFIER => X"00000000000000000000", + ES_QUAL_MASK => X"00000000000000000000", + ES_SDATA_MASK => X"00000000000000000000", + ES_VERT_OFFSET => B"000000000", + FTS_DESKEW_SEQ_ENABLE => B"1111", + FTS_LANE_DESKEW_CFG => B"1111", + FTS_LANE_DESKEW_EN => "TRUE", + GEARBOX_MODE => B"000", + IS_CPLLLOCKDETCLK_INVERTED => '0', + IS_DRPCLK_INVERTED => '0', + IS_GTGREFCLK_INVERTED => '0', + IS_RXUSRCLK2_INVERTED => '0', + IS_RXUSRCLK_INVERTED => '0', + IS_TXPHDLYTSTCLK_INVERTED => '0', + IS_TXUSRCLK2_INVERTED => '0', + IS_TXUSRCLK_INVERTED => '0', + OUTREFCLK_SEL_INV => B"11", + PCS_PCIE_EN => "TRUE", + PCS_RSVD_ATTR => X"0000000001CF", + PD_TRANS_TIME_FROM_P2 => X"03C", + PD_TRANS_TIME_NONE_P2 => X"09", + PD_TRANS_TIME_TO_P2 => X"64", + PMA_RSV => X"00018480", + PMA_RSV2 => X"2050", + PMA_RSV3 => B"00", + PMA_RSV4 => X"00000000", + RXBUFRESET_TIME => B"00001", + RXBUF_ADDR_MODE => "FULL", + RXBUF_EIDLE_HI_CNT => B"0100", + RXBUF_EIDLE_LO_CNT => B"0000", + RXBUF_EN => "TRUE", + RXBUF_RESET_ON_CB_CHANGE => "TRUE", + RXBUF_RESET_ON_COMMAALIGN => "FALSE", + RXBUF_RESET_ON_EIDLE => "TRUE", + RXBUF_RESET_ON_RATE_CHANGE => "TRUE", + RXBUF_THRESH_OVFLW => 61, + RXBUF_THRESH_OVRD => "FALSE", + RXBUF_THRESH_UNDFLW => 4, + RXCDRFREQRESET_TIME => B"00001", + RXCDRPHRESET_TIME => B"00001", + RXCDR_CFG => X"03000023FF10200020", + RXCDR_FR_RESET_ON_EIDLE => '0', + RXCDR_HOLD_DURING_EIDLE => '1', + RXCDR_LOCK_CFG => B"010101", + RXCDR_PH_RESET_ON_EIDLE => '0', + RXDFELPMRESET_TIME => B"0001111", + RXDLY_CFG => X"001F", + RXDLY_LCFG => X"030", + RXDLY_TAP_CFG => X"0000", + RXGEARBOX_EN => "FALSE", + RXISCANRESET_TIME => B"00001", + RXLPM_HF_CFG => B"00000011110000", + RXLPM_LF_CFG => B"00000011110000", + RXOOB_CFG => B"0000110", + RXOUT_DIV => 2, + RXPCSRESET_TIME => B"00001", + RXPHDLY_CFG => X"004020", + RXPH_CFG => X"000000", + RXPH_MONITOR_SEL => B"00000", + RXPMARESET_TIME => B"00011", + RXPRBS_ERR_LOOPBACK => '0', + RXSLIDE_AUTO_WAIT => 7, + RXSLIDE_MODE => "PMA", + RX_BIAS_CFG => B"000000000100", + RX_BUFFER_CFG => B"000000", + RX_CLK25_DIV => 4, + RX_CLKMUX_PD => '1', + RX_CM_SEL => B"11", + RX_CM_TRIM => B"010", + RX_DATA_WIDTH => 20, + RX_DDI_SEL => B"000000", + RX_DEBUG_CFG => B"000000000000", + RX_DEFER_RESET_BUF_EN => "TRUE", + RX_DFE_GAIN_CFG => X"020FEA", + RX_DFE_H2_CFG => B"000000000000", + RX_DFE_H3_CFG => B"000001000000", + RX_DFE_H4_CFG => B"00011110000", + RX_DFE_H5_CFG => B"00011100000", + RX_DFE_KL_CFG => B"0000011111110", + RX_DFE_KL_CFG2 => X"3290D86C", + RX_DFE_LPM_CFG => X"0954", + RX_DFE_LPM_HOLD_DURING_EIDLE => '1', + RX_DFE_UT_CFG => B"10001111000000000", + RX_DFE_VP_CFG => B"00011111100000011", + RX_DFE_XYD_CFG => B"0000000000000", + RX_DISPERR_SEQ_MATCH => "TRUE", + RX_INT_DATAWIDTH => 0, + RX_OS_CFG => B"0000010000000", + RX_SIG_VALID_DLY => 4, + RX_XCLK_SEL => "RXREC", + SAS_MAX_COM => 64, + SAS_MIN_COM => 36, + SATA_BURST_SEQ_LEN => B"1111", + SATA_BURST_VAL => B"100", + SATA_CPLL_CFG => "VCO_3000MHZ", + SATA_EIDLE_VAL => B"100", + SATA_MAX_BURST => 8, + SATA_MAX_INIT => 21, + SATA_MAX_WAKE => 7, + SATA_MIN_BURST => 4, + SATA_MIN_INIT => 12, + SATA_MIN_WAKE => 4, + SHOW_REALIGN_COMMA => "FALSE", + SIM_CPLLREFCLK_SEL => B"001", + SIM_RECEIVER_DETECT_PASS => "TRUE", + SIM_RESET_SPEEDUP => "FALSE", + SIM_TX_EIDLE_DRIVE_LEVEL => "1", + SIM_VERSION => "3.0", + TERM_RCAL_CFG => B"10000", + TERM_RCAL_OVRD => '0', + TRANS_TIME_RATE => X"0E", + TST_RSV => X"00000000", + TXBUF_EN => "FALSE", + TXBUF_RESET_ON_RATE_CHANGE => "TRUE", + TXDLY_CFG => X"001F", + TXDLY_LCFG => X"030", + TXDLY_TAP_CFG => X"0000", + TXGEARBOX_EN => "FALSE", + TXOUT_DIV => 2, + TXPCSRESET_TIME => B"00001", + TXPHDLY_CFG => X"084020", + TXPH_CFG => X"0780", + TXPH_MONITOR_SEL => B"00000", + TXPMARESET_TIME => B"00011", + TX_CLK25_DIV => 4, + TX_CLKMUX_PD => '1', + TX_DATA_WIDTH => 20, + TX_DEEMPH0 => B"10100", + TX_DEEMPH1 => B"01011", + TX_DRIVE_MODE => "PIPE", + TX_EIDLE_ASSERT_DELAY => B"010", + TX_EIDLE_DEASSERT_DELAY => B"100", + TX_INT_DATAWIDTH => 0, + TX_LOOPBACK_DRIVE_HIZ => "FALSE", + TX_MAINCURSOR_SEL => '0', + TX_MARGIN_FULL_0 => B"1001111", + TX_MARGIN_FULL_1 => B"1001110", + TX_MARGIN_FULL_2 => B"1001101", + TX_MARGIN_FULL_3 => B"1001100", + TX_MARGIN_FULL_4 => B"1000011", + TX_MARGIN_LOW_0 => B"1000101", + TX_MARGIN_LOW_1 => B"1000110", + TX_MARGIN_LOW_2 => B"1000011", + TX_MARGIN_LOW_3 => B"1000010", + TX_MARGIN_LOW_4 => B"1000000", + TX_PREDRIVER_MODE => '0', + TX_QPI_STATUS_EN => '0', + TX_RXDETECT_CFG => X"0064", + TX_RXDETECT_REF => B"011", + TX_XCLK_SEL => "TXUSR", + UCODEER_CLR => '0' + ) + port map ( + CFGRESET => '0', + CLKRSVD(3 downto 1) => B"000", + CLKRSVD(0) => USER_OOBCLK, + CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\, + CPLLLOCK => QRST_CPLLLOCK(0), + CPLLLOCKDETCLK => '0', + CPLLLOCKEN => '1', + CPLLPD => CPLLPD0, + CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\, + CPLLREFCLKSEL(2 downto 0) => B"001", + CPLLRESET => CPLLRESET0, + DMONITOROUT(7) => \gtx_channel.gtxe2_channel_i_n_177\, + DMONITOROUT(6) => \gtx_channel.gtxe2_channel_i_n_178\, + DMONITOROUT(5) => \gtx_channel.gtxe2_channel_i_n_179\, + DMONITOROUT(4) => \gtx_channel.gtxe2_channel_i_n_180\, + DMONITOROUT(3) => \gtx_channel.gtxe2_channel_i_n_181\, + DMONITOROUT(2) => \gtx_channel.gtxe2_channel_i_n_182\, + DMONITOROUT(1) => \gtx_channel.gtxe2_channel_i_n_183\, + DMONITOROUT(0) => \gtx_channel.gtxe2_channel_i_n_184\, + DRPADDR(8) => '0', + DRPADDR(7 downto 0) => DRPADDR(7 downto 0), + DRPCLK => pipe_dclk_in, + DRPDI(15 downto 0) => DRPDI(15 downto 0), + DRPDO(15 downto 0) => DRP_DO(15 downto 0), + DRPEN => \cplllock_reg1_reg[0]\, + DRPRDY => DRP_RDY, + DRPWE => \cplllock_reg1_reg[0]_0\, + EYESCANDATAERROR => \gtx_channel.gtxe2_channel_i_n_4\, + EYESCANMODE => '0', + EYESCANRESET => '0', + EYESCANTRIGGER => '0', + GTGREFCLK => '0', + GTNORTHREFCLK0 => '0', + GTNORTHREFCLK1 => '0', + GTREFCLK0 => sys_clk, + GTREFCLK1 => '0', + GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\, + GTRESETSEL => '0', + GTRSVD(15 downto 0) => B"0000000000000000", + GTRXRESET => DRP_GTXRESET, + GTSOUTHREFCLK0 => '0', + GTSOUTHREFCLK1 => '0', + GTTXRESET => DRP_GTXRESET, + GTXRXN => pci_exp_rxn(0), + GTXRXP => pci_exp_rxp(0), + GTXTXN => pci_exp_txn(0), + GTXTXP => pci_exp_txp(0), + LOOPBACK(2 downto 0) => B"000", + PCSRSVDIN(15 downto 0) => B"0000000000000000", + PCSRSVDIN2(4 downto 0) => B"00000", + PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0), + PHYSTATUS => RATE_PHYSTATUS, + PMARSVDIN(4 downto 0) => B"00000", + PMARSVDIN2(4 downto 0) => B"00000", + QPLLCLK => QPLL_QPLLOUTCLK, + QPLLREFCLK => QPLL_QPLLOUTREFCLK, + RESETOVRD => '0', + RX8B10BEN => rxchbonden_0, + RXBUFRESET => '0', + RXBUFSTATUS(2) => \gtx_channel.gtxe2_channel_i_n_82\, + RXBUFSTATUS(1) => \gtx_channel.gtxe2_channel_i_n_83\, + RXBUFSTATUS(0) => \gtx_channel.gtxe2_channel_i_n_84\, + RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\, + RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\, + RXCDRFREQRESET => '0', + RXCDRHOLD => '0', + RXCDRLOCK => gt_rxcdrlock_0, + RXCDROVRDEN => '0', + RXCDRRESET => '0', + RXCDRRESETRSV => '0', + RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\, + RXCHANISALIGNED => PIPE_RXCHANISALIGNED(0), + RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\, + RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4), + RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\, + RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\, + RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\, + RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\, + RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4), + RXCHARISK(3) => \gtx_channel.gtxe2_channel_i_n_197\, + RXCHARISK(2) => \gtx_channel.gtxe2_channel_i_n_198\, + RXCHARISK(1 downto 0) => gt_rx_data_k_wire_filter(1 downto 0), + RXCHBONDEN => rxchbonden_0, + RXCHBONDI(4 downto 0) => B"00000", + RXCHBONDLEVEL(2 downto 0) => B"001", + RXCHBONDMASTER => rxchbonden_0, + RXCHBONDO(4 downto 0) => RXCHBONDO(4 downto 0), + RXCHBONDSLAVE => '0', + RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0), + RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\, + RXCOMMADET => \gtx_channel.gtxe2_channel_i_n_16\, + RXCOMMADETEN => '1', + RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\, + RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\, + RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32), + RXDATA(31) => \gtx_channel.gtxe2_channel_i_n_138\, + RXDATA(30) => \gtx_channel.gtxe2_channel_i_n_139\, + RXDATA(29) => \gtx_channel.gtxe2_channel_i_n_140\, + RXDATA(28) => \gtx_channel.gtxe2_channel_i_n_141\, + RXDATA(27) => \gtx_channel.gtxe2_channel_i_n_142\, + RXDATA(26) => \gtx_channel.gtxe2_channel_i_n_143\, + RXDATA(25) => \gtx_channel.gtxe2_channel_i_n_144\, + RXDATA(24) => \gtx_channel.gtxe2_channel_i_n_145\, + RXDATA(23) => \gtx_channel.gtxe2_channel_i_n_146\, + RXDATA(22) => \gtx_channel.gtxe2_channel_i_n_147\, + RXDATA(21) => \gtx_channel.gtxe2_channel_i_n_148\, + RXDATA(20) => \gtx_channel.gtxe2_channel_i_n_149\, + RXDATA(19) => \gtx_channel.gtxe2_channel_i_n_150\, + RXDATA(18) => \gtx_channel.gtxe2_channel_i_n_151\, + RXDATA(17) => \gtx_channel.gtxe2_channel_i_n_152\, + RXDATA(16) => \gtx_channel.gtxe2_channel_i_n_153\, + RXDATA(15 downto 0) => gt_rx_data_wire_filter(15 downto 0), + RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\, + RXDDIEN => '0', + RXDFEAGCHOLD => \cplllock_reg1_reg[0]_1\, + RXDFEAGCOVRDEN => '0', + RXDFECM1EN => '0', + RXDFELFHOLD => '0', + RXDFELFOVRDEN => '1', + RXDFELPMRESET => '0', + RXDFETAP2HOLD => '0', + RXDFETAP2OVRDEN => '0', + RXDFETAP3HOLD => '0', + RXDFETAP3OVRDEN => '0', + RXDFETAP4HOLD => '0', + RXDFETAP4OVRDEN => '0', + RXDFETAP5HOLD => '0', + RXDFETAP5OVRDEN => '0', + RXDFEUTHOLD => '0', + RXDFEUTOVRDEN => '0', + RXDFEVPHOLD => '0', + RXDFEVPOVRDEN => '0', + RXDFEVSEN => '0', + RXDFEXYDEN => '0', + RXDFEXYDHOLD => '0', + RXDFEXYDOVRDEN => '0', + RXDISPERR(7) => \gtx_channel.gtxe2_channel_i_n_201\, + RXDISPERR(6) => \gtx_channel.gtxe2_channel_i_n_202\, + RXDISPERR(5) => \gtx_channel.gtxe2_channel_i_n_203\, + RXDISPERR(4) => \gtx_channel.gtxe2_channel_i_n_204\, + RXDISPERR(3) => \gtx_channel.gtxe2_channel_i_n_205\, + RXDISPERR(2) => \gtx_channel.gtxe2_channel_i_n_206\, + RXDISPERR(1) => \gtx_channel.gtxe2_channel_i_n_207\, + RXDISPERR(0) => \gtx_channel.gtxe2_channel_i_n_208\, + RXDLYBYPASS => '1', + RXDLYEN => '0', + RXDLYOVRDEN => '0', + RXDLYSRESET => '0', + RXDLYSRESETDONE => pipe_dclk_in_0, + RXELECIDLE => gt_rx_elec_idle_wire_filter(0), + RXELECIDLEMODE(1 downto 0) => B"00", + RXGEARBOXSLIP => '0', + RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0), + RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\, + RXLPMEN => rxchbonden_0, + RXLPMHFHOLD => '0', + RXLPMHFOVRDEN => '0', + RXLPMLFHOLD => '0', + RXLPMLFKLOVRDEN => '0', + RXMCOMMAALIGNEN => rxchbonden_0, + RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0), + RXMONITORSEL(1 downto 0) => B"00", + RXNOTINTABLE(7) => \gtx_channel.gtxe2_channel_i_n_209\, + RXNOTINTABLE(6) => \gtx_channel.gtxe2_channel_i_n_210\, + RXNOTINTABLE(5) => \gtx_channel.gtxe2_channel_i_n_211\, + RXNOTINTABLE(4) => \gtx_channel.gtxe2_channel_i_n_212\, + RXNOTINTABLE(3) => \gtx_channel.gtxe2_channel_i_n_213\, + RXNOTINTABLE(2) => \gtx_channel.gtxe2_channel_i_n_214\, + RXNOTINTABLE(1) => \gtx_channel.gtxe2_channel_i_n_215\, + RXNOTINTABLE(0) => \gtx_channel.gtxe2_channel_i_n_216\, + RXOOBRESET => '0', + RXOSHOLD => '0', + RXOSOVRDEN => '0', + RXOUTCLK => pipe_rxoutclk_out(0), + RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\, + RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\, + RXOUTCLKSEL(2 downto 0) => B"000", + RXPCOMMAALIGNEN => rxchbonden_0, + RXPCSRESET => '0', + RXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0), + RXPHALIGN => '0', + RXPHALIGNDONE => SYNC_RXPHALIGNDONE_M, + RXPHALIGNEN => '0', + RXPHDLYPD => '0', + RXPHDLYRESET => '0', + RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0), + RXPHOVRDEN => '0', + RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0), + RXPMARESET => rate_txpmareset_0, + RXPOLARITY => PIPE_RXPOLARITY(0), + RXPRBSCNTRESET => '0', + RXPRBSERR => \gtx_channel.gtxe2_channel_i_n_27\, + RXPRBSSEL(2 downto 0) => B"000", + RXQPIEN => '0', + RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\, + RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\, + RXRATE(2 downto 1) => B"00", + RXRATE(0) => RXRATE(0), + RXRATEDONE => RATE_RXRATEDONE, + RXRESETDONE => USER_RXRESETDONE, + RXSLIDE => '0', + RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\, + RXSTATUS(2 downto 0) => PIPE_RXSTATUS(2 downto 0), + RXSYSCLKSEL(1) => '0', + RXSYSCLKSEL(0) => RXSYSCLKSEL(0), + RXUSERRDY => rst_userrdy, + RXUSRCLK => pipe_rxusrclk_in, + RXUSRCLK2 => pipe_rxusrclk_in, + RXVALID => gt_rxvalid_0, + SETERRSTATUS => '0', + TSTIN(19 downto 0) => B"11111111111111111111", + TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0), + TX8B10BBYPASS(7 downto 0) => B"00000000", + TX8B10BEN => rxchbonden_0, + TXBUFDIFFCTRL(2 downto 0) => B"100", + TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0), + TXCHARDISPMODE(7 downto 1) => B"0000000", + TXCHARDISPMODE(0) => PIPE_TXCOMPLIANCE(0), + TXCHARDISPVAL(7 downto 0) => B"00000000", + TXCHARISK(7 downto 2) => B"000000", + TXCHARISK(1 downto 0) => PIPE_TXDATAK(1 downto 0), + TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\, + TXCOMINIT => '0', + TXCOMSAS => '0', + TXCOMWAKE => '0', + TXDATA(63 downto 16) => B"000000000000000000000000000000000000000000000000", + TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0), + TXDEEMPH => pipe_tx_deemph_gt, + TXDETECTRX => pipe_tx_rcvr_det_gt, + TXDIFFCTRL(3 downto 0) => B"1100", + TXDIFFPD => '0', + TXDLYBYPASS => '0', + TXDLYEN => sync_txdlyen_0, + TXDLYHOLD => '0', + TXDLYOVRDEN => '0', + TXDLYSRESET => SYNC_TXDLYSRESET, + TXDLYSRESETDONE => pipe_dclk_in_1, + TXDLYUPDOWN => '0', + TXELECIDLE => PIPE_TXELECIDLE(0), + TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\, + TXHEADER(2 downto 0) => B"000", + TXINHIBIT => '0', + TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0), + TXMARGIN(2 downto 0) => \cplllock_reg1_reg[0]_2\(2 downto 0), + TXOUTCLK => pipe_txoutclk_out, + TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\, + TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\, + TXOUTCLKSEL(2 downto 0) => B"011", + TXPCSRESET => '0', + TXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0), + TXPDELECIDLEMODE => '0', + TXPHALIGN => SYNC_TXPHALIGN, + TXPHALIGNDONE => pipe_dclk_in_2, + TXPHALIGNEN => '1', + TXPHDLYPD => '0', + TXPHDLYRESET => '0', + TXPHDLYTSTCLK => '0', + TXPHINIT => SYNC_TXPHINIT, + TXPHINITDONE => pipe_dclk_in_3, + TXPHOVRDEN => '0', + TXPISOPD => '0', + TXPMARESET => rate_txpmareset_0, + TXPOLARITY => '0', + TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0), + TXPOSTCURSORINV => '0', + TXPRBSFORCEERR => '0', + TXPRBSSEL(2 downto 0) => B"000", + TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0), + TXPRECURSORINV => '0', + TXQPIBIASEN => '0', + TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\, + TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\, + TXQPISTRONGPDOWN => '0', + TXQPIWEAKPUP => '0', + TXRATE(2 downto 1) => B"00", + TXRATE(0) => RXRATE(0), + TXRATEDONE => RATE_TXRATEDONE, + TXRESETDONE => USER_TXRESETDONE, + TXSEQUENCE(6 downto 0) => B"0000000", + TXSTARTSEQ => '0', + TXSWING => '0', + TXSYSCLKSEL(1) => '0', + TXSYSCLKSEL(0) => RXSYSCLKSEL(0), + TXUSERRDY => rst_userrdy, + TXUSRCLK => pipe_pclk_in, + TXUSRCLK2 => pipe_pclk_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gt_wrapper_37 is + port ( + cpllpd_0 : out STD_LOGIC; + QRST_CPLLLOCK : out STD_LOGIC_VECTOR ( 0 to 0 ); + DRP_RDY : out STD_LOGIC; + pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 ); + pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 ); + RATE_PHYSTATUS : out STD_LOGIC; + gt_rxcdrlock_1 : out STD_LOGIC; + PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_dclk_in_0 : out STD_LOGIC; + gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_dclk_in_1 : out STD_LOGIC; + RATE_RXRATEDONE : out STD_LOGIC; + USER_RXRESETDONE : out STD_LOGIC; + gt_rxvalid_1 : out STD_LOGIC; + pipe_dclk_in_2 : out STD_LOGIC; + pipe_dclk_in_3 : out STD_LOGIC; + pipe_dclk_in_4 : out STD_LOGIC; + RATE_TXRATEDONE : out STD_LOGIC; + USER_TXRESETDONE : out STD_LOGIC; + DRP_DO : out STD_LOGIC_VECTOR ( 15 downto 0 ); + pipe_dclk_in_5 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + gt_rx_data_wire_filter : out STD_LOGIC_VECTOR ( 15 downto 0 ); + gt_rx_data_k_wire_filter : out STD_LOGIC_VECTOR ( 1 downto 0 ); + gt_cpllpdrefclk : in STD_LOGIC; + CPLLPD0_3 : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + \cplllock_reg1_reg[1]\ : in STD_LOGIC; + \cplllock_reg1_reg[1]_0\ : in STD_LOGIC; + sys_clk : in STD_LOGIC; + DRP_GTXRESET : in STD_LOGIC; + pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 ); + pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 ); + QPLL_QPLLOUTCLK : in STD_LOGIC; + QPLL_QPLLOUTREFCLK : in STD_LOGIC; + rxchbonden_1 : in STD_LOGIC; + \cplllock_reg1_reg[1]_1\ : in STD_LOGIC; + rate_txpmareset_1 : in STD_LOGIC; + PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 0 to 0 ); + rst_userrdy : in STD_LOGIC; + pipe_rxusrclk_in : in STD_LOGIC; + pipe_tx_deemph_gt : in STD_LOGIC; + pipe_tx_rcvr_det_gt : in STD_LOGIC; + SYNC_TXDLYSRESET : in STD_LOGIC; + PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 ); + SYNC_TXPHALIGN : in STD_LOGIC; + SYNC_TXPHINIT : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 ); + PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 1 downto 0 ); + RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 0 to 0 ); + RXRATE : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cplllock_reg1_reg[1]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + USER_OOBCLK : in STD_LOGIC; + RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 ); + TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 ); + TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 ); + PIPE_TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); + TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 ); + PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DRPADDR : in STD_LOGIC_VECTOR ( 7 downto 0 ); + rate_cpllreset_1 : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_gt_wrapper_37 : entity is "pcie_7x_0_gt_wrapper"; +end pcie_7x_0_pcie_7x_0_gt_wrapper_37; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gt_wrapper_37 is + signal CPLLRESET0 : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_138\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_139\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_140\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_141\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_142\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_143\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_144\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_145\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_146\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_147\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_148\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_149\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_150\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_151\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_152\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_153\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_16\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_177\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_178\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_179\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_180\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_181\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_182\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_183\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_184\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_197\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_198\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_201\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_202\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_203\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_204\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_205\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_206\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_207\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_208\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_209\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_210\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_211\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_212\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_213\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_214\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_215\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_216\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_27\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_37\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_4\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_82\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_83\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_84\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_91\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_92\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_93\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_94\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_95\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE"; +begin +cpllPDInst: entity work.pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_58 + port map ( + CPLLRESET0 => CPLLRESET0, + RST_CPLLRESET => RST_CPLLRESET, + cpllpd_0 => cpllpd_0, + gt_cpllpdrefclk => gt_cpllpdrefclk, + rate_cpllreset_1 => rate_cpllreset_1 + ); +\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL + generic map( + ALIGN_COMMA_DOUBLE => "FALSE", + ALIGN_COMMA_ENABLE => B"1111111111", + ALIGN_COMMA_WORD => 1, + ALIGN_MCOMMA_DET => "TRUE", + ALIGN_MCOMMA_VALUE => B"1010000011", + ALIGN_PCOMMA_DET => "TRUE", + ALIGN_PCOMMA_VALUE => B"0101111100", + CBCC_DATA_SOURCE_SEL => "DECODED", + CHAN_BOND_KEEP_ALIGN => "TRUE", + CHAN_BOND_MAX_SKEW => 7, + CHAN_BOND_SEQ_1_1 => B"0001001010", + CHAN_BOND_SEQ_1_2 => B"0001001010", + CHAN_BOND_SEQ_1_3 => B"0001001010", + CHAN_BOND_SEQ_1_4 => B"0110111100", + CHAN_BOND_SEQ_1_ENABLE => B"1111", + CHAN_BOND_SEQ_2_1 => B"0001000101", + CHAN_BOND_SEQ_2_2 => B"0001000101", + CHAN_BOND_SEQ_2_3 => B"0001000101", + CHAN_BOND_SEQ_2_4 => B"0110111100", + CHAN_BOND_SEQ_2_ENABLE => B"1111", + CHAN_BOND_SEQ_2_USE => "TRUE", + CHAN_BOND_SEQ_LEN => 4, + CLK_CORRECT_USE => "TRUE", + CLK_COR_KEEP_IDLE => "TRUE", + CLK_COR_MAX_LAT => 20, + CLK_COR_MIN_LAT => 18, + CLK_COR_PRECEDENCE => "TRUE", + CLK_COR_REPEAT_WAIT => 0, + CLK_COR_SEQ_1_1 => B"0100011100", + CLK_COR_SEQ_1_2 => B"0000000000", + CLK_COR_SEQ_1_3 => B"0000000000", + CLK_COR_SEQ_1_4 => B"0000000000", + CLK_COR_SEQ_1_ENABLE => B"1111", + CLK_COR_SEQ_2_1 => B"0000000000", + CLK_COR_SEQ_2_2 => B"0000000000", + CLK_COR_SEQ_2_3 => B"0000000000", + CLK_COR_SEQ_2_4 => B"0000000000", + CLK_COR_SEQ_2_ENABLE => B"0000", + CLK_COR_SEQ_2_USE => "FALSE", + CLK_COR_SEQ_LEN => 1, + CPLL_CFG => X"A407CC", + CPLL_FBDIV => 5, + CPLL_FBDIV_45 => 5, + CPLL_INIT_CFG => X"00001E", + CPLL_LOCK_CFG => X"01E8", + CPLL_REFCLK_DIV => 1, + DEC_MCOMMA_DETECT => "TRUE", + DEC_PCOMMA_DETECT => "TRUE", + DEC_VALID_COMMA_ONLY => "FALSE", + DMONITOR_CFG => X"000B01", + ES_CONTROL => B"000000", + ES_ERRDET_EN => "FALSE", + ES_EYE_SCAN_EN => "FALSE", + ES_HORZ_OFFSET => X"000", + ES_PMA_CFG => B"0000000000", + ES_PRESCALE => B"00000", + ES_QUALIFIER => X"00000000000000000000", + ES_QUAL_MASK => X"00000000000000000000", + ES_SDATA_MASK => X"00000000000000000000", + ES_VERT_OFFSET => B"000000000", + FTS_DESKEW_SEQ_ENABLE => B"1111", + FTS_LANE_DESKEW_CFG => B"1111", + FTS_LANE_DESKEW_EN => "TRUE", + GEARBOX_MODE => B"000", + IS_CPLLLOCKDETCLK_INVERTED => '0', + IS_DRPCLK_INVERTED => '0', + IS_GTGREFCLK_INVERTED => '0', + IS_RXUSRCLK2_INVERTED => '0', + IS_RXUSRCLK_INVERTED => '0', + IS_TXPHDLYTSTCLK_INVERTED => '0', + IS_TXUSRCLK2_INVERTED => '0', + IS_TXUSRCLK_INVERTED => '0', + OUTREFCLK_SEL_INV => B"11", + PCS_PCIE_EN => "TRUE", + PCS_RSVD_ATTR => X"0000000001CF", + PD_TRANS_TIME_FROM_P2 => X"03C", + PD_TRANS_TIME_NONE_P2 => X"09", + PD_TRANS_TIME_TO_P2 => X"64", + PMA_RSV => X"00018480", + PMA_RSV2 => X"2050", + PMA_RSV3 => B"00", + PMA_RSV4 => X"00000000", + RXBUFRESET_TIME => B"00001", + RXBUF_ADDR_MODE => "FULL", + RXBUF_EIDLE_HI_CNT => B"0100", + RXBUF_EIDLE_LO_CNT => B"0000", + RXBUF_EN => "TRUE", + RXBUF_RESET_ON_CB_CHANGE => "TRUE", + RXBUF_RESET_ON_COMMAALIGN => "FALSE", + RXBUF_RESET_ON_EIDLE => "TRUE", + RXBUF_RESET_ON_RATE_CHANGE => "TRUE", + RXBUF_THRESH_OVFLW => 61, + RXBUF_THRESH_OVRD => "FALSE", + RXBUF_THRESH_UNDFLW => 4, + RXCDRFREQRESET_TIME => B"00001", + RXCDRPHRESET_TIME => B"00001", + RXCDR_CFG => X"03000023FF10200020", + RXCDR_FR_RESET_ON_EIDLE => '0', + RXCDR_HOLD_DURING_EIDLE => '1', + RXCDR_LOCK_CFG => B"010101", + RXCDR_PH_RESET_ON_EIDLE => '0', + RXDFELPMRESET_TIME => B"0001111", + RXDLY_CFG => X"001F", + RXDLY_LCFG => X"030", + RXDLY_TAP_CFG => X"0000", + RXGEARBOX_EN => "FALSE", + RXISCANRESET_TIME => B"00001", + RXLPM_HF_CFG => B"00000011110000", + RXLPM_LF_CFG => B"00000011110000", + RXOOB_CFG => B"0000110", + RXOUT_DIV => 2, + RXPCSRESET_TIME => B"00001", + RXPHDLY_CFG => X"004020", + RXPH_CFG => X"000000", + RXPH_MONITOR_SEL => B"00000", + RXPMARESET_TIME => B"00011", + RXPRBS_ERR_LOOPBACK => '0', + RXSLIDE_AUTO_WAIT => 7, + RXSLIDE_MODE => "PMA", + RX_BIAS_CFG => B"000000000100", + RX_BUFFER_CFG => B"000000", + RX_CLK25_DIV => 4, + RX_CLKMUX_PD => '1', + RX_CM_SEL => B"11", + RX_CM_TRIM => B"010", + RX_DATA_WIDTH => 20, + RX_DDI_SEL => B"000000", + RX_DEBUG_CFG => B"000000000000", + RX_DEFER_RESET_BUF_EN => "TRUE", + RX_DFE_GAIN_CFG => X"020FEA", + RX_DFE_H2_CFG => B"000000000000", + RX_DFE_H3_CFG => B"000001000000", + RX_DFE_H4_CFG => B"00011110000", + RX_DFE_H5_CFG => B"00011100000", + RX_DFE_KL_CFG => B"0000011111110", + RX_DFE_KL_CFG2 => X"3290D86C", + RX_DFE_LPM_CFG => X"0954", + RX_DFE_LPM_HOLD_DURING_EIDLE => '1', + RX_DFE_UT_CFG => B"10001111000000000", + RX_DFE_VP_CFG => B"00011111100000011", + RX_DFE_XYD_CFG => B"0000000000000", + RX_DISPERR_SEQ_MATCH => "TRUE", + RX_INT_DATAWIDTH => 0, + RX_OS_CFG => B"0000010000000", + RX_SIG_VALID_DLY => 4, + RX_XCLK_SEL => "RXREC", + SAS_MAX_COM => 64, + SAS_MIN_COM => 36, + SATA_BURST_SEQ_LEN => B"1111", + SATA_BURST_VAL => B"100", + SATA_CPLL_CFG => "VCO_3000MHZ", + SATA_EIDLE_VAL => B"100", + SATA_MAX_BURST => 8, + SATA_MAX_INIT => 21, + SATA_MAX_WAKE => 7, + SATA_MIN_BURST => 4, + SATA_MIN_INIT => 12, + SATA_MIN_WAKE => 4, + SHOW_REALIGN_COMMA => "FALSE", + SIM_CPLLREFCLK_SEL => B"001", + SIM_RECEIVER_DETECT_PASS => "TRUE", + SIM_RESET_SPEEDUP => "FALSE", + SIM_TX_EIDLE_DRIVE_LEVEL => "1", + SIM_VERSION => "3.0", + TERM_RCAL_CFG => B"10000", + TERM_RCAL_OVRD => '0', + TRANS_TIME_RATE => X"0E", + TST_RSV => X"00000000", + TXBUF_EN => "FALSE", + TXBUF_RESET_ON_RATE_CHANGE => "TRUE", + TXDLY_CFG => X"001F", + TXDLY_LCFG => X"030", + TXDLY_TAP_CFG => X"0000", + TXGEARBOX_EN => "FALSE", + TXOUT_DIV => 2, + TXPCSRESET_TIME => B"00001", + TXPHDLY_CFG => X"084020", + TXPH_CFG => X"0780", + TXPH_MONITOR_SEL => B"00000", + TXPMARESET_TIME => B"00011", + TX_CLK25_DIV => 4, + TX_CLKMUX_PD => '1', + TX_DATA_WIDTH => 20, + TX_DEEMPH0 => B"10100", + TX_DEEMPH1 => B"01011", + TX_DRIVE_MODE => "PIPE", + TX_EIDLE_ASSERT_DELAY => B"010", + TX_EIDLE_DEASSERT_DELAY => B"100", + TX_INT_DATAWIDTH => 0, + TX_LOOPBACK_DRIVE_HIZ => "FALSE", + TX_MAINCURSOR_SEL => '0', + TX_MARGIN_FULL_0 => B"1001111", + TX_MARGIN_FULL_1 => B"1001110", + TX_MARGIN_FULL_2 => B"1001101", + TX_MARGIN_FULL_3 => B"1001100", + TX_MARGIN_FULL_4 => B"1000011", + TX_MARGIN_LOW_0 => B"1000101", + TX_MARGIN_LOW_1 => B"1000110", + TX_MARGIN_LOW_2 => B"1000011", + TX_MARGIN_LOW_3 => B"1000010", + TX_MARGIN_LOW_4 => B"1000000", + TX_PREDRIVER_MODE => '0', + TX_QPI_STATUS_EN => '0', + TX_RXDETECT_CFG => X"0064", + TX_RXDETECT_REF => B"011", + TX_XCLK_SEL => "TXUSR", + UCODEER_CLR => '0' + ) + port map ( + CFGRESET => '0', + CLKRSVD(3 downto 1) => B"000", + CLKRSVD(0) => USER_OOBCLK, + CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\, + CPLLLOCK => QRST_CPLLLOCK(0), + CPLLLOCKDETCLK => '0', + CPLLLOCKEN => '1', + CPLLPD => CPLLPD0_3, + CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\, + CPLLREFCLKSEL(2 downto 0) => B"001", + CPLLRESET => CPLLRESET0, + DMONITOROUT(7) => \gtx_channel.gtxe2_channel_i_n_177\, + DMONITOROUT(6) => \gtx_channel.gtxe2_channel_i_n_178\, + DMONITOROUT(5) => \gtx_channel.gtxe2_channel_i_n_179\, + DMONITOROUT(4) => \gtx_channel.gtxe2_channel_i_n_180\, + DMONITOROUT(3) => \gtx_channel.gtxe2_channel_i_n_181\, + DMONITOROUT(2) => \gtx_channel.gtxe2_channel_i_n_182\, + DMONITOROUT(1) => \gtx_channel.gtxe2_channel_i_n_183\, + DMONITOROUT(0) => \gtx_channel.gtxe2_channel_i_n_184\, + DRPADDR(8) => '0', + DRPADDR(7 downto 0) => DRPADDR(7 downto 0), + DRPCLK => pipe_dclk_in, + DRPDI(15 downto 0) => DRPDI(15 downto 0), + DRPDO(15 downto 0) => DRP_DO(15 downto 0), + DRPEN => \cplllock_reg1_reg[1]\, + DRPRDY => DRP_RDY, + DRPWE => \cplllock_reg1_reg[1]_0\, + EYESCANDATAERROR => \gtx_channel.gtxe2_channel_i_n_4\, + EYESCANMODE => '0', + EYESCANRESET => '0', + EYESCANTRIGGER => '0', + GTGREFCLK => '0', + GTNORTHREFCLK0 => '0', + GTNORTHREFCLK1 => '0', + GTREFCLK0 => sys_clk, + GTREFCLK1 => '0', + GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\, + GTRESETSEL => '0', + GTRSVD(15 downto 0) => B"0000000000000000", + GTRXRESET => DRP_GTXRESET, + GTSOUTHREFCLK0 => '0', + GTSOUTHREFCLK1 => '0', + GTTXRESET => DRP_GTXRESET, + GTXRXN => pci_exp_rxn(0), + GTXRXP => pci_exp_rxp(0), + GTXTXN => pci_exp_txn(0), + GTXTXP => pci_exp_txp(0), + LOOPBACK(2 downto 0) => B"000", + PCSRSVDIN(15 downto 0) => B"0000000000000000", + PCSRSVDIN2(4 downto 0) => B"00000", + PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0), + PHYSTATUS => RATE_PHYSTATUS, + PMARSVDIN(4 downto 0) => B"00000", + PMARSVDIN2(4 downto 0) => B"00000", + QPLLCLK => QPLL_QPLLOUTCLK, + QPLLREFCLK => QPLL_QPLLOUTREFCLK, + RESETOVRD => '0', + RX8B10BEN => rxchbonden_1, + RXBUFRESET => '0', + RXBUFSTATUS(2) => \gtx_channel.gtxe2_channel_i_n_82\, + RXBUFSTATUS(1) => \gtx_channel.gtxe2_channel_i_n_83\, + RXBUFSTATUS(0) => \gtx_channel.gtxe2_channel_i_n_84\, + RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\, + RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\, + RXCDRFREQRESET => '0', + RXCDRHOLD => '0', + RXCDRLOCK => gt_rxcdrlock_1, + RXCDROVRDEN => '0', + RXCDRRESET => '0', + RXCDRRESETRSV => '0', + RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\, + RXCHANISALIGNED => PIPE_RXCHANISALIGNED(0), + RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\, + RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4), + RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\, + RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\, + RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\, + RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\, + RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4), + RXCHARISK(3) => \gtx_channel.gtxe2_channel_i_n_197\, + RXCHARISK(2) => \gtx_channel.gtxe2_channel_i_n_198\, + RXCHARISK(1 downto 0) => gt_rx_data_k_wire_filter(1 downto 0), + RXCHBONDEN => rxchbonden_1, + RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0), + RXCHBONDLEVEL(2 downto 0) => B"000", + RXCHBONDMASTER => '0', + RXCHBONDO(4) => \gtx_channel.gtxe2_channel_i_n_91\, + RXCHBONDO(3) => \gtx_channel.gtxe2_channel_i_n_92\, + RXCHBONDO(2) => \gtx_channel.gtxe2_channel_i_n_93\, + RXCHBONDO(1) => \gtx_channel.gtxe2_channel_i_n_94\, + RXCHBONDO(0) => \gtx_channel.gtxe2_channel_i_n_95\, + RXCHBONDSLAVE => rxchbonden_1, + RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0), + RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\, + RXCOMMADET => \gtx_channel.gtxe2_channel_i_n_16\, + RXCOMMADETEN => '1', + RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\, + RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\, + RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32), + RXDATA(31) => \gtx_channel.gtxe2_channel_i_n_138\, + RXDATA(30) => \gtx_channel.gtxe2_channel_i_n_139\, + RXDATA(29) => \gtx_channel.gtxe2_channel_i_n_140\, + RXDATA(28) => \gtx_channel.gtxe2_channel_i_n_141\, + RXDATA(27) => \gtx_channel.gtxe2_channel_i_n_142\, + RXDATA(26) => \gtx_channel.gtxe2_channel_i_n_143\, + RXDATA(25) => \gtx_channel.gtxe2_channel_i_n_144\, + RXDATA(24) => \gtx_channel.gtxe2_channel_i_n_145\, + RXDATA(23) => \gtx_channel.gtxe2_channel_i_n_146\, + RXDATA(22) => \gtx_channel.gtxe2_channel_i_n_147\, + RXDATA(21) => \gtx_channel.gtxe2_channel_i_n_148\, + RXDATA(20) => \gtx_channel.gtxe2_channel_i_n_149\, + RXDATA(19) => \gtx_channel.gtxe2_channel_i_n_150\, + RXDATA(18) => \gtx_channel.gtxe2_channel_i_n_151\, + RXDATA(17) => \gtx_channel.gtxe2_channel_i_n_152\, + RXDATA(16) => \gtx_channel.gtxe2_channel_i_n_153\, + RXDATA(15 downto 0) => gt_rx_data_wire_filter(15 downto 0), + RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\, + RXDDIEN => '0', + RXDFEAGCHOLD => \cplllock_reg1_reg[1]_1\, + RXDFEAGCOVRDEN => '0', + RXDFECM1EN => '0', + RXDFELFHOLD => '0', + RXDFELFOVRDEN => '1', + RXDFELPMRESET => '0', + RXDFETAP2HOLD => '0', + RXDFETAP2OVRDEN => '0', + RXDFETAP3HOLD => '0', + RXDFETAP3OVRDEN => '0', + RXDFETAP4HOLD => '0', + RXDFETAP4OVRDEN => '0', + RXDFETAP5HOLD => '0', + RXDFETAP5OVRDEN => '0', + RXDFEUTHOLD => '0', + RXDFEUTOVRDEN => '0', + RXDFEVPHOLD => '0', + RXDFEVPOVRDEN => '0', + RXDFEVSEN => '0', + RXDFEXYDEN => '0', + RXDFEXYDHOLD => '0', + RXDFEXYDOVRDEN => '0', + RXDISPERR(7) => \gtx_channel.gtxe2_channel_i_n_201\, + RXDISPERR(6) => \gtx_channel.gtxe2_channel_i_n_202\, + RXDISPERR(5) => \gtx_channel.gtxe2_channel_i_n_203\, + RXDISPERR(4) => \gtx_channel.gtxe2_channel_i_n_204\, + RXDISPERR(3) => \gtx_channel.gtxe2_channel_i_n_205\, + RXDISPERR(2) => \gtx_channel.gtxe2_channel_i_n_206\, + RXDISPERR(1) => \gtx_channel.gtxe2_channel_i_n_207\, + RXDISPERR(0) => \gtx_channel.gtxe2_channel_i_n_208\, + RXDLYBYPASS => '1', + RXDLYEN => '0', + RXDLYOVRDEN => '0', + RXDLYSRESET => '0', + RXDLYSRESETDONE => pipe_dclk_in_0, + RXELECIDLE => gt_rx_elec_idle_wire_filter(0), + RXELECIDLEMODE(1 downto 0) => B"00", + RXGEARBOXSLIP => '0', + RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0), + RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\, + RXLPMEN => rxchbonden_1, + RXLPMHFHOLD => '0', + RXLPMHFOVRDEN => '0', + RXLPMLFHOLD => '0', + RXLPMLFKLOVRDEN => '0', + RXMCOMMAALIGNEN => rxchbonden_1, + RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0), + RXMONITORSEL(1 downto 0) => B"00", + RXNOTINTABLE(7) => \gtx_channel.gtxe2_channel_i_n_209\, + RXNOTINTABLE(6) => \gtx_channel.gtxe2_channel_i_n_210\, + RXNOTINTABLE(5) => \gtx_channel.gtxe2_channel_i_n_211\, + RXNOTINTABLE(4) => \gtx_channel.gtxe2_channel_i_n_212\, + RXNOTINTABLE(3) => \gtx_channel.gtxe2_channel_i_n_213\, + RXNOTINTABLE(2) => \gtx_channel.gtxe2_channel_i_n_214\, + RXNOTINTABLE(1) => \gtx_channel.gtxe2_channel_i_n_215\, + RXNOTINTABLE(0) => \gtx_channel.gtxe2_channel_i_n_216\, + RXOOBRESET => '0', + RXOSHOLD => '0', + RXOSOVRDEN => '0', + RXOUTCLK => pipe_rxoutclk_out(0), + RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\, + RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\, + RXOUTCLKSEL(2 downto 0) => B"000", + RXPCOMMAALIGNEN => rxchbonden_1, + RXPCSRESET => '0', + RXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0), + RXPHALIGN => '0', + RXPHALIGNDONE => pipe_dclk_in_1, + RXPHALIGNEN => '0', + RXPHDLYPD => '0', + RXPHDLYRESET => '0', + RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0), + RXPHOVRDEN => '0', + RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0), + RXPMARESET => rate_txpmareset_1, + RXPOLARITY => PIPE_RXPOLARITY(0), + RXPRBSCNTRESET => '0', + RXPRBSERR => \gtx_channel.gtxe2_channel_i_n_27\, + RXPRBSSEL(2 downto 0) => B"000", + RXQPIEN => '0', + RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\, + RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\, + RXRATE(2 downto 1) => B"00", + RXRATE(0) => RXRATE(0), + RXRATEDONE => RATE_RXRATEDONE, + RXRESETDONE => USER_RXRESETDONE, + RXSLIDE => '0', + RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\, + RXSTATUS(2 downto 0) => pipe_dclk_in_5(2 downto 0), + RXSYSCLKSEL(1) => '0', + RXSYSCLKSEL(0) => RXSYSCLKSEL(0), + RXUSERRDY => rst_userrdy, + RXUSRCLK => pipe_rxusrclk_in, + RXUSRCLK2 => pipe_rxusrclk_in, + RXVALID => gt_rxvalid_1, + SETERRSTATUS => '0', + TSTIN(19 downto 0) => B"11111111111111111111", + TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0), + TX8B10BBYPASS(7 downto 0) => B"00000000", + TX8B10BEN => rxchbonden_1, + TXBUFDIFFCTRL(2 downto 0) => B"100", + TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0), + TXCHARDISPMODE(7 downto 1) => B"0000000", + TXCHARDISPMODE(0) => PIPE_TXCOMPLIANCE(0), + TXCHARDISPVAL(7 downto 0) => B"00000000", + TXCHARISK(7 downto 2) => B"000000", + TXCHARISK(1 downto 0) => PIPE_TXDATAK(1 downto 0), + TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\, + TXCOMINIT => '0', + TXCOMSAS => '0', + TXCOMWAKE => '0', + TXDATA(63 downto 16) => B"000000000000000000000000000000000000000000000000", + TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0), + TXDEEMPH => pipe_tx_deemph_gt, + TXDETECTRX => pipe_tx_rcvr_det_gt, + TXDIFFCTRL(3 downto 0) => B"1100", + TXDIFFPD => '0', + TXDLYBYPASS => '0', + TXDLYEN => '0', + TXDLYHOLD => '0', + TXDLYOVRDEN => '0', + TXDLYSRESET => SYNC_TXDLYSRESET, + TXDLYSRESETDONE => pipe_dclk_in_2, + TXDLYUPDOWN => '0', + TXELECIDLE => PIPE_TXELECIDLE(0), + TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\, + TXHEADER(2 downto 0) => B"000", + TXINHIBIT => '0', + TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0), + TXMARGIN(2 downto 0) => \cplllock_reg1_reg[1]_2\(2 downto 0), + TXOUTCLK => \gtx_channel.gtxe2_channel_i_n_37\, + TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\, + TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\, + TXOUTCLKSEL(2 downto 0) => B"000", + TXPCSRESET => '0', + TXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0), + TXPDELECIDLEMODE => '0', + TXPHALIGN => SYNC_TXPHALIGN, + TXPHALIGNDONE => pipe_dclk_in_3, + TXPHALIGNEN => '1', + TXPHDLYPD => '0', + TXPHDLYRESET => '0', + TXPHDLYTSTCLK => '0', + TXPHINIT => SYNC_TXPHINIT, + TXPHINITDONE => pipe_dclk_in_4, + TXPHOVRDEN => '0', + TXPISOPD => '0', + TXPMARESET => rate_txpmareset_1, + TXPOLARITY => '0', + TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0), + TXPOSTCURSORINV => '0', + TXPRBSFORCEERR => '0', + TXPRBSSEL(2 downto 0) => B"000", + TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0), + TXPRECURSORINV => '0', + TXQPIBIASEN => '0', + TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\, + TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\, + TXQPISTRONGPDOWN => '0', + TXQPIWEAKPUP => '0', + TXRATE(2 downto 1) => B"00", + TXRATE(0) => RXRATE(0), + TXRATEDONE => RATE_TXRATEDONE, + TXRESETDONE => USER_TXRESETDONE, + TXSEQUENCE(6 downto 0) => B"0000000", + TXSTARTSEQ => '0', + TXSWING => '0', + TXSYSCLKSEL(1) => '0', + TXSYSCLKSEL(0) => RXSYSCLKSEL(0), + TXUSERRDY => rst_userrdy, + TXUSRCLK => pipe_pclk_in, + TXUSRCLK2 => pipe_pclk_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gt_wrapper_43 is + port ( + cpllpd_1 : out STD_LOGIC; + QRST_CPLLLOCK : out STD_LOGIC_VECTOR ( 0 to 0 ); + DRP_RDY : out STD_LOGIC; + pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 ); + pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 ); + RATE_PHYSTATUS : out STD_LOGIC; + gt_rxcdrlock_2 : out STD_LOGIC; + PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_dclk_in_0 : out STD_LOGIC; + gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_dclk_in_1 : out STD_LOGIC; + RATE_RXRATEDONE : out STD_LOGIC; + USER_RXRESETDONE : out STD_LOGIC; + gt_rxvalid_2 : out STD_LOGIC; + pipe_dclk_in_2 : out STD_LOGIC; + pipe_dclk_in_3 : out STD_LOGIC; + pipe_dclk_in_4 : out STD_LOGIC; + RATE_TXRATEDONE : out STD_LOGIC; + USER_TXRESETDONE : out STD_LOGIC; + DRP_DO : out STD_LOGIC_VECTOR ( 15 downto 0 ); + pipe_dclk_in_5 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + gt_rx_data_wire_filter : out STD_LOGIC_VECTOR ( 15 downto 0 ); + gt_rx_data_k_wire_filter : out STD_LOGIC_VECTOR ( 1 downto 0 ); + gt_cpllpdrefclk : in STD_LOGIC; + CPLLPD0_4 : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + \cplllock_reg1_reg[2]\ : in STD_LOGIC; + \cplllock_reg1_reg[2]_0\ : in STD_LOGIC; + sys_clk : in STD_LOGIC; + DRP_GTXRESET : in STD_LOGIC; + pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 ); + pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 ); + QPLL_QPLLOUTCLK : in STD_LOGIC; + QPLL_QPLLOUTREFCLK : in STD_LOGIC; + rxchbonden_2 : in STD_LOGIC; + \cplllock_reg1_reg[2]_1\ : in STD_LOGIC; + rate_txpmareset_2 : in STD_LOGIC; + PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 0 to 0 ); + rst_userrdy : in STD_LOGIC; + pipe_rxusrclk_in : in STD_LOGIC; + pipe_tx_deemph_gt : in STD_LOGIC; + pipe_tx_rcvr_det_gt : in STD_LOGIC; + SYNC_TXDLYSRESET : in STD_LOGIC; + PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 ); + SYNC_TXPHALIGN : in STD_LOGIC; + SYNC_TXPHINIT : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 ); + PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 1 downto 0 ); + RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 0 to 0 ); + RXRATE : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cplllock_reg1_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + USER_OOBCLK : in STD_LOGIC; + RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 ); + TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 ); + TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 ); + PIPE_TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); + TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 ); + PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DRPADDR : in STD_LOGIC_VECTOR ( 7 downto 0 ); + rate_cpllreset_2 : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_gt_wrapper_43 : entity is "pcie_7x_0_gt_wrapper"; +end pcie_7x_0_pcie_7x_0_gt_wrapper_43; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gt_wrapper_43 is + signal CPLLRESET0 : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_138\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_139\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_140\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_141\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_142\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_143\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_144\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_145\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_146\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_147\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_148\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_149\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_150\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_151\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_152\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_153\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_16\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_177\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_178\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_179\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_180\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_181\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_182\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_183\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_184\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_197\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_198\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_201\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_202\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_203\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_204\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_205\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_206\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_207\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_208\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_209\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_210\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_211\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_212\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_213\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_214\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_215\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_216\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_27\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_37\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_4\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_82\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_83\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_84\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_91\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_92\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_93\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_94\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_95\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE"; +begin +cpllPDInst: entity work.pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_56 + port map ( + CPLLRESET0 => CPLLRESET0, + RST_CPLLRESET => RST_CPLLRESET, + cpllpd_1 => cpllpd_1, + gt_cpllpdrefclk => gt_cpllpdrefclk, + rate_cpllreset_2 => rate_cpllreset_2 + ); +\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL + generic map( + ALIGN_COMMA_DOUBLE => "FALSE", + ALIGN_COMMA_ENABLE => B"1111111111", + ALIGN_COMMA_WORD => 1, + ALIGN_MCOMMA_DET => "TRUE", + ALIGN_MCOMMA_VALUE => B"1010000011", + ALIGN_PCOMMA_DET => "TRUE", + ALIGN_PCOMMA_VALUE => B"0101111100", + CBCC_DATA_SOURCE_SEL => "DECODED", + CHAN_BOND_KEEP_ALIGN => "TRUE", + CHAN_BOND_MAX_SKEW => 7, + CHAN_BOND_SEQ_1_1 => B"0001001010", + CHAN_BOND_SEQ_1_2 => B"0001001010", + CHAN_BOND_SEQ_1_3 => B"0001001010", + CHAN_BOND_SEQ_1_4 => B"0110111100", + CHAN_BOND_SEQ_1_ENABLE => B"1111", + CHAN_BOND_SEQ_2_1 => B"0001000101", + CHAN_BOND_SEQ_2_2 => B"0001000101", + CHAN_BOND_SEQ_2_3 => B"0001000101", + CHAN_BOND_SEQ_2_4 => B"0110111100", + CHAN_BOND_SEQ_2_ENABLE => B"1111", + CHAN_BOND_SEQ_2_USE => "TRUE", + CHAN_BOND_SEQ_LEN => 4, + CLK_CORRECT_USE => "TRUE", + CLK_COR_KEEP_IDLE => "TRUE", + CLK_COR_MAX_LAT => 20, + CLK_COR_MIN_LAT => 18, + CLK_COR_PRECEDENCE => "TRUE", + CLK_COR_REPEAT_WAIT => 0, + CLK_COR_SEQ_1_1 => B"0100011100", + CLK_COR_SEQ_1_2 => B"0000000000", + CLK_COR_SEQ_1_3 => B"0000000000", + CLK_COR_SEQ_1_4 => B"0000000000", + CLK_COR_SEQ_1_ENABLE => B"1111", + CLK_COR_SEQ_2_1 => B"0000000000", + CLK_COR_SEQ_2_2 => B"0000000000", + CLK_COR_SEQ_2_3 => B"0000000000", + CLK_COR_SEQ_2_4 => B"0000000000", + CLK_COR_SEQ_2_ENABLE => B"0000", + CLK_COR_SEQ_2_USE => "FALSE", + CLK_COR_SEQ_LEN => 1, + CPLL_CFG => X"A407CC", + CPLL_FBDIV => 5, + CPLL_FBDIV_45 => 5, + CPLL_INIT_CFG => X"00001E", + CPLL_LOCK_CFG => X"01E8", + CPLL_REFCLK_DIV => 1, + DEC_MCOMMA_DETECT => "TRUE", + DEC_PCOMMA_DETECT => "TRUE", + DEC_VALID_COMMA_ONLY => "FALSE", + DMONITOR_CFG => X"000B01", + ES_CONTROL => B"000000", + ES_ERRDET_EN => "FALSE", + ES_EYE_SCAN_EN => "FALSE", + ES_HORZ_OFFSET => X"000", + ES_PMA_CFG => B"0000000000", + ES_PRESCALE => B"00000", + ES_QUALIFIER => X"00000000000000000000", + ES_QUAL_MASK => X"00000000000000000000", + ES_SDATA_MASK => X"00000000000000000000", + ES_VERT_OFFSET => B"000000000", + FTS_DESKEW_SEQ_ENABLE => B"1111", + FTS_LANE_DESKEW_CFG => B"1111", + FTS_LANE_DESKEW_EN => "TRUE", + GEARBOX_MODE => B"000", + IS_CPLLLOCKDETCLK_INVERTED => '0', + IS_DRPCLK_INVERTED => '0', + IS_GTGREFCLK_INVERTED => '0', + IS_RXUSRCLK2_INVERTED => '0', + IS_RXUSRCLK_INVERTED => '0', + IS_TXPHDLYTSTCLK_INVERTED => '0', + IS_TXUSRCLK2_INVERTED => '0', + IS_TXUSRCLK_INVERTED => '0', + OUTREFCLK_SEL_INV => B"11", + PCS_PCIE_EN => "TRUE", + PCS_RSVD_ATTR => X"0000000001CF", + PD_TRANS_TIME_FROM_P2 => X"03C", + PD_TRANS_TIME_NONE_P2 => X"09", + PD_TRANS_TIME_TO_P2 => X"64", + PMA_RSV => X"00018480", + PMA_RSV2 => X"2050", + PMA_RSV3 => B"00", + PMA_RSV4 => X"00000000", + RXBUFRESET_TIME => B"00001", + RXBUF_ADDR_MODE => "FULL", + RXBUF_EIDLE_HI_CNT => B"0100", + RXBUF_EIDLE_LO_CNT => B"0000", + RXBUF_EN => "TRUE", + RXBUF_RESET_ON_CB_CHANGE => "TRUE", + RXBUF_RESET_ON_COMMAALIGN => "FALSE", + RXBUF_RESET_ON_EIDLE => "TRUE", + RXBUF_RESET_ON_RATE_CHANGE => "TRUE", + RXBUF_THRESH_OVFLW => 61, + RXBUF_THRESH_OVRD => "FALSE", + RXBUF_THRESH_UNDFLW => 4, + RXCDRFREQRESET_TIME => B"00001", + RXCDRPHRESET_TIME => B"00001", + RXCDR_CFG => X"03000023FF10200020", + RXCDR_FR_RESET_ON_EIDLE => '0', + RXCDR_HOLD_DURING_EIDLE => '1', + RXCDR_LOCK_CFG => B"010101", + RXCDR_PH_RESET_ON_EIDLE => '0', + RXDFELPMRESET_TIME => B"0001111", + RXDLY_CFG => X"001F", + RXDLY_LCFG => X"030", + RXDLY_TAP_CFG => X"0000", + RXGEARBOX_EN => "FALSE", + RXISCANRESET_TIME => B"00001", + RXLPM_HF_CFG => B"00000011110000", + RXLPM_LF_CFG => B"00000011110000", + RXOOB_CFG => B"0000110", + RXOUT_DIV => 2, + RXPCSRESET_TIME => B"00001", + RXPHDLY_CFG => X"004020", + RXPH_CFG => X"000000", + RXPH_MONITOR_SEL => B"00000", + RXPMARESET_TIME => B"00011", + RXPRBS_ERR_LOOPBACK => '0', + RXSLIDE_AUTO_WAIT => 7, + RXSLIDE_MODE => "PMA", + RX_BIAS_CFG => B"000000000100", + RX_BUFFER_CFG => B"000000", + RX_CLK25_DIV => 4, + RX_CLKMUX_PD => '1', + RX_CM_SEL => B"11", + RX_CM_TRIM => B"010", + RX_DATA_WIDTH => 20, + RX_DDI_SEL => B"000000", + RX_DEBUG_CFG => B"000000000000", + RX_DEFER_RESET_BUF_EN => "TRUE", + RX_DFE_GAIN_CFG => X"020FEA", + RX_DFE_H2_CFG => B"000000000000", + RX_DFE_H3_CFG => B"000001000000", + RX_DFE_H4_CFG => B"00011110000", + RX_DFE_H5_CFG => B"00011100000", + RX_DFE_KL_CFG => B"0000011111110", + RX_DFE_KL_CFG2 => X"3290D86C", + RX_DFE_LPM_CFG => X"0954", + RX_DFE_LPM_HOLD_DURING_EIDLE => '1', + RX_DFE_UT_CFG => B"10001111000000000", + RX_DFE_VP_CFG => B"00011111100000011", + RX_DFE_XYD_CFG => B"0000000000000", + RX_DISPERR_SEQ_MATCH => "TRUE", + RX_INT_DATAWIDTH => 0, + RX_OS_CFG => B"0000010000000", + RX_SIG_VALID_DLY => 4, + RX_XCLK_SEL => "RXREC", + SAS_MAX_COM => 64, + SAS_MIN_COM => 36, + SATA_BURST_SEQ_LEN => B"1111", + SATA_BURST_VAL => B"100", + SATA_CPLL_CFG => "VCO_3000MHZ", + SATA_EIDLE_VAL => B"100", + SATA_MAX_BURST => 8, + SATA_MAX_INIT => 21, + SATA_MAX_WAKE => 7, + SATA_MIN_BURST => 4, + SATA_MIN_INIT => 12, + SATA_MIN_WAKE => 4, + SHOW_REALIGN_COMMA => "FALSE", + SIM_CPLLREFCLK_SEL => B"001", + SIM_RECEIVER_DETECT_PASS => "TRUE", + SIM_RESET_SPEEDUP => "FALSE", + SIM_TX_EIDLE_DRIVE_LEVEL => "1", + SIM_VERSION => "3.0", + TERM_RCAL_CFG => B"10000", + TERM_RCAL_OVRD => '0', + TRANS_TIME_RATE => X"0E", + TST_RSV => X"00000000", + TXBUF_EN => "FALSE", + TXBUF_RESET_ON_RATE_CHANGE => "TRUE", + TXDLY_CFG => X"001F", + TXDLY_LCFG => X"030", + TXDLY_TAP_CFG => X"0000", + TXGEARBOX_EN => "FALSE", + TXOUT_DIV => 2, + TXPCSRESET_TIME => B"00001", + TXPHDLY_CFG => X"084020", + TXPH_CFG => X"0780", + TXPH_MONITOR_SEL => B"00000", + TXPMARESET_TIME => B"00011", + TX_CLK25_DIV => 4, + TX_CLKMUX_PD => '1', + TX_DATA_WIDTH => 20, + TX_DEEMPH0 => B"10100", + TX_DEEMPH1 => B"01011", + TX_DRIVE_MODE => "PIPE", + TX_EIDLE_ASSERT_DELAY => B"010", + TX_EIDLE_DEASSERT_DELAY => B"100", + TX_INT_DATAWIDTH => 0, + TX_LOOPBACK_DRIVE_HIZ => "FALSE", + TX_MAINCURSOR_SEL => '0', + TX_MARGIN_FULL_0 => B"1001111", + TX_MARGIN_FULL_1 => B"1001110", + TX_MARGIN_FULL_2 => B"1001101", + TX_MARGIN_FULL_3 => B"1001100", + TX_MARGIN_FULL_4 => B"1000011", + TX_MARGIN_LOW_0 => B"1000101", + TX_MARGIN_LOW_1 => B"1000110", + TX_MARGIN_LOW_2 => B"1000011", + TX_MARGIN_LOW_3 => B"1000010", + TX_MARGIN_LOW_4 => B"1000000", + TX_PREDRIVER_MODE => '0', + TX_QPI_STATUS_EN => '0', + TX_RXDETECT_CFG => X"0064", + TX_RXDETECT_REF => B"011", + TX_XCLK_SEL => "TXUSR", + UCODEER_CLR => '0' + ) + port map ( + CFGRESET => '0', + CLKRSVD(3 downto 1) => B"000", + CLKRSVD(0) => USER_OOBCLK, + CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\, + CPLLLOCK => QRST_CPLLLOCK(0), + CPLLLOCKDETCLK => '0', + CPLLLOCKEN => '1', + CPLLPD => CPLLPD0_4, + CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\, + CPLLREFCLKSEL(2 downto 0) => B"001", + CPLLRESET => CPLLRESET0, + DMONITOROUT(7) => \gtx_channel.gtxe2_channel_i_n_177\, + DMONITOROUT(6) => \gtx_channel.gtxe2_channel_i_n_178\, + DMONITOROUT(5) => \gtx_channel.gtxe2_channel_i_n_179\, + DMONITOROUT(4) => \gtx_channel.gtxe2_channel_i_n_180\, + DMONITOROUT(3) => \gtx_channel.gtxe2_channel_i_n_181\, + DMONITOROUT(2) => \gtx_channel.gtxe2_channel_i_n_182\, + DMONITOROUT(1) => \gtx_channel.gtxe2_channel_i_n_183\, + DMONITOROUT(0) => \gtx_channel.gtxe2_channel_i_n_184\, + DRPADDR(8) => '0', + DRPADDR(7 downto 0) => DRPADDR(7 downto 0), + DRPCLK => pipe_dclk_in, + DRPDI(15 downto 0) => DRPDI(15 downto 0), + DRPDO(15 downto 0) => DRP_DO(15 downto 0), + DRPEN => \cplllock_reg1_reg[2]\, + DRPRDY => DRP_RDY, + DRPWE => \cplllock_reg1_reg[2]_0\, + EYESCANDATAERROR => \gtx_channel.gtxe2_channel_i_n_4\, + EYESCANMODE => '0', + EYESCANRESET => '0', + EYESCANTRIGGER => '0', + GTGREFCLK => '0', + GTNORTHREFCLK0 => '0', + GTNORTHREFCLK1 => '0', + GTREFCLK0 => sys_clk, + GTREFCLK1 => '0', + GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\, + GTRESETSEL => '0', + GTRSVD(15 downto 0) => B"0000000000000000", + GTRXRESET => DRP_GTXRESET, + GTSOUTHREFCLK0 => '0', + GTSOUTHREFCLK1 => '0', + GTTXRESET => DRP_GTXRESET, + GTXRXN => pci_exp_rxn(0), + GTXRXP => pci_exp_rxp(0), + GTXTXN => pci_exp_txn(0), + GTXTXP => pci_exp_txp(0), + LOOPBACK(2 downto 0) => B"000", + PCSRSVDIN(15 downto 0) => B"0000000000000000", + PCSRSVDIN2(4 downto 0) => B"00000", + PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0), + PHYSTATUS => RATE_PHYSTATUS, + PMARSVDIN(4 downto 0) => B"00000", + PMARSVDIN2(4 downto 0) => B"00000", + QPLLCLK => QPLL_QPLLOUTCLK, + QPLLREFCLK => QPLL_QPLLOUTREFCLK, + RESETOVRD => '0', + RX8B10BEN => rxchbonden_2, + RXBUFRESET => '0', + RXBUFSTATUS(2) => \gtx_channel.gtxe2_channel_i_n_82\, + RXBUFSTATUS(1) => \gtx_channel.gtxe2_channel_i_n_83\, + RXBUFSTATUS(0) => \gtx_channel.gtxe2_channel_i_n_84\, + RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\, + RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\, + RXCDRFREQRESET => '0', + RXCDRHOLD => '0', + RXCDRLOCK => gt_rxcdrlock_2, + RXCDROVRDEN => '0', + RXCDRRESET => '0', + RXCDRRESETRSV => '0', + RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\, + RXCHANISALIGNED => PIPE_RXCHANISALIGNED(0), + RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\, + RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4), + RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\, + RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\, + RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\, + RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\, + RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4), + RXCHARISK(3) => \gtx_channel.gtxe2_channel_i_n_197\, + RXCHARISK(2) => \gtx_channel.gtxe2_channel_i_n_198\, + RXCHARISK(1 downto 0) => gt_rx_data_k_wire_filter(1 downto 0), + RXCHBONDEN => rxchbonden_2, + RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0), + RXCHBONDLEVEL(2 downto 0) => B"000", + RXCHBONDMASTER => '0', + RXCHBONDO(4) => \gtx_channel.gtxe2_channel_i_n_91\, + RXCHBONDO(3) => \gtx_channel.gtxe2_channel_i_n_92\, + RXCHBONDO(2) => \gtx_channel.gtxe2_channel_i_n_93\, + RXCHBONDO(1) => \gtx_channel.gtxe2_channel_i_n_94\, + RXCHBONDO(0) => \gtx_channel.gtxe2_channel_i_n_95\, + RXCHBONDSLAVE => rxchbonden_2, + RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0), + RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\, + RXCOMMADET => \gtx_channel.gtxe2_channel_i_n_16\, + RXCOMMADETEN => '1', + RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\, + RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\, + RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32), + RXDATA(31) => \gtx_channel.gtxe2_channel_i_n_138\, + RXDATA(30) => \gtx_channel.gtxe2_channel_i_n_139\, + RXDATA(29) => \gtx_channel.gtxe2_channel_i_n_140\, + RXDATA(28) => \gtx_channel.gtxe2_channel_i_n_141\, + RXDATA(27) => \gtx_channel.gtxe2_channel_i_n_142\, + RXDATA(26) => \gtx_channel.gtxe2_channel_i_n_143\, + RXDATA(25) => \gtx_channel.gtxe2_channel_i_n_144\, + RXDATA(24) => \gtx_channel.gtxe2_channel_i_n_145\, + RXDATA(23) => \gtx_channel.gtxe2_channel_i_n_146\, + RXDATA(22) => \gtx_channel.gtxe2_channel_i_n_147\, + RXDATA(21) => \gtx_channel.gtxe2_channel_i_n_148\, + RXDATA(20) => \gtx_channel.gtxe2_channel_i_n_149\, + RXDATA(19) => \gtx_channel.gtxe2_channel_i_n_150\, + RXDATA(18) => \gtx_channel.gtxe2_channel_i_n_151\, + RXDATA(17) => \gtx_channel.gtxe2_channel_i_n_152\, + RXDATA(16) => \gtx_channel.gtxe2_channel_i_n_153\, + RXDATA(15 downto 0) => gt_rx_data_wire_filter(15 downto 0), + RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\, + RXDDIEN => '0', + RXDFEAGCHOLD => \cplllock_reg1_reg[2]_1\, + RXDFEAGCOVRDEN => '0', + RXDFECM1EN => '0', + RXDFELFHOLD => '0', + RXDFELFOVRDEN => '1', + RXDFELPMRESET => '0', + RXDFETAP2HOLD => '0', + RXDFETAP2OVRDEN => '0', + RXDFETAP3HOLD => '0', + RXDFETAP3OVRDEN => '0', + RXDFETAP4HOLD => '0', + RXDFETAP4OVRDEN => '0', + RXDFETAP5HOLD => '0', + RXDFETAP5OVRDEN => '0', + RXDFEUTHOLD => '0', + RXDFEUTOVRDEN => '0', + RXDFEVPHOLD => '0', + RXDFEVPOVRDEN => '0', + RXDFEVSEN => '0', + RXDFEXYDEN => '0', + RXDFEXYDHOLD => '0', + RXDFEXYDOVRDEN => '0', + RXDISPERR(7) => \gtx_channel.gtxe2_channel_i_n_201\, + RXDISPERR(6) => \gtx_channel.gtxe2_channel_i_n_202\, + RXDISPERR(5) => \gtx_channel.gtxe2_channel_i_n_203\, + RXDISPERR(4) => \gtx_channel.gtxe2_channel_i_n_204\, + RXDISPERR(3) => \gtx_channel.gtxe2_channel_i_n_205\, + RXDISPERR(2) => \gtx_channel.gtxe2_channel_i_n_206\, + RXDISPERR(1) => \gtx_channel.gtxe2_channel_i_n_207\, + RXDISPERR(0) => \gtx_channel.gtxe2_channel_i_n_208\, + RXDLYBYPASS => '1', + RXDLYEN => '0', + RXDLYOVRDEN => '0', + RXDLYSRESET => '0', + RXDLYSRESETDONE => pipe_dclk_in_0, + RXELECIDLE => gt_rx_elec_idle_wire_filter(0), + RXELECIDLEMODE(1 downto 0) => B"00", + RXGEARBOXSLIP => '0', + RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0), + RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\, + RXLPMEN => rxchbonden_2, + RXLPMHFHOLD => '0', + RXLPMHFOVRDEN => '0', + RXLPMLFHOLD => '0', + RXLPMLFKLOVRDEN => '0', + RXMCOMMAALIGNEN => rxchbonden_2, + RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0), + RXMONITORSEL(1 downto 0) => B"00", + RXNOTINTABLE(7) => \gtx_channel.gtxe2_channel_i_n_209\, + RXNOTINTABLE(6) => \gtx_channel.gtxe2_channel_i_n_210\, + RXNOTINTABLE(5) => \gtx_channel.gtxe2_channel_i_n_211\, + RXNOTINTABLE(4) => \gtx_channel.gtxe2_channel_i_n_212\, + RXNOTINTABLE(3) => \gtx_channel.gtxe2_channel_i_n_213\, + RXNOTINTABLE(2) => \gtx_channel.gtxe2_channel_i_n_214\, + RXNOTINTABLE(1) => \gtx_channel.gtxe2_channel_i_n_215\, + RXNOTINTABLE(0) => \gtx_channel.gtxe2_channel_i_n_216\, + RXOOBRESET => '0', + RXOSHOLD => '0', + RXOSOVRDEN => '0', + RXOUTCLK => pipe_rxoutclk_out(0), + RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\, + RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\, + RXOUTCLKSEL(2 downto 0) => B"000", + RXPCOMMAALIGNEN => rxchbonden_2, + RXPCSRESET => '0', + RXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0), + RXPHALIGN => '0', + RXPHALIGNDONE => pipe_dclk_in_1, + RXPHALIGNEN => '0', + RXPHDLYPD => '0', + RXPHDLYRESET => '0', + RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0), + RXPHOVRDEN => '0', + RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0), + RXPMARESET => rate_txpmareset_2, + RXPOLARITY => PIPE_RXPOLARITY(0), + RXPRBSCNTRESET => '0', + RXPRBSERR => \gtx_channel.gtxe2_channel_i_n_27\, + RXPRBSSEL(2 downto 0) => B"000", + RXQPIEN => '0', + RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\, + RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\, + RXRATE(2 downto 1) => B"00", + RXRATE(0) => RXRATE(0), + RXRATEDONE => RATE_RXRATEDONE, + RXRESETDONE => USER_RXRESETDONE, + RXSLIDE => '0', + RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\, + RXSTATUS(2 downto 0) => pipe_dclk_in_5(2 downto 0), + RXSYSCLKSEL(1) => '0', + RXSYSCLKSEL(0) => RXSYSCLKSEL(0), + RXUSERRDY => rst_userrdy, + RXUSRCLK => pipe_rxusrclk_in, + RXUSRCLK2 => pipe_rxusrclk_in, + RXVALID => gt_rxvalid_2, + SETERRSTATUS => '0', + TSTIN(19 downto 0) => B"11111111111111111111", + TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0), + TX8B10BBYPASS(7 downto 0) => B"00000000", + TX8B10BEN => rxchbonden_2, + TXBUFDIFFCTRL(2 downto 0) => B"100", + TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0), + TXCHARDISPMODE(7 downto 1) => B"0000000", + TXCHARDISPMODE(0) => PIPE_TXCOMPLIANCE(0), + TXCHARDISPVAL(7 downto 0) => B"00000000", + TXCHARISK(7 downto 2) => B"000000", + TXCHARISK(1 downto 0) => PIPE_TXDATAK(1 downto 0), + TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\, + TXCOMINIT => '0', + TXCOMSAS => '0', + TXCOMWAKE => '0', + TXDATA(63 downto 16) => B"000000000000000000000000000000000000000000000000", + TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0), + TXDEEMPH => pipe_tx_deemph_gt, + TXDETECTRX => pipe_tx_rcvr_det_gt, + TXDIFFCTRL(3 downto 0) => B"1100", + TXDIFFPD => '0', + TXDLYBYPASS => '0', + TXDLYEN => '0', + TXDLYHOLD => '0', + TXDLYOVRDEN => '0', + TXDLYSRESET => SYNC_TXDLYSRESET, + TXDLYSRESETDONE => pipe_dclk_in_2, + TXDLYUPDOWN => '0', + TXELECIDLE => PIPE_TXELECIDLE(0), + TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\, + TXHEADER(2 downto 0) => B"000", + TXINHIBIT => '0', + TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0), + TXMARGIN(2 downto 0) => \cplllock_reg1_reg[2]_2\(2 downto 0), + TXOUTCLK => \gtx_channel.gtxe2_channel_i_n_37\, + TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\, + TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\, + TXOUTCLKSEL(2 downto 0) => B"000", + TXPCSRESET => '0', + TXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0), + TXPDELECIDLEMODE => '0', + TXPHALIGN => SYNC_TXPHALIGN, + TXPHALIGNDONE => pipe_dclk_in_3, + TXPHALIGNEN => '1', + TXPHDLYPD => '0', + TXPHDLYRESET => '0', + TXPHDLYTSTCLK => '0', + TXPHINIT => SYNC_TXPHINIT, + TXPHINITDONE => pipe_dclk_in_4, + TXPHOVRDEN => '0', + TXPISOPD => '0', + TXPMARESET => rate_txpmareset_2, + TXPOLARITY => '0', + TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0), + TXPOSTCURSORINV => '0', + TXPRBSFORCEERR => '0', + TXPRBSSEL(2 downto 0) => B"000", + TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0), + TXPRECURSORINV => '0', + TXQPIBIASEN => '0', + TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\, + TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\, + TXQPISTRONGPDOWN => '0', + TXQPIWEAKPUP => '0', + TXRATE(2 downto 1) => B"00", + TXRATE(0) => RXRATE(0), + TXRATEDONE => RATE_TXRATEDONE, + TXRESETDONE => USER_TXRESETDONE, + TXSEQUENCE(6 downto 0) => B"0000000", + TXSTARTSEQ => '0', + TXSWING => '0', + TXSYSCLKSEL(1) => '0', + TXSYSCLKSEL(0) => RXSYSCLKSEL(0), + TXUSERRDY => rst_userrdy, + TXUSRCLK => pipe_pclk_in, + TXUSRCLK2 => pipe_pclk_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gt_wrapper_49 is + port ( + cpllpd_2 : out STD_LOGIC; + QRST_CPLLLOCK : out STD_LOGIC_VECTOR ( 0 to 0 ); + DRP_RDY : out STD_LOGIC; + pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 ); + pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 ); + RATE_PHYSTATUS : out STD_LOGIC; + gt_rxcdrlock_3 : out STD_LOGIC; + PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_dclk_in_0 : out STD_LOGIC; + gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_dclk_in_1 : out STD_LOGIC; + RATE_RXRATEDONE : out STD_LOGIC; + USER_RXRESETDONE : out STD_LOGIC; + gt_rxvalid_3 : out STD_LOGIC; + pipe_dclk_in_2 : out STD_LOGIC; + pipe_dclk_in_3 : out STD_LOGIC; + pipe_dclk_in_4 : out STD_LOGIC; + RATE_TXRATEDONE : out STD_LOGIC; + USER_TXRESETDONE : out STD_LOGIC; + DRP_DO : out STD_LOGIC_VECTOR ( 15 downto 0 ); + pipe_dclk_in_5 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + gt_rx_data_wire_filter : out STD_LOGIC_VECTOR ( 15 downto 0 ); + gt_rx_data_k_wire_filter : out STD_LOGIC_VECTOR ( 1 downto 0 ); + gt_cpllpdrefclk : in STD_LOGIC; + CPLLPD0_5 : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + \cplllock_reg1_reg[3]\ : in STD_LOGIC; + \cplllock_reg1_reg[3]_0\ : in STD_LOGIC; + sys_clk : in STD_LOGIC; + DRP_GTXRESET : in STD_LOGIC; + pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 ); + pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 ); + QPLL_QPLLOUTCLK : in STD_LOGIC; + QPLL_QPLLOUTREFCLK : in STD_LOGIC; + rxchbonden_3 : in STD_LOGIC; + \cplllock_reg1_reg[3]_1\ : in STD_LOGIC; + rate_txpmareset_3 : in STD_LOGIC; + PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 0 to 0 ); + rst_userrdy : in STD_LOGIC; + pipe_rxusrclk_in : in STD_LOGIC; + pipe_tx_deemph_gt : in STD_LOGIC; + pipe_tx_rcvr_det_gt : in STD_LOGIC; + SYNC_TXDLYSRESET : in STD_LOGIC; + PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 ); + SYNC_TXPHALIGN : in STD_LOGIC; + SYNC_TXPHINIT : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 ); + PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 1 downto 0 ); + RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 0 to 0 ); + RXRATE : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cplllock_reg1_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + USER_OOBCLK : in STD_LOGIC; + RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 ); + TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 ); + TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 ); + PIPE_TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); + TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 ); + PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 ); + PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DRPADDR : in STD_LOGIC_VECTOR ( 7 downto 0 ); + rate_cpllreset_3 : in STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_gt_wrapper_49 : entity is "pcie_7x_0_gt_wrapper"; +end pcie_7x_0_pcie_7x_0_gt_wrapper_49; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gt_wrapper_49 is + signal CPLLRESET0 : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_138\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_139\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_140\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_141\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_142\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_143\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_144\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_145\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_146\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_147\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_148\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_149\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_150\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_151\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_152\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_153\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_16\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_177\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_178\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_179\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_180\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_181\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_182\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_183\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_184\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_197\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_198\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_201\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_202\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_203\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_204\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_205\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_206\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_207\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_208\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_209\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_210\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_211\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_212\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_213\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_214\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_215\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_216\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_27\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_37\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_4\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_82\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_83\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_84\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_91\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_92\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_93\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_94\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_n_95\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE"; +begin +cpllPDInst: entity work.pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd + port map ( + CPLLRESET0 => CPLLRESET0, + RST_CPLLRESET => RST_CPLLRESET, + cpllpd_2 => cpllpd_2, + gt_cpllpdrefclk => gt_cpllpdrefclk, + rate_cpllreset_3 => rate_cpllreset_3 + ); +\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL + generic map( + ALIGN_COMMA_DOUBLE => "FALSE", + ALIGN_COMMA_ENABLE => B"1111111111", + ALIGN_COMMA_WORD => 1, + ALIGN_MCOMMA_DET => "TRUE", + ALIGN_MCOMMA_VALUE => B"1010000011", + ALIGN_PCOMMA_DET => "TRUE", + ALIGN_PCOMMA_VALUE => B"0101111100", + CBCC_DATA_SOURCE_SEL => "DECODED", + CHAN_BOND_KEEP_ALIGN => "TRUE", + CHAN_BOND_MAX_SKEW => 7, + CHAN_BOND_SEQ_1_1 => B"0001001010", + CHAN_BOND_SEQ_1_2 => B"0001001010", + CHAN_BOND_SEQ_1_3 => B"0001001010", + CHAN_BOND_SEQ_1_4 => B"0110111100", + CHAN_BOND_SEQ_1_ENABLE => B"1111", + CHAN_BOND_SEQ_2_1 => B"0001000101", + CHAN_BOND_SEQ_2_2 => B"0001000101", + CHAN_BOND_SEQ_2_3 => B"0001000101", + CHAN_BOND_SEQ_2_4 => B"0110111100", + CHAN_BOND_SEQ_2_ENABLE => B"1111", + CHAN_BOND_SEQ_2_USE => "TRUE", + CHAN_BOND_SEQ_LEN => 4, + CLK_CORRECT_USE => "TRUE", + CLK_COR_KEEP_IDLE => "TRUE", + CLK_COR_MAX_LAT => 20, + CLK_COR_MIN_LAT => 18, + CLK_COR_PRECEDENCE => "TRUE", + CLK_COR_REPEAT_WAIT => 0, + CLK_COR_SEQ_1_1 => B"0100011100", + CLK_COR_SEQ_1_2 => B"0000000000", + CLK_COR_SEQ_1_3 => B"0000000000", + CLK_COR_SEQ_1_4 => B"0000000000", + CLK_COR_SEQ_1_ENABLE => B"1111", + CLK_COR_SEQ_2_1 => B"0000000000", + CLK_COR_SEQ_2_2 => B"0000000000", + CLK_COR_SEQ_2_3 => B"0000000000", + CLK_COR_SEQ_2_4 => B"0000000000", + CLK_COR_SEQ_2_ENABLE => B"0000", + CLK_COR_SEQ_2_USE => "FALSE", + CLK_COR_SEQ_LEN => 1, + CPLL_CFG => X"A407CC", + CPLL_FBDIV => 5, + CPLL_FBDIV_45 => 5, + CPLL_INIT_CFG => X"00001E", + CPLL_LOCK_CFG => X"01E8", + CPLL_REFCLK_DIV => 1, + DEC_MCOMMA_DETECT => "TRUE", + DEC_PCOMMA_DETECT => "TRUE", + DEC_VALID_COMMA_ONLY => "FALSE", + DMONITOR_CFG => X"000B01", + ES_CONTROL => B"000000", + ES_ERRDET_EN => "FALSE", + ES_EYE_SCAN_EN => "FALSE", + ES_HORZ_OFFSET => X"000", + ES_PMA_CFG => B"0000000000", + ES_PRESCALE => B"00000", + ES_QUALIFIER => X"00000000000000000000", + ES_QUAL_MASK => X"00000000000000000000", + ES_SDATA_MASK => X"00000000000000000000", + ES_VERT_OFFSET => B"000000000", + FTS_DESKEW_SEQ_ENABLE => B"1111", + FTS_LANE_DESKEW_CFG => B"1111", + FTS_LANE_DESKEW_EN => "TRUE", + GEARBOX_MODE => B"000", + IS_CPLLLOCKDETCLK_INVERTED => '0', + IS_DRPCLK_INVERTED => '0', + IS_GTGREFCLK_INVERTED => '0', + IS_RXUSRCLK2_INVERTED => '0', + IS_RXUSRCLK_INVERTED => '0', + IS_TXPHDLYTSTCLK_INVERTED => '0', + IS_TXUSRCLK2_INVERTED => '0', + IS_TXUSRCLK_INVERTED => '0', + OUTREFCLK_SEL_INV => B"11", + PCS_PCIE_EN => "TRUE", + PCS_RSVD_ATTR => X"0000000001CF", + PD_TRANS_TIME_FROM_P2 => X"03C", + PD_TRANS_TIME_NONE_P2 => X"09", + PD_TRANS_TIME_TO_P2 => X"64", + PMA_RSV => X"00018480", + PMA_RSV2 => X"2050", + PMA_RSV3 => B"00", + PMA_RSV4 => X"00000000", + RXBUFRESET_TIME => B"00001", + RXBUF_ADDR_MODE => "FULL", + RXBUF_EIDLE_HI_CNT => B"0100", + RXBUF_EIDLE_LO_CNT => B"0000", + RXBUF_EN => "TRUE", + RXBUF_RESET_ON_CB_CHANGE => "TRUE", + RXBUF_RESET_ON_COMMAALIGN => "FALSE", + RXBUF_RESET_ON_EIDLE => "TRUE", + RXBUF_RESET_ON_RATE_CHANGE => "TRUE", + RXBUF_THRESH_OVFLW => 61, + RXBUF_THRESH_OVRD => "FALSE", + RXBUF_THRESH_UNDFLW => 4, + RXCDRFREQRESET_TIME => B"00001", + RXCDRPHRESET_TIME => B"00001", + RXCDR_CFG => X"03000023FF10200020", + RXCDR_FR_RESET_ON_EIDLE => '0', + RXCDR_HOLD_DURING_EIDLE => '1', + RXCDR_LOCK_CFG => B"010101", + RXCDR_PH_RESET_ON_EIDLE => '0', + RXDFELPMRESET_TIME => B"0001111", + RXDLY_CFG => X"001F", + RXDLY_LCFG => X"030", + RXDLY_TAP_CFG => X"0000", + RXGEARBOX_EN => "FALSE", + RXISCANRESET_TIME => B"00001", + RXLPM_HF_CFG => B"00000011110000", + RXLPM_LF_CFG => B"00000011110000", + RXOOB_CFG => B"0000110", + RXOUT_DIV => 2, + RXPCSRESET_TIME => B"00001", + RXPHDLY_CFG => X"004020", + RXPH_CFG => X"000000", + RXPH_MONITOR_SEL => B"00000", + RXPMARESET_TIME => B"00011", + RXPRBS_ERR_LOOPBACK => '0', + RXSLIDE_AUTO_WAIT => 7, + RXSLIDE_MODE => "PMA", + RX_BIAS_CFG => B"000000000100", + RX_BUFFER_CFG => B"000000", + RX_CLK25_DIV => 4, + RX_CLKMUX_PD => '1', + RX_CM_SEL => B"11", + RX_CM_TRIM => B"010", + RX_DATA_WIDTH => 20, + RX_DDI_SEL => B"000000", + RX_DEBUG_CFG => B"000000000000", + RX_DEFER_RESET_BUF_EN => "TRUE", + RX_DFE_GAIN_CFG => X"020FEA", + RX_DFE_H2_CFG => B"000000000000", + RX_DFE_H3_CFG => B"000001000000", + RX_DFE_H4_CFG => B"00011110000", + RX_DFE_H5_CFG => B"00011100000", + RX_DFE_KL_CFG => B"0000011111110", + RX_DFE_KL_CFG2 => X"3290D86C", + RX_DFE_LPM_CFG => X"0954", + RX_DFE_LPM_HOLD_DURING_EIDLE => '1', + RX_DFE_UT_CFG => B"10001111000000000", + RX_DFE_VP_CFG => B"00011111100000011", + RX_DFE_XYD_CFG => B"0000000000000", + RX_DISPERR_SEQ_MATCH => "TRUE", + RX_INT_DATAWIDTH => 0, + RX_OS_CFG => B"0000010000000", + RX_SIG_VALID_DLY => 4, + RX_XCLK_SEL => "RXREC", + SAS_MAX_COM => 64, + SAS_MIN_COM => 36, + SATA_BURST_SEQ_LEN => B"1111", + SATA_BURST_VAL => B"100", + SATA_CPLL_CFG => "VCO_3000MHZ", + SATA_EIDLE_VAL => B"100", + SATA_MAX_BURST => 8, + SATA_MAX_INIT => 21, + SATA_MAX_WAKE => 7, + SATA_MIN_BURST => 4, + SATA_MIN_INIT => 12, + SATA_MIN_WAKE => 4, + SHOW_REALIGN_COMMA => "FALSE", + SIM_CPLLREFCLK_SEL => B"001", + SIM_RECEIVER_DETECT_PASS => "TRUE", + SIM_RESET_SPEEDUP => "FALSE", + SIM_TX_EIDLE_DRIVE_LEVEL => "1", + SIM_VERSION => "3.0", + TERM_RCAL_CFG => B"10000", + TERM_RCAL_OVRD => '0', + TRANS_TIME_RATE => X"0E", + TST_RSV => X"00000000", + TXBUF_EN => "FALSE", + TXBUF_RESET_ON_RATE_CHANGE => "TRUE", + TXDLY_CFG => X"001F", + TXDLY_LCFG => X"030", + TXDLY_TAP_CFG => X"0000", + TXGEARBOX_EN => "FALSE", + TXOUT_DIV => 2, + TXPCSRESET_TIME => B"00001", + TXPHDLY_CFG => X"084020", + TXPH_CFG => X"0780", + TXPH_MONITOR_SEL => B"00000", + TXPMARESET_TIME => B"00011", + TX_CLK25_DIV => 4, + TX_CLKMUX_PD => '1', + TX_DATA_WIDTH => 20, + TX_DEEMPH0 => B"10100", + TX_DEEMPH1 => B"01011", + TX_DRIVE_MODE => "PIPE", + TX_EIDLE_ASSERT_DELAY => B"010", + TX_EIDLE_DEASSERT_DELAY => B"100", + TX_INT_DATAWIDTH => 0, + TX_LOOPBACK_DRIVE_HIZ => "FALSE", + TX_MAINCURSOR_SEL => '0', + TX_MARGIN_FULL_0 => B"1001111", + TX_MARGIN_FULL_1 => B"1001110", + TX_MARGIN_FULL_2 => B"1001101", + TX_MARGIN_FULL_3 => B"1001100", + TX_MARGIN_FULL_4 => B"1000011", + TX_MARGIN_LOW_0 => B"1000101", + TX_MARGIN_LOW_1 => B"1000110", + TX_MARGIN_LOW_2 => B"1000011", + TX_MARGIN_LOW_3 => B"1000010", + TX_MARGIN_LOW_4 => B"1000000", + TX_PREDRIVER_MODE => '0', + TX_QPI_STATUS_EN => '0', + TX_RXDETECT_CFG => X"0064", + TX_RXDETECT_REF => B"011", + TX_XCLK_SEL => "TXUSR", + UCODEER_CLR => '0' + ) + port map ( + CFGRESET => '0', + CLKRSVD(3 downto 1) => B"000", + CLKRSVD(0) => USER_OOBCLK, + CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\, + CPLLLOCK => QRST_CPLLLOCK(0), + CPLLLOCKDETCLK => '0', + CPLLLOCKEN => '1', + CPLLPD => CPLLPD0_5, + CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\, + CPLLREFCLKSEL(2 downto 0) => B"001", + CPLLRESET => CPLLRESET0, + DMONITOROUT(7) => \gtx_channel.gtxe2_channel_i_n_177\, + DMONITOROUT(6) => \gtx_channel.gtxe2_channel_i_n_178\, + DMONITOROUT(5) => \gtx_channel.gtxe2_channel_i_n_179\, + DMONITOROUT(4) => \gtx_channel.gtxe2_channel_i_n_180\, + DMONITOROUT(3) => \gtx_channel.gtxe2_channel_i_n_181\, + DMONITOROUT(2) => \gtx_channel.gtxe2_channel_i_n_182\, + DMONITOROUT(1) => \gtx_channel.gtxe2_channel_i_n_183\, + DMONITOROUT(0) => \gtx_channel.gtxe2_channel_i_n_184\, + DRPADDR(8) => '0', + DRPADDR(7 downto 0) => DRPADDR(7 downto 0), + DRPCLK => pipe_dclk_in, + DRPDI(15 downto 0) => DRPDI(15 downto 0), + DRPDO(15 downto 0) => DRP_DO(15 downto 0), + DRPEN => \cplllock_reg1_reg[3]\, + DRPRDY => DRP_RDY, + DRPWE => \cplllock_reg1_reg[3]_0\, + EYESCANDATAERROR => \gtx_channel.gtxe2_channel_i_n_4\, + EYESCANMODE => '0', + EYESCANRESET => '0', + EYESCANTRIGGER => '0', + GTGREFCLK => '0', + GTNORTHREFCLK0 => '0', + GTNORTHREFCLK1 => '0', + GTREFCLK0 => sys_clk, + GTREFCLK1 => '0', + GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\, + GTRESETSEL => '0', + GTRSVD(15 downto 0) => B"0000000000000000", + GTRXRESET => DRP_GTXRESET, + GTSOUTHREFCLK0 => '0', + GTSOUTHREFCLK1 => '0', + GTTXRESET => DRP_GTXRESET, + GTXRXN => pci_exp_rxn(0), + GTXRXP => pci_exp_rxp(0), + GTXTXN => pci_exp_txn(0), + GTXTXP => pci_exp_txp(0), + LOOPBACK(2 downto 0) => B"000", + PCSRSVDIN(15 downto 0) => B"0000000000000000", + PCSRSVDIN2(4 downto 0) => B"00000", + PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0), + PHYSTATUS => RATE_PHYSTATUS, + PMARSVDIN(4 downto 0) => B"00000", + PMARSVDIN2(4 downto 0) => B"00000", + QPLLCLK => QPLL_QPLLOUTCLK, + QPLLREFCLK => QPLL_QPLLOUTREFCLK, + RESETOVRD => '0', + RX8B10BEN => rxchbonden_3, + RXBUFRESET => '0', + RXBUFSTATUS(2) => \gtx_channel.gtxe2_channel_i_n_82\, + RXBUFSTATUS(1) => \gtx_channel.gtxe2_channel_i_n_83\, + RXBUFSTATUS(0) => \gtx_channel.gtxe2_channel_i_n_84\, + RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\, + RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\, + RXCDRFREQRESET => '0', + RXCDRHOLD => '0', + RXCDRLOCK => gt_rxcdrlock_3, + RXCDROVRDEN => '0', + RXCDRRESET => '0', + RXCDRRESETRSV => '0', + RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\, + RXCHANISALIGNED => PIPE_RXCHANISALIGNED(0), + RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\, + RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4), + RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\, + RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\, + RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\, + RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\, + RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4), + RXCHARISK(3) => \gtx_channel.gtxe2_channel_i_n_197\, + RXCHARISK(2) => \gtx_channel.gtxe2_channel_i_n_198\, + RXCHARISK(1 downto 0) => gt_rx_data_k_wire_filter(1 downto 0), + RXCHBONDEN => rxchbonden_3, + RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0), + RXCHBONDLEVEL(2 downto 0) => B"000", + RXCHBONDMASTER => '0', + RXCHBONDO(4) => \gtx_channel.gtxe2_channel_i_n_91\, + RXCHBONDO(3) => \gtx_channel.gtxe2_channel_i_n_92\, + RXCHBONDO(2) => \gtx_channel.gtxe2_channel_i_n_93\, + RXCHBONDO(1) => \gtx_channel.gtxe2_channel_i_n_94\, + RXCHBONDO(0) => \gtx_channel.gtxe2_channel_i_n_95\, + RXCHBONDSLAVE => rxchbonden_3, + RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0), + RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\, + RXCOMMADET => \gtx_channel.gtxe2_channel_i_n_16\, + RXCOMMADETEN => '1', + RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\, + RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\, + RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32), + RXDATA(31) => \gtx_channel.gtxe2_channel_i_n_138\, + RXDATA(30) => \gtx_channel.gtxe2_channel_i_n_139\, + RXDATA(29) => \gtx_channel.gtxe2_channel_i_n_140\, + RXDATA(28) => \gtx_channel.gtxe2_channel_i_n_141\, + RXDATA(27) => \gtx_channel.gtxe2_channel_i_n_142\, + RXDATA(26) => \gtx_channel.gtxe2_channel_i_n_143\, + RXDATA(25) => \gtx_channel.gtxe2_channel_i_n_144\, + RXDATA(24) => \gtx_channel.gtxe2_channel_i_n_145\, + RXDATA(23) => \gtx_channel.gtxe2_channel_i_n_146\, + RXDATA(22) => \gtx_channel.gtxe2_channel_i_n_147\, + RXDATA(21) => \gtx_channel.gtxe2_channel_i_n_148\, + RXDATA(20) => \gtx_channel.gtxe2_channel_i_n_149\, + RXDATA(19) => \gtx_channel.gtxe2_channel_i_n_150\, + RXDATA(18) => \gtx_channel.gtxe2_channel_i_n_151\, + RXDATA(17) => \gtx_channel.gtxe2_channel_i_n_152\, + RXDATA(16) => \gtx_channel.gtxe2_channel_i_n_153\, + RXDATA(15 downto 0) => gt_rx_data_wire_filter(15 downto 0), + RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\, + RXDDIEN => '0', + RXDFEAGCHOLD => \cplllock_reg1_reg[3]_1\, + RXDFEAGCOVRDEN => '0', + RXDFECM1EN => '0', + RXDFELFHOLD => '0', + RXDFELFOVRDEN => '1', + RXDFELPMRESET => '0', + RXDFETAP2HOLD => '0', + RXDFETAP2OVRDEN => '0', + RXDFETAP3HOLD => '0', + RXDFETAP3OVRDEN => '0', + RXDFETAP4HOLD => '0', + RXDFETAP4OVRDEN => '0', + RXDFETAP5HOLD => '0', + RXDFETAP5OVRDEN => '0', + RXDFEUTHOLD => '0', + RXDFEUTOVRDEN => '0', + RXDFEVPHOLD => '0', + RXDFEVPOVRDEN => '0', + RXDFEVSEN => '0', + RXDFEXYDEN => '0', + RXDFEXYDHOLD => '0', + RXDFEXYDOVRDEN => '0', + RXDISPERR(7) => \gtx_channel.gtxe2_channel_i_n_201\, + RXDISPERR(6) => \gtx_channel.gtxe2_channel_i_n_202\, + RXDISPERR(5) => \gtx_channel.gtxe2_channel_i_n_203\, + RXDISPERR(4) => \gtx_channel.gtxe2_channel_i_n_204\, + RXDISPERR(3) => \gtx_channel.gtxe2_channel_i_n_205\, + RXDISPERR(2) => \gtx_channel.gtxe2_channel_i_n_206\, + RXDISPERR(1) => \gtx_channel.gtxe2_channel_i_n_207\, + RXDISPERR(0) => \gtx_channel.gtxe2_channel_i_n_208\, + RXDLYBYPASS => '1', + RXDLYEN => '0', + RXDLYOVRDEN => '0', + RXDLYSRESET => '0', + RXDLYSRESETDONE => pipe_dclk_in_0, + RXELECIDLE => gt_rx_elec_idle_wire_filter(0), + RXELECIDLEMODE(1 downto 0) => B"00", + RXGEARBOXSLIP => '0', + RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0), + RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\, + RXLPMEN => rxchbonden_3, + RXLPMHFHOLD => '0', + RXLPMHFOVRDEN => '0', + RXLPMLFHOLD => '0', + RXLPMLFKLOVRDEN => '0', + RXMCOMMAALIGNEN => rxchbonden_3, + RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0), + RXMONITORSEL(1 downto 0) => B"00", + RXNOTINTABLE(7) => \gtx_channel.gtxe2_channel_i_n_209\, + RXNOTINTABLE(6) => \gtx_channel.gtxe2_channel_i_n_210\, + RXNOTINTABLE(5) => \gtx_channel.gtxe2_channel_i_n_211\, + RXNOTINTABLE(4) => \gtx_channel.gtxe2_channel_i_n_212\, + RXNOTINTABLE(3) => \gtx_channel.gtxe2_channel_i_n_213\, + RXNOTINTABLE(2) => \gtx_channel.gtxe2_channel_i_n_214\, + RXNOTINTABLE(1) => \gtx_channel.gtxe2_channel_i_n_215\, + RXNOTINTABLE(0) => \gtx_channel.gtxe2_channel_i_n_216\, + RXOOBRESET => '0', + RXOSHOLD => '0', + RXOSOVRDEN => '0', + RXOUTCLK => pipe_rxoutclk_out(0), + RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\, + RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\, + RXOUTCLKSEL(2 downto 0) => B"000", + RXPCOMMAALIGNEN => rxchbonden_3, + RXPCSRESET => '0', + RXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0), + RXPHALIGN => '0', + RXPHALIGNDONE => pipe_dclk_in_1, + RXPHALIGNEN => '0', + RXPHDLYPD => '0', + RXPHDLYRESET => '0', + RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0), + RXPHOVRDEN => '0', + RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0), + RXPMARESET => rate_txpmareset_3, + RXPOLARITY => PIPE_RXPOLARITY(0), + RXPRBSCNTRESET => '0', + RXPRBSERR => \gtx_channel.gtxe2_channel_i_n_27\, + RXPRBSSEL(2 downto 0) => B"000", + RXQPIEN => '0', + RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\, + RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\, + RXRATE(2 downto 1) => B"00", + RXRATE(0) => RXRATE(0), + RXRATEDONE => RATE_RXRATEDONE, + RXRESETDONE => USER_RXRESETDONE, + RXSLIDE => '0', + RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\, + RXSTATUS(2 downto 0) => pipe_dclk_in_5(2 downto 0), + RXSYSCLKSEL(1) => '0', + RXSYSCLKSEL(0) => RXSYSCLKSEL(0), + RXUSERRDY => rst_userrdy, + RXUSRCLK => pipe_rxusrclk_in, + RXUSRCLK2 => pipe_rxusrclk_in, + RXVALID => gt_rxvalid_3, + SETERRSTATUS => '0', + TSTIN(19 downto 0) => B"11111111111111111111", + TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0), + TX8B10BBYPASS(7 downto 0) => B"00000000", + TX8B10BEN => rxchbonden_3, + TXBUFDIFFCTRL(2 downto 0) => B"100", + TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0), + TXCHARDISPMODE(7 downto 1) => B"0000000", + TXCHARDISPMODE(0) => PIPE_TXCOMPLIANCE(0), + TXCHARDISPVAL(7 downto 0) => B"00000000", + TXCHARISK(7 downto 2) => B"000000", + TXCHARISK(1 downto 0) => PIPE_TXDATAK(1 downto 0), + TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\, + TXCOMINIT => '0', + TXCOMSAS => '0', + TXCOMWAKE => '0', + TXDATA(63 downto 16) => B"000000000000000000000000000000000000000000000000", + TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0), + TXDEEMPH => pipe_tx_deemph_gt, + TXDETECTRX => pipe_tx_rcvr_det_gt, + TXDIFFCTRL(3 downto 0) => B"1100", + TXDIFFPD => '0', + TXDLYBYPASS => '0', + TXDLYEN => '0', + TXDLYHOLD => '0', + TXDLYOVRDEN => '0', + TXDLYSRESET => SYNC_TXDLYSRESET, + TXDLYSRESETDONE => pipe_dclk_in_2, + TXDLYUPDOWN => '0', + TXELECIDLE => PIPE_TXELECIDLE(0), + TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\, + TXHEADER(2 downto 0) => B"000", + TXINHIBIT => '0', + TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0), + TXMARGIN(2 downto 0) => \cplllock_reg1_reg[3]_2\(2 downto 0), + TXOUTCLK => \gtx_channel.gtxe2_channel_i_n_37\, + TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\, + TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\, + TXOUTCLKSEL(2 downto 0) => B"000", + TXPCSRESET => '0', + TXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0), + TXPDELECIDLEMODE => '0', + TXPHALIGN => SYNC_TXPHALIGN, + TXPHALIGNDONE => pipe_dclk_in_3, + TXPHALIGNEN => '1', + TXPHDLYPD => '0', + TXPHDLYRESET => '0', + TXPHDLYTSTCLK => '0', + TXPHINIT => SYNC_TXPHINIT, + TXPHINITDONE => pipe_dclk_in_4, + TXPHOVRDEN => '0', + TXPISOPD => '0', + TXPMARESET => rate_txpmareset_3, + TXPOLARITY => '0', + TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0), + TXPOSTCURSORINV => '0', + TXPRBSFORCEERR => '0', + TXPRBSSEL(2 downto 0) => B"000", + TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0), + TXPRECURSORINV => '0', + TXQPIBIASEN => '0', + TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\, + TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\, + TXQPISTRONGPDOWN => '0', + TXQPIWEAKPUP => '0', + TXRATE(2 downto 1) => B"00", + TXRATE(0) => RXRATE(0), + TXRATEDONE => RATE_TXRATEDONE, + TXRESETDONE => USER_TXRESETDONE, + TXSEQUENCE(6 downto 0) => B"0000000", + TXSTARTSEQ => '0', + TXSWING => '0', + TXSYSCLKSEL(1) => '0', + TXSYSCLKSEL(0) => RXSYSCLKSEL(0), + TXUSERRDY => rst_userrdy, + TXUSRCLK => pipe_pclk_in, + TXUSRCLK2 => pipe_pclk_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_pcie_bram_7x; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_17 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(8 downto 0), + wdata(8 downto 0) => wdata(8 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_10 is + port ( + rdata : out STD_LOGIC_VECTOR ( 5 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 5 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_10 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_10; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_10 is +begin +\use_tdp.ramb36\: entity work.\pcie_7x_0_BRAM_TDP_MACRO_viv_\ + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(5 downto 0) => rdata(5 downto 0), + wdata(5 downto 0) => wdata(5 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_18 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_18 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_18; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_18 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_33 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_19 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_19 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_19; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_19 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_32 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_20 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_20 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_20; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_20 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_31 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_21 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_21 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_21; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_21 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_30 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_22 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_22 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_22; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_22 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_29 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_23 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_23 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_23; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_23 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_28 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_24 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_24 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_24; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_24 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_27 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_25 is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_25 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_25; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_25 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_26 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(4 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(4 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(4 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(4 downto 0), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_4 is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_4 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_4; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_4 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_16 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(8 downto 0), + wdata(8 downto 0) => wdata(8 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_5 is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_5 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_5; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_5 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_15 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(8 downto 0), + wdata(8 downto 0) => wdata(8 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_6 is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_6 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_6; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_6 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_14 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(8 downto 0), + wdata(8 downto 0) => wdata(8 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_7 is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_7 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_7; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_7 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_13 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(8 downto 0), + wdata(8 downto 0) => wdata(8 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_8 is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_8 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_8; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_8 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_12 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(8 downto 0), + wdata(8 downto 0) => wdata(8 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_7x_9 is + port ( + rdata : out STD_LOGIC_VECTOR ( 8 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_bram_7x_9 : entity is "pcie_7x_0_pcie_bram_7x"; +end pcie_7x_0_pcie_7x_0_pcie_bram_7x_9; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_7x_9 is +begin +\use_tdp.ramb36\: entity work.pcie_7x_0_BRAM_TDP_MACRO_11 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(8 downto 0), + wdata(8 downto 0) => wdata(8 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_pipe_pipeline is + port ( + pipe_rx1_valid : out STD_LOGIC; + pipe_rx1_chanisaligned : out STD_LOGIC; + pipe_rx1_phy_status : out STD_LOGIC; + pipe_rx1_elec_idle : out STD_LOGIC; + PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 3 downto 0 ); + PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_rx2_valid : out STD_LOGIC; + pipe_rx2_chanisaligned : out STD_LOGIC; + pipe_rx2_phy_status : out STD_LOGIC; + pipe_rx2_elec_idle : out STD_LOGIC; + pipe_rx3_valid : out STD_LOGIC; + pipe_rx3_chanisaligned : out STD_LOGIC; + pipe_rx3_phy_status : out STD_LOGIC; + pipe_rx3_elec_idle : out STD_LOGIC; + pipe_tx_rcvr_det_gt : out STD_LOGIC; + \pipe_stages_1.pipe_tx_rate_q_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_tx_deemph_gt : out STD_LOGIC; + pipe_rx0_valid : out STD_LOGIC; + pipe_rx0_chanisaligned : out STD_LOGIC; + pipe_rx0_phy_status : out STD_LOGIC; + pipe_rx0_elec_idle : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 7 downto 0 ); + PIPE_TXDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_1\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \pipe_stages_1.pipe_tx_margin_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_2\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rx1_valid_gt : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \pipe_stages_1.pipe_rx_phy_status_q_reg\ : in STD_LOGIC; + \pipe_stages_1.pipe_rx_elec_idle_q_reg\ : in STD_LOGIC; + pipe_rx0_polarity : in STD_LOGIC; + pipe_rx1_polarity : in STD_LOGIC; + pipe_rx2_polarity : in STD_LOGIC; + pipe_rx3_polarity : in STD_LOGIC; + pipe_tx0_compliance : in STD_LOGIC; + pipe_tx1_compliance : in STD_LOGIC; + pipe_tx2_compliance : in STD_LOGIC; + pipe_tx3_compliance : in STD_LOGIC; + pipe_tx0_elec_idle : in STD_LOGIC; + pipe_tx1_elec_idle : in STD_LOGIC; + pipe_tx2_elec_idle : in STD_LOGIC; + pipe_tx3_elec_idle : in STD_LOGIC; + pipe_rx2_valid_gt : in STD_LOGIC; + \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ : in STD_LOGIC; + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ : in STD_LOGIC; + pipe_rx3_valid_gt : in STD_LOGIC; + \pipe_stages_1.pipe_rx_phy_status_q_reg_1\ : in STD_LOGIC; + \pipe_stages_1.pipe_rx_elec_idle_q_reg_1\ : in STD_LOGIC; + pipe_tx_rcvr_det : in STD_LOGIC; + pipe_tx_rate : in STD_LOGIC; + pipe_tx_deemph : in STD_LOGIC; + pipe_rx0_valid_gt : in STD_LOGIC; + gt_rx_phy_status_q : in STD_LOGIC; + gt_rxelecidle_q : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_3\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_tx_data_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_tx_data_q_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_tx_data_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_tx_data_q_reg[15]_2\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_4\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_4\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_5\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_5\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_6\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_6\ : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_pcie_pipe_pipeline; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_pipe_pipeline is +begin +\pipe_2_lane.pipe_lane_1_i\: entity work.pcie_7x_0_pcie_7x_0_pcie_pipe_lane + port map ( + D(1 downto 0) => D(1 downto 0), + PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(3 downto 2), + PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(1), + PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(1), + PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(1), + PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(31 downto 16), + PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(3 downto 2), + PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(1), + Q(1 downto 0) => Q(1 downto 0), + SR(0) => SR(0), + pipe_pclk_in => pipe_pclk_in, + pipe_rx1_chanisaligned => pipe_rx1_chanisaligned, + pipe_rx1_elec_idle => pipe_rx1_elec_idle, + pipe_rx1_phy_status => pipe_rx1_phy_status, + pipe_rx1_polarity => pipe_rx1_polarity, + pipe_rx1_valid => pipe_rx1_valid, + pipe_rx1_valid_gt => pipe_rx1_valid_gt, + \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_3\(15 downto 0), + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg\, + \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ => \pipe_stages_1.pipe_rx_phy_status_q_reg\, + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0), + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_3\(2 downto 0), + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1 downto 0), + \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15 downto 0) => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15 downto 0), + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1 downto 0), + pipe_tx1_compliance => pipe_tx1_compliance, + pipe_tx1_elec_idle => pipe_tx1_elec_idle + ); +\pipe_4_lane.pipe_lane_2_i\: entity work.pcie_7x_0_pcie_7x_0_pcie_pipe_lane_0 + port map ( + PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(5 downto 4), + PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(2), + PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(2), + PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(2), + PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(47 downto 32), + PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(5 downto 4), + PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(2), + SR(0) => SR(0), + pipe_pclk_in => pipe_pclk_in, + pipe_rx2_chanisaligned => pipe_rx2_chanisaligned, + pipe_rx2_elec_idle => pipe_rx2_elec_idle, + pipe_rx2_phy_status => pipe_rx2_phy_status, + pipe_rx2_polarity => pipe_rx2_polarity, + pipe_rx2_valid => pipe_rx2_valid, + pipe_rx2_valid_gt => pipe_rx2_valid_gt, + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0), + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2\(1 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_4\(15 downto 0), + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\, + \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ => \pipe_stages_1.pipe_rx_phy_status_q_reg_0\, + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0), + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_4\(2 downto 0), + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\(1 downto 0), + \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15 downto 0) => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(15 downto 0), + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\(1 downto 0), + pipe_tx2_compliance => pipe_tx2_compliance, + pipe_tx2_elec_idle => pipe_tx2_elec_idle + ); +\pipe_4_lane.pipe_lane_3_i\: entity work.pcie_7x_0_pcie_7x_0_pcie_pipe_lane_1 + port map ( + PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(7 downto 6), + PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(3), + PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(3), + PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(3), + PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(63 downto 48), + PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(7 downto 6), + PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(3), + SR(0) => SR(0), + pipe_pclk_in => pipe_pclk_in, + pipe_rx3_chanisaligned => pipe_rx3_chanisaligned, + pipe_rx3_elec_idle => pipe_rx3_elec_idle, + pipe_rx3_phy_status => pipe_rx3_phy_status, + pipe_rx3_polarity => pipe_rx3_polarity, + pipe_rx3_valid => pipe_rx3_valid, + pipe_rx3_valid_gt => pipe_rx3_valid_gt, + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0), + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3\(1 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_5\(15 downto 0), + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg_1\, + \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ => \pipe_stages_1.pipe_rx_phy_status_q_reg_1\, + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0), + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_5\(2 downto 0), + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2\(1 downto 0), + \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15 downto 0) => \pipe_stages_1.pipe_tx_data_q_reg[15]_2\(15 downto 0), + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2\(1 downto 0), + pipe_tx3_compliance => pipe_tx3_compliance, + pipe_tx3_elec_idle => pipe_tx3_elec_idle + ); +pipe_lane_0_i: entity work.pcie_7x_0_pcie_7x_0_pcie_pipe_lane_2 + port map ( + PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(1 downto 0), + PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(0), + PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(0), + PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(0), + PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0), + PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(1 downto 0), + PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(0), + SR(0) => SR(0), + gt_rx_phy_status_q => gt_rx_phy_status_q, + gt_rxelecidle_q => gt_rxelecidle_q, + pipe_pclk_in => pipe_pclk_in, + pipe_rx0_chanisaligned => pipe_rx0_chanisaligned, + pipe_rx0_elec_idle => pipe_rx0_elec_idle, + pipe_rx0_phy_status => pipe_rx0_phy_status, + pipe_rx0_polarity => pipe_rx0_polarity, + pipe_rx0_valid => pipe_rx0_valid, + pipe_rx0_valid_gt => pipe_rx0_valid_gt, + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0), + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4\(1 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_2\(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_6\(15 downto 0), + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(2 downto 0), + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_6\(2 downto 0), + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\(1 downto 0), + \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15 downto 0) => \pipe_stages_1.pipe_tx_data_q_reg[15]\(15 downto 0), + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]\(1 downto 0), + pipe_tx0_compliance => pipe_tx0_compliance, + pipe_tx0_elec_idle => pipe_tx0_elec_idle + ); +pipe_misc_i: entity work.pcie_7x_0_pcie_7x_0_pcie_pipe_misc + port map ( + SR(0) => SR(0), + pipe_pclk_in => pipe_pclk_in, + \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0), + \pipe_stages_1.pipe_tx_margin_q_reg[2]_1\(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\(2 downto 0), + \pipe_stages_1.pipe_tx_rate_q_reg_0\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0), + pipe_tx_deemph => pipe_tx_deemph, + pipe_tx_deemph_gt => pipe_tx_deemph_gt, + pipe_tx_rate => pipe_tx_rate, + pipe_tx_rcvr_det => pipe_tx_rcvr_det, + pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_eq is + port ( + TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 ); + TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 ); + TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 ); + USER_RXEQ_ADAPT_DONE : out STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + USER_RATE_GEN3 : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_pipe_eq; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_eq is + signal \FSM_onehot_fsm_rx[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[1]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[3]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[4]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[5]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[6]\ : STD_LOGIC; + signal \FSM_sequential_fsm_tx[1]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_fsm_tx[2]_i_2_n_0\ : STD_LOGIC; + signal \^user_rxeq_adapt_done\ : STD_LOGIC; + signal fsm_tx : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \fsm_tx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal gen3_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of gen3_reg1 : signal is "true"; + signal gen3_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO"; + attribute async_reg of gen3_reg2 : signal is "true"; + signal p_0_out : STD_LOGIC_VECTOR ( 17 downto 0 ); + signal rxeq_adapt_done_i_2_n_0 : STD_LOGIC; + signal rxeq_adapt_done_reg_i_2_n_0 : STD_LOGIC; + signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC; + signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_control_reg1 : signal is "NO"; + attribute async_reg of rxeq_control_reg1 : signal is "true"; + signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_control_reg2 : signal is "NO"; + attribute async_reg of rxeq_control_reg2 : signal is "true"; + signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \rxeq_fs[5]_i_1_n_0\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[3]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[4]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[5]\ : STD_LOGIC; + signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \rxeq_lf[5]_i_1_n_0\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[3]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[4]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[5]\ : STD_LOGIC; + signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_lffs_reg1 : signal is "NO"; + attribute async_reg of rxeq_lffs_reg1 : signal is "true"; + signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_lffs_reg2 : signal is "NO"; + attribute async_reg of rxeq_lffs_reg2 : signal is "true"; + signal rxeq_new_txcoeff_req : STD_LOGIC; + signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC; + signal \rxeq_preset[0]_i_1_n_0\ : STD_LOGIC; + signal \rxeq_preset[1]_i_1_n_0\ : STD_LOGIC; + signal \rxeq_preset[2]_i_1_n_0\ : STD_LOGIC; + signal \rxeq_preset[2]_i_2_n_0\ : STD_LOGIC; + signal \rxeq_preset[2]_i_3_n_0\ : STD_LOGIC; + signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_preset_reg1 : signal is "NO"; + attribute async_reg of rxeq_preset_reg1 : signal is "true"; + signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_preset_reg2 : signal is "NO"; + attribute async_reg of rxeq_preset_reg2 : signal is "true"; + signal \rxeq_preset_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_preset_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_preset_reg_n_0_[2]\ : STD_LOGIC; + signal rxeq_preset_valid : STD_LOGIC; + signal rxeq_scan_i_n_0 : STD_LOGIC; + signal rxeq_scan_i_n_1 : STD_LOGIC; + signal rxeq_scan_i_n_2 : STD_LOGIC; + signal rxeq_scan_i_n_4 : STD_LOGIC; + signal rxeq_scan_i_n_5 : STD_LOGIC; + signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 ); + signal \rxeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC; + signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \rxeq_txpreset[3]_i_1_n_0\ : STD_LOGIC; + signal \rxeq_txpreset[3]_i_3_n_0\ : STD_LOGIC; + signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_txpreset_reg1 : signal is "NO"; + attribute async_reg of rxeq_txpreset_reg1 : signal is "true"; + signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_txpreset_reg2 : signal is "NO"; + attribute async_reg of rxeq_txpreset_reg2 : signal is "true"; + signal \rxeq_txpreset_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_txpreset_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_txpreset_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_txpreset_reg_n_0_[3]\ : STD_LOGIC; + signal rxeq_user_en_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_en_reg1 : signal is "NO"; + attribute async_reg of rxeq_user_en_reg1 : signal is "true"; + signal rxeq_user_en_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_en_reg2 : signal is "NO"; + attribute async_reg of rxeq_user_en_reg2 : signal is "true"; + signal rxeq_user_mode_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg1 : signal is "NO"; + attribute async_reg of rxeq_user_mode_reg1 : signal is "true"; + signal rxeq_user_mode_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg2 : signal is "NO"; + attribute async_reg of rxeq_user_mode_reg2 : signal is "true"; + signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg1 : signal is "NO"; + attribute async_reg of rxeq_user_txcoeff_reg1 : signal is "true"; + signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg2 : signal is "NO"; + attribute async_reg of rxeq_user_txcoeff_reg2 : signal is "true"; + signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of txeq_control_reg1 : signal is "NO"; + attribute async_reg of txeq_control_reg1 : signal is "true"; + signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of txeq_control_reg2 : signal is "NO"; + attribute async_reg of txeq_control_reg2 : signal is "true"; + signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of txeq_deemph_reg1 : signal is "NO"; + attribute async_reg of txeq_deemph_reg1 : signal is "true"; + signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of txeq_deemph_reg2 : signal is "NO"; + attribute async_reg of txeq_deemph_reg2 : signal is "true"; + signal \txeq_preset[17]_i_1_n_0\ : STD_LOGIC; + signal \txeq_preset[3]_i_1_n_0\ : STD_LOGIC; + signal \txeq_preset[7]_i_1_n_0\ : STD_LOGIC; + signal txeq_preset_done : STD_LOGIC; + signal txeq_preset_done_i_1_n_0 : STD_LOGIC; + signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txeq_preset_reg1 : signal is "NO"; + attribute async_reg of txeq_preset_reg1 : signal is "true"; + signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txeq_preset_reg2 : signal is "NO"; + attribute async_reg of txeq_preset_reg2 : signal is "true"; + signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC; + signal txeq_txcoeff : STD_LOGIC; + signal \txeq_txcoeff[0]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[0]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[10]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[10]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[11]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[11]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[12]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[12]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[13]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[13]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[14]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[14]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[15]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[15]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[16]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[16]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[17]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[17]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[18]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[18]_i_3_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[1]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[1]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[2]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[2]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[3]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[3]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[4]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[4]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[5]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[5]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[6]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[6]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[7]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[7]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[8]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[8]_i_2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[9]_i_1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[9]_i_2_n_0\ : STD_LOGIC; + signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[4]_i_1\ : label is "soft_lutpair50"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[1]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[2]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[3]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[4]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[5]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[6]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute SOFT_HLUTNM of \FSM_sequential_fsm_tx[1]_i_2\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \FSM_sequential_fsm_tx[2]_i_2\ : label is "soft_lutpair48"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[0]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[1]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[2]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of gen3_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true; + attribute KEEP of gen3_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_cnt[1]_i_1\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \rxeq_cnt[2]_i_1\ : label is "soft_lutpair50"; + attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[5]\ : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_preset[2]_i_3\ : label is "soft_lutpair51"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[2]\ : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[0]_i_1\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[10]_i_1\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[11]_i_1\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[1]_i_1\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[2]_i_1\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[3]_i_1\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[4]_i_1\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[5]_i_1\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[6]_i_1\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[7]_i_1\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[8]_i_1\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[9]_i_1\ : label is "soft_lutpair56"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_en_reg1_reg : label is std.standard.true; + attribute KEEP of rxeq_user_en_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_en_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_en_reg2_reg : label is std.standard.true; + attribute KEEP of rxeq_user_en_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_en_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_mode_reg1_reg : label is std.standard.true; + attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_mode_reg2_reg : label is std.standard.true; + attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[5]\ : label is "NO"; + attribute SOFT_HLUTNM of txeq_preset_done_i_1 : label is "soft_lutpair49"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[3]\ : label is "NO"; + attribute SOFT_HLUTNM of \txeq_txcoeff_cnt[1]_i_1\ : label is "soft_lutpair49"; +begin + USER_RXEQ_ADAPT_DONE <= \^user_rxeq_adapt_done\; +\FSM_onehot_fsm_rx[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABABABAA" + ) + port map ( + I0 => \FSM_onehot_fsm_rx[1]_i_2_n_0\, + I1 => rxeq_control_reg2(1), + I2 => rxeq_control_reg2(0), + I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + O => \FSM_onehot_fsm_rx[1]_i_1_n_0\ + ); +\FSM_onehot_fsm_rx[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + O => \FSM_onehot_fsm_rx[1]_i_2_n_0\ + ); +\FSM_onehot_fsm_rx[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF8FF88888888" + ) + port map ( + I0 => rxeq_control_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \rxeq_cnt_reg_n_0_[2]\, + I3 => \rxeq_cnt_reg_n_0_[1]\, + I4 => \rxeq_cnt_reg_n_0_[0]\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \FSM_onehot_fsm_rx[3]_i_1_n_0\ + ); +\FSM_onehot_fsm_rx[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"2ABA2AAA" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => \rxeq_cnt_reg_n_0_[2]\, + I2 => \rxeq_cnt_reg_n_0_[1]\, + I3 => \rxeq_cnt_reg_n_0_[0]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \FSM_onehot_fsm_rx[4]_i_1_n_0\ + ); +\FSM_onehot_fsm_rx_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx[1]_i_1_n_0\, + Q => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_2, + Q => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx[3]_i_1_n_0\, + Q => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx[4]_i_1_n_0\, + Q => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_1, + Q => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_0, + Q => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +\FSM_sequential_fsm_tx[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C04FC043C04FF04F" + ) + port map ( + I0 => \FSM_sequential_fsm_tx[1]_i_2_n_0\, + I1 => fsm_tx(0), + I2 => fsm_tx(1), + I3 => fsm_tx(2), + I4 => txeq_control_reg2(1), + I5 => txeq_control_reg2(0), + O => \fsm_tx__0\(0) + ); +\FSM_sequential_fsm_tx[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3F703F7C3F7C0F70" + ) + port map ( + I0 => \FSM_sequential_fsm_tx[1]_i_2_n_0\, + I1 => fsm_tx(0), + I2 => fsm_tx(1), + I3 => fsm_tx(2), + I4 => txeq_control_reg2(1), + I5 => txeq_control_reg2(0), + O => \fsm_tx__0\(1) + ); +\FSM_sequential_fsm_tx[1]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + O => \FSM_sequential_fsm_tx[1]_i_2_n_0\ + ); +\FSM_sequential_fsm_tx[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3A2A2A227F7F7F77" + ) + port map ( + I0 => fsm_tx(2), + I1 => fsm_tx(1), + I2 => fsm_tx(0), + I3 => txeq_control_reg2(1), + I4 => txeq_control_reg2(0), + I5 => \FSM_sequential_fsm_tx[2]_i_2_n_0\, + O => \fsm_tx__0\(2) + ); +\FSM_sequential_fsm_tx[2]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D0FFDFFF" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I2 => fsm_tx(0), + I3 => fsm_tx(1), + I4 => txeq_preset_done, + O => \FSM_sequential_fsm_tx[2]_i_2_n_0\ + ); +\FSM_sequential_fsm_tx_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fsm_tx__0\(0), + Q => fsm_tx(0), + S => RST_CPLLRESET + ); +\FSM_sequential_fsm_tx_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fsm_tx__0\(1), + Q => fsm_tx(1), + R => RST_CPLLRESET + ); +\FSM_sequential_fsm_tx_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fsm_tx__0\(2), + Q => fsm_tx(2), + R => RST_CPLLRESET + ); +gen3_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => USER_RATE_GEN3, + Q => gen3_reg1, + R => RST_CPLLRESET + ); +gen3_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gen3_reg1, + Q => gen3_reg2, + R => RST_CPLLRESET + ); +\gtx_channel.gtxe2_channel_i_i_22\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[17]\, + O => TXPOSTCURSOR(4) + ); +\gtx_channel.gtxe2_channel_i_i_23\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[16]\, + O => TXPOSTCURSOR(3) + ); +\gtx_channel.gtxe2_channel_i_i_24\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[15]\, + O => TXPOSTCURSOR(2) + ); +\gtx_channel.gtxe2_channel_i_i_25\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[14]\, + O => TXPOSTCURSOR(1) + ); +\gtx_channel.gtxe2_channel_i_i_26\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[13]\, + O => TXPOSTCURSOR(0) + ); +\gtx_channel.gtxe2_channel_i_i_27\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[4]\, + O => TXPRECURSOR(4) + ); +\gtx_channel.gtxe2_channel_i_i_28\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[3]\, + O => TXPRECURSOR(3) + ); +\gtx_channel.gtxe2_channel_i_i_29\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[2]\, + O => TXPRECURSOR(2) + ); +\gtx_channel.gtxe2_channel_i_i_30\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[1]\, + O => TXPRECURSOR(1) + ); +\gtx_channel.gtxe2_channel_i_i_31\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[0]\, + I1 => gen3_reg2, + O => TXPRECURSOR(0) + ); +\gtx_channel.gtxe2_channel_i_i_32\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[12]\, + O => TXMAINCURSOR(6) + ); +\gtx_channel.gtxe2_channel_i_i_33\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[11]\, + O => TXMAINCURSOR(5) + ); +\gtx_channel.gtxe2_channel_i_i_34\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[10]\, + O => TXMAINCURSOR(4) + ); +\gtx_channel.gtxe2_channel_i_i_35\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[9]\, + O => TXMAINCURSOR(3) + ); +\gtx_channel.gtxe2_channel_i_i_36\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[8]\, + O => TXMAINCURSOR(2) + ); +\gtx_channel.gtxe2_channel_i_i_37\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[7]\, + O => TXMAINCURSOR(1) + ); +\gtx_channel.gtxe2_channel_i_i_38\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[6]\, + O => TXMAINCURSOR(0) + ); +rxeq_adapt_done_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFFFFFF" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + O => rxeq_adapt_done_i_2_n_0 + ); +rxeq_adapt_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_5, + Q => \^user_rxeq_adapt_done\, + R => RST_CPLLRESET + ); +rxeq_adapt_done_reg_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => rxeq_control_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => rxeq_control_reg2(1), + O => rxeq_adapt_done_reg_i_2_n_0 + ); +rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_4, + Q => rxeq_adapt_done_reg_reg_n_0, + R => RST_CPLLRESET + ); +\rxeq_cnt[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8888FFF8" + ) + port map ( + I0 => rxeq_control_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I4 => \rxeq_cnt_reg_n_0_[0]\, + O => rxeq_cnt(0) + ); +\rxeq_cnt[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6660" + ) + port map ( + I0 => \rxeq_cnt_reg_n_0_[0]\, + I1 => \rxeq_cnt_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => rxeq_cnt(1) + ); +\rxeq_cnt[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"78787800" + ) + port map ( + I0 => \rxeq_cnt_reg_n_0_[1]\, + I1 => \rxeq_cnt_reg_n_0_[0]\, + I2 => \rxeq_cnt_reg_n_0_[2]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => rxeq_cnt(2) + ); +\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_cnt(0), + Q => \rxeq_cnt_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_cnt(1), + Q => \rxeq_cnt_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_cnt(2), + Q => \rxeq_cnt_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_control_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_control_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_control_reg1(0), + Q => rxeq_control_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_control_reg1(1), + Q => rxeq_control_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_fs[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(0), + O => rxeq_fs(0) + ); +\rxeq_fs[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(1), + O => rxeq_fs(1) + ); +\rxeq_fs[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(2), + O => rxeq_fs(2) + ); +\rxeq_fs[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(3), + O => rxeq_fs(3) + ); +\rxeq_fs[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(4), + O => rxeq_fs(4) + ); +\rxeq_fs[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F8" + ) + port map ( + I0 => rxeq_control_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx[1]_i_2_n_0\, + O => \rxeq_fs[5]_i_1_n_0\ + ); +\rxeq_fs[5]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(5), + O => rxeq_fs(5) + ); +\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1_n_0\, + D => rxeq_fs(0), + Q => \rxeq_fs_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1_n_0\, + D => rxeq_fs(1), + Q => \rxeq_fs_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1_n_0\, + D => rxeq_fs(2), + Q => \rxeq_fs_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1_n_0\, + D => rxeq_fs(3), + Q => \rxeq_fs_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1_n_0\, + D => rxeq_fs(4), + Q => \rxeq_fs_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1_n_0\, + D => rxeq_fs(5), + Q => \rxeq_fs_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\rxeq_lf[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(0), + O => rxeq_lf(0) + ); +\rxeq_lf[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(1), + O => rxeq_lf(1) + ); +\rxeq_lf[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(2), + O => rxeq_lf(2) + ); +\rxeq_lf[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(3), + O => rxeq_lf(3) + ); +\rxeq_lf[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(4), + O => rxeq_lf(4) + ); +\rxeq_lf[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAAAAAAA" + ) + port map ( + I0 => \FSM_onehot_fsm_rx[1]_i_2_n_0\, + I1 => \rxeq_cnt_reg_n_0_[2]\, + I2 => \rxeq_cnt_reg_n_0_[0]\, + I3 => \rxeq_cnt_reg_n_0_[1]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + O => \rxeq_lf[5]_i_1_n_0\ + ); +\rxeq_lf[5]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(5), + O => rxeq_lf(5) + ); +\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1_n_0\, + D => rxeq_lf(0), + Q => \rxeq_lf_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1_n_0\, + D => rxeq_lf(1), + Q => \rxeq_lf_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1_n_0\, + D => rxeq_lf(2), + Q => \rxeq_lf_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1_n_0\, + D => rxeq_lf(3), + Q => \rxeq_lf_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1_n_0\, + D => rxeq_lf(4), + Q => \rxeq_lf_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1_n_0\, + D => rxeq_lf(5), + Q => \rxeq_lf_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(3), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(4), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(5), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(0), + Q => rxeq_lffs_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(1), + Q => rxeq_lffs_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(2), + Q => rxeq_lffs_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(3), + Q => rxeq_lffs_reg2(3), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(4), + Q => rxeq_lffs_reg2(4), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(5), + Q => rxeq_lffs_reg2(5), + R => RST_CPLLRESET + ); +rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_new_txcoeff_req, + Q => rxeq_new_txcoeff_req_reg_n_0, + R => RST_CPLLRESET + ); +\rxeq_preset[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8FFA800" + ) + port map ( + I0 => rxeq_preset_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => \rxeq_preset[2]_i_2_n_0\, + I4 => \rxeq_preset_reg_n_0_[0]\, + O => \rxeq_preset[0]_i_1_n_0\ + ); +\rxeq_preset[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8FFA800" + ) + port map ( + I0 => rxeq_preset_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => \rxeq_preset[2]_i_2_n_0\, + I4 => \rxeq_preset_reg_n_0_[1]\, + O => \rxeq_preset[1]_i_1_n_0\ + ); +\rxeq_preset[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8FFA800" + ) + port map ( + I0 => rxeq_preset_reg2(2), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => \rxeq_preset[2]_i_2_n_0\, + I4 => \rxeq_preset_reg_n_0_[2]\, + O => \rxeq_preset[2]_i_1_n_0\ + ); +\rxeq_preset[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF0002" + ) + port map ( + I0 => \rxeq_preset[2]_i_3_n_0\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + I4 => rxeq_adapt_done_reg_i_2_n_0, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + O => \rxeq_preset[2]_i_2_n_0\ + ); +\rxeq_preset[2]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \rxeq_preset[2]_i_3_n_0\ + ); +\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_preset_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_preset_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_preset_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_reg1(0), + Q => rxeq_preset_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_reg1(1), + Q => rxeq_preset_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_reg1(2), + Q => rxeq_preset_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxeq_preset[0]_i_1_n_0\, + Q => \rxeq_preset_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxeq_preset[1]_i_1_n_0\, + Q => \rxeq_preset_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxeq_preset[2]_i_1_n_0\, + Q => \rxeq_preset_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +rxeq_preset_valid_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + Q => rxeq_preset_valid, + R => RST_CPLLRESET + ); +rxeq_scan_i: entity work.pcie_7x_0_pcie_7x_0_rxeq_scan_59 + port map ( + D(2) => rxeq_scan_i_n_0, + D(1) => rxeq_scan_i_n_1, + D(0) => rxeq_scan_i_n_2, + \FSM_onehot_fsm_rx_reg[5]\(2) => \rxeq_cnt_reg_n_0_[2]\, + \FSM_onehot_fsm_rx_reg[5]\(1) => \rxeq_cnt_reg_n_0_[1]\, + \FSM_onehot_fsm_rx_reg[5]\(0) => \rxeq_cnt_reg_n_0_[0]\, + Q(4) => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + Q(3) => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + Q(2) => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + Q(1) => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + Q(0) => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + RST_CPLLRESET => RST_CPLLRESET, + USER_RXEQ_ADAPT_DONE => \^user_rxeq_adapt_done\, + adapt_done_reg_0 => rxeq_scan_i_n_4, + \fs_reg1_reg[5]_0\(5) => \rxeq_fs_reg_n_0_[5]\, + \fs_reg1_reg[5]_0\(4) => \rxeq_fs_reg_n_0_[4]\, + \fs_reg1_reg[5]_0\(3) => \rxeq_fs_reg_n_0_[3]\, + \fs_reg1_reg[5]_0\(2) => \rxeq_fs_reg_n_0_[2]\, + \fs_reg1_reg[5]_0\(1) => \rxeq_fs_reg_n_0_[1]\, + \fs_reg1_reg[5]_0\(0) => \rxeq_fs_reg_n_0_[0]\, + \lf_reg1_reg[5]_0\(5) => \rxeq_lf_reg_n_0_[5]\, + \lf_reg1_reg[5]_0\(4) => \rxeq_lf_reg_n_0_[4]\, + \lf_reg1_reg[5]_0\(3) => \rxeq_lf_reg_n_0_[3]\, + \lf_reg1_reg[5]_0\(2) => \rxeq_lf_reg_n_0_[2]\, + \lf_reg1_reg[5]_0\(1) => \rxeq_lf_reg_n_0_[1]\, + \lf_reg1_reg[5]_0\(0) => \rxeq_lf_reg_n_0_[0]\, + new_txcoeff_done_reg_0 => rxeq_scan_i_n_5, + new_txcoeff_req_reg1_reg_0 => rxeq_new_txcoeff_req_reg_n_0, + \out\(1 downto 0) => rxeq_control_reg2(1 downto 0), + pipe_pclk_in => pipe_pclk_in, + \preset_reg1_reg[2]_0\(2) => \rxeq_preset_reg_n_0_[2]\, + \preset_reg1_reg[2]_0\(1) => \rxeq_preset_reg_n_0_[1]\, + \preset_reg1_reg[2]_0\(0) => \rxeq_preset_reg_n_0_[0]\, + rxeq_adapt_done_reg => rxeq_adapt_done_i_2_n_0, + rxeq_adapt_done_reg_reg => \FSM_onehot_fsm_rx[1]_i_2_n_0\, + rxeq_adapt_done_reg_reg_0 => rxeq_adapt_done_reg_i_2_n_0, + rxeq_adapt_done_reg_reg_1 => rxeq_adapt_done_reg_reg_n_0, + rxeq_new_txcoeff_req => rxeq_new_txcoeff_req, + rxeq_preset_valid => rxeq_preset_valid, + \txcoeff_reg1_reg[17]_0\(17) => \rxeq_txcoeff_reg_n_0_[17]\, + \txcoeff_reg1_reg[17]_0\(16) => \rxeq_txcoeff_reg_n_0_[16]\, + \txcoeff_reg1_reg[17]_0\(15) => \rxeq_txcoeff_reg_n_0_[15]\, + \txcoeff_reg1_reg[17]_0\(14) => \rxeq_txcoeff_reg_n_0_[14]\, + \txcoeff_reg1_reg[17]_0\(13) => \rxeq_txcoeff_reg_n_0_[13]\, + \txcoeff_reg1_reg[17]_0\(12) => \rxeq_txcoeff_reg_n_0_[12]\, + \txcoeff_reg1_reg[17]_0\(11) => \rxeq_txcoeff_reg_n_0_[11]\, + \txcoeff_reg1_reg[17]_0\(10) => \rxeq_txcoeff_reg_n_0_[10]\, + \txcoeff_reg1_reg[17]_0\(9) => \rxeq_txcoeff_reg_n_0_[9]\, + \txcoeff_reg1_reg[17]_0\(8) => \rxeq_txcoeff_reg_n_0_[8]\, + \txcoeff_reg1_reg[17]_0\(7) => \rxeq_txcoeff_reg_n_0_[7]\, + \txcoeff_reg1_reg[17]_0\(6) => \rxeq_txcoeff_reg_n_0_[6]\, + \txcoeff_reg1_reg[17]_0\(5) => \rxeq_txcoeff_reg_n_0_[5]\, + \txcoeff_reg1_reg[17]_0\(4) => \rxeq_txcoeff_reg_n_0_[4]\, + \txcoeff_reg1_reg[17]_0\(3) => \rxeq_txcoeff_reg_n_0_[3]\, + \txcoeff_reg1_reg[17]_0\(2) => \rxeq_txcoeff_reg_n_0_[2]\, + \txcoeff_reg1_reg[17]_0\(1) => \rxeq_txcoeff_reg_n_0_[1]\, + \txcoeff_reg1_reg[17]_0\(0) => \rxeq_txcoeff_reg_n_0_[0]\, + \txpreset_reg1_reg[3]_0\(3) => \rxeq_txpreset_reg_n_0_[3]\, + \txpreset_reg1_reg[3]_0\(2) => \rxeq_txpreset_reg_n_0_[2]\, + \txpreset_reg1_reg[3]_0\(1) => \rxeq_txpreset_reg_n_0_[1]\, + \txpreset_reg1_reg[3]_0\(0) => \rxeq_txpreset_reg_n_0_[0]\ + ); +\rxeq_txcoeff[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[6]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(0) + ); +\rxeq_txcoeff[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[16]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(10) + ); +\rxeq_txcoeff[11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[17]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(11) + ); +\rxeq_txcoeff[12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(12) + ); +\rxeq_txcoeff[13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(13) + ); +\rxeq_txcoeff[14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(2), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(14) + ); +\rxeq_txcoeff[15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(3), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(15) + ); +\rxeq_txcoeff[16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(4), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(16) + ); +\rxeq_txcoeff[17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(5), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(17) + ); +\rxeq_txcoeff[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[7]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(1) + ); +\rxeq_txcoeff[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[8]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(2) + ); +\rxeq_txcoeff[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[9]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(3) + ); +\rxeq_txcoeff[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[10]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(4) + ); +\rxeq_txcoeff[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[11]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(5) + ); +\rxeq_txcoeff[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[12]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(6) + ); +\rxeq_txcoeff[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[13]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(7) + ); +\rxeq_txcoeff[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[14]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(8) + ); +\rxeq_txcoeff[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[15]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(9) + ); +\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(0), + Q => \rxeq_txcoeff_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(10), + Q => \rxeq_txcoeff_reg_n_0_[10]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(11), + Q => \rxeq_txcoeff_reg_n_0_[11]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(12), + Q => \rxeq_txcoeff_reg_n_0_[12]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(13), + Q => \rxeq_txcoeff_reg_n_0_[13]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(14), + Q => \rxeq_txcoeff_reg_n_0_[14]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(15), + Q => \rxeq_txcoeff_reg_n_0_[15]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(16), + Q => \rxeq_txcoeff_reg_n_0_[16]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(17), + Q => \rxeq_txcoeff_reg_n_0_[17]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(1), + Q => \rxeq_txcoeff_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(2), + Q => \rxeq_txcoeff_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(3), + Q => \rxeq_txcoeff_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(4), + Q => \rxeq_txcoeff_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(5), + Q => \rxeq_txcoeff_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(6), + Q => \rxeq_txcoeff_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(7), + Q => \rxeq_txcoeff_reg_n_0_[7]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(8), + Q => \rxeq_txcoeff_reg_n_0_[8]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txcoeff(9), + Q => \rxeq_txcoeff_reg_n_0_[9]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(0) + ); +\rxeq_txpreset[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(1) + ); +\rxeq_txpreset[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(2), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(2) + ); +\rxeq_txpreset[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFF404" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + I1 => \rxeq_txpreset[3]_i_3_n_0\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => rxeq_control_reg2(1), + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \rxeq_txpreset[3]_i_1_n_0\ + ); +\rxeq_txpreset[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(3), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(3) + ); +\rxeq_txpreset[3]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + O => \rxeq_txpreset[3]_i_3_n_0\ + ); +\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(3), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(0), + Q => rxeq_txpreset_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(1), + Q => rxeq_txpreset_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(2), + Q => rxeq_txpreset_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(3), + Q => rxeq_txpreset_reg2(3), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txpreset(0), + Q => \rxeq_txpreset_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txpreset(1), + Q => \rxeq_txpreset_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txpreset(2), + Q => \rxeq_txpreset_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1_n_0\, + D => rxeq_txpreset(3), + Q => \rxeq_txpreset_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_en_reg1, + R => RST_CPLLRESET + ); +rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_en_reg1, + Q => rxeq_user_en_reg2, + R => RST_CPLLRESET + ); +rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_mode_reg1, + R => RST_CPLLRESET + ); +rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_mode_reg1, + Q => rxeq_user_mode_reg2, + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(10), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(11), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(12), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(13), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(14), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(15), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(16), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(17), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(3), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(4), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(5), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(6), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(7), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(8), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(9), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(0), + Q => rxeq_user_txcoeff_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(10), + Q => rxeq_user_txcoeff_reg2(10), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(11), + Q => rxeq_user_txcoeff_reg2(11), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(12), + Q => rxeq_user_txcoeff_reg2(12), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(13), + Q => rxeq_user_txcoeff_reg2(13), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(14), + Q => rxeq_user_txcoeff_reg2(14), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(15), + Q => rxeq_user_txcoeff_reg2(15), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(16), + Q => rxeq_user_txcoeff_reg2(16), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(17), + Q => rxeq_user_txcoeff_reg2(17), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(1), + Q => rxeq_user_txcoeff_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(2), + Q => rxeq_user_txcoeff_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(3), + Q => rxeq_user_txcoeff_reg2(3), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(4), + Q => rxeq_user_txcoeff_reg2(4), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(5), + Q => rxeq_user_txcoeff_reg2(5), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(6), + Q => rxeq_user_txcoeff_reg2(6), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(7), + Q => rxeq_user_txcoeff_reg2(7), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(8), + Q => rxeq_user_txcoeff_reg2(8), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(9), + Q => rxeq_user_txcoeff_reg2(9), + R => RST_CPLLRESET + ); +\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_control_reg1(0), + R => RST_CPLLRESET + ); +\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_control_reg1(1), + R => RST_CPLLRESET + ); +\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_control_reg1(0), + Q => txeq_control_reg2(0), + R => RST_CPLLRESET + ); +\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_control_reg1(1), + Q => txeq_control_reg2(1), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(0), + S => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(1), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(2), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(3), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(4), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(5), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(0), + Q => txeq_deemph_reg2(0), + S => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(1), + Q => txeq_deemph_reg2(1), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(2), + Q => txeq_deemph_reg2(2), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(3), + Q => txeq_deemph_reg2(3), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(4), + Q => txeq_deemph_reg2(4), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(5), + Q => txeq_deemph_reg2(5), + R => RST_CPLLRESET + ); +\txeq_preset[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001000" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(2), + I2 => txeq_preset_reg2(0), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(1), + O => p_0_out(0) + ); +\txeq_preset[10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABEAABAF" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(2), + I2 => txeq_preset_reg2(0), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(1), + O => p_0_out(10) + ); +\txeq_preset[11]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF200D" + ) + port map ( + I0 => txeq_preset_reg2(1), + I1 => txeq_preset_reg2(3), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(0), + I4 => RST_CPLLRESET, + O => p_0_out(11) + ); +\txeq_preset[12]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01151110" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(3), + I2 => txeq_preset_reg2(1), + I3 => txeq_preset_reg2(2), + I4 => txeq_preset_reg2(0), + O => p_0_out(12) + ); +\txeq_preset[13]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01000010" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => RST_CPLLRESET, + I2 => txeq_preset_reg2(0), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(1), + O => p_0_out(13) + ); +\txeq_preset[14]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01000010" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => RST_CPLLRESET, + I2 => txeq_preset_reg2(3), + I3 => txeq_preset_reg2(1), + I4 => txeq_preset_reg2(0), + O => p_0_out(14) + ); +\txeq_preset[15]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F0F1" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => txeq_preset_reg2(1), + I2 => RST_CPLLRESET, + I3 => txeq_preset_reg2(3), + O => p_0_out(15) + ); +\txeq_preset[16]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0006" + ) + port map ( + I0 => txeq_preset_reg2(3), + I1 => txeq_preset_reg2(0), + I2 => txeq_preset_reg2(2), + I3 => RST_CPLLRESET, + O => p_0_out(16) + ); +\txeq_preset[17]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AABA" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => fsm_tx(0), + I2 => fsm_tx(1), + I3 => fsm_tx(2), + O => \txeq_preset[17]_i_1_n_0\ + ); +\txeq_preset[17]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF400D" + ) + port map ( + I0 => txeq_preset_reg2(3), + I1 => txeq_preset_reg2(1), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(0), + I4 => RST_CPLLRESET, + O => p_0_out(17) + ); +\txeq_preset[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001004" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(3), + I2 => txeq_preset_reg2(1), + I3 => txeq_preset_reg2(2), + I4 => txeq_preset_reg2(0), + O => p_0_out(1) + ); +\txeq_preset[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0E00" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => txeq_preset_reg2(0), + I2 => RST_CPLLRESET, + I3 => txeq_preset_reg2(3), + O => p_0_out(2) + ); +\txeq_preset[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01440140" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(2), + I2 => txeq_preset_reg2(1), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(0), + O => \txeq_preset[3]_i_1_n_0\ + ); +\txeq_preset[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001400" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(0), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(1), + I4 => txeq_preset_reg2(3), + O => \txeq_preset[7]_i_1_n_0\ + ); +\txeq_preset[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAFBEAF" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(0), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(1), + I4 => txeq_preset_reg2(3), + O => p_0_out(8) + ); +\txeq_preset[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCFCCFCD" + ) + port map ( + I0 => txeq_preset_reg2(1), + I1 => RST_CPLLRESET, + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(0), + O => p_0_out(9) + ); +txeq_preset_done_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => fsm_tx(2), + I1 => fsm_tx(1), + I2 => fsm_tx(0), + O => txeq_preset_done_i_1_n_0 + ); +txeq_preset_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_done_i_1_n_0, + Q => txeq_preset_done, + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(0), + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(1), + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(2), + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(3), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(0), + Q => txeq_preset_reg2(0), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(1), + Q => txeq_preset_reg2(1), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(2), + Q => txeq_preset_reg2(2), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(3), + Q => txeq_preset_reg2(3), + R => RST_CPLLRESET + ); +\txeq_preset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => p_0_out(0), + Q => \txeq_preset_reg_n_0_[0]\, + R => '0' + ); +\txeq_preset_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => p_0_out(10), + Q => \txeq_preset_reg_n_0_[10]\, + R => '0' + ); +\txeq_preset_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => p_0_out(11), + Q => \txeq_preset_reg_n_0_[11]\, + R => '0' + ); +\txeq_preset_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => p_0_out(12), + Q => \txeq_preset_reg_n_0_[12]\, + R => '0' + ); +\txeq_preset_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => p_0_out(13), + Q => \txeq_preset_reg_n_0_[13]\, + R => '0' + ); +\txeq_preset_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => p_0_out(14), + Q => \txeq_preset_reg_n_0_[14]\, + R => '0' + ); +\txeq_preset_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => p_0_out(15), + Q => \txeq_preset_reg_n_0_[15]\, + R => '0' + ); +\txeq_preset_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => p_0_out(16), + Q => \txeq_preset_reg_n_0_[16]\, + R => '0' + ); +\txeq_preset_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => p_0_out(17), + Q => \txeq_preset_reg_n_0_[17]\, + R => '0' + ); +\txeq_preset_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => p_0_out(1), + Q => \txeq_preset_reg_n_0_[1]\, + R => '0' + ); +\txeq_preset_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => p_0_out(2), + Q => \txeq_preset_reg_n_0_[2]\, + R => '0' + ); +\txeq_preset_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => \txeq_preset[3]_i_1_n_0\, + Q => \txeq_preset_reg_n_0_[3]\, + R => '0' + ); +\txeq_preset_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => \txeq_preset[7]_i_1_n_0\, + Q => \txeq_preset_reg_n_0_[7]\, + R => '0' + ); +\txeq_preset_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => p_0_out(8), + Q => \txeq_preset_reg_n_0_[8]\, + R => '0' + ); +\txeq_preset_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1_n_0\, + D => p_0_out(9), + Q => \txeq_preset_reg_n_0_[9]\, + R => '0' + ); +\txeq_txcoeff[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"45404040" + ) + port map ( + I0 => fsm_tx(2), + I1 => \txeq_txcoeff[0]_i_2_n_0\, + I2 => fsm_tx(1), + I3 => fsm_tx(0), + I4 => \txeq_txcoeff_reg_n_0_[6]\, + O => \txeq_txcoeff[0]_i_1_n_0\ + ); +\txeq_txcoeff[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[6]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[7]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[0]\, + O => \txeq_txcoeff[0]_i_2_n_0\ + ); +\txeq_txcoeff[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[9]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[10]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[16]\, + O => \txeq_txcoeff[10]_i_1_n_0\ + ); +\txeq_txcoeff[10]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[16]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[17]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[10]\, + O => \txeq_txcoeff[10]_i_2_n_0\ + ); +\txeq_txcoeff[11]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[10]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[11]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[17]\, + O => \txeq_txcoeff[11]_i_1_n_0\ + ); +\txeq_txcoeff[11]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[17]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[18]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[11]\, + O => \txeq_txcoeff[11]_i_2_n_0\ + ); +\txeq_txcoeff[12]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[11]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[12]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[18]\, + O => \txeq_txcoeff[12]_i_1_n_0\ + ); +\txeq_txcoeff[12]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[18]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(0), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[12]\, + O => \txeq_txcoeff[12]_i_2_n_0\ + ); +\txeq_txcoeff[13]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[12]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[13]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(0), + O => \txeq_txcoeff[13]_i_1_n_0\ + ); +\txeq_txcoeff[13]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(0), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(1), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[13]\, + O => \txeq_txcoeff[13]_i_2_n_0\ + ); +\txeq_txcoeff[14]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[13]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[14]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(1), + O => \txeq_txcoeff[14]_i_1_n_0\ + ); +\txeq_txcoeff[14]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(1), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(2), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[14]\, + O => \txeq_txcoeff[14]_i_2_n_0\ + ); +\txeq_txcoeff[15]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[14]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[15]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(2), + O => \txeq_txcoeff[15]_i_1_n_0\ + ); +\txeq_txcoeff[15]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(2), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(3), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[15]\, + O => \txeq_txcoeff[15]_i_2_n_0\ + ); +\txeq_txcoeff[16]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[15]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[16]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(3), + O => \txeq_txcoeff[16]_i_1_n_0\ + ); +\txeq_txcoeff[16]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(3), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(4), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[16]\, + O => \txeq_txcoeff[16]_i_2_n_0\ + ); +\txeq_txcoeff[17]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[16]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[17]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(4), + O => \txeq_txcoeff[17]_i_1_n_0\ + ); +\txeq_txcoeff[17]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(4), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(5), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[17]\, + O => \txeq_txcoeff[17]_i_2_n_0\ + ); +\txeq_txcoeff[18]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF040FFF" + ) + port map ( + I0 => txeq_control_reg2(0), + I1 => txeq_control_reg2(1), + I2 => fsm_tx(2), + I3 => fsm_tx(1), + I4 => fsm_tx(0), + O => txeq_txcoeff + ); +\txeq_txcoeff[18]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F3220022002200" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[17]\, + I1 => fsm_tx(1), + I2 => \txeq_txcoeff[18]_i_3_n_0\, + I3 => fsm_tx(2), + I4 => txeq_deemph_reg2(5), + I5 => fsm_tx(0), + O => \txeq_txcoeff[18]_i_2_n_0\ + ); +\txeq_txcoeff[18]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + O => \txeq_txcoeff[18]_i_3_n_0\ + ); +\txeq_txcoeff[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[0]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[1]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[7]\, + O => \txeq_txcoeff[1]_i_1_n_0\ + ); +\txeq_txcoeff[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[7]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[8]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[1]\, + O => \txeq_txcoeff[1]_i_2_n_0\ + ); +\txeq_txcoeff[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[1]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[2]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[8]\, + O => \txeq_txcoeff[2]_i_1_n_0\ + ); +\txeq_txcoeff[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[8]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[9]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[2]\, + O => \txeq_txcoeff[2]_i_2_n_0\ + ); +\txeq_txcoeff[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[2]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[3]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[9]\, + O => \txeq_txcoeff[3]_i_1_n_0\ + ); +\txeq_txcoeff[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[9]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[10]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[3]\, + O => \txeq_txcoeff[3]_i_2_n_0\ + ); +\txeq_txcoeff[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[3]\, + I1 => fsm_tx(1), + I2 => fsm_tx(2), + I3 => \txeq_txcoeff[4]_i_2_n_0\, + O => \txeq_txcoeff[4]_i_1_n_0\ + ); +\txeq_txcoeff[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACCCCCC00000000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[11]\, + I1 => \txeq_txcoeff_reg_n_0_[10]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I4 => fsm_tx(1), + I5 => fsm_tx(0), + O => \txeq_txcoeff[4]_i_2_n_0\ + ); +\txeq_txcoeff[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[4]\, + I1 => fsm_tx(1), + I2 => fsm_tx(2), + I3 => \txeq_txcoeff[5]_i_2_n_0\, + O => \txeq_txcoeff[5]_i_1_n_0\ + ); +\txeq_txcoeff[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACCCCCC00000000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[12]\, + I1 => \txeq_txcoeff_reg_n_0_[11]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I4 => fsm_tx(1), + I5 => fsm_tx(0), + O => \txeq_txcoeff[5]_i_2_n_0\ + ); +\txeq_txcoeff[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[5]\, + I1 => fsm_tx(1), + I2 => fsm_tx(2), + I3 => \txeq_txcoeff[6]_i_2_n_0\, + O => \txeq_txcoeff[6]_i_1_n_0\ + ); +\txeq_txcoeff[6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACCCCCC00000000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[13]\, + I1 => \txeq_txcoeff_reg_n_0_[12]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I4 => fsm_tx(1), + I5 => fsm_tx(0), + O => \txeq_txcoeff[6]_i_2_n_0\ + ); +\txeq_txcoeff[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[6]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[7]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[13]\, + O => \txeq_txcoeff[7]_i_1_n_0\ + ); +\txeq_txcoeff[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[13]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[14]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[7]\, + O => \txeq_txcoeff[7]_i_2_n_0\ + ); +\txeq_txcoeff[8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[7]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[8]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[14]\, + O => \txeq_txcoeff[8]_i_1_n_0\ + ); +\txeq_txcoeff[8]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[14]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[15]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[8]\, + O => \txeq_txcoeff[8]_i_2_n_0\ + ); +\txeq_txcoeff[9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[8]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[9]_i_2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[15]\, + O => \txeq_txcoeff[9]_i_1_n_0\ + ); +\txeq_txcoeff[9]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[15]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[16]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[9]\, + O => \txeq_txcoeff[9]_i_2_n_0\ + ); +\txeq_txcoeff_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000004000F000400" + ) + port map ( + I0 => txeq_control_reg2(0), + I1 => txeq_control_reg2(1), + I2 => fsm_tx(2), + I3 => fsm_tx(0), + I4 => fsm_tx(1), + I5 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + O => txeq_txcoeff_cnt(0) + ); +\txeq_txcoeff_cnt[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00006000" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I2 => fsm_tx(0), + I3 => fsm_tx(1), + I4 => fsm_tx(2), + O => txeq_txcoeff_cnt(1) + ); +\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_txcoeff_cnt(0), + Q => \txeq_txcoeff_cnt_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_txcoeff_cnt(1), + Q => \txeq_txcoeff_cnt_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[0]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[10]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[10]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[11]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[11]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[12]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[12]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[13]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[13]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[14]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[14]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[15]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[15]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[16]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[16]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[17]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[17]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[18]_i_2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[18]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[1]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[2]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[3]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[4]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[5]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[6]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[7]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[7]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[8]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[8]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[9]_i_1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[9]\, + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_eq_39 is + port ( + TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 ); + TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 ); + TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 ); + USER_RXEQ_ADAPT_DONE : out STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + rate_gen3_1 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_eq_39 : entity is "pcie_7x_0_pipe_eq"; +end pcie_7x_0_pcie_7x_0_pipe_eq_39; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_eq_39 is + signal \FSM_onehot_fsm_rx[1]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[1]_i_2__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[3]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[4]_i_1__0_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[5]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[6]\ : STD_LOGIC; + signal \FSM_sequential_fsm_tx[1]_i_2__0_n_0\ : STD_LOGIC; + signal \FSM_sequential_fsm_tx[2]_i_2__0_n_0\ : STD_LOGIC; + signal \^user_rxeq_adapt_done\ : STD_LOGIC; + signal fsm_tx : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \fsm_tx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal gen3_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of gen3_reg1 : signal is "true"; + signal gen3_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO"; + attribute async_reg of gen3_reg2 : signal is "true"; + signal p_0_out : STD_LOGIC_VECTOR ( 17 downto 0 ); + signal \rxeq_adapt_done_i_2__0_n_0\ : STD_LOGIC; + signal \rxeq_adapt_done_reg_i_2__0_n_0\ : STD_LOGIC; + signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC; + signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_control_reg1 : signal is "NO"; + attribute async_reg of rxeq_control_reg1 : signal is "true"; + signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_control_reg2 : signal is "NO"; + attribute async_reg of rxeq_control_reg2 : signal is "true"; + signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \rxeq_fs[5]_i_1__0_n_0\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[3]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[4]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[5]\ : STD_LOGIC; + signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \rxeq_lf[5]_i_1__0_n_0\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[3]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[4]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[5]\ : STD_LOGIC; + signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_lffs_reg1 : signal is "NO"; + attribute async_reg of rxeq_lffs_reg1 : signal is "true"; + signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_lffs_reg2 : signal is "NO"; + attribute async_reg of rxeq_lffs_reg2 : signal is "true"; + signal rxeq_new_txcoeff_req : STD_LOGIC; + signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC; + signal \rxeq_preset[0]_i_1__0_n_0\ : STD_LOGIC; + signal \rxeq_preset[1]_i_1__0_n_0\ : STD_LOGIC; + signal \rxeq_preset[2]_i_1__0_n_0\ : STD_LOGIC; + signal \rxeq_preset[2]_i_2__0_n_0\ : STD_LOGIC; + signal \rxeq_preset[2]_i_3__0_n_0\ : STD_LOGIC; + signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_preset_reg1 : signal is "NO"; + attribute async_reg of rxeq_preset_reg1 : signal is "true"; + signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_preset_reg2 : signal is "NO"; + attribute async_reg of rxeq_preset_reg2 : signal is "true"; + signal \rxeq_preset_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_preset_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_preset_reg_n_0_[2]\ : STD_LOGIC; + signal rxeq_preset_valid : STD_LOGIC; + signal rxeq_scan_i_n_0 : STD_LOGIC; + signal rxeq_scan_i_n_1 : STD_LOGIC; + signal rxeq_scan_i_n_2 : STD_LOGIC; + signal rxeq_scan_i_n_4 : STD_LOGIC; + signal rxeq_scan_i_n_5 : STD_LOGIC; + signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 ); + signal \rxeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC; + signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \rxeq_txpreset[3]_i_1__0_n_0\ : STD_LOGIC; + signal \rxeq_txpreset[3]_i_3__0_n_0\ : STD_LOGIC; + signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_txpreset_reg1 : signal is "NO"; + attribute async_reg of rxeq_txpreset_reg1 : signal is "true"; + signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_txpreset_reg2 : signal is "NO"; + attribute async_reg of rxeq_txpreset_reg2 : signal is "true"; + signal \rxeq_txpreset_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_txpreset_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_txpreset_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_txpreset_reg_n_0_[3]\ : STD_LOGIC; + signal rxeq_user_en_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_en_reg1 : signal is "NO"; + attribute async_reg of rxeq_user_en_reg1 : signal is "true"; + signal rxeq_user_en_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_en_reg2 : signal is "NO"; + attribute async_reg of rxeq_user_en_reg2 : signal is "true"; + signal rxeq_user_mode_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg1 : signal is "NO"; + attribute async_reg of rxeq_user_mode_reg1 : signal is "true"; + signal rxeq_user_mode_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg2 : signal is "NO"; + attribute async_reg of rxeq_user_mode_reg2 : signal is "true"; + signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg1 : signal is "NO"; + attribute async_reg of rxeq_user_txcoeff_reg1 : signal is "true"; + signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg2 : signal is "NO"; + attribute async_reg of rxeq_user_txcoeff_reg2 : signal is "true"; + signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of txeq_control_reg1 : signal is "NO"; + attribute async_reg of txeq_control_reg1 : signal is "true"; + signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of txeq_control_reg2 : signal is "NO"; + attribute async_reg of txeq_control_reg2 : signal is "true"; + signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of txeq_deemph_reg1 : signal is "NO"; + attribute async_reg of txeq_deemph_reg1 : signal is "true"; + signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of txeq_deemph_reg2 : signal is "NO"; + attribute async_reg of txeq_deemph_reg2 : signal is "true"; + signal \txeq_preset[17]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_preset[3]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_preset[7]_i_1__0_n_0\ : STD_LOGIC; + signal txeq_preset_done : STD_LOGIC; + signal \txeq_preset_done_i_1__0_n_0\ : STD_LOGIC; + signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txeq_preset_reg1 : signal is "NO"; + attribute async_reg of txeq_preset_reg1 : signal is "true"; + signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txeq_preset_reg2 : signal is "NO"; + attribute async_reg of txeq_preset_reg2 : signal is "true"; + signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC; + signal txeq_txcoeff : STD_LOGIC; + signal \txeq_txcoeff[0]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[0]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[10]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[10]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[11]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[11]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[12]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[12]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[13]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[13]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[14]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[14]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[15]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[15]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[16]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[16]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[17]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[17]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[18]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[18]_i_3__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[1]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[1]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[2]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[2]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[3]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[3]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[4]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[4]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[5]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[5]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[6]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[6]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[7]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[7]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[8]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[8]_i_2__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[9]_i_1__0_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[9]_i_2__0_n_0\ : STD_LOGIC; + signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[4]_i_1__0\ : label is "soft_lutpair102"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[1]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[2]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[3]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[4]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[5]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[6]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute SOFT_HLUTNM of \FSM_sequential_fsm_tx[1]_i_2__0\ : label is "soft_lutpair100"; + attribute SOFT_HLUTNM of \FSM_sequential_fsm_tx[2]_i_2__0\ : label is "soft_lutpair100"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[0]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[1]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[2]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of gen3_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true; + attribute KEEP of gen3_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_cnt[1]_i_1__0\ : label is "soft_lutpair103"; + attribute SOFT_HLUTNM of \rxeq_cnt[2]_i_1__0\ : label is "soft_lutpair102"; + attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[5]\ : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_preset[2]_i_3__0\ : label is "soft_lutpair103"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[2]\ : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[0]_i_1__0\ : label is "soft_lutpair104"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[10]_i_1__0\ : label is "soft_lutpair109"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[11]_i_1__0\ : label is "soft_lutpair109"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[1]_i_1__0\ : label is "soft_lutpair104"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[2]_i_1__0\ : label is "soft_lutpair105"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[3]_i_1__0\ : label is "soft_lutpair105"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[4]_i_1__0\ : label is "soft_lutpair106"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[5]_i_1__0\ : label is "soft_lutpair106"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[6]_i_1__0\ : label is "soft_lutpair107"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[7]_i_1__0\ : label is "soft_lutpair107"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[8]_i_1__0\ : label is "soft_lutpair108"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[9]_i_1__0\ : label is "soft_lutpair108"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_en_reg1_reg : label is std.standard.true; + attribute KEEP of rxeq_user_en_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_en_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_en_reg2_reg : label is std.standard.true; + attribute KEEP of rxeq_user_en_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_en_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_mode_reg1_reg : label is std.standard.true; + attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_mode_reg2_reg : label is std.standard.true; + attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[5]\ : label is "NO"; + attribute SOFT_HLUTNM of \txeq_preset_done_i_1__0\ : label is "soft_lutpair101"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[3]\ : label is "NO"; + attribute SOFT_HLUTNM of \txeq_txcoeff_cnt[1]_i_1__0\ : label is "soft_lutpair101"; +begin + USER_RXEQ_ADAPT_DONE <= \^user_rxeq_adapt_done\; +\FSM_onehot_fsm_rx[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABABABAA" + ) + port map ( + I0 => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\, + I1 => rxeq_control_reg2(1), + I2 => rxeq_control_reg2(0), + I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + O => \FSM_onehot_fsm_rx[1]_i_1__0_n_0\ + ); +\FSM_onehot_fsm_rx[1]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + O => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\ + ); +\FSM_onehot_fsm_rx[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF8FF88888888" + ) + port map ( + I0 => rxeq_control_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \rxeq_cnt_reg_n_0_[2]\, + I3 => \rxeq_cnt_reg_n_0_[1]\, + I4 => \rxeq_cnt_reg_n_0_[0]\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \FSM_onehot_fsm_rx[3]_i_1__0_n_0\ + ); +\FSM_onehot_fsm_rx[4]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"2ABA2AAA" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => \rxeq_cnt_reg_n_0_[2]\, + I2 => \rxeq_cnt_reg_n_0_[1]\, + I3 => \rxeq_cnt_reg_n_0_[0]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \FSM_onehot_fsm_rx[4]_i_1__0_n_0\ + ); +\FSM_onehot_fsm_rx_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx[1]_i_1__0_n_0\, + Q => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_2, + Q => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx[3]_i_1__0_n_0\, + Q => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx[4]_i_1__0_n_0\, + Q => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_1, + Q => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_0, + Q => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +\FSM_sequential_fsm_tx[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C04FC043C04FF04F" + ) + port map ( + I0 => \FSM_sequential_fsm_tx[1]_i_2__0_n_0\, + I1 => fsm_tx(0), + I2 => fsm_tx(1), + I3 => fsm_tx(2), + I4 => txeq_control_reg2(1), + I5 => txeq_control_reg2(0), + O => \fsm_tx__0\(0) + ); +\FSM_sequential_fsm_tx[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3F703F7C3F7C0F70" + ) + port map ( + I0 => \FSM_sequential_fsm_tx[1]_i_2__0_n_0\, + I1 => fsm_tx(0), + I2 => fsm_tx(1), + I3 => fsm_tx(2), + I4 => txeq_control_reg2(1), + I5 => txeq_control_reg2(0), + O => \fsm_tx__0\(1) + ); +\FSM_sequential_fsm_tx[1]_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + O => \FSM_sequential_fsm_tx[1]_i_2__0_n_0\ + ); +\FSM_sequential_fsm_tx[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3A2A2A227F7F7F77" + ) + port map ( + I0 => fsm_tx(2), + I1 => fsm_tx(1), + I2 => fsm_tx(0), + I3 => txeq_control_reg2(1), + I4 => txeq_control_reg2(0), + I5 => \FSM_sequential_fsm_tx[2]_i_2__0_n_0\, + O => \fsm_tx__0\(2) + ); +\FSM_sequential_fsm_tx[2]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D0FFDFFF" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I2 => fsm_tx(0), + I3 => fsm_tx(1), + I4 => txeq_preset_done, + O => \FSM_sequential_fsm_tx[2]_i_2__0_n_0\ + ); +\FSM_sequential_fsm_tx_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fsm_tx__0\(0), + Q => fsm_tx(0), + S => RST_CPLLRESET + ); +\FSM_sequential_fsm_tx_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fsm_tx__0\(1), + Q => fsm_tx(1), + R => RST_CPLLRESET + ); +\FSM_sequential_fsm_tx_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fsm_tx__0\(2), + Q => fsm_tx(2), + R => RST_CPLLRESET + ); +gen3_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_gen3_1, + Q => gen3_reg1, + R => RST_CPLLRESET + ); +gen3_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gen3_reg1, + Q => gen3_reg2, + R => RST_CPLLRESET + ); +\gtx_channel.gtxe2_channel_i_i_22__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[17]\, + O => TXPOSTCURSOR(4) + ); +\gtx_channel.gtxe2_channel_i_i_23__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[16]\, + O => TXPOSTCURSOR(3) + ); +\gtx_channel.gtxe2_channel_i_i_24__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[15]\, + O => TXPOSTCURSOR(2) + ); +\gtx_channel.gtxe2_channel_i_i_25__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[14]\, + O => TXPOSTCURSOR(1) + ); +\gtx_channel.gtxe2_channel_i_i_26__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[13]\, + O => TXPOSTCURSOR(0) + ); +\gtx_channel.gtxe2_channel_i_i_27__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[4]\, + O => TXPRECURSOR(4) + ); +\gtx_channel.gtxe2_channel_i_i_28__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[3]\, + O => TXPRECURSOR(3) + ); +\gtx_channel.gtxe2_channel_i_i_29__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[2]\, + O => TXPRECURSOR(2) + ); +\gtx_channel.gtxe2_channel_i_i_30__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[1]\, + O => TXPRECURSOR(1) + ); +\gtx_channel.gtxe2_channel_i_i_31__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[0]\, + I1 => gen3_reg2, + O => TXPRECURSOR(0) + ); +\gtx_channel.gtxe2_channel_i_i_32__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[12]\, + O => TXMAINCURSOR(6) + ); +\gtx_channel.gtxe2_channel_i_i_33__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[11]\, + O => TXMAINCURSOR(5) + ); +\gtx_channel.gtxe2_channel_i_i_34__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[10]\, + O => TXMAINCURSOR(4) + ); +\gtx_channel.gtxe2_channel_i_i_35__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[9]\, + O => TXMAINCURSOR(3) + ); +\gtx_channel.gtxe2_channel_i_i_36__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[8]\, + O => TXMAINCURSOR(2) + ); +\gtx_channel.gtxe2_channel_i_i_37__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[7]\, + O => TXMAINCURSOR(1) + ); +\gtx_channel.gtxe2_channel_i_i_38__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[6]\, + O => TXMAINCURSOR(0) + ); +\rxeq_adapt_done_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFFFFFF" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + O => \rxeq_adapt_done_i_2__0_n_0\ + ); +rxeq_adapt_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_5, + Q => \^user_rxeq_adapt_done\, + R => RST_CPLLRESET + ); +\rxeq_adapt_done_reg_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => rxeq_control_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => rxeq_control_reg2(1), + O => \rxeq_adapt_done_reg_i_2__0_n_0\ + ); +rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_4, + Q => rxeq_adapt_done_reg_reg_n_0, + R => RST_CPLLRESET + ); +\rxeq_cnt[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8888FFF8" + ) + port map ( + I0 => rxeq_control_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I4 => \rxeq_cnt_reg_n_0_[0]\, + O => rxeq_cnt(0) + ); +\rxeq_cnt[1]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6660" + ) + port map ( + I0 => \rxeq_cnt_reg_n_0_[0]\, + I1 => \rxeq_cnt_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => rxeq_cnt(1) + ); +\rxeq_cnt[2]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"78787800" + ) + port map ( + I0 => \rxeq_cnt_reg_n_0_[1]\, + I1 => \rxeq_cnt_reg_n_0_[0]\, + I2 => \rxeq_cnt_reg_n_0_[2]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => rxeq_cnt(2) + ); +\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_cnt(0), + Q => \rxeq_cnt_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_cnt(1), + Q => \rxeq_cnt_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_cnt(2), + Q => \rxeq_cnt_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_control_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_control_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_control_reg1(0), + Q => rxeq_control_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_control_reg1(1), + Q => rxeq_control_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_fs[0]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(0), + O => rxeq_fs(0) + ); +\rxeq_fs[1]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(1), + O => rxeq_fs(1) + ); +\rxeq_fs[2]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(2), + O => rxeq_fs(2) + ); +\rxeq_fs[3]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(3), + O => rxeq_fs(3) + ); +\rxeq_fs[4]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(4), + O => rxeq_fs(4) + ); +\rxeq_fs[5]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F8" + ) + port map ( + I0 => rxeq_control_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\, + O => \rxeq_fs[5]_i_1__0_n_0\ + ); +\rxeq_fs[5]_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(5), + O => rxeq_fs(5) + ); +\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__0_n_0\, + D => rxeq_fs(0), + Q => \rxeq_fs_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__0_n_0\, + D => rxeq_fs(1), + Q => \rxeq_fs_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__0_n_0\, + D => rxeq_fs(2), + Q => \rxeq_fs_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__0_n_0\, + D => rxeq_fs(3), + Q => \rxeq_fs_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__0_n_0\, + D => rxeq_fs(4), + Q => \rxeq_fs_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__0_n_0\, + D => rxeq_fs(5), + Q => \rxeq_fs_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\rxeq_lf[0]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(0), + O => rxeq_lf(0) + ); +\rxeq_lf[1]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(1), + O => rxeq_lf(1) + ); +\rxeq_lf[2]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(2), + O => rxeq_lf(2) + ); +\rxeq_lf[3]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(3), + O => rxeq_lf(3) + ); +\rxeq_lf[4]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(4), + O => rxeq_lf(4) + ); +\rxeq_lf[5]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAAAAAAA" + ) + port map ( + I0 => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\, + I1 => \rxeq_cnt_reg_n_0_[2]\, + I2 => \rxeq_cnt_reg_n_0_[0]\, + I3 => \rxeq_cnt_reg_n_0_[1]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + O => \rxeq_lf[5]_i_1__0_n_0\ + ); +\rxeq_lf[5]_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(5), + O => rxeq_lf(5) + ); +\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__0_n_0\, + D => rxeq_lf(0), + Q => \rxeq_lf_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__0_n_0\, + D => rxeq_lf(1), + Q => \rxeq_lf_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__0_n_0\, + D => rxeq_lf(2), + Q => \rxeq_lf_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__0_n_0\, + D => rxeq_lf(3), + Q => \rxeq_lf_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__0_n_0\, + D => rxeq_lf(4), + Q => \rxeq_lf_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__0_n_0\, + D => rxeq_lf(5), + Q => \rxeq_lf_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(3), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(4), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(5), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(0), + Q => rxeq_lffs_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(1), + Q => rxeq_lffs_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(2), + Q => rxeq_lffs_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(3), + Q => rxeq_lffs_reg2(3), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(4), + Q => rxeq_lffs_reg2(4), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(5), + Q => rxeq_lffs_reg2(5), + R => RST_CPLLRESET + ); +rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_new_txcoeff_req, + Q => rxeq_new_txcoeff_req_reg_n_0, + R => RST_CPLLRESET + ); +\rxeq_preset[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8FFA800" + ) + port map ( + I0 => rxeq_preset_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => \rxeq_preset[2]_i_2__0_n_0\, + I4 => \rxeq_preset_reg_n_0_[0]\, + O => \rxeq_preset[0]_i_1__0_n_0\ + ); +\rxeq_preset[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8FFA800" + ) + port map ( + I0 => rxeq_preset_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => \rxeq_preset[2]_i_2__0_n_0\, + I4 => \rxeq_preset_reg_n_0_[1]\, + O => \rxeq_preset[1]_i_1__0_n_0\ + ); +\rxeq_preset[2]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8FFA800" + ) + port map ( + I0 => rxeq_preset_reg2(2), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => \rxeq_preset[2]_i_2__0_n_0\, + I4 => \rxeq_preset_reg_n_0_[2]\, + O => \rxeq_preset[2]_i_1__0_n_0\ + ); +\rxeq_preset[2]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF0002" + ) + port map ( + I0 => \rxeq_preset[2]_i_3__0_n_0\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + I4 => \rxeq_adapt_done_reg_i_2__0_n_0\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + O => \rxeq_preset[2]_i_2__0_n_0\ + ); +\rxeq_preset[2]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \rxeq_preset[2]_i_3__0_n_0\ + ); +\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_preset_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_preset_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_preset_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_reg1(0), + Q => rxeq_preset_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_reg1(1), + Q => rxeq_preset_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_reg1(2), + Q => rxeq_preset_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxeq_preset[0]_i_1__0_n_0\, + Q => \rxeq_preset_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxeq_preset[1]_i_1__0_n_0\, + Q => \rxeq_preset_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxeq_preset[2]_i_1__0_n_0\, + Q => \rxeq_preset_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +rxeq_preset_valid_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + Q => rxeq_preset_valid, + R => RST_CPLLRESET + ); +rxeq_scan_i: entity work.pcie_7x_0_pcie_7x_0_rxeq_scan_57 + port map ( + D(2) => rxeq_scan_i_n_0, + D(1) => rxeq_scan_i_n_1, + D(0) => rxeq_scan_i_n_2, + \FSM_onehot_fsm_rx_reg[5]\(2) => \rxeq_cnt_reg_n_0_[2]\, + \FSM_onehot_fsm_rx_reg[5]\(1) => \rxeq_cnt_reg_n_0_[1]\, + \FSM_onehot_fsm_rx_reg[5]\(0) => \rxeq_cnt_reg_n_0_[0]\, + Q(4) => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + Q(3) => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + Q(2) => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + Q(1) => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + Q(0) => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + RST_CPLLRESET => RST_CPLLRESET, + USER_RXEQ_ADAPT_DONE => \^user_rxeq_adapt_done\, + adapt_done_reg_0 => rxeq_scan_i_n_4, + \fs_reg1_reg[5]_0\(5) => \rxeq_fs_reg_n_0_[5]\, + \fs_reg1_reg[5]_0\(4) => \rxeq_fs_reg_n_0_[4]\, + \fs_reg1_reg[5]_0\(3) => \rxeq_fs_reg_n_0_[3]\, + \fs_reg1_reg[5]_0\(2) => \rxeq_fs_reg_n_0_[2]\, + \fs_reg1_reg[5]_0\(1) => \rxeq_fs_reg_n_0_[1]\, + \fs_reg1_reg[5]_0\(0) => \rxeq_fs_reg_n_0_[0]\, + \lf_reg1_reg[5]_0\(5) => \rxeq_lf_reg_n_0_[5]\, + \lf_reg1_reg[5]_0\(4) => \rxeq_lf_reg_n_0_[4]\, + \lf_reg1_reg[5]_0\(3) => \rxeq_lf_reg_n_0_[3]\, + \lf_reg1_reg[5]_0\(2) => \rxeq_lf_reg_n_0_[2]\, + \lf_reg1_reg[5]_0\(1) => \rxeq_lf_reg_n_0_[1]\, + \lf_reg1_reg[5]_0\(0) => \rxeq_lf_reg_n_0_[0]\, + new_txcoeff_done_reg_0 => rxeq_scan_i_n_5, + new_txcoeff_req_reg1_reg_0 => rxeq_new_txcoeff_req_reg_n_0, + \out\(1 downto 0) => rxeq_control_reg2(1 downto 0), + pipe_pclk_in => pipe_pclk_in, + \preset_reg1_reg[2]_0\(2) => \rxeq_preset_reg_n_0_[2]\, + \preset_reg1_reg[2]_0\(1) => \rxeq_preset_reg_n_0_[1]\, + \preset_reg1_reg[2]_0\(0) => \rxeq_preset_reg_n_0_[0]\, + rxeq_adapt_done_reg => \rxeq_adapt_done_i_2__0_n_0\, + rxeq_adapt_done_reg_reg => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\, + rxeq_adapt_done_reg_reg_0 => \rxeq_adapt_done_reg_i_2__0_n_0\, + rxeq_adapt_done_reg_reg_1 => rxeq_adapt_done_reg_reg_n_0, + rxeq_new_txcoeff_req => rxeq_new_txcoeff_req, + rxeq_preset_valid => rxeq_preset_valid, + \txcoeff_reg1_reg[17]_0\(17) => \rxeq_txcoeff_reg_n_0_[17]\, + \txcoeff_reg1_reg[17]_0\(16) => \rxeq_txcoeff_reg_n_0_[16]\, + \txcoeff_reg1_reg[17]_0\(15) => \rxeq_txcoeff_reg_n_0_[15]\, + \txcoeff_reg1_reg[17]_0\(14) => \rxeq_txcoeff_reg_n_0_[14]\, + \txcoeff_reg1_reg[17]_0\(13) => \rxeq_txcoeff_reg_n_0_[13]\, + \txcoeff_reg1_reg[17]_0\(12) => \rxeq_txcoeff_reg_n_0_[12]\, + \txcoeff_reg1_reg[17]_0\(11) => \rxeq_txcoeff_reg_n_0_[11]\, + \txcoeff_reg1_reg[17]_0\(10) => \rxeq_txcoeff_reg_n_0_[10]\, + \txcoeff_reg1_reg[17]_0\(9) => \rxeq_txcoeff_reg_n_0_[9]\, + \txcoeff_reg1_reg[17]_0\(8) => \rxeq_txcoeff_reg_n_0_[8]\, + \txcoeff_reg1_reg[17]_0\(7) => \rxeq_txcoeff_reg_n_0_[7]\, + \txcoeff_reg1_reg[17]_0\(6) => \rxeq_txcoeff_reg_n_0_[6]\, + \txcoeff_reg1_reg[17]_0\(5) => \rxeq_txcoeff_reg_n_0_[5]\, + \txcoeff_reg1_reg[17]_0\(4) => \rxeq_txcoeff_reg_n_0_[4]\, + \txcoeff_reg1_reg[17]_0\(3) => \rxeq_txcoeff_reg_n_0_[3]\, + \txcoeff_reg1_reg[17]_0\(2) => \rxeq_txcoeff_reg_n_0_[2]\, + \txcoeff_reg1_reg[17]_0\(1) => \rxeq_txcoeff_reg_n_0_[1]\, + \txcoeff_reg1_reg[17]_0\(0) => \rxeq_txcoeff_reg_n_0_[0]\, + \txpreset_reg1_reg[3]_0\(3) => \rxeq_txpreset_reg_n_0_[3]\, + \txpreset_reg1_reg[3]_0\(2) => \rxeq_txpreset_reg_n_0_[2]\, + \txpreset_reg1_reg[3]_0\(1) => \rxeq_txpreset_reg_n_0_[1]\, + \txpreset_reg1_reg[3]_0\(0) => \rxeq_txpreset_reg_n_0_[0]\ + ); +\rxeq_txcoeff[0]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[6]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(0) + ); +\rxeq_txcoeff[10]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[16]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(10) + ); +\rxeq_txcoeff[11]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[17]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(11) + ); +\rxeq_txcoeff[12]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(12) + ); +\rxeq_txcoeff[13]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(13) + ); +\rxeq_txcoeff[14]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(2), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(14) + ); +\rxeq_txcoeff[15]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(3), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(15) + ); +\rxeq_txcoeff[16]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(4), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(16) + ); +\rxeq_txcoeff[17]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(5), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(17) + ); +\rxeq_txcoeff[1]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[7]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(1) + ); +\rxeq_txcoeff[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[8]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(2) + ); +\rxeq_txcoeff[3]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[9]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(3) + ); +\rxeq_txcoeff[4]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[10]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(4) + ); +\rxeq_txcoeff[5]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[11]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(5) + ); +\rxeq_txcoeff[6]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[12]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(6) + ); +\rxeq_txcoeff[7]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[13]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(7) + ); +\rxeq_txcoeff[8]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[14]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(8) + ); +\rxeq_txcoeff[9]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[15]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(9) + ); +\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(0), + Q => \rxeq_txcoeff_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(10), + Q => \rxeq_txcoeff_reg_n_0_[10]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(11), + Q => \rxeq_txcoeff_reg_n_0_[11]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(12), + Q => \rxeq_txcoeff_reg_n_0_[12]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(13), + Q => \rxeq_txcoeff_reg_n_0_[13]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(14), + Q => \rxeq_txcoeff_reg_n_0_[14]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(15), + Q => \rxeq_txcoeff_reg_n_0_[15]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(16), + Q => \rxeq_txcoeff_reg_n_0_[16]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(17), + Q => \rxeq_txcoeff_reg_n_0_[17]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(1), + Q => \rxeq_txcoeff_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(2), + Q => \rxeq_txcoeff_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(3), + Q => \rxeq_txcoeff_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(4), + Q => \rxeq_txcoeff_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(5), + Q => \rxeq_txcoeff_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(6), + Q => \rxeq_txcoeff_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(7), + Q => \rxeq_txcoeff_reg_n_0_[7]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(8), + Q => \rxeq_txcoeff_reg_n_0_[8]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txcoeff(9), + Q => \rxeq_txcoeff_reg_n_0_[9]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset[0]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(0) + ); +\rxeq_txpreset[1]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(1) + ); +\rxeq_txpreset[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(2), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(2) + ); +\rxeq_txpreset[3]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFF404" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + I1 => \rxeq_txpreset[3]_i_3__0_n_0\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => rxeq_control_reg2(1), + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \rxeq_txpreset[3]_i_1__0_n_0\ + ); +\rxeq_txpreset[3]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(3), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(3) + ); +\rxeq_txpreset[3]_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + O => \rxeq_txpreset[3]_i_3__0_n_0\ + ); +\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(3), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(0), + Q => rxeq_txpreset_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(1), + Q => rxeq_txpreset_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(2), + Q => rxeq_txpreset_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(3), + Q => rxeq_txpreset_reg2(3), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txpreset(0), + Q => \rxeq_txpreset_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txpreset(1), + Q => \rxeq_txpreset_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txpreset(2), + Q => \rxeq_txpreset_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__0_n_0\, + D => rxeq_txpreset(3), + Q => \rxeq_txpreset_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_en_reg1, + R => RST_CPLLRESET + ); +rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_en_reg1, + Q => rxeq_user_en_reg2, + R => RST_CPLLRESET + ); +rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_mode_reg1, + R => RST_CPLLRESET + ); +rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_mode_reg1, + Q => rxeq_user_mode_reg2, + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(10), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(11), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(12), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(13), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(14), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(15), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(16), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(17), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(3), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(4), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(5), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(6), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(7), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(8), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(9), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(0), + Q => rxeq_user_txcoeff_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(10), + Q => rxeq_user_txcoeff_reg2(10), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(11), + Q => rxeq_user_txcoeff_reg2(11), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(12), + Q => rxeq_user_txcoeff_reg2(12), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(13), + Q => rxeq_user_txcoeff_reg2(13), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(14), + Q => rxeq_user_txcoeff_reg2(14), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(15), + Q => rxeq_user_txcoeff_reg2(15), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(16), + Q => rxeq_user_txcoeff_reg2(16), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(17), + Q => rxeq_user_txcoeff_reg2(17), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(1), + Q => rxeq_user_txcoeff_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(2), + Q => rxeq_user_txcoeff_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(3), + Q => rxeq_user_txcoeff_reg2(3), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(4), + Q => rxeq_user_txcoeff_reg2(4), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(5), + Q => rxeq_user_txcoeff_reg2(5), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(6), + Q => rxeq_user_txcoeff_reg2(6), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(7), + Q => rxeq_user_txcoeff_reg2(7), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(8), + Q => rxeq_user_txcoeff_reg2(8), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(9), + Q => rxeq_user_txcoeff_reg2(9), + R => RST_CPLLRESET + ); +\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_control_reg1(0), + R => RST_CPLLRESET + ); +\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_control_reg1(1), + R => RST_CPLLRESET + ); +\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_control_reg1(0), + Q => txeq_control_reg2(0), + R => RST_CPLLRESET + ); +\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_control_reg1(1), + Q => txeq_control_reg2(1), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(0), + S => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(1), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(2), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(3), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(4), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(5), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(0), + Q => txeq_deemph_reg2(0), + S => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(1), + Q => txeq_deemph_reg2(1), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(2), + Q => txeq_deemph_reg2(2), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(3), + Q => txeq_deemph_reg2(3), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(4), + Q => txeq_deemph_reg2(4), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(5), + Q => txeq_deemph_reg2(5), + R => RST_CPLLRESET + ); +\txeq_preset[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001000" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(2), + I2 => txeq_preset_reg2(0), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(1), + O => p_0_out(0) + ); +\txeq_preset[10]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABEAABAF" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(2), + I2 => txeq_preset_reg2(0), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(1), + O => p_0_out(10) + ); +\txeq_preset[11]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF200D" + ) + port map ( + I0 => txeq_preset_reg2(1), + I1 => txeq_preset_reg2(3), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(0), + I4 => RST_CPLLRESET, + O => p_0_out(11) + ); +\txeq_preset[12]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01151110" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(3), + I2 => txeq_preset_reg2(1), + I3 => txeq_preset_reg2(2), + I4 => txeq_preset_reg2(0), + O => p_0_out(12) + ); +\txeq_preset[13]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01000010" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => RST_CPLLRESET, + I2 => txeq_preset_reg2(0), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(1), + O => p_0_out(13) + ); +\txeq_preset[14]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01000010" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => RST_CPLLRESET, + I2 => txeq_preset_reg2(3), + I3 => txeq_preset_reg2(1), + I4 => txeq_preset_reg2(0), + O => p_0_out(14) + ); +\txeq_preset[15]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F0F1" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => txeq_preset_reg2(1), + I2 => RST_CPLLRESET, + I3 => txeq_preset_reg2(3), + O => p_0_out(15) + ); +\txeq_preset[16]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0006" + ) + port map ( + I0 => txeq_preset_reg2(3), + I1 => txeq_preset_reg2(0), + I2 => txeq_preset_reg2(2), + I3 => RST_CPLLRESET, + O => p_0_out(16) + ); +\txeq_preset[17]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AABA" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => fsm_tx(0), + I2 => fsm_tx(1), + I3 => fsm_tx(2), + O => \txeq_preset[17]_i_1__0_n_0\ + ); +\txeq_preset[17]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF400D" + ) + port map ( + I0 => txeq_preset_reg2(3), + I1 => txeq_preset_reg2(1), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(0), + I4 => RST_CPLLRESET, + O => p_0_out(17) + ); +\txeq_preset[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001004" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(3), + I2 => txeq_preset_reg2(1), + I3 => txeq_preset_reg2(2), + I4 => txeq_preset_reg2(0), + O => p_0_out(1) + ); +\txeq_preset[2]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0E00" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => txeq_preset_reg2(0), + I2 => RST_CPLLRESET, + I3 => txeq_preset_reg2(3), + O => p_0_out(2) + ); +\txeq_preset[3]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01440140" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(2), + I2 => txeq_preset_reg2(1), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(0), + O => \txeq_preset[3]_i_1__0_n_0\ + ); +\txeq_preset[7]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001400" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(0), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(1), + I4 => txeq_preset_reg2(3), + O => \txeq_preset[7]_i_1__0_n_0\ + ); +\txeq_preset[8]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAFBEAF" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(0), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(1), + I4 => txeq_preset_reg2(3), + O => p_0_out(8) + ); +\txeq_preset[9]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCFCCFCD" + ) + port map ( + I0 => txeq_preset_reg2(1), + I1 => RST_CPLLRESET, + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(0), + O => p_0_out(9) + ); +\txeq_preset_done_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => fsm_tx(2), + I1 => fsm_tx(1), + I2 => fsm_tx(0), + O => \txeq_preset_done_i_1__0_n_0\ + ); +txeq_preset_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txeq_preset_done_i_1__0_n_0\, + Q => txeq_preset_done, + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(0), + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(1), + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(2), + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(3), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(0), + Q => txeq_preset_reg2(0), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(1), + Q => txeq_preset_reg2(1), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(2), + Q => txeq_preset_reg2(2), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(3), + Q => txeq_preset_reg2(3), + R => RST_CPLLRESET + ); +\txeq_preset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => p_0_out(0), + Q => \txeq_preset_reg_n_0_[0]\, + R => '0' + ); +\txeq_preset_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => p_0_out(10), + Q => \txeq_preset_reg_n_0_[10]\, + R => '0' + ); +\txeq_preset_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => p_0_out(11), + Q => \txeq_preset_reg_n_0_[11]\, + R => '0' + ); +\txeq_preset_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => p_0_out(12), + Q => \txeq_preset_reg_n_0_[12]\, + R => '0' + ); +\txeq_preset_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => p_0_out(13), + Q => \txeq_preset_reg_n_0_[13]\, + R => '0' + ); +\txeq_preset_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => p_0_out(14), + Q => \txeq_preset_reg_n_0_[14]\, + R => '0' + ); +\txeq_preset_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => p_0_out(15), + Q => \txeq_preset_reg_n_0_[15]\, + R => '0' + ); +\txeq_preset_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => p_0_out(16), + Q => \txeq_preset_reg_n_0_[16]\, + R => '0' + ); +\txeq_preset_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => p_0_out(17), + Q => \txeq_preset_reg_n_0_[17]\, + R => '0' + ); +\txeq_preset_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => p_0_out(1), + Q => \txeq_preset_reg_n_0_[1]\, + R => '0' + ); +\txeq_preset_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => p_0_out(2), + Q => \txeq_preset_reg_n_0_[2]\, + R => '0' + ); +\txeq_preset_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => \txeq_preset[3]_i_1__0_n_0\, + Q => \txeq_preset_reg_n_0_[3]\, + R => '0' + ); +\txeq_preset_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => \txeq_preset[7]_i_1__0_n_0\, + Q => \txeq_preset_reg_n_0_[7]\, + R => '0' + ); +\txeq_preset_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => p_0_out(8), + Q => \txeq_preset_reg_n_0_[8]\, + R => '0' + ); +\txeq_preset_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__0_n_0\, + D => p_0_out(9), + Q => \txeq_preset_reg_n_0_[9]\, + R => '0' + ); +\txeq_txcoeff[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"45404040" + ) + port map ( + I0 => fsm_tx(2), + I1 => \txeq_txcoeff[0]_i_2__0_n_0\, + I2 => fsm_tx(1), + I3 => fsm_tx(0), + I4 => \txeq_txcoeff_reg_n_0_[6]\, + O => \txeq_txcoeff[0]_i_1__0_n_0\ + ); +\txeq_txcoeff[0]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[6]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[7]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[0]\, + O => \txeq_txcoeff[0]_i_2__0_n_0\ + ); +\txeq_txcoeff[10]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[9]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[10]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[16]\, + O => \txeq_txcoeff[10]_i_1__0_n_0\ + ); +\txeq_txcoeff[10]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[16]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[17]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[10]\, + O => \txeq_txcoeff[10]_i_2__0_n_0\ + ); +\txeq_txcoeff[11]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[10]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[11]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[17]\, + O => \txeq_txcoeff[11]_i_1__0_n_0\ + ); +\txeq_txcoeff[11]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[17]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[18]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[11]\, + O => \txeq_txcoeff[11]_i_2__0_n_0\ + ); +\txeq_txcoeff[12]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[11]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[12]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[18]\, + O => \txeq_txcoeff[12]_i_1__0_n_0\ + ); +\txeq_txcoeff[12]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[18]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(0), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[12]\, + O => \txeq_txcoeff[12]_i_2__0_n_0\ + ); +\txeq_txcoeff[13]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[12]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[13]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(0), + O => \txeq_txcoeff[13]_i_1__0_n_0\ + ); +\txeq_txcoeff[13]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(0), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(1), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[13]\, + O => \txeq_txcoeff[13]_i_2__0_n_0\ + ); +\txeq_txcoeff[14]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[13]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[14]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(1), + O => \txeq_txcoeff[14]_i_1__0_n_0\ + ); +\txeq_txcoeff[14]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(1), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(2), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[14]\, + O => \txeq_txcoeff[14]_i_2__0_n_0\ + ); +\txeq_txcoeff[15]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[14]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[15]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(2), + O => \txeq_txcoeff[15]_i_1__0_n_0\ + ); +\txeq_txcoeff[15]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(2), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(3), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[15]\, + O => \txeq_txcoeff[15]_i_2__0_n_0\ + ); +\txeq_txcoeff[16]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[15]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[16]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(3), + O => \txeq_txcoeff[16]_i_1__0_n_0\ + ); +\txeq_txcoeff[16]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(3), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(4), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[16]\, + O => \txeq_txcoeff[16]_i_2__0_n_0\ + ); +\txeq_txcoeff[17]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[16]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[17]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(4), + O => \txeq_txcoeff[17]_i_1__0_n_0\ + ); +\txeq_txcoeff[17]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(4), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(5), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[17]\, + O => \txeq_txcoeff[17]_i_2__0_n_0\ + ); +\txeq_txcoeff[18]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF040FFF" + ) + port map ( + I0 => txeq_control_reg2(0), + I1 => txeq_control_reg2(1), + I2 => fsm_tx(2), + I3 => fsm_tx(1), + I4 => fsm_tx(0), + O => txeq_txcoeff + ); +\txeq_txcoeff[18]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F3220022002200" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[17]\, + I1 => fsm_tx(1), + I2 => \txeq_txcoeff[18]_i_3__0_n_0\, + I3 => fsm_tx(2), + I4 => txeq_deemph_reg2(5), + I5 => fsm_tx(0), + O => \txeq_txcoeff[18]_i_2__0_n_0\ + ); +\txeq_txcoeff[18]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + O => \txeq_txcoeff[18]_i_3__0_n_0\ + ); +\txeq_txcoeff[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[0]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[1]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[7]\, + O => \txeq_txcoeff[1]_i_1__0_n_0\ + ); +\txeq_txcoeff[1]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[7]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[8]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[1]\, + O => \txeq_txcoeff[1]_i_2__0_n_0\ + ); +\txeq_txcoeff[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[1]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[2]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[8]\, + O => \txeq_txcoeff[2]_i_1__0_n_0\ + ); +\txeq_txcoeff[2]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[8]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[9]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[2]\, + O => \txeq_txcoeff[2]_i_2__0_n_0\ + ); +\txeq_txcoeff[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[2]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[3]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[9]\, + O => \txeq_txcoeff[3]_i_1__0_n_0\ + ); +\txeq_txcoeff[3]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[9]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[10]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[3]\, + O => \txeq_txcoeff[3]_i_2__0_n_0\ + ); +\txeq_txcoeff[4]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[3]\, + I1 => fsm_tx(1), + I2 => fsm_tx(2), + I3 => \txeq_txcoeff[4]_i_2__0_n_0\, + O => \txeq_txcoeff[4]_i_1__0_n_0\ + ); +\txeq_txcoeff[4]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACCCCCC00000000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[11]\, + I1 => \txeq_txcoeff_reg_n_0_[10]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I4 => fsm_tx(1), + I5 => fsm_tx(0), + O => \txeq_txcoeff[4]_i_2__0_n_0\ + ); +\txeq_txcoeff[5]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[4]\, + I1 => fsm_tx(1), + I2 => fsm_tx(2), + I3 => \txeq_txcoeff[5]_i_2__0_n_0\, + O => \txeq_txcoeff[5]_i_1__0_n_0\ + ); +\txeq_txcoeff[5]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACCCCCC00000000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[12]\, + I1 => \txeq_txcoeff_reg_n_0_[11]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I4 => fsm_tx(1), + I5 => fsm_tx(0), + O => \txeq_txcoeff[5]_i_2__0_n_0\ + ); +\txeq_txcoeff[6]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[5]\, + I1 => fsm_tx(1), + I2 => fsm_tx(2), + I3 => \txeq_txcoeff[6]_i_2__0_n_0\, + O => \txeq_txcoeff[6]_i_1__0_n_0\ + ); +\txeq_txcoeff[6]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACCCCCC00000000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[13]\, + I1 => \txeq_txcoeff_reg_n_0_[12]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I4 => fsm_tx(1), + I5 => fsm_tx(0), + O => \txeq_txcoeff[6]_i_2__0_n_0\ + ); +\txeq_txcoeff[7]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[6]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[7]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[13]\, + O => \txeq_txcoeff[7]_i_1__0_n_0\ + ); +\txeq_txcoeff[7]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[13]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[14]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[7]\, + O => \txeq_txcoeff[7]_i_2__0_n_0\ + ); +\txeq_txcoeff[8]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[7]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[8]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[14]\, + O => \txeq_txcoeff[8]_i_1__0_n_0\ + ); +\txeq_txcoeff[8]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[14]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[15]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[8]\, + O => \txeq_txcoeff[8]_i_2__0_n_0\ + ); +\txeq_txcoeff[9]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[8]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[9]_i_2__0_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[15]\, + O => \txeq_txcoeff[9]_i_1__0_n_0\ + ); +\txeq_txcoeff[9]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[15]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[16]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[9]\, + O => \txeq_txcoeff[9]_i_2__0_n_0\ + ); +\txeq_txcoeff_cnt[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000004000F000400" + ) + port map ( + I0 => txeq_control_reg2(0), + I1 => txeq_control_reg2(1), + I2 => fsm_tx(2), + I3 => fsm_tx(0), + I4 => fsm_tx(1), + I5 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + O => txeq_txcoeff_cnt(0) + ); +\txeq_txcoeff_cnt[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00006000" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I2 => fsm_tx(0), + I3 => fsm_tx(1), + I4 => fsm_tx(2), + O => txeq_txcoeff_cnt(1) + ); +\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_txcoeff_cnt(0), + Q => \txeq_txcoeff_cnt_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_txcoeff_cnt(1), + Q => \txeq_txcoeff_cnt_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[0]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[10]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[10]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[11]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[11]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[12]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[12]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[13]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[13]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[14]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[14]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[15]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[15]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[16]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[16]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[17]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[17]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[18]_i_2__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[18]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[1]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[2]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[3]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[4]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[5]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[6]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[7]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[7]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[8]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[8]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[9]_i_1__0_n_0\, + Q => \txeq_txcoeff_reg_n_0_[9]\, + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_eq_45 is + port ( + TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 ); + TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 ); + TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 ); + USER_RXEQ_ADAPT_DONE : out STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + rate_gen3_2 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_eq_45 : entity is "pcie_7x_0_pipe_eq"; +end pcie_7x_0_pcie_7x_0_pipe_eq_45; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_eq_45 is + signal \FSM_onehot_fsm_rx[1]_i_1__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[1]_i_2__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[3]_i_1__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[4]_i_1__1_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[5]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[6]\ : STD_LOGIC; + signal \FSM_sequential_fsm_tx[1]_i_2__1_n_0\ : STD_LOGIC; + signal \FSM_sequential_fsm_tx[2]_i_2__1_n_0\ : STD_LOGIC; + signal \^user_rxeq_adapt_done\ : STD_LOGIC; + signal fsm_tx : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \fsm_tx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal gen3_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of gen3_reg1 : signal is "true"; + signal gen3_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO"; + attribute async_reg of gen3_reg2 : signal is "true"; + signal p_0_out : STD_LOGIC_VECTOR ( 17 downto 0 ); + signal \rxeq_adapt_done_i_2__1_n_0\ : STD_LOGIC; + signal \rxeq_adapt_done_reg_i_2__1_n_0\ : STD_LOGIC; + signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC; + signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_control_reg1 : signal is "NO"; + attribute async_reg of rxeq_control_reg1 : signal is "true"; + signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_control_reg2 : signal is "NO"; + attribute async_reg of rxeq_control_reg2 : signal is "true"; + signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \rxeq_fs[5]_i_1__1_n_0\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[3]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[4]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[5]\ : STD_LOGIC; + signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \rxeq_lf[5]_i_1__1_n_0\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[3]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[4]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[5]\ : STD_LOGIC; + signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_lffs_reg1 : signal is "NO"; + attribute async_reg of rxeq_lffs_reg1 : signal is "true"; + signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_lffs_reg2 : signal is "NO"; + attribute async_reg of rxeq_lffs_reg2 : signal is "true"; + signal rxeq_new_txcoeff_req : STD_LOGIC; + signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC; + signal \rxeq_preset[0]_i_1__1_n_0\ : STD_LOGIC; + signal \rxeq_preset[1]_i_1__1_n_0\ : STD_LOGIC; + signal \rxeq_preset[2]_i_1__1_n_0\ : STD_LOGIC; + signal \rxeq_preset[2]_i_2__1_n_0\ : STD_LOGIC; + signal \rxeq_preset[2]_i_3__1_n_0\ : STD_LOGIC; + signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_preset_reg1 : signal is "NO"; + attribute async_reg of rxeq_preset_reg1 : signal is "true"; + signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_preset_reg2 : signal is "NO"; + attribute async_reg of rxeq_preset_reg2 : signal is "true"; + signal \rxeq_preset_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_preset_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_preset_reg_n_0_[2]\ : STD_LOGIC; + signal rxeq_preset_valid : STD_LOGIC; + signal rxeq_scan_i_n_0 : STD_LOGIC; + signal rxeq_scan_i_n_1 : STD_LOGIC; + signal rxeq_scan_i_n_2 : STD_LOGIC; + signal rxeq_scan_i_n_4 : STD_LOGIC; + signal rxeq_scan_i_n_5 : STD_LOGIC; + signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 ); + signal \rxeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC; + signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \rxeq_txpreset[3]_i_1__1_n_0\ : STD_LOGIC; + signal \rxeq_txpreset[3]_i_3__1_n_0\ : STD_LOGIC; + signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_txpreset_reg1 : signal is "NO"; + attribute async_reg of rxeq_txpreset_reg1 : signal is "true"; + signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_txpreset_reg2 : signal is "NO"; + attribute async_reg of rxeq_txpreset_reg2 : signal is "true"; + signal \rxeq_txpreset_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_txpreset_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_txpreset_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_txpreset_reg_n_0_[3]\ : STD_LOGIC; + signal rxeq_user_en_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_en_reg1 : signal is "NO"; + attribute async_reg of rxeq_user_en_reg1 : signal is "true"; + signal rxeq_user_en_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_en_reg2 : signal is "NO"; + attribute async_reg of rxeq_user_en_reg2 : signal is "true"; + signal rxeq_user_mode_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg1 : signal is "NO"; + attribute async_reg of rxeq_user_mode_reg1 : signal is "true"; + signal rxeq_user_mode_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg2 : signal is "NO"; + attribute async_reg of rxeq_user_mode_reg2 : signal is "true"; + signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg1 : signal is "NO"; + attribute async_reg of rxeq_user_txcoeff_reg1 : signal is "true"; + signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg2 : signal is "NO"; + attribute async_reg of rxeq_user_txcoeff_reg2 : signal is "true"; + signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of txeq_control_reg1 : signal is "NO"; + attribute async_reg of txeq_control_reg1 : signal is "true"; + signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of txeq_control_reg2 : signal is "NO"; + attribute async_reg of txeq_control_reg2 : signal is "true"; + signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of txeq_deemph_reg1 : signal is "NO"; + attribute async_reg of txeq_deemph_reg1 : signal is "true"; + signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of txeq_deemph_reg2 : signal is "NO"; + attribute async_reg of txeq_deemph_reg2 : signal is "true"; + signal \txeq_preset[17]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_preset[3]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_preset[7]_i_1__1_n_0\ : STD_LOGIC; + signal txeq_preset_done : STD_LOGIC; + signal \txeq_preset_done_i_1__1_n_0\ : STD_LOGIC; + signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txeq_preset_reg1 : signal is "NO"; + attribute async_reg of txeq_preset_reg1 : signal is "true"; + signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txeq_preset_reg2 : signal is "NO"; + attribute async_reg of txeq_preset_reg2 : signal is "true"; + signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC; + signal txeq_txcoeff : STD_LOGIC; + signal \txeq_txcoeff[0]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[0]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[10]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[10]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[11]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[11]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[12]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[12]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[13]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[13]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[14]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[14]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[15]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[15]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[16]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[16]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[17]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[17]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[18]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[18]_i_3__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[1]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[1]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[2]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[2]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[3]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[3]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[4]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[4]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[5]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[5]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[6]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[6]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[7]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[7]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[8]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[8]_i_2__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[9]_i_1__1_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[9]_i_2__1_n_0\ : STD_LOGIC; + signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[4]_i_1__1\ : label is "soft_lutpair144"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[1]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[2]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[3]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[4]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[5]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[6]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute SOFT_HLUTNM of \FSM_sequential_fsm_tx[1]_i_2__1\ : label is "soft_lutpair142"; + attribute SOFT_HLUTNM of \FSM_sequential_fsm_tx[2]_i_2__1\ : label is "soft_lutpair142"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[0]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[1]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[2]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of gen3_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true; + attribute KEEP of gen3_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_cnt[1]_i_1__1\ : label is "soft_lutpair145"; + attribute SOFT_HLUTNM of \rxeq_cnt[2]_i_1__1\ : label is "soft_lutpair144"; + attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[5]\ : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_preset[2]_i_3__1\ : label is "soft_lutpair145"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[2]\ : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[0]_i_1__1\ : label is "soft_lutpair146"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[10]_i_1__1\ : label is "soft_lutpair151"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[11]_i_1__1\ : label is "soft_lutpair151"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[1]_i_1__1\ : label is "soft_lutpair146"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[2]_i_1__1\ : label is "soft_lutpair147"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[3]_i_1__1\ : label is "soft_lutpair147"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[4]_i_1__1\ : label is "soft_lutpair148"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[5]_i_1__1\ : label is "soft_lutpair148"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[6]_i_1__1\ : label is "soft_lutpair149"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[7]_i_1__1\ : label is "soft_lutpair149"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[8]_i_1__1\ : label is "soft_lutpair150"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[9]_i_1__1\ : label is "soft_lutpair150"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_en_reg1_reg : label is std.standard.true; + attribute KEEP of rxeq_user_en_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_en_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_en_reg2_reg : label is std.standard.true; + attribute KEEP of rxeq_user_en_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_en_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_mode_reg1_reg : label is std.standard.true; + attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_mode_reg2_reg : label is std.standard.true; + attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[5]\ : label is "NO"; + attribute SOFT_HLUTNM of \txeq_preset_done_i_1__1\ : label is "soft_lutpair143"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[3]\ : label is "NO"; + attribute SOFT_HLUTNM of \txeq_txcoeff_cnt[1]_i_1__1\ : label is "soft_lutpair143"; +begin + USER_RXEQ_ADAPT_DONE <= \^user_rxeq_adapt_done\; +\FSM_onehot_fsm_rx[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABABABAA" + ) + port map ( + I0 => \FSM_onehot_fsm_rx[1]_i_2__1_n_0\, + I1 => rxeq_control_reg2(1), + I2 => rxeq_control_reg2(0), + I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + O => \FSM_onehot_fsm_rx[1]_i_1__1_n_0\ + ); +\FSM_onehot_fsm_rx[1]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + O => \FSM_onehot_fsm_rx[1]_i_2__1_n_0\ + ); +\FSM_onehot_fsm_rx[3]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF8FF88888888" + ) + port map ( + I0 => rxeq_control_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \rxeq_cnt_reg_n_0_[2]\, + I3 => \rxeq_cnt_reg_n_0_[1]\, + I4 => \rxeq_cnt_reg_n_0_[0]\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \FSM_onehot_fsm_rx[3]_i_1__1_n_0\ + ); +\FSM_onehot_fsm_rx[4]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"2ABA2AAA" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => \rxeq_cnt_reg_n_0_[2]\, + I2 => \rxeq_cnt_reg_n_0_[1]\, + I3 => \rxeq_cnt_reg_n_0_[0]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \FSM_onehot_fsm_rx[4]_i_1__1_n_0\ + ); +\FSM_onehot_fsm_rx_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx[1]_i_1__1_n_0\, + Q => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_2, + Q => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx[3]_i_1__1_n_0\, + Q => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx[4]_i_1__1_n_0\, + Q => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_1, + Q => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_0, + Q => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +\FSM_sequential_fsm_tx[0]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C04FC043C04FF04F" + ) + port map ( + I0 => \FSM_sequential_fsm_tx[1]_i_2__1_n_0\, + I1 => fsm_tx(0), + I2 => fsm_tx(1), + I3 => fsm_tx(2), + I4 => txeq_control_reg2(1), + I5 => txeq_control_reg2(0), + O => \fsm_tx__0\(0) + ); +\FSM_sequential_fsm_tx[1]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3F703F7C3F7C0F70" + ) + port map ( + I0 => \FSM_sequential_fsm_tx[1]_i_2__1_n_0\, + I1 => fsm_tx(0), + I2 => fsm_tx(1), + I3 => fsm_tx(2), + I4 => txeq_control_reg2(1), + I5 => txeq_control_reg2(0), + O => \fsm_tx__0\(1) + ); +\FSM_sequential_fsm_tx[1]_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + O => \FSM_sequential_fsm_tx[1]_i_2__1_n_0\ + ); +\FSM_sequential_fsm_tx[2]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3A2A2A227F7F7F77" + ) + port map ( + I0 => fsm_tx(2), + I1 => fsm_tx(1), + I2 => fsm_tx(0), + I3 => txeq_control_reg2(1), + I4 => txeq_control_reg2(0), + I5 => \FSM_sequential_fsm_tx[2]_i_2__1_n_0\, + O => \fsm_tx__0\(2) + ); +\FSM_sequential_fsm_tx[2]_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D0FFDFFF" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I2 => fsm_tx(0), + I3 => fsm_tx(1), + I4 => txeq_preset_done, + O => \FSM_sequential_fsm_tx[2]_i_2__1_n_0\ + ); +\FSM_sequential_fsm_tx_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fsm_tx__0\(0), + Q => fsm_tx(0), + S => RST_CPLLRESET + ); +\FSM_sequential_fsm_tx_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fsm_tx__0\(1), + Q => fsm_tx(1), + R => RST_CPLLRESET + ); +\FSM_sequential_fsm_tx_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fsm_tx__0\(2), + Q => fsm_tx(2), + R => RST_CPLLRESET + ); +gen3_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_gen3_2, + Q => gen3_reg1, + R => RST_CPLLRESET + ); +gen3_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gen3_reg1, + Q => gen3_reg2, + R => RST_CPLLRESET + ); +\gtx_channel.gtxe2_channel_i_i_22__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[17]\, + O => TXPOSTCURSOR(4) + ); +\gtx_channel.gtxe2_channel_i_i_23__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[16]\, + O => TXPOSTCURSOR(3) + ); +\gtx_channel.gtxe2_channel_i_i_24__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[15]\, + O => TXPOSTCURSOR(2) + ); +\gtx_channel.gtxe2_channel_i_i_25__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[14]\, + O => TXPOSTCURSOR(1) + ); +\gtx_channel.gtxe2_channel_i_i_26__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[13]\, + O => TXPOSTCURSOR(0) + ); +\gtx_channel.gtxe2_channel_i_i_27__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[4]\, + O => TXPRECURSOR(4) + ); +\gtx_channel.gtxe2_channel_i_i_28__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[3]\, + O => TXPRECURSOR(3) + ); +\gtx_channel.gtxe2_channel_i_i_29__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[2]\, + O => TXPRECURSOR(2) + ); +\gtx_channel.gtxe2_channel_i_i_30__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[1]\, + O => TXPRECURSOR(1) + ); +\gtx_channel.gtxe2_channel_i_i_31__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[0]\, + I1 => gen3_reg2, + O => TXPRECURSOR(0) + ); +\gtx_channel.gtxe2_channel_i_i_32__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[12]\, + O => TXMAINCURSOR(6) + ); +\gtx_channel.gtxe2_channel_i_i_33__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[11]\, + O => TXMAINCURSOR(5) + ); +\gtx_channel.gtxe2_channel_i_i_34__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[10]\, + O => TXMAINCURSOR(4) + ); +\gtx_channel.gtxe2_channel_i_i_35__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[9]\, + O => TXMAINCURSOR(3) + ); +\gtx_channel.gtxe2_channel_i_i_36__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[8]\, + O => TXMAINCURSOR(2) + ); +\gtx_channel.gtxe2_channel_i_i_37__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[7]\, + O => TXMAINCURSOR(1) + ); +\gtx_channel.gtxe2_channel_i_i_38__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[6]\, + O => TXMAINCURSOR(0) + ); +\rxeq_adapt_done_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFFFFFF" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + O => \rxeq_adapt_done_i_2__1_n_0\ + ); +rxeq_adapt_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_5, + Q => \^user_rxeq_adapt_done\, + R => RST_CPLLRESET + ); +\rxeq_adapt_done_reg_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => rxeq_control_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => rxeq_control_reg2(1), + O => \rxeq_adapt_done_reg_i_2__1_n_0\ + ); +rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_4, + Q => rxeq_adapt_done_reg_reg_n_0, + R => RST_CPLLRESET + ); +\rxeq_cnt[0]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8888FFF8" + ) + port map ( + I0 => rxeq_control_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I4 => \rxeq_cnt_reg_n_0_[0]\, + O => rxeq_cnt(0) + ); +\rxeq_cnt[1]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6660" + ) + port map ( + I0 => \rxeq_cnt_reg_n_0_[0]\, + I1 => \rxeq_cnt_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => rxeq_cnt(1) + ); +\rxeq_cnt[2]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"78787800" + ) + port map ( + I0 => \rxeq_cnt_reg_n_0_[1]\, + I1 => \rxeq_cnt_reg_n_0_[0]\, + I2 => \rxeq_cnt_reg_n_0_[2]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => rxeq_cnt(2) + ); +\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_cnt(0), + Q => \rxeq_cnt_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_cnt(1), + Q => \rxeq_cnt_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_cnt(2), + Q => \rxeq_cnt_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_control_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_control_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_control_reg1(0), + Q => rxeq_control_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_control_reg1(1), + Q => rxeq_control_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_fs[0]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(0), + O => rxeq_fs(0) + ); +\rxeq_fs[1]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(1), + O => rxeq_fs(1) + ); +\rxeq_fs[2]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(2), + O => rxeq_fs(2) + ); +\rxeq_fs[3]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(3), + O => rxeq_fs(3) + ); +\rxeq_fs[4]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(4), + O => rxeq_fs(4) + ); +\rxeq_fs[5]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F8" + ) + port map ( + I0 => rxeq_control_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx[1]_i_2__1_n_0\, + O => \rxeq_fs[5]_i_1__1_n_0\ + ); +\rxeq_fs[5]_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(5), + O => rxeq_fs(5) + ); +\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__1_n_0\, + D => rxeq_fs(0), + Q => \rxeq_fs_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__1_n_0\, + D => rxeq_fs(1), + Q => \rxeq_fs_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__1_n_0\, + D => rxeq_fs(2), + Q => \rxeq_fs_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__1_n_0\, + D => rxeq_fs(3), + Q => \rxeq_fs_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__1_n_0\, + D => rxeq_fs(4), + Q => \rxeq_fs_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__1_n_0\, + D => rxeq_fs(5), + Q => \rxeq_fs_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\rxeq_lf[0]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(0), + O => rxeq_lf(0) + ); +\rxeq_lf[1]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(1), + O => rxeq_lf(1) + ); +\rxeq_lf[2]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(2), + O => rxeq_lf(2) + ); +\rxeq_lf[3]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(3), + O => rxeq_lf(3) + ); +\rxeq_lf[4]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(4), + O => rxeq_lf(4) + ); +\rxeq_lf[5]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAAAAAAA" + ) + port map ( + I0 => \FSM_onehot_fsm_rx[1]_i_2__1_n_0\, + I1 => \rxeq_cnt_reg_n_0_[2]\, + I2 => \rxeq_cnt_reg_n_0_[0]\, + I3 => \rxeq_cnt_reg_n_0_[1]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + O => \rxeq_lf[5]_i_1__1_n_0\ + ); +\rxeq_lf[5]_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(5), + O => rxeq_lf(5) + ); +\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__1_n_0\, + D => rxeq_lf(0), + Q => \rxeq_lf_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__1_n_0\, + D => rxeq_lf(1), + Q => \rxeq_lf_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__1_n_0\, + D => rxeq_lf(2), + Q => \rxeq_lf_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__1_n_0\, + D => rxeq_lf(3), + Q => \rxeq_lf_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__1_n_0\, + D => rxeq_lf(4), + Q => \rxeq_lf_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__1_n_0\, + D => rxeq_lf(5), + Q => \rxeq_lf_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(3), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(4), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(5), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(0), + Q => rxeq_lffs_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(1), + Q => rxeq_lffs_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(2), + Q => rxeq_lffs_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(3), + Q => rxeq_lffs_reg2(3), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(4), + Q => rxeq_lffs_reg2(4), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(5), + Q => rxeq_lffs_reg2(5), + R => RST_CPLLRESET + ); +rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_new_txcoeff_req, + Q => rxeq_new_txcoeff_req_reg_n_0, + R => RST_CPLLRESET + ); +\rxeq_preset[0]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8FFA800" + ) + port map ( + I0 => rxeq_preset_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => \rxeq_preset[2]_i_2__1_n_0\, + I4 => \rxeq_preset_reg_n_0_[0]\, + O => \rxeq_preset[0]_i_1__1_n_0\ + ); +\rxeq_preset[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8FFA800" + ) + port map ( + I0 => rxeq_preset_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => \rxeq_preset[2]_i_2__1_n_0\, + I4 => \rxeq_preset_reg_n_0_[1]\, + O => \rxeq_preset[1]_i_1__1_n_0\ + ); +\rxeq_preset[2]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8FFA800" + ) + port map ( + I0 => rxeq_preset_reg2(2), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => \rxeq_preset[2]_i_2__1_n_0\, + I4 => \rxeq_preset_reg_n_0_[2]\, + O => \rxeq_preset[2]_i_1__1_n_0\ + ); +\rxeq_preset[2]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF0002" + ) + port map ( + I0 => \rxeq_preset[2]_i_3__1_n_0\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + I4 => \rxeq_adapt_done_reg_i_2__1_n_0\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + O => \rxeq_preset[2]_i_2__1_n_0\ + ); +\rxeq_preset[2]_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \rxeq_preset[2]_i_3__1_n_0\ + ); +\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_preset_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_preset_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_preset_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_reg1(0), + Q => rxeq_preset_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_reg1(1), + Q => rxeq_preset_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_reg1(2), + Q => rxeq_preset_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxeq_preset[0]_i_1__1_n_0\, + Q => \rxeq_preset_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxeq_preset[1]_i_1__1_n_0\, + Q => \rxeq_preset_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxeq_preset[2]_i_1__1_n_0\, + Q => \rxeq_preset_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +rxeq_preset_valid_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + Q => rxeq_preset_valid, + R => RST_CPLLRESET + ); +rxeq_scan_i: entity work.pcie_7x_0_pcie_7x_0_rxeq_scan_55 + port map ( + D(2) => rxeq_scan_i_n_0, + D(1) => rxeq_scan_i_n_1, + D(0) => rxeq_scan_i_n_2, + \FSM_onehot_fsm_rx_reg[5]\(2) => \rxeq_cnt_reg_n_0_[2]\, + \FSM_onehot_fsm_rx_reg[5]\(1) => \rxeq_cnt_reg_n_0_[1]\, + \FSM_onehot_fsm_rx_reg[5]\(0) => \rxeq_cnt_reg_n_0_[0]\, + Q(4) => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + Q(3) => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + Q(2) => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + Q(1) => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + Q(0) => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + RST_CPLLRESET => RST_CPLLRESET, + USER_RXEQ_ADAPT_DONE => \^user_rxeq_adapt_done\, + adapt_done_reg_0 => rxeq_scan_i_n_4, + \fs_reg1_reg[5]_0\(5) => \rxeq_fs_reg_n_0_[5]\, + \fs_reg1_reg[5]_0\(4) => \rxeq_fs_reg_n_0_[4]\, + \fs_reg1_reg[5]_0\(3) => \rxeq_fs_reg_n_0_[3]\, + \fs_reg1_reg[5]_0\(2) => \rxeq_fs_reg_n_0_[2]\, + \fs_reg1_reg[5]_0\(1) => \rxeq_fs_reg_n_0_[1]\, + \fs_reg1_reg[5]_0\(0) => \rxeq_fs_reg_n_0_[0]\, + \lf_reg1_reg[5]_0\(5) => \rxeq_lf_reg_n_0_[5]\, + \lf_reg1_reg[5]_0\(4) => \rxeq_lf_reg_n_0_[4]\, + \lf_reg1_reg[5]_0\(3) => \rxeq_lf_reg_n_0_[3]\, + \lf_reg1_reg[5]_0\(2) => \rxeq_lf_reg_n_0_[2]\, + \lf_reg1_reg[5]_0\(1) => \rxeq_lf_reg_n_0_[1]\, + \lf_reg1_reg[5]_0\(0) => \rxeq_lf_reg_n_0_[0]\, + new_txcoeff_done_reg_0 => rxeq_scan_i_n_5, + new_txcoeff_req_reg1_reg_0 => rxeq_new_txcoeff_req_reg_n_0, + \out\(1 downto 0) => rxeq_control_reg2(1 downto 0), + pipe_pclk_in => pipe_pclk_in, + \preset_reg1_reg[2]_0\(2) => \rxeq_preset_reg_n_0_[2]\, + \preset_reg1_reg[2]_0\(1) => \rxeq_preset_reg_n_0_[1]\, + \preset_reg1_reg[2]_0\(0) => \rxeq_preset_reg_n_0_[0]\, + rxeq_adapt_done_reg => \rxeq_adapt_done_i_2__1_n_0\, + rxeq_adapt_done_reg_reg => \FSM_onehot_fsm_rx[1]_i_2__1_n_0\, + rxeq_adapt_done_reg_reg_0 => \rxeq_adapt_done_reg_i_2__1_n_0\, + rxeq_adapt_done_reg_reg_1 => rxeq_adapt_done_reg_reg_n_0, + rxeq_new_txcoeff_req => rxeq_new_txcoeff_req, + rxeq_preset_valid => rxeq_preset_valid, + \txcoeff_reg1_reg[17]_0\(17) => \rxeq_txcoeff_reg_n_0_[17]\, + \txcoeff_reg1_reg[17]_0\(16) => \rxeq_txcoeff_reg_n_0_[16]\, + \txcoeff_reg1_reg[17]_0\(15) => \rxeq_txcoeff_reg_n_0_[15]\, + \txcoeff_reg1_reg[17]_0\(14) => \rxeq_txcoeff_reg_n_0_[14]\, + \txcoeff_reg1_reg[17]_0\(13) => \rxeq_txcoeff_reg_n_0_[13]\, + \txcoeff_reg1_reg[17]_0\(12) => \rxeq_txcoeff_reg_n_0_[12]\, + \txcoeff_reg1_reg[17]_0\(11) => \rxeq_txcoeff_reg_n_0_[11]\, + \txcoeff_reg1_reg[17]_0\(10) => \rxeq_txcoeff_reg_n_0_[10]\, + \txcoeff_reg1_reg[17]_0\(9) => \rxeq_txcoeff_reg_n_0_[9]\, + \txcoeff_reg1_reg[17]_0\(8) => \rxeq_txcoeff_reg_n_0_[8]\, + \txcoeff_reg1_reg[17]_0\(7) => \rxeq_txcoeff_reg_n_0_[7]\, + \txcoeff_reg1_reg[17]_0\(6) => \rxeq_txcoeff_reg_n_0_[6]\, + \txcoeff_reg1_reg[17]_0\(5) => \rxeq_txcoeff_reg_n_0_[5]\, + \txcoeff_reg1_reg[17]_0\(4) => \rxeq_txcoeff_reg_n_0_[4]\, + \txcoeff_reg1_reg[17]_0\(3) => \rxeq_txcoeff_reg_n_0_[3]\, + \txcoeff_reg1_reg[17]_0\(2) => \rxeq_txcoeff_reg_n_0_[2]\, + \txcoeff_reg1_reg[17]_0\(1) => \rxeq_txcoeff_reg_n_0_[1]\, + \txcoeff_reg1_reg[17]_0\(0) => \rxeq_txcoeff_reg_n_0_[0]\, + \txpreset_reg1_reg[3]_0\(3) => \rxeq_txpreset_reg_n_0_[3]\, + \txpreset_reg1_reg[3]_0\(2) => \rxeq_txpreset_reg_n_0_[2]\, + \txpreset_reg1_reg[3]_0\(1) => \rxeq_txpreset_reg_n_0_[1]\, + \txpreset_reg1_reg[3]_0\(0) => \rxeq_txpreset_reg_n_0_[0]\ + ); +\rxeq_txcoeff[0]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[6]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(0) + ); +\rxeq_txcoeff[10]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[16]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(10) + ); +\rxeq_txcoeff[11]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[17]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(11) + ); +\rxeq_txcoeff[12]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(12) + ); +\rxeq_txcoeff[13]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(13) + ); +\rxeq_txcoeff[14]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(2), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(14) + ); +\rxeq_txcoeff[15]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(3), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(15) + ); +\rxeq_txcoeff[16]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(4), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(16) + ); +\rxeq_txcoeff[17]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(5), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(17) + ); +\rxeq_txcoeff[1]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[7]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(1) + ); +\rxeq_txcoeff[2]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[8]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(2) + ); +\rxeq_txcoeff[3]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[9]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(3) + ); +\rxeq_txcoeff[4]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[10]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(4) + ); +\rxeq_txcoeff[5]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[11]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(5) + ); +\rxeq_txcoeff[6]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[12]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(6) + ); +\rxeq_txcoeff[7]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[13]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(7) + ); +\rxeq_txcoeff[8]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[14]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(8) + ); +\rxeq_txcoeff[9]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[15]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(9) + ); +\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(0), + Q => \rxeq_txcoeff_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(10), + Q => \rxeq_txcoeff_reg_n_0_[10]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(11), + Q => \rxeq_txcoeff_reg_n_0_[11]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(12), + Q => \rxeq_txcoeff_reg_n_0_[12]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(13), + Q => \rxeq_txcoeff_reg_n_0_[13]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(14), + Q => \rxeq_txcoeff_reg_n_0_[14]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(15), + Q => \rxeq_txcoeff_reg_n_0_[15]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(16), + Q => \rxeq_txcoeff_reg_n_0_[16]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(17), + Q => \rxeq_txcoeff_reg_n_0_[17]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(1), + Q => \rxeq_txcoeff_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(2), + Q => \rxeq_txcoeff_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(3), + Q => \rxeq_txcoeff_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(4), + Q => \rxeq_txcoeff_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(5), + Q => \rxeq_txcoeff_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(6), + Q => \rxeq_txcoeff_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(7), + Q => \rxeq_txcoeff_reg_n_0_[7]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(8), + Q => \rxeq_txcoeff_reg_n_0_[8]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txcoeff(9), + Q => \rxeq_txcoeff_reg_n_0_[9]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset[0]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(0) + ); +\rxeq_txpreset[1]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(1) + ); +\rxeq_txpreset[2]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(2), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(2) + ); +\rxeq_txpreset[3]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFF404" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + I1 => \rxeq_txpreset[3]_i_3__1_n_0\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => rxeq_control_reg2(1), + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \rxeq_txpreset[3]_i_1__1_n_0\ + ); +\rxeq_txpreset[3]_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(3), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(3) + ); +\rxeq_txpreset[3]_i_3__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + O => \rxeq_txpreset[3]_i_3__1_n_0\ + ); +\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(3), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(0), + Q => rxeq_txpreset_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(1), + Q => rxeq_txpreset_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(2), + Q => rxeq_txpreset_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(3), + Q => rxeq_txpreset_reg2(3), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txpreset(0), + Q => \rxeq_txpreset_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txpreset(1), + Q => \rxeq_txpreset_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txpreset(2), + Q => \rxeq_txpreset_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__1_n_0\, + D => rxeq_txpreset(3), + Q => \rxeq_txpreset_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_en_reg1, + R => RST_CPLLRESET + ); +rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_en_reg1, + Q => rxeq_user_en_reg2, + R => RST_CPLLRESET + ); +rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_mode_reg1, + R => RST_CPLLRESET + ); +rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_mode_reg1, + Q => rxeq_user_mode_reg2, + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(10), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(11), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(12), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(13), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(14), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(15), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(16), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(17), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(3), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(4), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(5), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(6), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(7), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(8), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(9), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(0), + Q => rxeq_user_txcoeff_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(10), + Q => rxeq_user_txcoeff_reg2(10), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(11), + Q => rxeq_user_txcoeff_reg2(11), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(12), + Q => rxeq_user_txcoeff_reg2(12), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(13), + Q => rxeq_user_txcoeff_reg2(13), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(14), + Q => rxeq_user_txcoeff_reg2(14), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(15), + Q => rxeq_user_txcoeff_reg2(15), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(16), + Q => rxeq_user_txcoeff_reg2(16), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(17), + Q => rxeq_user_txcoeff_reg2(17), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(1), + Q => rxeq_user_txcoeff_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(2), + Q => rxeq_user_txcoeff_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(3), + Q => rxeq_user_txcoeff_reg2(3), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(4), + Q => rxeq_user_txcoeff_reg2(4), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(5), + Q => rxeq_user_txcoeff_reg2(5), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(6), + Q => rxeq_user_txcoeff_reg2(6), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(7), + Q => rxeq_user_txcoeff_reg2(7), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(8), + Q => rxeq_user_txcoeff_reg2(8), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(9), + Q => rxeq_user_txcoeff_reg2(9), + R => RST_CPLLRESET + ); +\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_control_reg1(0), + R => RST_CPLLRESET + ); +\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_control_reg1(1), + R => RST_CPLLRESET + ); +\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_control_reg1(0), + Q => txeq_control_reg2(0), + R => RST_CPLLRESET + ); +\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_control_reg1(1), + Q => txeq_control_reg2(1), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(0), + S => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(1), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(2), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(3), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(4), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(5), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(0), + Q => txeq_deemph_reg2(0), + S => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(1), + Q => txeq_deemph_reg2(1), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(2), + Q => txeq_deemph_reg2(2), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(3), + Q => txeq_deemph_reg2(3), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(4), + Q => txeq_deemph_reg2(4), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(5), + Q => txeq_deemph_reg2(5), + R => RST_CPLLRESET + ); +\txeq_preset[0]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001000" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(2), + I2 => txeq_preset_reg2(0), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(1), + O => p_0_out(0) + ); +\txeq_preset[10]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABEAABAF" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(2), + I2 => txeq_preset_reg2(0), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(1), + O => p_0_out(10) + ); +\txeq_preset[11]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF200D" + ) + port map ( + I0 => txeq_preset_reg2(1), + I1 => txeq_preset_reg2(3), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(0), + I4 => RST_CPLLRESET, + O => p_0_out(11) + ); +\txeq_preset[12]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01151110" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(3), + I2 => txeq_preset_reg2(1), + I3 => txeq_preset_reg2(2), + I4 => txeq_preset_reg2(0), + O => p_0_out(12) + ); +\txeq_preset[13]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01000010" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => RST_CPLLRESET, + I2 => txeq_preset_reg2(0), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(1), + O => p_0_out(13) + ); +\txeq_preset[14]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01000010" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => RST_CPLLRESET, + I2 => txeq_preset_reg2(3), + I3 => txeq_preset_reg2(1), + I4 => txeq_preset_reg2(0), + O => p_0_out(14) + ); +\txeq_preset[15]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F0F1" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => txeq_preset_reg2(1), + I2 => RST_CPLLRESET, + I3 => txeq_preset_reg2(3), + O => p_0_out(15) + ); +\txeq_preset[16]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0006" + ) + port map ( + I0 => txeq_preset_reg2(3), + I1 => txeq_preset_reg2(0), + I2 => txeq_preset_reg2(2), + I3 => RST_CPLLRESET, + O => p_0_out(16) + ); +\txeq_preset[17]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AABA" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => fsm_tx(0), + I2 => fsm_tx(1), + I3 => fsm_tx(2), + O => \txeq_preset[17]_i_1__1_n_0\ + ); +\txeq_preset[17]_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF400D" + ) + port map ( + I0 => txeq_preset_reg2(3), + I1 => txeq_preset_reg2(1), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(0), + I4 => RST_CPLLRESET, + O => p_0_out(17) + ); +\txeq_preset[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001004" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(3), + I2 => txeq_preset_reg2(1), + I3 => txeq_preset_reg2(2), + I4 => txeq_preset_reg2(0), + O => p_0_out(1) + ); +\txeq_preset[2]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0E00" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => txeq_preset_reg2(0), + I2 => RST_CPLLRESET, + I3 => txeq_preset_reg2(3), + O => p_0_out(2) + ); +\txeq_preset[3]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01440140" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(2), + I2 => txeq_preset_reg2(1), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(0), + O => \txeq_preset[3]_i_1__1_n_0\ + ); +\txeq_preset[7]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001400" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(0), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(1), + I4 => txeq_preset_reg2(3), + O => \txeq_preset[7]_i_1__1_n_0\ + ); +\txeq_preset[8]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAFBEAF" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(0), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(1), + I4 => txeq_preset_reg2(3), + O => p_0_out(8) + ); +\txeq_preset[9]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCFCCFCD" + ) + port map ( + I0 => txeq_preset_reg2(1), + I1 => RST_CPLLRESET, + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(0), + O => p_0_out(9) + ); +\txeq_preset_done_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => fsm_tx(2), + I1 => fsm_tx(1), + I2 => fsm_tx(0), + O => \txeq_preset_done_i_1__1_n_0\ + ); +txeq_preset_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txeq_preset_done_i_1__1_n_0\, + Q => txeq_preset_done, + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(0), + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(1), + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(2), + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(3), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(0), + Q => txeq_preset_reg2(0), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(1), + Q => txeq_preset_reg2(1), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(2), + Q => txeq_preset_reg2(2), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(3), + Q => txeq_preset_reg2(3), + R => RST_CPLLRESET + ); +\txeq_preset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => p_0_out(0), + Q => \txeq_preset_reg_n_0_[0]\, + R => '0' + ); +\txeq_preset_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => p_0_out(10), + Q => \txeq_preset_reg_n_0_[10]\, + R => '0' + ); +\txeq_preset_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => p_0_out(11), + Q => \txeq_preset_reg_n_0_[11]\, + R => '0' + ); +\txeq_preset_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => p_0_out(12), + Q => \txeq_preset_reg_n_0_[12]\, + R => '0' + ); +\txeq_preset_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => p_0_out(13), + Q => \txeq_preset_reg_n_0_[13]\, + R => '0' + ); +\txeq_preset_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => p_0_out(14), + Q => \txeq_preset_reg_n_0_[14]\, + R => '0' + ); +\txeq_preset_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => p_0_out(15), + Q => \txeq_preset_reg_n_0_[15]\, + R => '0' + ); +\txeq_preset_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => p_0_out(16), + Q => \txeq_preset_reg_n_0_[16]\, + R => '0' + ); +\txeq_preset_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => p_0_out(17), + Q => \txeq_preset_reg_n_0_[17]\, + R => '0' + ); +\txeq_preset_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => p_0_out(1), + Q => \txeq_preset_reg_n_0_[1]\, + R => '0' + ); +\txeq_preset_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => p_0_out(2), + Q => \txeq_preset_reg_n_0_[2]\, + R => '0' + ); +\txeq_preset_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => \txeq_preset[3]_i_1__1_n_0\, + Q => \txeq_preset_reg_n_0_[3]\, + R => '0' + ); +\txeq_preset_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => \txeq_preset[7]_i_1__1_n_0\, + Q => \txeq_preset_reg_n_0_[7]\, + R => '0' + ); +\txeq_preset_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => p_0_out(8), + Q => \txeq_preset_reg_n_0_[8]\, + R => '0' + ); +\txeq_preset_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__1_n_0\, + D => p_0_out(9), + Q => \txeq_preset_reg_n_0_[9]\, + R => '0' + ); +\txeq_txcoeff[0]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"45404040" + ) + port map ( + I0 => fsm_tx(2), + I1 => \txeq_txcoeff[0]_i_2__1_n_0\, + I2 => fsm_tx(1), + I3 => fsm_tx(0), + I4 => \txeq_txcoeff_reg_n_0_[6]\, + O => \txeq_txcoeff[0]_i_1__1_n_0\ + ); +\txeq_txcoeff[0]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[6]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[7]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[0]\, + O => \txeq_txcoeff[0]_i_2__1_n_0\ + ); +\txeq_txcoeff[10]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[9]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[10]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[16]\, + O => \txeq_txcoeff[10]_i_1__1_n_0\ + ); +\txeq_txcoeff[10]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[16]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[17]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[10]\, + O => \txeq_txcoeff[10]_i_2__1_n_0\ + ); +\txeq_txcoeff[11]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[10]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[11]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[17]\, + O => \txeq_txcoeff[11]_i_1__1_n_0\ + ); +\txeq_txcoeff[11]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[17]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[18]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[11]\, + O => \txeq_txcoeff[11]_i_2__1_n_0\ + ); +\txeq_txcoeff[12]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[11]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[12]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[18]\, + O => \txeq_txcoeff[12]_i_1__1_n_0\ + ); +\txeq_txcoeff[12]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[18]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(0), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[12]\, + O => \txeq_txcoeff[12]_i_2__1_n_0\ + ); +\txeq_txcoeff[13]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[12]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[13]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(0), + O => \txeq_txcoeff[13]_i_1__1_n_0\ + ); +\txeq_txcoeff[13]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(0), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(1), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[13]\, + O => \txeq_txcoeff[13]_i_2__1_n_0\ + ); +\txeq_txcoeff[14]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[13]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[14]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(1), + O => \txeq_txcoeff[14]_i_1__1_n_0\ + ); +\txeq_txcoeff[14]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(1), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(2), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[14]\, + O => \txeq_txcoeff[14]_i_2__1_n_0\ + ); +\txeq_txcoeff[15]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[14]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[15]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(2), + O => \txeq_txcoeff[15]_i_1__1_n_0\ + ); +\txeq_txcoeff[15]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(2), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(3), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[15]\, + O => \txeq_txcoeff[15]_i_2__1_n_0\ + ); +\txeq_txcoeff[16]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[15]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[16]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(3), + O => \txeq_txcoeff[16]_i_1__1_n_0\ + ); +\txeq_txcoeff[16]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(3), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(4), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[16]\, + O => \txeq_txcoeff[16]_i_2__1_n_0\ + ); +\txeq_txcoeff[17]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[16]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[17]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(4), + O => \txeq_txcoeff[17]_i_1__1_n_0\ + ); +\txeq_txcoeff[17]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(4), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(5), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[17]\, + O => \txeq_txcoeff[17]_i_2__1_n_0\ + ); +\txeq_txcoeff[18]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF040FFF" + ) + port map ( + I0 => txeq_control_reg2(0), + I1 => txeq_control_reg2(1), + I2 => fsm_tx(2), + I3 => fsm_tx(1), + I4 => fsm_tx(0), + O => txeq_txcoeff + ); +\txeq_txcoeff[18]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F3220022002200" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[17]\, + I1 => fsm_tx(1), + I2 => \txeq_txcoeff[18]_i_3__1_n_0\, + I3 => fsm_tx(2), + I4 => txeq_deemph_reg2(5), + I5 => fsm_tx(0), + O => \txeq_txcoeff[18]_i_2__1_n_0\ + ); +\txeq_txcoeff[18]_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + O => \txeq_txcoeff[18]_i_3__1_n_0\ + ); +\txeq_txcoeff[1]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[0]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[1]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[7]\, + O => \txeq_txcoeff[1]_i_1__1_n_0\ + ); +\txeq_txcoeff[1]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[7]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[8]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[1]\, + O => \txeq_txcoeff[1]_i_2__1_n_0\ + ); +\txeq_txcoeff[2]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[1]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[2]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[8]\, + O => \txeq_txcoeff[2]_i_1__1_n_0\ + ); +\txeq_txcoeff[2]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[8]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[9]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[2]\, + O => \txeq_txcoeff[2]_i_2__1_n_0\ + ); +\txeq_txcoeff[3]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[2]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[3]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[9]\, + O => \txeq_txcoeff[3]_i_1__1_n_0\ + ); +\txeq_txcoeff[3]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[9]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[10]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[3]\, + O => \txeq_txcoeff[3]_i_2__1_n_0\ + ); +\txeq_txcoeff[4]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[3]\, + I1 => fsm_tx(1), + I2 => fsm_tx(2), + I3 => \txeq_txcoeff[4]_i_2__1_n_0\, + O => \txeq_txcoeff[4]_i_1__1_n_0\ + ); +\txeq_txcoeff[4]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACCCCCC00000000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[11]\, + I1 => \txeq_txcoeff_reg_n_0_[10]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I4 => fsm_tx(1), + I5 => fsm_tx(0), + O => \txeq_txcoeff[4]_i_2__1_n_0\ + ); +\txeq_txcoeff[5]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[4]\, + I1 => fsm_tx(1), + I2 => fsm_tx(2), + I3 => \txeq_txcoeff[5]_i_2__1_n_0\, + O => \txeq_txcoeff[5]_i_1__1_n_0\ + ); +\txeq_txcoeff[5]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACCCCCC00000000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[12]\, + I1 => \txeq_txcoeff_reg_n_0_[11]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I4 => fsm_tx(1), + I5 => fsm_tx(0), + O => \txeq_txcoeff[5]_i_2__1_n_0\ + ); +\txeq_txcoeff[6]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[5]\, + I1 => fsm_tx(1), + I2 => fsm_tx(2), + I3 => \txeq_txcoeff[6]_i_2__1_n_0\, + O => \txeq_txcoeff[6]_i_1__1_n_0\ + ); +\txeq_txcoeff[6]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACCCCCC00000000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[13]\, + I1 => \txeq_txcoeff_reg_n_0_[12]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I4 => fsm_tx(1), + I5 => fsm_tx(0), + O => \txeq_txcoeff[6]_i_2__1_n_0\ + ); +\txeq_txcoeff[7]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[6]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[7]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[13]\, + O => \txeq_txcoeff[7]_i_1__1_n_0\ + ); +\txeq_txcoeff[7]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[13]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[14]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[7]\, + O => \txeq_txcoeff[7]_i_2__1_n_0\ + ); +\txeq_txcoeff[8]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[7]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[8]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[14]\, + O => \txeq_txcoeff[8]_i_1__1_n_0\ + ); +\txeq_txcoeff[8]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[14]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[15]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[8]\, + O => \txeq_txcoeff[8]_i_2__1_n_0\ + ); +\txeq_txcoeff[9]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[8]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[9]_i_2__1_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[15]\, + O => \txeq_txcoeff[9]_i_1__1_n_0\ + ); +\txeq_txcoeff[9]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[15]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[16]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[9]\, + O => \txeq_txcoeff[9]_i_2__1_n_0\ + ); +\txeq_txcoeff_cnt[0]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000004000F000400" + ) + port map ( + I0 => txeq_control_reg2(0), + I1 => txeq_control_reg2(1), + I2 => fsm_tx(2), + I3 => fsm_tx(0), + I4 => fsm_tx(1), + I5 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + O => txeq_txcoeff_cnt(0) + ); +\txeq_txcoeff_cnt[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00006000" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I2 => fsm_tx(0), + I3 => fsm_tx(1), + I4 => fsm_tx(2), + O => txeq_txcoeff_cnt(1) + ); +\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_txcoeff_cnt(0), + Q => \txeq_txcoeff_cnt_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_txcoeff_cnt(1), + Q => \txeq_txcoeff_cnt_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[0]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[10]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[10]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[11]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[11]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[12]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[12]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[13]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[13]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[14]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[14]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[15]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[15]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[16]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[16]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[17]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[17]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[18]_i_2__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[18]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[1]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[2]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[3]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[4]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[5]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[6]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[7]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[7]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[8]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[8]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[9]_i_1__1_n_0\, + Q => \txeq_txcoeff_reg_n_0_[9]\, + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_eq_51 is + port ( + TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 ); + TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 ); + TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 ); + USER_RXEQ_ADAPT_DONE : out STD_LOGIC; + RST_CPLLRESET : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + rate_gen3_3 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pipe_eq_51 : entity is "pcie_7x_0_pipe_eq"; +end pcie_7x_0_pcie_7x_0_pipe_eq_51; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_eq_51 is + signal \FSM_onehot_fsm_rx[1]_i_1__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[1]_i_2__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[3]_i_1__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx[4]_i_1__2_n_0\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[2]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[4]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[5]\ : STD_LOGIC; + signal \FSM_onehot_fsm_rx_reg_n_0_[6]\ : STD_LOGIC; + signal \FSM_sequential_fsm_tx[1]_i_2__2_n_0\ : STD_LOGIC; + signal \FSM_sequential_fsm_tx[2]_i_2__2_n_0\ : STD_LOGIC; + signal \^user_rxeq_adapt_done\ : STD_LOGIC; + signal fsm_tx : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \fsm_tx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal gen3_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of gen3_reg1 : signal is "true"; + signal gen3_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO"; + attribute async_reg of gen3_reg2 : signal is "true"; + signal p_0_out : STD_LOGIC_VECTOR ( 17 downto 0 ); + signal \rxeq_adapt_done_i_2__2_n_0\ : STD_LOGIC; + signal \rxeq_adapt_done_reg_i_2__2_n_0\ : STD_LOGIC; + signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC; + signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_control_reg1 : signal is "NO"; + attribute async_reg of rxeq_control_reg1 : signal is "true"; + signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_control_reg2 : signal is "NO"; + attribute async_reg of rxeq_control_reg2 : signal is "true"; + signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \rxeq_fs[5]_i_1__2_n_0\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[3]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[4]\ : STD_LOGIC; + signal \rxeq_fs_reg_n_0_[5]\ : STD_LOGIC; + signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \rxeq_lf[5]_i_1__2_n_0\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[3]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[4]\ : STD_LOGIC; + signal \rxeq_lf_reg_n_0_[5]\ : STD_LOGIC; + signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_lffs_reg1 : signal is "NO"; + attribute async_reg of rxeq_lffs_reg1 : signal is "true"; + signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_lffs_reg2 : signal is "NO"; + attribute async_reg of rxeq_lffs_reg2 : signal is "true"; + signal rxeq_new_txcoeff_req : STD_LOGIC; + signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC; + signal \rxeq_preset[0]_i_1__2_n_0\ : STD_LOGIC; + signal \rxeq_preset[1]_i_1__2_n_0\ : STD_LOGIC; + signal \rxeq_preset[2]_i_1__2_n_0\ : STD_LOGIC; + signal \rxeq_preset[2]_i_2__2_n_0\ : STD_LOGIC; + signal \rxeq_preset[2]_i_3__2_n_0\ : STD_LOGIC; + signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_preset_reg1 : signal is "NO"; + attribute async_reg of rxeq_preset_reg1 : signal is "true"; + signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_preset_reg2 : signal is "NO"; + attribute async_reg of rxeq_preset_reg2 : signal is "true"; + signal \rxeq_preset_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_preset_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_preset_reg_n_0_[2]\ : STD_LOGIC; + signal rxeq_preset_valid : STD_LOGIC; + signal rxeq_scan_i_n_0 : STD_LOGIC; + signal rxeq_scan_i_n_1 : STD_LOGIC; + signal rxeq_scan_i_n_2 : STD_LOGIC; + signal rxeq_scan_i_n_4 : STD_LOGIC; + signal rxeq_scan_i_n_5 : STD_LOGIC; + signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 ); + signal \rxeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC; + signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC; + signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \rxeq_txpreset[3]_i_1__2_n_0\ : STD_LOGIC; + signal \rxeq_txpreset[3]_i_3__2_n_0\ : STD_LOGIC; + signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_txpreset_reg1 : signal is "NO"; + attribute async_reg of rxeq_txpreset_reg1 : signal is "true"; + signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_txpreset_reg2 : signal is "NO"; + attribute async_reg of rxeq_txpreset_reg2 : signal is "true"; + signal \rxeq_txpreset_reg_n_0_[0]\ : STD_LOGIC; + signal \rxeq_txpreset_reg_n_0_[1]\ : STD_LOGIC; + signal \rxeq_txpreset_reg_n_0_[2]\ : STD_LOGIC; + signal \rxeq_txpreset_reg_n_0_[3]\ : STD_LOGIC; + signal rxeq_user_en_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_en_reg1 : signal is "NO"; + attribute async_reg of rxeq_user_en_reg1 : signal is "true"; + signal rxeq_user_en_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_en_reg2 : signal is "NO"; + attribute async_reg of rxeq_user_en_reg2 : signal is "true"; + signal rxeq_user_mode_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg1 : signal is "NO"; + attribute async_reg of rxeq_user_mode_reg1 : signal is "true"; + signal rxeq_user_mode_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg2 : signal is "NO"; + attribute async_reg of rxeq_user_mode_reg2 : signal is "true"; + signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg1 : signal is "NO"; + attribute async_reg of rxeq_user_txcoeff_reg1 : signal is "true"; + signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 ); + attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg2 : signal is "NO"; + attribute async_reg of rxeq_user_txcoeff_reg2 : signal is "true"; + signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of txeq_control_reg1 : signal is "NO"; + attribute async_reg of txeq_control_reg1 : signal is "true"; + signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SHIFT_EXTRACT of txeq_control_reg2 : signal is "NO"; + attribute async_reg of txeq_control_reg2 : signal is "true"; + signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of txeq_deemph_reg1 : signal is "NO"; + attribute async_reg of txeq_deemph_reg1 : signal is "true"; + signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SHIFT_EXTRACT of txeq_deemph_reg2 : signal is "NO"; + attribute async_reg of txeq_deemph_reg2 : signal is "true"; + signal \txeq_preset[17]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_preset[3]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_preset[7]_i_1__2_n_0\ : STD_LOGIC; + signal txeq_preset_done : STD_LOGIC; + signal \txeq_preset_done_i_1__2_n_0\ : STD_LOGIC; + signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txeq_preset_reg1 : signal is "NO"; + attribute async_reg of txeq_preset_reg1 : signal is "true"; + signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SHIFT_EXTRACT of txeq_preset_reg2 : signal is "NO"; + attribute async_reg of txeq_preset_reg2 : signal is "true"; + signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC; + signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC; + signal txeq_txcoeff : STD_LOGIC; + signal \txeq_txcoeff[0]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[0]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[10]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[10]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[11]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[11]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[12]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[12]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[13]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[13]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[14]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[14]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[15]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[15]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[16]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[16]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[17]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[17]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[18]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[18]_i_3__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[1]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[1]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[2]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[2]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[3]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[3]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[4]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[4]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[5]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[5]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[6]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[6]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[7]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[7]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[8]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[8]_i_2__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[9]_i_1__2_n_0\ : STD_LOGIC; + signal \txeq_txcoeff[9]_i_2__2_n_0\ : STD_LOGIC; + signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC; + signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[4]_i_1__2\ : label is "soft_lutpair185"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[1]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[2]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[3]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[4]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[5]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[6]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001"; + attribute SOFT_HLUTNM of \FSM_sequential_fsm_tx[1]_i_2__2\ : label is "soft_lutpair183"; + attribute SOFT_HLUTNM of \FSM_sequential_fsm_tx[2]_i_2__2\ : label is "soft_lutpair183"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[0]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[1]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[2]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of gen3_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true; + attribute KEEP of gen3_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_cnt[1]_i_1__2\ : label is "soft_lutpair186"; + attribute SOFT_HLUTNM of \rxeq_cnt[2]_i_1__2\ : label is "soft_lutpair185"; + attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[5]\ : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_preset[2]_i_3__2\ : label is "soft_lutpair186"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[2]\ : label is "NO"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[0]_i_1__2\ : label is "soft_lutpair187"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[10]_i_1__2\ : label is "soft_lutpair192"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[11]_i_1__2\ : label is "soft_lutpair192"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[1]_i_1__2\ : label is "soft_lutpair187"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[2]_i_1__2\ : label is "soft_lutpair188"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[3]_i_1__2\ : label is "soft_lutpair188"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[4]_i_1__2\ : label is "soft_lutpair189"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[5]_i_1__2\ : label is "soft_lutpair189"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[6]_i_1__2\ : label is "soft_lutpair190"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[7]_i_1__2\ : label is "soft_lutpair190"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[8]_i_1__2\ : label is "soft_lutpair191"; + attribute SOFT_HLUTNM of \rxeq_txcoeff[9]_i_1__2\ : label is "soft_lutpair191"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_en_reg1_reg : label is std.standard.true; + attribute KEEP of rxeq_user_en_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_en_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_en_reg2_reg : label is std.standard.true; + attribute KEEP of rxeq_user_en_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_en_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_mode_reg1_reg : label is std.standard.true; + attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of rxeq_user_mode_reg2_reg : label is std.standard.true; + attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of rxeq_user_mode_reg2_reg : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true; + attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes"; + attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true; + attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[5]\ : label is "NO"; + attribute SOFT_HLUTNM of \txeq_preset_done_i_1__2\ : label is "soft_lutpair184"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[0]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[1]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[2]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[3]\ : label is std.standard.true; + attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes"; + attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[3]\ : label is "NO"; + attribute SOFT_HLUTNM of \txeq_txcoeff_cnt[1]_i_1__2\ : label is "soft_lutpair184"; +begin + USER_RXEQ_ADAPT_DONE <= \^user_rxeq_adapt_done\; +\FSM_onehot_fsm_rx[1]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABABABAA" + ) + port map ( + I0 => \FSM_onehot_fsm_rx[1]_i_2__2_n_0\, + I1 => rxeq_control_reg2(1), + I2 => rxeq_control_reg2(0), + I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + O => \FSM_onehot_fsm_rx[1]_i_1__2_n_0\ + ); +\FSM_onehot_fsm_rx[1]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + O => \FSM_onehot_fsm_rx[1]_i_2__2_n_0\ + ); +\FSM_onehot_fsm_rx[3]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF8FF88888888" + ) + port map ( + I0 => rxeq_control_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \rxeq_cnt_reg_n_0_[2]\, + I3 => \rxeq_cnt_reg_n_0_[1]\, + I4 => \rxeq_cnt_reg_n_0_[0]\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \FSM_onehot_fsm_rx[3]_i_1__2_n_0\ + ); +\FSM_onehot_fsm_rx[4]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"2ABA2AAA" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => \rxeq_cnt_reg_n_0_[2]\, + I2 => \rxeq_cnt_reg_n_0_[1]\, + I3 => \rxeq_cnt_reg_n_0_[0]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \FSM_onehot_fsm_rx[4]_i_1__2_n_0\ + ); +\FSM_onehot_fsm_rx_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx[1]_i_1__2_n_0\, + Q => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + S => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_2, + Q => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx[3]_i_1__2_n_0\, + Q => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx[4]_i_1__2_n_0\, + Q => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_1, + Q => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\FSM_onehot_fsm_rx_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_0, + Q => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +\FSM_sequential_fsm_tx[0]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C04FC043C04FF04F" + ) + port map ( + I0 => \FSM_sequential_fsm_tx[1]_i_2__2_n_0\, + I1 => fsm_tx(0), + I2 => fsm_tx(1), + I3 => fsm_tx(2), + I4 => txeq_control_reg2(1), + I5 => txeq_control_reg2(0), + O => \fsm_tx__0\(0) + ); +\FSM_sequential_fsm_tx[1]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3F703F7C3F7C0F70" + ) + port map ( + I0 => \FSM_sequential_fsm_tx[1]_i_2__2_n_0\, + I1 => fsm_tx(0), + I2 => fsm_tx(1), + I3 => fsm_tx(2), + I4 => txeq_control_reg2(1), + I5 => txeq_control_reg2(0), + O => \fsm_tx__0\(1) + ); +\FSM_sequential_fsm_tx[1]_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + O => \FSM_sequential_fsm_tx[1]_i_2__2_n_0\ + ); +\FSM_sequential_fsm_tx[2]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3A2A2A227F7F7F77" + ) + port map ( + I0 => fsm_tx(2), + I1 => fsm_tx(1), + I2 => fsm_tx(0), + I3 => txeq_control_reg2(1), + I4 => txeq_control_reg2(0), + I5 => \FSM_sequential_fsm_tx[2]_i_2__2_n_0\, + O => \fsm_tx__0\(2) + ); +\FSM_sequential_fsm_tx[2]_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D0FFDFFF" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I2 => fsm_tx(0), + I3 => fsm_tx(1), + I4 => txeq_preset_done, + O => \FSM_sequential_fsm_tx[2]_i_2__2_n_0\ + ); +\FSM_sequential_fsm_tx_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fsm_tx__0\(0), + Q => fsm_tx(0), + S => RST_CPLLRESET + ); +\FSM_sequential_fsm_tx_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fsm_tx__0\(1), + Q => fsm_tx(1), + R => RST_CPLLRESET + ); +\FSM_sequential_fsm_tx_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \fsm_tx__0\(2), + Q => fsm_tx(2), + R => RST_CPLLRESET + ); +gen3_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rate_gen3_3, + Q => gen3_reg1, + R => RST_CPLLRESET + ); +gen3_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => gen3_reg1, + Q => gen3_reg2, + R => RST_CPLLRESET + ); +\gtx_channel.gtxe2_channel_i_i_23__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[17]\, + O => TXPOSTCURSOR(4) + ); +\gtx_channel.gtxe2_channel_i_i_24__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[16]\, + O => TXPOSTCURSOR(3) + ); +\gtx_channel.gtxe2_channel_i_i_25__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[15]\, + O => TXPOSTCURSOR(2) + ); +\gtx_channel.gtxe2_channel_i_i_26__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[14]\, + O => TXPOSTCURSOR(1) + ); +\gtx_channel.gtxe2_channel_i_i_27__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[13]\, + O => TXPOSTCURSOR(0) + ); +\gtx_channel.gtxe2_channel_i_i_28__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[4]\, + O => TXPRECURSOR(4) + ); +\gtx_channel.gtxe2_channel_i_i_29__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[3]\, + O => TXPRECURSOR(3) + ); +\gtx_channel.gtxe2_channel_i_i_30__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[2]\, + O => TXPRECURSOR(2) + ); +\gtx_channel.gtxe2_channel_i_i_31__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[1]\, + O => TXPRECURSOR(1) + ); +\gtx_channel.gtxe2_channel_i_i_32__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[0]\, + I1 => gen3_reg2, + O => TXPRECURSOR(0) + ); +\gtx_channel.gtxe2_channel_i_i_33__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[12]\, + O => TXMAINCURSOR(6) + ); +\gtx_channel.gtxe2_channel_i_i_34__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[11]\, + O => TXMAINCURSOR(5) + ); +\gtx_channel.gtxe2_channel_i_i_35__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[10]\, + O => TXMAINCURSOR(4) + ); +\gtx_channel.gtxe2_channel_i_i_36__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[9]\, + O => TXMAINCURSOR(3) + ); +\gtx_channel.gtxe2_channel_i_i_37__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[8]\, + O => TXMAINCURSOR(2) + ); +\gtx_channel.gtxe2_channel_i_i_38__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[7]\, + O => TXMAINCURSOR(1) + ); +\gtx_channel.gtxe2_channel_i_i_39\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => gen3_reg2, + I1 => \txeq_txcoeff_reg_n_0_[6]\, + O => TXMAINCURSOR(0) + ); +\rxeq_adapt_done_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFFFFFF" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + O => \rxeq_adapt_done_i_2__2_n_0\ + ); +rxeq_adapt_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_5, + Q => \^user_rxeq_adapt_done\, + R => RST_CPLLRESET + ); +\rxeq_adapt_done_reg_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => rxeq_control_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => rxeq_control_reg2(1), + O => \rxeq_adapt_done_reg_i_2__2_n_0\ + ); +rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_scan_i_n_4, + Q => rxeq_adapt_done_reg_reg_n_0, + R => RST_CPLLRESET + ); +\rxeq_cnt[0]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8888FFF8" + ) + port map ( + I0 => rxeq_control_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I4 => \rxeq_cnt_reg_n_0_[0]\, + O => rxeq_cnt(0) + ); +\rxeq_cnt[1]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6660" + ) + port map ( + I0 => \rxeq_cnt_reg_n_0_[0]\, + I1 => \rxeq_cnt_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => rxeq_cnt(1) + ); +\rxeq_cnt[2]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"78787800" + ) + port map ( + I0 => \rxeq_cnt_reg_n_0_[1]\, + I1 => \rxeq_cnt_reg_n_0_[0]\, + I2 => \rxeq_cnt_reg_n_0_[2]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => rxeq_cnt(2) + ); +\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_cnt(0), + Q => \rxeq_cnt_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_cnt(1), + Q => \rxeq_cnt_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_cnt(2), + Q => \rxeq_cnt_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_control_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_control_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_control_reg1(0), + Q => rxeq_control_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_control_reg1(1), + Q => rxeq_control_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_fs[0]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(0), + O => rxeq_fs(0) + ); +\rxeq_fs[1]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(1), + O => rxeq_fs(1) + ); +\rxeq_fs[2]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(2), + O => rxeq_fs(2) + ); +\rxeq_fs[3]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(3), + O => rxeq_fs(3) + ); +\rxeq_fs[4]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(4), + O => rxeq_fs(4) + ); +\rxeq_fs[5]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F8" + ) + port map ( + I0 => rxeq_control_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I2 => \FSM_onehot_fsm_rx[1]_i_2__2_n_0\, + O => \rxeq_fs[5]_i_1__2_n_0\ + ); +\rxeq_fs[5]_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => rxeq_lffs_reg2(5), + O => rxeq_fs(5) + ); +\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__2_n_0\, + D => rxeq_fs(0), + Q => \rxeq_fs_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__2_n_0\, + D => rxeq_fs(1), + Q => \rxeq_fs_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__2_n_0\, + D => rxeq_fs(2), + Q => \rxeq_fs_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__2_n_0\, + D => rxeq_fs(3), + Q => \rxeq_fs_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__2_n_0\, + D => rxeq_fs(4), + Q => \rxeq_fs_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_fs[5]_i_1__2_n_0\, + D => rxeq_fs(5), + Q => \rxeq_fs_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\rxeq_lf[0]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(0), + O => rxeq_lf(0) + ); +\rxeq_lf[1]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(1), + O => rxeq_lf(1) + ); +\rxeq_lf[2]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(2), + O => rxeq_lf(2) + ); +\rxeq_lf[3]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(3), + O => rxeq_lf(3) + ); +\rxeq_lf[4]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(4), + O => rxeq_lf(4) + ); +\rxeq_lf[5]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAAAAAAA" + ) + port map ( + I0 => \FSM_onehot_fsm_rx[1]_i_2__2_n_0\, + I1 => \rxeq_cnt_reg_n_0_[2]\, + I2 => \rxeq_cnt_reg_n_0_[0]\, + I3 => \rxeq_cnt_reg_n_0_[1]\, + I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + O => \rxeq_lf[5]_i_1__2_n_0\ + ); +\rxeq_lf[5]_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I1 => rxeq_lffs_reg2(5), + O => rxeq_lf(5) + ); +\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__2_n_0\, + D => rxeq_lf(0), + Q => \rxeq_lf_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__2_n_0\, + D => rxeq_lf(1), + Q => \rxeq_lf_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__2_n_0\, + D => rxeq_lf(2), + Q => \rxeq_lf_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__2_n_0\, + D => rxeq_lf(3), + Q => \rxeq_lf_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__2_n_0\, + D => rxeq_lf(4), + Q => \rxeq_lf_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_lf[5]_i_1__2_n_0\, + D => rxeq_lf(5), + Q => \rxeq_lf_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(3), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(4), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_lffs_reg1(5), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(0), + Q => rxeq_lffs_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(1), + Q => rxeq_lffs_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(2), + Q => rxeq_lffs_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(3), + Q => rxeq_lffs_reg2(3), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(4), + Q => rxeq_lffs_reg2(4), + R => RST_CPLLRESET + ); +\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_lffs_reg1(5), + Q => rxeq_lffs_reg2(5), + R => RST_CPLLRESET + ); +rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_new_txcoeff_req, + Q => rxeq_new_txcoeff_req_reg_n_0, + R => RST_CPLLRESET + ); +\rxeq_preset[0]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8FFA800" + ) + port map ( + I0 => rxeq_preset_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => \rxeq_preset[2]_i_2__2_n_0\, + I4 => \rxeq_preset_reg_n_0_[0]\, + O => \rxeq_preset[0]_i_1__2_n_0\ + ); +\rxeq_preset[1]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8FFA800" + ) + port map ( + I0 => rxeq_preset_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => \rxeq_preset[2]_i_2__2_n_0\, + I4 => \rxeq_preset_reg_n_0_[1]\, + O => \rxeq_preset[1]_i_1__2_n_0\ + ); +\rxeq_preset[2]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8FFA800" + ) + port map ( + I0 => rxeq_preset_reg2(2), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => \rxeq_preset[2]_i_2__2_n_0\, + I4 => \rxeq_preset_reg_n_0_[2]\, + O => \rxeq_preset[2]_i_1__2_n_0\ + ); +\rxeq_preset[2]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF0002" + ) + port map ( + I0 => \rxeq_preset[2]_i_3__2_n_0\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I3 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + I4 => \rxeq_adapt_done_reg_i_2__2_n_0\, + I5 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + O => \rxeq_preset[2]_i_2__2_n_0\ + ); +\rxeq_preset[2]_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \rxeq_preset[2]_i_3__2_n_0\ + ); +\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_preset_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_preset_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_preset_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_reg1(0), + Q => rxeq_preset_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_reg1(1), + Q => rxeq_preset_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_preset_reg1(2), + Q => rxeq_preset_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxeq_preset[0]_i_1__2_n_0\, + Q => \rxeq_preset_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxeq_preset[1]_i_1__2_n_0\, + Q => \rxeq_preset_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \rxeq_preset[2]_i_1__2_n_0\, + Q => \rxeq_preset_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +rxeq_preset_valid_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + Q => rxeq_preset_valid, + R => RST_CPLLRESET + ); +rxeq_scan_i: entity work.pcie_7x_0_pcie_7x_0_rxeq_scan + port map ( + D(2) => rxeq_scan_i_n_0, + D(1) => rxeq_scan_i_n_1, + D(0) => rxeq_scan_i_n_2, + \FSM_onehot_fsm_rx_reg[5]\(2) => \rxeq_cnt_reg_n_0_[2]\, + \FSM_onehot_fsm_rx_reg[5]\(1) => \rxeq_cnt_reg_n_0_[1]\, + \FSM_onehot_fsm_rx_reg[5]\(0) => \rxeq_cnt_reg_n_0_[0]\, + Q(4) => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + Q(3) => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + Q(2) => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + Q(1) => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + Q(0) => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + RST_CPLLRESET => RST_CPLLRESET, + USER_RXEQ_ADAPT_DONE => \^user_rxeq_adapt_done\, + adapt_done_reg_0 => rxeq_scan_i_n_4, + \fs_reg1_reg[5]_0\(5) => \rxeq_fs_reg_n_0_[5]\, + \fs_reg1_reg[5]_0\(4) => \rxeq_fs_reg_n_0_[4]\, + \fs_reg1_reg[5]_0\(3) => \rxeq_fs_reg_n_0_[3]\, + \fs_reg1_reg[5]_0\(2) => \rxeq_fs_reg_n_0_[2]\, + \fs_reg1_reg[5]_0\(1) => \rxeq_fs_reg_n_0_[1]\, + \fs_reg1_reg[5]_0\(0) => \rxeq_fs_reg_n_0_[0]\, + \lf_reg1_reg[5]_0\(5) => \rxeq_lf_reg_n_0_[5]\, + \lf_reg1_reg[5]_0\(4) => \rxeq_lf_reg_n_0_[4]\, + \lf_reg1_reg[5]_0\(3) => \rxeq_lf_reg_n_0_[3]\, + \lf_reg1_reg[5]_0\(2) => \rxeq_lf_reg_n_0_[2]\, + \lf_reg1_reg[5]_0\(1) => \rxeq_lf_reg_n_0_[1]\, + \lf_reg1_reg[5]_0\(0) => \rxeq_lf_reg_n_0_[0]\, + new_txcoeff_done_reg_0 => rxeq_scan_i_n_5, + new_txcoeff_req_reg1_reg_0 => rxeq_new_txcoeff_req_reg_n_0, + \out\(1 downto 0) => rxeq_control_reg2(1 downto 0), + pipe_pclk_in => pipe_pclk_in, + \preset_reg1_reg[2]_0\(2) => \rxeq_preset_reg_n_0_[2]\, + \preset_reg1_reg[2]_0\(1) => \rxeq_preset_reg_n_0_[1]\, + \preset_reg1_reg[2]_0\(0) => \rxeq_preset_reg_n_0_[0]\, + rxeq_adapt_done_reg => \rxeq_adapt_done_i_2__2_n_0\, + rxeq_adapt_done_reg_reg => \FSM_onehot_fsm_rx[1]_i_2__2_n_0\, + rxeq_adapt_done_reg_reg_0 => \rxeq_adapt_done_reg_i_2__2_n_0\, + rxeq_adapt_done_reg_reg_1 => rxeq_adapt_done_reg_reg_n_0, + rxeq_new_txcoeff_req => rxeq_new_txcoeff_req, + rxeq_preset_valid => rxeq_preset_valid, + \txcoeff_reg1_reg[17]_0\(17) => \rxeq_txcoeff_reg_n_0_[17]\, + \txcoeff_reg1_reg[17]_0\(16) => \rxeq_txcoeff_reg_n_0_[16]\, + \txcoeff_reg1_reg[17]_0\(15) => \rxeq_txcoeff_reg_n_0_[15]\, + \txcoeff_reg1_reg[17]_0\(14) => \rxeq_txcoeff_reg_n_0_[14]\, + \txcoeff_reg1_reg[17]_0\(13) => \rxeq_txcoeff_reg_n_0_[13]\, + \txcoeff_reg1_reg[17]_0\(12) => \rxeq_txcoeff_reg_n_0_[12]\, + \txcoeff_reg1_reg[17]_0\(11) => \rxeq_txcoeff_reg_n_0_[11]\, + \txcoeff_reg1_reg[17]_0\(10) => \rxeq_txcoeff_reg_n_0_[10]\, + \txcoeff_reg1_reg[17]_0\(9) => \rxeq_txcoeff_reg_n_0_[9]\, + \txcoeff_reg1_reg[17]_0\(8) => \rxeq_txcoeff_reg_n_0_[8]\, + \txcoeff_reg1_reg[17]_0\(7) => \rxeq_txcoeff_reg_n_0_[7]\, + \txcoeff_reg1_reg[17]_0\(6) => \rxeq_txcoeff_reg_n_0_[6]\, + \txcoeff_reg1_reg[17]_0\(5) => \rxeq_txcoeff_reg_n_0_[5]\, + \txcoeff_reg1_reg[17]_0\(4) => \rxeq_txcoeff_reg_n_0_[4]\, + \txcoeff_reg1_reg[17]_0\(3) => \rxeq_txcoeff_reg_n_0_[3]\, + \txcoeff_reg1_reg[17]_0\(2) => \rxeq_txcoeff_reg_n_0_[2]\, + \txcoeff_reg1_reg[17]_0\(1) => \rxeq_txcoeff_reg_n_0_[1]\, + \txcoeff_reg1_reg[17]_0\(0) => \rxeq_txcoeff_reg_n_0_[0]\, + \txpreset_reg1_reg[3]_0\(3) => \rxeq_txpreset_reg_n_0_[3]\, + \txpreset_reg1_reg[3]_0\(2) => \rxeq_txpreset_reg_n_0_[2]\, + \txpreset_reg1_reg[3]_0\(1) => \rxeq_txpreset_reg_n_0_[1]\, + \txpreset_reg1_reg[3]_0\(0) => \rxeq_txpreset_reg_n_0_[0]\ + ); +\rxeq_txcoeff[0]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[6]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(0) + ); +\rxeq_txcoeff[10]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[16]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(10) + ); +\rxeq_txcoeff[11]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[17]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(11) + ); +\rxeq_txcoeff[12]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(12) + ); +\rxeq_txcoeff[13]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(13) + ); +\rxeq_txcoeff[14]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(2), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(14) + ); +\rxeq_txcoeff[15]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(3), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(15) + ); +\rxeq_txcoeff[16]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(4), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(16) + ); +\rxeq_txcoeff[17]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => txeq_deemph_reg2(5), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(17) + ); +\rxeq_txcoeff[1]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[7]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(1) + ); +\rxeq_txcoeff[2]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[8]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(2) + ); +\rxeq_txcoeff[3]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[9]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(3) + ); +\rxeq_txcoeff[4]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[10]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(4) + ); +\rxeq_txcoeff[5]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[11]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(5) + ); +\rxeq_txcoeff[6]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[12]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(6) + ); +\rxeq_txcoeff[7]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[13]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(7) + ); +\rxeq_txcoeff[8]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[14]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(8) + ); +\rxeq_txcoeff[9]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \rxeq_txcoeff_reg_n_0_[15]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txcoeff(9) + ); +\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(0), + Q => \rxeq_txcoeff_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(10), + Q => \rxeq_txcoeff_reg_n_0_[10]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(11), + Q => \rxeq_txcoeff_reg_n_0_[11]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(12), + Q => \rxeq_txcoeff_reg_n_0_[12]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(13), + Q => \rxeq_txcoeff_reg_n_0_[13]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(14), + Q => \rxeq_txcoeff_reg_n_0_[14]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(15), + Q => \rxeq_txcoeff_reg_n_0_[15]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(16), + Q => \rxeq_txcoeff_reg_n_0_[16]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(17), + Q => \rxeq_txcoeff_reg_n_0_[17]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(1), + Q => \rxeq_txcoeff_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(2), + Q => \rxeq_txcoeff_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(3), + Q => \rxeq_txcoeff_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(4), + Q => \rxeq_txcoeff_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(5), + Q => \rxeq_txcoeff_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(6), + Q => \rxeq_txcoeff_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(7), + Q => \rxeq_txcoeff_reg_n_0_[7]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(8), + Q => \rxeq_txcoeff_reg_n_0_[8]\, + R => RST_CPLLRESET + ); +\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txcoeff(9), + Q => \rxeq_txcoeff_reg_n_0_[9]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset[0]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(0), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(0) + ); +\rxeq_txpreset[1]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(1), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(1) + ); +\rxeq_txpreset[2]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(2), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(2) + ); +\rxeq_txpreset[3]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFF404" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[6]\, + I1 => \rxeq_txpreset[3]_i_3__2_n_0\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + I3 => rxeq_control_reg2(1), + I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + O => \rxeq_txpreset[3]_i_1__2_n_0\ + ); +\rxeq_txpreset[3]_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => rxeq_txpreset_reg2(3), + I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\, + O => rxeq_txpreset(3) + ); +\rxeq_txpreset[3]_i_3__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\, + I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\, + I2 => \FSM_onehot_fsm_rx_reg_n_0_[5]\, + O => \rxeq_txpreset[3]_i_3__2_n_0\ + ); +\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_txpreset_reg1(3), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(0), + Q => rxeq_txpreset_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(1), + Q => rxeq_txpreset_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(2), + Q => rxeq_txpreset_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_txpreset_reg1(3), + Q => rxeq_txpreset_reg2(3), + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txpreset(0), + Q => \rxeq_txpreset_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txpreset(1), + Q => \rxeq_txpreset_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txpreset(2), + Q => \rxeq_txpreset_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \rxeq_txpreset[3]_i_1__2_n_0\, + D => rxeq_txpreset(3), + Q => \rxeq_txpreset_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_en_reg1, + R => RST_CPLLRESET + ); +rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_en_reg1, + Q => rxeq_user_en_reg2, + R => RST_CPLLRESET + ); +rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_mode_reg1, + R => RST_CPLLRESET + ); +rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_mode_reg1, + Q => rxeq_user_mode_reg2, + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(0), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(10), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(11), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(12), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(13), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(14), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(15), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(16), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(17), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(1), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(2), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(3), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(4), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(5), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(6), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(7), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(8), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => rxeq_user_txcoeff_reg1(9), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(0), + Q => rxeq_user_txcoeff_reg2(0), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(10), + Q => rxeq_user_txcoeff_reg2(10), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(11), + Q => rxeq_user_txcoeff_reg2(11), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(12), + Q => rxeq_user_txcoeff_reg2(12), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(13), + Q => rxeq_user_txcoeff_reg2(13), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(14), + Q => rxeq_user_txcoeff_reg2(14), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(15), + Q => rxeq_user_txcoeff_reg2(15), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(16), + Q => rxeq_user_txcoeff_reg2(16), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(17), + Q => rxeq_user_txcoeff_reg2(17), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(1), + Q => rxeq_user_txcoeff_reg2(1), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(2), + Q => rxeq_user_txcoeff_reg2(2), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(3), + Q => rxeq_user_txcoeff_reg2(3), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(4), + Q => rxeq_user_txcoeff_reg2(4), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(5), + Q => rxeq_user_txcoeff_reg2(5), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(6), + Q => rxeq_user_txcoeff_reg2(6), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(7), + Q => rxeq_user_txcoeff_reg2(7), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(8), + Q => rxeq_user_txcoeff_reg2(8), + R => RST_CPLLRESET + ); +\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => rxeq_user_txcoeff_reg1(9), + Q => rxeq_user_txcoeff_reg2(9), + R => RST_CPLLRESET + ); +\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_control_reg1(0), + R => RST_CPLLRESET + ); +\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_control_reg1(1), + R => RST_CPLLRESET + ); +\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_control_reg1(0), + Q => txeq_control_reg2(0), + R => RST_CPLLRESET + ); +\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_control_reg1(1), + Q => txeq_control_reg2(1), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(0), + S => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(1), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(2), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(3), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(4), + R => RST_CPLLRESET + ); +\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_deemph_reg1(5), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(0), + Q => txeq_deemph_reg2(0), + S => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(1), + Q => txeq_deemph_reg2(1), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(2), + Q => txeq_deemph_reg2(2), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(3), + Q => txeq_deemph_reg2(3), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(4), + Q => txeq_deemph_reg2(4), + R => RST_CPLLRESET + ); +\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_deemph_reg1(5), + Q => txeq_deemph_reg2(5), + R => RST_CPLLRESET + ); +\txeq_preset[0]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001000" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(2), + I2 => txeq_preset_reg2(0), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(1), + O => p_0_out(0) + ); +\txeq_preset[10]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABEAABAF" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(2), + I2 => txeq_preset_reg2(0), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(1), + O => p_0_out(10) + ); +\txeq_preset[11]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF200D" + ) + port map ( + I0 => txeq_preset_reg2(1), + I1 => txeq_preset_reg2(3), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(0), + I4 => RST_CPLLRESET, + O => p_0_out(11) + ); +\txeq_preset[12]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01151110" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(3), + I2 => txeq_preset_reg2(1), + I3 => txeq_preset_reg2(2), + I4 => txeq_preset_reg2(0), + O => p_0_out(12) + ); +\txeq_preset[13]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01000010" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => RST_CPLLRESET, + I2 => txeq_preset_reg2(0), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(1), + O => p_0_out(13) + ); +\txeq_preset[14]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01000010" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => RST_CPLLRESET, + I2 => txeq_preset_reg2(3), + I3 => txeq_preset_reg2(1), + I4 => txeq_preset_reg2(0), + O => p_0_out(14) + ); +\txeq_preset[15]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F0F1" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => txeq_preset_reg2(1), + I2 => RST_CPLLRESET, + I3 => txeq_preset_reg2(3), + O => p_0_out(15) + ); +\txeq_preset[16]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0006" + ) + port map ( + I0 => txeq_preset_reg2(3), + I1 => txeq_preset_reg2(0), + I2 => txeq_preset_reg2(2), + I3 => RST_CPLLRESET, + O => p_0_out(16) + ); +\txeq_preset[17]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AABA" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => fsm_tx(0), + I2 => fsm_tx(1), + I3 => fsm_tx(2), + O => \txeq_preset[17]_i_1__2_n_0\ + ); +\txeq_preset[17]_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF400D" + ) + port map ( + I0 => txeq_preset_reg2(3), + I1 => txeq_preset_reg2(1), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(0), + I4 => RST_CPLLRESET, + O => p_0_out(17) + ); +\txeq_preset[1]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001004" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(3), + I2 => txeq_preset_reg2(1), + I3 => txeq_preset_reg2(2), + I4 => txeq_preset_reg2(0), + O => p_0_out(1) + ); +\txeq_preset[2]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0E00" + ) + port map ( + I0 => txeq_preset_reg2(2), + I1 => txeq_preset_reg2(0), + I2 => RST_CPLLRESET, + I3 => txeq_preset_reg2(3), + O => p_0_out(2) + ); +\txeq_preset[3]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01440140" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(2), + I2 => txeq_preset_reg2(1), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(0), + O => \txeq_preset[3]_i_1__2_n_0\ + ); +\txeq_preset[7]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001400" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(0), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(1), + I4 => txeq_preset_reg2(3), + O => \txeq_preset[7]_i_1__2_n_0\ + ); +\txeq_preset[8]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAFBEAF" + ) + port map ( + I0 => RST_CPLLRESET, + I1 => txeq_preset_reg2(0), + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(1), + I4 => txeq_preset_reg2(3), + O => p_0_out(8) + ); +\txeq_preset[9]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCFCCFCD" + ) + port map ( + I0 => txeq_preset_reg2(1), + I1 => RST_CPLLRESET, + I2 => txeq_preset_reg2(2), + I3 => txeq_preset_reg2(3), + I4 => txeq_preset_reg2(0), + O => p_0_out(9) + ); +\txeq_preset_done_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => fsm_tx(2), + I1 => fsm_tx(1), + I2 => fsm_tx(0), + O => \txeq_preset_done_i_1__2_n_0\ + ); +txeq_preset_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \txeq_preset_done_i_1__2_n_0\, + Q => txeq_preset_done, + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(0), + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(1), + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(2), + R => RST_CPLLRESET + ); +\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => '0', + Q => txeq_preset_reg1(3), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(0), + Q => txeq_preset_reg2(0), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(1), + Q => txeq_preset_reg2(1), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(2), + Q => txeq_preset_reg2(2), + R => RST_CPLLRESET + ); +\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_preset_reg1(3), + Q => txeq_preset_reg2(3), + R => RST_CPLLRESET + ); +\txeq_preset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => p_0_out(0), + Q => \txeq_preset_reg_n_0_[0]\, + R => '0' + ); +\txeq_preset_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => p_0_out(10), + Q => \txeq_preset_reg_n_0_[10]\, + R => '0' + ); +\txeq_preset_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => p_0_out(11), + Q => \txeq_preset_reg_n_0_[11]\, + R => '0' + ); +\txeq_preset_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => p_0_out(12), + Q => \txeq_preset_reg_n_0_[12]\, + R => '0' + ); +\txeq_preset_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => p_0_out(13), + Q => \txeq_preset_reg_n_0_[13]\, + R => '0' + ); +\txeq_preset_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => p_0_out(14), + Q => \txeq_preset_reg_n_0_[14]\, + R => '0' + ); +\txeq_preset_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => p_0_out(15), + Q => \txeq_preset_reg_n_0_[15]\, + R => '0' + ); +\txeq_preset_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => p_0_out(16), + Q => \txeq_preset_reg_n_0_[16]\, + R => '0' + ); +\txeq_preset_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => p_0_out(17), + Q => \txeq_preset_reg_n_0_[17]\, + R => '0' + ); +\txeq_preset_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => p_0_out(1), + Q => \txeq_preset_reg_n_0_[1]\, + R => '0' + ); +\txeq_preset_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => p_0_out(2), + Q => \txeq_preset_reg_n_0_[2]\, + R => '0' + ); +\txeq_preset_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => \txeq_preset[3]_i_1__2_n_0\, + Q => \txeq_preset_reg_n_0_[3]\, + R => '0' + ); +\txeq_preset_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => \txeq_preset[7]_i_1__2_n_0\, + Q => \txeq_preset_reg_n_0_[7]\, + R => '0' + ); +\txeq_preset_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => p_0_out(8), + Q => \txeq_preset_reg_n_0_[8]\, + R => '0' + ); +\txeq_preset_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => \txeq_preset[17]_i_1__2_n_0\, + D => p_0_out(9), + Q => \txeq_preset_reg_n_0_[9]\, + R => '0' + ); +\txeq_txcoeff[0]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"45404040" + ) + port map ( + I0 => fsm_tx(2), + I1 => \txeq_txcoeff[0]_i_2__2_n_0\, + I2 => fsm_tx(1), + I3 => fsm_tx(0), + I4 => \txeq_txcoeff_reg_n_0_[6]\, + O => \txeq_txcoeff[0]_i_1__2_n_0\ + ); +\txeq_txcoeff[0]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[6]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[7]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[0]\, + O => \txeq_txcoeff[0]_i_2__2_n_0\ + ); +\txeq_txcoeff[10]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[9]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[10]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[16]\, + O => \txeq_txcoeff[10]_i_1__2_n_0\ + ); +\txeq_txcoeff[10]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[16]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[17]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[10]\, + O => \txeq_txcoeff[10]_i_2__2_n_0\ + ); +\txeq_txcoeff[11]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[10]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[11]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[17]\, + O => \txeq_txcoeff[11]_i_1__2_n_0\ + ); +\txeq_txcoeff[11]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[17]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[18]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[11]\, + O => \txeq_txcoeff[11]_i_2__2_n_0\ + ); +\txeq_txcoeff[12]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[11]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[12]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[18]\, + O => \txeq_txcoeff[12]_i_1__2_n_0\ + ); +\txeq_txcoeff[12]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[18]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(0), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[12]\, + O => \txeq_txcoeff[12]_i_2__2_n_0\ + ); +\txeq_txcoeff[13]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[12]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[13]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(0), + O => \txeq_txcoeff[13]_i_1__2_n_0\ + ); +\txeq_txcoeff[13]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(0), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(1), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[13]\, + O => \txeq_txcoeff[13]_i_2__2_n_0\ + ); +\txeq_txcoeff[14]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[13]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[14]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(1), + O => \txeq_txcoeff[14]_i_1__2_n_0\ + ); +\txeq_txcoeff[14]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(1), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(2), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[14]\, + O => \txeq_txcoeff[14]_i_2__2_n_0\ + ); +\txeq_txcoeff[15]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[14]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[15]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(2), + O => \txeq_txcoeff[15]_i_1__2_n_0\ + ); +\txeq_txcoeff[15]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(2), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(3), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[15]\, + O => \txeq_txcoeff[15]_i_2__2_n_0\ + ); +\txeq_txcoeff[16]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[15]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[16]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(3), + O => \txeq_txcoeff[16]_i_1__2_n_0\ + ); +\txeq_txcoeff[16]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(3), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(4), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[16]\, + O => \txeq_txcoeff[16]_i_2__2_n_0\ + ); +\txeq_txcoeff[17]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[16]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[17]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => txeq_deemph_reg2(4), + O => \txeq_txcoeff[17]_i_1__2_n_0\ + ); +\txeq_txcoeff[17]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => txeq_deemph_reg2(4), + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => txeq_deemph_reg2(5), + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[17]\, + O => \txeq_txcoeff[17]_i_2__2_n_0\ + ); +\txeq_txcoeff[18]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF040FFF" + ) + port map ( + I0 => txeq_control_reg2(0), + I1 => txeq_control_reg2(1), + I2 => fsm_tx(2), + I3 => fsm_tx(1), + I4 => fsm_tx(0), + O => txeq_txcoeff + ); +\txeq_txcoeff[18]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F3220022002200" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[17]\, + I1 => fsm_tx(1), + I2 => \txeq_txcoeff[18]_i_3__2_n_0\, + I3 => fsm_tx(2), + I4 => txeq_deemph_reg2(5), + I5 => fsm_tx(0), + O => \txeq_txcoeff[18]_i_2__2_n_0\ + ); +\txeq_txcoeff[18]_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + O => \txeq_txcoeff[18]_i_3__2_n_0\ + ); +\txeq_txcoeff[1]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[0]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[1]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[7]\, + O => \txeq_txcoeff[1]_i_1__2_n_0\ + ); +\txeq_txcoeff[1]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[7]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[8]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[1]\, + O => \txeq_txcoeff[1]_i_2__2_n_0\ + ); +\txeq_txcoeff[2]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[1]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[2]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[8]\, + O => \txeq_txcoeff[2]_i_1__2_n_0\ + ); +\txeq_txcoeff[2]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[8]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[9]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[2]\, + O => \txeq_txcoeff[2]_i_2__2_n_0\ + ); +\txeq_txcoeff[3]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[2]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[3]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[9]\, + O => \txeq_txcoeff[3]_i_1__2_n_0\ + ); +\txeq_txcoeff[3]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[9]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[10]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[3]\, + O => \txeq_txcoeff[3]_i_2__2_n_0\ + ); +\txeq_txcoeff[4]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[3]\, + I1 => fsm_tx(1), + I2 => fsm_tx(2), + I3 => \txeq_txcoeff[4]_i_2__2_n_0\, + O => \txeq_txcoeff[4]_i_1__2_n_0\ + ); +\txeq_txcoeff[4]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACCCCCC00000000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[11]\, + I1 => \txeq_txcoeff_reg_n_0_[10]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I4 => fsm_tx(1), + I5 => fsm_tx(0), + O => \txeq_txcoeff[4]_i_2__2_n_0\ + ); +\txeq_txcoeff[5]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[4]\, + I1 => fsm_tx(1), + I2 => fsm_tx(2), + I3 => \txeq_txcoeff[5]_i_2__2_n_0\, + O => \txeq_txcoeff[5]_i_1__2_n_0\ + ); +\txeq_txcoeff[5]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACCCCCC00000000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[12]\, + I1 => \txeq_txcoeff_reg_n_0_[11]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I4 => fsm_tx(1), + I5 => fsm_tx(0), + O => \txeq_txcoeff[5]_i_2__2_n_0\ + ); +\txeq_txcoeff[6]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[5]\, + I1 => fsm_tx(1), + I2 => fsm_tx(2), + I3 => \txeq_txcoeff[6]_i_2__2_n_0\, + O => \txeq_txcoeff[6]_i_1__2_n_0\ + ); +\txeq_txcoeff[6]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CACCCCCC00000000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[13]\, + I1 => \txeq_txcoeff_reg_n_0_[12]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I4 => fsm_tx(1), + I5 => fsm_tx(0), + O => \txeq_txcoeff[6]_i_2__2_n_0\ + ); +\txeq_txcoeff[7]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[6]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[7]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[13]\, + O => \txeq_txcoeff[7]_i_1__2_n_0\ + ); +\txeq_txcoeff[7]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[13]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[14]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[7]\, + O => \txeq_txcoeff[7]_i_2__2_n_0\ + ); +\txeq_txcoeff[8]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[7]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[8]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[14]\, + O => \txeq_txcoeff[8]_i_1__2_n_0\ + ); +\txeq_txcoeff[8]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[14]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[15]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[8]\, + O => \txeq_txcoeff[8]_i_2__2_n_0\ + ); +\txeq_txcoeff[9]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30BB308830883088" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[8]\, + I1 => fsm_tx(2), + I2 => \txeq_txcoeff[9]_i_2__2_n_0\, + I3 => fsm_tx(1), + I4 => fsm_tx(0), + I5 => \txeq_txcoeff_reg_n_0_[15]\, + O => \txeq_txcoeff[9]_i_1__2_n_0\ + ); +\txeq_txcoeff[9]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA8AFFFFBA8A0000" + ) + port map ( + I0 => \txeq_txcoeff_reg_n_0_[15]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I3 => \txeq_txcoeff_reg_n_0_[16]\, + I4 => fsm_tx(0), + I5 => \txeq_preset_reg_n_0_[9]\, + O => \txeq_txcoeff[9]_i_2__2_n_0\ + ); +\txeq_txcoeff_cnt[0]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000004000F000400" + ) + port map ( + I0 => txeq_control_reg2(0), + I1 => txeq_control_reg2(1), + I2 => fsm_tx(2), + I3 => fsm_tx(0), + I4 => fsm_tx(1), + I5 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + O => txeq_txcoeff_cnt(0) + ); +\txeq_txcoeff_cnt[1]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00006000" + ) + port map ( + I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\, + I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\, + I2 => fsm_tx(0), + I3 => fsm_tx(1), + I4 => fsm_tx(2), + O => txeq_txcoeff_cnt(1) + ); +\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_txcoeff_cnt(0), + Q => \txeq_txcoeff_cnt_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => txeq_txcoeff_cnt(1), + Q => \txeq_txcoeff_cnt_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[0]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[0]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[10]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[10]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[11]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[11]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[12]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[12]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[13]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[13]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[14]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[14]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[15]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[15]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[16]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[16]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[17]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[17]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[18]_i_2__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[18]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[1]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[1]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[2]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[2]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[3]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[3]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[4]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[4]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[5]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[5]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[6]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[6]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[7]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[7]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[8]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[8]\, + R => RST_CPLLRESET + ); +\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => txeq_txcoeff, + D => \txeq_txcoeff[9]_i_1__2_n_0\, + Q => \txeq_txcoeff_reg_n_0_[9]\, + R => RST_CPLLRESET + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_axi_basic_top is + port ( + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + trn_rsrc_dsc_d : out STD_LOGIC; + m_axis_rx_tvalid_reg : out STD_LOGIC; + m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_rx_tlast : out STD_LOGIC; + reg_tcfg_gnt : out STD_LOGIC; + tready_thrtl_reg : out STD_LOGIC; + trn_teof : out STD_LOGIC; + trn_tsrc_rdy : out STD_LOGIC; + trn_trem : out STD_LOGIC_VECTOR ( 0 to 0 ); + trn_in_packet : out STD_LOGIC; + reg_dsc_detect : out STD_LOGIC; + ppm_L1_thrtl : out STD_LOGIC; + lnk_up_thrtl : out STD_LOGIC; + m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 ); + ppm_L1_trig : out STD_LOGIC; + cfg_pm_turnoff_ok_n : out STD_LOGIC; + trn_tcfg_gnt : out STD_LOGIC; + trn_tsof : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 63 downto 0 ); + \throttle_ctl_pipeline.reg_tdata_reg[63]\ : out STD_LOGIC_VECTOR ( 63 downto 0 ); + \throttle_ctl_pipeline.reg_tuser_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \throttle_ctl_pipeline.reg_tkeep_reg[7]\ : in STD_LOGIC; + pipe_userclk2_in : in STD_LOGIC; + trn_rrem : in STD_LOGIC_VECTOR ( 0 to 0 ); + trn_rsrc_dsc : in STD_LOGIC; + rsrc_rdy_filtered : in STD_LOGIC; + trn_reof : in STD_LOGIC; + trn_rsrc_dsc_prev0 : in STD_LOGIC; + trn_rsof : in STD_LOGIC; + trn_recrc_err : in STD_LOGIC; + trn_rerrfwd : in STD_LOGIC; + tx_cfg_gnt : in STD_LOGIC; + trn_tcfg_req : in STD_LOGIC; + trn_tdst_rdy : in STD_LOGIC; + tbuf_av_min_trig : in STD_LOGIC; + cfg_turnoff_ok : in STD_LOGIC; + s_axis_tx_tlast : in STD_LOGIC; + s_axis_tx_tvalid : in STD_LOGIC; + s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); + trn_in_packet_reg : in STD_LOGIC; + ppm_L1_thrtl_reg : in STD_LOGIC; + lnk_up_thrtl_reg : in STD_LOGIC; + m_axis_rx_tready : in STD_LOGIC; + dsc_detect : in STD_LOGIC; + \out\ : in STD_LOGIC; + tcfg_req_trig : in STD_LOGIC; + tready_thrtl_i_5 : in STD_LOGIC; + cfg_pcie_link_state : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ); + trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 ); + trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 ); + trn_rbar_hit : in STD_LOGIC_VECTOR ( 6 downto 0 ); + cfg_to_turnoff : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_axi_basic_top; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_axi_basic_top is +begin +rx_inst: entity work.pcie_7x_0_pcie_7x_0_axi_basic_rx + port map ( + E(0) => E(0), + Q(63 downto 0) => Q(63 downto 0), + dsc_detect => dsc_detect, + m_axis_rx_tkeep(0) => m_axis_rx_tkeep(0), + m_axis_rx_tlast => m_axis_rx_tlast, + m_axis_rx_tready => m_axis_rx_tready, + m_axis_rx_tuser(12 downto 0) => m_axis_rx_tuser(12 downto 0), + m_axis_rx_tvalid_reg => m_axis_rx_tvalid_reg, + pipe_userclk2_in => pipe_userclk2_in, + reg_dsc_detect_reg => reg_dsc_detect, + rsrc_rdy_filtered => rsrc_rdy_filtered, + trn_in_packet => trn_in_packet, + trn_in_packet_reg => trn_in_packet_reg, + trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0), + \trn_rbar_hit_prev_reg[0]\ => \throttle_ctl_pipeline.reg_tkeep_reg[7]\, + trn_rd(63 downto 0) => trn_rd(63 downto 0), + trn_recrc_err => trn_recrc_err, + trn_reof => trn_reof, + trn_rerrfwd => trn_rerrfwd, + trn_rrem(0) => trn_rrem(0), + trn_rsof => trn_rsof, + trn_rsrc_dsc => trn_rsrc_dsc, + trn_rsrc_dsc_d => trn_rsrc_dsc_d, + trn_rsrc_dsc_prev0 => trn_rsrc_dsc_prev0 + ); +tx_inst: entity work.pcie_7x_0_pcie_7x_0_axi_basic_tx + port map ( + cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0), + cfg_pm_turnoff_ok_n => cfg_pm_turnoff_ok_n, + cfg_to_turnoff => cfg_to_turnoff, + cfg_turnoff_ok => cfg_turnoff_ok, + lnk_up_thrtl => lnk_up_thrtl, + lnk_up_thrtl_reg => lnk_up_thrtl_reg, + \out\ => \out\, + pipe_userclk2_in => pipe_userclk2_in, + ppm_L1_thrtl => ppm_L1_thrtl, + ppm_L1_thrtl_reg => ppm_L1_thrtl_reg, + ppm_L1_trig => ppm_L1_trig, + reg_tcfg_gnt => reg_tcfg_gnt, + s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0), + s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0), + s_axis_tx_tlast => s_axis_tx_tlast, + s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0), + s_axis_tx_tvalid => s_axis_tx_tvalid, + tbuf_av_min_trig => tbuf_av_min_trig, + tcfg_req_trig => tcfg_req_trig, + \throttle_ctl_pipeline.reg_tdata_reg[63]\(63 downto 0) => \throttle_ctl_pipeline.reg_tdata_reg[63]\(63 downto 0), + \throttle_ctl_pipeline.reg_tkeep_reg[7]\ => \throttle_ctl_pipeline.reg_tkeep_reg[7]\, + \throttle_ctl_pipeline.reg_tuser_reg[3]\(3 downto 0) => \throttle_ctl_pipeline.reg_tuser_reg[3]\(3 downto 0), + tready_thrtl_i_5 => tready_thrtl_i_5, + tready_thrtl_reg => tready_thrtl_reg, + trn_tbuf_av(5 downto 0) => trn_tbuf_av(5 downto 0), + trn_tcfg_gnt => trn_tcfg_gnt, + trn_tcfg_req => trn_tcfg_req, + trn_tdst_rdy => trn_tdst_rdy, + trn_teof => trn_teof, + trn_trem(0) => trn_trem(0), + trn_tsof => trn_tsof, + trn_tsrc_rdy => trn_tsrc_rdy, + tx_cfg_gnt => tx_cfg_gnt + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_brams_7x is + port ( + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 67 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 67 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_pcie_brams_7x; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_brams_7x is +begin +\brams[0].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_18 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +\brams[1].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_19 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(17 downto 9), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17 downto 9), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +\brams[2].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_20 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(26 downto 18), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(26 downto 18), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +\brams[3].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_21 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(35 downto 27), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(35 downto 27), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +\brams[4].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_22 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(44 downto 36), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(44 downto 36), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +\brams[5].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_23 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(53 downto 45), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(53 downto 45), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +\brams[6].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_24 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(62 downto 54), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(62 downto 54), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +\brams[7].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_25 + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(4 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(67 downto 63), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(4 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(67 downto 63), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_brams_7x_3 is + port ( + rdata : out STD_LOGIC_VECTOR ( 68 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 68 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of pcie_7x_0_pcie_7x_0_pcie_brams_7x_3 : entity is "pcie_7x_0_pcie_brams_7x"; +end pcie_7x_0_pcie_7x_0_pcie_brams_7x_3; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_brams_7x_3 is +begin +\brams[0].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(8 downto 0), + wdata(8 downto 0) => wdata(8 downto 0) + ); +\brams[1].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_4 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(17 downto 9), + wdata(8 downto 0) => wdata(17 downto 9) + ); +\brams[2].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_5 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(26 downto 18), + wdata(8 downto 0) => wdata(26 downto 18) + ); +\brams[3].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_6 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(35 downto 27), + wdata(8 downto 0) => wdata(35 downto 27) + ); +\brams[4].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_7 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(44 downto 36), + wdata(8 downto 0) => wdata(44 downto 36) + ); +\brams[5].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_8 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(53 downto 45), + wdata(8 downto 0) => wdata(53 downto 45) + ); +\brams[6].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_9 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(8 downto 0) => rdata(62 downto 54), + wdata(8 downto 0) => wdata(62 downto 54) + ); +\brams[7].ram\: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_7x_10 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(5 downto 0) => rdata(68 downto 63), + wdata(5 downto 0) => wdata(68 downto 63) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pipe_wrapper is + port ( + cpllpd : out STD_LOGIC; + cpllpd_0 : out STD_LOGIC; + cpllpd_1 : out STD_LOGIC; + cpllpd_2 : out STD_LOGIC; + pci_exp_txn : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_txp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 3 downto 0 ); + gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_txoutclk_out : out STD_LOGIC; + PIPE_RXSTATUS : out STD_LOGIC_VECTOR ( 2 downto 0 ); + gt_rx_data_wire_filter : out STD_LOGIC_VECTOR ( 63 downto 0 ); + gt_rx_data_k_wire_filter : out STD_LOGIC_VECTOR ( 7 downto 0 ); + pipe_dclk_in_0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pipe_dclk_in_1 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pipe_dclk_in_2 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + reg_clock_locked_reg : out STD_LOGIC; + gt_rxvalid_q_reg : out STD_LOGIC; + gt_rxvalid_q_reg_0 : out STD_LOGIC; + gt_rxvalid_q_reg_1 : out STD_LOGIC; + gt_rxvalid_q_reg_2 : out STD_LOGIC; + gen3_reg : out STD_LOGIC; + pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); + rate_cpllpd_0 : out STD_LOGIC; + rate_cpllpd_1 : out STD_LOGIC; + rate_cpllpd_2 : out STD_LOGIC; + rate_cpllpd_3 : out STD_LOGIC; + gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CPLLPD0 : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + sys_clk : in STD_LOGIC; + pci_exp_rxn : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_rxp : in STD_LOGIC_VECTOR ( 3 downto 0 ); + PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_rxusrclk_in : in STD_LOGIC; + pipe_tx_deemph_gt : in STD_LOGIC; + pipe_tx_rcvr_det_gt : in STD_LOGIC; + PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_pclk_in : in STD_LOGIC; + PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \cplllock_reg1_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + PIPE_TXDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 7 downto 0 ); + CPLLPD0_3 : in STD_LOGIC; + CPLLPD0_4 : in STD_LOGIC; + CPLLPD0_5 : in STD_LOGIC; + reset_n_reg1_reg_0 : in STD_LOGIC; + reg_clock_locked : in STD_LOGIC; + pipe_rx0_valid_gt : in STD_LOGIC; + pipe_rx1_valid_gt : in STD_LOGIC; + pipe_rx2_valid_gt : in STD_LOGIC; + pipe_rx3_valid_gt : in STD_LOGIC; + \rate_reg1_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_mmcm_lock_in : in STD_LOGIC; + pipe_oobclk_in : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_pipe_wrapper; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pipe_wrapper is + signal \^pipe_rxstatus\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal SYNC_TXSYNC_START0 : STD_LOGIC; + signal SYNC_TXSYNC_START00_out : STD_LOGIC; + signal SYNC_TXSYNC_START010_out : STD_LOGIC; + signal SYNC_TXSYNC_START05_out : STD_LOGIC; + signal drp_done_0 : STD_LOGIC; + signal drp_done_1 : STD_LOGIC; + signal drp_done_2 : STD_LOGIC; + signal drp_done_3 : STD_LOGIC; + signal eq_txeq_maincursor_0 : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal eq_txeq_maincursor_14 : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal eq_txeq_maincursor_21 : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal eq_txeq_maincursor_7 : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal eq_txeq_postcursor_0 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal eq_txeq_postcursor_10 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal eq_txeq_postcursor_15 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal eq_txeq_postcursor_5 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal eq_txeq_precursor_0 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal eq_txeq_precursor_10 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal eq_txeq_precursor_15 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal eq_txeq_precursor_5 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \^gen3_reg\ : STD_LOGIC; + signal gt_cpllpdrefclk : STD_LOGIC; + signal gt_phystatus_0 : STD_LOGIC; + signal gt_phystatus_1 : STD_LOGIC; + signal gt_phystatus_2 : STD_LOGIC; + signal gt_phystatus_3 : STD_LOGIC; + signal \^gt_rx_elec_idle_wire_filter\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal gt_rxcdrlock_0 : STD_LOGIC; + signal gt_rxcdrlock_1 : STD_LOGIC; + signal gt_rxcdrlock_2 : STD_LOGIC; + signal gt_rxcdrlock_3 : STD_LOGIC; + signal \gt_rxchbondi[3]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal gt_rxratedone_0 : STD_LOGIC; + signal gt_rxratedone_1 : STD_LOGIC; + signal gt_rxratedone_2 : STD_LOGIC; + signal gt_rxratedone_3 : STD_LOGIC; + signal gt_rxresetdone_0 : STD_LOGIC; + signal gt_rxresetdone_1 : STD_LOGIC; + signal gt_rxresetdone_2 : STD_LOGIC; + signal gt_rxresetdone_3 : STD_LOGIC; + signal gt_rxvalid_0 : STD_LOGIC; + signal gt_rxvalid_1 : STD_LOGIC; + signal gt_rxvalid_2 : STD_LOGIC; + signal gt_rxvalid_3 : STD_LOGIC; + signal gt_txratedone_0 : STD_LOGIC; + signal gt_txratedone_1 : STD_LOGIC; + signal gt_txratedone_2 : STD_LOGIC; + signal gt_txratedone_3 : STD_LOGIC; + signal gt_txresetdone_0 : STD_LOGIC; + signal gt_txresetdone_1 : STD_LOGIC; + signal gt_txresetdone_2 : STD_LOGIC; + signal gt_txresetdone_3 : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_i_52_n_0\ : STD_LOGIC; + signal \gtx_channel.gtxe2_channel_i_i_6__2_n_0\ : STD_LOGIC; + signal p_0_in1_in : STD_LOGIC; + signal p_0_in1_in_0 : STD_LOGIC; + signal p_0_in1_in_3 : STD_LOGIC; + signal p_0_in1_in_4 : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal p_1_in2_in : STD_LOGIC; + signal p_1_in2_in_1 : STD_LOGIC; + signal p_1_in2_in_2 : STD_LOGIC; + signal p_1_in2_in_5 : STD_LOGIC; + signal \^pipe_dclk_in_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^pipe_dclk_in_1\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^pipe_dclk_in_2\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \pipe_lane[0].gt_wrapper_i_n_1\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_11\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_15\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_17\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_18\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_2\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_21\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_22\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_23\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_24\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_25\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_26\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_27\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_28\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_29\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_30\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_31\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_32\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_33\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_34\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_35\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_36\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i_n_8\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_0\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_1\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_10\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_11\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_12\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_13\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_14\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_15\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_16\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_17\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_18\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_19\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_2\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_20\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_21\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_22\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_23\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_24\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_25\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_3\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_4\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_5\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_6\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_7\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_8\ : STD_LOGIC; + signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_9\ : STD_LOGIC; + signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_17\ : STD_LOGIC; + signal \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0\ : STD_LOGIC; + signal \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1\ : STD_LOGIC; + signal \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2\ : STD_LOGIC; + signal \pipe_lane[0].pipe_sync_i_n_1\ : STD_LOGIC; + signal \pipe_lane[0].pipe_user_i_n_1\ : STD_LOGIC; + signal \pipe_lane[0].pipe_user_i_n_10\ : STD_LOGIC; + signal \pipe_lane[0].pipe_user_i_n_11\ : STD_LOGIC; + signal \pipe_lane[0].pipe_user_i_n_12\ : STD_LOGIC; + signal \pipe_lane[0].pipe_user_i_n_15\ : STD_LOGIC; + signal \pipe_lane[0].pipe_user_i_n_5\ : STD_LOGIC; + signal \pipe_lane[0].pipe_user_i_n_6\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_1\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_11\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_15\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_16\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_17\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_2\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_20\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_21\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_22\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_23\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_24\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_25\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_26\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_27\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_28\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_29\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_30\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_31\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_32\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_33\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_34\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_35\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i_n_8\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_0\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_1\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_10\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_11\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_12\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_13\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_14\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_15\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_16\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_17\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_18\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_19\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_2\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_20\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_21\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_22\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_23\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_24\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_25\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_3\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_4\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_5\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_6\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_7\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_8\ : STD_LOGIC; + signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_9\ : STD_LOGIC; + signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_17\ : STD_LOGIC; + signal \pipe_lane[1].pipe_rate.pipe_rate_i_n_1\ : STD_LOGIC; + signal \pipe_lane[1].pipe_user_i_n_1\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_1\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_11\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_15\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_16\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_17\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_2\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_20\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_21\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_22\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_23\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_24\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_25\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_26\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_27\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_28\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_29\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_30\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_31\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_32\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_33\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_34\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_35\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i_n_8\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_0\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_1\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_10\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_11\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_12\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_13\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_14\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_15\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_16\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_17\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_18\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_19\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_2\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_20\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_21\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_22\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_23\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_24\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_25\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_3\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_4\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_5\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_6\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_7\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_8\ : STD_LOGIC; + signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_9\ : STD_LOGIC; + signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_17\ : STD_LOGIC; + signal \pipe_lane[2].pipe_user_i_n_10\ : STD_LOGIC; + signal \pipe_lane[2].pipe_user_i_n_11\ : STD_LOGIC; + signal \pipe_lane[2].pipe_user_i_n_14\ : STD_LOGIC; + signal \pipe_lane[2].pipe_user_i_n_2\ : STD_LOGIC; + signal \pipe_lane[2].pipe_user_i_n_5\ : STD_LOGIC; + signal \pipe_lane[2].pipe_user_i_n_9\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_1\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_11\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_15\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_16\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_17\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_2\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_20\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_21\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_22\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_23\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_24\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_25\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_26\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_27\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_28\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_29\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_30\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_31\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_32\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_33\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_34\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_35\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i_n_8\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_0\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_1\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_10\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_11\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_12\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_13\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_14\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_15\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_16\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_17\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_18\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_19\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_2\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_20\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_21\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_22\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_23\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_24\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_25\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_3\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_4\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_5\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_6\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_7\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_8\ : STD_LOGIC; + signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_9\ : STD_LOGIC; + signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_17\ : STD_LOGIC; + signal \pipe_lane[3].pipe_user_i_n_1\ : STD_LOGIC; + signal \^pipe_pclk_sel_out\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \pipe_reset.pipe_reset_i_n_0\ : STD_LOGIC; + signal \pipe_reset.pipe_reset_i_n_1\ : STD_LOGIC; + signal qdrp_done : STD_LOGIC; + signal \qpll_reset.qpll_reset_i_n_0\ : STD_LOGIC; + signal qpllpd : STD_LOGIC; + signal qrst_drp_start : STD_LOGIC; + signal qrst_qpllreset : STD_LOGIC; + signal rate_cpllreset_0 : STD_LOGIC; + signal rate_cpllreset_1 : STD_LOGIC; + signal rate_cpllreset_2 : STD_LOGIC; + signal rate_cpllreset_3 : STD_LOGIC; + signal rate_done_0 : STD_LOGIC; + signal rate_done_1 : STD_LOGIC; + signal rate_done_2 : STD_LOGIC; + signal rate_done_3 : STD_LOGIC; + signal rate_drp_start_0 : STD_LOGIC; + signal rate_drp_start_1 : STD_LOGIC; + signal rate_drp_start_2 : STD_LOGIC; + signal rate_drp_start_3 : STD_LOGIC; + signal rate_drp_x16_0 : STD_LOGIC; + signal rate_drp_x16_1 : STD_LOGIC; + signal rate_drp_x16_2 : STD_LOGIC; + signal rate_drp_x16_3 : STD_LOGIC; + signal rate_drp_x16x20_mode_0 : STD_LOGIC; + signal rate_drp_x16x20_mode_1 : STD_LOGIC; + signal rate_drp_x16x20_mode_2 : STD_LOGIC; + signal rate_drp_x16x20_mode_3 : STD_LOGIC; + signal rate_gen3_1 : STD_LOGIC; + signal rate_gen3_2 : STD_LOGIC; + signal rate_gen3_3 : STD_LOGIC; + signal rate_idle_0 : STD_LOGIC; + signal rate_idle_1 : STD_LOGIC; + signal rate_idle_2 : STD_LOGIC; + signal rate_idle_3 : STD_LOGIC; + signal rate_qpllpd : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rate_qpllreset : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rate_rate_0 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal rate_rate_3 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal rate_rate_6 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal rate_rate_9 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal rate_resetovrd_start_0 : STD_LOGIC; + signal rate_resetovrd_start_1 : STD_LOGIC; + signal rate_resetovrd_start_2 : STD_LOGIC; + signal rate_resetovrd_start_3 : STD_LOGIC; + signal rate_rxsync_0 : STD_LOGIC; + signal rate_rxsync_1 : STD_LOGIC; + signal rate_rxsync_2 : STD_LOGIC; + signal rate_rxsync_3 : STD_LOGIC; + signal rate_rxsync_start_0 : STD_LOGIC; + signal rate_rxsync_start_1 : STD_LOGIC; + signal rate_rxsync_start_2 : STD_LOGIC; + signal rate_rxsync_start_3 : STD_LOGIC; + signal rate_sysclksel_0 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal rate_sysclksel_2 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal rate_sysclksel_4 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal rate_sysclksel_6 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal rate_txpmareset_0 : STD_LOGIC; + signal rate_txpmareset_1 : STD_LOGIC; + signal rate_txpmareset_2 : STD_LOGIC; + signal rate_txpmareset_3 : STD_LOGIC; + signal reset_n_reg1 : STD_LOGIC; + attribute SHIFT_EXTRACT : string; + attribute SHIFT_EXTRACT of reset_n_reg1 : signal is "NO"; + attribute async_reg : string; + attribute async_reg of reset_n_reg1 : signal is "true"; + signal reset_n_reg2 : STD_LOGIC; + attribute SHIFT_EXTRACT of reset_n_reg2 : signal is "NO"; + attribute async_reg of reset_n_reg2 : signal is "true"; + signal rst_cpllreset : STD_LOGIC; + signal rst_dclk_reset : STD_LOGIC; + signal rst_gtreset : STD_LOGIC; + signal rst_rxusrclk_reset : STD_LOGIC; + signal rst_txsync_start : STD_LOGIC; + signal rst_userrdy : STD_LOGIC; + signal rxchbonden_0 : STD_LOGIC; + signal rxchbonden_1 : STD_LOGIC; + signal rxchbonden_2 : STD_LOGIC; + signal rxchbonden_3 : STD_LOGIC; + signal rxdlysresetdone_3 : STD_LOGIC; + signal rxphaligndone_s_3 : STD_LOGIC; + signal sync_txdlyen_0 : STD_LOGIC; + signal sync_txdlysreset_0 : STD_LOGIC; + signal sync_txdlysreset_1 : STD_LOGIC; + signal sync_txdlysreset_2 : STD_LOGIC; + signal sync_txdlysreset_3 : STD_LOGIC; + signal sync_txphalign_0 : STD_LOGIC; + signal sync_txphalign_1 : STD_LOGIC; + signal sync_txphalign_2 : STD_LOGIC; + signal sync_txphalign_3 : STD_LOGIC; + signal sync_txphinit_0 : STD_LOGIC; + signal sync_txphinit_1 : STD_LOGIC; + signal sync_txphinit_2 : STD_LOGIC; + signal sync_txphinit_3 : STD_LOGIC; + signal sync_txsync_done_0 : STD_LOGIC; + signal sync_txsync_done_1 : STD_LOGIC; + signal sync_txsync_done_2 : STD_LOGIC; + signal sync_txsync_done_3 : STD_LOGIC; + signal txdlysresetdone_3 : STD_LOGIC; + signal txsyncallin : STD_LOGIC; + signal user_active_lane_0 : STD_LOGIC; + signal user_active_lane_1 : STD_LOGIC; + signal user_active_lane_2 : STD_LOGIC; + signal user_active_lane_3 : STD_LOGIC; + signal user_oobclk_0 : STD_LOGIC; + signal user_oobclk_1 : STD_LOGIC; + signal user_oobclk_2 : STD_LOGIC; + signal user_oobclk_3 : STD_LOGIC; + signal user_resetdone : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal user_rx_converge : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal user_rxcdrlock_0 : STD_LOGIC; + signal user_rxcdrlock_1 : STD_LOGIC; + signal user_rxcdrlock_2 : STD_LOGIC; + signal user_rxcdrlock_3 : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of cpllpd_refclk_inst : label is "PRIMITIVE"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of reset_n_reg1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of reset_n_reg1_reg : label is "yes"; + attribute SHIFT_EXTRACT of reset_n_reg1_reg : label is "NO"; + attribute ASYNC_REG_boolean of reset_n_reg2_reg : label is std.standard.true; + attribute KEEP of reset_n_reg2_reg : label is "yes"; + attribute SHIFT_EXTRACT of reset_n_reg2_reg : label is "NO"; +begin + PIPE_RXSTATUS(2 downto 0) <= \^pipe_rxstatus\(2 downto 0); + gen3_reg <= \^gen3_reg\; + gt_rx_elec_idle_wire_filter(3 downto 0) <= \^gt_rx_elec_idle_wire_filter\(3 downto 0); + pipe_dclk_in_0(2 downto 0) <= \^pipe_dclk_in_0\(2 downto 0); + pipe_dclk_in_1(2 downto 0) <= \^pipe_dclk_in_1\(2 downto 0); + pipe_dclk_in_2(2 downto 0) <= \^pipe_dclk_in_2\(2 downto 0); + pipe_pclk_sel_out(3 downto 0) <= \^pipe_pclk_sel_out\(3 downto 0); +cpllpd_refclk_inst: unisim.vcomponents.BUFG + port map ( + I => sys_clk, + O => gt_cpllpdrefclk + ); +\gtx_channel.gtxe2_channel_i_i_52\: unisim.vcomponents.LUT5 + generic map( + INIT => X"4555FFFF" + ) + port map ( + I0 => \pipe_lane[2].pipe_user_i_n_14\, + I1 => \pipe_lane[2].pipe_user_i_n_9\, + I2 => \pipe_lane[2].pipe_user_i_n_11\, + I3 => \pipe_lane[2].pipe_user_i_n_10\, + I4 => user_rx_converge(3), + O => \gtx_channel.gtxe2_channel_i_i_52_n_0\ + ); +\gtx_channel.gtxe2_channel_i_i_6__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAAA0080" + ) + port map ( + I0 => user_rx_converge(1), + I1 => \pipe_lane[0].pipe_user_i_n_11\, + I2 => \pipe_lane[0].pipe_user_i_n_12\, + I3 => \pipe_lane[0].pipe_user_i_n_10\, + I4 => \pipe_lane[0].pipe_user_i_n_15\, + I5 => \gtx_channel.gtxe2_channel_i_i_52_n_0\, + O => \gtx_channel.gtxe2_channel_i_i_6__2_n_0\ + ); +\pipe_lane[0].gt_wrapper_i\: entity work.pcie_7x_0_pcie_7x_0_gt_wrapper + port map ( + CPLLPD0 => CPLLPD0, + DRPADDR(7) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_18\, + DRPADDR(6) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_19\, + DRPADDR(5) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_20\, + DRPADDR(4) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_21\, + DRPADDR(3) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_22\, + DRPADDR(2) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_23\, + DRPADDR(1) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_24\, + DRPADDR(0) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_25\, + DRPDI(15) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_2\, + DRPDI(14) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_3\, + DRPDI(13) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_4\, + DRPDI(12) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_5\, + DRPDI(11) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_6\, + DRPDI(10) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_7\, + DRPDI(9) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_8\, + DRPDI(8) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_9\, + DRPDI(7) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_10\, + DRPDI(6) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_11\, + DRPDI(5) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_12\, + DRPDI(4) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_13\, + DRPDI(3) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_14\, + DRPDI(2) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_15\, + DRPDI(1) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_16\, + DRPDI(0) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_17\, + DRP_DO(15) => \pipe_lane[0].gt_wrapper_i_n_21\, + DRP_DO(14) => \pipe_lane[0].gt_wrapper_i_n_22\, + DRP_DO(13) => \pipe_lane[0].gt_wrapper_i_n_23\, + DRP_DO(12) => \pipe_lane[0].gt_wrapper_i_n_24\, + DRP_DO(11) => \pipe_lane[0].gt_wrapper_i_n_25\, + DRP_DO(10) => \pipe_lane[0].gt_wrapper_i_n_26\, + DRP_DO(9) => \pipe_lane[0].gt_wrapper_i_n_27\, + DRP_DO(8) => \pipe_lane[0].gt_wrapper_i_n_28\, + DRP_DO(7) => \pipe_lane[0].gt_wrapper_i_n_29\, + DRP_DO(6) => \pipe_lane[0].gt_wrapper_i_n_30\, + DRP_DO(5) => \pipe_lane[0].gt_wrapper_i_n_31\, + DRP_DO(4) => \pipe_lane[0].gt_wrapper_i_n_32\, + DRP_DO(3) => \pipe_lane[0].gt_wrapper_i_n_33\, + DRP_DO(2) => \pipe_lane[0].gt_wrapper_i_n_34\, + DRP_DO(1) => \pipe_lane[0].gt_wrapper_i_n_35\, + DRP_DO(0) => \pipe_lane[0].gt_wrapper_i_n_36\, + DRP_GTXRESET => rst_gtreset, + DRP_RDY => \pipe_lane[0].gt_wrapper_i_n_2\, + PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(1 downto 0), + PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(0), + PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(0), + PIPE_RXSTATUS(2 downto 0) => \^pipe_rxstatus\(2 downto 0), + PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(0), + PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0), + PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(1 downto 0), + PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(0), + QPLL_QPLLOUTCLK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1\, + QPLL_QPLLOUTREFCLK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2\, + QRST_CPLLLOCK(0) => \pipe_lane[0].gt_wrapper_i_n_1\, + RATE_PHYSTATUS => gt_phystatus_0, + RATE_RXRATEDONE => gt_rxratedone_0, + RATE_TXRATEDONE => gt_txratedone_0, + RST_CPLLRESET => rst_cpllreset, + RXCHBONDO(4 downto 0) => \gt_rxchbondi[3]_0\(4 downto 0), + RXRATE(0) => rate_rate_0(0), + RXSYSCLKSEL(0) => rate_sysclksel_0(0), + SYNC_RXPHALIGNDONE_M => \pipe_lane[0].gt_wrapper_i_n_11\, + SYNC_TXDLYSRESET => sync_txdlysreset_0, + SYNC_TXPHALIGN => sync_txphalign_0, + SYNC_TXPHINIT => sync_txphinit_0, + TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_0(6 downto 0), + TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_0(4 downto 0), + TXPRECURSOR(4 downto 0) => eq_txeq_precursor_0(4 downto 0), + USER_OOBCLK => user_oobclk_0, + USER_RXRESETDONE => gt_rxresetdone_0, + USER_TXRESETDONE => gt_txresetdone_0, + \cplllock_reg1_reg[0]\ => \pipe_lane[0].pipe_drp.pipe_drp_i_n_0\, + \cplllock_reg1_reg[0]_0\ => \pipe_lane[0].pipe_drp.pipe_drp_i_n_1\, + \cplllock_reg1_reg[0]_1\ => \gtx_channel.gtxe2_channel_i_i_6__2_n_0\, + \cplllock_reg1_reg[0]_2\(2 downto 0) => \cplllock_reg1_reg[3]\(2 downto 0), + cpllpd => cpllpd, + gt_cpllpdrefclk => gt_cpllpdrefclk, + gt_rx_data_k_wire_filter(1 downto 0) => gt_rx_data_k_wire_filter(1 downto 0), + gt_rx_data_wire_filter(15 downto 0) => gt_rx_data_wire_filter(15 downto 0), + gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(0), + gt_rxcdrlock_0 => gt_rxcdrlock_0, + gt_rxvalid_0 => gt_rxvalid_0, + pci_exp_rxn(0) => pci_exp_rxn(0), + pci_exp_rxp(0) => pci_exp_rxp(0), + pci_exp_txn(0) => pci_exp_txn(0), + pci_exp_txp(0) => pci_exp_txp(0), + pipe_dclk_in => pipe_dclk_in, + pipe_dclk_in_0 => \pipe_lane[0].gt_wrapper_i_n_8\, + pipe_dclk_in_1 => \pipe_lane[0].gt_wrapper_i_n_15\, + pipe_dclk_in_2 => \pipe_lane[0].gt_wrapper_i_n_17\, + pipe_dclk_in_3 => \pipe_lane[0].gt_wrapper_i_n_18\, + pipe_pclk_in => pipe_pclk_in, + pipe_rxoutclk_out(0) => pipe_rxoutclk_out(0), + pipe_rxusrclk_in => pipe_rxusrclk_in, + pipe_tx_deemph_gt => pipe_tx_deemph_gt, + pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt, + pipe_txoutclk_out => pipe_txoutclk_out, + rate_cpllreset_0 => rate_cpllreset_0, + rate_txpmareset_0 => rate_txpmareset_0, + rst_userrdy => rst_userrdy, + rxchbonden_0 => rxchbonden_0, + sync_txdlyen_0 => sync_txdlyen_0, + sys_clk => sys_clk + ); +\pipe_lane[0].pipe_drp.pipe_drp_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_drp + port map ( + D(15) => \pipe_lane[0].gt_wrapper_i_n_21\, + D(14) => \pipe_lane[0].gt_wrapper_i_n_22\, + D(13) => \pipe_lane[0].gt_wrapper_i_n_23\, + D(12) => \pipe_lane[0].gt_wrapper_i_n_24\, + D(11) => \pipe_lane[0].gt_wrapper_i_n_25\, + D(10) => \pipe_lane[0].gt_wrapper_i_n_26\, + D(9) => \pipe_lane[0].gt_wrapper_i_n_27\, + D(8) => \pipe_lane[0].gt_wrapper_i_n_28\, + D(7) => \pipe_lane[0].gt_wrapper_i_n_29\, + D(6) => \pipe_lane[0].gt_wrapper_i_n_30\, + D(5) => \pipe_lane[0].gt_wrapper_i_n_31\, + D(4) => \pipe_lane[0].gt_wrapper_i_n_32\, + D(3) => \pipe_lane[0].gt_wrapper_i_n_33\, + D(2) => \pipe_lane[0].gt_wrapper_i_n_34\, + D(1) => \pipe_lane[0].gt_wrapper_i_n_35\, + D(0) => \pipe_lane[0].gt_wrapper_i_n_36\, + DRPADDR(7) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_18\, + DRPADDR(6) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_19\, + DRPADDR(5) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_20\, + DRPADDR(4) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_21\, + DRPADDR(3) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_22\, + DRPADDR(2) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_23\, + DRPADDR(1) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_24\, + DRPADDR(0) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_25\, + DRPDI(15) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_2\, + DRPDI(14) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_3\, + DRPDI(13) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_4\, + DRPDI(12) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_5\, + DRPDI(11) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_6\, + DRPDI(10) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_7\, + DRPDI(9) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_8\, + DRPDI(8) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_9\, + DRPDI(7) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_10\, + DRPDI(6) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_11\, + DRPDI(5) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_12\, + DRPDI(4) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_13\, + DRPDI(3) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_14\, + DRPDI(2) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_15\, + DRPDI(1) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_16\, + DRPDI(0) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_17\, + DRP_DONE => drp_done_0, + DRP_GTXRESET => rst_gtreset, + DRP_RDY => \pipe_lane[0].gt_wrapper_i_n_2\, + RATE_DRP_START => rate_drp_start_0, + RATE_DRP_X16 => rate_drp_x16_0, + RATE_DRP_X16X20_MODE => rate_drp_x16x20_mode_0, + RST_DCLK_RESET => rst_dclk_reset, + \fsm_reg[1]_0\ => \pipe_lane[0].pipe_drp.pipe_drp_i_n_0\, + \fsm_reg[1]_1\ => \pipe_lane[0].pipe_drp.pipe_drp_i_n_1\, + pipe_dclk_in => pipe_dclk_in, + \rate_reg1_reg[0]_0\(0) => \rate_reg1_reg[0]\(0) + ); +\pipe_lane[0].pipe_eq.pipe_eq_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_eq + port map ( + RST_CPLLRESET => rst_cpllreset, + TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_0(6 downto 0), + TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_0(4 downto 0), + TXPRECURSOR(4 downto 0) => eq_txeq_precursor_0(4 downto 0), + USER_RATE_GEN3 => \^gen3_reg\, + USER_RXEQ_ADAPT_DONE => \pipe_lane[0].pipe_eq.pipe_eq_i_n_17\, + pipe_pclk_in => pipe_pclk_in + ); +\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i\: entity work.pcie_7x_0_pcie_7x_0_gt_common + port map ( + QPLL_DRP_DONE => qdrp_done, + QPLL_DRP_GEN3 => \pipe_lane[1].pipe_rate.pipe_rate_i_n_1\, + QPLL_QPLLLOCK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0\, + QPLL_QPLLOUTCLK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1\, + QPLL_QPLLOUTREFCLK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2\, + QPLL_QPLLPD => qpllpd, + QPLL_QPLLRESET => qrst_qpllreset, + QRST_DRP_START => qrst_drp_start, + RST_DCLK_RESET => rst_dclk_reset, + pipe_dclk_in => pipe_dclk_in, + sys_clk => sys_clk + ); +\pipe_lane[0].pipe_rate.pipe_rate_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_rate + port map ( + QRST_CPLLLOCK(0) => \pipe_lane[0].gt_wrapper_i_n_1\, + QRST_QPLLPD_IN(0) => rate_qpllpd(0), + QRST_QPLLRESET_IN(0) => rate_qpllreset(0), + RATE_DRP_DONE => drp_done_0, + RATE_DRP_START => rate_drp_start_0, + RATE_DRP_X16 => rate_drp_x16_0, + RATE_DRP_X16X20_MODE => rate_drp_x16x20_mode_0, + RATE_PHYSTATUS => gt_phystatus_0, + RATE_QPLLLOCK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0\, + RATE_RXRATEDONE => gt_rxratedone_0, + RATE_TXRATEDONE => gt_txratedone_0, + RATE_TXSYNC_DONE => sync_txsync_done_0, + RST_CPLLRESET => rst_cpllreset, + RST_IDLE => \pipe_reset.pipe_reset_i_n_1\, + RST_TXSYNC_START => rst_txsync_start, + RXRATE(0) => rate_rate_0(0), + RXSYSCLKSEL(0) => rate_sysclksel_0(0), + SYNC_RATE_IDLE => rate_idle_0, + SYNC_RXSYNC_START => rate_rxsync_start_0, + SYNC_TXSYNC_START => SYNC_TXSYNC_START010_out, + USER_RATE_DONE => rate_done_0, + USER_RATE_GEN3 => \^gen3_reg\, + USER_RATE_RXSYNC => rate_rxsync_0, + USER_RESETOVRD_START => rate_resetovrd_start_0, + USER_RXRESETDONE => gt_rxresetdone_0, + USER_TXRESETDONE => gt_txresetdone_0, + \fsm[0]_i_9_0\ => p_1_in2_in, + \out\ => p_0_in1_in, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_pclk_in => pipe_pclk_in, + pipe_pclk_sel_out(0) => \^pipe_pclk_sel_out\(0), + rate_cpllpd_0 => rate_cpllpd_0, + rate_cpllreset_0 => rate_cpllreset_0, + \rate_in_reg1_reg[0]_0\(0) => \rate_reg1_reg[0]\(0), + rate_txpmareset_0 => rate_txpmareset_0, + rxchbonden_0 => rxchbonden_0, + user_active_lane_0 => user_active_lane_0 + ); +\pipe_lane[0].pipe_sync_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_sync + port map ( + \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\ => \pipe_lane[0].pipe_user_i_n_6\, + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ => p_1_in2_in, + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\ => p_0_in1_in, + Q(2) => sync_txphalign_0, + Q(1) => sync_txphinit_0, + Q(0) => sync_txdlysreset_0, + RST_CPLLRESET => rst_cpllreset, + RST_TXSYNC_DONE(0) => sync_txsync_done_0, + SYNC_RATE_IDLE => rate_idle_0, + SYNC_RXCDRLOCK => user_rxcdrlock_0, + SYNC_RXDLYSRESETDONE => rxdlysresetdone_3, + SYNC_RXPHALIGNDONE_M => \pipe_lane[0].gt_wrapper_i_n_11\, + SYNC_RXPHALIGNDONE_S => rxphaligndone_s_3, + SYNC_RXSYNC_START => rate_rxsync_start_0, + SYNC_TXDLYSRESETDONE => txdlysresetdone_3, + SYNC_TXPHALIGNDONE => txsyncallin, + SYNC_TXPHINITDONE => \pipe_lane[0].pipe_user_i_n_5\, + SYNC_TXSYNC_START => SYNC_TXSYNC_START010_out, + USER_RATE_GEN3 => \^gen3_reg\, + gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(0), + \out\ => p_1_in, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_pclk_in => pipe_pclk_in, + sync_txdlyen_0 => sync_txdlyen_0, + txphaligndone_reg3_reg_0 => \pipe_lane[0].pipe_sync_i_n_1\, + user_active_lane_0 => user_active_lane_0 + ); +\pipe_lane[0].pipe_user_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_user + port map ( + \FSM_onehot_txsync_fsm.fsm_tx_reg[5]\ => \pipe_lane[0].pipe_sync_i_n_1\, + \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\ => p_1_in, + PIPE_RXSTATUS(0) => \^pipe_rxstatus\(2), + PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(0), + PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(0), + RST_CPLLRESET => rst_cpllreset, + RST_IDLE => \pipe_reset.pipe_reset_i_n_1\, + RST_PHYSTATUS(0) => gt_phystatus_0, + RST_RESETDONE(0) => user_resetdone(0), + RST_RXCDRLOCK(0) => user_rxcdrlock_0, + RST_RXUSRCLK_RESET => rst_rxusrclk_reset, + SYNC_TXPHALIGNDONE => txsyncallin, + SYNC_TXPHINITDONE => \pipe_lane[0].pipe_user_i_n_5\, + USER_OOBCLK => user_oobclk_0, + USER_RATE_DONE => rate_done_0, + USER_RATE_GEN3 => \^gen3_reg\, + USER_RATE_IDLE => rate_idle_0, + USER_RATE_RXSYNC => rate_rxsync_0, + USER_RESETOVRD_START => rate_resetovrd_start_0, + USER_RXEQ_ADAPT_DONE => \pipe_lane[0].pipe_eq.pipe_eq_i_n_17\, + USER_RXRESETDONE => gt_rxresetdone_0, + USER_TXRESETDONE => gt_txresetdone_0, + \converge_cnt_reg[15]_0\ => \pipe_lane[0].pipe_user_i_n_10\, + \converge_cnt_reg[1]_0\ => \pipe_lane[0].pipe_user_i_n_11\, + \converge_cnt_reg[6]_0\ => \pipe_lane[0].pipe_user_i_n_12\, + converge_gen3_reg_0 => \pipe_lane[0].pipe_user_i_n_15\, + gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(0), + gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(0), + gt_rxcdrlock_0 => gt_rxcdrlock_0, + gt_rxvalid_0 => gt_rxvalid_0, + gt_rxvalid_q_reg => gt_rxvalid_q_reg, + \out\ => \pipe_lane[0].pipe_user_i_n_1\, + pipe_oobclk_in => pipe_oobclk_in, + pipe_pclk_in => pipe_pclk_in, + pipe_pclk_sel_out(0) => \^pipe_pclk_sel_out\(0), + pipe_rx0_valid_gt => pipe_rx0_valid_gt, + pipe_rxusrclk_in => pipe_rxusrclk_in, + txcompliance_reg2_reg_0 => p_0_in1_in, + txelecidle_reg2_reg_0 => p_1_in2_in, + txelecidle_reg2_reg_1 => \pipe_lane[0].pipe_user_i_n_6\, + txphaligndone_reg1_reg => \pipe_lane[1].gt_wrapper_i_n_16\, + txphaligndone_reg1_reg_0 => \pipe_lane[0].gt_wrapper_i_n_17\, + txphaligndone_reg1_reg_1 => \pipe_lane[2].pipe_user_i_n_2\, + txphinitdone_reg1_reg => \pipe_lane[1].gt_wrapper_i_n_17\, + txphinitdone_reg1_reg_0 => \pipe_lane[0].gt_wrapper_i_n_18\, + txphinitdone_reg1_reg_1 => \pipe_lane[2].pipe_user_i_n_5\, + user_active_lane_0 => user_active_lane_0, + user_active_lane_1 => user_active_lane_1 + ); +\pipe_lane[1].gt_wrapper_i\: entity work.pcie_7x_0_pcie_7x_0_gt_wrapper_37 + port map ( + CPLLPD0_3 => CPLLPD0_3, + DRPADDR(7) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_2\, + DRPADDR(6) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_3\, + DRPADDR(5) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_4\, + DRPADDR(4) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_5\, + DRPADDR(3) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_6\, + DRPADDR(2) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_7\, + DRPADDR(1) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_8\, + DRPADDR(0) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_9\, + DRPDI(15) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_10\, + DRPDI(14) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_11\, + DRPDI(13) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_12\, + DRPDI(12) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_13\, + DRPDI(11) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_14\, + DRPDI(10) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_15\, + DRPDI(9) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_16\, + DRPDI(8) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_17\, + DRPDI(7) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_18\, + DRPDI(6) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_19\, + DRPDI(5) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_20\, + DRPDI(4) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_21\, + DRPDI(3) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_22\, + DRPDI(2) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_23\, + DRPDI(1) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_24\, + DRPDI(0) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_25\, + DRP_DO(15) => \pipe_lane[1].gt_wrapper_i_n_20\, + DRP_DO(14) => \pipe_lane[1].gt_wrapper_i_n_21\, + DRP_DO(13) => \pipe_lane[1].gt_wrapper_i_n_22\, + DRP_DO(12) => \pipe_lane[1].gt_wrapper_i_n_23\, + DRP_DO(11) => \pipe_lane[1].gt_wrapper_i_n_24\, + DRP_DO(10) => \pipe_lane[1].gt_wrapper_i_n_25\, + DRP_DO(9) => \pipe_lane[1].gt_wrapper_i_n_26\, + DRP_DO(8) => \pipe_lane[1].gt_wrapper_i_n_27\, + DRP_DO(7) => \pipe_lane[1].gt_wrapper_i_n_28\, + DRP_DO(6) => \pipe_lane[1].gt_wrapper_i_n_29\, + DRP_DO(5) => \pipe_lane[1].gt_wrapper_i_n_30\, + DRP_DO(4) => \pipe_lane[1].gt_wrapper_i_n_31\, + DRP_DO(3) => \pipe_lane[1].gt_wrapper_i_n_32\, + DRP_DO(2) => \pipe_lane[1].gt_wrapper_i_n_33\, + DRP_DO(1) => \pipe_lane[1].gt_wrapper_i_n_34\, + DRP_DO(0) => \pipe_lane[1].gt_wrapper_i_n_35\, + DRP_GTXRESET => rst_gtreset, + DRP_RDY => \pipe_lane[1].gt_wrapper_i_n_2\, + PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(3 downto 2), + PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(1), + PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(1), + PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(1), + PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(31 downto 16), + PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(3 downto 2), + PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(1), + QPLL_QPLLOUTCLK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1\, + QPLL_QPLLOUTREFCLK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2\, + QRST_CPLLLOCK(0) => \pipe_lane[1].gt_wrapper_i_n_1\, + RATE_PHYSTATUS => gt_phystatus_1, + RATE_RXRATEDONE => gt_rxratedone_1, + RATE_TXRATEDONE => gt_txratedone_1, + RST_CPLLRESET => rst_cpllreset, + RXCHBONDO(4 downto 0) => \gt_rxchbondi[3]_0\(4 downto 0), + RXRATE(0) => rate_rate_3(0), + RXSYSCLKSEL(0) => rate_sysclksel_2(0), + SYNC_TXDLYSRESET => sync_txdlysreset_1, + SYNC_TXPHALIGN => sync_txphalign_1, + SYNC_TXPHINIT => sync_txphinit_1, + TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_7(6 downto 0), + TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_5(4 downto 0), + TXPRECURSOR(4 downto 0) => eq_txeq_precursor_5(4 downto 0), + USER_OOBCLK => user_oobclk_1, + USER_RXRESETDONE => gt_rxresetdone_1, + USER_TXRESETDONE => gt_txresetdone_1, + \cplllock_reg1_reg[1]\ => \pipe_lane[1].pipe_drp.pipe_drp_i_n_0\, + \cplllock_reg1_reg[1]_0\ => \pipe_lane[1].pipe_drp.pipe_drp_i_n_1\, + \cplllock_reg1_reg[1]_1\ => \gtx_channel.gtxe2_channel_i_i_6__2_n_0\, + \cplllock_reg1_reg[1]_2\(2 downto 0) => \cplllock_reg1_reg[3]\(2 downto 0), + cpllpd_0 => cpllpd_0, + gt_cpllpdrefclk => gt_cpllpdrefclk, + gt_rx_data_k_wire_filter(1 downto 0) => gt_rx_data_k_wire_filter(3 downto 2), + gt_rx_data_wire_filter(15 downto 0) => gt_rx_data_wire_filter(31 downto 16), + gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(1), + gt_rxcdrlock_1 => gt_rxcdrlock_1, + gt_rxvalid_1 => gt_rxvalid_1, + pci_exp_rxn(0) => pci_exp_rxn(1), + pci_exp_rxp(0) => pci_exp_rxp(1), + pci_exp_txn(0) => pci_exp_txn(1), + pci_exp_txp(0) => pci_exp_txp(1), + pipe_dclk_in => pipe_dclk_in, + pipe_dclk_in_0 => \pipe_lane[1].gt_wrapper_i_n_8\, + pipe_dclk_in_1 => \pipe_lane[1].gt_wrapper_i_n_11\, + pipe_dclk_in_2 => \pipe_lane[1].gt_wrapper_i_n_15\, + pipe_dclk_in_3 => \pipe_lane[1].gt_wrapper_i_n_16\, + pipe_dclk_in_4 => \pipe_lane[1].gt_wrapper_i_n_17\, + pipe_dclk_in_5(2 downto 0) => \^pipe_dclk_in_0\(2 downto 0), + pipe_pclk_in => pipe_pclk_in, + pipe_rxoutclk_out(0) => pipe_rxoutclk_out(1), + pipe_rxusrclk_in => pipe_rxusrclk_in, + pipe_tx_deemph_gt => pipe_tx_deemph_gt, + pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt, + rate_cpllreset_1 => rate_cpllreset_1, + rate_txpmareset_1 => rate_txpmareset_1, + rst_userrdy => rst_userrdy, + rxchbonden_1 => rxchbonden_1, + sys_clk => sys_clk + ); +\pipe_lane[1].pipe_drp.pipe_drp_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_drp_38 + port map ( + D(15) => \pipe_lane[1].gt_wrapper_i_n_20\, + D(14) => \pipe_lane[1].gt_wrapper_i_n_21\, + D(13) => \pipe_lane[1].gt_wrapper_i_n_22\, + D(12) => \pipe_lane[1].gt_wrapper_i_n_23\, + D(11) => \pipe_lane[1].gt_wrapper_i_n_24\, + D(10) => \pipe_lane[1].gt_wrapper_i_n_25\, + D(9) => \pipe_lane[1].gt_wrapper_i_n_26\, + D(8) => \pipe_lane[1].gt_wrapper_i_n_27\, + D(7) => \pipe_lane[1].gt_wrapper_i_n_28\, + D(6) => \pipe_lane[1].gt_wrapper_i_n_29\, + D(5) => \pipe_lane[1].gt_wrapper_i_n_30\, + D(4) => \pipe_lane[1].gt_wrapper_i_n_31\, + D(3) => \pipe_lane[1].gt_wrapper_i_n_32\, + D(2) => \pipe_lane[1].gt_wrapper_i_n_33\, + D(1) => \pipe_lane[1].gt_wrapper_i_n_34\, + D(0) => \pipe_lane[1].gt_wrapper_i_n_35\, + DRPADDR(7) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_2\, + DRPADDR(6) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_3\, + DRPADDR(5) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_4\, + DRPADDR(4) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_5\, + DRPADDR(3) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_6\, + DRPADDR(2) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_7\, + DRPADDR(1) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_8\, + DRPADDR(0) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_9\, + DRPDI(15) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_10\, + DRPDI(14) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_11\, + DRPDI(13) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_12\, + DRPDI(12) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_13\, + DRPDI(11) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_14\, + DRPDI(10) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_15\, + DRPDI(9) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_16\, + DRPDI(8) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_17\, + DRPDI(7) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_18\, + DRPDI(6) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_19\, + DRPDI(5) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_20\, + DRPDI(4) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_21\, + DRPDI(3) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_22\, + DRPDI(2) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_23\, + DRPDI(1) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_24\, + DRPDI(0) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_25\, + DRP_DONE => drp_done_1, + DRP_GTXRESET => rst_gtreset, + DRP_RDY => \pipe_lane[1].gt_wrapper_i_n_2\, + RATE_DRP_START => rate_drp_start_1, + RATE_DRP_X16 => rate_drp_x16_1, + RATE_DRP_X16X20_MODE => rate_drp_x16x20_mode_1, + RST_DCLK_RESET => rst_dclk_reset, + \fsm_reg[1]_0\ => \pipe_lane[1].pipe_drp.pipe_drp_i_n_0\, + \fsm_reg[1]_1\ => \pipe_lane[1].pipe_drp.pipe_drp_i_n_1\, + pipe_dclk_in => pipe_dclk_in, + \rate_reg1_reg[0]_0\(0) => \rate_reg1_reg[0]\(0) + ); +\pipe_lane[1].pipe_eq.pipe_eq_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_eq_39 + port map ( + RST_CPLLRESET => rst_cpllreset, + TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_7(6 downto 0), + TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_5(4 downto 0), + TXPRECURSOR(4 downto 0) => eq_txeq_precursor_5(4 downto 0), + USER_RXEQ_ADAPT_DONE => \pipe_lane[1].pipe_eq.pipe_eq_i_n_17\, + pipe_pclk_in => pipe_pclk_in, + rate_gen3_1 => rate_gen3_1 + ); +\pipe_lane[1].pipe_rate.pipe_rate_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_rate_40 + port map ( + QPLL_DRP_GEN3 => \pipe_lane[1].pipe_rate.pipe_rate_i_n_1\, + QRST_CPLLLOCK(0) => \pipe_lane[1].gt_wrapper_i_n_1\, + QRST_QPLLPD_IN(0) => rate_qpllpd(1), + QRST_QPLLRESET_IN(0) => rate_qpllreset(1), + RATE_DRP_DONE => drp_done_1, + RATE_DRP_START => rate_drp_start_1, + RATE_DRP_X16 => rate_drp_x16_1, + RATE_DRP_X16X20_MODE => rate_drp_x16x20_mode_1, + RATE_PHYSTATUS => gt_phystatus_1, + RATE_QPLLLOCK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0\, + RATE_RXRATEDONE => gt_rxratedone_1, + RATE_TXRATEDONE => gt_txratedone_1, + RATE_TXSYNC_DONE => sync_txsync_done_1, + RST_CPLLRESET => rst_cpllreset, + RST_IDLE => \pipe_reset.pipe_reset_i_n_1\, + RST_TXSYNC_START => rst_txsync_start, + RXRATE(0) => rate_rate_3(0), + RXSYSCLKSEL(0) => rate_sysclksel_2(0), + SYNC_RATE_IDLE => rate_idle_1, + SYNC_RXSYNC_START => rate_rxsync_start_1, + SYNC_TXSYNC_START => SYNC_TXSYNC_START05_out, + USER_RATE_DONE => rate_done_1, + USER_RATE_GEN3 => \^gen3_reg\, + USER_RATE_RXSYNC => rate_rxsync_1, + USER_RESETOVRD_START => rate_resetovrd_start_1, + USER_RXRESETDONE => gt_rxresetdone_1, + USER_TXRESETDONE => gt_txresetdone_1, + \fsm[0]_i_9__0_0\ => p_1_in2_in_1, + \out\ => p_0_in1_in_0, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_pclk_in => pipe_pclk_in, + pipe_pclk_sel_out(0) => \^pipe_pclk_sel_out\(1), + rate_cpllpd_1 => rate_cpllpd_1, + rate_cpllreset_1 => rate_cpllreset_1, + rate_gen3_1 => rate_gen3_1, + rate_gen3_2 => rate_gen3_2, + rate_gen3_3 => rate_gen3_3, + \rate_in_reg1_reg[0]_0\(0) => \rate_reg1_reg[0]\(0), + rate_txpmareset_1 => rate_txpmareset_1, + rxchbonden_1 => rxchbonden_1, + user_active_lane_1 => user_active_lane_1 + ); +\pipe_lane[1].pipe_sync_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_sync_41 + port map ( + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ => p_0_in1_in_0, + Q(2) => sync_txphalign_1, + Q(1) => sync_txphinit_1, + Q(0) => sync_txdlysreset_1, + RST_CPLLRESET => rst_cpllreset, + RST_TXSYNC_DONE(0) => sync_txsync_done_1, + SYNC_GEN3 => rate_gen3_1, + SYNC_RATE_IDLE => rate_idle_1, + SYNC_RXCDRLOCK => user_rxcdrlock_1, + SYNC_RXDLYSRESETDONE => rxdlysresetdone_3, + SYNC_RXPHALIGNDONE_M => \pipe_lane[0].gt_wrapper_i_n_11\, + SYNC_RXPHALIGNDONE_S => rxphaligndone_s_3, + SYNC_RXSYNC_START => rate_rxsync_start_1, + SYNC_TXDLYSRESETDONE => txdlysresetdone_3, + SYNC_TXPHALIGNDONE => txsyncallin, + SYNC_TXPHINITDONE => \pipe_lane[0].pipe_user_i_n_5\, + SYNC_TXSYNC_START => SYNC_TXSYNC_START05_out, + gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(1), + \out\ => p_1_in2_in_1, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_pclk_in => pipe_pclk_in, + user_active_lane_1 => user_active_lane_1 + ); +\pipe_lane[1].pipe_user_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_user_42 + port map ( + PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(1), + PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(1), + RST_CPLLRESET => rst_cpllreset, + RST_IDLE => \pipe_reset.pipe_reset_i_n_1\, + RST_PHYSTATUS(0) => gt_phystatus_1, + RST_RESETDONE(0) => user_resetdone(1), + RST_RXCDRLOCK(0) => user_rxcdrlock_1, + RST_RXUSRCLK_RESET => rst_rxusrclk_reset, + USER_OOBCLK => user_oobclk_1, + USER_RATE_DONE => rate_done_1, + USER_RATE_GEN3 => rate_gen3_1, + USER_RATE_IDLE => rate_idle_1, + USER_RATE_RXSYNC => rate_rxsync_1, + USER_RESETOVRD_START => rate_resetovrd_start_1, + USER_RXEQ_ADAPT_DONE => \pipe_lane[1].pipe_eq.pipe_eq_i_n_17\, + USER_RXRESETDONE => gt_rxresetdone_1, + USER_TXRESETDONE => gt_txresetdone_1, + gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(1), + gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(1), + gt_rxcdrlock_1 => gt_rxcdrlock_1, + gt_rxvalid_1 => gt_rxvalid_1, + gt_rxvalid_q_reg => gt_rxvalid_q_reg_0, + \out\ => \pipe_lane[1].pipe_user_i_n_1\, + pipe_oobclk_in => pipe_oobclk_in, + pipe_pclk_in => pipe_pclk_in, + pipe_pclk_sel_out(0) => \^pipe_pclk_sel_out\(1), + pipe_rx1_valid_gt => pipe_rx1_valid_gt, + pipe_rxusrclk_in => pipe_rxusrclk_in, + rxstatus_reg1_reg_0(0) => \^pipe_dclk_in_0\(2), + txcompliance_reg2_reg_0 => p_0_in1_in_0, + txelecidle_reg2_reg_0 => p_1_in2_in_1, + user_active_lane_1 => user_active_lane_1, + user_rx_converge(0) => user_rx_converge(1) + ); +\pipe_lane[2].gt_wrapper_i\: entity work.pcie_7x_0_pcie_7x_0_gt_wrapper_43 + port map ( + CPLLPD0_4 => CPLLPD0_4, + DRPADDR(7) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_2\, + DRPADDR(6) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_3\, + DRPADDR(5) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_4\, + DRPADDR(4) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_5\, + DRPADDR(3) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_6\, + DRPADDR(2) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_7\, + DRPADDR(1) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_8\, + DRPADDR(0) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_9\, + DRPDI(15) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_10\, + DRPDI(14) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_11\, + DRPDI(13) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_12\, + DRPDI(12) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_13\, + DRPDI(11) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_14\, + DRPDI(10) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_15\, + DRPDI(9) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_16\, + DRPDI(8) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_17\, + DRPDI(7) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_18\, + DRPDI(6) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_19\, + DRPDI(5) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_20\, + DRPDI(4) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_21\, + DRPDI(3) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_22\, + DRPDI(2) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_23\, + DRPDI(1) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_24\, + DRPDI(0) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_25\, + DRP_DO(15) => \pipe_lane[2].gt_wrapper_i_n_20\, + DRP_DO(14) => \pipe_lane[2].gt_wrapper_i_n_21\, + DRP_DO(13) => \pipe_lane[2].gt_wrapper_i_n_22\, + DRP_DO(12) => \pipe_lane[2].gt_wrapper_i_n_23\, + DRP_DO(11) => \pipe_lane[2].gt_wrapper_i_n_24\, + DRP_DO(10) => \pipe_lane[2].gt_wrapper_i_n_25\, + DRP_DO(9) => \pipe_lane[2].gt_wrapper_i_n_26\, + DRP_DO(8) => \pipe_lane[2].gt_wrapper_i_n_27\, + DRP_DO(7) => \pipe_lane[2].gt_wrapper_i_n_28\, + DRP_DO(6) => \pipe_lane[2].gt_wrapper_i_n_29\, + DRP_DO(5) => \pipe_lane[2].gt_wrapper_i_n_30\, + DRP_DO(4) => \pipe_lane[2].gt_wrapper_i_n_31\, + DRP_DO(3) => \pipe_lane[2].gt_wrapper_i_n_32\, + DRP_DO(2) => \pipe_lane[2].gt_wrapper_i_n_33\, + DRP_DO(1) => \pipe_lane[2].gt_wrapper_i_n_34\, + DRP_DO(0) => \pipe_lane[2].gt_wrapper_i_n_35\, + DRP_GTXRESET => rst_gtreset, + DRP_RDY => \pipe_lane[2].gt_wrapper_i_n_2\, + PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(5 downto 4), + PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(2), + PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(2), + PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(2), + PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(47 downto 32), + PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(5 downto 4), + PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(2), + QPLL_QPLLOUTCLK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1\, + QPLL_QPLLOUTREFCLK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2\, + QRST_CPLLLOCK(0) => \pipe_lane[2].gt_wrapper_i_n_1\, + RATE_PHYSTATUS => gt_phystatus_2, + RATE_RXRATEDONE => gt_rxratedone_2, + RATE_TXRATEDONE => gt_txratedone_2, + RST_CPLLRESET => rst_cpllreset, + RXCHBONDO(4 downto 0) => \gt_rxchbondi[3]_0\(4 downto 0), + RXRATE(0) => rate_rate_6(0), + RXSYSCLKSEL(0) => rate_sysclksel_4(0), + SYNC_TXDLYSRESET => sync_txdlysreset_2, + SYNC_TXPHALIGN => sync_txphalign_2, + SYNC_TXPHINIT => sync_txphinit_2, + TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_14(6 downto 0), + TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_10(4 downto 0), + TXPRECURSOR(4 downto 0) => eq_txeq_precursor_10(4 downto 0), + USER_OOBCLK => user_oobclk_2, + USER_RXRESETDONE => gt_rxresetdone_2, + USER_TXRESETDONE => gt_txresetdone_2, + \cplllock_reg1_reg[2]\ => \pipe_lane[2].pipe_drp.pipe_drp_i_n_0\, + \cplllock_reg1_reg[2]_0\ => \pipe_lane[2].pipe_drp.pipe_drp_i_n_1\, + \cplllock_reg1_reg[2]_1\ => \gtx_channel.gtxe2_channel_i_i_6__2_n_0\, + \cplllock_reg1_reg[2]_2\(2 downto 0) => \cplllock_reg1_reg[3]\(2 downto 0), + cpllpd_1 => cpllpd_1, + gt_cpllpdrefclk => gt_cpllpdrefclk, + gt_rx_data_k_wire_filter(1 downto 0) => gt_rx_data_k_wire_filter(5 downto 4), + gt_rx_data_wire_filter(15 downto 0) => gt_rx_data_wire_filter(47 downto 32), + gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(2), + gt_rxcdrlock_2 => gt_rxcdrlock_2, + gt_rxvalid_2 => gt_rxvalid_2, + pci_exp_rxn(0) => pci_exp_rxn(2), + pci_exp_rxp(0) => pci_exp_rxp(2), + pci_exp_txn(0) => pci_exp_txn(2), + pci_exp_txp(0) => pci_exp_txp(2), + pipe_dclk_in => pipe_dclk_in, + pipe_dclk_in_0 => \pipe_lane[2].gt_wrapper_i_n_8\, + pipe_dclk_in_1 => \pipe_lane[2].gt_wrapper_i_n_11\, + pipe_dclk_in_2 => \pipe_lane[2].gt_wrapper_i_n_15\, + pipe_dclk_in_3 => \pipe_lane[2].gt_wrapper_i_n_16\, + pipe_dclk_in_4 => \pipe_lane[2].gt_wrapper_i_n_17\, + pipe_dclk_in_5(2 downto 0) => \^pipe_dclk_in_1\(2 downto 0), + pipe_pclk_in => pipe_pclk_in, + pipe_rxoutclk_out(0) => pipe_rxoutclk_out(2), + pipe_rxusrclk_in => pipe_rxusrclk_in, + pipe_tx_deemph_gt => pipe_tx_deemph_gt, + pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt, + rate_cpllreset_2 => rate_cpllreset_2, + rate_txpmareset_2 => rate_txpmareset_2, + rst_userrdy => rst_userrdy, + rxchbonden_2 => rxchbonden_2, + sys_clk => sys_clk + ); +\pipe_lane[2].pipe_drp.pipe_drp_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_drp_44 + port map ( + D(15) => \pipe_lane[2].gt_wrapper_i_n_20\, + D(14) => \pipe_lane[2].gt_wrapper_i_n_21\, + D(13) => \pipe_lane[2].gt_wrapper_i_n_22\, + D(12) => \pipe_lane[2].gt_wrapper_i_n_23\, + D(11) => \pipe_lane[2].gt_wrapper_i_n_24\, + D(10) => \pipe_lane[2].gt_wrapper_i_n_25\, + D(9) => \pipe_lane[2].gt_wrapper_i_n_26\, + D(8) => \pipe_lane[2].gt_wrapper_i_n_27\, + D(7) => \pipe_lane[2].gt_wrapper_i_n_28\, + D(6) => \pipe_lane[2].gt_wrapper_i_n_29\, + D(5) => \pipe_lane[2].gt_wrapper_i_n_30\, + D(4) => \pipe_lane[2].gt_wrapper_i_n_31\, + D(3) => \pipe_lane[2].gt_wrapper_i_n_32\, + D(2) => \pipe_lane[2].gt_wrapper_i_n_33\, + D(1) => \pipe_lane[2].gt_wrapper_i_n_34\, + D(0) => \pipe_lane[2].gt_wrapper_i_n_35\, + DRPADDR(7) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_2\, + DRPADDR(6) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_3\, + DRPADDR(5) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_4\, + DRPADDR(4) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_5\, + DRPADDR(3) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_6\, + DRPADDR(2) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_7\, + DRPADDR(1) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_8\, + DRPADDR(0) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_9\, + DRPDI(15) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_10\, + DRPDI(14) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_11\, + DRPDI(13) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_12\, + DRPDI(12) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_13\, + DRPDI(11) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_14\, + DRPDI(10) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_15\, + DRPDI(9) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_16\, + DRPDI(8) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_17\, + DRPDI(7) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_18\, + DRPDI(6) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_19\, + DRPDI(5) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_20\, + DRPDI(4) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_21\, + DRPDI(3) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_22\, + DRPDI(2) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_23\, + DRPDI(1) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_24\, + DRPDI(0) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_25\, + DRP_DONE => drp_done_2, + DRP_GTXRESET => rst_gtreset, + DRP_RDY => \pipe_lane[2].gt_wrapper_i_n_2\, + RATE_DRP_START => rate_drp_start_2, + RATE_DRP_X16 => rate_drp_x16_2, + RATE_DRP_X16X20_MODE => rate_drp_x16x20_mode_2, + RST_DCLK_RESET => rst_dclk_reset, + \fsm_reg[1]_0\ => \pipe_lane[2].pipe_drp.pipe_drp_i_n_0\, + \fsm_reg[1]_1\ => \pipe_lane[2].pipe_drp.pipe_drp_i_n_1\, + pipe_dclk_in => pipe_dclk_in, + \rate_reg1_reg[0]_0\(0) => \rate_reg1_reg[0]\(0) + ); +\pipe_lane[2].pipe_eq.pipe_eq_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_eq_45 + port map ( + RST_CPLLRESET => rst_cpllreset, + TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_14(6 downto 0), + TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_10(4 downto 0), + TXPRECURSOR(4 downto 0) => eq_txeq_precursor_10(4 downto 0), + USER_RXEQ_ADAPT_DONE => \pipe_lane[2].pipe_eq.pipe_eq_i_n_17\, + pipe_pclk_in => pipe_pclk_in, + rate_gen3_2 => rate_gen3_2 + ); +\pipe_lane[2].pipe_rate.pipe_rate_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_rate_46 + port map ( + QRST_CPLLLOCK(0) => \pipe_lane[2].gt_wrapper_i_n_1\, + QRST_QPLLPD_IN(0) => rate_qpllpd(2), + QRST_QPLLRESET_IN(0) => rate_qpllreset(2), + RATE_DRP_DONE => drp_done_2, + RATE_DRP_START => rate_drp_start_2, + RATE_DRP_X16 => rate_drp_x16_2, + RATE_DRP_X16X20_MODE => rate_drp_x16x20_mode_2, + RATE_PHYSTATUS => gt_phystatus_2, + RATE_QPLLLOCK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0\, + RATE_RXRATEDONE => gt_rxratedone_2, + RATE_TXRATEDONE => gt_txratedone_2, + RATE_TXSYNC_DONE => sync_txsync_done_2, + RST_CPLLRESET => rst_cpllreset, + RST_IDLE => \pipe_reset.pipe_reset_i_n_1\, + RST_TXSYNC_START => rst_txsync_start, + RXRATE(0) => rate_rate_6(0), + RXSYSCLKSEL(0) => rate_sysclksel_4(0), + SYNC_RATE_IDLE => rate_idle_2, + SYNC_RXSYNC_START => rate_rxsync_start_2, + SYNC_TXSYNC_START => SYNC_TXSYNC_START00_out, + USER_RATE_DONE => rate_done_2, + USER_RATE_RXSYNC => rate_rxsync_2, + USER_RESETOVRD_START => rate_resetovrd_start_2, + USER_RXRESETDONE => gt_rxresetdone_2, + USER_TXRESETDONE => gt_txresetdone_2, + \fsm[0]_i_9__1_0\ => p_1_in2_in_2, + \out\ => p_0_in1_in_3, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_pclk_in => pipe_pclk_in, + pipe_pclk_sel_out(0) => \^pipe_pclk_sel_out\(2), + rate_cpllpd_2 => rate_cpllpd_2, + rate_cpllreset_2 => rate_cpllreset_2, + rate_gen3_2 => rate_gen3_2, + \rate_in_reg1_reg[0]_0\(0) => \rate_reg1_reg[0]\(0), + rate_txpmareset_2 => rate_txpmareset_2, + rxchbonden_2 => rxchbonden_2, + user_active_lane_2 => user_active_lane_2 + ); +\pipe_lane[2].pipe_sync_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_sync_47 + port map ( + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ => p_0_in1_in_3, + Q(2) => sync_txphalign_2, + Q(1) => sync_txphinit_2, + Q(0) => sync_txdlysreset_2, + RST_CPLLRESET => rst_cpllreset, + RST_TXSYNC_DONE(0) => sync_txsync_done_2, + SYNC_GEN3 => rate_gen3_2, + SYNC_RATE_IDLE => rate_idle_2, + SYNC_RXCDRLOCK => user_rxcdrlock_2, + SYNC_RXDLYSRESETDONE => rxdlysresetdone_3, + SYNC_RXPHALIGNDONE_M => \pipe_lane[0].gt_wrapper_i_n_11\, + SYNC_RXPHALIGNDONE_S => rxphaligndone_s_3, + SYNC_RXSYNC_START => rate_rxsync_start_2, + SYNC_TXDLYSRESETDONE => txdlysresetdone_3, + SYNC_TXPHALIGNDONE => txsyncallin, + SYNC_TXPHINITDONE => \pipe_lane[0].pipe_user_i_n_5\, + SYNC_TXSYNC_START => SYNC_TXSYNC_START00_out, + gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(2), + \out\ => p_1_in2_in_2, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_pclk_in => pipe_pclk_in, + user_active_lane_2 => user_active_lane_2 + ); +\pipe_lane[2].pipe_user_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_user_48 + port map ( + PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(2), + PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(2), + RST_CPLLRESET => rst_cpllreset, + RST_IDLE => \pipe_reset.pipe_reset_i_n_1\, + RST_PHYSTATUS(0) => gt_phystatus_2, + RST_RESETDONE(0) => user_resetdone(2), + RST_RXCDRLOCK(0) => user_rxcdrlock_2, + RST_RXUSRCLK_RESET => rst_rxusrclk_reset, + USER_OOBCLK => user_oobclk_2, + USER_RATE_DONE => rate_done_2, + USER_RATE_IDLE => rate_idle_2, + USER_RATE_RXSYNC => rate_rxsync_2, + USER_RESETOVRD_START => rate_resetovrd_start_2, + USER_RXEQ_ADAPT_DONE => \pipe_lane[2].pipe_eq.pipe_eq_i_n_17\, + USER_RXRESETDONE => gt_rxresetdone_2, + USER_TXRESETDONE => gt_txresetdone_2, + \converge_cnt_reg[15]_0\ => \pipe_lane[2].pipe_user_i_n_9\, + \converge_cnt_reg[1]_0\ => \pipe_lane[2].pipe_user_i_n_10\, + \converge_cnt_reg[6]_0\ => \pipe_lane[2].pipe_user_i_n_11\, + converge_gen3_reg_0 => \pipe_lane[2].pipe_user_i_n_14\, + gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(2), + gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(2), + gt_rxcdrlock_2 => gt_rxcdrlock_2, + gt_rxvalid_2 => gt_rxvalid_2, + gt_rxvalid_q_reg => gt_rxvalid_q_reg_1, + \out\ => \pipe_lane[3].pipe_user_i_n_1\, + phy_rdy_n_int_reg => \pipe_lane[0].pipe_user_i_n_1\, + phy_rdy_n_int_reg_0 => \pipe_lane[1].pipe_user_i_n_1\, + pipe_oobclk_in => pipe_oobclk_in, + pipe_pclk_in => pipe_pclk_in, + pipe_pclk_sel_out(0) => \^pipe_pclk_sel_out\(2), + pipe_rx2_valid_gt => pipe_rx2_valid_gt, + pipe_rxusrclk_in => pipe_rxusrclk_in, + rate_gen3_2 => rate_gen3_2, + reg_clock_locked => reg_clock_locked, + reg_clock_locked_reg => reg_clock_locked_reg, + rxstatus_reg1_reg_0(0) => \^pipe_dclk_in_1\(2), + txcompliance_reg2_reg_0 => \pipe_lane[2].pipe_user_i_n_2\, + txcompliance_reg2_reg_1 => p_0_in1_in_3, + txcompliance_reg2_reg_2 => \pipe_lane[2].pipe_user_i_n_5\, + txelecidle_reg2_reg_0 => p_1_in2_in_2, + txphaligndone_reg1_reg => \pipe_lane[2].gt_wrapper_i_n_16\, + txphaligndone_reg1_reg_0 => p_0_in1_in_4, + txphaligndone_reg1_reg_1 => p_1_in2_in_5, + txphaligndone_reg1_reg_2 => \pipe_lane[3].gt_wrapper_i_n_16\, + txphinitdone_reg1_reg => \pipe_lane[2].gt_wrapper_i_n_17\, + txphinitdone_reg1_reg_0 => \pipe_lane[3].gt_wrapper_i_n_17\, + user_active_lane_2 => user_active_lane_2 + ); +\pipe_lane[3].gt_wrapper_i\: entity work.pcie_7x_0_pcie_7x_0_gt_wrapper_49 + port map ( + CPLLPD0_5 => CPLLPD0_5, + DRPADDR(7) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_2\, + DRPADDR(6) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_3\, + DRPADDR(5) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_4\, + DRPADDR(4) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_5\, + DRPADDR(3) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_6\, + DRPADDR(2) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_7\, + DRPADDR(1) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_8\, + DRPADDR(0) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_9\, + DRPDI(15) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_10\, + DRPDI(14) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_11\, + DRPDI(13) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_12\, + DRPDI(12) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_13\, + DRPDI(11) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_14\, + DRPDI(10) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_15\, + DRPDI(9) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_16\, + DRPDI(8) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_17\, + DRPDI(7) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_18\, + DRPDI(6) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_19\, + DRPDI(5) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_20\, + DRPDI(4) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_21\, + DRPDI(3) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_22\, + DRPDI(2) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_23\, + DRPDI(1) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_24\, + DRPDI(0) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_25\, + DRP_DO(15) => \pipe_lane[3].gt_wrapper_i_n_20\, + DRP_DO(14) => \pipe_lane[3].gt_wrapper_i_n_21\, + DRP_DO(13) => \pipe_lane[3].gt_wrapper_i_n_22\, + DRP_DO(12) => \pipe_lane[3].gt_wrapper_i_n_23\, + DRP_DO(11) => \pipe_lane[3].gt_wrapper_i_n_24\, + DRP_DO(10) => \pipe_lane[3].gt_wrapper_i_n_25\, + DRP_DO(9) => \pipe_lane[3].gt_wrapper_i_n_26\, + DRP_DO(8) => \pipe_lane[3].gt_wrapper_i_n_27\, + DRP_DO(7) => \pipe_lane[3].gt_wrapper_i_n_28\, + DRP_DO(6) => \pipe_lane[3].gt_wrapper_i_n_29\, + DRP_DO(5) => \pipe_lane[3].gt_wrapper_i_n_30\, + DRP_DO(4) => \pipe_lane[3].gt_wrapper_i_n_31\, + DRP_DO(3) => \pipe_lane[3].gt_wrapper_i_n_32\, + DRP_DO(2) => \pipe_lane[3].gt_wrapper_i_n_33\, + DRP_DO(1) => \pipe_lane[3].gt_wrapper_i_n_34\, + DRP_DO(0) => \pipe_lane[3].gt_wrapper_i_n_35\, + DRP_GTXRESET => rst_gtreset, + DRP_RDY => \pipe_lane[3].gt_wrapper_i_n_2\, + PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(7 downto 6), + PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(3), + PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(3), + PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(3), + PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(63 downto 48), + PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(7 downto 6), + PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(3), + QPLL_QPLLOUTCLK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1\, + QPLL_QPLLOUTREFCLK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2\, + QRST_CPLLLOCK(0) => \pipe_lane[3].gt_wrapper_i_n_1\, + RATE_PHYSTATUS => gt_phystatus_3, + RATE_RXRATEDONE => gt_rxratedone_3, + RATE_TXRATEDONE => gt_txratedone_3, + RST_CPLLRESET => rst_cpllreset, + RXCHBONDO(4 downto 0) => \gt_rxchbondi[3]_0\(4 downto 0), + RXRATE(0) => rate_rate_9(0), + RXSYSCLKSEL(0) => rate_sysclksel_6(0), + SYNC_TXDLYSRESET => sync_txdlysreset_3, + SYNC_TXPHALIGN => sync_txphalign_3, + SYNC_TXPHINIT => sync_txphinit_3, + TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_21(6 downto 0), + TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_15(4 downto 0), + TXPRECURSOR(4 downto 0) => eq_txeq_precursor_15(4 downto 0), + USER_OOBCLK => user_oobclk_3, + USER_RXRESETDONE => gt_rxresetdone_3, + USER_TXRESETDONE => gt_txresetdone_3, + \cplllock_reg1_reg[3]\ => \pipe_lane[3].pipe_drp.pipe_drp_i_n_0\, + \cplllock_reg1_reg[3]_0\ => \pipe_lane[3].pipe_drp.pipe_drp_i_n_1\, + \cplllock_reg1_reg[3]_1\ => \gtx_channel.gtxe2_channel_i_i_6__2_n_0\, + \cplllock_reg1_reg[3]_2\(2 downto 0) => \cplllock_reg1_reg[3]\(2 downto 0), + cpllpd_2 => cpllpd_2, + gt_cpllpdrefclk => gt_cpllpdrefclk, + gt_rx_data_k_wire_filter(1 downto 0) => gt_rx_data_k_wire_filter(7 downto 6), + gt_rx_data_wire_filter(15 downto 0) => gt_rx_data_wire_filter(63 downto 48), + gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(3), + gt_rxcdrlock_3 => gt_rxcdrlock_3, + gt_rxvalid_3 => gt_rxvalid_3, + pci_exp_rxn(0) => pci_exp_rxn(3), + pci_exp_rxp(0) => pci_exp_rxp(3), + pci_exp_txn(0) => pci_exp_txn(3), + pci_exp_txp(0) => pci_exp_txp(3), + pipe_dclk_in => pipe_dclk_in, + pipe_dclk_in_0 => \pipe_lane[3].gt_wrapper_i_n_8\, + pipe_dclk_in_1 => \pipe_lane[3].gt_wrapper_i_n_11\, + pipe_dclk_in_2 => \pipe_lane[3].gt_wrapper_i_n_15\, + pipe_dclk_in_3 => \pipe_lane[3].gt_wrapper_i_n_16\, + pipe_dclk_in_4 => \pipe_lane[3].gt_wrapper_i_n_17\, + pipe_dclk_in_5(2 downto 0) => \^pipe_dclk_in_2\(2 downto 0), + pipe_pclk_in => pipe_pclk_in, + pipe_rxoutclk_out(0) => pipe_rxoutclk_out(3), + pipe_rxusrclk_in => pipe_rxusrclk_in, + pipe_tx_deemph_gt => pipe_tx_deemph_gt, + pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt, + rate_cpllreset_3 => rate_cpllreset_3, + rate_txpmareset_3 => rate_txpmareset_3, + rst_userrdy => rst_userrdy, + rxchbonden_3 => rxchbonden_3, + sys_clk => sys_clk + ); +\pipe_lane[3].pipe_drp.pipe_drp_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_drp_50 + port map ( + D(15) => \pipe_lane[3].gt_wrapper_i_n_20\, + D(14) => \pipe_lane[3].gt_wrapper_i_n_21\, + D(13) => \pipe_lane[3].gt_wrapper_i_n_22\, + D(12) => \pipe_lane[3].gt_wrapper_i_n_23\, + D(11) => \pipe_lane[3].gt_wrapper_i_n_24\, + D(10) => \pipe_lane[3].gt_wrapper_i_n_25\, + D(9) => \pipe_lane[3].gt_wrapper_i_n_26\, + D(8) => \pipe_lane[3].gt_wrapper_i_n_27\, + D(7) => \pipe_lane[3].gt_wrapper_i_n_28\, + D(6) => \pipe_lane[3].gt_wrapper_i_n_29\, + D(5) => \pipe_lane[3].gt_wrapper_i_n_30\, + D(4) => \pipe_lane[3].gt_wrapper_i_n_31\, + D(3) => \pipe_lane[3].gt_wrapper_i_n_32\, + D(2) => \pipe_lane[3].gt_wrapper_i_n_33\, + D(1) => \pipe_lane[3].gt_wrapper_i_n_34\, + D(0) => \pipe_lane[3].gt_wrapper_i_n_35\, + DRPADDR(7) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_2\, + DRPADDR(6) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_3\, + DRPADDR(5) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_4\, + DRPADDR(4) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_5\, + DRPADDR(3) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_6\, + DRPADDR(2) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_7\, + DRPADDR(1) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_8\, + DRPADDR(0) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_9\, + DRPDI(15) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_10\, + DRPDI(14) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_11\, + DRPDI(13) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_12\, + DRPDI(12) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_13\, + DRPDI(11) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_14\, + DRPDI(10) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_15\, + DRPDI(9) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_16\, + DRPDI(8) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_17\, + DRPDI(7) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_18\, + DRPDI(6) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_19\, + DRPDI(5) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_20\, + DRPDI(4) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_21\, + DRPDI(3) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_22\, + DRPDI(2) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_23\, + DRPDI(1) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_24\, + DRPDI(0) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_25\, + DRP_DONE => drp_done_3, + DRP_GTXRESET => rst_gtreset, + DRP_RDY => \pipe_lane[3].gt_wrapper_i_n_2\, + RATE_DRP_START => rate_drp_start_3, + RATE_DRP_X16 => rate_drp_x16_3, + RATE_DRP_X16X20_MODE => rate_drp_x16x20_mode_3, + RST_DCLK_RESET => rst_dclk_reset, + \fsm_reg[1]_0\ => \pipe_lane[3].pipe_drp.pipe_drp_i_n_0\, + \fsm_reg[1]_1\ => \pipe_lane[3].pipe_drp.pipe_drp_i_n_1\, + pipe_dclk_in => pipe_dclk_in, + \rate_reg1_reg[0]_0\(0) => \rate_reg1_reg[0]\(0) + ); +\pipe_lane[3].pipe_eq.pipe_eq_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_eq_51 + port map ( + RST_CPLLRESET => rst_cpllreset, + TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_21(6 downto 0), + TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_15(4 downto 0), + TXPRECURSOR(4 downto 0) => eq_txeq_precursor_15(4 downto 0), + USER_RXEQ_ADAPT_DONE => \pipe_lane[3].pipe_eq.pipe_eq_i_n_17\, + pipe_pclk_in => pipe_pclk_in, + rate_gen3_3 => rate_gen3_3 + ); +\pipe_lane[3].pipe_rate.pipe_rate_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_rate_52 + port map ( + QPLL_QPLLLOCK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0\, + QRST_CPLLLOCK(0) => \pipe_lane[3].gt_wrapper_i_n_1\, + QRST_QPLLPD_IN(0) => rate_qpllpd(3), + QRST_QPLLRESET_IN(0) => rate_qpllreset(3), + RATE_DRP_DONE => drp_done_3, + RATE_DRP_START => rate_drp_start_3, + RATE_DRP_X16 => rate_drp_x16_3, + RATE_DRP_X16X20_MODE => rate_drp_x16x20_mode_3, + RATE_PHYSTATUS => gt_phystatus_3, + RATE_RXRATEDONE => gt_rxratedone_3, + RATE_TXRATEDONE => gt_txratedone_3, + RATE_TXSYNC_DONE => sync_txsync_done_3, + RST_CPLLRESET => rst_cpllreset, + RST_IDLE => \pipe_reset.pipe_reset_i_n_1\, + RST_TXSYNC_START => rst_txsync_start, + RXRATE(0) => rate_rate_9(0), + RXSYSCLKSEL(0) => rate_sysclksel_6(0), + SYNC_RATE_IDLE => rate_idle_3, + SYNC_RXSYNC_START => rate_rxsync_start_3, + SYNC_TXSYNC_START => SYNC_TXSYNC_START0, + USER_RATE_DONE => rate_done_3, + USER_RATE_RXSYNC => rate_rxsync_3, + USER_RESETOVRD_START => rate_resetovrd_start_3, + USER_RXRESETDONE => gt_rxresetdone_3, + USER_TXRESETDONE => gt_txresetdone_3, + \fsm[0]_i_9__2_0\ => p_1_in2_in_5, + \out\ => p_0_in1_in_4, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_pclk_in => pipe_pclk_in, + pipe_pclk_sel_out(0) => \^pipe_pclk_sel_out\(3), + rate_cpllpd_3 => rate_cpllpd_3, + rate_cpllreset_3 => rate_cpllreset_3, + rate_gen3_3 => rate_gen3_3, + \rate_in_reg1_reg[0]_0\(0) => \rate_reg1_reg[0]\(0), + rate_txpmareset_3 => rate_txpmareset_3, + rxchbonden_3 => rxchbonden_3, + user_active_lane_3 => user_active_lane_3 + ); +\pipe_lane[3].pipe_sync_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_sync_53 + port map ( + \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ => p_0_in1_in_4, + Q(2) => sync_txphalign_3, + Q(1) => sync_txphinit_3, + Q(0) => sync_txdlysreset_3, + RST_CPLLRESET => rst_cpllreset, + RST_TXSYNC_DONE(0) => sync_txsync_done_3, + SYNC_GEN3 => rate_gen3_3, + SYNC_RATE_IDLE => rate_idle_3, + SYNC_RXCDRLOCK => user_rxcdrlock_3, + SYNC_RXDLYSRESETDONE => rxdlysresetdone_3, + SYNC_RXPHALIGNDONE_M => \pipe_lane[0].gt_wrapper_i_n_11\, + SYNC_RXPHALIGNDONE_S => rxphaligndone_s_3, + SYNC_RXSYNC_START => rate_rxsync_start_3, + SYNC_TXDLYSRESETDONE => txdlysresetdone_3, + SYNC_TXPHALIGNDONE => txsyncallin, + SYNC_TXPHINITDONE => \pipe_lane[0].pipe_user_i_n_5\, + SYNC_TXSYNC_START => SYNC_TXSYNC_START0, + gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(3), + \out\ => p_1_in2_in_5, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_pclk_in => pipe_pclk_in, + user_active_lane_3 => user_active_lane_3 + ); +\pipe_lane[3].pipe_user_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_user_54 + port map ( + PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(3), + PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(3), + RST_CPLLRESET => rst_cpllreset, + RST_IDLE => \pipe_reset.pipe_reset_i_n_1\, + RST_PHYSTATUS(0) => gt_phystatus_3, + RST_RESETDONE(0) => user_resetdone(3), + RST_RXCDRLOCK(0) => user_rxcdrlock_3, + RST_RXUSRCLK_RESET => rst_rxusrclk_reset, + USER_OOBCLK => user_oobclk_3, + USER_RATE_DONE => rate_done_3, + USER_RATE_IDLE => rate_idle_3, + USER_RATE_RXSYNC => rate_rxsync_3, + USER_RESETOVRD_START => rate_resetovrd_start_3, + USER_RXEQ_ADAPT_DONE => \pipe_lane[3].pipe_eq.pipe_eq_i_n_17\, + USER_RXRESETDONE => gt_rxresetdone_3, + USER_TXRESETDONE => gt_txresetdone_3, + gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(3), + gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(3), + gt_rxcdrlock_3 => gt_rxcdrlock_3, + gt_rxvalid_3 => gt_rxvalid_3, + gt_rxvalid_q_reg => gt_rxvalid_q_reg_2, + \out\ => \pipe_lane[3].pipe_user_i_n_1\, + pipe_oobclk_in => pipe_oobclk_in, + pipe_pclk_in => pipe_pclk_in, + pipe_pclk_sel_out(0) => \^pipe_pclk_sel_out\(3), + pipe_rx3_valid_gt => pipe_rx3_valid_gt, + pipe_rxusrclk_in => pipe_rxusrclk_in, + rate_gen3_3 => rate_gen3_3, + rxstatus_reg1_reg_0(0) => \^pipe_dclk_in_2\(2), + txcompliance_reg2_reg_0 => p_0_in1_in_4, + txelecidle_reg2_reg_0 => p_1_in2_in_5, + user_active_lane_3 => user_active_lane_3, + user_rx_converge(0) => user_rx_converge(3) + ); +\pipe_reset.pipe_reset_i\: entity work.pcie_7x_0_pcie_7x_0_pipe_reset + port map ( + D(3 downto 0) => user_resetdone(3 downto 0), + DRP_GTXRESET => rst_gtreset, + Q(1) => \pipe_reset.pipe_reset_i_n_1\, + Q(0) => rst_txsync_start, + QRST_CPLLLOCK(3) => \pipe_lane[3].gt_wrapper_i_n_1\, + QRST_CPLLLOCK(2) => \pipe_lane[2].gt_wrapper_i_n_1\, + QRST_CPLLLOCK(1) => \pipe_lane[1].gt_wrapper_i_n_1\, + QRST_CPLLLOCK(0) => \pipe_lane[0].gt_wrapper_i_n_1\, + QRST_IDLE => \qpll_reset.qpll_reset_i_n_0\, + RST_CPLLRESET => rst_cpllreset, + RST_DCLK_RESET => rst_dclk_reset, + RST_RXUSRCLK_RESET => rst_rxusrclk_reset, + SS(0) => \pipe_reset.pipe_reset_i_n_0\, + \drp_done_reg1_reg[3]_0\(3) => drp_done_3, + \drp_done_reg1_reg[3]_0\(2) => drp_done_2, + \drp_done_reg1_reg[3]_0\(1) => drp_done_1, + \drp_done_reg1_reg[3]_0\(0) => drp_done_0, + \out\ => reset_n_reg2, + \phystatus_reg1_reg[3]_0\(3) => gt_phystatus_3, + \phystatus_reg1_reg[3]_0\(2) => gt_phystatus_2, + \phystatus_reg1_reg[3]_0\(1) => gt_phystatus_1, + \phystatus_reg1_reg[3]_0\(0) => gt_phystatus_0, + pipe_dclk_in => pipe_dclk_in, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_pclk_in => pipe_pclk_in, + pipe_rxusrclk_in => pipe_rxusrclk_in, + \rate_idle_reg1_reg[3]_0\(3) => rate_idle_3, + \rate_idle_reg1_reg[3]_0\(2) => rate_idle_2, + \rate_idle_reg1_reg[3]_0\(1) => rate_idle_1, + \rate_idle_reg1_reg[3]_0\(0) => rate_idle_0, + rst_userrdy => rst_userrdy, + \rxcdrlock_reg1_reg[3]_0\(3) => user_rxcdrlock_3, + \rxcdrlock_reg1_reg[3]_0\(2) => user_rxcdrlock_2, + \rxcdrlock_reg1_reg[3]_0\(1) => user_rxcdrlock_1, + \rxcdrlock_reg1_reg[3]_0\(0) => user_rxcdrlock_0, + \txsync_done_reg1_reg[3]_0\(3) => sync_txsync_done_3, + \txsync_done_reg1_reg[3]_0\(2) => sync_txsync_done_2, + \txsync_done_reg1_reg[3]_0\(1) => sync_txsync_done_1, + \txsync_done_reg1_reg[3]_0\(0) => sync_txsync_done_0 + ); +\qpll_reset.qpll_reset_i\: entity work.pcie_7x_0_pcie_7x_0_qpll_reset + port map ( + D(3 downto 0) => rate_qpllpd(3 downto 0), + Q(1) => \qpll_reset.qpll_reset_i_n_0\, + Q(0) => qrst_drp_start, + QPLL_QPLLLOCK => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_0\, + QPLL_QPLLPD => qpllpd, + QPLL_QPLLRESET => qrst_qpllreset, + QRST_DRP_DONE(0) => qdrp_done, + SS(0) => \pipe_reset.pipe_reset_i_n_0\, + \cplllock_reg1_reg[3]_0\(3) => \pipe_lane[3].gt_wrapper_i_n_1\, + \cplllock_reg1_reg[3]_0\(2) => \pipe_lane[2].gt_wrapper_i_n_1\, + \cplllock_reg1_reg[3]_0\(1) => \pipe_lane[1].gt_wrapper_i_n_1\, + \cplllock_reg1_reg[3]_0\(0) => \pipe_lane[0].gt_wrapper_i_n_1\, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_pclk_in => pipe_pclk_in, + \qpllreset_in_reg1_reg[3]_0\(3 downto 0) => rate_qpllreset(3 downto 0), + \rate_reg1_reg[0]_0\(0) => \rate_reg1_reg[0]\(0) + ); +reset_n_reg1_reg: unisim.vcomponents.FDCE + port map ( + C => pipe_pclk_in, + CE => '1', + CLR => reset_n_reg1_reg_0, + D => '1', + Q => reset_n_reg1 + ); +reset_n_reg2_reg: unisim.vcomponents.FDCE + port map ( + C => pipe_pclk_in, + CE => '1', + CLR => reset_n_reg1_reg_0, + D => reset_n_reg1, + Q => reset_n_reg2 + ); +rxdlysresetdone_0: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \pipe_lane[1].gt_wrapper_i_n_8\, + I1 => \pipe_lane[0].gt_wrapper_i_n_8\, + I2 => \pipe_lane[3].gt_wrapper_i_n_8\, + I3 => \pipe_lane[2].gt_wrapper_i_n_8\, + O => rxdlysresetdone_3 + ); +rxphaligndone_s_0: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \pipe_lane[1].gt_wrapper_i_n_11\, + I1 => \pipe_lane[3].gt_wrapper_i_n_11\, + I2 => \pipe_lane[2].gt_wrapper_i_n_11\, + O => rxphaligndone_s_3 + ); +txdlysresetdone_0: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \pipe_lane[1].gt_wrapper_i_n_15\, + I1 => \pipe_lane[0].gt_wrapper_i_n_15\, + I2 => \pipe_lane[3].gt_wrapper_i_n_15\, + I3 => \pipe_lane[2].gt_wrapper_i_n_15\, + O => txdlysresetdone_3 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_gt_top is + port ( + pipe_rx0_valid_gt : out STD_LOGIC; + phy_rdy_n : out STD_LOGIC; + pipe_rx1_valid_gt : out STD_LOGIC; + pipe_rx2_valid_gt : out STD_LOGIC; + pipe_rx3_valid_gt : out STD_LOGIC; + gt_rx_phy_status_q_reg : out STD_LOGIC; + gt_rxelecidle_q_reg : out STD_LOGIC; + gt_rx_phy_status_q_reg_0 : out STD_LOGIC; + gt_rxelecidle_q_reg_0 : out STD_LOGIC; + gt_rx_phy_status_q_reg_1 : out STD_LOGIC; + gt_rxelecidle_q_reg_1 : out STD_LOGIC; + gt_rx_phy_status_q : out STD_LOGIC; + gt_rxelecidle_q : out STD_LOGIC; + sys_rst_n : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \gt_rxdata_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \gt_rxdata_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \gt_rxdata_q_reg[15]_1\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \gt_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gt_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gt_rx_status_q_reg[2]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gt_rx_status_q_reg[2]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + gt_rxvalid_q_reg : out STD_LOGIC_VECTOR ( 1 downto 0 ); + gt_rxvalid_q_reg_0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + gt_rxvalid_q_reg_1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); + USER_RATE_GEN3 : out STD_LOGIC; + pci_exp_txn : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_txp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_txoutclk_out : out STD_LOGIC; + sys_rst_n_0 : out STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + pipe_mmcm_lock_in : in STD_LOGIC; + pl_ltssm_state : in STD_LOGIC_VECTOR ( 5 downto 0 ); + pipe_rxusrclk_in : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + \rate_reg1_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sys_clk : in STD_LOGIC; + pipe_oobclk_in : in STD_LOGIC; + PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_rxn : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_rxp : in STD_LOGIC_VECTOR ( 3 downto 0 ); + PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_tx_deemph_gt : in STD_LOGIC; + pipe_tx_rcvr_det_gt : in STD_LOGIC; + PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \cplllock_reg1_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + PIPE_TXDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 7 downto 0 ); + reset_n_reg1_reg : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_gt_top; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_gt_top is + signal gt_rx_data_k_wire_filter : STD_LOGIC_VECTOR ( 13 downto 0 ); + signal gt_rx_data_wire_filter : STD_LOGIC_VECTOR ( 111 downto 0 ); + signal gt_rx_elec_idle_wire_filter : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal gt_rx_phy_status_wire_filter : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\ : STD_LOGIC; + signal \^phy_rdy_n\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i/CPLLPD0\ : STD_LOGIC; + signal \pipe_lane[0].gt_wrapper_i/cpllpd\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i/CPLLPD0\ : STD_LOGIC; + signal \pipe_lane[1].gt_wrapper_i/cpllpd\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i/CPLLPD0\ : STD_LOGIC; + signal \pipe_lane[2].gt_wrapper_i/cpllpd\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i/CPLLPD0\ : STD_LOGIC; + signal \pipe_lane[3].gt_wrapper_i/cpllpd\ : STD_LOGIC; + signal \^pipe_rx0_valid_gt\ : STD_LOGIC; + signal \^pipe_rx1_valid_gt\ : STD_LOGIC; + signal \^pipe_rx2_valid_gt\ : STD_LOGIC; + signal \^pipe_rx3_valid_gt\ : STD_LOGIC; + signal pipe_wrapper_i_n_100 : STD_LOGIC; + signal pipe_wrapper_i_n_101 : STD_LOGIC; + signal pipe_wrapper_i_n_102 : STD_LOGIC; + signal pipe_wrapper_i_n_103 : STD_LOGIC; + signal pipe_wrapper_i_n_104 : STD_LOGIC; + signal pipe_wrapper_i_n_105 : STD_LOGIC; + signal pipe_wrapper_i_n_106 : STD_LOGIC; + signal pipe_wrapper_i_n_107 : STD_LOGIC; + signal pipe_wrapper_i_n_108 : STD_LOGIC; + signal pipe_wrapper_i_n_109 : STD_LOGIC; + signal pipe_wrapper_i_n_110 : STD_LOGIC; + signal pipe_wrapper_i_n_111 : STD_LOGIC; + signal pipe_wrapper_i_n_112 : STD_LOGIC; + signal pipe_wrapper_i_n_113 : STD_LOGIC; + signal pipe_wrapper_i_n_25 : STD_LOGIC; + signal pipe_wrapper_i_n_26 : STD_LOGIC; + signal pipe_wrapper_i_n_27 : STD_LOGIC; + signal pl_ltssm_state_q : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal rate_cpllpd_0 : STD_LOGIC; + signal rate_cpllpd_1 : STD_LOGIC; + signal rate_cpllpd_2 : STD_LOGIC; + signal rate_cpllpd_3 : STD_LOGIC; + signal reg_clock_locked : STD_LOGIC; + signal reg_clock_locked_i_1_n_0 : STD_LOGIC; + signal \^sys_rst_n_0\ : STD_LOGIC; +begin + phy_rdy_n <= \^phy_rdy_n\; + pipe_rx0_valid_gt <= \^pipe_rx0_valid_gt\; + pipe_rx1_valid_gt <= \^pipe_rx1_valid_gt\; + pipe_rx2_valid_gt <= \^pipe_rx2_valid_gt\; + pipe_rx3_valid_gt <= \^pipe_rx3_valid_gt\; + sys_rst_n_0 <= \^sys_rst_n_0\; +\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst\: entity work.pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x + port map ( + D(1 downto 0) => D(1 downto 0), + PIPE_RXDATA(15 downto 0) => gt_rx_data_wire_filter(15 downto 0), + PIPE_RXDATAK(1 downto 0) => gt_rx_data_k_wire_filter(1 downto 0), + PIPE_RXELECIDLE(0) => gt_rx_elec_idle_wire_filter(0), + PIPE_RXSTATUS(2) => pipe_wrapper_i_n_25, + PIPE_RXSTATUS(1) => pipe_wrapper_i_n_26, + PIPE_RXSTATUS(0) => pipe_wrapper_i_n_27, + Q(15 downto 0) => Q(15 downto 0), + SR(0) => \^phy_rdy_n\, + gt_rx_phy_status_q => gt_rx_phy_status_q, + gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(0), + \gt_rx_status_q_reg[0]_0\(5 downto 0) => pl_ltssm_state_q(5 downto 0), + \gt_rx_status_q_reg[2]_0\(2 downto 0) => \gt_rx_status_q_reg[2]_2\(2 downto 0), + gt_rxelecidle_q => gt_rxelecidle_q, + gt_rxvalid_q_reg_0 => \^pipe_rx0_valid_gt\, + gt_rxvalid_q_reg_1 => pipe_wrapper_i_n_110, + pipe_pclk_in => pipe_pclk_in, + \pl_ltssm_state_q_reg[5]\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\ + ); +\gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst\: entity work.pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_34 + port map ( + PIPE_RXDATA(15 downto 0) => gt_rx_data_wire_filter(47 downto 32), + PIPE_RXDATAK(1 downto 0) => gt_rx_data_k_wire_filter(5 downto 4), + PIPE_RXELECIDLE(0) => gt_rx_elec_idle_wire_filter(1), + PIPE_RXSTATUS(2) => pipe_wrapper_i_n_100, + PIPE_RXSTATUS(1) => pipe_wrapper_i_n_101, + PIPE_RXSTATUS(0) => pipe_wrapper_i_n_102, + Q(15 downto 0) => \gt_rxdata_q_reg[15]\(15 downto 0), + SR(0) => \^phy_rdy_n\, + gt_rx_phy_status_q_reg_0 => gt_rx_phy_status_q_reg, + gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(1), + \gt_rx_status_q_reg[0]_0\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\, + \gt_rx_status_q_reg[2]_0\(2 downto 0) => \gt_rx_status_q_reg[2]\(2 downto 0), + gt_rxelecidle_q_reg_0 => gt_rxelecidle_q_reg, + gt_rxvalid_q_reg_0 => \^pipe_rx1_valid_gt\, + gt_rxvalid_q_reg_1(1 downto 0) => gt_rxvalid_q_reg(1 downto 0), + gt_rxvalid_q_reg_2 => pipe_wrapper_i_n_111, + pipe_pclk_in => pipe_pclk_in + ); +\gt_rx_valid_filter[2].GT_RX_VALID_FILTER_7x_inst\: entity work.pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_35 + port map ( + PIPE_RXDATA(15 downto 0) => gt_rx_data_wire_filter(79 downto 64), + PIPE_RXDATAK(1 downto 0) => gt_rx_data_k_wire_filter(9 downto 8), + PIPE_RXELECIDLE(0) => gt_rx_elec_idle_wire_filter(2), + PIPE_RXSTATUS(2) => pipe_wrapper_i_n_103, + PIPE_RXSTATUS(1) => pipe_wrapper_i_n_104, + PIPE_RXSTATUS(0) => pipe_wrapper_i_n_105, + Q(15 downto 0) => \gt_rxdata_q_reg[15]_0\(15 downto 0), + SR(0) => \^phy_rdy_n\, + gt_rx_phy_status_q_reg_0 => gt_rx_phy_status_q_reg_0, + gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(2), + \gt_rx_status_q_reg[0]_0\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\, + \gt_rx_status_q_reg[2]_0\(2 downto 0) => \gt_rx_status_q_reg[2]_0\(2 downto 0), + gt_rxelecidle_q_reg_0 => gt_rxelecidle_q_reg_0, + gt_rxvalid_q_reg_0 => \^pipe_rx2_valid_gt\, + gt_rxvalid_q_reg_1(1 downto 0) => gt_rxvalid_q_reg_0(1 downto 0), + gt_rxvalid_q_reg_2 => pipe_wrapper_i_n_112, + pipe_pclk_in => pipe_pclk_in + ); +\gt_rx_valid_filter[3].GT_RX_VALID_FILTER_7x_inst\: entity work.pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_36 + port map ( + PIPE_RXDATA(15 downto 0) => gt_rx_data_wire_filter(111 downto 96), + PIPE_RXDATAK(1 downto 0) => gt_rx_data_k_wire_filter(13 downto 12), + PIPE_RXELECIDLE(0) => gt_rx_elec_idle_wire_filter(3), + PIPE_RXSTATUS(2) => pipe_wrapper_i_n_106, + PIPE_RXSTATUS(1) => pipe_wrapper_i_n_107, + PIPE_RXSTATUS(0) => pipe_wrapper_i_n_108, + Q(15 downto 0) => \gt_rxdata_q_reg[15]_1\(15 downto 0), + SR(0) => \^phy_rdy_n\, + gt_rx_phy_status_q_reg_0 => gt_rx_phy_status_q_reg_1, + gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(3), + \gt_rx_status_q_reg[0]_0\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\, + \gt_rx_status_q_reg[2]_0\(2 downto 0) => \gt_rx_status_q_reg[2]_1\(2 downto 0), + gt_rxelecidle_q_reg_0 => gt_rxelecidle_q_reg_1, + gt_rxvalid_q_reg_0 => \^pipe_rx3_valid_gt\, + gt_rxvalid_q_reg_1(1 downto 0) => gt_rxvalid_q_reg_1(1 downto 0), + gt_rxvalid_q_reg_2 => pipe_wrapper_i_n_113, + pipe_pclk_in => pipe_pclk_in + ); +\gtx_channel.gtxe2_channel_i_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \pipe_lane[0].gt_wrapper_i/cpllpd\, + I1 => rate_cpllpd_0, + O => \pipe_lane[0].gt_wrapper_i/CPLLPD0\ + ); +\gtx_channel.gtxe2_channel_i_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \pipe_lane[1].gt_wrapper_i/cpllpd\, + I1 => rate_cpllpd_1, + O => \pipe_lane[1].gt_wrapper_i/CPLLPD0\ + ); +\gtx_channel.gtxe2_channel_i_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \pipe_lane[2].gt_wrapper_i/cpllpd\, + I1 => rate_cpllpd_2, + O => \pipe_lane[2].gt_wrapper_i/CPLLPD0\ + ); +\gtx_channel.gtxe2_channel_i_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \pipe_lane[3].gt_wrapper_i/cpllpd\, + I1 => rate_cpllpd_3, + O => \pipe_lane[3].gt_wrapper_i/CPLLPD0\ + ); +pcie_block_i_i_29: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^phy_rdy_n\, + O => sys_rst_n + ); +phy_rdy_n_int_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_pclk_in, + CE => '1', + D => pipe_wrapper_i_n_109, + Q => \^phy_rdy_n\, + R => '0' + ); +pipe_wrapper_i: entity work.pcie_7x_0_pcie_7x_0_pipe_wrapper + port map ( + CPLLPD0 => \pipe_lane[0].gt_wrapper_i/CPLLPD0\, + CPLLPD0_3 => \pipe_lane[1].gt_wrapper_i/CPLLPD0\, + CPLLPD0_4 => \pipe_lane[2].gt_wrapper_i/CPLLPD0\, + CPLLPD0_5 => \pipe_lane[3].gt_wrapper_i/CPLLPD0\, + PIPE_POWERDOWN(7 downto 0) => PIPE_POWERDOWN(7 downto 0), + PIPE_RXCHANISALIGNED(3 downto 0) => PIPE_RXCHANISALIGNED(3 downto 0), + PIPE_RXPOLARITY(3 downto 0) => PIPE_RXPOLARITY(3 downto 0), + PIPE_RXSTATUS(2) => pipe_wrapper_i_n_25, + PIPE_RXSTATUS(1) => pipe_wrapper_i_n_26, + PIPE_RXSTATUS(0) => pipe_wrapper_i_n_27, + PIPE_TXCOMPLIANCE(3 downto 0) => PIPE_TXCOMPLIANCE(3 downto 0), + PIPE_TXDATA(63 downto 0) => PIPE_TXDATA(63 downto 0), + PIPE_TXDATAK(7 downto 0) => PIPE_TXDATAK(7 downto 0), + PIPE_TXELECIDLE(3 downto 0) => PIPE_TXELECIDLE(3 downto 0), + \cplllock_reg1_reg[3]\(2 downto 0) => \cplllock_reg1_reg[3]\(2 downto 0), + cpllpd => \pipe_lane[0].gt_wrapper_i/cpllpd\, + cpllpd_0 => \pipe_lane[1].gt_wrapper_i/cpllpd\, + cpllpd_1 => \pipe_lane[2].gt_wrapper_i/cpllpd\, + cpllpd_2 => \pipe_lane[3].gt_wrapper_i/cpllpd\, + gen3_reg => USER_RATE_GEN3, + gt_rx_data_k_wire_filter(7 downto 6) => gt_rx_data_k_wire_filter(13 downto 12), + gt_rx_data_k_wire_filter(5 downto 4) => gt_rx_data_k_wire_filter(9 downto 8), + gt_rx_data_k_wire_filter(3 downto 2) => gt_rx_data_k_wire_filter(5 downto 4), + gt_rx_data_k_wire_filter(1 downto 0) => gt_rx_data_k_wire_filter(1 downto 0), + gt_rx_data_wire_filter(63 downto 48) => gt_rx_data_wire_filter(111 downto 96), + gt_rx_data_wire_filter(47 downto 32) => gt_rx_data_wire_filter(79 downto 64), + gt_rx_data_wire_filter(31 downto 16) => gt_rx_data_wire_filter(47 downto 32), + gt_rx_data_wire_filter(15 downto 0) => gt_rx_data_wire_filter(15 downto 0), + gt_rx_elec_idle_wire_filter(3 downto 0) => gt_rx_elec_idle_wire_filter(3 downto 0), + gt_rx_phy_status_wire_filter(3 downto 0) => gt_rx_phy_status_wire_filter(3 downto 0), + gt_rxvalid_q_reg => pipe_wrapper_i_n_110, + gt_rxvalid_q_reg_0 => pipe_wrapper_i_n_111, + gt_rxvalid_q_reg_1 => pipe_wrapper_i_n_112, + gt_rxvalid_q_reg_2 => pipe_wrapper_i_n_113, + pci_exp_rxn(3 downto 0) => pci_exp_rxn(3 downto 0), + pci_exp_rxp(3 downto 0) => pci_exp_rxp(3 downto 0), + pci_exp_txn(3 downto 0) => pci_exp_txn(3 downto 0), + pci_exp_txp(3 downto 0) => pci_exp_txp(3 downto 0), + pipe_dclk_in => pipe_dclk_in, + pipe_dclk_in_0(2) => pipe_wrapper_i_n_100, + pipe_dclk_in_0(1) => pipe_wrapper_i_n_101, + pipe_dclk_in_0(0) => pipe_wrapper_i_n_102, + pipe_dclk_in_1(2) => pipe_wrapper_i_n_103, + pipe_dclk_in_1(1) => pipe_wrapper_i_n_104, + pipe_dclk_in_1(0) => pipe_wrapper_i_n_105, + pipe_dclk_in_2(2) => pipe_wrapper_i_n_106, + pipe_dclk_in_2(1) => pipe_wrapper_i_n_107, + pipe_dclk_in_2(0) => pipe_wrapper_i_n_108, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_oobclk_in => pipe_oobclk_in, + pipe_pclk_in => pipe_pclk_in, + pipe_pclk_sel_out(3 downto 0) => pipe_pclk_sel_out(3 downto 0), + pipe_rx0_valid_gt => \^pipe_rx0_valid_gt\, + pipe_rx1_valid_gt => \^pipe_rx1_valid_gt\, + pipe_rx2_valid_gt => \^pipe_rx2_valid_gt\, + pipe_rx3_valid_gt => \^pipe_rx3_valid_gt\, + pipe_rxoutclk_out(3 downto 0) => pipe_rxoutclk_out(3 downto 0), + pipe_rxusrclk_in => pipe_rxusrclk_in, + pipe_tx_deemph_gt => pipe_tx_deemph_gt, + pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt, + pipe_txoutclk_out => pipe_txoutclk_out, + rate_cpllpd_0 => rate_cpllpd_0, + rate_cpllpd_1 => rate_cpllpd_1, + rate_cpllpd_2 => rate_cpllpd_2, + rate_cpllpd_3 => rate_cpllpd_3, + \rate_reg1_reg[0]\(0) => \rate_reg1_reg[0]\(0), + reg_clock_locked => reg_clock_locked, + reg_clock_locked_reg => pipe_wrapper_i_n_109, + reset_n_reg1_reg_0 => \^sys_rst_n_0\, + sys_clk => sys_clk + ); +\pl_ltssm_state_q_reg[0]\: unisim.vcomponents.FDCE + port map ( + C => pipe_pclk_in, + CE => '1', + CLR => reg_clock_locked_i_1_n_0, + D => pl_ltssm_state(0), + Q => pl_ltssm_state_q(0) + ); +\pl_ltssm_state_q_reg[1]\: unisim.vcomponents.FDCE + port map ( + C => pipe_pclk_in, + CE => '1', + CLR => reg_clock_locked_i_1_n_0, + D => pl_ltssm_state(1), + Q => pl_ltssm_state_q(1) + ); +\pl_ltssm_state_q_reg[2]\: unisim.vcomponents.FDCE + port map ( + C => pipe_pclk_in, + CE => '1', + CLR => reg_clock_locked_i_1_n_0, + D => pl_ltssm_state(2), + Q => pl_ltssm_state_q(2) + ); +\pl_ltssm_state_q_reg[3]\: unisim.vcomponents.FDCE + port map ( + C => pipe_pclk_in, + CE => '1', + CLR => reg_clock_locked_i_1_n_0, + D => pl_ltssm_state(3), + Q => pl_ltssm_state_q(3) + ); +\pl_ltssm_state_q_reg[4]\: unisim.vcomponents.FDCE + port map ( + C => pipe_pclk_in, + CE => '1', + CLR => reg_clock_locked_i_1_n_0, + D => pl_ltssm_state(4), + Q => pl_ltssm_state_q(4) + ); +\pl_ltssm_state_q_reg[5]\: unisim.vcomponents.FDCE + port map ( + C => pipe_pclk_in, + CE => '1', + CLR => reg_clock_locked_i_1_n_0, + D => pl_ltssm_state(5), + Q => pl_ltssm_state_q(5) + ); +pl_phy_lnk_up_q_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => reset_n_reg1_reg, + O => \^sys_rst_n_0\ + ); +reg_clock_locked_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => pipe_mmcm_lock_in, + O => reg_clock_locked_i_1_n_0 + ); +reg_clock_locked_reg: unisim.vcomponents.FDCE + port map ( + C => pipe_pclk_in, + CE => '1', + CLR => reg_clock_locked_i_1_n_0, + D => '1', + Q => reg_clock_locked + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_bram_top_7x is + port ( + rdata : out STD_LOGIC_VECTOR ( 68 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 67 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + mim_tx_wen : in STD_LOGIC; + mim_tx_ren : in STD_LOGIC; + MIMTXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMTXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wdata : in STD_LOGIC_VECTOR ( 68 downto 0 ); + mim_rx_wen : in STD_LOGIC; + mim_rx_ren : in STD_LOGIC; + MIMRXWADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + MIMRXRADDR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 67 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_pcie_bram_top_7x; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_bram_top_7x is +begin +pcie_brams_rx: entity work.pcie_7x_0_pcie_7x_0_pcie_brams_7x + port map ( + MIMRXRADDR(11 downto 0) => MIMRXRADDR(11 downto 0), + MIMRXWADDR(11 downto 0) => MIMRXWADDR(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(67 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(67 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(67 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(67 downto 0), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + pipe_userclk1_in => pipe_userclk1_in + ); +pcie_brams_tx: entity work.pcie_7x_0_pcie_7x_0_pcie_brams_7x_3 + port map ( + MIMTXRADDR(11 downto 0) => MIMTXRADDR(11 downto 0), + MIMTXWADDR(11 downto 0) => MIMTXWADDR(11 downto 0), + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(68 downto 0) => rdata(68 downto 0), + wdata(68 downto 0) => wdata(68 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_7x is + port ( + user_reset_int_reg : out STD_LOGIC; + src_in : out STD_LOGIC; + cfg_mgmt_rd_wr_done : out STD_LOGIC; + cfg_err_aer_headerlog_set : out STD_LOGIC; + cfg_err_cpl_rdy : out STD_LOGIC; + cfg_interrupt_rdy : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + cfg_msg_received : out STD_LOGIC; + cfg_received_func_lvl_rst : out STD_LOGIC; + trn_in_packet_reg : out STD_LOGIC; + trn_reof : out STD_LOGIC; + trn_rsof : out STD_LOGIC; + trn_rsrc_dsc : out STD_LOGIC; + ppm_L1_thrtl_reg : out STD_LOGIC; + cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 ); + dsc_detect : out STD_LOGIC; + rsrc_rdy_filtered : out STD_LOGIC; + trn_rsrc_dsc_prev0 : out STD_LOGIC; + tcfg_req_trig : out STD_LOGIC; + trn_tcfg_req : out STD_LOGIC; + pcie_drp_clk_0 : out STD_LOGIC; + trn_tbuf_av : out STD_LOGIC_VECTOR ( 5 downto 0 ); + tbuf_av_min_trig : out STD_LOGIC; + lnk_up_thrtl_reg : out STD_LOGIC; + trn_tdst_rdy : out STD_LOGIC; + cfg_aer_ecrc_check_en : out STD_LOGIC; + cfg_aer_ecrc_gen_en : out STD_LOGIC; + cfg_aer_rooterr_corr_err_received : out STD_LOGIC; + cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_fatal_err_received : out STD_LOGIC; + cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC; + cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC; + cfg_bridge_serr_en : out STD_LOGIC; + cfg_command : out STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_dcommand2 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + cfg_dcommand : out STD_LOGIC_VECTOR ( 14 downto 0 ); + cfg_dstatus : out STD_LOGIC_VECTOR ( 3 downto 0 ); + cfg_interrupt_msienable : out STD_LOGIC; + cfg_interrupt_msixenable : out STD_LOGIC; + cfg_interrupt_msixfm : out STD_LOGIC; + cfg_lcommand : out STD_LOGIC_VECTOR ( 10 downto 0 ); + cfg_lstatus : out STD_LOGIC_VECTOR ( 9 downto 0 ); + cfg_msg_received_assert_int_a : out STD_LOGIC; + cfg_msg_received_assert_int_b : out STD_LOGIC; + cfg_msg_received_assert_int_c : out STD_LOGIC; + cfg_msg_received_assert_int_d : out STD_LOGIC; + cfg_msg_received_deassert_int_a : out STD_LOGIC; + cfg_msg_received_deassert_int_b : out STD_LOGIC; + cfg_msg_received_deassert_int_c : out STD_LOGIC; + cfg_msg_received_deassert_int_d : out STD_LOGIC; + cfg_msg_received_err_cor : out STD_LOGIC; + cfg_msg_received_err_fatal : out STD_LOGIC; + cfg_msg_received_err_non_fatal : out STD_LOGIC; + cfg_msg_received_pm_as_nak : out STD_LOGIC; + cfg_to_turnoff : out STD_LOGIC; + cfg_msg_received_pme_to_ack : out STD_LOGIC; + cfg_msg_received_pm_pme : out STD_LOGIC; + cfg_msg_received_setslotpowerlimit : out STD_LOGIC; + cfg_pmcsr_pme_en : out STD_LOGIC; + cfg_pmcsr_pme_status : out STD_LOGIC; + cfg_root_control_pme_int_en : out STD_LOGIC; + cfg_root_control_syserr_corr_err_en : out STD_LOGIC; + cfg_root_control_syserr_fatal_err_en : out STD_LOGIC; + cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC; + cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC; + pcie_drp_rdy : out STD_LOGIC; + pipe_rx0_polarity : out STD_LOGIC; + pipe_rx1_polarity : out STD_LOGIC; + pipe_rx2_polarity : out STD_LOGIC; + pipe_rx3_polarity : out STD_LOGIC; + pipe_tx0_compliance : out STD_LOGIC; + pipe_tx0_elec_idle : out STD_LOGIC; + pipe_tx1_compliance : out STD_LOGIC; + pipe_tx1_elec_idle : out STD_LOGIC; + pipe_tx2_compliance : out STD_LOGIC; + pipe_tx2_elec_idle : out STD_LOGIC; + pipe_tx3_compliance : out STD_LOGIC; + pipe_tx3_elec_idle : out STD_LOGIC; + pipe_tx_deemph : out STD_LOGIC; + pipe_tx_rate : out STD_LOGIC; + pipe_tx_rcvr_det : out STD_LOGIC; + pl_directed_change_done : out STD_LOGIC; + pl_link_gen2_cap : out STD_LOGIC; + pl_link_partner_gen2_supported : out STD_LOGIC; + pl_link_upcfg_cap : out STD_LOGIC; + pl_received_hot_rst : out STD_LOGIC; + pl_sel_lnk_rate : out STD_LOGIC; + trn_lnk_up : out STD_LOGIC; + trn_recrc_err : out STD_LOGIC; + trn_rerrfwd : out STD_LOGIC; + tx_err_drop : out STD_LOGIC; + fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 ); + pcie_drp_clk_1 : out STD_LOGIC_VECTOR ( 63 downto 0 ); + cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); + pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 ); + pipe_tx0_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); + pipe_tx1_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); + pipe_tx2_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); + pipe_tx3_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pipe_tx0_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pipe_tx0_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pipe_tx1_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pipe_tx1_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pipe_tx2_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pipe_tx2_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pipe_tx3_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pipe_tx3_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pcie_drp_clk_2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pipe_tx_margin : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); + pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 ); + cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 ); + cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 ); + trn_rbar_hit : out STD_LOGIC_VECTOR ( 6 downto 0 ); + bridge_reset_int : in STD_LOGIC; + pl_phy_lnk_up : in STD_LOGIC; + cfg_trn_pending : in STD_LOGIC; + cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC; + cfg_mgmt_wr_readonly : in STD_LOGIC; + cfg_mgmt_wr_en : in STD_LOGIC; + cfg_mgmt_rd_en : in STD_LOGIC; + cfg_err_malformed : in STD_LOGIC; + cfg_err_cor : in STD_LOGIC; + cfg_err_ur : in STD_LOGIC; + cfg_err_ecrc : in STD_LOGIC; + cfg_err_cpl_timeout : in STD_LOGIC; + cfg_err_cpl_abort : in STD_LOGIC; + cfg_err_cpl_unexpect : in STD_LOGIC; + cfg_err_poisoned : in STD_LOGIC; + cfg_err_atomic_egress_blocked : in STD_LOGIC; + cfg_err_mc_blocked : in STD_LOGIC; + cfg_err_internal_uncor : in STD_LOGIC; + cfg_err_internal_cor : in STD_LOGIC; + cfg_err_posted : in STD_LOGIC; + cfg_err_locked : in STD_LOGIC; + cfg_err_norecovery : in STD_LOGIC; + cfg_interrupt : in STD_LOGIC; + cfg_interrupt_assert : in STD_LOGIC; + cfg_interrupt_stat : in STD_LOGIC; + cfg_pm_halt_aspm_l0s : in STD_LOGIC; + cfg_pm_halt_aspm_l1 : in STD_LOGIC; + cfg_pm_force_state_en : in STD_LOGIC; + cfg_pm_wake : in STD_LOGIC; + trn_in_packet : in STD_LOGIC; + trn_rdst_rdy : in STD_LOGIC; + ppm_L1_trig : in STD_LOGIC; + ppm_L1_thrtl : in STD_LOGIC; + trn_rsrc_dsc_d : in STD_LOGIC; + reg_dsc_detect : in STD_LOGIC; + reg_tcfg_gnt : in STD_LOGIC; + lnk_up_thrtl : in STD_LOGIC; + \out\ : in STD_LOGIC; + pipe_userclk1_in : in STD_LOGIC; + cfg_pm_turnoff_ok_n : in STD_LOGIC; + pcie_drp_clk : in STD_LOGIC; + pcie_drp_en : in STD_LOGIC; + pcie_drp_we : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + pipe_rx0_chanisaligned : in STD_LOGIC; + pipe_rx0_elec_idle : in STD_LOGIC; + pipe_rx0_phy_status : in STD_LOGIC; + pipe_rx0_valid : in STD_LOGIC; + pipe_rx1_chanisaligned : in STD_LOGIC; + pipe_rx1_elec_idle : in STD_LOGIC; + pipe_rx1_phy_status : in STD_LOGIC; + pipe_rx1_valid : in STD_LOGIC; + pipe_rx2_chanisaligned : in STD_LOGIC; + pipe_rx2_elec_idle : in STD_LOGIC; + pipe_rx2_phy_status : in STD_LOGIC; + pipe_rx2_valid : in STD_LOGIC; + pipe_rx3_chanisaligned : in STD_LOGIC; + pipe_rx3_elec_idle : in STD_LOGIC; + pipe_rx3_phy_status : in STD_LOGIC; + pipe_rx3_valid : in STD_LOGIC; + pl_directed_link_auton : in STD_LOGIC; + pl_directed_link_speed : in STD_LOGIC; + pl_downstream_deemph_source : in STD_LOGIC; + pl_transmit_hot_rst : in STD_LOGIC; + pl_upstream_prefer_deemph : in STD_LOGIC; + sys_rst_n : in STD_LOGIC; + rx_np_ok : in STD_LOGIC; + rx_np_req : in STD_LOGIC; + trn_tcfg_gnt : in STD_LOGIC; + cfg_aer_ecrc_check_en_0 : in STD_LOGIC_VECTOR ( 3 downto 0 ); + trn_teof : in STD_LOGIC; + trn_tsof : in STD_LOGIC; + trn_tsrc_rdy : in STD_LOGIC; + pipe_userclk2_in : in STD_LOGIC; + cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 ); + trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); + pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_aer_ecrc_check_en_1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_aer_ecrc_check_en_2 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_aer_ecrc_check_en_3 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_aer_ecrc_check_en_4 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_aer_ecrc_check_en_5 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_aer_ecrc_check_en_6 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_aer_ecrc_check_en_7 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 ); + trn_trem : in STD_LOGIC_VECTOR ( 0 to 0 ); + cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_aer_ecrc_check_en_8 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_aer_ecrc_check_en_9 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_aer_ecrc_check_en_10 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_aer_ecrc_check_en_11 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); + cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); + cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); + cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); + pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_pcie_7x; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_7x is + signal cfg_err_aer_headerlog_set_n : STD_LOGIC; + signal cfg_err_cpl_rdy_n : STD_LOGIC; + signal cfg_interrupt_rdy_n : STD_LOGIC; + signal cfg_mgmt_rd_wr_done_n : STD_LOGIC; + signal \^cfg_msg_received\ : STD_LOGIC; + signal \^cfg_pcie_link_state\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal cfg_received_func_lvl_rst_n : STD_LOGIC; + signal mim_rx_raddr : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal mim_rx_rdata : STD_LOGIC_VECTOR ( 67 downto 0 ); + signal mim_rx_ren : STD_LOGIC; + signal mim_rx_waddr : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal mim_rx_wdata : STD_LOGIC_VECTOR ( 67 downto 0 ); + signal mim_rx_wen : STD_LOGIC; + signal mim_tx_raddr : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal mim_tx_rdata : STD_LOGIC_VECTOR ( 68 downto 0 ); + signal mim_tx_ren : STD_LOGIC; + signal mim_tx_waddr : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal mim_tx_wdata : STD_LOGIC_VECTOR ( 68 downto 0 ); + signal mim_tx_wen : STD_LOGIC; + signal pcie_block_i_i_10_n_0 : STD_LOGIC; + signal pcie_block_i_i_11_n_0 : STD_LOGIC; + signal pcie_block_i_i_12_n_0 : STD_LOGIC; + signal pcie_block_i_i_13_n_0 : STD_LOGIC; + signal pcie_block_i_i_14_n_0 : STD_LOGIC; + signal pcie_block_i_i_15_n_0 : STD_LOGIC; + signal pcie_block_i_i_16_n_0 : STD_LOGIC; + signal pcie_block_i_i_17_n_0 : STD_LOGIC; + signal pcie_block_i_i_18_n_0 : STD_LOGIC; + signal pcie_block_i_i_19_n_0 : STD_LOGIC; + signal pcie_block_i_i_1_n_0 : STD_LOGIC; + signal pcie_block_i_i_20_n_0 : STD_LOGIC; + signal pcie_block_i_i_21_n_0 : STD_LOGIC; + signal pcie_block_i_i_22_n_0 : STD_LOGIC; + signal pcie_block_i_i_23_n_0 : STD_LOGIC; + signal pcie_block_i_i_24_n_0 : STD_LOGIC; + signal pcie_block_i_i_25_n_0 : STD_LOGIC; + signal pcie_block_i_i_27_n_0 : STD_LOGIC; + signal pcie_block_i_i_28_n_0 : STD_LOGIC; + signal pcie_block_i_i_2_n_0 : STD_LOGIC; + signal pcie_block_i_i_3_n_0 : STD_LOGIC; + signal pcie_block_i_i_4_n_0 : STD_LOGIC; + signal pcie_block_i_i_5_n_0 : STD_LOGIC; + signal pcie_block_i_i_6_n_0 : STD_LOGIC; + signal pcie_block_i_i_7_n_0 : STD_LOGIC; + signal pcie_block_i_i_8_n_0 : STD_LOGIC; + signal pcie_block_i_i_9_n_0 : STD_LOGIC; + signal pcie_block_i_n_100 : STD_LOGIC; + signal pcie_block_i_n_101 : STD_LOGIC; + signal pcie_block_i_n_102 : STD_LOGIC; + signal pcie_block_i_n_103 : STD_LOGIC; + signal pcie_block_i_n_104 : STD_LOGIC; + signal pcie_block_i_n_105 : STD_LOGIC; + signal pcie_block_i_n_106 : STD_LOGIC; + signal pcie_block_i_n_107 : STD_LOGIC; + signal pcie_block_i_n_108 : STD_LOGIC; + signal pcie_block_i_n_1097 : STD_LOGIC; + signal pcie_block_i_n_1098 : STD_LOGIC; + signal pcie_block_i_n_1099 : STD_LOGIC; + signal pcie_block_i_n_1100 : STD_LOGIC; + signal pcie_block_i_n_1101 : STD_LOGIC; + signal pcie_block_i_n_1102 : STD_LOGIC; + signal pcie_block_i_n_1103 : STD_LOGIC; + signal pcie_block_i_n_1143 : STD_LOGIC; + signal pcie_block_i_n_140 : STD_LOGIC; + signal pcie_block_i_n_141 : STD_LOGIC; + signal pcie_block_i_n_142 : STD_LOGIC; + signal pcie_block_i_n_143 : STD_LOGIC; + signal pcie_block_i_n_144 : STD_LOGIC; + signal pcie_block_i_n_145 : STD_LOGIC; + signal pcie_block_i_n_146 : STD_LOGIC; + signal pcie_block_i_n_155 : STD_LOGIC; + signal pcie_block_i_n_156 : STD_LOGIC; + signal pcie_block_i_n_157 : STD_LOGIC; + signal pcie_block_i_n_158 : STD_LOGIC; + signal pcie_block_i_n_159 : STD_LOGIC; + signal pcie_block_i_n_160 : STD_LOGIC; + signal pcie_block_i_n_169 : STD_LOGIC; + signal pcie_block_i_n_172 : STD_LOGIC; + signal pcie_block_i_n_173 : STD_LOGIC; + signal pcie_block_i_n_174 : STD_LOGIC; + signal pcie_block_i_n_175 : STD_LOGIC; + signal pcie_block_i_n_176 : STD_LOGIC; + signal pcie_block_i_n_177 : STD_LOGIC; + signal pcie_block_i_n_178 : STD_LOGIC; + signal pcie_block_i_n_179 : STD_LOGIC; + signal pcie_block_i_n_180 : STD_LOGIC; + signal pcie_block_i_n_181 : STD_LOGIC; + signal pcie_block_i_n_182 : STD_LOGIC; + signal pcie_block_i_n_183 : STD_LOGIC; + signal pcie_block_i_n_184 : STD_LOGIC; + signal pcie_block_i_n_185 : STD_LOGIC; + signal pcie_block_i_n_186 : STD_LOGIC; + signal pcie_block_i_n_187 : STD_LOGIC; + signal pcie_block_i_n_188 : STD_LOGIC; + signal pcie_block_i_n_189 : STD_LOGIC; + signal pcie_block_i_n_190 : STD_LOGIC; + signal pcie_block_i_n_191 : STD_LOGIC; + signal pcie_block_i_n_192 : STD_LOGIC; + signal pcie_block_i_n_193 : STD_LOGIC; + signal pcie_block_i_n_194 : STD_LOGIC; + signal pcie_block_i_n_195 : STD_LOGIC; + signal pcie_block_i_n_610 : STD_LOGIC; + signal pcie_block_i_n_611 : STD_LOGIC; + signal pcie_block_i_n_618 : STD_LOGIC; + signal pcie_block_i_n_619 : STD_LOGIC; + signal pcie_block_i_n_687 : STD_LOGIC; + signal pcie_block_i_n_688 : STD_LOGIC; + signal pcie_block_i_n_689 : STD_LOGIC; + signal pcie_block_i_n_690 : STD_LOGIC; + signal pcie_block_i_n_691 : STD_LOGIC; + signal pcie_block_i_n_704 : STD_LOGIC; + signal pcie_block_i_n_705 : STD_LOGIC; + signal pcie_block_i_n_706 : STD_LOGIC; + signal pcie_block_i_n_707 : STD_LOGIC; + signal pcie_block_i_n_708 : STD_LOGIC; + signal pcie_block_i_n_709 : STD_LOGIC; + signal pcie_block_i_n_710 : STD_LOGIC; + signal pcie_block_i_n_711 : STD_LOGIC; + signal pcie_block_i_n_712 : STD_LOGIC; + signal pcie_block_i_n_713 : STD_LOGIC; + signal pcie_block_i_n_714 : STD_LOGIC; + signal pcie_block_i_n_715 : STD_LOGIC; + signal pcie_block_i_n_716 : STD_LOGIC; + signal pcie_block_i_n_717 : STD_LOGIC; + signal pcie_block_i_n_718 : STD_LOGIC; + signal pcie_block_i_n_719 : STD_LOGIC; + signal pcie_block_i_n_72 : STD_LOGIC; + signal pcie_block_i_n_720 : STD_LOGIC; + signal pcie_block_i_n_721 : STD_LOGIC; + signal pcie_block_i_n_722 : STD_LOGIC; + signal pcie_block_i_n_723 : STD_LOGIC; + signal pcie_block_i_n_724 : STD_LOGIC; + signal pcie_block_i_n_725 : STD_LOGIC; + signal pcie_block_i_n_726 : STD_LOGIC; + signal pcie_block_i_n_727 : STD_LOGIC; + signal pcie_block_i_n_728 : STD_LOGIC; + signal pcie_block_i_n_729 : STD_LOGIC; + signal pcie_block_i_n_730 : STD_LOGIC; + signal pcie_block_i_n_731 : STD_LOGIC; + signal pcie_block_i_n_732 : STD_LOGIC; + signal pcie_block_i_n_733 : STD_LOGIC; + signal pcie_block_i_n_734 : STD_LOGIC; + signal pcie_block_i_n_735 : STD_LOGIC; + signal pcie_block_i_n_736 : STD_LOGIC; + signal pcie_block_i_n_737 : STD_LOGIC; + signal pcie_block_i_n_738 : STD_LOGIC; + signal pcie_block_i_n_739 : STD_LOGIC; + signal pcie_block_i_n_740 : STD_LOGIC; + signal pcie_block_i_n_741 : STD_LOGIC; + signal pcie_block_i_n_742 : STD_LOGIC; + signal pcie_block_i_n_743 : STD_LOGIC; + signal pcie_block_i_n_744 : STD_LOGIC; + signal pcie_block_i_n_745 : STD_LOGIC; + signal pcie_block_i_n_746 : STD_LOGIC; + signal pcie_block_i_n_747 : STD_LOGIC; + signal pcie_block_i_n_748 : STD_LOGIC; + signal pcie_block_i_n_749 : STD_LOGIC; + signal pcie_block_i_n_75 : STD_LOGIC; + signal pcie_block_i_n_750 : STD_LOGIC; + signal pcie_block_i_n_751 : STD_LOGIC; + signal pcie_block_i_n_752 : STD_LOGIC; + signal pcie_block_i_n_753 : STD_LOGIC; + signal pcie_block_i_n_754 : STD_LOGIC; + signal pcie_block_i_n_755 : STD_LOGIC; + signal pcie_block_i_n_756 : STD_LOGIC; + signal pcie_block_i_n_757 : STD_LOGIC; + signal pcie_block_i_n_758 : STD_LOGIC; + signal pcie_block_i_n_759 : STD_LOGIC; + signal pcie_block_i_n_76 : STD_LOGIC; + signal pcie_block_i_n_760 : STD_LOGIC; + signal pcie_block_i_n_761 : STD_LOGIC; + signal pcie_block_i_n_762 : STD_LOGIC; + signal pcie_block_i_n_763 : STD_LOGIC; + signal pcie_block_i_n_764 : STD_LOGIC; + signal pcie_block_i_n_765 : STD_LOGIC; + signal pcie_block_i_n_766 : STD_LOGIC; + signal pcie_block_i_n_767 : STD_LOGIC; + signal pcie_block_i_n_768 : STD_LOGIC; + signal pcie_block_i_n_769 : STD_LOGIC; + signal pcie_block_i_n_77 : STD_LOGIC; + signal pcie_block_i_n_770 : STD_LOGIC; + signal pcie_block_i_n_771 : STD_LOGIC; + signal pcie_block_i_n_772 : STD_LOGIC; + signal pcie_block_i_n_773 : STD_LOGIC; + signal pcie_block_i_n_774 : STD_LOGIC; + signal pcie_block_i_n_775 : STD_LOGIC; + signal pcie_block_i_n_776 : STD_LOGIC; + signal pcie_block_i_n_777 : STD_LOGIC; + signal pcie_block_i_n_778 : STD_LOGIC; + signal pcie_block_i_n_779 : STD_LOGIC; + signal pcie_block_i_n_78 : STD_LOGIC; + signal pcie_block_i_n_780 : STD_LOGIC; + signal pcie_block_i_n_781 : STD_LOGIC; + signal pcie_block_i_n_782 : STD_LOGIC; + signal pcie_block_i_n_783 : STD_LOGIC; + signal pcie_block_i_n_784 : STD_LOGIC; + signal pcie_block_i_n_785 : STD_LOGIC; + signal pcie_block_i_n_786 : STD_LOGIC; + signal pcie_block_i_n_787 : STD_LOGIC; + signal pcie_block_i_n_788 : STD_LOGIC; + signal pcie_block_i_n_789 : STD_LOGIC; + signal pcie_block_i_n_790 : STD_LOGIC; + signal pcie_block_i_n_791 : STD_LOGIC; + signal pcie_block_i_n_792 : STD_LOGIC; + signal pcie_block_i_n_793 : STD_LOGIC; + signal pcie_block_i_n_794 : STD_LOGIC; + signal pcie_block_i_n_795 : STD_LOGIC; + signal pcie_block_i_n_796 : STD_LOGIC; + signal pcie_block_i_n_797 : STD_LOGIC; + signal pcie_block_i_n_798 : STD_LOGIC; + signal pcie_block_i_n_799 : STD_LOGIC; + signal pcie_block_i_n_800 : STD_LOGIC; + signal pcie_block_i_n_801 : STD_LOGIC; + signal pcie_block_i_n_802 : STD_LOGIC; + signal pcie_block_i_n_803 : STD_LOGIC; + signal pcie_block_i_n_804 : STD_LOGIC; + signal pcie_block_i_n_805 : STD_LOGIC; + signal pcie_block_i_n_806 : STD_LOGIC; + signal pcie_block_i_n_807 : STD_LOGIC; + signal pcie_block_i_n_808 : STD_LOGIC; + signal pcie_block_i_n_809 : STD_LOGIC; + signal pcie_block_i_n_810 : STD_LOGIC; + signal pcie_block_i_n_811 : STD_LOGIC; + signal pcie_block_i_n_812 : STD_LOGIC; + signal pcie_block_i_n_813 : STD_LOGIC; + signal pcie_block_i_n_814 : STD_LOGIC; + signal pcie_block_i_n_815 : STD_LOGIC; + signal pcie_block_i_n_816 : STD_LOGIC; + signal pcie_block_i_n_817 : STD_LOGIC; + signal pcie_block_i_n_818 : STD_LOGIC; + signal pcie_block_i_n_819 : STD_LOGIC; + signal pcie_block_i_n_820 : STD_LOGIC; + signal pcie_block_i_n_821 : STD_LOGIC; + signal pcie_block_i_n_822 : STD_LOGIC; + signal pcie_block_i_n_823 : STD_LOGIC; + signal pcie_block_i_n_824 : STD_LOGIC; + signal pcie_block_i_n_825 : STD_LOGIC; + signal pcie_block_i_n_826 : STD_LOGIC; + signal pcie_block_i_n_827 : STD_LOGIC; + signal pcie_block_i_n_828 : STD_LOGIC; + signal pcie_block_i_n_829 : STD_LOGIC; + signal pcie_block_i_n_830 : STD_LOGIC; + signal pcie_block_i_n_831 : STD_LOGIC; + signal pcie_block_i_n_832 : STD_LOGIC; + signal pcie_block_i_n_833 : STD_LOGIC; + signal pcie_block_i_n_834 : STD_LOGIC; + signal pcie_block_i_n_835 : STD_LOGIC; + signal pcie_block_i_n_836 : STD_LOGIC; + signal pcie_block_i_n_837 : STD_LOGIC; + signal pcie_block_i_n_838 : STD_LOGIC; + signal pcie_block_i_n_839 : STD_LOGIC; + signal pcie_block_i_n_84 : STD_LOGIC; + signal pcie_block_i_n_840 : STD_LOGIC; + signal pcie_block_i_n_841 : STD_LOGIC; + signal pcie_block_i_n_842 : STD_LOGIC; + signal pcie_block_i_n_843 : STD_LOGIC; + signal pcie_block_i_n_844 : STD_LOGIC; + signal pcie_block_i_n_845 : STD_LOGIC; + signal pcie_block_i_n_846 : STD_LOGIC; + signal pcie_block_i_n_847 : STD_LOGIC; + signal pcie_block_i_n_848 : STD_LOGIC; + signal pcie_block_i_n_849 : STD_LOGIC; + signal pcie_block_i_n_85 : STD_LOGIC; + signal pcie_block_i_n_850 : STD_LOGIC; + signal pcie_block_i_n_851 : STD_LOGIC; + signal pcie_block_i_n_852 : STD_LOGIC; + signal pcie_block_i_n_853 : STD_LOGIC; + signal pcie_block_i_n_854 : STD_LOGIC; + signal pcie_block_i_n_855 : STD_LOGIC; + signal pcie_block_i_n_856 : STD_LOGIC; + signal pcie_block_i_n_857 : STD_LOGIC; + signal pcie_block_i_n_858 : STD_LOGIC; + signal pcie_block_i_n_859 : STD_LOGIC; + signal pcie_block_i_n_86 : STD_LOGIC; + signal pcie_block_i_n_860 : STD_LOGIC; + signal pcie_block_i_n_861 : STD_LOGIC; + signal pcie_block_i_n_862 : STD_LOGIC; + signal pcie_block_i_n_863 : STD_LOGIC; + signal pcie_block_i_n_864 : STD_LOGIC; + signal pcie_block_i_n_865 : STD_LOGIC; + signal pcie_block_i_n_866 : STD_LOGIC; + signal pcie_block_i_n_867 : STD_LOGIC; + signal pcie_block_i_n_868 : STD_LOGIC; + signal pcie_block_i_n_869 : STD_LOGIC; + signal pcie_block_i_n_87 : STD_LOGIC; + signal pcie_block_i_n_870 : STD_LOGIC; + signal pcie_block_i_n_871 : STD_LOGIC; + signal pcie_block_i_n_872 : STD_LOGIC; + signal pcie_block_i_n_873 : STD_LOGIC; + signal pcie_block_i_n_874 : STD_LOGIC; + signal pcie_block_i_n_875 : STD_LOGIC; + signal pcie_block_i_n_876 : STD_LOGIC; + signal pcie_block_i_n_877 : STD_LOGIC; + signal pcie_block_i_n_878 : STD_LOGIC; + signal pcie_block_i_n_879 : STD_LOGIC; + signal pcie_block_i_n_88 : STD_LOGIC; + signal pcie_block_i_n_880 : STD_LOGIC; + signal pcie_block_i_n_881 : STD_LOGIC; + signal pcie_block_i_n_882 : STD_LOGIC; + signal pcie_block_i_n_883 : STD_LOGIC; + signal pcie_block_i_n_884 : STD_LOGIC; + signal pcie_block_i_n_885 : STD_LOGIC; + signal pcie_block_i_n_886 : STD_LOGIC; + signal pcie_block_i_n_887 : STD_LOGIC; + signal pcie_block_i_n_888 : STD_LOGIC; + signal pcie_block_i_n_889 : STD_LOGIC; + signal pcie_block_i_n_89 : STD_LOGIC; + signal pcie_block_i_n_890 : STD_LOGIC; + signal pcie_block_i_n_891 : STD_LOGIC; + signal pcie_block_i_n_892 : STD_LOGIC; + signal pcie_block_i_n_893 : STD_LOGIC; + signal pcie_block_i_n_894 : STD_LOGIC; + signal pcie_block_i_n_895 : STD_LOGIC; + signal pcie_block_i_n_896 : STD_LOGIC; + signal pcie_block_i_n_897 : STD_LOGIC; + signal pcie_block_i_n_898 : STD_LOGIC; + signal pcie_block_i_n_899 : STD_LOGIC; + signal pcie_block_i_n_90 : STD_LOGIC; + signal pcie_block_i_n_900 : STD_LOGIC; + signal pcie_block_i_n_901 : STD_LOGIC; + signal pcie_block_i_n_902 : STD_LOGIC; + signal pcie_block_i_n_903 : STD_LOGIC; + signal pcie_block_i_n_904 : STD_LOGIC; + signal pcie_block_i_n_905 : STD_LOGIC; + signal pcie_block_i_n_906 : STD_LOGIC; + signal pcie_block_i_n_907 : STD_LOGIC; + signal pcie_block_i_n_908 : STD_LOGIC; + signal pcie_block_i_n_909 : STD_LOGIC; + signal pcie_block_i_n_91 : STD_LOGIC; + signal pcie_block_i_n_910 : STD_LOGIC; + signal pcie_block_i_n_911 : STD_LOGIC; + signal pcie_block_i_n_912 : STD_LOGIC; + signal pcie_block_i_n_913 : STD_LOGIC; + signal pcie_block_i_n_914 : STD_LOGIC; + signal pcie_block_i_n_915 : STD_LOGIC; + signal pcie_block_i_n_916 : STD_LOGIC; + signal pcie_block_i_n_917 : STD_LOGIC; + signal pcie_block_i_n_918 : STD_LOGIC; + signal pcie_block_i_n_919 : STD_LOGIC; + signal pcie_block_i_n_92 : STD_LOGIC; + signal pcie_block_i_n_920 : STD_LOGIC; + signal pcie_block_i_n_921 : STD_LOGIC; + signal pcie_block_i_n_922 : STD_LOGIC; + signal pcie_block_i_n_923 : STD_LOGIC; + signal pcie_block_i_n_924 : STD_LOGIC; + signal pcie_block_i_n_925 : STD_LOGIC; + signal pcie_block_i_n_926 : STD_LOGIC; + signal pcie_block_i_n_927 : STD_LOGIC; + signal pcie_block_i_n_928 : STD_LOGIC; + signal pcie_block_i_n_929 : STD_LOGIC; + signal pcie_block_i_n_93 : STD_LOGIC; + signal pcie_block_i_n_930 : STD_LOGIC; + signal pcie_block_i_n_931 : STD_LOGIC; + signal pcie_block_i_n_932 : STD_LOGIC; + signal pcie_block_i_n_933 : STD_LOGIC; + signal pcie_block_i_n_934 : STD_LOGIC; + signal pcie_block_i_n_935 : STD_LOGIC; + signal pcie_block_i_n_936 : STD_LOGIC; + signal pcie_block_i_n_937 : STD_LOGIC; + signal pcie_block_i_n_938 : STD_LOGIC; + signal pcie_block_i_n_939 : STD_LOGIC; + signal pcie_block_i_n_94 : STD_LOGIC; + signal pcie_block_i_n_940 : STD_LOGIC; + signal pcie_block_i_n_941 : STD_LOGIC; + signal pcie_block_i_n_942 : STD_LOGIC; + signal pcie_block_i_n_943 : STD_LOGIC; + signal pcie_block_i_n_944 : STD_LOGIC; + signal pcie_block_i_n_945 : STD_LOGIC; + signal pcie_block_i_n_946 : STD_LOGIC; + signal pcie_block_i_n_947 : STD_LOGIC; + signal pcie_block_i_n_948 : STD_LOGIC; + signal pcie_block_i_n_949 : STD_LOGIC; + signal pcie_block_i_n_95 : STD_LOGIC; + signal pcie_block_i_n_950 : STD_LOGIC; + signal pcie_block_i_n_951 : STD_LOGIC; + signal pcie_block_i_n_952 : STD_LOGIC; + signal pcie_block_i_n_953 : STD_LOGIC; + signal pcie_block_i_n_954 : STD_LOGIC; + signal pcie_block_i_n_955 : STD_LOGIC; + signal pcie_block_i_n_956 : STD_LOGIC; + signal pcie_block_i_n_957 : STD_LOGIC; + signal pcie_block_i_n_958 : STD_LOGIC; + signal pcie_block_i_n_959 : STD_LOGIC; + signal pcie_block_i_n_96 : STD_LOGIC; + signal pcie_block_i_n_98 : STD_LOGIC; + signal pcie_block_i_n_99 : STD_LOGIC; + signal pipe_rx4_polarity : STD_LOGIC; + signal pipe_rx5_polarity : STD_LOGIC; + signal pipe_rx6_polarity : STD_LOGIC; + signal pipe_rx7_polarity : STD_LOGIC; + signal pipe_tx4_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx4_compliance : STD_LOGIC; + signal pipe_tx4_data : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_tx4_elec_idle : STD_LOGIC; + signal pipe_tx4_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx5_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx5_compliance : STD_LOGIC; + signal pipe_tx5_data : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_tx5_elec_idle : STD_LOGIC; + signal pipe_tx5_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx6_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx6_compliance : STD_LOGIC; + signal pipe_tx6_data : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_tx6_elec_idle : STD_LOGIC; + signal pipe_tx6_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx7_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx7_compliance : STD_LOGIC; + signal pipe_tx7_data : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_tx7_elec_idle : STD_LOGIC; + signal pipe_tx7_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pl_phy_lnk_up_n : STD_LOGIC; + signal trn_rd : STD_LOGIC_VECTOR ( 127 downto 64 ); + signal \^trn_reof\ : STD_LOGIC; + signal trn_rrem : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \^trn_rsof\ : STD_LOGIC; + signal \^trn_rsrc_dsc\ : STD_LOGIC; + signal trn_rsrc_rdy : STD_LOGIC; + signal \^trn_tbuf_av\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \^trn_tcfg_req\ : STD_LOGIC; + signal \^trn_tdst_rdy\ : STD_LOGIC; + signal user_rst_n : STD_LOGIC; + signal NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of pcie_block_i : label is "PRIMITIVE"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of trn_rsrc_dsc_prev_i_1 : label is "soft_lutpair256"; + attribute SOFT_HLUTNM of trn_rsrc_rdy_prev_i_1 : label is "soft_lutpair256"; +begin + cfg_msg_received <= \^cfg_msg_received\; + cfg_pcie_link_state(2 downto 0) <= \^cfg_pcie_link_state\(2 downto 0); + trn_reof <= \^trn_reof\; + trn_rsof <= \^trn_rsof\; + trn_rsrc_dsc <= \^trn_rsrc_dsc\; + trn_tbuf_av(5 downto 0) <= \^trn_tbuf_av\(5 downto 0); + trn_tcfg_req <= \^trn_tcfg_req\; + trn_tdst_rdy <= \^trn_tdst_rdy\; +\cfg_bus_number_d[7]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^cfg_msg_received\, + O => E(0) + ); +cfg_err_aer_headerlog_set_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_aer_headerlog_set_n, + O => cfg_err_aer_headerlog_set + ); +cfg_err_cpl_rdy_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_cpl_rdy_n, + O => cfg_err_cpl_rdy + ); +cfg_interrupt_rdy_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_interrupt_rdy_n, + O => cfg_interrupt_rdy + ); +cfg_mgmt_rd_wr_done_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_mgmt_rd_wr_done_n, + O => cfg_mgmt_rd_wr_done + ); +cfg_received_func_lvl_rst_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_received_func_lvl_rst_n, + O => cfg_received_func_lvl_rst + ); +lnk_up_thrtl_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"4F" + ) + port map ( + I0 => \^trn_tdst_rdy\, + I1 => lnk_up_thrtl, + I2 => \out\, + O => lnk_up_thrtl_reg + ); +m_axis_rx_tvalid_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000027000000" + ) + port map ( + I0 => \^trn_reof\, + I1 => trn_rdst_rdy, + I2 => \^trn_rsof\, + I3 => \^trn_rsrc_dsc\, + I4 => trn_in_packet, + I5 => trn_rsrc_dsc_d, + O => dsc_detect + ); +pcie_block_i: unisim.vcomponents.PCIE_2_1 + generic map( + AER_BASE_PTR => X"000", + AER_CAP_ECRC_CHECK_CAPABLE => "FALSE", + AER_CAP_ECRC_GEN_CAPABLE => "FALSE", + AER_CAP_ID => X"0001", + AER_CAP_MULTIHEADER => "FALSE", + AER_CAP_NEXTPTR => X"000", + AER_CAP_ON => "FALSE", + AER_CAP_OPTIONAL_ERR_SUPPORT => X"000000", + AER_CAP_PERMIT_ROOTERR_UPDATE => "FALSE", + AER_CAP_VERSION => X"1", + ALLOW_X8_GEN2 => "FALSE", + BAR0 => X"FFFF0000", + BAR1 => X"00000000", + BAR2 => X"00000000", + BAR3 => X"00000000", + BAR4 => X"00000000", + BAR5 => X"00000000", + CAPABILITIES_PTR => X"40", + CARDBUS_CIS_POINTER => X"00000000", + CFG_ECRC_ERR_CPLSTAT => 0, + CLASS_CODE => X"050000", + CMD_INTX_IMPLEMENTED => "TRUE", + CPL_TIMEOUT_DISABLE_SUPPORTED => "FALSE", + CPL_TIMEOUT_RANGES_SUPPORTED => X"2", + CRM_MODULE_RSTS => X"00", + DEV_CAP2_ARI_FORWARDING_SUPPORTED => "FALSE", + DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED => "FALSE", + DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED => "FALSE", + DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED => "FALSE", + DEV_CAP2_CAS128_COMPLETER_SUPPORTED => "FALSE", + DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED => "FALSE", + DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED => "FALSE", + DEV_CAP2_LTR_MECHANISM_SUPPORTED => "FALSE", + DEV_CAP2_MAX_ENDEND_TLP_PREFIXES => X"0", + DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING => "FALSE", + DEV_CAP2_TPH_COMPLETER_SUPPORTED => X"0", + DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE => "TRUE", + DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE => "TRUE", + DEV_CAP_ENDPOINT_L0S_LATENCY => 0, + DEV_CAP_ENDPOINT_L1_LATENCY => 7, + DEV_CAP_EXT_TAG_SUPPORTED => "FALSE", + DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE => "FALSE", + DEV_CAP_MAX_PAYLOAD_SUPPORTED => 3, + DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => 0, + DEV_CAP_ROLE_BASED_ERROR => "TRUE", + DEV_CAP_RSVD_14_12 => 0, + DEV_CAP_RSVD_17_16 => 0, + DEV_CAP_RSVD_31_29 => 0, + DEV_CONTROL_AUX_POWER_SUPPORTED => "FALSE", + DEV_CONTROL_EXT_TAG_DEFAULT => "FALSE", + DISABLE_ASPM_L1_TIMER => "FALSE", + DISABLE_BAR_FILTERING => "FALSE", + DISABLE_ERR_MSG => "FALSE", + DISABLE_ID_CHECK => "FALSE", + DISABLE_LANE_REVERSAL => "TRUE", + DISABLE_LOCKED_FILTER => "FALSE", + DISABLE_PPM_FILTER => "FALSE", + DISABLE_RX_POISONED_RESP => "FALSE", + DISABLE_RX_TC_FILTER => "FALSE", + DISABLE_SCRAMBLING => "FALSE", + DNSTREAM_LINK_NUM => X"00", + DSN_BASE_PTR => X"100", + DSN_CAP_ID => X"0003", + DSN_CAP_NEXTPTR => X"000", + DSN_CAP_ON => "TRUE", + DSN_CAP_VERSION => X"1", + ENABLE_MSG_ROUTE => X"000", + ENABLE_RX_TD_ECRC_TRIM => "FALSE", + ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED => "FALSE", + ENTER_RVRY_EI_L0 => "TRUE", + EXIT_LOOPBACK_ON_EI => "TRUE", + EXPANSION_ROM => X"00000000", + EXT_CFG_CAP_PTR => X"3F", + EXT_CFG_XP_CAP_PTR => X"3FF", + HEADER_TYPE => X"00", + INFER_EI => X"00", + INTERRUPT_PIN => X"01", + INTERRUPT_STAT_AUTO => "TRUE", + IS_SWITCH => "FALSE", + LAST_CONFIG_DWORD => X"3FF", + LINK_CAP_ASPM_OPTIONALITY => "FALSE", + LINK_CAP_ASPM_SUPPORT => 1, + LINK_CAP_CLOCK_POWER_MANAGEMENT => "FALSE", + LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP => "FALSE", + LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 => 7, + LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 => 7, + LINK_CAP_L0S_EXIT_LATENCY_GEN1 => 7, + LINK_CAP_L0S_EXIT_LATENCY_GEN2 => 7, + LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 => 7, + LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 => 7, + LINK_CAP_L1_EXIT_LATENCY_GEN1 => 7, + LINK_CAP_L1_EXIT_LATENCY_GEN2 => 7, + LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP => "FALSE", + LINK_CAP_MAX_LINK_SPEED => X"2", + LINK_CAP_MAX_LINK_WIDTH => X"04", + LINK_CAP_RSVD_23 => 0, + LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE => "FALSE", + LINK_CONTROL_RCB => 0, + LINK_CTRL2_DEEMPHASIS => "FALSE", + LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE => "FALSE", + LINK_CTRL2_TARGET_LINK_SPEED => X"2", + LINK_STATUS_SLOT_CLOCK_CONFIG => "TRUE", + LL_ACK_TIMEOUT => X"0000", + LL_ACK_TIMEOUT_EN => "FALSE", + LL_ACK_TIMEOUT_FUNC => 0, + LL_REPLAY_TIMEOUT => X"0000", + LL_REPLAY_TIMEOUT_EN => "FALSE", + LL_REPLAY_TIMEOUT_FUNC => 1, + LTSSM_MAX_LINK_WIDTH => X"04", + MPS_FORCE => "FALSE", + MSIX_BASE_PTR => X"9C", + MSIX_CAP_ID => X"11", + MSIX_CAP_NEXTPTR => X"00", + MSIX_CAP_ON => "FALSE", + MSIX_CAP_PBA_BIR => 0, + MSIX_CAP_PBA_OFFSET => X"00000000", + MSIX_CAP_TABLE_BIR => 0, + MSIX_CAP_TABLE_OFFSET => X"00000000", + MSIX_CAP_TABLE_SIZE => X"000", + MSI_BASE_PTR => X"48", + MSI_CAP_64_BIT_ADDR_CAPABLE => "TRUE", + MSI_CAP_ID => X"05", + MSI_CAP_MULTIMSGCAP => 0, + MSI_CAP_MULTIMSG_EXTENSION => 0, + MSI_CAP_NEXTPTR => X"60", + MSI_CAP_ON => "FALSE", + MSI_CAP_PER_VECTOR_MASKING_CAPABLE => "FALSE", + N_FTS_COMCLK_GEN1 => 255, + N_FTS_COMCLK_GEN2 => 255, + N_FTS_GEN1 => 255, + N_FTS_GEN2 => 255, + PCIE_BASE_PTR => X"60", + PCIE_CAP_CAPABILITY_ID => X"10", + PCIE_CAP_CAPABILITY_VERSION => X"2", + PCIE_CAP_DEVICE_PORT_TYPE => X"0", + PCIE_CAP_NEXTPTR => X"00", + PCIE_CAP_ON => "TRUE", + PCIE_CAP_RSVD_15_14 => 0, + PCIE_CAP_SLOT_IMPLEMENTED => "FALSE", + PCIE_REVISION => 2, + PL_AUTO_CONFIG => 0, + PL_FAST_TRAIN => "TRUE", + PM_ASPML0S_TIMEOUT => X"0000", + PM_ASPML0S_TIMEOUT_EN => "FALSE", + PM_ASPML0S_TIMEOUT_FUNC => 0, + PM_ASPM_FASTEXIT => "FALSE", + PM_BASE_PTR => X"40", + PM_CAP_AUXCURRENT => 0, + PM_CAP_D1SUPPORT => "FALSE", + PM_CAP_D2SUPPORT => "FALSE", + PM_CAP_DSI => "FALSE", + PM_CAP_ID => X"01", + PM_CAP_NEXTPTR => X"60", + PM_CAP_ON => "TRUE", + PM_CAP_PMESUPPORT => X"0F", + PM_CAP_PME_CLOCK => "FALSE", + PM_CAP_RSVD_04 => 0, + PM_CAP_VERSION => 3, + PM_CSR_B2B3 => "FALSE", + PM_CSR_BPCCEN => "FALSE", + PM_CSR_NOSOFTRST => "TRUE", + PM_DATA0 => X"00", + PM_DATA1 => X"00", + PM_DATA2 => X"00", + PM_DATA3 => X"00", + PM_DATA4 => X"00", + PM_DATA5 => X"00", + PM_DATA6 => X"00", + PM_DATA7 => X"00", + PM_DATA_SCALE0 => X"0", + PM_DATA_SCALE1 => X"0", + PM_DATA_SCALE2 => X"0", + PM_DATA_SCALE3 => X"0", + PM_DATA_SCALE4 => X"0", + PM_DATA_SCALE5 => X"0", + PM_DATA_SCALE6 => X"0", + PM_DATA_SCALE7 => X"0", + PM_MF => "FALSE", + RBAR_BASE_PTR => X"000", + RBAR_CAP_CONTROL_ENCODEDBAR0 => X"00", + RBAR_CAP_CONTROL_ENCODEDBAR1 => X"00", + RBAR_CAP_CONTROL_ENCODEDBAR2 => X"00", + RBAR_CAP_CONTROL_ENCODEDBAR3 => X"00", + RBAR_CAP_CONTROL_ENCODEDBAR4 => X"00", + RBAR_CAP_CONTROL_ENCODEDBAR5 => X"00", + RBAR_CAP_ID => X"0015", + RBAR_CAP_INDEX0 => X"0", + RBAR_CAP_INDEX1 => X"0", + RBAR_CAP_INDEX2 => X"0", + RBAR_CAP_INDEX3 => X"0", + RBAR_CAP_INDEX4 => X"0", + RBAR_CAP_INDEX5 => X"0", + RBAR_CAP_NEXTPTR => X"000", + RBAR_CAP_ON => "FALSE", + RBAR_CAP_SUP0 => X"00000001", + RBAR_CAP_SUP1 => X"00000001", + RBAR_CAP_SUP2 => X"00000001", + RBAR_CAP_SUP3 => X"00000001", + RBAR_CAP_SUP4 => X"00000001", + RBAR_CAP_SUP5 => X"00000001", + RBAR_CAP_VERSION => X"1", + RBAR_NUM => X"0", + RECRC_CHK => 0, + RECRC_CHK_TRIM => "FALSE", + ROOT_CAP_CRS_SW_VISIBILITY => "FALSE", + RP_AUTO_SPD => X"1", + RP_AUTO_SPD_LOOPCNT => X"1F", + SELECT_DLL_IF => "FALSE", + SIM_VERSION => "1.0", + SLOT_CAP_ATT_BUTTON_PRESENT => "FALSE", + SLOT_CAP_ATT_INDICATOR_PRESENT => "FALSE", + SLOT_CAP_ELEC_INTERLOCK_PRESENT => "FALSE", + SLOT_CAP_HOTPLUG_CAPABLE => "FALSE", + SLOT_CAP_HOTPLUG_SURPRISE => "FALSE", + SLOT_CAP_MRL_SENSOR_PRESENT => "FALSE", + SLOT_CAP_NO_CMD_COMPLETED_SUPPORT => "FALSE", + SLOT_CAP_PHYSICAL_SLOT_NUM => X"0000", + SLOT_CAP_POWER_CONTROLLER_PRESENT => "FALSE", + SLOT_CAP_POWER_INDICATOR_PRESENT => "FALSE", + SLOT_CAP_SLOT_POWER_LIMIT_SCALE => 0, + SLOT_CAP_SLOT_POWER_LIMIT_VALUE => X"00", + SPARE_BIT0 => 0, + SPARE_BIT1 => 0, + SPARE_BIT2 => 0, + SPARE_BIT3 => 0, + SPARE_BIT4 => 0, + SPARE_BIT5 => 0, + SPARE_BIT6 => 0, + SPARE_BIT7 => 0, + SPARE_BIT8 => 0, + SPARE_BYTE0 => X"00", + SPARE_BYTE1 => X"00", + SPARE_BYTE2 => X"00", + SPARE_BYTE3 => X"00", + SPARE_WORD0 => X"00000000", + SPARE_WORD1 => X"00000000", + SPARE_WORD2 => X"00000000", + SPARE_WORD3 => X"00000000", + SSL_MESSAGE_AUTO => "FALSE", + TECRC_EP_INV => "FALSE", + TL_RBYPASS => "FALSE", + TL_RX_RAM_RADDR_LATENCY => 0, + TL_RX_RAM_RDATA_LATENCY => 2, + TL_RX_RAM_WRITE_LATENCY => 0, + TL_TFC_DISABLE => "FALSE", + TL_TX_CHECKS_DISABLE => "FALSE", + TL_TX_RAM_RADDR_LATENCY => 0, + TL_TX_RAM_RDATA_LATENCY => 2, + TL_TX_RAM_WRITE_LATENCY => 0, + TRN_DW => "FALSE", + TRN_NP_FC => "TRUE", + UPCONFIG_CAPABLE => "TRUE", + UPSTREAM_FACING => "TRUE", + UR_ATOMIC => "FALSE", + UR_CFG1 => "TRUE", + UR_INV_REQ => "TRUE", + UR_PRS_RESPONSE => "TRUE", + USER_CLK2_DIV2 => "FALSE", + USER_CLK_FREQ => 3, + USE_RID_PINS => "FALSE", + VC0_CPL_INFINITE => "TRUE", + VC0_RX_RAM_LIMIT => X"0FFF", + VC0_TOTAL_CREDITS_CD => 973, + VC0_TOTAL_CREDITS_CH => 36, + VC0_TOTAL_CREDITS_NPD => 24, + VC0_TOTAL_CREDITS_NPH => 12, + VC0_TOTAL_CREDITS_PD => 949, + VC0_TOTAL_CREDITS_PH => 32, + VC0_TX_LASTPACKET => 30, + VC_BASE_PTR => X"000", + VC_CAP_ID => X"0002", + VC_CAP_NEXTPTR => X"000", + VC_CAP_ON => "FALSE", + VC_CAP_REJECT_SNOOP_TRANSACTIONS => "FALSE", + VC_CAP_VERSION => X"1", + VSEC_BASE_PTR => X"000", + VSEC_CAP_HDR_ID => X"1234", + VSEC_CAP_HDR_LENGTH => X"018", + VSEC_CAP_HDR_REVISION => X"1", + VSEC_CAP_ID => X"000B", + VSEC_CAP_IS_LINK_VISIBLE => "TRUE", + VSEC_CAP_NEXTPTR => X"000", + VSEC_CAP_ON => "FALSE", + VSEC_CAP_VERSION => X"1" + ) + port map ( + CFGAERECRCCHECKEN => cfg_aer_ecrc_check_en, + CFGAERECRCGENEN => cfg_aer_ecrc_gen_en, + CFGAERINTERRUPTMSGNUM(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0), + CFGAERROOTERRCORRERRRECEIVED => cfg_aer_rooterr_corr_err_received, + CFGAERROOTERRCORRERRREPORTINGEN => cfg_aer_rooterr_corr_err_reporting_en, + CFGAERROOTERRFATALERRRECEIVED => cfg_aer_rooterr_fatal_err_received, + CFGAERROOTERRFATALERRREPORTINGEN => cfg_aer_rooterr_fatal_err_reporting_en, + CFGAERROOTERRNONFATALERRRECEIVED => cfg_aer_rooterr_non_fatal_err_received, + CFGAERROOTERRNONFATALERRREPORTINGEN => cfg_aer_rooterr_non_fatal_err_reporting_en, + CFGBRIDGESERREN => cfg_bridge_serr_en, + CFGCOMMANDBUSMASTERENABLE => cfg_command(2), + CFGCOMMANDINTERRUPTDISABLE => cfg_command(4), + CFGCOMMANDIOENABLE => cfg_command(0), + CFGCOMMANDMEMENABLE => cfg_command(1), + CFGCOMMANDSERREN => cfg_command(3), + CFGDEVCONTROL2ARIFORWARDEN => cfg_dcommand2(5), + CFGDEVCONTROL2ATOMICEGRESSBLOCK => cfg_dcommand2(7), + CFGDEVCONTROL2ATOMICREQUESTEREN => cfg_dcommand2(6), + CFGDEVCONTROL2CPLTIMEOUTDIS => cfg_dcommand2(4), + CFGDEVCONTROL2CPLTIMEOUTVAL(3 downto 0) => cfg_dcommand2(3 downto 0), + CFGDEVCONTROL2IDOCPLEN => cfg_dcommand2(9), + CFGDEVCONTROL2IDOREQEN => cfg_dcommand2(8), + CFGDEVCONTROL2LTREN => cfg_dcommand2(10), + CFGDEVCONTROL2TLPPREFIXBLOCK => cfg_dcommand2(11), + CFGDEVCONTROLAUXPOWEREN => cfg_dcommand(10), + CFGDEVCONTROLCORRERRREPORTINGEN => cfg_dcommand(0), + CFGDEVCONTROLENABLERO => cfg_dcommand(4), + CFGDEVCONTROLEXTTAGEN => cfg_dcommand(8), + CFGDEVCONTROLFATALERRREPORTINGEN => cfg_dcommand(2), + CFGDEVCONTROLMAXPAYLOAD(2 downto 0) => cfg_dcommand(7 downto 5), + CFGDEVCONTROLMAXREADREQ(2 downto 0) => cfg_dcommand(14 downto 12), + CFGDEVCONTROLNONFATALREPORTINGEN => cfg_dcommand(1), + CFGDEVCONTROLNOSNOOPEN => cfg_dcommand(11), + CFGDEVCONTROLPHANTOMEN => cfg_dcommand(9), + CFGDEVCONTROLURERRREPORTINGEN => cfg_dcommand(3), + CFGDEVID(15 downto 0) => B"0111000000100100", + CFGDEVSTATUSCORRERRDETECTED => cfg_dstatus(0), + CFGDEVSTATUSFATALERRDETECTED => cfg_dstatus(2), + CFGDEVSTATUSNONFATALERRDETECTED => cfg_dstatus(1), + CFGDEVSTATUSURDETECTED => cfg_dstatus(3), + CFGDSBUSNUMBER(7 downto 0) => cfg_ds_bus_number(7 downto 0), + CFGDSDEVICENUMBER(4 downto 0) => cfg_ds_device_number(4 downto 0), + CFGDSFUNCTIONNUMBER(2 downto 0) => cfg_ds_function_number(2 downto 0), + CFGDSN(63 downto 0) => cfg_dsn(63 downto 0), + CFGERRACSN => '1', + CFGERRAERHEADERLOG(127 downto 0) => cfg_err_aer_headerlog(127 downto 0), + CFGERRAERHEADERLOGSETN => cfg_err_aer_headerlog_set_n, + CFGERRATOMICEGRESSBLOCKEDN => pcie_block_i_i_1_n_0, + CFGERRCORN => pcie_block_i_i_2_n_0, + CFGERRCPLABORTN => pcie_block_i_i_3_n_0, + CFGERRCPLRDYN => cfg_err_cpl_rdy_n, + CFGERRCPLTIMEOUTN => pcie_block_i_i_4_n_0, + CFGERRCPLUNEXPECTN => pcie_block_i_i_5_n_0, + CFGERRECRCN => pcie_block_i_i_6_n_0, + CFGERRINTERNALCORN => pcie_block_i_i_7_n_0, + CFGERRINTERNALUNCORN => pcie_block_i_i_8_n_0, + CFGERRLOCKEDN => pcie_block_i_i_9_n_0, + CFGERRMALFORMEDN => pcie_block_i_i_10_n_0, + CFGERRMCBLOCKEDN => pcie_block_i_i_11_n_0, + CFGERRNORECOVERYN => pcie_block_i_i_12_n_0, + CFGERRPOISONEDN => pcie_block_i_i_13_n_0, + CFGERRPOSTEDN => pcie_block_i_i_14_n_0, + CFGERRTLPCPLHEADER(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0), + CFGERRURN => pcie_block_i_i_15_n_0, + CFGFORCECOMMONCLOCKOFF => '0', + CFGFORCEEXTENDEDSYNCON => '0', + CFGFORCEMPS(2 downto 0) => B"000", + CFGINTERRUPTASSERTN => pcie_block_i_i_16_n_0, + CFGINTERRUPTDI(7 downto 0) => cfg_interrupt_di(7 downto 0), + CFGINTERRUPTDO(7 downto 0) => cfg_interrupt_do(7 downto 0), + CFGINTERRUPTMMENABLE(2 downto 0) => cfg_interrupt_mmenable(2 downto 0), + CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable, + CFGINTERRUPTMSIXENABLE => cfg_interrupt_msixenable, + CFGINTERRUPTMSIXFM => cfg_interrupt_msixfm, + CFGINTERRUPTN => pcie_block_i_i_17_n_0, + CFGINTERRUPTRDYN => cfg_interrupt_rdy_n, + CFGINTERRUPTSTATN => pcie_block_i_i_18_n_0, + CFGLINKCONTROLASPMCONTROL(1 downto 0) => cfg_lcommand(1 downto 0), + CFGLINKCONTROLAUTOBANDWIDTHINTEN => cfg_lcommand(10), + CFGLINKCONTROLBANDWIDTHINTEN => cfg_lcommand(9), + CFGLINKCONTROLCLOCKPMEN => cfg_lcommand(7), + CFGLINKCONTROLCOMMONCLOCK => cfg_lcommand(5), + CFGLINKCONTROLEXTENDEDSYNC => cfg_lcommand(6), + CFGLINKCONTROLHWAUTOWIDTHDIS => cfg_lcommand(8), + CFGLINKCONTROLLINKDISABLE => cfg_lcommand(3), + CFGLINKCONTROLRCB => cfg_lcommand(2), + CFGLINKCONTROLRETRAINLINK => cfg_lcommand(4), + CFGLINKSTATUSAUTOBANDWIDTHSTATUS => cfg_lstatus(9), + CFGLINKSTATUSBANDWIDTHSTATUS => cfg_lstatus(8), + CFGLINKSTATUSCURRENTSPEED(1 downto 0) => cfg_lstatus(1 downto 0), + CFGLINKSTATUSDLLACTIVE => cfg_lstatus(7), + CFGLINKSTATUSLINKTRAINING => cfg_lstatus(6), + CFGLINKSTATUSNEGOTIATEDWIDTH(3 downto 0) => cfg_lstatus(5 downto 2), + CFGMGMTBYTEENN(3 downto 0) => cfg_mgmt_byte_en_n(3 downto 0), + CFGMGMTDI(31 downto 0) => cfg_mgmt_di(31 downto 0), + CFGMGMTDO(31 downto 0) => cfg_mgmt_do(31 downto 0), + CFGMGMTDWADDR(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0), + CFGMGMTRDENN => pcie_block_i_i_19_n_0, + CFGMGMTRDWRDONEN => cfg_mgmt_rd_wr_done_n, + CFGMGMTWRENN => pcie_block_i_i_20_n_0, + CFGMGMTWRREADONLYN => pcie_block_i_i_21_n_0, + CFGMGMTWRRW1CASRWN => pcie_block_i_i_22_n_0, + CFGMSGDATA(15 downto 0) => cfg_msg_data(15 downto 0), + CFGMSGRECEIVED => \^cfg_msg_received\, + CFGMSGRECEIVEDASSERTINTA => cfg_msg_received_assert_int_a, + CFGMSGRECEIVEDASSERTINTB => cfg_msg_received_assert_int_b, + CFGMSGRECEIVEDASSERTINTC => cfg_msg_received_assert_int_c, + CFGMSGRECEIVEDASSERTINTD => cfg_msg_received_assert_int_d, + CFGMSGRECEIVEDDEASSERTINTA => cfg_msg_received_deassert_int_a, + CFGMSGRECEIVEDDEASSERTINTB => cfg_msg_received_deassert_int_b, + CFGMSGRECEIVEDDEASSERTINTC => cfg_msg_received_deassert_int_c, + CFGMSGRECEIVEDDEASSERTINTD => cfg_msg_received_deassert_int_d, + CFGMSGRECEIVEDERRCOR => cfg_msg_received_err_cor, + CFGMSGRECEIVEDERRFATAL => cfg_msg_received_err_fatal, + CFGMSGRECEIVEDERRNONFATAL => cfg_msg_received_err_non_fatal, + CFGMSGRECEIVEDPMASNAK => cfg_msg_received_pm_as_nak, + CFGMSGRECEIVEDPMETO => cfg_to_turnoff, + CFGMSGRECEIVEDPMETOACK => cfg_msg_received_pme_to_ack, + CFGMSGRECEIVEDPMPME => cfg_msg_received_pm_pme, + CFGMSGRECEIVEDSETSLOTPOWERLIMIT => cfg_msg_received_setslotpowerlimit, + CFGMSGRECEIVEDUNLOCK => pcie_block_i_n_72, + CFGPCIECAPINTERRUPTMSGNUM(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0), + CFGPCIELINKSTATE(2 downto 0) => \^cfg_pcie_link_state\(2 downto 0), + CFGPMCSRPMEEN => cfg_pmcsr_pme_en, + CFGPMCSRPMESTATUS => cfg_pmcsr_pme_status, + CFGPMCSRPOWERSTATE(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0), + CFGPMFORCESTATE(1 downto 0) => cfg_pm_force_state(1 downto 0), + CFGPMFORCESTATEENN => pcie_block_i_i_23_n_0, + CFGPMHALTASPML0SN => pcie_block_i_i_24_n_0, + CFGPMHALTASPML1N => pcie_block_i_i_25_n_0, + CFGPMRCVASREQL1N => pcie_block_i_n_75, + CFGPMRCVENTERL1N => pcie_block_i_n_76, + CFGPMRCVENTERL23N => pcie_block_i_n_77, + CFGPMRCVREQACKN => pcie_block_i_n_78, + CFGPMSENDPMETON => '1', + CFGPMTURNOFFOKN => cfg_pm_turnoff_ok_n, + CFGPMWAKEN => pcie_block_i_i_27_n_0, + CFGPORTNUMBER(7 downto 0) => B"00000000", + CFGREVID(7 downto 0) => B"00000000", + CFGROOTCONTROLPMEINTEN => cfg_root_control_pme_int_en, + CFGROOTCONTROLSYSERRCORRERREN => cfg_root_control_syserr_corr_err_en, + CFGROOTCONTROLSYSERRFATALERREN => cfg_root_control_syserr_fatal_err_en, + CFGROOTCONTROLSYSERRNONFATALERREN => cfg_root_control_syserr_non_fatal_err_en, + CFGSLOTCONTROLELECTROMECHILCTLPULSE => cfg_slot_control_electromech_il_ctl_pulse, + CFGSUBSYSID(15 downto 0) => B"0000000000000111", + CFGSUBSYSVENDID(15 downto 0) => B"0001000011101110", + CFGTRANSACTION => pcie_block_i_n_84, + CFGTRANSACTIONADDR(6) => pcie_block_i_n_1097, + CFGTRANSACTIONADDR(5) => pcie_block_i_n_1098, + CFGTRANSACTIONADDR(4) => pcie_block_i_n_1099, + CFGTRANSACTIONADDR(3) => pcie_block_i_n_1100, + CFGTRANSACTIONADDR(2) => pcie_block_i_n_1101, + CFGTRANSACTIONADDR(1) => pcie_block_i_n_1102, + CFGTRANSACTIONADDR(0) => pcie_block_i_n_1103, + CFGTRANSACTIONTYPE => pcie_block_i_n_85, + CFGTRNPENDINGN => pcie_block_i_i_28_n_0, + CFGVCTCVCMAP(6 downto 0) => cfg_vc_tcvc_map(6 downto 0), + CFGVENDID(15 downto 0) => B"0001000011101110", + CMRSTN => '1', + CMSTICKYRSTN => '1', + DBGMODE(1 downto 0) => B"00", + DBGSCLRA => pcie_block_i_n_86, + DBGSCLRB => pcie_block_i_n_87, + DBGSCLRC => pcie_block_i_n_88, + DBGSCLRD => pcie_block_i_n_89, + DBGSCLRE => pcie_block_i_n_90, + DBGSCLRF => pcie_block_i_n_91, + DBGSCLRG => pcie_block_i_n_92, + DBGSCLRH => pcie_block_i_n_93, + DBGSCLRI => pcie_block_i_n_94, + DBGSCLRJ => pcie_block_i_n_95, + DBGSCLRK => pcie_block_i_n_96, + DBGSUBMODE => '0', + DBGVECA(63) => pcie_block_i_n_704, + DBGVECA(62) => pcie_block_i_n_705, + DBGVECA(61) => pcie_block_i_n_706, + DBGVECA(60) => pcie_block_i_n_707, + DBGVECA(59) => pcie_block_i_n_708, + DBGVECA(58) => pcie_block_i_n_709, + DBGVECA(57) => pcie_block_i_n_710, + DBGVECA(56) => pcie_block_i_n_711, + DBGVECA(55) => pcie_block_i_n_712, + DBGVECA(54) => pcie_block_i_n_713, + DBGVECA(53) => pcie_block_i_n_714, + DBGVECA(52) => pcie_block_i_n_715, + DBGVECA(51) => pcie_block_i_n_716, + DBGVECA(50) => pcie_block_i_n_717, + DBGVECA(49) => pcie_block_i_n_718, + DBGVECA(48) => pcie_block_i_n_719, + DBGVECA(47) => pcie_block_i_n_720, + DBGVECA(46) => pcie_block_i_n_721, + DBGVECA(45) => pcie_block_i_n_722, + DBGVECA(44) => pcie_block_i_n_723, + DBGVECA(43) => pcie_block_i_n_724, + DBGVECA(42) => pcie_block_i_n_725, + DBGVECA(41) => pcie_block_i_n_726, + DBGVECA(40) => pcie_block_i_n_727, + DBGVECA(39) => pcie_block_i_n_728, + DBGVECA(38) => pcie_block_i_n_729, + DBGVECA(37) => pcie_block_i_n_730, + DBGVECA(36) => pcie_block_i_n_731, + DBGVECA(35) => pcie_block_i_n_732, + DBGVECA(34) => pcie_block_i_n_733, + DBGVECA(33) => pcie_block_i_n_734, + DBGVECA(32) => pcie_block_i_n_735, + DBGVECA(31) => pcie_block_i_n_736, + DBGVECA(30) => pcie_block_i_n_737, + DBGVECA(29) => pcie_block_i_n_738, + DBGVECA(28) => pcie_block_i_n_739, + DBGVECA(27) => pcie_block_i_n_740, + DBGVECA(26) => pcie_block_i_n_741, + DBGVECA(25) => pcie_block_i_n_742, + DBGVECA(24) => pcie_block_i_n_743, + DBGVECA(23) => pcie_block_i_n_744, + DBGVECA(22) => pcie_block_i_n_745, + DBGVECA(21) => pcie_block_i_n_746, + DBGVECA(20) => pcie_block_i_n_747, + DBGVECA(19) => pcie_block_i_n_748, + DBGVECA(18) => pcie_block_i_n_749, + DBGVECA(17) => pcie_block_i_n_750, + DBGVECA(16) => pcie_block_i_n_751, + DBGVECA(15) => pcie_block_i_n_752, + DBGVECA(14) => pcie_block_i_n_753, + DBGVECA(13) => pcie_block_i_n_754, + DBGVECA(12) => pcie_block_i_n_755, + DBGVECA(11) => pcie_block_i_n_756, + DBGVECA(10) => pcie_block_i_n_757, + DBGVECA(9) => pcie_block_i_n_758, + DBGVECA(8) => pcie_block_i_n_759, + DBGVECA(7) => pcie_block_i_n_760, + DBGVECA(6) => pcie_block_i_n_761, + DBGVECA(5) => pcie_block_i_n_762, + DBGVECA(4) => pcie_block_i_n_763, + DBGVECA(3) => pcie_block_i_n_764, + DBGVECA(2) => pcie_block_i_n_765, + DBGVECA(1) => pcie_block_i_n_766, + DBGVECA(0) => pcie_block_i_n_767, + DBGVECB(63) => pcie_block_i_n_768, + DBGVECB(62) => pcie_block_i_n_769, + DBGVECB(61) => pcie_block_i_n_770, + DBGVECB(60) => pcie_block_i_n_771, + DBGVECB(59) => pcie_block_i_n_772, + DBGVECB(58) => pcie_block_i_n_773, + DBGVECB(57) => pcie_block_i_n_774, + DBGVECB(56) => pcie_block_i_n_775, + DBGVECB(55) => pcie_block_i_n_776, + DBGVECB(54) => pcie_block_i_n_777, + DBGVECB(53) => pcie_block_i_n_778, + DBGVECB(52) => pcie_block_i_n_779, + DBGVECB(51) => pcie_block_i_n_780, + DBGVECB(50) => pcie_block_i_n_781, + DBGVECB(49) => pcie_block_i_n_782, + DBGVECB(48) => pcie_block_i_n_783, + DBGVECB(47) => pcie_block_i_n_784, + DBGVECB(46) => pcie_block_i_n_785, + DBGVECB(45) => pcie_block_i_n_786, + DBGVECB(44) => pcie_block_i_n_787, + DBGVECB(43) => pcie_block_i_n_788, + DBGVECB(42) => pcie_block_i_n_789, + DBGVECB(41) => pcie_block_i_n_790, + DBGVECB(40) => pcie_block_i_n_791, + DBGVECB(39) => pcie_block_i_n_792, + DBGVECB(38) => pcie_block_i_n_793, + DBGVECB(37) => pcie_block_i_n_794, + DBGVECB(36) => pcie_block_i_n_795, + DBGVECB(35) => pcie_block_i_n_796, + DBGVECB(34) => pcie_block_i_n_797, + DBGVECB(33) => pcie_block_i_n_798, + DBGVECB(32) => pcie_block_i_n_799, + DBGVECB(31) => pcie_block_i_n_800, + DBGVECB(30) => pcie_block_i_n_801, + DBGVECB(29) => pcie_block_i_n_802, + DBGVECB(28) => pcie_block_i_n_803, + DBGVECB(27) => pcie_block_i_n_804, + DBGVECB(26) => pcie_block_i_n_805, + DBGVECB(25) => pcie_block_i_n_806, + DBGVECB(24) => pcie_block_i_n_807, + DBGVECB(23) => pcie_block_i_n_808, + DBGVECB(22) => pcie_block_i_n_809, + DBGVECB(21) => pcie_block_i_n_810, + DBGVECB(20) => pcie_block_i_n_811, + DBGVECB(19) => pcie_block_i_n_812, + DBGVECB(18) => pcie_block_i_n_813, + DBGVECB(17) => pcie_block_i_n_814, + DBGVECB(16) => pcie_block_i_n_815, + DBGVECB(15) => pcie_block_i_n_816, + DBGVECB(14) => pcie_block_i_n_817, + DBGVECB(13) => pcie_block_i_n_818, + DBGVECB(12) => pcie_block_i_n_819, + DBGVECB(11) => pcie_block_i_n_820, + DBGVECB(10) => pcie_block_i_n_821, + DBGVECB(9) => pcie_block_i_n_822, + DBGVECB(8) => pcie_block_i_n_823, + DBGVECB(7) => pcie_block_i_n_824, + DBGVECB(6) => pcie_block_i_n_825, + DBGVECB(5) => pcie_block_i_n_826, + DBGVECB(4) => pcie_block_i_n_827, + DBGVECB(3) => pcie_block_i_n_828, + DBGVECB(2) => pcie_block_i_n_829, + DBGVECB(1) => pcie_block_i_n_830, + DBGVECB(0) => pcie_block_i_n_831, + DBGVECC(11) => pcie_block_i_n_172, + DBGVECC(10) => pcie_block_i_n_173, + DBGVECC(9) => pcie_block_i_n_174, + DBGVECC(8) => pcie_block_i_n_175, + DBGVECC(7) => pcie_block_i_n_176, + DBGVECC(6) => pcie_block_i_n_177, + DBGVECC(5) => pcie_block_i_n_178, + DBGVECC(4) => pcie_block_i_n_179, + DBGVECC(3) => pcie_block_i_n_180, + DBGVECC(2) => pcie_block_i_n_181, + DBGVECC(1) => pcie_block_i_n_182, + DBGVECC(0) => pcie_block_i_n_183, + DLRSTN => '1', + DRPADDR(8 downto 0) => pcie_drp_addr(8 downto 0), + DRPCLK => pcie_drp_clk, + DRPDI(15 downto 0) => pcie_drp_di(15 downto 0), + DRPDO(15 downto 0) => pcie_drp_do(15 downto 0), + DRPEN => pcie_drp_en, + DRPRDY => pcie_drp_rdy, + DRPWE => pcie_drp_we, + FUNCLVLRSTN => '1', + LL2BADDLLPERR => pcie_block_i_n_98, + LL2BADTLPERR => pcie_block_i_n_99, + LL2LINKSTATUS(4) => pcie_block_i_n_687, + LL2LINKSTATUS(3) => pcie_block_i_n_688, + LL2LINKSTATUS(2) => pcie_block_i_n_689, + LL2LINKSTATUS(1) => pcie_block_i_n_690, + LL2LINKSTATUS(0) => pcie_block_i_n_691, + LL2PROTOCOLERR => pcie_block_i_n_100, + LL2RECEIVERERR => pcie_block_i_n_101, + LL2REPLAYROERR => pcie_block_i_n_102, + LL2REPLAYTOERR => pcie_block_i_n_103, + LL2SENDASREQL1 => '0', + LL2SENDENTERL1 => '0', + LL2SENDENTERL23 => '0', + LL2SENDPMACK => '0', + LL2SUSPENDNOW => '0', + LL2SUSPENDOK => pcie_block_i_n_104, + LL2TFCINIT1SEQ => pcie_block_i_n_105, + LL2TFCINIT2SEQ => pcie_block_i_n_106, + LL2TLPRCV => '0', + LL2TXIDLE => pcie_block_i_n_107, + LNKCLKEN => pcie_block_i_n_108, + MIMRXRADDR(12 downto 0) => mim_rx_raddr(12 downto 0), + MIMRXRDATA(67 downto 0) => mim_rx_rdata(67 downto 0), + MIMRXREN => mim_rx_ren, + MIMRXWADDR(12 downto 0) => mim_rx_waddr(12 downto 0), + MIMRXWDATA(67 downto 0) => mim_rx_wdata(67 downto 0), + MIMRXWEN => mim_rx_wen, + MIMTXRADDR(12 downto 0) => mim_tx_raddr(12 downto 0), + MIMTXRDATA(68 downto 0) => mim_tx_rdata(68 downto 0), + MIMTXREN => mim_tx_ren, + MIMTXWADDR(12 downto 0) => mim_tx_waddr(12 downto 0), + MIMTXWDATA(68 downto 0) => mim_tx_wdata(68 downto 0), + MIMTXWEN => mim_tx_wen, + PIPECLK => pipe_pclk_in, + PIPERX0CHANISALIGNED => pipe_rx0_chanisaligned, + PIPERX0CHARISK(1 downto 0) => cfg_aer_ecrc_check_en_4(1 downto 0), + PIPERX0DATA(15 downto 0) => Q(15 downto 0), + PIPERX0ELECIDLE => pipe_rx0_elec_idle, + PIPERX0PHYSTATUS => pipe_rx0_phy_status, + PIPERX0POLARITY => pipe_rx0_polarity, + PIPERX0STATUS(2 downto 0) => cfg_aer_ecrc_check_en_8(2 downto 0), + PIPERX0VALID => pipe_rx0_valid, + PIPERX1CHANISALIGNED => pipe_rx1_chanisaligned, + PIPERX1CHARISK(1 downto 0) => cfg_aer_ecrc_check_en_5(1 downto 0), + PIPERX1DATA(15 downto 0) => cfg_aer_ecrc_check_en_1(15 downto 0), + PIPERX1ELECIDLE => pipe_rx1_elec_idle, + PIPERX1PHYSTATUS => pipe_rx1_phy_status, + PIPERX1POLARITY => pipe_rx1_polarity, + PIPERX1STATUS(2 downto 0) => cfg_aer_ecrc_check_en_9(2 downto 0), + PIPERX1VALID => pipe_rx1_valid, + PIPERX2CHANISALIGNED => pipe_rx2_chanisaligned, + PIPERX2CHARISK(1 downto 0) => cfg_aer_ecrc_check_en_6(1 downto 0), + PIPERX2DATA(15 downto 0) => cfg_aer_ecrc_check_en_2(15 downto 0), + PIPERX2ELECIDLE => pipe_rx2_elec_idle, + PIPERX2PHYSTATUS => pipe_rx2_phy_status, + PIPERX2POLARITY => pipe_rx2_polarity, + PIPERX2STATUS(2 downto 0) => cfg_aer_ecrc_check_en_10(2 downto 0), + PIPERX2VALID => pipe_rx2_valid, + PIPERX3CHANISALIGNED => pipe_rx3_chanisaligned, + PIPERX3CHARISK(1 downto 0) => cfg_aer_ecrc_check_en_7(1 downto 0), + PIPERX3DATA(15 downto 0) => cfg_aer_ecrc_check_en_3(15 downto 0), + PIPERX3ELECIDLE => pipe_rx3_elec_idle, + PIPERX3PHYSTATUS => pipe_rx3_phy_status, + PIPERX3POLARITY => pipe_rx3_polarity, + PIPERX3STATUS(2 downto 0) => cfg_aer_ecrc_check_en_11(2 downto 0), + PIPERX3VALID => pipe_rx3_valid, + PIPERX4CHANISALIGNED => '0', + PIPERX4CHARISK(1 downto 0) => B"00", + PIPERX4DATA(15 downto 0) => B"0000000000000000", + PIPERX4ELECIDLE => '1', + PIPERX4PHYSTATUS => '0', + PIPERX4POLARITY => pipe_rx4_polarity, + PIPERX4STATUS(2 downto 0) => B"000", + PIPERX4VALID => '0', + PIPERX5CHANISALIGNED => '0', + PIPERX5CHARISK(1 downto 0) => B"00", + PIPERX5DATA(15 downto 0) => B"0000000000000000", + PIPERX5ELECIDLE => '1', + PIPERX5PHYSTATUS => '0', + PIPERX5POLARITY => pipe_rx5_polarity, + PIPERX5STATUS(2 downto 0) => B"000", + PIPERX5VALID => '0', + PIPERX6CHANISALIGNED => '0', + PIPERX6CHARISK(1 downto 0) => B"00", + PIPERX6DATA(15 downto 0) => B"0000000000000000", + PIPERX6ELECIDLE => '1', + PIPERX6PHYSTATUS => '0', + PIPERX6POLARITY => pipe_rx6_polarity, + PIPERX6STATUS(2 downto 0) => B"000", + PIPERX6VALID => '0', + PIPERX7CHANISALIGNED => '0', + PIPERX7CHARISK(1 downto 0) => B"00", + PIPERX7DATA(15 downto 0) => B"0000000000000000", + PIPERX7ELECIDLE => '1', + PIPERX7PHYSTATUS => '0', + PIPERX7POLARITY => pipe_rx7_polarity, + PIPERX7STATUS(2 downto 0) => B"000", + PIPERX7VALID => '0', + PIPETX0CHARISK(1 downto 0) => pipe_tx0_char_is_k(1 downto 0), + PIPETX0COMPLIANCE => pipe_tx0_compliance, + PIPETX0DATA(15 downto 0) => pipe_tx0_data(15 downto 0), + PIPETX0ELECIDLE => pipe_tx0_elec_idle, + PIPETX0POWERDOWN(1 downto 0) => pipe_tx0_powerdown(1 downto 0), + PIPETX1CHARISK(1 downto 0) => pipe_tx1_char_is_k(1 downto 0), + PIPETX1COMPLIANCE => pipe_tx1_compliance, + PIPETX1DATA(15 downto 0) => pipe_tx1_data(15 downto 0), + PIPETX1ELECIDLE => pipe_tx1_elec_idle, + PIPETX1POWERDOWN(1 downto 0) => pipe_tx1_powerdown(1 downto 0), + PIPETX2CHARISK(1 downto 0) => pipe_tx2_char_is_k(1 downto 0), + PIPETX2COMPLIANCE => pipe_tx2_compliance, + PIPETX2DATA(15 downto 0) => pipe_tx2_data(15 downto 0), + PIPETX2ELECIDLE => pipe_tx2_elec_idle, + PIPETX2POWERDOWN(1 downto 0) => pipe_tx2_powerdown(1 downto 0), + PIPETX3CHARISK(1 downto 0) => pipe_tx3_char_is_k(1 downto 0), + PIPETX3COMPLIANCE => pipe_tx3_compliance, + PIPETX3DATA(15 downto 0) => pipe_tx3_data(15 downto 0), + PIPETX3ELECIDLE => pipe_tx3_elec_idle, + PIPETX3POWERDOWN(1 downto 0) => pipe_tx3_powerdown(1 downto 0), + PIPETX4CHARISK(1 downto 0) => pipe_tx4_char_is_k(1 downto 0), + PIPETX4COMPLIANCE => pipe_tx4_compliance, + PIPETX4DATA(15 downto 0) => pipe_tx4_data(15 downto 0), + PIPETX4ELECIDLE => pipe_tx4_elec_idle, + PIPETX4POWERDOWN(1 downto 0) => pipe_tx4_powerdown(1 downto 0), + PIPETX5CHARISK(1 downto 0) => pipe_tx5_char_is_k(1 downto 0), + PIPETX5COMPLIANCE => pipe_tx5_compliance, + PIPETX5DATA(15 downto 0) => pipe_tx5_data(15 downto 0), + PIPETX5ELECIDLE => pipe_tx5_elec_idle, + PIPETX5POWERDOWN(1 downto 0) => pipe_tx5_powerdown(1 downto 0), + PIPETX6CHARISK(1 downto 0) => pipe_tx6_char_is_k(1 downto 0), + PIPETX6COMPLIANCE => pipe_tx6_compliance, + PIPETX6DATA(15 downto 0) => pipe_tx6_data(15 downto 0), + PIPETX6ELECIDLE => pipe_tx6_elec_idle, + PIPETX6POWERDOWN(1 downto 0) => pipe_tx6_powerdown(1 downto 0), + PIPETX7CHARISK(1 downto 0) => pipe_tx7_char_is_k(1 downto 0), + PIPETX7COMPLIANCE => pipe_tx7_compliance, + PIPETX7DATA(15 downto 0) => pipe_tx7_data(15 downto 0), + PIPETX7ELECIDLE => pipe_tx7_elec_idle, + PIPETX7POWERDOWN(1 downto 0) => pipe_tx7_powerdown(1 downto 0), + PIPETXDEEMPH => pipe_tx_deemph, + PIPETXMARGIN(2 downto 0) => pipe_tx_margin(2 downto 0), + PIPETXRATE => pipe_tx_rate, + PIPETXRCVRDET => pipe_tx_rcvr_det, + PIPETXRESET => pcie_block_i_n_140, + PL2DIRECTEDLSTATE(4 downto 0) => B"00000", + PL2L0REQ => pcie_block_i_n_141, + PL2LINKUP => pcie_block_i_n_142, + PL2RECEIVERERR => pcie_block_i_n_143, + PL2RECOVERY => pcie_block_i_n_144, + PL2RXELECIDLE => pcie_block_i_n_145, + PL2RXPMSTATE(1) => pcie_block_i_n_610, + PL2RXPMSTATE(0) => pcie_block_i_n_611, + PL2SUSPENDOK => pcie_block_i_n_146, + PLDBGMODE(2 downto 0) => B"000", + PLDBGVEC(11) => pcie_block_i_n_184, + PLDBGVEC(10) => pcie_block_i_n_185, + PLDBGVEC(9) => pcie_block_i_n_186, + PLDBGVEC(8) => pcie_block_i_n_187, + PLDBGVEC(7) => pcie_block_i_n_188, + PLDBGVEC(6) => pcie_block_i_n_189, + PLDBGVEC(5) => pcie_block_i_n_190, + PLDBGVEC(4) => pcie_block_i_n_191, + PLDBGVEC(3) => pcie_block_i_n_192, + PLDBGVEC(2) => pcie_block_i_n_193, + PLDBGVEC(1) => pcie_block_i_n_194, + PLDBGVEC(0) => pcie_block_i_n_195, + PLDIRECTEDCHANGEDONE => pl_directed_change_done, + PLDIRECTEDLINKAUTON => pl_directed_link_auton, + PLDIRECTEDLINKCHANGE(1 downto 0) => pl_directed_link_change(1 downto 0), + PLDIRECTEDLINKSPEED => pl_directed_link_speed, + PLDIRECTEDLINKWIDTH(1 downto 0) => pl_directed_link_width(1 downto 0), + PLDIRECTEDLTSSMNEW(5 downto 0) => B"000000", + PLDIRECTEDLTSSMNEWVLD => '0', + PLDIRECTEDLTSSMSTALL => '0', + PLDOWNSTREAMDEEMPHSOURCE => pl_downstream_deemph_source, + PLINITIALLINKWIDTH(2 downto 0) => pl_initial_link_width(2 downto 0), + PLLANEREVERSALMODE(1 downto 0) => pl_lane_reversal_mode(1 downto 0), + PLLINKGEN2CAP => pl_link_gen2_cap, + PLLINKPARTNERGEN2SUPPORTED => pl_link_partner_gen2_supported, + PLLINKUPCFGCAP => pl_link_upcfg_cap, + PLLTSSMSTATE(5 downto 0) => pl_ltssm_state(5 downto 0), + PLPHYLNKUPN => pl_phy_lnk_up_n, + PLRECEIVEDHOTRST => pl_received_hot_rst, + PLRSTN => '1', + PLRXPMSTATE(1 downto 0) => pl_rx_pm_state(1 downto 0), + PLSELLNKRATE => pl_sel_lnk_rate, + PLSELLNKWIDTH(1 downto 0) => pl_sel_lnk_width(1 downto 0), + PLTRANSMITHOTRST => pl_transmit_hot_rst, + PLTXPMSTATE(2 downto 0) => pl_tx_pm_state(2 downto 0), + PLUPSTREAMPREFERDEEMPH => pl_upstream_prefer_deemph, + RECEIVEDFUNCLVLRSTN => cfg_received_func_lvl_rst_n, + SYSRSTN => sys_rst_n, + TL2ASPMSUSPENDCREDITCHECK => '0', + TL2ASPMSUSPENDCREDITCHECKOK => pcie_block_i_n_155, + TL2ASPMSUSPENDREQ => pcie_block_i_n_156, + TL2ERRFCPE => pcie_block_i_n_157, + TL2ERRHDR(63) => pcie_block_i_n_832, + TL2ERRHDR(62) => pcie_block_i_n_833, + TL2ERRHDR(61) => pcie_block_i_n_834, + TL2ERRHDR(60) => pcie_block_i_n_835, + TL2ERRHDR(59) => pcie_block_i_n_836, + TL2ERRHDR(58) => pcie_block_i_n_837, + TL2ERRHDR(57) => pcie_block_i_n_838, + TL2ERRHDR(56) => pcie_block_i_n_839, + TL2ERRHDR(55) => pcie_block_i_n_840, + TL2ERRHDR(54) => pcie_block_i_n_841, + TL2ERRHDR(53) => pcie_block_i_n_842, + TL2ERRHDR(52) => pcie_block_i_n_843, + TL2ERRHDR(51) => pcie_block_i_n_844, + TL2ERRHDR(50) => pcie_block_i_n_845, + TL2ERRHDR(49) => pcie_block_i_n_846, + TL2ERRHDR(48) => pcie_block_i_n_847, + TL2ERRHDR(47) => pcie_block_i_n_848, + TL2ERRHDR(46) => pcie_block_i_n_849, + TL2ERRHDR(45) => pcie_block_i_n_850, + TL2ERRHDR(44) => pcie_block_i_n_851, + TL2ERRHDR(43) => pcie_block_i_n_852, + TL2ERRHDR(42) => pcie_block_i_n_853, + TL2ERRHDR(41) => pcie_block_i_n_854, + TL2ERRHDR(40) => pcie_block_i_n_855, + TL2ERRHDR(39) => pcie_block_i_n_856, + TL2ERRHDR(38) => pcie_block_i_n_857, + TL2ERRHDR(37) => pcie_block_i_n_858, + TL2ERRHDR(36) => pcie_block_i_n_859, + TL2ERRHDR(35) => pcie_block_i_n_860, + TL2ERRHDR(34) => pcie_block_i_n_861, + TL2ERRHDR(33) => pcie_block_i_n_862, + TL2ERRHDR(32) => pcie_block_i_n_863, + TL2ERRHDR(31) => pcie_block_i_n_864, + TL2ERRHDR(30) => pcie_block_i_n_865, + TL2ERRHDR(29) => pcie_block_i_n_866, + TL2ERRHDR(28) => pcie_block_i_n_867, + TL2ERRHDR(27) => pcie_block_i_n_868, + TL2ERRHDR(26) => pcie_block_i_n_869, + TL2ERRHDR(25) => pcie_block_i_n_870, + TL2ERRHDR(24) => pcie_block_i_n_871, + TL2ERRHDR(23) => pcie_block_i_n_872, + TL2ERRHDR(22) => pcie_block_i_n_873, + TL2ERRHDR(21) => pcie_block_i_n_874, + TL2ERRHDR(20) => pcie_block_i_n_875, + TL2ERRHDR(19) => pcie_block_i_n_876, + TL2ERRHDR(18) => pcie_block_i_n_877, + TL2ERRHDR(17) => pcie_block_i_n_878, + TL2ERRHDR(16) => pcie_block_i_n_879, + TL2ERRHDR(15) => pcie_block_i_n_880, + TL2ERRHDR(14) => pcie_block_i_n_881, + TL2ERRHDR(13) => pcie_block_i_n_882, + TL2ERRHDR(12) => pcie_block_i_n_883, + TL2ERRHDR(11) => pcie_block_i_n_884, + TL2ERRHDR(10) => pcie_block_i_n_885, + TL2ERRHDR(9) => pcie_block_i_n_886, + TL2ERRHDR(8) => pcie_block_i_n_887, + TL2ERRHDR(7) => pcie_block_i_n_888, + TL2ERRHDR(6) => pcie_block_i_n_889, + TL2ERRHDR(5) => pcie_block_i_n_890, + TL2ERRHDR(4) => pcie_block_i_n_891, + TL2ERRHDR(3) => pcie_block_i_n_892, + TL2ERRHDR(2) => pcie_block_i_n_893, + TL2ERRHDR(1) => pcie_block_i_n_894, + TL2ERRHDR(0) => pcie_block_i_n_895, + TL2ERRMALFORMED => pcie_block_i_n_158, + TL2ERRRXOVERFLOW => pcie_block_i_n_159, + TL2PPMSUSPENDOK => pcie_block_i_n_160, + TL2PPMSUSPENDREQ => '0', + TLRSTN => '1', + TRNFCCPLD(11 downto 0) => fc_cpld(11 downto 0), + TRNFCCPLH(7 downto 0) => fc_cplh(7 downto 0), + TRNFCNPD(11 downto 0) => fc_npd(11 downto 0), + TRNFCNPH(7 downto 0) => fc_nph(7 downto 0), + TRNFCPD(11 downto 0) => fc_pd(11 downto 0), + TRNFCPH(7 downto 0) => fc_ph(7 downto 0), + TRNFCSEL(2 downto 0) => fc_sel(2 downto 0), + TRNLNKUP => trn_lnk_up, + TRNRBARHIT(7) => pcie_block_i_n_1143, + TRNRBARHIT(6 downto 0) => trn_rbar_hit(6 downto 0), + TRNRD(127 downto 64) => trn_rd(127 downto 64), + TRNRD(63 downto 0) => pcie_drp_clk_1(63 downto 0), + TRNRDLLPDATA(63) => pcie_block_i_n_896, + TRNRDLLPDATA(62) => pcie_block_i_n_897, + TRNRDLLPDATA(61) => pcie_block_i_n_898, + TRNRDLLPDATA(60) => pcie_block_i_n_899, + TRNRDLLPDATA(59) => pcie_block_i_n_900, + TRNRDLLPDATA(58) => pcie_block_i_n_901, + TRNRDLLPDATA(57) => pcie_block_i_n_902, + TRNRDLLPDATA(56) => pcie_block_i_n_903, + TRNRDLLPDATA(55) => pcie_block_i_n_904, + TRNRDLLPDATA(54) => pcie_block_i_n_905, + TRNRDLLPDATA(53) => pcie_block_i_n_906, + TRNRDLLPDATA(52) => pcie_block_i_n_907, + TRNRDLLPDATA(51) => pcie_block_i_n_908, + TRNRDLLPDATA(50) => pcie_block_i_n_909, + TRNRDLLPDATA(49) => pcie_block_i_n_910, + TRNRDLLPDATA(48) => pcie_block_i_n_911, + TRNRDLLPDATA(47) => pcie_block_i_n_912, + TRNRDLLPDATA(46) => pcie_block_i_n_913, + TRNRDLLPDATA(45) => pcie_block_i_n_914, + TRNRDLLPDATA(44) => pcie_block_i_n_915, + TRNRDLLPDATA(43) => pcie_block_i_n_916, + TRNRDLLPDATA(42) => pcie_block_i_n_917, + TRNRDLLPDATA(41) => pcie_block_i_n_918, + TRNRDLLPDATA(40) => pcie_block_i_n_919, + TRNRDLLPDATA(39) => pcie_block_i_n_920, + TRNRDLLPDATA(38) => pcie_block_i_n_921, + TRNRDLLPDATA(37) => pcie_block_i_n_922, + TRNRDLLPDATA(36) => pcie_block_i_n_923, + TRNRDLLPDATA(35) => pcie_block_i_n_924, + TRNRDLLPDATA(34) => pcie_block_i_n_925, + TRNRDLLPDATA(33) => pcie_block_i_n_926, + TRNRDLLPDATA(32) => pcie_block_i_n_927, + TRNRDLLPDATA(31) => pcie_block_i_n_928, + TRNRDLLPDATA(30) => pcie_block_i_n_929, + TRNRDLLPDATA(29) => pcie_block_i_n_930, + TRNRDLLPDATA(28) => pcie_block_i_n_931, + TRNRDLLPDATA(27) => pcie_block_i_n_932, + TRNRDLLPDATA(26) => pcie_block_i_n_933, + TRNRDLLPDATA(25) => pcie_block_i_n_934, + TRNRDLLPDATA(24) => pcie_block_i_n_935, + TRNRDLLPDATA(23) => pcie_block_i_n_936, + TRNRDLLPDATA(22) => pcie_block_i_n_937, + TRNRDLLPDATA(21) => pcie_block_i_n_938, + TRNRDLLPDATA(20) => pcie_block_i_n_939, + TRNRDLLPDATA(19) => pcie_block_i_n_940, + TRNRDLLPDATA(18) => pcie_block_i_n_941, + TRNRDLLPDATA(17) => pcie_block_i_n_942, + TRNRDLLPDATA(16) => pcie_block_i_n_943, + TRNRDLLPDATA(15) => pcie_block_i_n_944, + TRNRDLLPDATA(14) => pcie_block_i_n_945, + TRNRDLLPDATA(13) => pcie_block_i_n_946, + TRNRDLLPDATA(12) => pcie_block_i_n_947, + TRNRDLLPDATA(11) => pcie_block_i_n_948, + TRNRDLLPDATA(10) => pcie_block_i_n_949, + TRNRDLLPDATA(9) => pcie_block_i_n_950, + TRNRDLLPDATA(8) => pcie_block_i_n_951, + TRNRDLLPDATA(7) => pcie_block_i_n_952, + TRNRDLLPDATA(6) => pcie_block_i_n_953, + TRNRDLLPDATA(5) => pcie_block_i_n_954, + TRNRDLLPDATA(4) => pcie_block_i_n_955, + TRNRDLLPDATA(3) => pcie_block_i_n_956, + TRNRDLLPDATA(2) => pcie_block_i_n_957, + TRNRDLLPDATA(1) => pcie_block_i_n_958, + TRNRDLLPDATA(0) => pcie_block_i_n_959, + TRNRDLLPSRCRDY(1) => pcie_block_i_n_618, + TRNRDLLPSRCRDY(0) => pcie_block_i_n_619, + TRNRDSTRDY => trn_rdst_rdy, + TRNRECRCERR => trn_recrc_err, + TRNREOF => \^trn_reof\, + TRNRERRFWD => trn_rerrfwd, + TRNRFCPRET => '1', + TRNRNPOK => rx_np_ok, + TRNRNPREQ => rx_np_req, + TRNRREM(1) => trn_rrem(1), + TRNRREM(0) => pcie_drp_clk_2(0), + TRNRSOF => \^trn_rsof\, + TRNRSRCDSC => \^trn_rsrc_dsc\, + TRNRSRCRDY => trn_rsrc_rdy, + TRNTBUFAV(5 downto 0) => \^trn_tbuf_av\(5 downto 0), + TRNTCFGGNT => trn_tcfg_gnt, + TRNTCFGREQ => \^trn_tcfg_req\, + TRNTD(127 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000", + TRNTD(63 downto 0) => trn_td(63 downto 0), + TRNTDLLPDATA(31 downto 0) => B"00000000000000000000000000000000", + TRNTDLLPDSTRDY => pcie_block_i_n_169, + TRNTDLLPSRCRDY => '0', + TRNTDSTRDY(3 downto 1) => NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED(3 downto 1), + TRNTDSTRDY(0) => \^trn_tdst_rdy\, + TRNTECRCGEN => cfg_aer_ecrc_check_en_0(0), + TRNTEOF => trn_teof, + TRNTERRDROP => tx_err_drop, + TRNTERRFWD => cfg_aer_ecrc_check_en_0(1), + TRNTREM(1) => '0', + TRNTREM(0) => trn_trem(0), + TRNTSOF => trn_tsof, + TRNTSRCDSC => cfg_aer_ecrc_check_en_0(3), + TRNTSRCRDY => trn_tsrc_rdy, + TRNTSTR => cfg_aer_ecrc_check_en_0(2), + USERCLK => pipe_userclk1_in, + USERCLK2 => pipe_userclk2_in, + USERRSTN => user_rst_n + ); +pcie_block_i_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_atomic_egress_blocked, + O => pcie_block_i_i_1_n_0 + ); +pcie_block_i_i_10: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_malformed, + O => pcie_block_i_i_10_n_0 + ); +pcie_block_i_i_11: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_mc_blocked, + O => pcie_block_i_i_11_n_0 + ); +pcie_block_i_i_12: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_norecovery, + O => pcie_block_i_i_12_n_0 + ); +pcie_block_i_i_13: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_poisoned, + O => pcie_block_i_i_13_n_0 + ); +pcie_block_i_i_14: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_posted, + O => pcie_block_i_i_14_n_0 + ); +pcie_block_i_i_15: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_ur, + O => pcie_block_i_i_15_n_0 + ); +pcie_block_i_i_16: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_interrupt_assert, + O => pcie_block_i_i_16_n_0 + ); +pcie_block_i_i_17: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_interrupt, + O => pcie_block_i_i_17_n_0 + ); +pcie_block_i_i_18: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_interrupt_stat, + O => pcie_block_i_i_18_n_0 + ); +pcie_block_i_i_19: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_mgmt_rd_en, + O => pcie_block_i_i_19_n_0 + ); +pcie_block_i_i_2: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_cor, + O => pcie_block_i_i_2_n_0 + ); +pcie_block_i_i_20: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_mgmt_wr_en, + O => pcie_block_i_i_20_n_0 + ); +pcie_block_i_i_21: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_mgmt_wr_readonly, + O => pcie_block_i_i_21_n_0 + ); +pcie_block_i_i_22: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_mgmt_wr_rw1c_as_rw, + O => pcie_block_i_i_22_n_0 + ); +pcie_block_i_i_23: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_pm_force_state_en, + O => pcie_block_i_i_23_n_0 + ); +pcie_block_i_i_24: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_pm_halt_aspm_l0s, + O => pcie_block_i_i_24_n_0 + ); +pcie_block_i_i_25: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_pm_halt_aspm_l1, + O => pcie_block_i_i_25_n_0 + ); +pcie_block_i_i_27: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_pm_wake, + O => pcie_block_i_i_27_n_0 + ); +pcie_block_i_i_28: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_trn_pending, + O => pcie_block_i_i_28_n_0 + ); +pcie_block_i_i_3: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_cpl_abort, + O => pcie_block_i_i_3_n_0 + ); +pcie_block_i_i_4: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_cpl_timeout, + O => pcie_block_i_i_4_n_0 + ); +pcie_block_i_i_5: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_cpl_unexpect, + O => pcie_block_i_i_5_n_0 + ); +pcie_block_i_i_6: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_ecrc, + O => pcie_block_i_i_6_n_0 + ); +pcie_block_i_i_7: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_internal_cor, + O => pcie_block_i_i_7_n_0 + ); +pcie_block_i_i_8: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_internal_uncor, + O => pcie_block_i_i_8_n_0 + ); +pcie_block_i_i_9: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_err_locked, + O => pcie_block_i_i_9_n_0 + ); +pcie_bram_top: entity work.pcie_7x_0_pcie_7x_0_pcie_bram_top_7x + port map ( + MIMRXRADDR(11 downto 0) => mim_rx_raddr(11 downto 0), + MIMRXWADDR(11 downto 0) => mim_rx_waddr(11 downto 0), + MIMTXRADDR(11 downto 0) => mim_tx_raddr(11 downto 0), + MIMTXWADDR(11 downto 0) => mim_tx_waddr(11 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(67 downto 0) => mim_rx_rdata(67 downto 0), + \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(67 downto 0) => mim_rx_wdata(67 downto 0), + mim_rx_ren => mim_rx_ren, + mim_rx_wen => mim_rx_wen, + mim_tx_ren => mim_tx_ren, + mim_tx_wen => mim_tx_wen, + pipe_userclk1_in => pipe_userclk1_in, + rdata(68 downto 0) => mim_tx_rdata(68 downto 0), + wdata(68 downto 0) => mim_tx_wdata(68 downto 0) + ); +phy_lnk_up_cdc_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => pl_phy_lnk_up_n, + O => src_in + ); +ppm_L1_thrtl_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEAAAA" + ) + port map ( + I0 => ppm_L1_trig, + I1 => \^cfg_pcie_link_state\(0), + I2 => \^cfg_pcie_link_state\(2), + I3 => \^cfg_pcie_link_state\(1), + I4 => ppm_L1_thrtl, + O => ppm_L1_thrtl_reg + ); +tbuf_av_min_thrtl_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \^trn_tbuf_av\(5), + I1 => \^trn_tbuf_av\(4), + I2 => \^trn_tbuf_av\(3), + I3 => \^trn_tbuf_av\(2), + I4 => \^trn_tbuf_av\(1), + O => tbuf_av_min_trig + ); +tready_thrtl_i_11: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000100010001" + ) + port map ( + I0 => \^trn_tbuf_av\(5), + I1 => \^trn_tbuf_av\(4), + I2 => \^trn_tbuf_av\(3), + I3 => \^trn_tbuf_av\(2), + I4 => \^trn_tbuf_av\(0), + I5 => \^trn_tbuf_av\(1), + O => pcie_drp_clk_0 + ); +tready_thrtl_i_9: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^trn_tcfg_req\, + I1 => reg_tcfg_gnt, + O => tcfg_req_trig + ); +trn_in_packet_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"08000000AEAA2AAA" + ) + port map ( + I0 => trn_in_packet, + I1 => trn_rdst_rdy, + I2 => \^trn_reof\, + I3 => trn_rsrc_rdy, + I4 => \^trn_rsof\, + I5 => \^trn_rsrc_dsc\, + O => trn_in_packet_reg + ); +trn_rsrc_dsc_prev_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^trn_rsrc_dsc\, + I1 => reg_dsc_detect, + O => trn_rsrc_dsc_prev0 + ); +trn_rsrc_rdy_prev_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"AA08" + ) + port map ( + I0 => trn_rsrc_rdy, + I1 => \^trn_rsof\, + I2 => \^trn_rsrc_dsc\, + I3 => trn_in_packet, + O => rsrc_rdy_filtered + ); +user_reset_int_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"2A" + ) + port map ( + I0 => bridge_reset_int, + I1 => pl_phy_lnk_up, + I2 => user_rst_n, + O => user_reset_int_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie_top is + port ( + m_axis_rx_tvalid_reg : out STD_LOGIC; + m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_rx_tlast : out STD_LOGIC; + trn_tcfg_req : out STD_LOGIC; + tready_thrtl_reg : out STD_LOGIC; + PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 3 downto 0 ); + PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_tx_rcvr_det_gt : out STD_LOGIC; + \pipe_stages_1.pipe_tx_rate_q_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_tx_deemph_gt : out STD_LOGIC; + user_reset_int_reg : out STD_LOGIC; + src_in : out STD_LOGIC; + cfg_mgmt_rd_wr_done : out STD_LOGIC; + cfg_err_aer_headerlog_set : out STD_LOGIC; + cfg_err_cpl_rdy : out STD_LOGIC; + cfg_interrupt_rdy : out STD_LOGIC; + cfg_msg_received : out STD_LOGIC; + cfg_received_func_lvl_rst : out STD_LOGIC; + cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 ); + trn_tbuf_av : out STD_LOGIC_VECTOR ( 5 downto 0 ); + cfg_to_turnoff : out STD_LOGIC; + cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 ); + PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 7 downto 0 ); + PIPE_TXDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 7 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_aer_ecrc_check_en : out STD_LOGIC; + cfg_aer_ecrc_gen_en : out STD_LOGIC; + cfg_aer_rooterr_corr_err_received : out STD_LOGIC; + cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_fatal_err_received : out STD_LOGIC; + cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC; + cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC; + cfg_bridge_serr_en : out STD_LOGIC; + cfg_command : out STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_dcommand2 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + cfg_dcommand : out STD_LOGIC_VECTOR ( 14 downto 0 ); + cfg_dstatus : out STD_LOGIC_VECTOR ( 3 downto 0 ); + cfg_interrupt_msienable : out STD_LOGIC; + cfg_interrupt_msixenable : out STD_LOGIC; + cfg_interrupt_msixfm : out STD_LOGIC; + cfg_lcommand : out STD_LOGIC_VECTOR ( 10 downto 0 ); + cfg_lstatus : out STD_LOGIC_VECTOR ( 9 downto 0 ); + cfg_msg_received_assert_int_a : out STD_LOGIC; + cfg_msg_received_assert_int_b : out STD_LOGIC; + cfg_msg_received_assert_int_c : out STD_LOGIC; + cfg_msg_received_assert_int_d : out STD_LOGIC; + cfg_msg_received_deassert_int_a : out STD_LOGIC; + cfg_msg_received_deassert_int_b : out STD_LOGIC; + cfg_msg_received_deassert_int_c : out STD_LOGIC; + cfg_msg_received_deassert_int_d : out STD_LOGIC; + cfg_msg_received_err_cor : out STD_LOGIC; + cfg_msg_received_err_fatal : out STD_LOGIC; + cfg_msg_received_err_non_fatal : out STD_LOGIC; + cfg_msg_received_pm_as_nak : out STD_LOGIC; + cfg_msg_received_pme_to_ack : out STD_LOGIC; + cfg_msg_received_pm_pme : out STD_LOGIC; + cfg_msg_received_setslotpowerlimit : out STD_LOGIC; + cfg_pmcsr_pme_en : out STD_LOGIC; + cfg_pmcsr_pme_status : out STD_LOGIC; + cfg_root_control_pme_int_en : out STD_LOGIC; + cfg_root_control_syserr_corr_err_en : out STD_LOGIC; + cfg_root_control_syserr_fatal_err_en : out STD_LOGIC; + cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC; + cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC; + pcie_drp_rdy : out STD_LOGIC; + pl_directed_change_done : out STD_LOGIC; + pl_link_gen2_cap : out STD_LOGIC; + pl_link_partner_gen2_supported : out STD_LOGIC; + pl_link_upcfg_cap : out STD_LOGIC; + pl_received_hot_rst : out STD_LOGIC; + pl_sel_lnk_rate : out STD_LOGIC; + trn_lnk_up : out STD_LOGIC; + tx_err_drop : out STD_LOGIC; + fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 ); + pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); + pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 ); + cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 ); + cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \throttle_ctl_pipeline.reg_tkeep_reg[7]\ : in STD_LOGIC; + pipe_userclk2_in : in STD_LOGIC; + tx_cfg_gnt : in STD_LOGIC; + cfg_turnoff_ok : in STD_LOGIC; + s_axis_tx_tlast : in STD_LOGIC; + s_axis_tx_tvalid : in STD_LOGIC; + s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rx1_valid_gt : in STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \pipe_stages_1.pipe_rx_phy_status_q_reg\ : in STD_LOGIC; + \pipe_stages_1.pipe_rx_elec_idle_q_reg\ : in STD_LOGIC; + pipe_rx2_valid_gt : in STD_LOGIC; + \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ : in STD_LOGIC; + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ : in STD_LOGIC; + pipe_rx3_valid_gt : in STD_LOGIC; + \pipe_stages_1.pipe_rx_phy_status_q_reg_1\ : in STD_LOGIC; + \pipe_stages_1.pipe_rx_elec_idle_q_reg_1\ : in STD_LOGIC; + pipe_rx0_valid_gt : in STD_LOGIC; + gt_rx_phy_status_q : in STD_LOGIC; + gt_rxelecidle_q : in STD_LOGIC; + bridge_reset_int : in STD_LOGIC; + pl_phy_lnk_up : in STD_LOGIC; + m_axis_rx_tready : in STD_LOGIC; + cfg_trn_pending : in STD_LOGIC; + cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC; + cfg_mgmt_wr_readonly : in STD_LOGIC; + cfg_mgmt_wr_en : in STD_LOGIC; + cfg_mgmt_rd_en : in STD_LOGIC; + cfg_err_malformed : in STD_LOGIC; + cfg_err_cor : in STD_LOGIC; + cfg_err_ur : in STD_LOGIC; + cfg_err_ecrc : in STD_LOGIC; + cfg_err_cpl_timeout : in STD_LOGIC; + cfg_err_cpl_abort : in STD_LOGIC; + cfg_err_cpl_unexpect : in STD_LOGIC; + cfg_err_poisoned : in STD_LOGIC; + cfg_err_atomic_egress_blocked : in STD_LOGIC; + cfg_err_mc_blocked : in STD_LOGIC; + cfg_err_internal_uncor : in STD_LOGIC; + cfg_err_internal_cor : in STD_LOGIC; + cfg_err_posted : in STD_LOGIC; + cfg_err_locked : in STD_LOGIC; + cfg_err_norecovery : in STD_LOGIC; + cfg_interrupt : in STD_LOGIC; + cfg_interrupt_assert : in STD_LOGIC; + cfg_interrupt_stat : in STD_LOGIC; + cfg_pm_halt_aspm_l0s : in STD_LOGIC; + cfg_pm_halt_aspm_l1 : in STD_LOGIC; + cfg_pm_force_state_en : in STD_LOGIC; + cfg_pm_wake : in STD_LOGIC; + \out\ : in STD_LOGIC; + s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ); + D : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pipe_stages_1.pipe_rx_data_q_reg[15]_2\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \pipe_stages_1.pipe_rx_status_q_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + pipe_userclk1_in : in STD_LOGIC; + pcie_drp_clk : in STD_LOGIC; + pcie_drp_en : in STD_LOGIC; + pcie_drp_we : in STD_LOGIC; + pl_directed_link_auton : in STD_LOGIC; + pl_directed_link_speed : in STD_LOGIC; + pl_downstream_deemph_source : in STD_LOGIC; + pl_transmit_hot_rst : in STD_LOGIC; + pl_upstream_prefer_deemph : in STD_LOGIC; + sys_rst_n : in STD_LOGIC; + rx_np_ok : in STD_LOGIC; + rx_np_req : in STD_LOGIC; + cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 ); + pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); + fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); + cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); + cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); + cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); + pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ) + ); +end pcie_7x_0_pcie_7x_0_pcie_top; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie_top is + signal \^cfg_msg_data\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \^cfg_pcie_link_state\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^cfg_to_turnoff\ : STD_LOGIC; + signal cfg_turnoff_ok_w : STD_LOGIC; + signal pcie_7x_i_n_13 : STD_LOGIC; + signal pcie_7x_i_n_22 : STD_LOGIC; + signal pcie_7x_i_n_30 : STD_LOGIC; + signal pcie_7x_i_n_6 : STD_LOGIC; + signal pcie_7x_i_n_9 : STD_LOGIC; + signal pipe_rx0_chanisaligned : STD_LOGIC; + signal pipe_rx0_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_rx0_data : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_rx0_elec_idle : STD_LOGIC; + signal pipe_rx0_phy_status : STD_LOGIC; + signal pipe_rx0_polarity : STD_LOGIC; + signal pipe_rx0_status : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal pipe_rx0_valid : STD_LOGIC; + signal pipe_rx1_chanisaligned : STD_LOGIC; + signal pipe_rx1_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_rx1_data : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_rx1_elec_idle : STD_LOGIC; + signal pipe_rx1_phy_status : STD_LOGIC; + signal pipe_rx1_polarity : STD_LOGIC; + signal pipe_rx1_status : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal pipe_rx1_valid : STD_LOGIC; + signal pipe_rx2_chanisaligned : STD_LOGIC; + signal pipe_rx2_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_rx2_data : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_rx2_elec_idle : STD_LOGIC; + signal pipe_rx2_phy_status : STD_LOGIC; + signal pipe_rx2_polarity : STD_LOGIC; + signal pipe_rx2_status : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal pipe_rx2_valid : STD_LOGIC; + signal pipe_rx3_chanisaligned : STD_LOGIC; + signal pipe_rx3_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_rx3_data : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_rx3_elec_idle : STD_LOGIC; + signal pipe_rx3_phy_status : STD_LOGIC; + signal pipe_rx3_polarity : STD_LOGIC; + signal pipe_rx3_status : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal pipe_rx3_valid : STD_LOGIC; + signal pipe_tx0_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx0_compliance : STD_LOGIC; + signal pipe_tx0_data : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_tx0_elec_idle : STD_LOGIC; + signal pipe_tx0_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx1_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx1_compliance : STD_LOGIC; + signal pipe_tx1_data : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_tx1_elec_idle : STD_LOGIC; + signal pipe_tx1_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx2_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx2_compliance : STD_LOGIC; + signal pipe_tx2_data : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_tx2_elec_idle : STD_LOGIC; + signal pipe_tx2_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx3_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx3_compliance : STD_LOGIC; + signal pipe_tx3_data : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_tx3_elec_idle : STD_LOGIC; + signal pipe_tx3_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx_deemph : STD_LOGIC; + signal pipe_tx_margin : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal pipe_tx_rate : STD_LOGIC; + signal pipe_tx_rcvr_det : STD_LOGIC; + signal \rx_inst/rx_pipeline_inst/dsc_detect\ : STD_LOGIC; + signal \rx_inst/rx_pipeline_inst/reg_dsc_detect\ : STD_LOGIC; + signal \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered\ : STD_LOGIC; + signal \rx_inst/rx_pipeline_inst/trn_in_packet\ : STD_LOGIC; + signal \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d\ : STD_LOGIC; + signal \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0\ : STD_LOGIC; + signal trn_rbar_hit : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal trn_rd : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal trn_rdst_rdy : STD_LOGIC; + signal trn_recrc_err : STD_LOGIC; + signal trn_reof : STD_LOGIC; + signal trn_rerrfwd : STD_LOGIC; + signal trn_rrem : STD_LOGIC_VECTOR ( 0 to 0 ); + signal trn_rsof : STD_LOGIC; + signal trn_rsrc_dsc : STD_LOGIC; + signal \^trn_tbuf_av\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal trn_tcfg_gnt : STD_LOGIC; + signal \^trn_tcfg_req\ : STD_LOGIC; + signal trn_td : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal trn_tdst_rdy : STD_LOGIC; + signal trn_tecrc_gen : STD_LOGIC; + signal trn_teof : STD_LOGIC; + signal trn_terrfwd : STD_LOGIC; + signal trn_trem : STD_LOGIC; + signal trn_tsof : STD_LOGIC; + signal trn_tsrc_dsc : STD_LOGIC; + signal trn_tsrc_rdy : STD_LOGIC; + signal trn_tstr : STD_LOGIC; + signal \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/lnk_up_thrtl\ : STD_LOGIC; + signal \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_thrtl\ : STD_LOGIC; + signal \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_trig\ : STD_LOGIC; + signal \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/reg_tcfg_gnt\ : STD_LOGIC; + signal \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tbuf_av_min_trig\ : STD_LOGIC; + signal \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tcfg_req_trig\ : STD_LOGIC; + signal \tx_inst/tx_pipeline_inst/reg_disable_trn2\ : STD_LOGIC; +begin + cfg_msg_data(15 downto 0) <= \^cfg_msg_data\(15 downto 0); + cfg_pcie_link_state(2 downto 0) <= \^cfg_pcie_link_state\(2 downto 0); + cfg_to_turnoff <= \^cfg_to_turnoff\; + trn_tbuf_av(5 downto 0) <= \^trn_tbuf_av\(5 downto 0); + trn_tcfg_req <= \^trn_tcfg_req\; +axi_basic_top: entity work.pcie_7x_0_pcie_7x_0_axi_basic_top + port map ( + E(0) => trn_rdst_rdy, + Q(63 downto 0) => m_axis_rx_tdata(63 downto 0), + cfg_pcie_link_state(2 downto 0) => \^cfg_pcie_link_state\(2 downto 0), + cfg_pm_turnoff_ok_n => cfg_turnoff_ok_w, + cfg_to_turnoff => \^cfg_to_turnoff\, + cfg_turnoff_ok => cfg_turnoff_ok, + dsc_detect => \rx_inst/rx_pipeline_inst/dsc_detect\, + lnk_up_thrtl => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/lnk_up_thrtl\, + lnk_up_thrtl_reg => pcie_7x_i_n_30, + m_axis_rx_tkeep(0) => m_axis_rx_tkeep(0), + m_axis_rx_tlast => m_axis_rx_tlast, + m_axis_rx_tready => m_axis_rx_tready, + m_axis_rx_tuser(12 downto 0) => m_axis_rx_tuser(12 downto 0), + m_axis_rx_tvalid_reg => m_axis_rx_tvalid_reg, + \out\ => \out\, + pipe_userclk2_in => pipe_userclk2_in, + ppm_L1_thrtl => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_thrtl\, + ppm_L1_thrtl_reg => pcie_7x_i_n_13, + ppm_L1_trig => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_trig\, + reg_dsc_detect => \rx_inst/rx_pipeline_inst/reg_dsc_detect\, + reg_tcfg_gnt => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/reg_tcfg_gnt\, + rsrc_rdy_filtered => \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered\, + s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0), + s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0), + s_axis_tx_tlast => s_axis_tx_tlast, + s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0), + s_axis_tx_tvalid => s_axis_tx_tvalid, + tbuf_av_min_trig => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tbuf_av_min_trig\, + tcfg_req_trig => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tcfg_req_trig\, + \throttle_ctl_pipeline.reg_tdata_reg[63]\(63 downto 32) => trn_td(31 downto 0), + \throttle_ctl_pipeline.reg_tdata_reg[63]\(31 downto 0) => trn_td(63 downto 32), + \throttle_ctl_pipeline.reg_tkeep_reg[7]\ => \throttle_ctl_pipeline.reg_tkeep_reg[7]\, + \throttle_ctl_pipeline.reg_tuser_reg[3]\(3) => trn_tsrc_dsc, + \throttle_ctl_pipeline.reg_tuser_reg[3]\(2) => trn_tstr, + \throttle_ctl_pipeline.reg_tuser_reg[3]\(1) => trn_terrfwd, + \throttle_ctl_pipeline.reg_tuser_reg[3]\(0) => trn_tecrc_gen, + tready_thrtl_i_5 => pcie_7x_i_n_22, + tready_thrtl_reg => tready_thrtl_reg, + trn_in_packet => \rx_inst/rx_pipeline_inst/trn_in_packet\, + trn_in_packet_reg => pcie_7x_i_n_9, + trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0), + trn_rd(63 downto 0) => trn_rd(63 downto 0), + trn_recrc_err => trn_recrc_err, + trn_reof => trn_reof, + trn_rerrfwd => trn_rerrfwd, + trn_rrem(0) => trn_rrem(0), + trn_rsof => trn_rsof, + trn_rsrc_dsc => trn_rsrc_dsc, + trn_rsrc_dsc_d => \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d\, + trn_rsrc_dsc_prev0 => \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0\, + trn_tbuf_av(5 downto 0) => \^trn_tbuf_av\(5 downto 0), + trn_tcfg_gnt => trn_tcfg_gnt, + trn_tcfg_req => \^trn_tcfg_req\, + trn_tdst_rdy => trn_tdst_rdy, + trn_teof => trn_teof, + trn_trem(0) => trn_trem, + trn_tsof => trn_tsof, + trn_tsrc_rdy => trn_tsrc_rdy, + tx_cfg_gnt => tx_cfg_gnt + ); +\cfg_bus_number_d[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \out\, + O => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_bus_number_d_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(8), + Q => cfg_bus_number(0), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_bus_number_d_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(9), + Q => cfg_bus_number(1), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_bus_number_d_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(10), + Q => cfg_bus_number(2), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_bus_number_d_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(11), + Q => cfg_bus_number(3), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_bus_number_d_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(12), + Q => cfg_bus_number(4), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_bus_number_d_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(13), + Q => cfg_bus_number(5), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_bus_number_d_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(14), + Q => cfg_bus_number(6), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_bus_number_d_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(15), + Q => cfg_bus_number(7), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_device_number_d_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(3), + Q => cfg_device_number(0), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_device_number_d_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(4), + Q => cfg_device_number(1), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_device_number_d_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(5), + Q => cfg_device_number(2), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_device_number_d_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(6), + Q => cfg_device_number(3), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_device_number_d_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(7), + Q => cfg_device_number(4), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_function_number_d_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(0), + Q => cfg_function_number(0), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_function_number_d_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(1), + Q => cfg_function_number(1), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +\cfg_function_number_d_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => pcie_7x_i_n_6, + D => \^cfg_msg_data\(2), + Q => cfg_function_number(2), + R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\ + ); +pcie_7x_i: entity work.pcie_7x_0_pcie_7x_0_pcie_7x + port map ( + E(0) => pcie_7x_i_n_6, + Q(15 downto 0) => pipe_rx0_data(15 downto 0), + bridge_reset_int => bridge_reset_int, + cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en, + cfg_aer_ecrc_check_en_0(3) => trn_tsrc_dsc, + cfg_aer_ecrc_check_en_0(2) => trn_tstr, + cfg_aer_ecrc_check_en_0(1) => trn_terrfwd, + cfg_aer_ecrc_check_en_0(0) => trn_tecrc_gen, + cfg_aer_ecrc_check_en_1(15 downto 0) => pipe_rx1_data(15 downto 0), + cfg_aer_ecrc_check_en_10(2 downto 0) => pipe_rx2_status(2 downto 0), + cfg_aer_ecrc_check_en_11(2 downto 0) => pipe_rx3_status(2 downto 0), + cfg_aer_ecrc_check_en_2(15 downto 0) => pipe_rx2_data(15 downto 0), + cfg_aer_ecrc_check_en_3(15 downto 0) => pipe_rx3_data(15 downto 0), + cfg_aer_ecrc_check_en_4(1 downto 0) => pipe_rx0_char_is_k(1 downto 0), + cfg_aer_ecrc_check_en_5(1 downto 0) => pipe_rx1_char_is_k(1 downto 0), + cfg_aer_ecrc_check_en_6(1 downto 0) => pipe_rx2_char_is_k(1 downto 0), + cfg_aer_ecrc_check_en_7(1 downto 0) => pipe_rx3_char_is_k(1 downto 0), + cfg_aer_ecrc_check_en_8(2 downto 0) => pipe_rx0_status(2 downto 0), + cfg_aer_ecrc_check_en_9(2 downto 0) => pipe_rx1_status(2 downto 0), + cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en, + cfg_aer_interrupt_msgnum(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0), + cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received, + cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en, + cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received, + cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en, + cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received, + cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en, + cfg_bridge_serr_en => cfg_bridge_serr_en, + cfg_command(4 downto 0) => cfg_command(4 downto 0), + cfg_dcommand(14 downto 0) => cfg_dcommand(14 downto 0), + cfg_dcommand2(11 downto 0) => cfg_dcommand2(11 downto 0), + cfg_ds_bus_number(7 downto 0) => cfg_ds_bus_number(7 downto 0), + cfg_ds_device_number(4 downto 0) => cfg_ds_device_number(4 downto 0), + cfg_ds_function_number(2 downto 0) => cfg_ds_function_number(2 downto 0), + cfg_dsn(63 downto 0) => cfg_dsn(63 downto 0), + cfg_dstatus(3 downto 0) => cfg_dstatus(3 downto 0), + cfg_err_aer_headerlog(127 downto 0) => cfg_err_aer_headerlog(127 downto 0), + cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set, + cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked, + cfg_err_cor => cfg_err_cor, + cfg_err_cpl_abort => cfg_err_cpl_abort, + cfg_err_cpl_rdy => cfg_err_cpl_rdy, + cfg_err_cpl_timeout => cfg_err_cpl_timeout, + cfg_err_cpl_unexpect => cfg_err_cpl_unexpect, + cfg_err_ecrc => cfg_err_ecrc, + cfg_err_internal_cor => cfg_err_internal_cor, + cfg_err_internal_uncor => cfg_err_internal_uncor, + cfg_err_locked => cfg_err_locked, + cfg_err_malformed => cfg_err_malformed, + cfg_err_mc_blocked => cfg_err_mc_blocked, + cfg_err_norecovery => cfg_err_norecovery, + cfg_err_poisoned => cfg_err_poisoned, + cfg_err_posted => cfg_err_posted, + cfg_err_tlp_cpl_header(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0), + cfg_err_ur => cfg_err_ur, + cfg_interrupt => cfg_interrupt, + cfg_interrupt_assert => cfg_interrupt_assert, + cfg_interrupt_di(7 downto 0) => cfg_interrupt_di(7 downto 0), + cfg_interrupt_do(7 downto 0) => cfg_interrupt_do(7 downto 0), + cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0), + cfg_interrupt_msienable => cfg_interrupt_msienable, + cfg_interrupt_msixenable => cfg_interrupt_msixenable, + cfg_interrupt_msixfm => cfg_interrupt_msixfm, + cfg_interrupt_rdy => cfg_interrupt_rdy, + cfg_interrupt_stat => cfg_interrupt_stat, + cfg_lcommand(10 downto 0) => cfg_lcommand(10 downto 0), + cfg_lstatus(9 downto 0) => cfg_lstatus(9 downto 0), + cfg_mgmt_byte_en_n(3 downto 0) => cfg_mgmt_byte_en_n(3 downto 0), + cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0), + cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0), + cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0), + cfg_mgmt_rd_en => cfg_mgmt_rd_en, + cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done, + cfg_mgmt_wr_en => cfg_mgmt_wr_en, + cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly, + cfg_mgmt_wr_rw1c_as_rw => cfg_mgmt_wr_rw1c_as_rw, + cfg_msg_data(15 downto 0) => \^cfg_msg_data\(15 downto 0), + cfg_msg_received => cfg_msg_received, + cfg_msg_received_assert_int_a => cfg_msg_received_assert_int_a, + cfg_msg_received_assert_int_b => cfg_msg_received_assert_int_b, + cfg_msg_received_assert_int_c => cfg_msg_received_assert_int_c, + cfg_msg_received_assert_int_d => cfg_msg_received_assert_int_d, + cfg_msg_received_deassert_int_a => cfg_msg_received_deassert_int_a, + cfg_msg_received_deassert_int_b => cfg_msg_received_deassert_int_b, + cfg_msg_received_deassert_int_c => cfg_msg_received_deassert_int_c, + cfg_msg_received_deassert_int_d => cfg_msg_received_deassert_int_d, + cfg_msg_received_err_cor => cfg_msg_received_err_cor, + cfg_msg_received_err_fatal => cfg_msg_received_err_fatal, + cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal, + cfg_msg_received_pm_as_nak => cfg_msg_received_pm_as_nak, + cfg_msg_received_pm_pme => cfg_msg_received_pm_pme, + cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack, + cfg_msg_received_setslotpowerlimit => cfg_msg_received_setslotpowerlimit, + cfg_pcie_link_state(2 downto 0) => \^cfg_pcie_link_state\(2 downto 0), + cfg_pciecap_interrupt_msgnum(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0), + cfg_pm_force_state(1 downto 0) => cfg_pm_force_state(1 downto 0), + cfg_pm_force_state_en => cfg_pm_force_state_en, + cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s, + cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1, + cfg_pm_turnoff_ok_n => cfg_turnoff_ok_w, + cfg_pm_wake => cfg_pm_wake, + cfg_pmcsr_pme_en => cfg_pmcsr_pme_en, + cfg_pmcsr_pme_status => cfg_pmcsr_pme_status, + cfg_pmcsr_powerstate(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0), + cfg_received_func_lvl_rst => cfg_received_func_lvl_rst, + cfg_root_control_pme_int_en => cfg_root_control_pme_int_en, + cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en, + cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en, + cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en, + cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse, + cfg_to_turnoff => \^cfg_to_turnoff\, + cfg_trn_pending => cfg_trn_pending, + cfg_vc_tcvc_map(6 downto 0) => cfg_vc_tcvc_map(6 downto 0), + dsc_detect => \rx_inst/rx_pipeline_inst/dsc_detect\, + fc_cpld(11 downto 0) => fc_cpld(11 downto 0), + fc_cplh(7 downto 0) => fc_cplh(7 downto 0), + fc_npd(11 downto 0) => fc_npd(11 downto 0), + fc_nph(7 downto 0) => fc_nph(7 downto 0), + fc_pd(11 downto 0) => fc_pd(11 downto 0), + fc_ph(7 downto 0) => fc_ph(7 downto 0), + fc_sel(2 downto 0) => fc_sel(2 downto 0), + lnk_up_thrtl => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/lnk_up_thrtl\, + lnk_up_thrtl_reg => pcie_7x_i_n_30, + \out\ => \out\, + pcie_drp_addr(8 downto 0) => pcie_drp_addr(8 downto 0), + pcie_drp_clk => pcie_drp_clk, + pcie_drp_clk_0 => pcie_7x_i_n_22, + pcie_drp_clk_1(63 downto 0) => trn_rd(63 downto 0), + pcie_drp_clk_2(0) => trn_rrem(0), + pcie_drp_di(15 downto 0) => pcie_drp_di(15 downto 0), + pcie_drp_do(15 downto 0) => pcie_drp_do(15 downto 0), + pcie_drp_en => pcie_drp_en, + pcie_drp_rdy => pcie_drp_rdy, + pcie_drp_we => pcie_drp_we, + pipe_pclk_in => pipe_pclk_in, + pipe_rx0_chanisaligned => pipe_rx0_chanisaligned, + pipe_rx0_elec_idle => pipe_rx0_elec_idle, + pipe_rx0_phy_status => pipe_rx0_phy_status, + pipe_rx0_polarity => pipe_rx0_polarity, + pipe_rx0_valid => pipe_rx0_valid, + pipe_rx1_chanisaligned => pipe_rx1_chanisaligned, + pipe_rx1_elec_idle => pipe_rx1_elec_idle, + pipe_rx1_phy_status => pipe_rx1_phy_status, + pipe_rx1_polarity => pipe_rx1_polarity, + pipe_rx1_valid => pipe_rx1_valid, + pipe_rx2_chanisaligned => pipe_rx2_chanisaligned, + pipe_rx2_elec_idle => pipe_rx2_elec_idle, + pipe_rx2_phy_status => pipe_rx2_phy_status, + pipe_rx2_polarity => pipe_rx2_polarity, + pipe_rx2_valid => pipe_rx2_valid, + pipe_rx3_chanisaligned => pipe_rx3_chanisaligned, + pipe_rx3_elec_idle => pipe_rx3_elec_idle, + pipe_rx3_phy_status => pipe_rx3_phy_status, + pipe_rx3_polarity => pipe_rx3_polarity, + pipe_rx3_valid => pipe_rx3_valid, + pipe_tx0_char_is_k(1 downto 0) => pipe_tx0_char_is_k(1 downto 0), + pipe_tx0_compliance => pipe_tx0_compliance, + pipe_tx0_data(15 downto 0) => pipe_tx0_data(15 downto 0), + pipe_tx0_elec_idle => pipe_tx0_elec_idle, + pipe_tx0_powerdown(1 downto 0) => pipe_tx0_powerdown(1 downto 0), + pipe_tx1_char_is_k(1 downto 0) => pipe_tx1_char_is_k(1 downto 0), + pipe_tx1_compliance => pipe_tx1_compliance, + pipe_tx1_data(15 downto 0) => pipe_tx1_data(15 downto 0), + pipe_tx1_elec_idle => pipe_tx1_elec_idle, + pipe_tx1_powerdown(1 downto 0) => pipe_tx1_powerdown(1 downto 0), + pipe_tx2_char_is_k(1 downto 0) => pipe_tx2_char_is_k(1 downto 0), + pipe_tx2_compliance => pipe_tx2_compliance, + pipe_tx2_data(15 downto 0) => pipe_tx2_data(15 downto 0), + pipe_tx2_elec_idle => pipe_tx2_elec_idle, + pipe_tx2_powerdown(1 downto 0) => pipe_tx2_powerdown(1 downto 0), + pipe_tx3_char_is_k(1 downto 0) => pipe_tx3_char_is_k(1 downto 0), + pipe_tx3_compliance => pipe_tx3_compliance, + pipe_tx3_data(15 downto 0) => pipe_tx3_data(15 downto 0), + pipe_tx3_elec_idle => pipe_tx3_elec_idle, + pipe_tx3_powerdown(1 downto 0) => pipe_tx3_powerdown(1 downto 0), + pipe_tx_deemph => pipe_tx_deemph, + pipe_tx_margin(2 downto 0) => pipe_tx_margin(2 downto 0), + pipe_tx_rate => pipe_tx_rate, + pipe_tx_rcvr_det => pipe_tx_rcvr_det, + pipe_userclk1_in => pipe_userclk1_in, + pipe_userclk2_in => pipe_userclk2_in, + pl_directed_change_done => pl_directed_change_done, + pl_directed_link_auton => pl_directed_link_auton, + pl_directed_link_change(1 downto 0) => pl_directed_link_change(1 downto 0), + pl_directed_link_speed => pl_directed_link_speed, + pl_directed_link_width(1 downto 0) => pl_directed_link_width(1 downto 0), + pl_downstream_deemph_source => pl_downstream_deemph_source, + pl_initial_link_width(2 downto 0) => pl_initial_link_width(2 downto 0), + pl_lane_reversal_mode(1 downto 0) => pl_lane_reversal_mode(1 downto 0), + pl_link_gen2_cap => pl_link_gen2_cap, + pl_link_partner_gen2_supported => pl_link_partner_gen2_supported, + pl_link_upcfg_cap => pl_link_upcfg_cap, + pl_ltssm_state(5 downto 0) => pl_ltssm_state(5 downto 0), + pl_phy_lnk_up => pl_phy_lnk_up, + pl_received_hot_rst => pl_received_hot_rst, + pl_rx_pm_state(1 downto 0) => pl_rx_pm_state(1 downto 0), + pl_sel_lnk_rate => pl_sel_lnk_rate, + pl_sel_lnk_width(1 downto 0) => pl_sel_lnk_width(1 downto 0), + pl_transmit_hot_rst => pl_transmit_hot_rst, + pl_tx_pm_state(2 downto 0) => pl_tx_pm_state(2 downto 0), + pl_upstream_prefer_deemph => pl_upstream_prefer_deemph, + ppm_L1_thrtl => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_thrtl\, + ppm_L1_thrtl_reg => pcie_7x_i_n_13, + ppm_L1_trig => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_trig\, + reg_dsc_detect => \rx_inst/rx_pipeline_inst/reg_dsc_detect\, + reg_tcfg_gnt => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/reg_tcfg_gnt\, + rsrc_rdy_filtered => \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered\, + rx_np_ok => rx_np_ok, + rx_np_req => rx_np_req, + src_in => src_in, + sys_rst_n => sys_rst_n, + tbuf_av_min_trig => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tbuf_av_min_trig\, + tcfg_req_trig => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tcfg_req_trig\, + trn_in_packet => \rx_inst/rx_pipeline_inst/trn_in_packet\, + trn_in_packet_reg => pcie_7x_i_n_9, + trn_lnk_up => trn_lnk_up, + trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0), + trn_rdst_rdy => trn_rdst_rdy, + trn_recrc_err => trn_recrc_err, + trn_reof => trn_reof, + trn_rerrfwd => trn_rerrfwd, + trn_rsof => trn_rsof, + trn_rsrc_dsc => trn_rsrc_dsc, + trn_rsrc_dsc_d => \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d\, + trn_rsrc_dsc_prev0 => \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0\, + trn_tbuf_av(5 downto 0) => \^trn_tbuf_av\(5 downto 0), + trn_tcfg_gnt => trn_tcfg_gnt, + trn_tcfg_req => \^trn_tcfg_req\, + trn_td(63 downto 0) => trn_td(63 downto 0), + trn_tdst_rdy => trn_tdst_rdy, + trn_teof => trn_teof, + trn_trem(0) => trn_trem, + trn_tsof => trn_tsof, + trn_tsrc_rdy => trn_tsrc_rdy, + tx_err_drop => tx_err_drop, + user_reset_int_reg => user_reset_int_reg + ); +pcie_pipe_pipeline_i: entity work.pcie_7x_0_pcie_7x_0_pcie_pipe_pipeline + port map ( + D(1 downto 0) => D(1 downto 0), + PIPE_POWERDOWN(7 downto 0) => PIPE_POWERDOWN(7 downto 0), + PIPE_RXCHANISALIGNED(3 downto 0) => PIPE_RXCHANISALIGNED(3 downto 0), + PIPE_RXPOLARITY(3 downto 0) => PIPE_RXPOLARITY(3 downto 0), + PIPE_TXCOMPLIANCE(3 downto 0) => PIPE_TXCOMPLIANCE(3 downto 0), + PIPE_TXDATA(63 downto 0) => PIPE_TXDATA(63 downto 0), + PIPE_TXDATAK(7 downto 0) => PIPE_TXDATAK(7 downto 0), + PIPE_TXELECIDLE(3 downto 0) => PIPE_TXELECIDLE(3 downto 0), + Q(1 downto 0) => pipe_rx1_char_is_k(1 downto 0), + SR(0) => SR(0), + gt_rx_phy_status_q => gt_rx_phy_status_q, + gt_rxelecidle_q => gt_rxelecidle_q, + pipe_pclk_in => pipe_pclk_in, + pipe_rx0_chanisaligned => pipe_rx0_chanisaligned, + pipe_rx0_elec_idle => pipe_rx0_elec_idle, + pipe_rx0_phy_status => pipe_rx0_phy_status, + pipe_rx0_polarity => pipe_rx0_polarity, + pipe_rx0_valid => pipe_rx0_valid, + pipe_rx0_valid_gt => pipe_rx0_valid_gt, + pipe_rx1_chanisaligned => pipe_rx1_chanisaligned, + pipe_rx1_elec_idle => pipe_rx1_elec_idle, + pipe_rx1_phy_status => pipe_rx1_phy_status, + pipe_rx1_polarity => pipe_rx1_polarity, + pipe_rx1_valid => pipe_rx1_valid, + pipe_rx1_valid_gt => pipe_rx1_valid_gt, + pipe_rx2_chanisaligned => pipe_rx2_chanisaligned, + pipe_rx2_elec_idle => pipe_rx2_elec_idle, + pipe_rx2_phy_status => pipe_rx2_phy_status, + pipe_rx2_polarity => pipe_rx2_polarity, + pipe_rx2_valid => pipe_rx2_valid, + pipe_rx2_valid_gt => pipe_rx2_valid_gt, + pipe_rx3_chanisaligned => pipe_rx3_chanisaligned, + pipe_rx3_elec_idle => pipe_rx3_elec_idle, + pipe_rx3_phy_status => pipe_rx3_phy_status, + pipe_rx3_polarity => pipe_rx3_polarity, + pipe_rx3_valid => pipe_rx3_valid, + pipe_rx3_valid_gt => pipe_rx3_valid_gt, + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0) => pipe_rx2_char_is_k(1 downto 0), + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0) => pipe_rx3_char_is_k(1 downto 0), + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0) => pipe_rx0_char_is_k(1 downto 0), + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0), + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0), + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => pipe_rx1_data(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0) => pipe_rx2_data(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0) => pipe_rx3_data(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_2\(15 downto 0) => pipe_rx0_data(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_3\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_4\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_5\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_6\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_2\(15 downto 0), + \pipe_stages_1.pipe_rx_elec_idle_q_reg\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg\, + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\, + \pipe_stages_1.pipe_rx_elec_idle_q_reg_1\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg_1\, + \pipe_stages_1.pipe_rx_phy_status_q_reg\ => \pipe_stages_1.pipe_rx_phy_status_q_reg\, + \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ => \pipe_stages_1.pipe_rx_phy_status_q_reg_0\, + \pipe_stages_1.pipe_rx_phy_status_q_reg_1\ => \pipe_stages_1.pipe_rx_phy_status_q_reg_1\, + \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0) => pipe_rx1_status(2 downto 0), + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0) => pipe_rx2_status(2 downto 0), + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0) => pipe_rx3_status(2 downto 0), + \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(2 downto 0) => pipe_rx0_status(2 downto 0), + \pipe_stages_1.pipe_rx_status_q_reg[2]_3\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0), + \pipe_stages_1.pipe_rx_status_q_reg[2]_4\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0), + \pipe_stages_1.pipe_rx_status_q_reg[2]_5\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0), + \pipe_stages_1.pipe_rx_status_q_reg[2]_6\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(2 downto 0), + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\(1 downto 0) => pipe_tx0_char_is_k(1 downto 0), + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1 downto 0) => pipe_tx1_char_is_k(1 downto 0), + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\(1 downto 0) => pipe_tx2_char_is_k(1 downto 0), + \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2\(1 downto 0) => pipe_tx3_char_is_k(1 downto 0), + \pipe_stages_1.pipe_tx_data_q_reg[15]\(15 downto 0) => pipe_tx0_data(15 downto 0), + \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15 downto 0) => pipe_tx1_data(15 downto 0), + \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(15 downto 0) => pipe_tx2_data(15 downto 0), + \pipe_stages_1.pipe_tx_data_q_reg[15]_2\(15 downto 0) => pipe_tx3_data(15 downto 0), + \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0) => Q(2 downto 0), + \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\(2 downto 0) => pipe_tx_margin(2 downto 0), + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]\(1 downto 0) => pipe_tx0_powerdown(1 downto 0), + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1 downto 0) => pipe_tx1_powerdown(1 downto 0), + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\(1 downto 0) => pipe_tx2_powerdown(1 downto 0), + \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2\(1 downto 0) => pipe_tx3_powerdown(1 downto 0), + \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0), + pipe_tx0_compliance => pipe_tx0_compliance, + pipe_tx0_elec_idle => pipe_tx0_elec_idle, + pipe_tx1_compliance => pipe_tx1_compliance, + pipe_tx1_elec_idle => pipe_tx1_elec_idle, + pipe_tx2_compliance => pipe_tx2_compliance, + pipe_tx2_elec_idle => pipe_tx2_elec_idle, + pipe_tx3_compliance => pipe_tx3_compliance, + pipe_tx3_elec_idle => pipe_tx3_elec_idle, + pipe_tx_deemph => pipe_tx_deemph, + pipe_tx_deemph_gt => pipe_tx_deemph_gt, + pipe_tx_rate => pipe_tx_rate, + pipe_tx_rcvr_det => pipe_tx_rcvr_det, + pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_core_top is + port ( + pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 ); + pl_phy_lnk_up : out STD_LOGIC; + user_reset_out : out STD_LOGIC; + m_axis_rx_tvalid : out STD_LOGIC; + s_axis_tx_tready : out STD_LOGIC; + cfg_aer_ecrc_check_en : out STD_LOGIC; + cfg_aer_ecrc_gen_en : out STD_LOGIC; + cfg_aer_rooterr_corr_err_received : out STD_LOGIC; + cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_fatal_err_received : out STD_LOGIC; + cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC; + cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC; + cfg_bridge_serr_en : out STD_LOGIC; + cfg_command : out STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_dcommand2 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + cfg_dcommand : out STD_LOGIC_VECTOR ( 14 downto 0 ); + cfg_dstatus : out STD_LOGIC_VECTOR ( 3 downto 0 ); + cfg_interrupt_msienable : out STD_LOGIC; + cfg_interrupt_msixenable : out STD_LOGIC; + cfg_interrupt_msixfm : out STD_LOGIC; + cfg_lcommand : out STD_LOGIC_VECTOR ( 10 downto 0 ); + cfg_lstatus : out STD_LOGIC_VECTOR ( 9 downto 0 ); + cfg_msg_received : out STD_LOGIC; + cfg_msg_received_assert_int_a : out STD_LOGIC; + cfg_msg_received_assert_int_b : out STD_LOGIC; + cfg_msg_received_assert_int_c : out STD_LOGIC; + cfg_msg_received_assert_int_d : out STD_LOGIC; + cfg_msg_received_deassert_int_a : out STD_LOGIC; + cfg_msg_received_deassert_int_b : out STD_LOGIC; + cfg_msg_received_deassert_int_c : out STD_LOGIC; + cfg_msg_received_deassert_int_d : out STD_LOGIC; + cfg_msg_received_err_cor : out STD_LOGIC; + cfg_msg_received_err_fatal : out STD_LOGIC; + cfg_msg_received_err_non_fatal : out STD_LOGIC; + cfg_msg_received_pm_as_nak : out STD_LOGIC; + cfg_to_turnoff : out STD_LOGIC; + cfg_msg_received_pme_to_ack : out STD_LOGIC; + cfg_msg_received_pm_pme : out STD_LOGIC; + cfg_msg_received_setslotpowerlimit : out STD_LOGIC; + cfg_pmcsr_pme_en : out STD_LOGIC; + cfg_pmcsr_pme_status : out STD_LOGIC; + cfg_root_control_pme_int_en : out STD_LOGIC; + cfg_root_control_syserr_corr_err_en : out STD_LOGIC; + cfg_root_control_syserr_fatal_err_en : out STD_LOGIC; + cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC; + cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC; + pcie_drp_rdy : out STD_LOGIC; + pl_directed_change_done : out STD_LOGIC; + pl_link_gen2_cap : out STD_LOGIC; + pl_link_partner_gen2_supported : out STD_LOGIC; + pl_link_upcfg_cap : out STD_LOGIC; + pl_sel_lnk_rate : out STD_LOGIC; + tx_cfg_req : out STD_LOGIC; + tx_err_drop : out STD_LOGIC; + fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 ); + cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); + pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); + tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 ); + cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 ); + cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 ); + pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); + gen3_reg : out STD_LOGIC; + pci_exp_txn : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_txp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_txoutclk_out : out STD_LOGIC; + user_lnk_up : out STD_LOGIC; + m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_rx_tlast : out STD_LOGIC; + m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 ); + cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pl_received_hot_rst : out STD_LOGIC; + cfg_mgmt_rd_wr_done : out STD_LOGIC; + cfg_err_aer_headerlog_set : out STD_LOGIC; + cfg_err_cpl_rdy : out STD_LOGIC; + cfg_interrupt_rdy : out STD_LOGIC; + cfg_received_func_lvl_rst : out STD_LOGIC; + pipe_pclk_in : in STD_LOGIC; + m_axis_rx_tready : in STD_LOGIC; + s_axis_tx_tlast : in STD_LOGIC; + s_axis_tx_tvalid : in STD_LOGIC; + pipe_userclk2_in : in STD_LOGIC; + pipe_userclk1_in : in STD_LOGIC; + pcie_drp_clk : in STD_LOGIC; + pcie_drp_en : in STD_LOGIC; + pcie_drp_we : in STD_LOGIC; + pl_directed_link_auton : in STD_LOGIC; + pl_directed_link_speed : in STD_LOGIC; + pl_downstream_deemph_source : in STD_LOGIC; + pl_transmit_hot_rst : in STD_LOGIC; + pl_upstream_prefer_deemph : in STD_LOGIC; + rx_np_ok : in STD_LOGIC; + rx_np_req : in STD_LOGIC; + cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 ); + pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); + fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); + cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); + cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); + pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); + pipe_mmcm_lock_in : in STD_LOGIC; + pipe_rxusrclk_in : in STD_LOGIC; + pipe_dclk_in : in STD_LOGIC; + sys_clk : in STD_LOGIC; + pipe_oobclk_in : in STD_LOGIC; + pci_exp_rxn : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_rxp : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sys_rst_n : in STD_LOGIC; + tx_cfg_gnt : in STD_LOGIC; + cfg_turnoff_ok : in STD_LOGIC; + s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); + cfg_mgmt_byte_en : in STD_LOGIC_VECTOR ( 3 downto 0 ); + cfg_trn_pending : in STD_LOGIC; + cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC; + cfg_mgmt_wr_readonly : in STD_LOGIC; + cfg_mgmt_wr_en : in STD_LOGIC; + cfg_mgmt_rd_en : in STD_LOGIC; + cfg_err_malformed : in STD_LOGIC; + cfg_err_cor : in STD_LOGIC; + cfg_err_ur : in STD_LOGIC; + cfg_err_ecrc : in STD_LOGIC; + cfg_err_cpl_timeout : in STD_LOGIC; + cfg_err_cpl_abort : in STD_LOGIC; + cfg_err_cpl_unexpect : in STD_LOGIC; + cfg_err_poisoned : in STD_LOGIC; + cfg_err_atomic_egress_blocked : in STD_LOGIC; + cfg_err_mc_blocked : in STD_LOGIC; + cfg_err_internal_uncor : in STD_LOGIC; + cfg_err_internal_cor : in STD_LOGIC; + cfg_err_posted : in STD_LOGIC; + cfg_err_locked : in STD_LOGIC; + cfg_err_norecovery : in STD_LOGIC; + cfg_interrupt : in STD_LOGIC; + cfg_interrupt_assert : in STD_LOGIC; + cfg_interrupt_stat : in STD_LOGIC; + cfg_pm_halt_aspm_l0s : in STD_LOGIC; + cfg_pm_halt_aspm_l1 : in STD_LOGIC; + cfg_pm_force_state_en : in STD_LOGIC; + cfg_pm_wake : in STD_LOGIC + ); +end pcie_7x_0_pcie_7x_0_core_top; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_core_top is + signal \_inferred__0/store_ltssm_inferred_i_2_n_0\ : STD_LOGIC; + signal \_inferred__0/store_ltssm_inferred_i_3_n_0\ : STD_LOGIC; + signal bridge_reset_int : STD_LOGIC; + signal gt_rx_phy_status_q : STD_LOGIC; + signal gt_rxelecidle_q : STD_LOGIC; + signal gt_top_i_n_10 : STD_LOGIC; + signal gt_top_i_n_120 : STD_LOGIC; + signal gt_top_i_n_13 : STD_LOGIC; + signal gt_top_i_n_5 : STD_LOGIC; + signal gt_top_i_n_6 : STD_LOGIC; + signal gt_top_i_n_7 : STD_LOGIC; + signal gt_top_i_n_78 : STD_LOGIC; + signal gt_top_i_n_79 : STD_LOGIC; + signal gt_top_i_n_8 : STD_LOGIC; + signal gt_top_i_n_80 : STD_LOGIC; + signal gt_top_i_n_81 : STD_LOGIC; + signal gt_top_i_n_82 : STD_LOGIC; + signal gt_top_i_n_83 : STD_LOGIC; + signal gt_top_i_n_84 : STD_LOGIC; + signal gt_top_i_n_85 : STD_LOGIC; + signal gt_top_i_n_86 : STD_LOGIC; + signal gt_top_i_n_87 : STD_LOGIC; + signal gt_top_i_n_88 : STD_LOGIC; + signal gt_top_i_n_89 : STD_LOGIC; + signal gt_top_i_n_9 : STD_LOGIC; + signal \ltssm_reg1_reg[0]_srl2_n_0\ : STD_LOGIC; + signal \ltssm_reg1_reg[1]_srl2_n_0\ : STD_LOGIC; + signal \ltssm_reg1_reg[2]_srl2_n_0\ : STD_LOGIC; + signal \ltssm_reg1_reg[3]_srl2_n_0\ : STD_LOGIC; + signal \ltssm_reg1_reg[4]_srl2_n_0\ : STD_LOGIC; + signal \ltssm_reg1_reg[5]_srl2_n_0\ : STD_LOGIC; + signal ltssm_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal pcie_block_i_i_32_n_0 : STD_LOGIC; + signal pcie_block_i_i_33_n_0 : STD_LOGIC; + signal pcie_block_i_i_34_n_0 : STD_LOGIC; + signal pcie_block_i_i_35_n_0 : STD_LOGIC; + signal pcie_top_i_n_20 : STD_LOGIC; + signal phy_rdy_n : STD_LOGIC; + signal pipe_rx0_chanisaligned_gt : STD_LOGIC; + signal pipe_rx0_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_rx0_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_rx0_polarity_gt : STD_LOGIC; + signal pipe_rx0_valid_gt : STD_LOGIC; + signal pipe_rx1_chanisaligned_gt : STD_LOGIC; + signal pipe_rx1_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_rx1_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_rx1_polarity_gt : STD_LOGIC; + signal pipe_rx1_valid_gt : STD_LOGIC; + signal pipe_rx2_chanisaligned_gt : STD_LOGIC; + signal pipe_rx2_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_rx2_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_rx2_polarity_gt : STD_LOGIC; + signal pipe_rx2_valid_gt : STD_LOGIC; + signal pipe_rx3_chanisaligned_gt : STD_LOGIC; + signal pipe_rx3_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_rx3_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_rx3_polarity_gt : STD_LOGIC; + signal pipe_rx3_valid_gt : STD_LOGIC; + signal pipe_tx0_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx0_compliance_gt : STD_LOGIC; + signal pipe_tx0_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_tx0_elec_idle_gt : STD_LOGIC; + signal pipe_tx0_powerdown_gt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx1_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx1_compliance_gt : STD_LOGIC; + signal pipe_tx1_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_tx1_elec_idle_gt : STD_LOGIC; + signal pipe_tx1_powerdown_gt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx2_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx2_compliance_gt : STD_LOGIC; + signal pipe_tx2_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_tx2_elec_idle_gt : STD_LOGIC; + signal pipe_tx2_powerdown_gt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx3_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx3_compliance_gt : STD_LOGIC; + signal pipe_tx3_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal pipe_tx3_elec_idle_gt : STD_LOGIC; + signal pipe_tx3_powerdown_gt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal pipe_tx_deemph_gt : STD_LOGIC; + signal pipe_tx_margin_gt : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal pipe_tx_rate_gt : STD_LOGIC; + signal pipe_tx_rcvr_det_gt : STD_LOGIC; + signal \^pl_ltssm_state\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \^pl_phy_lnk_up\ : STD_LOGIC; + signal pl_phy_lnk_up_sync : STD_LOGIC; + signal pl_phy_lnk_up_wire : STD_LOGIC; + signal \^pl_received_hot_rst\ : STD_LOGIC; + signal pl_received_hot_rst_sync : STD_LOGIC; + signal pl_received_hot_rst_wire : STD_LOGIC; + signal store_ltssm : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of store_ltssm : signal is std.standard.true; + signal sys_or_hot_rst : STD_LOGIC; + signal trn_lnk_up : STD_LOGIC; + signal user_lnk_up_int : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of user_lnk_up_int : signal is "true"; + attribute async_reg : string; + attribute async_reg of user_lnk_up_int : signal is "true"; + signal user_lnk_up_mux : STD_LOGIC; + attribute async_reg of user_lnk_up_mux : signal is "true"; + signal \^user_reset_out\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \ltssm_reg1_reg[0]_srl2\ : label is "inst/\inst/ltssm_reg1_reg "; + attribute srl_name : string; + attribute srl_name of \ltssm_reg1_reg[0]_srl2\ : label is "inst/\inst/ltssm_reg1_reg[0]_srl2 "; + attribute srl_bus_name of \ltssm_reg1_reg[1]_srl2\ : label is "inst/\inst/ltssm_reg1_reg "; + attribute srl_name of \ltssm_reg1_reg[1]_srl2\ : label is "inst/\inst/ltssm_reg1_reg[1]_srl2 "; + attribute srl_bus_name of \ltssm_reg1_reg[2]_srl2\ : label is "inst/\inst/ltssm_reg1_reg "; + attribute srl_name of \ltssm_reg1_reg[2]_srl2\ : label is "inst/\inst/ltssm_reg1_reg[2]_srl2 "; + attribute srl_bus_name of \ltssm_reg1_reg[3]_srl2\ : label is "inst/\inst/ltssm_reg1_reg "; + attribute srl_name of \ltssm_reg1_reg[3]_srl2\ : label is "inst/\inst/ltssm_reg1_reg[3]_srl2 "; + attribute srl_bus_name of \ltssm_reg1_reg[4]_srl2\ : label is "inst/\inst/ltssm_reg1_reg "; + attribute srl_name of \ltssm_reg1_reg[4]_srl2\ : label is "inst/\inst/ltssm_reg1_reg[4]_srl2 "; + attribute srl_bus_name of \ltssm_reg1_reg[5]_srl2\ : label is "inst/\inst/ltssm_reg1_reg "; + attribute srl_name of \ltssm_reg1_reg[5]_srl2\ : label is "inst/\inst/ltssm_reg1_reg[5]_srl2 "; + attribute DEST_SYNC_FF : integer; + attribute DEST_SYNC_FF of phy_lnk_up_cdc : label is 2; + attribute INIT_SYNC_FF : integer; + attribute INIT_SYNC_FF of phy_lnk_up_cdc : label is 0; + attribute SIM_ASSERT_CHK : integer; + attribute SIM_ASSERT_CHK of phy_lnk_up_cdc : label is 0; + attribute SRC_INPUT_REG : integer; + attribute SRC_INPUT_REG of phy_lnk_up_cdc : label is 0; + attribute VERSION : integer; + attribute VERSION of phy_lnk_up_cdc : label is 0; + attribute XPM_CDC : string; + attribute XPM_CDC of phy_lnk_up_cdc : label is "SINGLE"; + attribute XPM_MODULE : string; + attribute XPM_MODULE of phy_lnk_up_cdc : label is "TRUE"; + attribute DEST_SYNC_FF of pl_received_hot_rst_cdc : label is 2; + attribute INIT_SYNC_FF of pl_received_hot_rst_cdc : label is 0; + attribute SIM_ASSERT_CHK of pl_received_hot_rst_cdc : label is 0; + attribute SRC_INPUT_REG of pl_received_hot_rst_cdc : label is 0; + attribute VERSION of pl_received_hot_rst_cdc : label is 0; + attribute XPM_CDC of pl_received_hot_rst_cdc : label is "SINGLE"; + attribute XPM_MODULE of pl_received_hot_rst_cdc : label is "TRUE"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of user_lnk_up_int_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of user_lnk_up_int_reg : label is "yes"; + attribute ASYNC_REG_boolean of user_lnk_up_mux_reg : label is std.standard.true; + attribute KEEP of user_lnk_up_mux_reg : label is "yes"; +begin + pl_ltssm_state(5 downto 0) <= \^pl_ltssm_state\(5 downto 0); + pl_phy_lnk_up <= \^pl_phy_lnk_up\; + pl_received_hot_rst <= \^pl_received_hot_rst\; + user_lnk_up <= user_lnk_up_int; + user_reset_out <= \^user_reset_out\; +\_inferred__0/store_ltssm_inferred_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \_inferred__0/store_ltssm_inferred_i_2_n_0\, + I1 => \_inferred__0/store_ltssm_inferred_i_3_n_0\, + O => store_ltssm + ); +\_inferred__0/store_ltssm_inferred_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6FF6FFFFFFFF6FF6" + ) + port map ( + I0 => ltssm_reg2(0), + I1 => \^pl_ltssm_state\(0), + I2 => \^pl_ltssm_state\(2), + I3 => ltssm_reg2(2), + I4 => \^pl_ltssm_state\(1), + I5 => ltssm_reg2(1), + O => \_inferred__0/store_ltssm_inferred_i_2_n_0\ + ); +\_inferred__0/store_ltssm_inferred_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6FF6FFFFFFFF6FF6" + ) + port map ( + I0 => ltssm_reg2(3), + I1 => \^pl_ltssm_state\(3), + I2 => \^pl_ltssm_state\(5), + I3 => ltssm_reg2(5), + I4 => \^pl_ltssm_state\(4), + I5 => ltssm_reg2(4), + O => \_inferred__0/store_ltssm_inferred_i_3_n_0\ + ); +gt_top_i: entity work.pcie_7x_0_pcie_7x_0_gt_top + port map ( + D(1 downto 0) => pipe_rx0_char_is_k_gt(1 downto 0), + PIPE_POWERDOWN(7 downto 6) => pipe_tx3_powerdown_gt(1 downto 0), + PIPE_POWERDOWN(5 downto 4) => pipe_tx2_powerdown_gt(1 downto 0), + PIPE_POWERDOWN(3 downto 2) => pipe_tx1_powerdown_gt(1 downto 0), + PIPE_POWERDOWN(1 downto 0) => pipe_tx0_powerdown_gt(1 downto 0), + PIPE_RXCHANISALIGNED(3) => pipe_rx3_chanisaligned_gt, + PIPE_RXCHANISALIGNED(2) => pipe_rx2_chanisaligned_gt, + PIPE_RXCHANISALIGNED(1) => pipe_rx1_chanisaligned_gt, + PIPE_RXCHANISALIGNED(0) => pipe_rx0_chanisaligned_gt, + PIPE_RXPOLARITY(3) => pipe_rx3_polarity_gt, + PIPE_RXPOLARITY(2) => pipe_rx2_polarity_gt, + PIPE_RXPOLARITY(1) => pipe_rx1_polarity_gt, + PIPE_RXPOLARITY(0) => pipe_rx0_polarity_gt, + PIPE_TXCOMPLIANCE(3) => pipe_tx3_compliance_gt, + PIPE_TXCOMPLIANCE(2) => pipe_tx2_compliance_gt, + PIPE_TXCOMPLIANCE(1) => pipe_tx1_compliance_gt, + PIPE_TXCOMPLIANCE(0) => pipe_tx0_compliance_gt, + PIPE_TXDATA(63 downto 48) => pipe_tx3_data_gt(15 downto 0), + PIPE_TXDATA(47 downto 32) => pipe_tx2_data_gt(15 downto 0), + PIPE_TXDATA(31 downto 16) => pipe_tx1_data_gt(15 downto 0), + PIPE_TXDATA(15 downto 0) => pipe_tx0_data_gt(15 downto 0), + PIPE_TXDATAK(7 downto 6) => pipe_tx3_char_is_k_gt(1 downto 0), + PIPE_TXDATAK(5 downto 4) => pipe_tx2_char_is_k_gt(1 downto 0), + PIPE_TXDATAK(3 downto 2) => pipe_tx1_char_is_k_gt(1 downto 0), + PIPE_TXDATAK(1 downto 0) => pipe_tx0_char_is_k_gt(1 downto 0), + PIPE_TXELECIDLE(3) => pipe_tx3_elec_idle_gt, + PIPE_TXELECIDLE(2) => pipe_tx2_elec_idle_gt, + PIPE_TXELECIDLE(1) => pipe_tx1_elec_idle_gt, + PIPE_TXELECIDLE(0) => pipe_tx0_elec_idle_gt, + Q(15 downto 0) => pipe_rx0_data_gt(15 downto 0), + USER_RATE_GEN3 => gen3_reg, + \cplllock_reg1_reg[3]\(2 downto 0) => pipe_tx_margin_gt(2 downto 0), + gt_rx_phy_status_q => gt_rx_phy_status_q, + gt_rx_phy_status_q_reg => gt_top_i_n_5, + gt_rx_phy_status_q_reg_0 => gt_top_i_n_7, + gt_rx_phy_status_q_reg_1 => gt_top_i_n_9, + \gt_rx_status_q_reg[2]\(2) => gt_top_i_n_78, + \gt_rx_status_q_reg[2]\(1) => gt_top_i_n_79, + \gt_rx_status_q_reg[2]\(0) => gt_top_i_n_80, + \gt_rx_status_q_reg[2]_0\(2) => gt_top_i_n_81, + \gt_rx_status_q_reg[2]_0\(1) => gt_top_i_n_82, + \gt_rx_status_q_reg[2]_0\(0) => gt_top_i_n_83, + \gt_rx_status_q_reg[2]_1\(2) => gt_top_i_n_84, + \gt_rx_status_q_reg[2]_1\(1) => gt_top_i_n_85, + \gt_rx_status_q_reg[2]_1\(0) => gt_top_i_n_86, + \gt_rx_status_q_reg[2]_2\(2) => gt_top_i_n_87, + \gt_rx_status_q_reg[2]_2\(1) => gt_top_i_n_88, + \gt_rx_status_q_reg[2]_2\(0) => gt_top_i_n_89, + \gt_rxdata_q_reg[15]\(15 downto 0) => pipe_rx1_data_gt(15 downto 0), + \gt_rxdata_q_reg[15]_0\(15 downto 0) => pipe_rx2_data_gt(15 downto 0), + \gt_rxdata_q_reg[15]_1\(15 downto 0) => pipe_rx3_data_gt(15 downto 0), + gt_rxelecidle_q => gt_rxelecidle_q, + gt_rxelecidle_q_reg => gt_top_i_n_6, + gt_rxelecidle_q_reg_0 => gt_top_i_n_8, + gt_rxelecidle_q_reg_1 => gt_top_i_n_10, + gt_rxvalid_q_reg(1 downto 0) => pipe_rx1_char_is_k_gt(1 downto 0), + gt_rxvalid_q_reg_0(1 downto 0) => pipe_rx2_char_is_k_gt(1 downto 0), + gt_rxvalid_q_reg_1(1 downto 0) => pipe_rx3_char_is_k_gt(1 downto 0), + pci_exp_rxn(3 downto 0) => pci_exp_rxn(3 downto 0), + pci_exp_rxp(3 downto 0) => pci_exp_rxp(3 downto 0), + pci_exp_txn(3 downto 0) => pci_exp_txn(3 downto 0), + pci_exp_txp(3 downto 0) => pci_exp_txp(3 downto 0), + phy_rdy_n => phy_rdy_n, + pipe_dclk_in => pipe_dclk_in, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_oobclk_in => pipe_oobclk_in, + pipe_pclk_in => pipe_pclk_in, + pipe_pclk_sel_out(3 downto 0) => pipe_pclk_sel_out(3 downto 0), + pipe_rx0_valid_gt => pipe_rx0_valid_gt, + pipe_rx1_valid_gt => pipe_rx1_valid_gt, + pipe_rx2_valid_gt => pipe_rx2_valid_gt, + pipe_rx3_valid_gt => pipe_rx3_valid_gt, + pipe_rxoutclk_out(3 downto 0) => pipe_rxoutclk_out(3 downto 0), + pipe_rxusrclk_in => pipe_rxusrclk_in, + pipe_tx_deemph_gt => pipe_tx_deemph_gt, + pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt, + pipe_txoutclk_out => pipe_txoutclk_out, + pl_ltssm_state(5 downto 0) => \^pl_ltssm_state\(5 downto 0), + \rate_reg1_reg[0]\(0) => pipe_tx_rate_gt, + reset_n_reg1_reg => sys_rst_n, + sys_clk => sys_clk, + sys_rst_n => gt_top_i_n_13, + sys_rst_n_0 => gt_top_i_n_120 + ); +\ltssm_reg1_reg[0]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => pipe_pclk_in, + D => \^pl_ltssm_state\(0), + Q => \ltssm_reg1_reg[0]_srl2_n_0\ + ); +\ltssm_reg1_reg[1]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => pipe_pclk_in, + D => \^pl_ltssm_state\(1), + Q => \ltssm_reg1_reg[1]_srl2_n_0\ + ); +\ltssm_reg1_reg[2]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => pipe_pclk_in, + D => \^pl_ltssm_state\(2), + Q => \ltssm_reg1_reg[2]_srl2_n_0\ + ); +\ltssm_reg1_reg[3]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => pipe_pclk_in, + D => \^pl_ltssm_state\(3), + Q => \ltssm_reg1_reg[3]_srl2_n_0\ + ); +\ltssm_reg1_reg[4]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => pipe_pclk_in, + D => \^pl_ltssm_state\(4), + Q => \ltssm_reg1_reg[4]_srl2_n_0\ + ); +\ltssm_reg1_reg[5]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => pipe_pclk_in, + D => \^pl_ltssm_state\(5), + Q => \ltssm_reg1_reg[5]_srl2_n_0\ + ); +\ltssm_reg2_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \ltssm_reg1_reg[0]_srl2_n_0\, + Q => ltssm_reg2(0), + R => '0' + ); +\ltssm_reg2_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \ltssm_reg1_reg[1]_srl2_n_0\, + Q => ltssm_reg2(1), + R => '0' + ); +\ltssm_reg2_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \ltssm_reg1_reg[2]_srl2_n_0\, + Q => ltssm_reg2(2), + R => '0' + ); +\ltssm_reg2_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \ltssm_reg1_reg[3]_srl2_n_0\, + Q => ltssm_reg2(3), + R => '0' + ); +\ltssm_reg2_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \ltssm_reg1_reg[4]_srl2_n_0\, + Q => ltssm_reg2(4), + R => '0' + ); +\ltssm_reg2_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => pipe_pclk_in, + CE => '1', + D => \ltssm_reg1_reg[5]_srl2_n_0\, + Q => ltssm_reg2(5), + R => '0' + ); +pcie_block_i_i_32: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_mgmt_byte_en(3), + O => pcie_block_i_i_32_n_0 + ); +pcie_block_i_i_33: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_mgmt_byte_en(2), + O => pcie_block_i_i_33_n_0 + ); +pcie_block_i_i_34: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_mgmt_byte_en(1), + O => pcie_block_i_i_34_n_0 + ); +pcie_block_i_i_35: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cfg_mgmt_byte_en(0), + O => pcie_block_i_i_35_n_0 + ); +pcie_top_i: entity work.pcie_7x_0_pcie_7x_0_pcie_top + port map ( + D(1 downto 0) => pipe_rx1_char_is_k_gt(1 downto 0), + PIPE_POWERDOWN(7 downto 6) => pipe_tx3_powerdown_gt(1 downto 0), + PIPE_POWERDOWN(5 downto 4) => pipe_tx2_powerdown_gt(1 downto 0), + PIPE_POWERDOWN(3 downto 2) => pipe_tx1_powerdown_gt(1 downto 0), + PIPE_POWERDOWN(1 downto 0) => pipe_tx0_powerdown_gt(1 downto 0), + PIPE_RXCHANISALIGNED(3) => pipe_rx3_chanisaligned_gt, + PIPE_RXCHANISALIGNED(2) => pipe_rx2_chanisaligned_gt, + PIPE_RXCHANISALIGNED(1) => pipe_rx1_chanisaligned_gt, + PIPE_RXCHANISALIGNED(0) => pipe_rx0_chanisaligned_gt, + PIPE_RXPOLARITY(3) => pipe_rx3_polarity_gt, + PIPE_RXPOLARITY(2) => pipe_rx2_polarity_gt, + PIPE_RXPOLARITY(1) => pipe_rx1_polarity_gt, + PIPE_RXPOLARITY(0) => pipe_rx0_polarity_gt, + PIPE_TXCOMPLIANCE(3) => pipe_tx3_compliance_gt, + PIPE_TXCOMPLIANCE(2) => pipe_tx2_compliance_gt, + PIPE_TXCOMPLIANCE(1) => pipe_tx1_compliance_gt, + PIPE_TXCOMPLIANCE(0) => pipe_tx0_compliance_gt, + PIPE_TXDATA(63 downto 48) => pipe_tx3_data_gt(15 downto 0), + PIPE_TXDATA(47 downto 32) => pipe_tx2_data_gt(15 downto 0), + PIPE_TXDATA(31 downto 16) => pipe_tx1_data_gt(15 downto 0), + PIPE_TXDATA(15 downto 0) => pipe_tx0_data_gt(15 downto 0), + PIPE_TXDATAK(7 downto 6) => pipe_tx3_char_is_k_gt(1 downto 0), + PIPE_TXDATAK(5 downto 4) => pipe_tx2_char_is_k_gt(1 downto 0), + PIPE_TXDATAK(3 downto 2) => pipe_tx1_char_is_k_gt(1 downto 0), + PIPE_TXDATAK(1 downto 0) => pipe_tx0_char_is_k_gt(1 downto 0), + PIPE_TXELECIDLE(3) => pipe_tx3_elec_idle_gt, + PIPE_TXELECIDLE(2) => pipe_tx2_elec_idle_gt, + PIPE_TXELECIDLE(1) => pipe_tx1_elec_idle_gt, + PIPE_TXELECIDLE(0) => pipe_tx0_elec_idle_gt, + Q(2 downto 0) => pipe_tx_margin_gt(2 downto 0), + SR(0) => phy_rdy_n, + bridge_reset_int => bridge_reset_int, + cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en, + cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en, + cfg_aer_interrupt_msgnum(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0), + cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received, + cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en, + cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received, + cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en, + cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received, + cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en, + cfg_bridge_serr_en => cfg_bridge_serr_en, + cfg_bus_number(7 downto 0) => cfg_bus_number(7 downto 0), + cfg_command(4 downto 0) => cfg_command(4 downto 0), + cfg_dcommand(14 downto 0) => cfg_dcommand(14 downto 0), + cfg_dcommand2(11 downto 0) => cfg_dcommand2(11 downto 0), + cfg_device_number(4 downto 0) => cfg_device_number(4 downto 0), + cfg_ds_bus_number(7 downto 0) => cfg_ds_bus_number(7 downto 0), + cfg_ds_device_number(4 downto 0) => cfg_ds_device_number(4 downto 0), + cfg_ds_function_number(2 downto 0) => cfg_ds_function_number(2 downto 0), + cfg_dsn(63 downto 0) => cfg_dsn(63 downto 0), + cfg_dstatus(3 downto 0) => cfg_dstatus(3 downto 0), + cfg_err_aer_headerlog(127 downto 0) => cfg_err_aer_headerlog(127 downto 0), + cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set, + cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked, + cfg_err_cor => cfg_err_cor, + cfg_err_cpl_abort => cfg_err_cpl_abort, + cfg_err_cpl_rdy => cfg_err_cpl_rdy, + cfg_err_cpl_timeout => cfg_err_cpl_timeout, + cfg_err_cpl_unexpect => cfg_err_cpl_unexpect, + cfg_err_ecrc => cfg_err_ecrc, + cfg_err_internal_cor => cfg_err_internal_cor, + cfg_err_internal_uncor => cfg_err_internal_uncor, + cfg_err_locked => cfg_err_locked, + cfg_err_malformed => cfg_err_malformed, + cfg_err_mc_blocked => cfg_err_mc_blocked, + cfg_err_norecovery => cfg_err_norecovery, + cfg_err_poisoned => cfg_err_poisoned, + cfg_err_posted => cfg_err_posted, + cfg_err_tlp_cpl_header(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0), + cfg_err_ur => cfg_err_ur, + cfg_function_number(2 downto 0) => cfg_function_number(2 downto 0), + cfg_interrupt => cfg_interrupt, + cfg_interrupt_assert => cfg_interrupt_assert, + cfg_interrupt_di(7 downto 0) => cfg_interrupt_di(7 downto 0), + cfg_interrupt_do(7 downto 0) => cfg_interrupt_do(7 downto 0), + cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0), + cfg_interrupt_msienable => cfg_interrupt_msienable, + cfg_interrupt_msixenable => cfg_interrupt_msixenable, + cfg_interrupt_msixfm => cfg_interrupt_msixfm, + cfg_interrupt_rdy => cfg_interrupt_rdy, + cfg_interrupt_stat => cfg_interrupt_stat, + cfg_lcommand(10 downto 0) => cfg_lcommand(10 downto 0), + cfg_lstatus(9 downto 0) => cfg_lstatus(9 downto 0), + cfg_mgmt_byte_en_n(3) => pcie_block_i_i_32_n_0, + cfg_mgmt_byte_en_n(2) => pcie_block_i_i_33_n_0, + cfg_mgmt_byte_en_n(1) => pcie_block_i_i_34_n_0, + cfg_mgmt_byte_en_n(0) => pcie_block_i_i_35_n_0, + cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0), + cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0), + cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0), + cfg_mgmt_rd_en => cfg_mgmt_rd_en, + cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done, + cfg_mgmt_wr_en => cfg_mgmt_wr_en, + cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly, + cfg_mgmt_wr_rw1c_as_rw => cfg_mgmt_wr_rw1c_as_rw, + cfg_msg_data(15 downto 0) => cfg_msg_data(15 downto 0), + cfg_msg_received => cfg_msg_received, + cfg_msg_received_assert_int_a => cfg_msg_received_assert_int_a, + cfg_msg_received_assert_int_b => cfg_msg_received_assert_int_b, + cfg_msg_received_assert_int_c => cfg_msg_received_assert_int_c, + cfg_msg_received_assert_int_d => cfg_msg_received_assert_int_d, + cfg_msg_received_deassert_int_a => cfg_msg_received_deassert_int_a, + cfg_msg_received_deassert_int_b => cfg_msg_received_deassert_int_b, + cfg_msg_received_deassert_int_c => cfg_msg_received_deassert_int_c, + cfg_msg_received_deassert_int_d => cfg_msg_received_deassert_int_d, + cfg_msg_received_err_cor => cfg_msg_received_err_cor, + cfg_msg_received_err_fatal => cfg_msg_received_err_fatal, + cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal, + cfg_msg_received_pm_as_nak => cfg_msg_received_pm_as_nak, + cfg_msg_received_pm_pme => cfg_msg_received_pm_pme, + cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack, + cfg_msg_received_setslotpowerlimit => cfg_msg_received_setslotpowerlimit, + cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0), + cfg_pciecap_interrupt_msgnum(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0), + cfg_pm_force_state(1 downto 0) => cfg_pm_force_state(1 downto 0), + cfg_pm_force_state_en => cfg_pm_force_state_en, + cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s, + cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1, + cfg_pm_wake => cfg_pm_wake, + cfg_pmcsr_pme_en => cfg_pmcsr_pme_en, + cfg_pmcsr_pme_status => cfg_pmcsr_pme_status, + cfg_pmcsr_powerstate(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0), + cfg_received_func_lvl_rst => cfg_received_func_lvl_rst, + cfg_root_control_pme_int_en => cfg_root_control_pme_int_en, + cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en, + cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en, + cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en, + cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse, + cfg_to_turnoff => cfg_to_turnoff, + cfg_trn_pending => cfg_trn_pending, + cfg_turnoff_ok => cfg_turnoff_ok, + cfg_vc_tcvc_map(6 downto 0) => cfg_vc_tcvc_map(6 downto 0), + fc_cpld(11 downto 0) => fc_cpld(11 downto 0), + fc_cplh(7 downto 0) => fc_cplh(7 downto 0), + fc_npd(11 downto 0) => fc_npd(11 downto 0), + fc_nph(7 downto 0) => fc_nph(7 downto 0), + fc_pd(11 downto 0) => fc_pd(11 downto 0), + fc_ph(7 downto 0) => fc_ph(7 downto 0), + fc_sel(2 downto 0) => fc_sel(2 downto 0), + gt_rx_phy_status_q => gt_rx_phy_status_q, + gt_rxelecidle_q => gt_rxelecidle_q, + m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0), + m_axis_rx_tkeep(0) => m_axis_rx_tkeep(0), + m_axis_rx_tlast => m_axis_rx_tlast, + m_axis_rx_tready => m_axis_rx_tready, + m_axis_rx_tuser(12 downto 0) => m_axis_rx_tuser(12 downto 0), + m_axis_rx_tvalid_reg => m_axis_rx_tvalid, + \out\ => user_lnk_up_int, + pcie_drp_addr(8 downto 0) => pcie_drp_addr(8 downto 0), + pcie_drp_clk => pcie_drp_clk, + pcie_drp_di(15 downto 0) => pcie_drp_di(15 downto 0), + pcie_drp_do(15 downto 0) => pcie_drp_do(15 downto 0), + pcie_drp_en => pcie_drp_en, + pcie_drp_rdy => pcie_drp_rdy, + pcie_drp_we => pcie_drp_we, + pipe_pclk_in => pipe_pclk_in, + pipe_rx0_valid_gt => pipe_rx0_valid_gt, + pipe_rx1_valid_gt => pipe_rx1_valid_gt, + pipe_rx2_valid_gt => pipe_rx2_valid_gt, + pipe_rx3_valid_gt => pipe_rx3_valid_gt, + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0) => pipe_rx2_char_is_k_gt(1 downto 0), + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0) => pipe_rx3_char_is_k_gt(1 downto 0), + \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0) => pipe_rx0_char_is_k_gt(1 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => pipe_rx1_data_gt(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0) => pipe_rx2_data_gt(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0) => pipe_rx3_data_gt(15 downto 0), + \pipe_stages_1.pipe_rx_data_q_reg[15]_2\(15 downto 0) => pipe_rx0_data_gt(15 downto 0), + \pipe_stages_1.pipe_rx_elec_idle_q_reg\ => gt_top_i_n_6, + \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ => gt_top_i_n_8, + \pipe_stages_1.pipe_rx_elec_idle_q_reg_1\ => gt_top_i_n_10, + \pipe_stages_1.pipe_rx_phy_status_q_reg\ => gt_top_i_n_5, + \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ => gt_top_i_n_7, + \pipe_stages_1.pipe_rx_phy_status_q_reg_1\ => gt_top_i_n_9, + \pipe_stages_1.pipe_rx_status_q_reg[2]\(2) => gt_top_i_n_78, + \pipe_stages_1.pipe_rx_status_q_reg[2]\(1) => gt_top_i_n_79, + \pipe_stages_1.pipe_rx_status_q_reg[2]\(0) => gt_top_i_n_80, + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2) => gt_top_i_n_81, + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(1) => gt_top_i_n_82, + \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(0) => gt_top_i_n_83, + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2) => gt_top_i_n_84, + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(1) => gt_top_i_n_85, + \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(0) => gt_top_i_n_86, + \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(2) => gt_top_i_n_87, + \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(1) => gt_top_i_n_88, + \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(0) => gt_top_i_n_89, + \pipe_stages_1.pipe_tx_rate_q_reg\(0) => pipe_tx_rate_gt, + pipe_tx_deemph_gt => pipe_tx_deemph_gt, + pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt, + pipe_userclk1_in => pipe_userclk1_in, + pipe_userclk2_in => pipe_userclk2_in, + pl_directed_change_done => pl_directed_change_done, + pl_directed_link_auton => pl_directed_link_auton, + pl_directed_link_change(1 downto 0) => pl_directed_link_change(1 downto 0), + pl_directed_link_speed => pl_directed_link_speed, + pl_directed_link_width(1 downto 0) => pl_directed_link_width(1 downto 0), + pl_downstream_deemph_source => pl_downstream_deemph_source, + pl_initial_link_width(2 downto 0) => pl_initial_link_width(2 downto 0), + pl_lane_reversal_mode(1 downto 0) => pl_lane_reversal_mode(1 downto 0), + pl_link_gen2_cap => pl_link_gen2_cap, + pl_link_partner_gen2_supported => pl_link_partner_gen2_supported, + pl_link_upcfg_cap => pl_link_upcfg_cap, + pl_ltssm_state(5 downto 0) => \^pl_ltssm_state\(5 downto 0), + pl_phy_lnk_up => \^pl_phy_lnk_up\, + pl_received_hot_rst => pl_received_hot_rst_wire, + pl_rx_pm_state(1 downto 0) => pl_rx_pm_state(1 downto 0), + pl_sel_lnk_rate => pl_sel_lnk_rate, + pl_sel_lnk_width(1 downto 0) => pl_sel_lnk_width(1 downto 0), + pl_transmit_hot_rst => pl_transmit_hot_rst, + pl_tx_pm_state(2 downto 0) => pl_tx_pm_state(2 downto 0), + pl_upstream_prefer_deemph => pl_upstream_prefer_deemph, + rx_np_ok => rx_np_ok, + rx_np_req => rx_np_req, + s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0), + s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0), + s_axis_tx_tlast => s_axis_tx_tlast, + s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0), + s_axis_tx_tvalid => s_axis_tx_tvalid, + src_in => pl_phy_lnk_up_wire, + sys_rst_n => gt_top_i_n_13, + \throttle_ctl_pipeline.reg_tkeep_reg[7]\ => \^user_reset_out\, + tready_thrtl_reg => s_axis_tx_tready, + trn_lnk_up => trn_lnk_up, + trn_tbuf_av(5 downto 0) => tx_buf_av(5 downto 0), + trn_tcfg_req => tx_cfg_req, + tx_cfg_gnt => tx_cfg_gnt, + tx_err_drop => tx_err_drop, + user_reset_int_reg => pcie_top_i_n_20 + ); +phy_lnk_up_cdc: entity work.\pcie_7x_0_xpm_cdc_single__2\ + port map ( + dest_clk => pipe_userclk2_in, + dest_out => pl_phy_lnk_up_sync, + src_clk => '0', + src_in => pl_phy_lnk_up_wire + ); +pl_phy_lnk_up_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => pl_phy_lnk_up_sync, + Q => \^pl_phy_lnk_up\, + R => gt_top_i_n_120 + ); +pl_received_hot_rst_cdc: entity work.pcie_7x_0_xpm_cdc_single + port map ( + dest_clk => pipe_userclk2_in, + dest_out => pl_received_hot_rst_sync, + src_clk => '0', + src_in => pl_received_hot_rst_wire + ); +pl_received_hot_rst_q_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => pl_received_hot_rst_sync, + Q => \^pl_received_hot_rst\, + R => gt_top_i_n_120 + ); +user_lnk_up_int_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => trn_lnk_up, + Q => user_lnk_up_int, + R => gt_top_i_n_120 + ); +user_lnk_up_mux_reg: unisim.vcomponents.FDRE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => user_lnk_up_int, + Q => user_lnk_up_mux, + R => gt_top_i_n_120 + ); +user_reset_int_reg: unisim.vcomponents.FDPE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => pcie_top_i_n_20, + PRE => sys_or_hot_rst, + Q => bridge_reset_int + ); +user_reset_out_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^pl_received_hot_rst\, + I1 => sys_rst_n, + O => sys_or_hot_rst + ); +user_reset_out_reg: unisim.vcomponents.FDPE + port map ( + C => pipe_userclk2_in, + CE => '1', + D => bridge_reset_int, + PRE => sys_or_hot_rst, + Q => \^user_reset_out\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0_pcie_7x_0_pcie2_top is + port ( + pci_exp_txn : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_txp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_rxn : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_rxp : in STD_LOGIC_VECTOR ( 3 downto 0 ); + int_pclk_out_slave : out STD_LOGIC; + int_pipe_rxusrclk_out : out STD_LOGIC; + int_rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); + int_dclk_out : out STD_LOGIC; + int_userclk1_out : out STD_LOGIC; + int_userclk2_out : out STD_LOGIC; + int_oobclk_out : out STD_LOGIC; + int_mmcm_lock_out : out STD_LOGIC; + int_qplllock_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); + int_qplloutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); + int_qplloutrefclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); + int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_pclk_in : in STD_LOGIC; + pipe_rxusrclk_in : in STD_LOGIC; + pipe_rxoutclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_dclk_in : in STD_LOGIC; + pipe_userclk1_in : in STD_LOGIC; + pipe_userclk2_in : in STD_LOGIC; + pipe_oobclk_in : in STD_LOGIC; + pipe_mmcm_lock_in : in STD_LOGIC; + pipe_txoutclk_out : out STD_LOGIC; + pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_gen3_out : out STD_LOGIC; + qpll_drp_crscode : in STD_LOGIC_VECTOR ( 11 downto 0 ); + qpll_drp_fsm : in STD_LOGIC_VECTOR ( 17 downto 0 ); + qpll_drp_done : in STD_LOGIC_VECTOR ( 1 downto 0 ); + qpll_drp_reset : in STD_LOGIC_VECTOR ( 1 downto 0 ); + qpll_qplllock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + qpll_qplloutclk : in STD_LOGIC_VECTOR ( 1 downto 0 ); + qpll_qplloutrefclk : in STD_LOGIC_VECTOR ( 1 downto 0 ); + qpll_qplld : out STD_LOGIC; + qpll_qpllreset : out STD_LOGIC_VECTOR ( 1 downto 0 ); + qpll_drp_clk : out STD_LOGIC; + qpll_drp_rst_n : out STD_LOGIC; + qpll_drp_ovrd : out STD_LOGIC; + qpll_drp_gen3 : out STD_LOGIC; + qpll_drp_start : out STD_LOGIC; + user_clk_out : out STD_LOGIC; + user_reset_out : out STD_LOGIC; + user_lnk_up : out STD_LOGIC; + user_app_rdy : out STD_LOGIC; + tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 ); + tx_err_drop : out STD_LOGIC; + tx_cfg_req : out STD_LOGIC; + s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_tx_tvalid : in STD_LOGIC; + s_axis_tx_tready : out STD_LOGIC; + s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_tx_tlast : in STD_LOGIC; + s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ); + tx_cfg_gnt : in STD_LOGIC; + m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axis_rx_tvalid : out STD_LOGIC; + m_axis_rx_tready : in STD_LOGIC; + m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axis_rx_tlast : out STD_LOGIC; + m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 ); + rx_np_ok : in STD_LOGIC; + rx_np_req : in STD_LOGIC; + fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_rd_wr_done : out STD_LOGIC; + cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_dcommand2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_pmcsr_pme_en : out STD_LOGIC; + cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_pmcsr_pme_status : out STD_LOGIC; + cfg_received_func_lvl_rst : out STD_LOGIC; + cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_byte_en : in STD_LOGIC_VECTOR ( 3 downto 0 ); + cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); + cfg_mgmt_wr_en : in STD_LOGIC; + cfg_mgmt_rd_en : in STD_LOGIC; + cfg_mgmt_wr_readonly : in STD_LOGIC; + cfg_err_ecrc : in STD_LOGIC; + cfg_err_ur : in STD_LOGIC; + cfg_err_cpl_timeout : in STD_LOGIC; + cfg_err_cpl_unexpect : in STD_LOGIC; + cfg_err_cpl_abort : in STD_LOGIC; + cfg_err_posted : in STD_LOGIC; + cfg_err_cor : in STD_LOGIC; + cfg_err_atomic_egress_blocked : in STD_LOGIC; + cfg_err_internal_cor : in STD_LOGIC; + cfg_err_malformed : in STD_LOGIC; + cfg_err_mc_blocked : in STD_LOGIC; + cfg_err_poisoned : in STD_LOGIC; + cfg_err_norecovery : in STD_LOGIC; + cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); + cfg_err_cpl_rdy : out STD_LOGIC; + cfg_err_locked : in STD_LOGIC; + cfg_err_acs : in STD_LOGIC; + cfg_err_internal_uncor : in STD_LOGIC; + cfg_trn_pending : in STD_LOGIC; + cfg_pm_halt_aspm_l0s : in STD_LOGIC; + cfg_pm_halt_aspm_l1 : in STD_LOGIC; + cfg_pm_force_state_en : in STD_LOGIC; + cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); + cfg_msg_received : out STD_LOGIC; + cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_interrupt : in STD_LOGIC; + cfg_interrupt_rdy : out STD_LOGIC; + cfg_interrupt_assert : in STD_LOGIC; + cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_interrupt_msienable : out STD_LOGIC; + cfg_interrupt_msixenable : out STD_LOGIC; + cfg_interrupt_msixfm : out STD_LOGIC; + cfg_interrupt_stat : in STD_LOGIC; + cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_to_turnoff : out STD_LOGIC; + cfg_turnoff_ok : in STD_LOGIC; + cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_pm_wake : in STD_LOGIC; + cfg_msg_received_pm_as_nak : out STD_LOGIC; + cfg_msg_received_setslotpowerlimit : out STD_LOGIC; + cfg_pm_send_pme_to : in STD_LOGIC; + cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC; + cfg_bridge_serr_en : out STD_LOGIC; + cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC; + cfg_root_control_syserr_corr_err_en : out STD_LOGIC; + cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC; + cfg_root_control_syserr_fatal_err_en : out STD_LOGIC; + cfg_root_control_pme_int_en : out STD_LOGIC; + cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_corr_err_received : out STD_LOGIC; + cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC; + cfg_aer_rooterr_fatal_err_received : out STD_LOGIC; + cfg_msg_received_err_cor : out STD_LOGIC; + cfg_msg_received_err_non_fatal : out STD_LOGIC; + cfg_msg_received_err_fatal : out STD_LOGIC; + cfg_msg_received_pm_pme : out STD_LOGIC; + cfg_msg_received_pme_to_ack : out STD_LOGIC; + cfg_msg_received_assert_int_a : out STD_LOGIC; + cfg_msg_received_assert_int_b : out STD_LOGIC; + cfg_msg_received_assert_int_c : out STD_LOGIC; + cfg_msg_received_assert_int_d : out STD_LOGIC; + cfg_msg_received_deassert_int_a : out STD_LOGIC; + cfg_msg_received_deassert_int_b : out STD_LOGIC; + cfg_msg_received_deassert_int_c : out STD_LOGIC; + cfg_msg_received_deassert_int_d : out STD_LOGIC; + pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_directed_link_speed : in STD_LOGIC; + pl_directed_link_auton : in STD_LOGIC; + pl_upstream_prefer_deemph : in STD_LOGIC; + pl_sel_lnk_rate : out STD_LOGIC; + pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 ); + pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_phy_lnk_up : out STD_LOGIC; + pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_link_upcfg_cap : out STD_LOGIC; + pl_link_gen2_cap : out STD_LOGIC; + pl_link_partner_gen2_supported : out STD_LOGIC; + pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pl_directed_change_done : out STD_LOGIC; + pl_received_hot_rst : out STD_LOGIC; + pl_transmit_hot_rst : in STD_LOGIC; + pl_downstream_deemph_source : in STD_LOGIC; + cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 ); + cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_err_aer_headerlog_set : out STD_LOGIC; + cfg_aer_ecrc_check_en : out STD_LOGIC; + cfg_aer_ecrc_gen_en : out STD_LOGIC; + cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 ); + pcie_drp_clk : in STD_LOGIC; + pcie_drp_en : in STD_LOGIC; + pcie_drp_we : in STD_LOGIC; + pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 ); + pcie_drp_rdy : out STD_LOGIC; + pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 ); + startup_eos_in : in STD_LOGIC; + startup_cfgclk : out STD_LOGIC; + startup_cfgmclk : out STD_LOGIC; + startup_eos : out STD_LOGIC; + startup_preq : out STD_LOGIC; + startup_clk : in STD_LOGIC; + startup_gsr : in STD_LOGIC; + startup_gts : in STD_LOGIC; + startup_keyclearb : in STD_LOGIC; + startup_pack : in STD_LOGIC; + startup_usrcclko : in STD_LOGIC; + startup_usrcclkts : in STD_LOGIC; + startup_usrdoneo : in STD_LOGIC; + startup_usrdonets : in STD_LOGIC; + icap_clk : in STD_LOGIC; + icap_csib : in STD_LOGIC; + icap_rdwrb : in STD_LOGIC; + icap_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); + icap_o : out STD_LOGIC_VECTOR ( 31 downto 0 ); + pipe_txprbssel : in STD_LOGIC_VECTOR ( 2 downto 0 ); + pipe_rxprbssel : in STD_LOGIC_VECTOR ( 2 downto 0 ); + pipe_txprbsforceerr : in STD_LOGIC; + pipe_rxprbscntreset : in STD_LOGIC; + pipe_loopback : in STD_LOGIC_VECTOR ( 2 downto 0 ); + pipe_rxprbserr : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_txinhibit : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_rst_fsm : out STD_LOGIC_VECTOR ( 4 downto 0 ); + pipe_qrst_fsm : out STD_LOGIC_VECTOR ( 11 downto 0 ); + pipe_rate_fsm : out STD_LOGIC_VECTOR ( 19 downto 0 ); + pipe_sync_fsm_tx : out STD_LOGIC_VECTOR ( 23 downto 0 ); + pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 27 downto 0 ); + pipe_drp_fsm : out STD_LOGIC_VECTOR ( 27 downto 0 ); + pipe_rst_idle : out STD_LOGIC; + pipe_qrst_idle : out STD_LOGIC; + pipe_rate_idle : out STD_LOGIC; + pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_rxstatus : out STD_LOGIC_VECTOR ( 11 downto 0 ); + pipe_dmonitorout : out STD_LOGIC_VECTOR ( 59 downto 0 ); + pipe_cpll_lock : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_qpll_lock : out STD_LOGIC_VECTOR ( 0 to 0 ); + pipe_rxpmaresetdone : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 11 downto 0 ); + pipe_txphaligndone : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_txphinitdone : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_rxsyncdone : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_rxdisperr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + pipe_rxnotintable : out STD_LOGIC_VECTOR ( 31 downto 0 ); + pipe_rxcommadet : out STD_LOGIC_VECTOR ( 3 downto 0 ); + gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_debug_0 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_debug_1 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_debug_2 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_debug_3 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_debug_4 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_debug_5 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_debug_6 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_debug_7 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_debug_8 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_debug_9 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_debug : out STD_LOGIC_VECTOR ( 31 downto 0 ); + ext_ch_gt_drpclk : out STD_LOGIC; + ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 35 downto 0 ); + ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 63 downto 0 ); + ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 3 downto 0 ); + ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 63 downto 0 ); + ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 3 downto 0 ); + common_commands_in : in STD_LOGIC_VECTOR ( 11 downto 0 ); + pipe_rx_0_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_rx_1_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_rx_2_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_rx_3_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_rx_4_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_rx_5_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_rx_6_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_rx_7_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 ); + common_commands_out : out STD_LOGIC_VECTOR ( 11 downto 0 ); + pipe_tx_0_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_tx_1_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_tx_2_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_tx_3_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_tx_4_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_tx_5_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_tx_6_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_tx_7_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 ); + pipe_mmcm_rst_n : in STD_LOGIC; + sys_clk : in STD_LOGIC; + sys_rst_n : in STD_LOGIC + ); + attribute CFG_CTL_IF : string; + attribute CFG_CTL_IF of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute CFG_FC_IF : string; + attribute CFG_FC_IF of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute CFG_MGMT_IF : string; + attribute CFG_MGMT_IF of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute CFG_STATUS_IF : string; + attribute CFG_STATUS_IF of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute C_DATA_WIDTH : integer; + attribute C_DATA_WIDTH of pcie_7x_0_pcie_7x_0_pcie2_top : entity is 64; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "yes"; + attribute ENABLE_JTAG_DBG : string; + attribute ENABLE_JTAG_DBG of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute ERR_REPORTING_IF : string; + attribute ERR_REPORTING_IF of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute EXT_CH_GT_DRP : string; + attribute EXT_CH_GT_DRP of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute EXT_PIPE_INTERFACE : string; + attribute EXT_PIPE_INTERFACE of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute EXT_STARTUP_PRIMITIVE : string; + attribute EXT_STARTUP_PRIMITIVE of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute KEEP_WIDTH : integer; + attribute KEEP_WIDTH of pcie_7x_0_pcie_7x_0_pcie2_top : entity is 8; + attribute LINK_CAP_MAX_LINK_WIDTH : integer; + attribute LINK_CAP_MAX_LINK_WIDTH of pcie_7x_0_pcie_7x_0_pcie2_top : entity is 4; + attribute PCIE_ASYNC_EN : string; + attribute PCIE_ASYNC_EN of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute PCIE_EXT_CLK : string; + attribute PCIE_EXT_CLK of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute PCIE_EXT_GT_COMMON : string; + attribute PCIE_EXT_GT_COMMON of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute PIPE_SIM : string; + attribute PIPE_SIM of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute PL_INTERFACE : string; + attribute PL_INTERFACE of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute RCV_MSG_IF : string; + attribute RCV_MSG_IF of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute REDUCE_OOB_FREQ : string; + attribute REDUCE_OOB_FREQ of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute SHARED_LOGIC_IN_CORE : string; + attribute SHARED_LOGIC_IN_CORE of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute TRANSCEIVER_CTRL_STATUS_PORTS : string; + attribute TRANSCEIVER_CTRL_STATUS_PORTS of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute bar_0 : string; + attribute bar_0 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FFFF0000"; + attribute bar_1 : string; + attribute bar_1 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00000000"; + attribute bar_2 : string; + attribute bar_2 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00000000"; + attribute bar_3 : string; + attribute bar_3 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00000000"; + attribute bar_4 : string; + attribute bar_4 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00000000"; + attribute bar_5 : string; + attribute bar_5 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00000000"; + attribute bram_lat : string; + attribute bram_lat of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_aer_base_ptr : string; + attribute c_aer_base_ptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "000"; + attribute c_aer_cap_ecrc_check_capable : string; + attribute c_aer_cap_ecrc_check_capable of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_aer_cap_ecrc_gen_capable : string; + attribute c_aer_cap_ecrc_gen_capable of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_aer_cap_multiheader : string; + attribute c_aer_cap_multiheader of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_aer_cap_nextptr : string; + attribute c_aer_cap_nextptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "000"; + attribute c_aer_cap_on : string; + attribute c_aer_cap_on of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_aer_cap_optional_err_support : string; + attribute c_aer_cap_optional_err_support of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "000000"; + attribute c_aer_cap_permit_rooterr_update : string; + attribute c_aer_cap_permit_rooterr_update of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_buf_opt_bma : string; + attribute c_buf_opt_bma of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_component_name : string; + attribute c_component_name of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "pcie_7x_0"; + attribute c_cpl_inf : string; + attribute c_cpl_inf of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_cpl_infinite : string; + attribute c_cpl_infinite of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_cpl_timeout_disable_sup : string; + attribute c_cpl_timeout_disable_sup of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_cpl_timeout_range : string; + attribute c_cpl_timeout_range of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0010"; + attribute c_cpl_timeout_ranges_sup : string; + attribute c_cpl_timeout_ranges_sup of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "2"; + attribute c_d1_support : string; + attribute c_d1_support of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_d2_support : string; + attribute c_d2_support of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_de_emph : string; + attribute c_de_emph of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_dev_cap2_ari_forwarding_supported : string; + attribute c_dev_cap2_ari_forwarding_supported of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_dev_cap2_atomicop32_completer_supported : string; + attribute c_dev_cap2_atomicop32_completer_supported of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_dev_cap2_atomicop64_completer_supported : string; + attribute c_dev_cap2_atomicop64_completer_supported of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_dev_cap2_atomicop_routing_supported : string; + attribute c_dev_cap2_atomicop_routing_supported of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_dev_cap2_cas128_completer_supported : string; + attribute c_dev_cap2_cas128_completer_supported of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_dev_cap2_tph_completer_supported : string; + attribute c_dev_cap2_tph_completer_supported of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute c_dev_control_ext_tag_default : string; + attribute c_dev_control_ext_tag_default of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_dev_port_type : string; + attribute c_dev_port_type of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_dis_lane_reverse : string; + attribute c_dis_lane_reverse of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_disable_rx_poisoned_resp : string; + attribute c_disable_rx_poisoned_resp of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_disable_scrambling : string; + attribute c_disable_scrambling of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_disable_tx_aspm_l0s : string; + attribute c_disable_tx_aspm_l0s of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_dll_lnk_actv_cap : string; + attribute c_dll_lnk_actv_cap of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_dsi_bool : string; + attribute c_dsi_bool of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_dsn_base_ptr : string; + attribute c_dsn_base_ptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "100"; + attribute c_dsn_cap_enabled : string; + attribute c_dsn_cap_enabled of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_dsn_next_ptr : string; + attribute c_dsn_next_ptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "000"; + attribute c_enable_msg_route : string; + attribute c_enable_msg_route of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00000000000"; + attribute c_ep_l0s_accpt_lat : string; + attribute c_ep_l0s_accpt_lat of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_ep_l1_accpt_lat : string; + attribute c_ep_l1_accpt_lat of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "7"; + attribute c_ext_pci_cfg_space_addr : string; + attribute c_ext_pci_cfg_space_addr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "3FF"; + attribute c_external_clocking : string; + attribute c_external_clocking of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_fc_cpld : string; + attribute c_fc_cpld of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "973"; + attribute c_fc_cplh : string; + attribute c_fc_cplh of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "36"; + attribute c_fc_npd : string; + attribute c_fc_npd of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "24"; + attribute c_fc_nph : string; + attribute c_fc_nph of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "12"; + attribute c_fc_pd : string; + attribute c_fc_pd of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "949"; + attribute c_fc_ph : string; + attribute c_fc_ph of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "32"; + attribute c_gen1 : string; + attribute c_gen1 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "1'b1"; + attribute c_header_type : string; + attribute c_header_type of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute c_hw_auton_spd_disable : string; + attribute c_hw_auton_spd_disable of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_int_width : integer; + attribute c_int_width of pcie_7x_0_pcie_7x_0_pcie2_top : entity is 64; + attribute c_last_cfg_dw : string; + attribute c_last_cfg_dw of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "10C"; + attribute c_link_cap_aspm_optionality : string; + attribute c_link_cap_aspm_optionality of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_ll_ack_timeout : string; + attribute c_ll_ack_timeout of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0000"; + attribute c_ll_ack_timeout_enable : string; + attribute c_ll_ack_timeout_enable of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_ll_ack_timeout_function : string; + attribute c_ll_ack_timeout_function of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_ll_replay_timeout : string; + attribute c_ll_replay_timeout of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0000"; + attribute c_ll_replay_timeout_enable : string; + attribute c_ll_replay_timeout_enable of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_ll_replay_timeout_func : string; + attribute c_ll_replay_timeout_func of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "1"; + attribute c_lnk_bndwdt_notif : string; + attribute c_lnk_bndwdt_notif of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_msi : string; + attribute c_msi of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_msi_64b_addr : string; + attribute c_msi_64b_addr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_msi_cap_on : string; + attribute c_msi_cap_on of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_msi_mult_msg_extn : string; + attribute c_msi_mult_msg_extn of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_msi_per_vctr_mask_cap : string; + attribute c_msi_per_vctr_mask_cap of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_msix_cap_on : string; + attribute c_msix_cap_on of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_msix_next_ptr : string; + attribute c_msix_next_ptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute c_msix_pba_bir : string; + attribute c_msix_pba_bir of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_msix_pba_offset : string; + attribute c_msix_pba_offset of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_msix_table_bir : string; + attribute c_msix_table_bir of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_msix_table_offset : string; + attribute c_msix_table_offset of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_msix_table_size : string; + attribute c_msix_table_size of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "000"; + attribute c_pci_cfg_space_addr : string; + attribute c_pci_cfg_space_addr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "3F"; + attribute c_pcie_blk_locn : string; + attribute c_pcie_blk_locn of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_pcie_cap_next_ptr : string; + attribute c_pcie_cap_next_ptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute c_pcie_cap_slot_implemented : string; + attribute c_pcie_cap_slot_implemented of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_pcie_dbg_ports : string; + attribute c_pcie_dbg_ports of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_pcie_fast_config : integer; + attribute c_pcie_fast_config of pcie_7x_0_pcie_7x_0_pcie2_top : entity is 0; + attribute c_perf_level_high : string; + attribute c_perf_level_high of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_phantom_functions : string; + attribute c_phantom_functions of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_pm_cap_next_ptr : string; + attribute c_pm_cap_next_ptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "60"; + attribute c_pme_support : string; + attribute c_pme_support of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0F"; + attribute c_rbar_base_ptr : string; + attribute c_rbar_base_ptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "000"; + attribute c_rbar_cap_control_encodedbar0 : string; + attribute c_rbar_cap_control_encodedbar0 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute c_rbar_cap_control_encodedbar1 : string; + attribute c_rbar_cap_control_encodedbar1 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute c_rbar_cap_control_encodedbar2 : string; + attribute c_rbar_cap_control_encodedbar2 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute c_rbar_cap_control_encodedbar3 : string; + attribute c_rbar_cap_control_encodedbar3 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute c_rbar_cap_control_encodedbar4 : string; + attribute c_rbar_cap_control_encodedbar4 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute c_rbar_cap_control_encodedbar5 : string; + attribute c_rbar_cap_control_encodedbar5 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute c_rbar_cap_index0 : string; + attribute c_rbar_cap_index0 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_rbar_cap_index1 : string; + attribute c_rbar_cap_index1 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_rbar_cap_index2 : string; + attribute c_rbar_cap_index2 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_rbar_cap_index3 : string; + attribute c_rbar_cap_index3 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_rbar_cap_index4 : string; + attribute c_rbar_cap_index4 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_rbar_cap_index5 : string; + attribute c_rbar_cap_index5 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_rbar_cap_nextptr : string; + attribute c_rbar_cap_nextptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "000"; + attribute c_rbar_cap_on : string; + attribute c_rbar_cap_on of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_rbar_cap_sup0 : string; + attribute c_rbar_cap_sup0 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00001"; + attribute c_rbar_cap_sup1 : string; + attribute c_rbar_cap_sup1 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00001"; + attribute c_rbar_cap_sup2 : string; + attribute c_rbar_cap_sup2 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00001"; + attribute c_rbar_cap_sup3 : string; + attribute c_rbar_cap_sup3 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00001"; + attribute c_rbar_cap_sup4 : string; + attribute c_rbar_cap_sup4 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00001"; + attribute c_rbar_cap_sup5 : string; + attribute c_rbar_cap_sup5 of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00001"; + attribute c_rbar_num : string; + attribute c_rbar_num of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_rcb : string; + attribute c_rcb of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_recrc_check : string; + attribute c_recrc_check of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_recrc_check_trim : string; + attribute c_recrc_check_trim of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_rev_gt_order : string; + attribute c_rev_gt_order of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_root_cap_crs : string; + attribute c_root_cap_crs of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_rx_raddr_lat : string; + attribute c_rx_raddr_lat of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_rx_ram_limit : string; + attribute c_rx_ram_limit of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FFF"; + attribute c_rx_rdata_lat : string; + attribute c_rx_rdata_lat of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "2"; + attribute c_rx_write_lat : string; + attribute c_rx_write_lat of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_silicon_rev : string; + attribute c_silicon_rev of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "2"; + attribute c_slot_cap_attn_butn : string; + attribute c_slot_cap_attn_butn of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_slot_cap_attn_ind : string; + attribute c_slot_cap_attn_ind of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_slot_cap_elec_interlock : string; + attribute c_slot_cap_elec_interlock of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_slot_cap_hotplug_cap : string; + attribute c_slot_cap_hotplug_cap of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_slot_cap_hotplug_surprise : string; + attribute c_slot_cap_hotplug_surprise of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_slot_cap_mrl : string; + attribute c_slot_cap_mrl of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_slot_cap_no_cmd_comp_sup : string; + attribute c_slot_cap_no_cmd_comp_sup of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_slot_cap_physical_slot_num : string; + attribute c_slot_cap_physical_slot_num of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_slot_cap_pwr_ctrl : string; + attribute c_slot_cap_pwr_ctrl of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_slot_cap_pwr_ind : string; + attribute c_slot_cap_pwr_ind of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_slot_cap_pwr_limit_scale : string; + attribute c_slot_cap_pwr_limit_scale of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_slot_cap_pwr_limit_value : string; + attribute c_slot_cap_pwr_limit_value of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_surprise_dn_err_cap : string; + attribute c_surprise_dn_err_cap of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_trgt_lnk_spd : string; + attribute c_trgt_lnk_spd of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "2"; + attribute c_trn_np_fc : string; + attribute c_trn_np_fc of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_tx_last_tlp : string; + attribute c_tx_last_tlp of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "30"; + attribute c_tx_raddr_lat : string; + attribute c_tx_raddr_lat of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_tx_rdata_lat : string; + attribute c_tx_rdata_lat of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "2"; + attribute c_tx_write_lat : string; + attribute c_tx_write_lat of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute c_upconfig_capable : string; + attribute c_upconfig_capable of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_upstream_facing : string; + attribute c_upstream_facing of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_ur_atomic : string; + attribute c_ur_atomic of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_ur_inv_req : string; + attribute c_ur_inv_req of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_ur_prs_response : string; + attribute c_ur_prs_response of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute c_vc_base_ptr : string; + attribute c_vc_base_ptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "000"; + attribute c_vc_cap_enabled : string; + attribute c_vc_cap_enabled of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_vc_cap_reject_snoop : string; + attribute c_vc_cap_reject_snoop of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_vc_next_ptr : string; + attribute c_vc_next_ptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "000"; + attribute c_vsec_base_ptr : string; + attribute c_vsec_base_ptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "000"; + attribute c_vsec_cap_enabled : string; + attribute c_vsec_cap_enabled of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute c_vsec_next_ptr : string; + attribute c_vsec_next_ptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "000"; + attribute c_xlnx_ref_board : string; + attribute c_xlnx_ref_board of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "ZC706"; + attribute cap_ver : string; + attribute cap_ver of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "2"; + attribute cardbus_cis_ptr : string; + attribute cardbus_cis_ptr of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00000000"; + attribute class_code : string; + attribute class_code of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "050000"; + attribute cmps : string; + attribute cmps of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "3"; + attribute con_scl_fctr_d0_state : string; + attribute con_scl_fctr_d0_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute con_scl_fctr_d1_state : string; + attribute con_scl_fctr_d1_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute con_scl_fctr_d2_state : string; + attribute con_scl_fctr_d2_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute con_scl_fctr_d3_state : string; + attribute con_scl_fctr_d3_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute cost_table : integer; + attribute cost_table of pcie_7x_0_pcie_7x_0_pcie2_top : entity is 1; + attribute d1_sup : string; + attribute d1_sup of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute d2_sup : string; + attribute d2_sup of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute dev_id : string; + attribute dev_id of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "7024"; + attribute dev_port_type : string; + attribute dev_port_type of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0000"; + attribute dis_scl_fctr_d0_state : string; + attribute dis_scl_fctr_d0_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute dis_scl_fctr_d1_state : string; + attribute dis_scl_fctr_d1_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute dis_scl_fctr_d2_state : string; + attribute dis_scl_fctr_d2_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute dis_scl_fctr_d3_state : string; + attribute dis_scl_fctr_d3_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute dsi : string; + attribute dsi of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute ep_l0s_accpt_lat : string; + attribute ep_l0s_accpt_lat of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "000"; + attribute ep_l1_accpt_lat : string; + attribute ep_l1_accpt_lat of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "111"; + attribute ext_tag_fld_sup : string; + attribute ext_tag_fld_sup of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "FALSE"; + attribute int_pin : string; + attribute int_pin of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "1"; + attribute intx : string; + attribute intx of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute max_lnk_spd : string; + attribute max_lnk_spd of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "2"; + attribute max_lnk_wdt : string; + attribute max_lnk_wdt of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "000100"; + attribute mps : string; + attribute mps of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "011"; + attribute no_soft_rst : string; + attribute no_soft_rst of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute pci_exp_int_freq : integer; + attribute pci_exp_int_freq of pcie_7x_0_pcie_7x_0_pcie2_top : entity is 3; + attribute pci_exp_ref_freq : string; + attribute pci_exp_ref_freq of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0"; + attribute phantm_func_sup : string; + attribute phantm_func_sup of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute pme_sup : string; + attribute pme_sup of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0F"; + attribute pwr_con_d0_state : string; + attribute pwr_con_d0_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute pwr_con_d1_state : string; + attribute pwr_con_d1_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute pwr_con_d2_state : string; + attribute pwr_con_d2_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute pwr_con_d3_state : string; + attribute pwr_con_d3_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute pwr_dis_d0_state : string; + attribute pwr_dis_d0_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute pwr_dis_d1_state : string; + attribute pwr_dis_d1_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute pwr_dis_d2_state : string; + attribute pwr_dis_d2_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute pwr_dis_d3_state : string; + attribute pwr_dis_d3_state of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute rev_id : string; + attribute rev_id of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00"; + attribute slot_clk : string; + attribute slot_clk of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "TRUE"; + attribute subsys_id : string; + attribute subsys_id of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "0007"; + attribute subsys_ven_id : string; + attribute subsys_ven_id of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "10EE"; + attribute ven_id : string; + attribute ven_id of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "10EE"; + attribute xrom_bar : string; + attribute xrom_bar of pcie_7x_0_pcie_7x_0_pcie2_top : entity is "00000000"; +end pcie_7x_0_pcie_7x_0_pcie2_top; + +architecture STRUCTURE of pcie_7x_0_pcie_7x_0_pcie2_top is + signal \\ : STD_LOGIC; + signal \^cfg_command\ : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \^cfg_dcommand\ : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal \^cfg_dcommand2\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \^cfg_dstatus\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^cfg_lcommand\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \^cfg_lstatus\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \^cfg_trn_pending\ : STD_LOGIC; + signal \^m_axis_rx_tkeep\ : STD_LOGIC_VECTOR ( 6 to 6 ); + signal \^m_axis_rx_tuser\ : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal \^pipe_userclk2_in\ : STD_LOGIC; +begin + \^cfg_trn_pending\ <= cfg_trn_pending; + \^pipe_userclk2_in\ <= pipe_userclk2_in; + cfg_command(15) <= \\; + cfg_command(14) <= \\; + cfg_command(13) <= \\; + cfg_command(12) <= \\; + cfg_command(11) <= \\; + cfg_command(10) <= \^cfg_command\(10); + cfg_command(9) <= \\; + cfg_command(8) <= \^cfg_command\(8); + cfg_command(7) <= \\; + cfg_command(6) <= \\; + cfg_command(5) <= \\; + cfg_command(4) <= \\; + cfg_command(3) <= \\; + cfg_command(2 downto 0) <= \^cfg_command\(2 downto 0); + cfg_dcommand(15) <= \\; + cfg_dcommand(14 downto 0) <= \^cfg_dcommand\(14 downto 0); + cfg_dcommand2(15) <= \\; + cfg_dcommand2(14) <= \\; + cfg_dcommand2(13) <= \\; + cfg_dcommand2(12) <= \\; + cfg_dcommand2(11 downto 0) <= \^cfg_dcommand2\(11 downto 0); + cfg_dstatus(15) <= \\; + cfg_dstatus(14) <= \\; + cfg_dstatus(13) <= \\; + cfg_dstatus(12) <= \\; + cfg_dstatus(11) <= \\; + cfg_dstatus(10) <= \\; + cfg_dstatus(9) <= \\; + cfg_dstatus(8) <= \\; + cfg_dstatus(7) <= \\; + cfg_dstatus(6) <= \\; + cfg_dstatus(5) <= \^cfg_trn_pending\; + cfg_dstatus(4) <= \\; + cfg_dstatus(3 downto 0) <= \^cfg_dstatus\(3 downto 0); + cfg_lcommand(15) <= \\; + cfg_lcommand(14) <= \\; + cfg_lcommand(13) <= \\; + cfg_lcommand(12) <= \\; + cfg_lcommand(11 downto 3) <= \^cfg_lcommand\(11 downto 3); + cfg_lcommand(2) <= \\; + cfg_lcommand(1 downto 0) <= \^cfg_lcommand\(1 downto 0); + cfg_lstatus(15 downto 13) <= \^cfg_lstatus\(15 downto 13); + cfg_lstatus(12) <= \\; + cfg_lstatus(11) <= \^cfg_lstatus\(11); + cfg_lstatus(10) <= \\; + cfg_lstatus(9) <= \\; + cfg_lstatus(8) <= \\; + cfg_lstatus(7 downto 4) <= \^cfg_lstatus\(7 downto 4); + cfg_lstatus(3) <= \\; + cfg_lstatus(2) <= \\; + cfg_lstatus(1 downto 0) <= \^cfg_lstatus\(1 downto 0); + cfg_status(15) <= \\; + cfg_status(14) <= \\; + cfg_status(13) <= \\; + cfg_status(12) <= \\; + cfg_status(11) <= \\; + cfg_status(10) <= \\; + cfg_status(9) <= \\; + cfg_status(8) <= \\; + cfg_status(7) <= \\; + cfg_status(6) <= \\; + cfg_status(5) <= \\; + cfg_status(4) <= \\; + cfg_status(3) <= \\; + cfg_status(2) <= \\; + cfg_status(1) <= \\; + cfg_status(0) <= \\; + common_commands_out(11) <= \\; + common_commands_out(10) <= \\; + common_commands_out(9) <= \\; + common_commands_out(8) <= \\; + common_commands_out(7) <= \\; + common_commands_out(6) <= \\; + common_commands_out(5) <= \\; + common_commands_out(4) <= \\; + common_commands_out(3) <= \\; + common_commands_out(2) <= \\; + common_commands_out(1) <= \\; + common_commands_out(0) <= \\; + ext_ch_gt_drpclk <= \\; + ext_ch_gt_drpdo(63) <= \\; + ext_ch_gt_drpdo(62) <= \\; + ext_ch_gt_drpdo(61) <= \\; + ext_ch_gt_drpdo(60) <= \\; + ext_ch_gt_drpdo(59) <= \\; + ext_ch_gt_drpdo(58) <= \\; + ext_ch_gt_drpdo(57) <= \\; + ext_ch_gt_drpdo(56) <= \\; + ext_ch_gt_drpdo(55) <= \\; + ext_ch_gt_drpdo(54) <= \\; + ext_ch_gt_drpdo(53) <= \\; + ext_ch_gt_drpdo(52) <= \\; + ext_ch_gt_drpdo(51) <= \\; + ext_ch_gt_drpdo(50) <= \\; + ext_ch_gt_drpdo(49) <= \\; + ext_ch_gt_drpdo(48) <= \\; + ext_ch_gt_drpdo(47) <= \\; + ext_ch_gt_drpdo(46) <= \\; + ext_ch_gt_drpdo(45) <= \\; + ext_ch_gt_drpdo(44) <= \\; + ext_ch_gt_drpdo(43) <= \\; + ext_ch_gt_drpdo(42) <= \\; + ext_ch_gt_drpdo(41) <= \\; + ext_ch_gt_drpdo(40) <= \\; + ext_ch_gt_drpdo(39) <= \\; + ext_ch_gt_drpdo(38) <= \\; + ext_ch_gt_drpdo(37) <= \\; + ext_ch_gt_drpdo(36) <= \\; + ext_ch_gt_drpdo(35) <= \\; + ext_ch_gt_drpdo(34) <= \\; + ext_ch_gt_drpdo(33) <= \\; + ext_ch_gt_drpdo(32) <= \\; + ext_ch_gt_drpdo(31) <= \\; + ext_ch_gt_drpdo(30) <= \\; + ext_ch_gt_drpdo(29) <= \\; + ext_ch_gt_drpdo(28) <= \\; + ext_ch_gt_drpdo(27) <= \\; + ext_ch_gt_drpdo(26) <= \\; + ext_ch_gt_drpdo(25) <= \\; + ext_ch_gt_drpdo(24) <= \\; + ext_ch_gt_drpdo(23) <= \\; + ext_ch_gt_drpdo(22) <= \\; + ext_ch_gt_drpdo(21) <= \\; + ext_ch_gt_drpdo(20) <= \\; + ext_ch_gt_drpdo(19) <= \\; + ext_ch_gt_drpdo(18) <= \\; + ext_ch_gt_drpdo(17) <= \\; + ext_ch_gt_drpdo(16) <= \\; + ext_ch_gt_drpdo(15) <= \\; + ext_ch_gt_drpdo(14) <= \\; + ext_ch_gt_drpdo(13) <= \\; + ext_ch_gt_drpdo(12) <= \\; + ext_ch_gt_drpdo(11) <= \\; + ext_ch_gt_drpdo(10) <= \\; + ext_ch_gt_drpdo(9) <= \\; + ext_ch_gt_drpdo(8) <= \\; + ext_ch_gt_drpdo(7) <= \\; + ext_ch_gt_drpdo(6) <= \\; + ext_ch_gt_drpdo(5) <= \\; + ext_ch_gt_drpdo(4) <= \\; + ext_ch_gt_drpdo(3) <= \\; + ext_ch_gt_drpdo(2) <= \\; + ext_ch_gt_drpdo(1) <= \\; + ext_ch_gt_drpdo(0) <= \\; + ext_ch_gt_drprdy(3) <= \\; + ext_ch_gt_drprdy(2) <= \\; + ext_ch_gt_drprdy(1) <= \\; + ext_ch_gt_drprdy(0) <= \\; + gt_ch_drp_rdy(3) <= \\; + gt_ch_drp_rdy(2) <= \\; + gt_ch_drp_rdy(1) <= \\; + gt_ch_drp_rdy(0) <= \\; + icap_o(31) <= \\; + icap_o(30) <= \\; + icap_o(29) <= \\; + icap_o(28) <= \\; + icap_o(27) <= \\; + icap_o(26) <= \\; + icap_o(25) <= \\; + icap_o(24) <= \\; + icap_o(23) <= \\; + icap_o(22) <= \\; + icap_o(21) <= \\; + icap_o(20) <= \\; + icap_o(19) <= \\; + icap_o(18) <= \\; + icap_o(17) <= \\; + icap_o(16) <= \\; + icap_o(15) <= \\; + icap_o(14) <= \\; + icap_o(13) <= \\; + icap_o(12) <= \\; + icap_o(11) <= \\; + icap_o(10) <= \\; + icap_o(9) <= \\; + icap_o(8) <= \\; + icap_o(7) <= \\; + icap_o(6) <= \\; + icap_o(5) <= \\; + icap_o(4) <= \\; + icap_o(3) <= \\; + icap_o(2) <= \\; + icap_o(1) <= \\; + icap_o(0) <= \\; + int_dclk_out <= \\; + int_mmcm_lock_out <= \\; + int_oobclk_out <= \\; + int_pclk_out_slave <= \\; + int_pipe_rxusrclk_out <= \\; + int_qplllock_out(1) <= \\; + int_qplllock_out(0) <= \\; + int_qplloutclk_out(1) <= \\; + int_qplloutclk_out(0) <= \\; + int_qplloutrefclk_out(1) <= \\; + int_qplloutrefclk_out(0) <= \\; + int_rxoutclk_out(3) <= \\; + int_rxoutclk_out(2) <= \\; + int_rxoutclk_out(1) <= \\; + int_rxoutclk_out(0) <= \\; + int_userclk1_out <= \\; + int_userclk2_out <= \\; + m_axis_rx_tkeep(7) <= \^m_axis_rx_tkeep\(6); + m_axis_rx_tkeep(6) <= \^m_axis_rx_tkeep\(6); + m_axis_rx_tkeep(5) <= \^m_axis_rx_tkeep\(6); + m_axis_rx_tkeep(4) <= \^m_axis_rx_tkeep\(6); + m_axis_rx_tkeep(3) <= \\; + m_axis_rx_tkeep(2) <= \\; + m_axis_rx_tkeep(1) <= \\; + m_axis_rx_tkeep(0) <= \\; + m_axis_rx_tuser(21) <= \^m_axis_rx_tuser\(21); + m_axis_rx_tuser(20) <= \\; + m_axis_rx_tuser(19) <= \^m_axis_rx_tuser\(19); + m_axis_rx_tuser(18) <= \^m_axis_rx_tuser\(17); + m_axis_rx_tuser(17) <= \^m_axis_rx_tuser\(17); + m_axis_rx_tuser(16) <= \\; + m_axis_rx_tuser(15) <= \\; + m_axis_rx_tuser(14) <= \^m_axis_rx_tuser\(14); + m_axis_rx_tuser(13) <= \\; + m_axis_rx_tuser(12) <= \\; + m_axis_rx_tuser(11) <= \\; + m_axis_rx_tuser(10) <= \\; + m_axis_rx_tuser(9) <= \\; + m_axis_rx_tuser(8 downto 0) <= \^m_axis_rx_tuser\(8 downto 0); + pipe_cpll_lock(3) <= \\; + pipe_cpll_lock(2) <= \\; + pipe_cpll_lock(1) <= \\; + pipe_cpll_lock(0) <= \\; + pipe_debug(31) <= \\; + pipe_debug(30) <= \\; + pipe_debug(29) <= \\; + pipe_debug(28) <= \\; + pipe_debug(27) <= \\; + pipe_debug(26) <= \\; + pipe_debug(25) <= \\; + pipe_debug(24) <= \\; + pipe_debug(23) <= \\; + pipe_debug(22) <= \\; + pipe_debug(21) <= \\; + pipe_debug(20) <= \\; + pipe_debug(19) <= \\; + pipe_debug(18) <= \\; + pipe_debug(17) <= \\; + pipe_debug(16) <= \\; + pipe_debug(15) <= \\; + pipe_debug(14) <= \\; + pipe_debug(13) <= \\; + pipe_debug(12) <= \\; + pipe_debug(11) <= \\; + pipe_debug(10) <= \\; + pipe_debug(9) <= \\; + pipe_debug(8) <= \\; + pipe_debug(7) <= \\; + pipe_debug(6) <= \\; + pipe_debug(5) <= \\; + pipe_debug(4) <= \\; + pipe_debug(3) <= \\; + pipe_debug(2) <= \\; + pipe_debug(1) <= \\; + pipe_debug(0) <= \\; + pipe_debug_0(3) <= \\; + pipe_debug_0(2) <= \\; + pipe_debug_0(1) <= \\; + pipe_debug_0(0) <= \\; + pipe_debug_1(3) <= \\; + pipe_debug_1(2) <= \\; + pipe_debug_1(1) <= \\; + pipe_debug_1(0) <= \\; + pipe_debug_2(3) <= \\; + pipe_debug_2(2) <= \\; + pipe_debug_2(1) <= \\; + pipe_debug_2(0) <= \\; + pipe_debug_3(3) <= \\; + pipe_debug_3(2) <= \\; + pipe_debug_3(1) <= \\; + pipe_debug_3(0) <= \\; + pipe_debug_4(3) <= \\; + pipe_debug_4(2) <= \\; + pipe_debug_4(1) <= \\; + pipe_debug_4(0) <= \\; + pipe_debug_5(3) <= \\; + pipe_debug_5(2) <= \\; + pipe_debug_5(1) <= \\; + pipe_debug_5(0) <= \\; + pipe_debug_6(3) <= \\; + pipe_debug_6(2) <= \\; + pipe_debug_6(1) <= \\; + pipe_debug_6(0) <= \\; + pipe_debug_7(3) <= \\; + pipe_debug_7(2) <= \\; + pipe_debug_7(1) <= \\; + pipe_debug_7(0) <= \\; + pipe_debug_8(3) <= \\; + pipe_debug_8(2) <= \\; + pipe_debug_8(1) <= \\; + pipe_debug_8(0) <= \\; + pipe_debug_9(3) <= \\; + pipe_debug_9(2) <= \\; + pipe_debug_9(1) <= \\; + pipe_debug_9(0) <= \\; + pipe_dmonitorout(59) <= \\; + pipe_dmonitorout(58) <= \\; + pipe_dmonitorout(57) <= \\; + pipe_dmonitorout(56) <= \\; + pipe_dmonitorout(55) <= \\; + pipe_dmonitorout(54) <= \\; + pipe_dmonitorout(53) <= \\; + pipe_dmonitorout(52) <= \\; + pipe_dmonitorout(51) <= \\; + pipe_dmonitorout(50) <= \\; + pipe_dmonitorout(49) <= \\; + pipe_dmonitorout(48) <= \\; + pipe_dmonitorout(47) <= \\; + pipe_dmonitorout(46) <= \\; + pipe_dmonitorout(45) <= \\; + pipe_dmonitorout(44) <= \\; + pipe_dmonitorout(43) <= \\; + pipe_dmonitorout(42) <= \\; + pipe_dmonitorout(41) <= \\; + pipe_dmonitorout(40) <= \\; + pipe_dmonitorout(39) <= \\; + pipe_dmonitorout(38) <= \\; + pipe_dmonitorout(37) <= \\; + pipe_dmonitorout(36) <= \\; + pipe_dmonitorout(35) <= \\; + pipe_dmonitorout(34) <= \\; + pipe_dmonitorout(33) <= \\; + pipe_dmonitorout(32) <= \\; + pipe_dmonitorout(31) <= \\; + pipe_dmonitorout(30) <= \\; + pipe_dmonitorout(29) <= \\; + pipe_dmonitorout(28) <= \\; + pipe_dmonitorout(27) <= \\; + pipe_dmonitorout(26) <= \\; + pipe_dmonitorout(25) <= \\; + pipe_dmonitorout(24) <= \\; + pipe_dmonitorout(23) <= \\; + pipe_dmonitorout(22) <= \\; + pipe_dmonitorout(21) <= \\; + pipe_dmonitorout(20) <= \\; + pipe_dmonitorout(19) <= \\; + pipe_dmonitorout(18) <= \\; + pipe_dmonitorout(17) <= \\; + pipe_dmonitorout(16) <= \\; + pipe_dmonitorout(15) <= \\; + pipe_dmonitorout(14) <= \\; + pipe_dmonitorout(13) <= \\; + pipe_dmonitorout(12) <= \\; + pipe_dmonitorout(11) <= \\; + pipe_dmonitorout(10) <= \\; + pipe_dmonitorout(9) <= \\; + pipe_dmonitorout(8) <= \\; + pipe_dmonitorout(7) <= \\; + pipe_dmonitorout(6) <= \\; + pipe_dmonitorout(5) <= \\; + pipe_dmonitorout(4) <= \\; + pipe_dmonitorout(3) <= \\; + pipe_dmonitorout(2) <= \\; + pipe_dmonitorout(1) <= \\; + pipe_dmonitorout(0) <= \\; + pipe_drp_fsm(27) <= \\; + pipe_drp_fsm(26) <= \\; + pipe_drp_fsm(25) <= \\; + pipe_drp_fsm(24) <= \\; + pipe_drp_fsm(23) <= \\; + pipe_drp_fsm(22) <= \\; + pipe_drp_fsm(21) <= \\; + pipe_drp_fsm(20) <= \\; + pipe_drp_fsm(19) <= \\; + pipe_drp_fsm(18) <= \\; + pipe_drp_fsm(17) <= \\; + pipe_drp_fsm(16) <= \\; + pipe_drp_fsm(15) <= \\; + pipe_drp_fsm(14) <= \\; + pipe_drp_fsm(13) <= \\; + pipe_drp_fsm(12) <= \\; + pipe_drp_fsm(11) <= \\; + pipe_drp_fsm(10) <= \\; + pipe_drp_fsm(9) <= \\; + pipe_drp_fsm(8) <= \\; + pipe_drp_fsm(7) <= \\; + pipe_drp_fsm(6) <= \\; + pipe_drp_fsm(5) <= \\; + pipe_drp_fsm(4) <= \\; + pipe_drp_fsm(3) <= \\; + pipe_drp_fsm(2) <= \\; + pipe_drp_fsm(1) <= \\; + pipe_drp_fsm(0) <= \\; + pipe_eyescandataerror(3) <= \\; + pipe_eyescandataerror(2) <= \\; + pipe_eyescandataerror(1) <= \\; + pipe_eyescandataerror(0) <= \\; + pipe_qpll_lock(0) <= \\; + pipe_qrst_fsm(11) <= \\; + pipe_qrst_fsm(10) <= \\; + pipe_qrst_fsm(9) <= \\; + pipe_qrst_fsm(8) <= \\; + pipe_qrst_fsm(7) <= \\; + pipe_qrst_fsm(6) <= \\; + pipe_qrst_fsm(5) <= \\; + pipe_qrst_fsm(4) <= \\; + pipe_qrst_fsm(3) <= \\; + pipe_qrst_fsm(2) <= \\; + pipe_qrst_fsm(1) <= \\; + pipe_qrst_fsm(0) <= \\; + pipe_qrst_idle <= \\; + pipe_rate_fsm(19) <= \\; + pipe_rate_fsm(18) <= \\; + pipe_rate_fsm(17) <= \\; + pipe_rate_fsm(16) <= \\; + pipe_rate_fsm(15) <= \\; + pipe_rate_fsm(14) <= \\; + pipe_rate_fsm(13) <= \\; + pipe_rate_fsm(12) <= \\; + pipe_rate_fsm(11) <= \\; + pipe_rate_fsm(10) <= \\; + pipe_rate_fsm(9) <= \\; + pipe_rate_fsm(8) <= \\; + pipe_rate_fsm(7) <= \\; + pipe_rate_fsm(6) <= \\; + pipe_rate_fsm(5) <= \\; + pipe_rate_fsm(4) <= \\; + pipe_rate_fsm(3) <= \\; + pipe_rate_fsm(2) <= \\; + pipe_rate_fsm(1) <= \\; + pipe_rate_fsm(0) <= \\; + pipe_rate_idle <= \\; + pipe_rst_fsm(4) <= \\; + pipe_rst_fsm(3) <= \\; + pipe_rst_fsm(2) <= \\; + pipe_rst_fsm(1) <= \\; + pipe_rst_fsm(0) <= \\; + pipe_rst_idle <= \\; + pipe_rxbufstatus(11) <= \\; + pipe_rxbufstatus(10) <= \\; + pipe_rxbufstatus(9) <= \\; + pipe_rxbufstatus(8) <= \\; + pipe_rxbufstatus(7) <= \\; + pipe_rxbufstatus(6) <= \\; + pipe_rxbufstatus(5) <= \\; + pipe_rxbufstatus(4) <= \\; + pipe_rxbufstatus(3) <= \\; + pipe_rxbufstatus(2) <= \\; + pipe_rxbufstatus(1) <= \\; + pipe_rxbufstatus(0) <= \\; + pipe_rxcommadet(3) <= \\; + pipe_rxcommadet(2) <= \\; + pipe_rxcommadet(1) <= \\; + pipe_rxcommadet(0) <= \\; + pipe_rxdisperr(31) <= \\; + pipe_rxdisperr(30) <= \\; + pipe_rxdisperr(29) <= \\; + pipe_rxdisperr(28) <= \\; + pipe_rxdisperr(27) <= \\; + pipe_rxdisperr(26) <= \\; + pipe_rxdisperr(25) <= \\; + pipe_rxdisperr(24) <= \\; + pipe_rxdisperr(23) <= \\; + pipe_rxdisperr(22) <= \\; + pipe_rxdisperr(21) <= \\; + pipe_rxdisperr(20) <= \\; + pipe_rxdisperr(19) <= \\; + pipe_rxdisperr(18) <= \\; + pipe_rxdisperr(17) <= \\; + pipe_rxdisperr(16) <= \\; + pipe_rxdisperr(15) <= \\; + pipe_rxdisperr(14) <= \\; + pipe_rxdisperr(13) <= \\; + pipe_rxdisperr(12) <= \\; + pipe_rxdisperr(11) <= \\; + pipe_rxdisperr(10) <= \\; + pipe_rxdisperr(9) <= \\; + pipe_rxdisperr(8) <= \\; + pipe_rxdisperr(7) <= \\; + pipe_rxdisperr(6) <= \\; + pipe_rxdisperr(5) <= \\; + pipe_rxdisperr(4) <= \\; + pipe_rxdisperr(3) <= \\; + pipe_rxdisperr(2) <= \\; + pipe_rxdisperr(1) <= \\; + pipe_rxdisperr(0) <= \\; + pipe_rxdlysresetdone(3) <= \\; + pipe_rxdlysresetdone(2) <= \\; + pipe_rxdlysresetdone(1) <= \\; + pipe_rxdlysresetdone(0) <= \\; + pipe_rxnotintable(31) <= \\; + pipe_rxnotintable(30) <= \\; + pipe_rxnotintable(29) <= \\; + pipe_rxnotintable(28) <= \\; + pipe_rxnotintable(27) <= \\; + pipe_rxnotintable(26) <= \\; + pipe_rxnotintable(25) <= \\; + pipe_rxnotintable(24) <= \\; + pipe_rxnotintable(23) <= \\; + pipe_rxnotintable(22) <= \\; + pipe_rxnotintable(21) <= \\; + pipe_rxnotintable(20) <= \\; + pipe_rxnotintable(19) <= \\; + pipe_rxnotintable(18) <= \\; + pipe_rxnotintable(17) <= \\; + pipe_rxnotintable(16) <= \\; + pipe_rxnotintable(15) <= \\; + pipe_rxnotintable(14) <= \\; + pipe_rxnotintable(13) <= \\; + pipe_rxnotintable(12) <= \\; + pipe_rxnotintable(11) <= \\; + pipe_rxnotintable(10) <= \\; + pipe_rxnotintable(9) <= \\; + pipe_rxnotintable(8) <= \\; + pipe_rxnotintable(7) <= \\; + pipe_rxnotintable(6) <= \\; + pipe_rxnotintable(5) <= \\; + pipe_rxnotintable(4) <= \\; + pipe_rxnotintable(3) <= \\; + pipe_rxnotintable(2) <= \\; + pipe_rxnotintable(1) <= \\; + pipe_rxnotintable(0) <= \\; + pipe_rxphaligndone(3) <= \\; + pipe_rxphaligndone(2) <= \\; + pipe_rxphaligndone(1) <= \\; + pipe_rxphaligndone(0) <= \\; + pipe_rxpmaresetdone(3) <= \\; + pipe_rxpmaresetdone(2) <= \\; + pipe_rxpmaresetdone(1) <= \\; + pipe_rxpmaresetdone(0) <= \\; + pipe_rxprbserr(3) <= \\; + pipe_rxprbserr(2) <= \\; + pipe_rxprbserr(1) <= \\; + pipe_rxprbserr(0) <= \\; + pipe_rxstatus(11) <= \\; + pipe_rxstatus(10) <= \\; + pipe_rxstatus(9) <= \\; + pipe_rxstatus(8) <= \\; + pipe_rxstatus(7) <= \\; + pipe_rxstatus(6) <= \\; + pipe_rxstatus(5) <= \\; + pipe_rxstatus(4) <= \\; + pipe_rxstatus(3) <= \\; + pipe_rxstatus(2) <= \\; + pipe_rxstatus(1) <= \\; + pipe_rxstatus(0) <= \\; + pipe_rxsyncdone(3) <= \\; + pipe_rxsyncdone(2) <= \\; + pipe_rxsyncdone(1) <= \\; + pipe_rxsyncdone(0) <= \\; + pipe_sync_fsm_rx(27) <= \\; + pipe_sync_fsm_rx(26) <= \\; + pipe_sync_fsm_rx(25) <= \\; + pipe_sync_fsm_rx(24) <= \\; + pipe_sync_fsm_rx(23) <= \\; + pipe_sync_fsm_rx(22) <= \\; + pipe_sync_fsm_rx(21) <= \\; + pipe_sync_fsm_rx(20) <= \\; + pipe_sync_fsm_rx(19) <= \\; + pipe_sync_fsm_rx(18) <= \\; + pipe_sync_fsm_rx(17) <= \\; + pipe_sync_fsm_rx(16) <= \\; + pipe_sync_fsm_rx(15) <= \\; + pipe_sync_fsm_rx(14) <= \\; + pipe_sync_fsm_rx(13) <= \\; + pipe_sync_fsm_rx(12) <= \\; + pipe_sync_fsm_rx(11) <= \\; + pipe_sync_fsm_rx(10) <= \\; + pipe_sync_fsm_rx(9) <= \\; + pipe_sync_fsm_rx(8) <= \\; + pipe_sync_fsm_rx(7) <= \\; + pipe_sync_fsm_rx(6) <= \\; + pipe_sync_fsm_rx(5) <= \\; + pipe_sync_fsm_rx(4) <= \\; + pipe_sync_fsm_rx(3) <= \\; + pipe_sync_fsm_rx(2) <= \\; + pipe_sync_fsm_rx(1) <= \\; + pipe_sync_fsm_rx(0) <= \\; + pipe_sync_fsm_tx(23) <= \\; + pipe_sync_fsm_tx(22) <= \\; + pipe_sync_fsm_tx(21) <= \\; + pipe_sync_fsm_tx(20) <= \\; + pipe_sync_fsm_tx(19) <= \\; + pipe_sync_fsm_tx(18) <= \\; + pipe_sync_fsm_tx(17) <= \\; + pipe_sync_fsm_tx(16) <= \\; + pipe_sync_fsm_tx(15) <= \\; + pipe_sync_fsm_tx(14) <= \\; + pipe_sync_fsm_tx(13) <= \\; + pipe_sync_fsm_tx(12) <= \\; + pipe_sync_fsm_tx(11) <= \\; + pipe_sync_fsm_tx(10) <= \\; + pipe_sync_fsm_tx(9) <= \\; + pipe_sync_fsm_tx(8) <= \\; + pipe_sync_fsm_tx(7) <= \\; + pipe_sync_fsm_tx(6) <= \\; + pipe_sync_fsm_tx(5) <= \\; + pipe_sync_fsm_tx(4) <= \\; + pipe_sync_fsm_tx(3) <= \\; + pipe_sync_fsm_tx(2) <= \\; + pipe_sync_fsm_tx(1) <= \\; + pipe_sync_fsm_tx(0) <= \\; + pipe_tx_0_sigs(24) <= \\; + pipe_tx_0_sigs(23) <= \\; + pipe_tx_0_sigs(22) <= \\; + pipe_tx_0_sigs(21) <= \\; + pipe_tx_0_sigs(20) <= \\; + pipe_tx_0_sigs(19) <= \\; + pipe_tx_0_sigs(18) <= \\; + pipe_tx_0_sigs(17) <= \\; + pipe_tx_0_sigs(16) <= \\; + pipe_tx_0_sigs(15) <= \\; + pipe_tx_0_sigs(14) <= \\; + pipe_tx_0_sigs(13) <= \\; + pipe_tx_0_sigs(12) <= \\; + pipe_tx_0_sigs(11) <= \\; + pipe_tx_0_sigs(10) <= \\; + pipe_tx_0_sigs(9) <= \\; + pipe_tx_0_sigs(8) <= \\; + pipe_tx_0_sigs(7) <= \\; + pipe_tx_0_sigs(6) <= \\; + pipe_tx_0_sigs(5) <= \\; + pipe_tx_0_sigs(4) <= \\; + pipe_tx_0_sigs(3) <= \\; + pipe_tx_0_sigs(2) <= \\; + pipe_tx_0_sigs(1) <= \\; + pipe_tx_0_sigs(0) <= \\; + pipe_tx_1_sigs(24) <= \\; + pipe_tx_1_sigs(23) <= \\; + pipe_tx_1_sigs(22) <= \\; + pipe_tx_1_sigs(21) <= \\; + pipe_tx_1_sigs(20) <= \\; + pipe_tx_1_sigs(19) <= \\; + pipe_tx_1_sigs(18) <= \\; + pipe_tx_1_sigs(17) <= \\; + pipe_tx_1_sigs(16) <= \\; + pipe_tx_1_sigs(15) <= \\; + pipe_tx_1_sigs(14) <= \\; + pipe_tx_1_sigs(13) <= \\; + pipe_tx_1_sigs(12) <= \\; + pipe_tx_1_sigs(11) <= \\; + pipe_tx_1_sigs(10) <= \\; + pipe_tx_1_sigs(9) <= \\; + pipe_tx_1_sigs(8) <= \\; + pipe_tx_1_sigs(7) <= \\; + pipe_tx_1_sigs(6) <= \\; + pipe_tx_1_sigs(5) <= \\; + pipe_tx_1_sigs(4) <= \\; + pipe_tx_1_sigs(3) <= \\; + pipe_tx_1_sigs(2) <= \\; + pipe_tx_1_sigs(1) <= \\; + pipe_tx_1_sigs(0) <= \\; + pipe_tx_2_sigs(24) <= \\; + pipe_tx_2_sigs(23) <= \\; + pipe_tx_2_sigs(22) <= \\; + pipe_tx_2_sigs(21) <= \\; + pipe_tx_2_sigs(20) <= \\; + pipe_tx_2_sigs(19) <= \\; + pipe_tx_2_sigs(18) <= \\; + pipe_tx_2_sigs(17) <= \\; + pipe_tx_2_sigs(16) <= \\; + pipe_tx_2_sigs(15) <= \\; + pipe_tx_2_sigs(14) <= \\; + pipe_tx_2_sigs(13) <= \\; + pipe_tx_2_sigs(12) <= \\; + pipe_tx_2_sigs(11) <= \\; + pipe_tx_2_sigs(10) <= \\; + pipe_tx_2_sigs(9) <= \\; + pipe_tx_2_sigs(8) <= \\; + pipe_tx_2_sigs(7) <= \\; + pipe_tx_2_sigs(6) <= \\; + pipe_tx_2_sigs(5) <= \\; + pipe_tx_2_sigs(4) <= \\; + pipe_tx_2_sigs(3) <= \\; + pipe_tx_2_sigs(2) <= \\; + pipe_tx_2_sigs(1) <= \\; + pipe_tx_2_sigs(0) <= \\; + pipe_tx_3_sigs(24) <= \\; + pipe_tx_3_sigs(23) <= \\; + pipe_tx_3_sigs(22) <= \\; + pipe_tx_3_sigs(21) <= \\; + pipe_tx_3_sigs(20) <= \\; + pipe_tx_3_sigs(19) <= \\; + pipe_tx_3_sigs(18) <= \\; + pipe_tx_3_sigs(17) <= \\; + pipe_tx_3_sigs(16) <= \\; + pipe_tx_3_sigs(15) <= \\; + pipe_tx_3_sigs(14) <= \\; + pipe_tx_3_sigs(13) <= \\; + pipe_tx_3_sigs(12) <= \\; + pipe_tx_3_sigs(11) <= \\; + pipe_tx_3_sigs(10) <= \\; + pipe_tx_3_sigs(9) <= \\; + pipe_tx_3_sigs(8) <= \\; + pipe_tx_3_sigs(7) <= \\; + pipe_tx_3_sigs(6) <= \\; + pipe_tx_3_sigs(5) <= \\; + pipe_tx_3_sigs(4) <= \\; + pipe_tx_3_sigs(3) <= \\; + pipe_tx_3_sigs(2) <= \\; + pipe_tx_3_sigs(1) <= \\; + pipe_tx_3_sigs(0) <= \\; + pipe_tx_4_sigs(24) <= \\; + pipe_tx_4_sigs(23) <= \\; + pipe_tx_4_sigs(22) <= \\; + pipe_tx_4_sigs(21) <= \\; + pipe_tx_4_sigs(20) <= \\; + pipe_tx_4_sigs(19) <= \\; + pipe_tx_4_sigs(18) <= \\; + pipe_tx_4_sigs(17) <= \\; + pipe_tx_4_sigs(16) <= \\; + pipe_tx_4_sigs(15) <= \\; + pipe_tx_4_sigs(14) <= \\; + pipe_tx_4_sigs(13) <= \\; + pipe_tx_4_sigs(12) <= \\; + pipe_tx_4_sigs(11) <= \\; + pipe_tx_4_sigs(10) <= \\; + pipe_tx_4_sigs(9) <= \\; + pipe_tx_4_sigs(8) <= \\; + pipe_tx_4_sigs(7) <= \\; + pipe_tx_4_sigs(6) <= \\; + pipe_tx_4_sigs(5) <= \\; + pipe_tx_4_sigs(4) <= \\; + pipe_tx_4_sigs(3) <= \\; + pipe_tx_4_sigs(2) <= \\; + pipe_tx_4_sigs(1) <= \\; + pipe_tx_4_sigs(0) <= \\; + pipe_tx_5_sigs(24) <= \\; + pipe_tx_5_sigs(23) <= \\; + pipe_tx_5_sigs(22) <= \\; + pipe_tx_5_sigs(21) <= \\; + pipe_tx_5_sigs(20) <= \\; + pipe_tx_5_sigs(19) <= \\; + pipe_tx_5_sigs(18) <= \\; + pipe_tx_5_sigs(17) <= \\; + pipe_tx_5_sigs(16) <= \\; + pipe_tx_5_sigs(15) <= \\; + pipe_tx_5_sigs(14) <= \\; + pipe_tx_5_sigs(13) <= \\; + pipe_tx_5_sigs(12) <= \\; + pipe_tx_5_sigs(11) <= \\; + pipe_tx_5_sigs(10) <= \\; + pipe_tx_5_sigs(9) <= \\; + pipe_tx_5_sigs(8) <= \\; + pipe_tx_5_sigs(7) <= \\; + pipe_tx_5_sigs(6) <= \\; + pipe_tx_5_sigs(5) <= \\; + pipe_tx_5_sigs(4) <= \\; + pipe_tx_5_sigs(3) <= \\; + pipe_tx_5_sigs(2) <= \\; + pipe_tx_5_sigs(1) <= \\; + pipe_tx_5_sigs(0) <= \\; + pipe_tx_6_sigs(24) <= \\; + pipe_tx_6_sigs(23) <= \\; + pipe_tx_6_sigs(22) <= \\; + pipe_tx_6_sigs(21) <= \\; + pipe_tx_6_sigs(20) <= \\; + pipe_tx_6_sigs(19) <= \\; + pipe_tx_6_sigs(18) <= \\; + pipe_tx_6_sigs(17) <= \\; + pipe_tx_6_sigs(16) <= \\; + pipe_tx_6_sigs(15) <= \\; + pipe_tx_6_sigs(14) <= \\; + pipe_tx_6_sigs(13) <= \\; + pipe_tx_6_sigs(12) <= \\; + pipe_tx_6_sigs(11) <= \\; + pipe_tx_6_sigs(10) <= \\; + pipe_tx_6_sigs(9) <= \\; + pipe_tx_6_sigs(8) <= \\; + pipe_tx_6_sigs(7) <= \\; + pipe_tx_6_sigs(6) <= \\; + pipe_tx_6_sigs(5) <= \\; + pipe_tx_6_sigs(4) <= \\; + pipe_tx_6_sigs(3) <= \\; + pipe_tx_6_sigs(2) <= \\; + pipe_tx_6_sigs(1) <= \\; + pipe_tx_6_sigs(0) <= \\; + pipe_tx_7_sigs(24) <= \\; + pipe_tx_7_sigs(23) <= \\; + pipe_tx_7_sigs(22) <= \\; + pipe_tx_7_sigs(21) <= \\; + pipe_tx_7_sigs(20) <= \\; + pipe_tx_7_sigs(19) <= \\; + pipe_tx_7_sigs(18) <= \\; + pipe_tx_7_sigs(17) <= \\; + pipe_tx_7_sigs(16) <= \\; + pipe_tx_7_sigs(15) <= \\; + pipe_tx_7_sigs(14) <= \\; + pipe_tx_7_sigs(13) <= \\; + pipe_tx_7_sigs(12) <= \\; + pipe_tx_7_sigs(11) <= \\; + pipe_tx_7_sigs(10) <= \\; + pipe_tx_7_sigs(9) <= \\; + pipe_tx_7_sigs(8) <= \\; + pipe_tx_7_sigs(7) <= \\; + pipe_tx_7_sigs(6) <= \\; + pipe_tx_7_sigs(5) <= \\; + pipe_tx_7_sigs(4) <= \\; + pipe_tx_7_sigs(3) <= \\; + pipe_tx_7_sigs(2) <= \\; + pipe_tx_7_sigs(1) <= \\; + pipe_tx_7_sigs(0) <= \\; + pipe_txdlysresetdone(3) <= \\; + pipe_txdlysresetdone(2) <= \\; + pipe_txdlysresetdone(1) <= \\; + pipe_txdlysresetdone(0) <= \\; + pipe_txphaligndone(3) <= \\; + pipe_txphaligndone(2) <= \\; + pipe_txphaligndone(1) <= \\; + pipe_txphaligndone(0) <= \\; + pipe_txphinitdone(3) <= \\; + pipe_txphinitdone(2) <= \\; + pipe_txphinitdone(1) <= \\; + pipe_txphinitdone(0) <= \\; + qpll_drp_clk <= \\; + qpll_drp_gen3 <= \\; + qpll_drp_ovrd <= \\; + qpll_drp_rst_n <= \\; + qpll_drp_start <= \\; + qpll_qplld <= \\; + qpll_qpllreset(1) <= \\; + qpll_qpllreset(0) <= \\; + startup_cfgclk <= \\; + startup_cfgmclk <= \\; + startup_eos <= \\; + startup_preq <= \\; + user_app_rdy <= \\; + user_clk_out <= \^pipe_userclk2_in\; +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +inst: entity work.pcie_7x_0_pcie_7x_0_core_top + port map ( + cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en, + cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en, + cfg_aer_interrupt_msgnum(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0), + cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received, + cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en, + cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received, + cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en, + cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received, + cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en, + cfg_bridge_serr_en => cfg_bridge_serr_en, + cfg_bus_number(7 downto 0) => cfg_bus_number(7 downto 0), + cfg_command(4) => \^cfg_command\(10), + cfg_command(3) => \^cfg_command\(8), + cfg_command(2 downto 0) => \^cfg_command\(2 downto 0), + cfg_dcommand(14 downto 0) => \^cfg_dcommand\(14 downto 0), + cfg_dcommand2(11 downto 0) => \^cfg_dcommand2\(11 downto 0), + cfg_device_number(4 downto 0) => cfg_device_number(4 downto 0), + cfg_ds_bus_number(7 downto 0) => cfg_ds_bus_number(7 downto 0), + cfg_ds_device_number(4 downto 0) => cfg_ds_device_number(4 downto 0), + cfg_ds_function_number(2 downto 0) => cfg_ds_function_number(2 downto 0), + cfg_dsn(63 downto 0) => cfg_dsn(63 downto 0), + cfg_dstatus(3 downto 0) => \^cfg_dstatus\(3 downto 0), + cfg_err_aer_headerlog(127 downto 0) => cfg_err_aer_headerlog(127 downto 0), + cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set, + cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked, + cfg_err_cor => cfg_err_cor, + cfg_err_cpl_abort => cfg_err_cpl_abort, + cfg_err_cpl_rdy => cfg_err_cpl_rdy, + cfg_err_cpl_timeout => cfg_err_cpl_timeout, + cfg_err_cpl_unexpect => cfg_err_cpl_unexpect, + cfg_err_ecrc => cfg_err_ecrc, + cfg_err_internal_cor => cfg_err_internal_cor, + cfg_err_internal_uncor => cfg_err_internal_uncor, + cfg_err_locked => cfg_err_locked, + cfg_err_malformed => cfg_err_malformed, + cfg_err_mc_blocked => cfg_err_mc_blocked, + cfg_err_norecovery => cfg_err_norecovery, + cfg_err_poisoned => cfg_err_poisoned, + cfg_err_posted => cfg_err_posted, + cfg_err_tlp_cpl_header(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0), + cfg_err_ur => cfg_err_ur, + cfg_function_number(2 downto 0) => cfg_function_number(2 downto 0), + cfg_interrupt => cfg_interrupt, + cfg_interrupt_assert => cfg_interrupt_assert, + cfg_interrupt_di(7 downto 0) => cfg_interrupt_di(7 downto 0), + cfg_interrupt_do(7 downto 0) => cfg_interrupt_do(7 downto 0), + cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0), + cfg_interrupt_msienable => cfg_interrupt_msienable, + cfg_interrupt_msixenable => cfg_interrupt_msixenable, + cfg_interrupt_msixfm => cfg_interrupt_msixfm, + cfg_interrupt_rdy => cfg_interrupt_rdy, + cfg_interrupt_stat => cfg_interrupt_stat, + cfg_lcommand(10 downto 2) => \^cfg_lcommand\(11 downto 3), + cfg_lcommand(1 downto 0) => \^cfg_lcommand\(1 downto 0), + cfg_lstatus(9 downto 7) => \^cfg_lstatus\(15 downto 13), + cfg_lstatus(6) => \^cfg_lstatus\(11), + cfg_lstatus(5 downto 2) => \^cfg_lstatus\(7 downto 4), + cfg_lstatus(1 downto 0) => \^cfg_lstatus\(1 downto 0), + cfg_mgmt_byte_en(3 downto 0) => cfg_mgmt_byte_en(3 downto 0), + cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0), + cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0), + cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0), + cfg_mgmt_rd_en => cfg_mgmt_rd_en, + cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done, + cfg_mgmt_wr_en => cfg_mgmt_wr_en, + cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly, + cfg_mgmt_wr_rw1c_as_rw => cfg_mgmt_wr_rw1c_as_rw, + cfg_msg_data(15 downto 0) => cfg_msg_data(15 downto 0), + cfg_msg_received => cfg_msg_received, + cfg_msg_received_assert_int_a => cfg_msg_received_assert_int_a, + cfg_msg_received_assert_int_b => cfg_msg_received_assert_int_b, + cfg_msg_received_assert_int_c => cfg_msg_received_assert_int_c, + cfg_msg_received_assert_int_d => cfg_msg_received_assert_int_d, + cfg_msg_received_deassert_int_a => cfg_msg_received_deassert_int_a, + cfg_msg_received_deassert_int_b => cfg_msg_received_deassert_int_b, + cfg_msg_received_deassert_int_c => cfg_msg_received_deassert_int_c, + cfg_msg_received_deassert_int_d => cfg_msg_received_deassert_int_d, + cfg_msg_received_err_cor => cfg_msg_received_err_cor, + cfg_msg_received_err_fatal => cfg_msg_received_err_fatal, + cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal, + cfg_msg_received_pm_as_nak => cfg_msg_received_pm_as_nak, + cfg_msg_received_pm_pme => cfg_msg_received_pm_pme, + cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack, + cfg_msg_received_setslotpowerlimit => cfg_msg_received_setslotpowerlimit, + cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0), + cfg_pciecap_interrupt_msgnum(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0), + cfg_pm_force_state(1 downto 0) => cfg_pm_force_state(1 downto 0), + cfg_pm_force_state_en => cfg_pm_force_state_en, + cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s, + cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1, + cfg_pm_wake => cfg_pm_wake, + cfg_pmcsr_pme_en => cfg_pmcsr_pme_en, + cfg_pmcsr_pme_status => cfg_pmcsr_pme_status, + cfg_pmcsr_powerstate(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0), + cfg_received_func_lvl_rst => cfg_received_func_lvl_rst, + cfg_root_control_pme_int_en => cfg_root_control_pme_int_en, + cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en, + cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en, + cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en, + cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse, + cfg_to_turnoff => cfg_to_turnoff, + cfg_trn_pending => \^cfg_trn_pending\, + cfg_turnoff_ok => cfg_turnoff_ok, + cfg_vc_tcvc_map(6 downto 0) => cfg_vc_tcvc_map(6 downto 0), + fc_cpld(11 downto 0) => fc_cpld(11 downto 0), + fc_cplh(7 downto 0) => fc_cplh(7 downto 0), + fc_npd(11 downto 0) => fc_npd(11 downto 0), + fc_nph(7 downto 0) => fc_nph(7 downto 0), + fc_pd(11 downto 0) => fc_pd(11 downto 0), + fc_ph(7 downto 0) => fc_ph(7 downto 0), + fc_sel(2 downto 0) => fc_sel(2 downto 0), + gen3_reg => pipe_gen3_out, + m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0), + m_axis_rx_tkeep(0) => \^m_axis_rx_tkeep\(6), + m_axis_rx_tlast => m_axis_rx_tlast, + m_axis_rx_tready => m_axis_rx_tready, + m_axis_rx_tuser(12) => \^m_axis_rx_tuser\(21), + m_axis_rx_tuser(11) => \^m_axis_rx_tuser\(19), + m_axis_rx_tuser(10) => \^m_axis_rx_tuser\(17), + m_axis_rx_tuser(9) => \^m_axis_rx_tuser\(14), + m_axis_rx_tuser(8 downto 0) => \^m_axis_rx_tuser\(8 downto 0), + m_axis_rx_tvalid => m_axis_rx_tvalid, + pci_exp_rxn(3 downto 0) => pci_exp_rxn(3 downto 0), + pci_exp_rxp(3 downto 0) => pci_exp_rxp(3 downto 0), + pci_exp_txn(3 downto 0) => pci_exp_txn(3 downto 0), + pci_exp_txp(3 downto 0) => pci_exp_txp(3 downto 0), + pcie_drp_addr(8 downto 0) => pcie_drp_addr(8 downto 0), + pcie_drp_clk => pcie_drp_clk, + pcie_drp_di(15 downto 0) => pcie_drp_di(15 downto 0), + pcie_drp_do(15 downto 0) => pcie_drp_do(15 downto 0), + pcie_drp_en => pcie_drp_en, + pcie_drp_rdy => pcie_drp_rdy, + pcie_drp_we => pcie_drp_we, + pipe_dclk_in => pipe_dclk_in, + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_oobclk_in => pipe_oobclk_in, + pipe_pclk_in => pipe_pclk_in, + pipe_pclk_sel_out(3 downto 0) => pipe_pclk_sel_out(3 downto 0), + pipe_rxoutclk_out(3 downto 0) => pipe_rxoutclk_out(3 downto 0), + pipe_rxusrclk_in => pipe_rxusrclk_in, + pipe_txoutclk_out => pipe_txoutclk_out, + pipe_userclk1_in => pipe_userclk1_in, + pipe_userclk2_in => \^pipe_userclk2_in\, + pl_directed_change_done => pl_directed_change_done, + pl_directed_link_auton => pl_directed_link_auton, + pl_directed_link_change(1 downto 0) => pl_directed_link_change(1 downto 0), + pl_directed_link_speed => pl_directed_link_speed, + pl_directed_link_width(1 downto 0) => pl_directed_link_width(1 downto 0), + pl_downstream_deemph_source => pl_downstream_deemph_source, + pl_initial_link_width(2 downto 0) => pl_initial_link_width(2 downto 0), + pl_lane_reversal_mode(1 downto 0) => pl_lane_reversal_mode(1 downto 0), + pl_link_gen2_cap => pl_link_gen2_cap, + pl_link_partner_gen2_supported => pl_link_partner_gen2_supported, + pl_link_upcfg_cap => pl_link_upcfg_cap, + pl_ltssm_state(5 downto 0) => pl_ltssm_state(5 downto 0), + pl_phy_lnk_up => pl_phy_lnk_up, + pl_received_hot_rst => pl_received_hot_rst, + pl_rx_pm_state(1 downto 0) => pl_rx_pm_state(1 downto 0), + pl_sel_lnk_rate => pl_sel_lnk_rate, + pl_sel_lnk_width(1 downto 0) => pl_sel_lnk_width(1 downto 0), + pl_transmit_hot_rst => pl_transmit_hot_rst, + pl_tx_pm_state(2 downto 0) => pl_tx_pm_state(2 downto 0), + pl_upstream_prefer_deemph => pl_upstream_prefer_deemph, + rx_np_ok => rx_np_ok, + rx_np_req => rx_np_req, + s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0), + s_axis_tx_tkeep(0) => s_axis_tx_tkeep(7), + s_axis_tx_tlast => s_axis_tx_tlast, + s_axis_tx_tready => s_axis_tx_tready, + s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0), + s_axis_tx_tvalid => s_axis_tx_tvalid, + sys_clk => sys_clk, + sys_rst_n => sys_rst_n, + tx_buf_av(5 downto 0) => tx_buf_av(5 downto 0), + tx_cfg_gnt => tx_cfg_gnt, + tx_cfg_req => tx_cfg_req, + tx_err_drop => tx_err_drop, + user_lnk_up => user_lnk_up, + user_reset_out => user_reset_out + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pcie_7x_0 is + port ( + pci_exp_txp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_txn : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_rxp : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_rxn : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_pclk_in : in STD_LOGIC; + pipe_rxusrclk_in : in STD_LOGIC; + pipe_rxoutclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_dclk_in : in STD_LOGIC; + pipe_userclk1_in : in STD_LOGIC; + pipe_userclk2_in : in STD_LOGIC; + pipe_oobclk_in : in STD_LOGIC; + pipe_mmcm_lock_in : in STD_LOGIC; + pipe_txoutclk_out : out STD_LOGIC; + pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_gen3_out : out STD_LOGIC; + user_clk_out : out STD_LOGIC; + user_reset_out : out STD_LOGIC; + user_lnk_up : out STD_LOGIC; + user_app_rdy : out STD_LOGIC; + tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 ); + tx_cfg_req : out STD_LOGIC; + tx_err_drop : out STD_LOGIC; + s_axis_tx_tready : out STD_LOGIC; + s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_tx_tlast : in STD_LOGIC; + s_axis_tx_tvalid : in STD_LOGIC; + s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ); + tx_cfg_gnt : in STD_LOGIC; + m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axis_rx_tlast : out STD_LOGIC; + m_axis_rx_tvalid : out STD_LOGIC; + m_axis_rx_tready : in STD_LOGIC; + m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 ); + rx_np_ok : in STD_LOGIC; + rx_np_req : in STD_LOGIC; + fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_rd_wr_done : out STD_LOGIC; + cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_dcommand2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_pmcsr_pme_en : out STD_LOGIC; + cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_pmcsr_pme_status : out STD_LOGIC; + cfg_received_func_lvl_rst : out STD_LOGIC; + cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_byte_en : in STD_LOGIC_VECTOR ( 3 downto 0 ); + cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); + cfg_mgmt_wr_en : in STD_LOGIC; + cfg_mgmt_rd_en : in STD_LOGIC; + cfg_mgmt_wr_readonly : in STD_LOGIC; + cfg_err_ecrc : in STD_LOGIC; + cfg_err_ur : in STD_LOGIC; + cfg_err_cpl_timeout : in STD_LOGIC; + cfg_err_cpl_unexpect : in STD_LOGIC; + cfg_err_cpl_abort : in STD_LOGIC; + cfg_err_posted : in STD_LOGIC; + cfg_err_cor : in STD_LOGIC; + cfg_err_atomic_egress_blocked : in STD_LOGIC; + cfg_err_internal_cor : in STD_LOGIC; + cfg_err_malformed : in STD_LOGIC; + cfg_err_mc_blocked : in STD_LOGIC; + cfg_err_poisoned : in STD_LOGIC; + cfg_err_norecovery : in STD_LOGIC; + cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); + cfg_err_cpl_rdy : out STD_LOGIC; + cfg_err_locked : in STD_LOGIC; + cfg_err_acs : in STD_LOGIC; + cfg_err_internal_uncor : in STD_LOGIC; + cfg_trn_pending : in STD_LOGIC; + cfg_pm_halt_aspm_l0s : in STD_LOGIC; + cfg_pm_halt_aspm_l1 : in STD_LOGIC; + cfg_pm_force_state_en : in STD_LOGIC; + cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); + cfg_interrupt : in STD_LOGIC; + cfg_interrupt_rdy : out STD_LOGIC; + cfg_interrupt_assert : in STD_LOGIC; + cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_interrupt_msienable : out STD_LOGIC; + cfg_interrupt_msixenable : out STD_LOGIC; + cfg_interrupt_msixfm : out STD_LOGIC; + cfg_interrupt_stat : in STD_LOGIC; + cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_to_turnoff : out STD_LOGIC; + cfg_turnoff_ok : in STD_LOGIC; + cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_pm_wake : in STD_LOGIC; + cfg_pm_send_pme_to : in STD_LOGIC; + cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC; + cfg_msg_received : out STD_LOGIC; + cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_bridge_serr_en : out STD_LOGIC; + cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC; + cfg_root_control_syserr_corr_err_en : out STD_LOGIC; + cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC; + cfg_root_control_syserr_fatal_err_en : out STD_LOGIC; + cfg_root_control_pme_int_en : out STD_LOGIC; + cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_corr_err_received : out STD_LOGIC; + cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC; + cfg_aer_rooterr_fatal_err_received : out STD_LOGIC; + cfg_msg_received_err_cor : out STD_LOGIC; + cfg_msg_received_err_non_fatal : out STD_LOGIC; + cfg_msg_received_err_fatal : out STD_LOGIC; + cfg_msg_received_pm_as_nak : out STD_LOGIC; + cfg_msg_received_pm_pme : out STD_LOGIC; + cfg_msg_received_pme_to_ack : out STD_LOGIC; + cfg_msg_received_assert_int_a : out STD_LOGIC; + cfg_msg_received_assert_int_b : out STD_LOGIC; + cfg_msg_received_assert_int_c : out STD_LOGIC; + cfg_msg_received_assert_int_d : out STD_LOGIC; + cfg_msg_received_deassert_int_a : out STD_LOGIC; + cfg_msg_received_deassert_int_b : out STD_LOGIC; + cfg_msg_received_deassert_int_c : out STD_LOGIC; + cfg_msg_received_deassert_int_d : out STD_LOGIC; + cfg_msg_received_setslotpowerlimit : out STD_LOGIC; + pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_directed_link_speed : in STD_LOGIC; + pl_directed_link_auton : in STD_LOGIC; + pl_upstream_prefer_deemph : in STD_LOGIC; + pl_sel_lnk_rate : out STD_LOGIC; + pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 ); + pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_phy_lnk_up : out STD_LOGIC; + pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_link_upcfg_cap : out STD_LOGIC; + pl_link_gen2_cap : out STD_LOGIC; + pl_link_partner_gen2_supported : out STD_LOGIC; + pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pl_directed_change_done : out STD_LOGIC; + pl_received_hot_rst : out STD_LOGIC; + pl_transmit_hot_rst : in STD_LOGIC; + pl_downstream_deemph_source : in STD_LOGIC; + cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 ); + cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_err_aer_headerlog_set : out STD_LOGIC; + cfg_aer_ecrc_check_en : out STD_LOGIC; + cfg_aer_ecrc_gen_en : out STD_LOGIC; + cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 ); + sys_clk : in STD_LOGIC; + sys_rst_n : in STD_LOGIC; + pipe_mmcm_rst_n : in STD_LOGIC; + pcie_drp_clk : in STD_LOGIC; + pcie_drp_en : in STD_LOGIC; + pcie_drp_we : in STD_LOGIC; + pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 ); + pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 ); + pcie_drp_rdy : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of pcie_7x_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of pcie_7x_0 : entity is "pcie_7x_0,pcie_7x_0_pcie2_top,{}"; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of pcie_7x_0 : entity is "yes"; + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of pcie_7x_0 : entity is "pcie_7x_0_pcie2_top,Vivado 2020.2"; +end pcie_7x_0; + +architecture STRUCTURE of pcie_7x_0 is + signal \\ : STD_LOGIC; + signal \\ : STD_LOGIC; + signal \^cfg_command\ : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \^cfg_dcommand\ : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal \^cfg_dcommand2\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \^cfg_dstatus\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \^cfg_lcommand\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \^cfg_lstatus\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \^m_axis_rx_tkeep\ : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal \^m_axis_rx_tuser\ : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal NLW_inst_ext_ch_gt_drpclk_UNCONNECTED : STD_LOGIC; + signal NLW_inst_int_dclk_out_UNCONNECTED : STD_LOGIC; + signal NLW_inst_int_mmcm_lock_out_UNCONNECTED : STD_LOGIC; + signal NLW_inst_int_oobclk_out_UNCONNECTED : STD_LOGIC; + signal NLW_inst_int_pclk_out_slave_UNCONNECTED : STD_LOGIC; + signal NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED : STD_LOGIC; + signal NLW_inst_int_userclk1_out_UNCONNECTED : STD_LOGIC; + signal NLW_inst_int_userclk2_out_UNCONNECTED : STD_LOGIC; + signal NLW_inst_pipe_qrst_idle_UNCONNECTED : STD_LOGIC; + signal NLW_inst_pipe_rate_idle_UNCONNECTED : STD_LOGIC; + signal NLW_inst_pipe_rst_idle_UNCONNECTED : STD_LOGIC; + signal NLW_inst_qpll_drp_clk_UNCONNECTED : STD_LOGIC; + signal NLW_inst_qpll_drp_gen3_UNCONNECTED : STD_LOGIC; + signal NLW_inst_qpll_drp_ovrd_UNCONNECTED : STD_LOGIC; + signal NLW_inst_qpll_drp_rst_n_UNCONNECTED : STD_LOGIC; + signal NLW_inst_qpll_drp_start_UNCONNECTED : STD_LOGIC; + signal NLW_inst_qpll_qplld_UNCONNECTED : STD_LOGIC; + signal NLW_inst_startup_cfgclk_UNCONNECTED : STD_LOGIC; + signal NLW_inst_startup_cfgmclk_UNCONNECTED : STD_LOGIC; + signal NLW_inst_startup_eos_UNCONNECTED : STD_LOGIC; + signal NLW_inst_startup_preq_UNCONNECTED : STD_LOGIC; + signal NLW_inst_user_app_rdy_UNCONNECTED : STD_LOGIC; + signal NLW_inst_cfg_command_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 3 ); + signal NLW_inst_cfg_dcommand_UNCONNECTED : STD_LOGIC_VECTOR ( 15 to 15 ); + signal NLW_inst_cfg_dcommand2_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 12 ); + signal NLW_inst_cfg_dstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 4 ); + signal NLW_inst_cfg_lcommand_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 2 ); + signal NLW_inst_cfg_lstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 2 ); + signal NLW_inst_cfg_status_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal NLW_inst_common_commands_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_ext_ch_gt_drpdo_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_ext_ch_gt_drprdy_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_gt_ch_drp_rdy_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_icap_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_int_qplllock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_int_qplloutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_int_qplloutrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_int_rxoutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_m_axis_rx_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_m_axis_rx_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 9 ); + signal NLW_inst_pipe_cpll_lock_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_debug_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_pipe_debug_0_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_debug_1_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_debug_2_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_debug_3_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_debug_4_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_debug_5_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_debug_6_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_debug_7_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_debug_8_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_debug_9_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_dmonitorout_UNCONNECTED : STD_LOGIC_VECTOR ( 59 downto 0 ); + signal NLW_inst_pipe_drp_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 27 downto 0 ); + signal NLW_inst_pipe_eyescandataerror_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_qpll_lock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_pipe_qrst_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_pipe_rate_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); + signal NLW_inst_pipe_rst_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_inst_pipe_rxbufstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_pipe_rxcommadet_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_rxdisperr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_pipe_rxdlysresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_rxnotintable_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_pipe_rxphaligndone_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_rxpmaresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_rxprbserr_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_rxstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_pipe_rxsyncdone_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_sync_fsm_rx_UNCONNECTED : STD_LOGIC_VECTOR ( 27 downto 0 ); + signal NLW_inst_pipe_sync_fsm_tx_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal NLW_inst_pipe_tx_0_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 ); + signal NLW_inst_pipe_tx_1_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 ); + signal NLW_inst_pipe_tx_2_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 ); + signal NLW_inst_pipe_tx_3_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 ); + signal NLW_inst_pipe_tx_4_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 ); + signal NLW_inst_pipe_tx_5_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 ); + signal NLW_inst_pipe_tx_6_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 ); + signal NLW_inst_pipe_tx_7_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 ); + signal NLW_inst_pipe_txdlysresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_txphaligndone_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_pipe_txphinitdone_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_qpll_qpllreset_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute CFG_CTL_IF : string; + attribute CFG_CTL_IF of inst : label is "TRUE"; + attribute CFG_FC_IF : string; + attribute CFG_FC_IF of inst : label is "TRUE"; + attribute CFG_MGMT_IF : string; + attribute CFG_MGMT_IF of inst : label is "TRUE"; + attribute CFG_STATUS_IF : string; + attribute CFG_STATUS_IF of inst : label is "TRUE"; + attribute CLASS_CODE : string; + attribute CLASS_CODE of inst : label is "050000"; + attribute C_DATA_WIDTH : integer; + attribute C_DATA_WIDTH of inst : label is 64; + attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; + attribute ENABLE_JTAG_DBG : string; + attribute ENABLE_JTAG_DBG of inst : label is "FALSE"; + attribute ERR_REPORTING_IF : string; + attribute ERR_REPORTING_IF of inst : label is "TRUE"; + attribute EXT_CH_GT_DRP : string; + attribute EXT_CH_GT_DRP of inst : label is "FALSE"; + attribute EXT_PIPE_INTERFACE : string; + attribute EXT_PIPE_INTERFACE of inst : label is "FALSE"; + attribute EXT_STARTUP_PRIMITIVE : string; + attribute EXT_STARTUP_PRIMITIVE of inst : label is "FALSE"; + attribute KEEP_WIDTH : integer; + attribute KEEP_WIDTH of inst : label is 8; + attribute LINK_CAP_MAX_LINK_WIDTH : integer; + attribute LINK_CAP_MAX_LINK_WIDTH of inst : label is 4; + attribute PCIE_ASYNC_EN : string; + attribute PCIE_ASYNC_EN of inst : label is "FALSE"; + attribute PCIE_EXT_CLK : string; + attribute PCIE_EXT_CLK of inst : label is "TRUE"; + attribute PCIE_EXT_GT_COMMON : string; + attribute PCIE_EXT_GT_COMMON of inst : label is "FALSE"; + attribute PIPE_SIM : string; + attribute PIPE_SIM of inst : label is "FALSE"; + attribute PL_INTERFACE : string; + attribute PL_INTERFACE of inst : label is "TRUE"; + attribute RCV_MSG_IF : string; + attribute RCV_MSG_IF of inst : label is "TRUE"; + attribute REDUCE_OOB_FREQ : string; + attribute REDUCE_OOB_FREQ of inst : label is "FALSE"; + attribute SHARED_LOGIC_IN_CORE : string; + attribute SHARED_LOGIC_IN_CORE of inst : label is "FALSE"; + attribute TRANSCEIVER_CTRL_STATUS_PORTS : string; + attribute TRANSCEIVER_CTRL_STATUS_PORTS of inst : label is "FALSE"; + attribute bar_0 : string; + attribute bar_0 of inst : label is "FFFF0000"; + attribute bar_1 : string; + attribute bar_1 of inst : label is "00000000"; + attribute bar_2 : string; + attribute bar_2 of inst : label is "00000000"; + attribute bar_3 : string; + attribute bar_3 of inst : label is "00000000"; + attribute bar_4 : string; + attribute bar_4 of inst : label is "00000000"; + attribute bar_5 : string; + attribute bar_5 of inst : label is "00000000"; + attribute bram_lat : string; + attribute bram_lat of inst : label is "0"; + attribute c_aer_base_ptr : string; + attribute c_aer_base_ptr of inst : label is "000"; + attribute c_aer_cap_ecrc_check_capable : string; + attribute c_aer_cap_ecrc_check_capable of inst : label is "FALSE"; + attribute c_aer_cap_ecrc_gen_capable : string; + attribute c_aer_cap_ecrc_gen_capable of inst : label is "FALSE"; + attribute c_aer_cap_multiheader : string; + attribute c_aer_cap_multiheader of inst : label is "FALSE"; + attribute c_aer_cap_nextptr : string; + attribute c_aer_cap_nextptr of inst : label is "000"; + attribute c_aer_cap_on : string; + attribute c_aer_cap_on of inst : label is "FALSE"; + attribute c_aer_cap_optional_err_support : string; + attribute c_aer_cap_optional_err_support of inst : label is "000000"; + attribute c_aer_cap_permit_rooterr_update : string; + attribute c_aer_cap_permit_rooterr_update of inst : label is "FALSE"; + attribute c_buf_opt_bma : string; + attribute c_buf_opt_bma of inst : label is "TRUE"; + attribute c_component_name : string; + attribute c_component_name of inst : label is "pcie_7x_0"; + attribute c_cpl_inf : string; + attribute c_cpl_inf of inst : label is "TRUE"; + attribute c_cpl_infinite : string; + attribute c_cpl_infinite of inst : label is "TRUE"; + attribute c_cpl_timeout_disable_sup : string; + attribute c_cpl_timeout_disable_sup of inst : label is "FALSE"; + attribute c_cpl_timeout_range : string; + attribute c_cpl_timeout_range of inst : label is "0010"; + attribute c_cpl_timeout_ranges_sup : string; + attribute c_cpl_timeout_ranges_sup of inst : label is "2"; + attribute c_d1_support : string; + attribute c_d1_support of inst : label is "FALSE"; + attribute c_d2_support : string; + attribute c_d2_support of inst : label is "FALSE"; + attribute c_de_emph : string; + attribute c_de_emph of inst : label is "FALSE"; + attribute c_dev_cap2_ari_forwarding_supported : string; + attribute c_dev_cap2_ari_forwarding_supported of inst : label is "FALSE"; + attribute c_dev_cap2_atomicop32_completer_supported : string; + attribute c_dev_cap2_atomicop32_completer_supported of inst : label is "FALSE"; + attribute c_dev_cap2_atomicop64_completer_supported : string; + attribute c_dev_cap2_atomicop64_completer_supported of inst : label is "FALSE"; + attribute c_dev_cap2_atomicop_routing_supported : string; + attribute c_dev_cap2_atomicop_routing_supported of inst : label is "FALSE"; + attribute c_dev_cap2_cas128_completer_supported : string; + attribute c_dev_cap2_cas128_completer_supported of inst : label is "FALSE"; + attribute c_dev_cap2_tph_completer_supported : string; + attribute c_dev_cap2_tph_completer_supported of inst : label is "00"; + attribute c_dev_control_ext_tag_default : string; + attribute c_dev_control_ext_tag_default of inst : label is "FALSE"; + attribute c_dev_port_type : string; + attribute c_dev_port_type of inst : label is "0"; + attribute c_dis_lane_reverse : string; + attribute c_dis_lane_reverse of inst : label is "TRUE"; + attribute c_disable_rx_poisoned_resp : string; + attribute c_disable_rx_poisoned_resp of inst : label is "FALSE"; + attribute c_disable_scrambling : string; + attribute c_disable_scrambling of inst : label is "FALSE"; + attribute c_disable_tx_aspm_l0s : string; + attribute c_disable_tx_aspm_l0s of inst : label is "FALSE"; + attribute c_dll_lnk_actv_cap : string; + attribute c_dll_lnk_actv_cap of inst : label is "FALSE"; + attribute c_dsi_bool : string; + attribute c_dsi_bool of inst : label is "FALSE"; + attribute c_dsn_base_ptr : string; + attribute c_dsn_base_ptr of inst : label is "100"; + attribute c_dsn_cap_enabled : string; + attribute c_dsn_cap_enabled of inst : label is "TRUE"; + attribute c_dsn_next_ptr : string; + attribute c_dsn_next_ptr of inst : label is "000"; + attribute c_enable_msg_route : string; + attribute c_enable_msg_route of inst : label is "00000000000"; + attribute c_ep_l0s_accpt_lat : string; + attribute c_ep_l0s_accpt_lat of inst : label is "0"; + attribute c_ep_l1_accpt_lat : string; + attribute c_ep_l1_accpt_lat of inst : label is "7"; + attribute c_ext_pci_cfg_space_addr : string; + attribute c_ext_pci_cfg_space_addr of inst : label is "3FF"; + attribute c_external_clocking : string; + attribute c_external_clocking of inst : label is "TRUE"; + attribute c_fc_cpld : string; + attribute c_fc_cpld of inst : label is "973"; + attribute c_fc_cplh : string; + attribute c_fc_cplh of inst : label is "36"; + attribute c_fc_npd : string; + attribute c_fc_npd of inst : label is "24"; + attribute c_fc_nph : string; + attribute c_fc_nph of inst : label is "12"; + attribute c_fc_pd : string; + attribute c_fc_pd of inst : label is "949"; + attribute c_fc_ph : string; + attribute c_fc_ph of inst : label is "32"; + attribute c_gen1 : string; + attribute c_gen1 of inst : label is "1'b1"; + attribute c_header_type : string; + attribute c_header_type of inst : label is "00"; + attribute c_hw_auton_spd_disable : string; + attribute c_hw_auton_spd_disable of inst : label is "FALSE"; + attribute c_int_width : integer; + attribute c_int_width of inst : label is 64; + attribute c_last_cfg_dw : string; + attribute c_last_cfg_dw of inst : label is "10C"; + attribute c_link_cap_aspm_optionality : string; + attribute c_link_cap_aspm_optionality of inst : label is "FALSE"; + attribute c_ll_ack_timeout : string; + attribute c_ll_ack_timeout of inst : label is "0000"; + attribute c_ll_ack_timeout_enable : string; + attribute c_ll_ack_timeout_enable of inst : label is "FALSE"; + attribute c_ll_ack_timeout_function : string; + attribute c_ll_ack_timeout_function of inst : label is "0"; + attribute c_ll_replay_timeout : string; + attribute c_ll_replay_timeout of inst : label is "0000"; + attribute c_ll_replay_timeout_enable : string; + attribute c_ll_replay_timeout_enable of inst : label is "FALSE"; + attribute c_ll_replay_timeout_func : string; + attribute c_ll_replay_timeout_func of inst : label is "1"; + attribute c_lnk_bndwdt_notif : string; + attribute c_lnk_bndwdt_notif of inst : label is "FALSE"; + attribute c_msi : string; + attribute c_msi of inst : label is "0"; + attribute c_msi_64b_addr : string; + attribute c_msi_64b_addr of inst : label is "TRUE"; + attribute c_msi_cap_on : string; + attribute c_msi_cap_on of inst : label is "FALSE"; + attribute c_msi_mult_msg_extn : string; + attribute c_msi_mult_msg_extn of inst : label is "0"; + attribute c_msi_per_vctr_mask_cap : string; + attribute c_msi_per_vctr_mask_cap of inst : label is "FALSE"; + attribute c_msix_cap_on : string; + attribute c_msix_cap_on of inst : label is "FALSE"; + attribute c_msix_next_ptr : string; + attribute c_msix_next_ptr of inst : label is "00"; + attribute c_msix_pba_bir : string; + attribute c_msix_pba_bir of inst : label is "0"; + attribute c_msix_pba_offset : string; + attribute c_msix_pba_offset of inst : label is "0"; + attribute c_msix_table_bir : string; + attribute c_msix_table_bir of inst : label is "0"; + attribute c_msix_table_offset : string; + attribute c_msix_table_offset of inst : label is "0"; + attribute c_msix_table_size : string; + attribute c_msix_table_size of inst : label is "000"; + attribute c_pci_cfg_space_addr : string; + attribute c_pci_cfg_space_addr of inst : label is "3F"; + attribute c_pcie_blk_locn : string; + attribute c_pcie_blk_locn of inst : label is "0"; + attribute c_pcie_cap_next_ptr : string; + attribute c_pcie_cap_next_ptr of inst : label is "00"; + attribute c_pcie_cap_slot_implemented : string; + attribute c_pcie_cap_slot_implemented of inst : label is "FALSE"; + attribute c_pcie_dbg_ports : string; + attribute c_pcie_dbg_ports of inst : label is "TRUE"; + attribute c_pcie_fast_config : integer; + attribute c_pcie_fast_config of inst : label is 0; + attribute c_perf_level_high : string; + attribute c_perf_level_high of inst : label is "TRUE"; + attribute c_phantom_functions : string; + attribute c_phantom_functions of inst : label is "0"; + attribute c_pm_cap_next_ptr : string; + attribute c_pm_cap_next_ptr of inst : label is "60"; + attribute c_pme_support : string; + attribute c_pme_support of inst : label is "0F"; + attribute c_rbar_base_ptr : string; + attribute c_rbar_base_ptr of inst : label is "000"; + attribute c_rbar_cap_control_encodedbar0 : string; + attribute c_rbar_cap_control_encodedbar0 of inst : label is "00"; + attribute c_rbar_cap_control_encodedbar1 : string; + attribute c_rbar_cap_control_encodedbar1 of inst : label is "00"; + attribute c_rbar_cap_control_encodedbar2 : string; + attribute c_rbar_cap_control_encodedbar2 of inst : label is "00"; + attribute c_rbar_cap_control_encodedbar3 : string; + attribute c_rbar_cap_control_encodedbar3 of inst : label is "00"; + attribute c_rbar_cap_control_encodedbar4 : string; + attribute c_rbar_cap_control_encodedbar4 of inst : label is "00"; + attribute c_rbar_cap_control_encodedbar5 : string; + attribute c_rbar_cap_control_encodedbar5 of inst : label is "00"; + attribute c_rbar_cap_index0 : string; + attribute c_rbar_cap_index0 of inst : label is "0"; + attribute c_rbar_cap_index1 : string; + attribute c_rbar_cap_index1 of inst : label is "0"; + attribute c_rbar_cap_index2 : string; + attribute c_rbar_cap_index2 of inst : label is "0"; + attribute c_rbar_cap_index3 : string; + attribute c_rbar_cap_index3 of inst : label is "0"; + attribute c_rbar_cap_index4 : string; + attribute c_rbar_cap_index4 of inst : label is "0"; + attribute c_rbar_cap_index5 : string; + attribute c_rbar_cap_index5 of inst : label is "0"; + attribute c_rbar_cap_nextptr : string; + attribute c_rbar_cap_nextptr of inst : label is "000"; + attribute c_rbar_cap_on : string; + attribute c_rbar_cap_on of inst : label is "FALSE"; + attribute c_rbar_cap_sup0 : string; + attribute c_rbar_cap_sup0 of inst : label is "00001"; + attribute c_rbar_cap_sup1 : string; + attribute c_rbar_cap_sup1 of inst : label is "00001"; + attribute c_rbar_cap_sup2 : string; + attribute c_rbar_cap_sup2 of inst : label is "00001"; + attribute c_rbar_cap_sup3 : string; + attribute c_rbar_cap_sup3 of inst : label is "00001"; + attribute c_rbar_cap_sup4 : string; + attribute c_rbar_cap_sup4 of inst : label is "00001"; + attribute c_rbar_cap_sup5 : string; + attribute c_rbar_cap_sup5 of inst : label is "00001"; + attribute c_rbar_num : string; + attribute c_rbar_num of inst : label is "0"; + attribute c_rcb : string; + attribute c_rcb of inst : label is "0"; + attribute c_recrc_check : string; + attribute c_recrc_check of inst : label is "0"; + attribute c_recrc_check_trim : string; + attribute c_recrc_check_trim of inst : label is "FALSE"; + attribute c_rev_gt_order : string; + attribute c_rev_gt_order of inst : label is "FALSE"; + attribute c_root_cap_crs : string; + attribute c_root_cap_crs of inst : label is "FALSE"; + attribute c_rx_raddr_lat : string; + attribute c_rx_raddr_lat of inst : label is "0"; + attribute c_rx_ram_limit : string; + attribute c_rx_ram_limit of inst : label is "FFF"; + attribute c_rx_rdata_lat : string; + attribute c_rx_rdata_lat of inst : label is "2"; + attribute c_rx_write_lat : string; + attribute c_rx_write_lat of inst : label is "0"; + attribute c_silicon_rev : string; + attribute c_silicon_rev of inst : label is "2"; + attribute c_slot_cap_attn_butn : string; + attribute c_slot_cap_attn_butn of inst : label is "FALSE"; + attribute c_slot_cap_attn_ind : string; + attribute c_slot_cap_attn_ind of inst : label is "FALSE"; + attribute c_slot_cap_elec_interlock : string; + attribute c_slot_cap_elec_interlock of inst : label is "FALSE"; + attribute c_slot_cap_hotplug_cap : string; + attribute c_slot_cap_hotplug_cap of inst : label is "FALSE"; + attribute c_slot_cap_hotplug_surprise : string; + attribute c_slot_cap_hotplug_surprise of inst : label is "FALSE"; + attribute c_slot_cap_mrl : string; + attribute c_slot_cap_mrl of inst : label is "FALSE"; + attribute c_slot_cap_no_cmd_comp_sup : string; + attribute c_slot_cap_no_cmd_comp_sup of inst : label is "FALSE"; + attribute c_slot_cap_physical_slot_num : string; + attribute c_slot_cap_physical_slot_num of inst : label is "0"; + attribute c_slot_cap_pwr_ctrl : string; + attribute c_slot_cap_pwr_ctrl of inst : label is "FALSE"; + attribute c_slot_cap_pwr_ind : string; + attribute c_slot_cap_pwr_ind of inst : label is "FALSE"; + attribute c_slot_cap_pwr_limit_scale : string; + attribute c_slot_cap_pwr_limit_scale of inst : label is "0"; + attribute c_slot_cap_pwr_limit_value : string; + attribute c_slot_cap_pwr_limit_value of inst : label is "0"; + attribute c_surprise_dn_err_cap : string; + attribute c_surprise_dn_err_cap of inst : label is "FALSE"; + attribute c_trgt_lnk_spd : string; + attribute c_trgt_lnk_spd of inst : label is "2"; + attribute c_trn_np_fc : string; + attribute c_trn_np_fc of inst : label is "TRUE"; + attribute c_tx_last_tlp : string; + attribute c_tx_last_tlp of inst : label is "30"; + attribute c_tx_raddr_lat : string; + attribute c_tx_raddr_lat of inst : label is "0"; + attribute c_tx_rdata_lat : string; + attribute c_tx_rdata_lat of inst : label is "2"; + attribute c_tx_write_lat : string; + attribute c_tx_write_lat of inst : label is "0"; + attribute c_upconfig_capable : string; + attribute c_upconfig_capable of inst : label is "TRUE"; + attribute c_upstream_facing : string; + attribute c_upstream_facing of inst : label is "TRUE"; + attribute c_ur_atomic : string; + attribute c_ur_atomic of inst : label is "FALSE"; + attribute c_ur_inv_req : string; + attribute c_ur_inv_req of inst : label is "TRUE"; + attribute c_ur_prs_response : string; + attribute c_ur_prs_response of inst : label is "TRUE"; + attribute c_vc_base_ptr : string; + attribute c_vc_base_ptr of inst : label is "000"; + attribute c_vc_cap_enabled : string; + attribute c_vc_cap_enabled of inst : label is "FALSE"; + attribute c_vc_cap_reject_snoop : string; + attribute c_vc_cap_reject_snoop of inst : label is "FALSE"; + attribute c_vc_next_ptr : string; + attribute c_vc_next_ptr of inst : label is "000"; + attribute c_vsec_base_ptr : string; + attribute c_vsec_base_ptr of inst : label is "000"; + attribute c_vsec_cap_enabled : string; + attribute c_vsec_cap_enabled of inst : label is "FALSE"; + attribute c_vsec_next_ptr : string; + attribute c_vsec_next_ptr of inst : label is "000"; + attribute c_xlnx_ref_board : string; + attribute c_xlnx_ref_board of inst : label is "ZC706"; + attribute cap_ver : string; + attribute cap_ver of inst : label is "2"; + attribute cardbus_cis_ptr : string; + attribute cardbus_cis_ptr of inst : label is "00000000"; + attribute cmps : string; + attribute cmps of inst : label is "3"; + attribute con_scl_fctr_d0_state : string; + attribute con_scl_fctr_d0_state of inst : label is "0"; + attribute con_scl_fctr_d1_state : string; + attribute con_scl_fctr_d1_state of inst : label is "0"; + attribute con_scl_fctr_d2_state : string; + attribute con_scl_fctr_d2_state of inst : label is "0"; + attribute con_scl_fctr_d3_state : string; + attribute con_scl_fctr_d3_state of inst : label is "0"; + attribute cost_table : integer; + attribute cost_table of inst : label is 1; + attribute d1_sup : string; + attribute d1_sup of inst : label is "0"; + attribute d2_sup : string; + attribute d2_sup of inst : label is "0"; + attribute dev_id : string; + attribute dev_id of inst : label is "7024"; + attribute dev_port_type : string; + attribute dev_port_type of inst : label is "0000"; + attribute dis_scl_fctr_d0_state : string; + attribute dis_scl_fctr_d0_state of inst : label is "0"; + attribute dis_scl_fctr_d1_state : string; + attribute dis_scl_fctr_d1_state of inst : label is "0"; + attribute dis_scl_fctr_d2_state : string; + attribute dis_scl_fctr_d2_state of inst : label is "0"; + attribute dis_scl_fctr_d3_state : string; + attribute dis_scl_fctr_d3_state of inst : label is "0"; + attribute dsi : string; + attribute dsi of inst : label is "0"; + attribute ep_l0s_accpt_lat : string; + attribute ep_l0s_accpt_lat of inst : label is "000"; + attribute ep_l1_accpt_lat : string; + attribute ep_l1_accpt_lat of inst : label is "111"; + attribute ext_tag_fld_sup : string; + attribute ext_tag_fld_sup of inst : label is "FALSE"; + attribute int_pin : string; + attribute int_pin of inst : label is "1"; + attribute intx : string; + attribute intx of inst : label is "TRUE"; + attribute max_lnk_spd : string; + attribute max_lnk_spd of inst : label is "2"; + attribute max_lnk_wdt : string; + attribute max_lnk_wdt of inst : label is "000100"; + attribute mps : string; + attribute mps of inst : label is "011"; + attribute no_soft_rst : string; + attribute no_soft_rst of inst : label is "TRUE"; + attribute pci_exp_int_freq : integer; + attribute pci_exp_int_freq of inst : label is 3; + attribute pci_exp_ref_freq : string; + attribute pci_exp_ref_freq of inst : label is "0"; + attribute phantm_func_sup : string; + attribute phantm_func_sup of inst : label is "00"; + attribute pme_sup : string; + attribute pme_sup of inst : label is "0F"; + attribute pwr_con_d0_state : string; + attribute pwr_con_d0_state of inst : label is "00"; + attribute pwr_con_d1_state : string; + attribute pwr_con_d1_state of inst : label is "00"; + attribute pwr_con_d2_state : string; + attribute pwr_con_d2_state of inst : label is "00"; + attribute pwr_con_d3_state : string; + attribute pwr_con_d3_state of inst : label is "00"; + attribute pwr_dis_d0_state : string; + attribute pwr_dis_d0_state of inst : label is "00"; + attribute pwr_dis_d1_state : string; + attribute pwr_dis_d1_state of inst : label is "00"; + attribute pwr_dis_d2_state : string; + attribute pwr_dis_d2_state of inst : label is "00"; + attribute pwr_dis_d3_state : string; + attribute pwr_dis_d3_state of inst : label is "00"; + attribute rev_id : string; + attribute rev_id of inst : label is "00"; + attribute slot_clk : string; + attribute slot_clk of inst : label is "TRUE"; + attribute subsys_id : string; + attribute subsys_id of inst : label is "0007"; + attribute subsys_ven_id : string; + attribute subsys_ven_id of inst : label is "10EE"; + attribute ven_id : string; + attribute ven_id of inst : label is "10EE"; + attribute xrom_bar : string; + attribute xrom_bar of inst : label is "00000000"; + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_INFO of cfg_aer_ecrc_check_en : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_check_en"; + attribute X_INTERFACE_INFO of cfg_aer_ecrc_gen_en : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_gen_en"; + attribute X_INTERFACE_INFO of cfg_aer_rooterr_corr_err_received : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_received"; + attribute X_INTERFACE_INFO of cfg_aer_rooterr_corr_err_reporting_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_reporting_en"; + attribute X_INTERFACE_INFO of cfg_aer_rooterr_fatal_err_received : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_received"; + attribute X_INTERFACE_INFO of cfg_aer_rooterr_fatal_err_reporting_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_reporting_en"; + attribute X_INTERFACE_INFO of cfg_aer_rooterr_non_fatal_err_received : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_received"; + attribute X_INTERFACE_INFO of cfg_aer_rooterr_non_fatal_err_reporting_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_reporting_en"; + attribute X_INTERFACE_INFO of cfg_bridge_serr_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bridge_serr_en"; + attribute X_INTERFACE_INFO of cfg_err_acs : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err acs"; + attribute X_INTERFACE_INFO of cfg_err_aer_headerlog_set : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog_set"; + attribute X_INTERFACE_INFO of cfg_err_atomic_egress_blocked : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err atomic_egress_blocked"; + attribute X_INTERFACE_INFO of cfg_err_cor : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cor"; + attribute X_INTERFACE_INFO of cfg_err_cpl_abort : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_abort"; + attribute X_INTERFACE_INFO of cfg_err_cpl_rdy : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_rdy"; + attribute X_INTERFACE_INFO of cfg_err_cpl_timeout : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_timeout"; + attribute X_INTERFACE_INFO of cfg_err_cpl_unexpect : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_unexpect"; + attribute X_INTERFACE_INFO of cfg_err_ecrc : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ecrc"; + attribute X_INTERFACE_INFO of cfg_err_internal_cor : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_cor"; + attribute X_INTERFACE_INFO of cfg_err_internal_uncor : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_uncor"; + attribute X_INTERFACE_INFO of cfg_err_locked : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err locked"; + attribute X_INTERFACE_INFO of cfg_err_malformed : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err malformed"; + attribute X_INTERFACE_INFO of cfg_err_mc_blocked : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err mc_blocked"; + attribute X_INTERFACE_INFO of cfg_err_norecovery : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err norecovery"; + attribute X_INTERFACE_INFO of cfg_err_poisoned : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err poisoned"; + attribute X_INTERFACE_INFO of cfg_err_posted : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err posted"; + attribute X_INTERFACE_INFO of cfg_err_ur : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ur"; + attribute X_INTERFACE_INFO of cfg_interrupt : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt interrupt"; + attribute X_INTERFACE_INFO of cfg_interrupt_assert : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt assert"; + attribute X_INTERFACE_INFO of cfg_interrupt_msienable : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msienable"; + attribute X_INTERFACE_INFO of cfg_interrupt_msixenable : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixenable"; + attribute X_INTERFACE_INFO of cfg_interrupt_msixfm : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixfm"; + attribute X_INTERFACE_INFO of cfg_interrupt_rdy : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt rdy"; + attribute X_INTERFACE_INFO of cfg_interrupt_stat : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt stat"; + attribute X_INTERFACE_INFO of cfg_mgmt_rd_en : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_EN"; + attribute X_INTERFACE_INFO of cfg_mgmt_rd_wr_done : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_WRITE_DONE"; + attribute X_INTERFACE_INFO of cfg_mgmt_wr_en : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_EN"; + attribute X_INTERFACE_INFO of cfg_mgmt_wr_readonly : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READONLY"; + attribute X_INTERFACE_INFO of cfg_mgmt_wr_rw1c_as_rw : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt TYPE1_CFG_REG_ACCESS"; + attribute X_INTERFACE_INFO of cfg_msg_received : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received"; + attribute X_INTERFACE_INFO of cfg_msg_received_assert_int_a : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_a"; + attribute X_INTERFACE_INFO of cfg_msg_received_assert_int_b : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_b"; + attribute X_INTERFACE_INFO of cfg_msg_received_assert_int_c : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_c"; + attribute X_INTERFACE_INFO of cfg_msg_received_assert_int_d : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_d"; + attribute X_INTERFACE_INFO of cfg_msg_received_deassert_int_a : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_a"; + attribute X_INTERFACE_INFO of cfg_msg_received_deassert_int_b : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_b"; + attribute X_INTERFACE_INFO of cfg_msg_received_deassert_int_c : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_c"; + attribute X_INTERFACE_INFO of cfg_msg_received_deassert_int_d : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_d"; + attribute X_INTERFACE_INFO of cfg_msg_received_err_cor : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_cor"; + attribute X_INTERFACE_INFO of cfg_msg_received_err_fatal : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_fatal"; + attribute X_INTERFACE_INFO of cfg_msg_received_err_non_fatal : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_non_fatal"; + attribute X_INTERFACE_INFO of cfg_msg_received_pm_as_nak : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_pm_as_nak"; + attribute X_INTERFACE_INFO of cfg_msg_received_pm_pme : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pm_pme"; + attribute X_INTERFACE_INFO of cfg_msg_received_pme_to_ack : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pme_to_ack"; + attribute X_INTERFACE_INFO of cfg_msg_received_setslotpowerlimit : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_setslotpowerlimit"; + attribute X_INTERFACE_INFO of cfg_pm_force_state_en : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state_en"; + attribute X_INTERFACE_INFO of cfg_pm_halt_aspm_l0s : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l0s"; + attribute X_INTERFACE_INFO of cfg_pm_halt_aspm_l1 : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l1"; + attribute X_INTERFACE_INFO of cfg_pm_send_pme_to : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_send_pme_to"; + attribute X_INTERFACE_INFO of cfg_pm_wake : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_wake"; + attribute X_INTERFACE_INFO of cfg_pmcsr_pme_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_en"; + attribute X_INTERFACE_INFO of cfg_pmcsr_pme_status : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_status"; + attribute X_INTERFACE_INFO of cfg_received_func_lvl_rst : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status received_func_lvl_rst"; + attribute X_INTERFACE_INFO of cfg_root_control_pme_int_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_pme_int_en"; + attribute X_INTERFACE_INFO of cfg_root_control_syserr_corr_err_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_corr_err_en"; + attribute X_INTERFACE_INFO of cfg_root_control_syserr_fatal_err_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_fatal_err_en"; + attribute X_INTERFACE_INFO of cfg_root_control_syserr_non_fatal_err_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_non_fatal_err_en"; + attribute X_INTERFACE_INFO of cfg_slot_control_electromech_il_ctl_pulse : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status slot_control_electromech_il_ctl_pulse"; + attribute X_INTERFACE_INFO of cfg_to_turnoff : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status turnoff"; + attribute X_INTERFACE_INFO of cfg_trn_pending : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control trn_pending"; + attribute X_INTERFACE_INFO of cfg_turnoff_ok : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control turnoff_ok"; + attribute X_INTERFACE_INFO of m_axis_rx_tlast : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TLAST"; + attribute X_INTERFACE_INFO of m_axis_rx_tready : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TREADY"; + attribute X_INTERFACE_INFO of m_axis_rx_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TVALID"; + attribute X_INTERFACE_INFO of pcie_drp_en : signal is "xilinx.com:interface:drp:1.0 drp DEN"; + attribute X_INTERFACE_INFO of pcie_drp_rdy : signal is "xilinx.com:interface:drp:1.0 drp DRDY"; + attribute X_INTERFACE_INFO of pcie_drp_we : signal is "xilinx.com:interface:drp:1.0 drp DWE"; + attribute X_INTERFACE_INFO of pipe_dclk_in : signal is "xilinx.com:interface:pipe_clock:1.0 pipe_clock dclk_in"; + attribute X_INTERFACE_INFO of pipe_gen3_out : signal is "xilinx.com:interface:pipe_clock:1.0 pipe_clock gen3_out"; + attribute X_INTERFACE_INFO of pipe_mmcm_lock_in : signal is "xilinx.com:interface:pipe_clock:1.0 pipe_clock mmcm_lock_in"; + attribute X_INTERFACE_INFO of pipe_mmcm_rst_n : signal is "xilinx.com:interface:pipe_clock:1.0 pipe_clock mmcm_rst_n"; + attribute X_INTERFACE_INFO of pipe_oobclk_in : signal is "xilinx.com:interface:pipe_clock:1.0 pipe_clock oobclk_in"; + attribute X_INTERFACE_INFO of pipe_pclk_in : signal is "xilinx.com:interface:pipe_clock:1.0 pipe_clock pclk_in"; + attribute X_INTERFACE_INFO of pipe_rxusrclk_in : signal is "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxusrclk_in"; + attribute X_INTERFACE_INFO of pipe_txoutclk_out : signal is "xilinx.com:interface:pipe_clock:1.0 pipe_clock txoutclk_out"; + attribute X_INTERFACE_INFO of pipe_userclk1_in : signal is "xilinx.com:interface:pipe_clock:1.0 pipe_clock userclk1_in"; + attribute X_INTERFACE_INFO of pipe_userclk2_in : signal is "xilinx.com:interface:pipe_clock:1.0 pipe_clock userclk2_in"; + attribute X_INTERFACE_INFO of pl_directed_change_done : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_change_done"; + attribute X_INTERFACE_INFO of pl_directed_link_auton : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_auton"; + attribute X_INTERFACE_INFO of pl_directed_link_speed : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_speed"; + attribute X_INTERFACE_INFO of pl_downstream_deemph_source : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl downstream_deemph_source"; + attribute X_INTERFACE_INFO of pl_link_gen2_cap : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_gen2_cap"; + attribute X_INTERFACE_INFO of pl_link_partner_gen2_supported : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_partner_gen2_supported"; + attribute X_INTERFACE_INFO of pl_link_upcfg_cap : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_upcfg_cap"; + attribute X_INTERFACE_INFO of pl_phy_lnk_up : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl phy_lnk_up"; + attribute X_INTERFACE_INFO of pl_received_hot_rst : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl received_hot_rst"; + attribute X_INTERFACE_INFO of pl_sel_lnk_rate : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_rate"; + attribute X_INTERFACE_INFO of pl_transmit_hot_rst : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl transmit_hot_rst"; + attribute X_INTERFACE_INFO of pl_upstream_prefer_deemph : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl upstream_prefer_deemph"; + attribute X_INTERFACE_INFO of rx_np_ok : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_ok"; + attribute X_INTERFACE_INFO of rx_np_req : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_req"; + attribute X_INTERFACE_INFO of s_axis_tx_tlast : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TLAST"; + attribute X_INTERFACE_INFO of s_axis_tx_tready : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TREADY"; + attribute X_INTERFACE_INFO of s_axis_tx_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TVALID"; + attribute X_INTERFACE_INFO of sys_clk : signal is "xilinx.com:signal:clock:1.0 CLK.sys_clk CLK"; + attribute X_INTERFACE_PARAMETER : string; + attribute X_INTERFACE_PARAMETER of sys_clk : signal is "XIL_INTERFACENAME CLK.sys_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of sys_rst_n : signal is "xilinx.com:signal:reset:1.0 RST.sys_rst_n RST"; + attribute X_INTERFACE_PARAMETER of sys_rst_n : signal is "XIL_INTERFACENAME RST.sys_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of tx_cfg_gnt : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control tx_cfg_gnt"; + attribute X_INTERFACE_INFO of tx_cfg_req : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_cfg_req"; + attribute X_INTERFACE_INFO of tx_err_drop : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_err_drop"; + attribute X_INTERFACE_INFO of user_clk_out : signal is "xilinx.com:signal:clock:1.0 CLK.user_clk_out CLK"; + attribute X_INTERFACE_PARAMETER of user_clk_out : signal is "XIL_INTERFACENAME CLK.user_clk_out, ASSOCIATED_BUSIF m_axis_rx:s_axis_tx, FREQ_HZ 125000000, ASSOCIATED_RESET user_reset_out, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of user_reset_out : signal is "xilinx.com:signal:reset:1.0 RST.user_reset_out RST"; + attribute X_INTERFACE_PARAMETER of user_reset_out : signal is "XIL_INTERFACENAME RST.user_reset_out, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of cfg_aer_interrupt_msgnum : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_interrupt_msgnum"; + attribute X_INTERFACE_INFO of cfg_bus_number : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bus_number"; + attribute X_INTERFACE_INFO of cfg_command : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status command"; + attribute X_INTERFACE_INFO of cfg_dcommand : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand"; + attribute X_INTERFACE_INFO of cfg_dcommand2 : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand2"; + attribute X_INTERFACE_INFO of cfg_device_number : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status device_number"; + attribute X_INTERFACE_INFO of cfg_ds_bus_number : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_bus_number"; + attribute X_INTERFACE_INFO of cfg_ds_device_number : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_device_number"; + attribute X_INTERFACE_INFO of cfg_ds_function_number : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_function_number"; + attribute X_INTERFACE_INFO of cfg_dsn : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control dsn"; + attribute X_INTERFACE_INFO of cfg_dstatus : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dstatus"; + attribute X_INTERFACE_INFO of cfg_err_aer_headerlog : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog"; + attribute X_INTERFACE_INFO of cfg_err_tlp_cpl_header : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err tlp_cpl_header"; + attribute X_INTERFACE_INFO of cfg_function_number : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status function_number"; + attribute X_INTERFACE_INFO of cfg_interrupt_di : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt write_data"; + attribute X_INTERFACE_INFO of cfg_interrupt_do : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt read_data"; + attribute X_INTERFACE_INFO of cfg_interrupt_mmenable : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt mmenable"; + attribute X_INTERFACE_INFO of cfg_lcommand : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lcommand"; + attribute X_INTERFACE_INFO of cfg_lstatus : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lstatus"; + attribute X_INTERFACE_INFO of cfg_mgmt_byte_en : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt BYTE_EN"; + attribute X_INTERFACE_INFO of cfg_mgmt_di : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_DATA"; + attribute X_INTERFACE_INFO of cfg_mgmt_do : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_DATA"; + attribute X_INTERFACE_INFO of cfg_mgmt_dwaddr : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt ADDR"; + attribute X_INTERFACE_INFO of cfg_msg_data : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd data"; + attribute X_INTERFACE_INFO of cfg_pcie_link_state : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pcie_link_state"; + attribute X_INTERFACE_INFO of cfg_pciecap_interrupt_msgnum : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt pciecap_interrupt_msgnum"; + attribute X_INTERFACE_INFO of cfg_pm_force_state : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state"; + attribute X_INTERFACE_INFO of cfg_pmcsr_powerstate : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_powerstate"; + attribute X_INTERFACE_INFO of cfg_status : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status status"; + attribute X_INTERFACE_INFO of cfg_vc_tcvc_map : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status vc_tcvc_map"; + attribute X_INTERFACE_INFO of fc_cpld : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLD"; + attribute X_INTERFACE_INFO of fc_cplh : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLH"; + attribute X_INTERFACE_INFO of fc_npd : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPD"; + attribute X_INTERFACE_INFO of fc_nph : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPH"; + attribute X_INTERFACE_INFO of fc_pd : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PD"; + attribute X_INTERFACE_INFO of fc_ph : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PH"; + attribute X_INTERFACE_INFO of fc_sel : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc SEL"; + attribute X_INTERFACE_INFO of m_axis_rx_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TDATA"; + attribute X_INTERFACE_INFO of m_axis_rx_tkeep : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TKEEP"; + attribute X_INTERFACE_INFO of m_axis_rx_tuser : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TUSER"; + attribute X_INTERFACE_PARAMETER of m_axis_rx_tuser : signal is "XIL_INTERFACENAME m_axis_rx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of pci_exp_rxn : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxn"; + attribute X_INTERFACE_INFO of pci_exp_rxp : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxp"; + attribute X_INTERFACE_INFO of pci_exp_txn : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txn"; + attribute X_INTERFACE_INFO of pci_exp_txp : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txp"; + attribute X_INTERFACE_INFO of pcie_drp_addr : signal is "xilinx.com:interface:drp:1.0 drp DADDR"; + attribute X_INTERFACE_INFO of pcie_drp_di : signal is "xilinx.com:interface:drp:1.0 drp DI"; + attribute X_INTERFACE_INFO of pcie_drp_do : signal is "xilinx.com:interface:drp:1.0 drp DO"; + attribute X_INTERFACE_INFO of pipe_pclk_sel_out : signal is "xilinx.com:interface:pipe_clock:1.0 pipe_clock pclk_sel_out"; + attribute X_INTERFACE_INFO of pipe_rxoutclk_in : signal is "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxoutclk_in"; + attribute X_INTERFACE_INFO of pipe_rxoutclk_out : signal is "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxoutclk_out"; + attribute X_INTERFACE_INFO of pl_directed_link_change : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_change"; + attribute X_INTERFACE_INFO of pl_directed_link_width : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_width"; + attribute X_INTERFACE_INFO of pl_initial_link_width : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl initial_link_width"; + attribute X_INTERFACE_INFO of pl_lane_reversal_mode : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl lane_reversal_mode"; + attribute X_INTERFACE_INFO of pl_ltssm_state : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl ltssm_state"; + attribute X_INTERFACE_INFO of pl_rx_pm_state : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl rx_pm_state"; + attribute X_INTERFACE_INFO of pl_sel_lnk_width : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_width"; + attribute X_INTERFACE_INFO of pl_tx_pm_state : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl tx_pm_state"; + attribute X_INTERFACE_INFO of s_axis_tx_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TDATA"; + attribute X_INTERFACE_INFO of s_axis_tx_tkeep : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TKEEP"; + attribute X_INTERFACE_INFO of s_axis_tx_tuser : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TUSER"; + attribute X_INTERFACE_PARAMETER of s_axis_tx_tuser : signal is "XIL_INTERFACENAME s_axis_tx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of tx_buf_av : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_buf_av"; +begin + cfg_command(15) <= \\; + cfg_command(14) <= \\; + cfg_command(13) <= \\; + cfg_command(12) <= \\; + cfg_command(11) <= \\; + cfg_command(10) <= \^cfg_command\(10); + cfg_command(9) <= \\; + cfg_command(8) <= \^cfg_command\(8); + cfg_command(7) <= \\; + cfg_command(6) <= \\; + cfg_command(5) <= \\; + cfg_command(4) <= \\; + cfg_command(3) <= \\; + cfg_command(2 downto 0) <= \^cfg_command\(2 downto 0); + cfg_dcommand(15) <= \\; + cfg_dcommand(14 downto 0) <= \^cfg_dcommand\(14 downto 0); + cfg_dcommand2(15) <= \\; + cfg_dcommand2(14) <= \\; + cfg_dcommand2(13) <= \\; + cfg_dcommand2(12) <= \\; + cfg_dcommand2(11 downto 0) <= \^cfg_dcommand2\(11 downto 0); + cfg_dstatus(15) <= \\; + cfg_dstatus(14) <= \\; + cfg_dstatus(13) <= \\; + cfg_dstatus(12) <= \\; + cfg_dstatus(11) <= \\; + cfg_dstatus(10) <= \\; + cfg_dstatus(9) <= \\; + cfg_dstatus(8) <= \\; + cfg_dstatus(7) <= \\; + cfg_dstatus(6) <= \\; + cfg_dstatus(5) <= \^cfg_dstatus\(5); + cfg_dstatus(4) <= \\; + cfg_dstatus(3 downto 0) <= \^cfg_dstatus\(3 downto 0); + cfg_lcommand(15) <= \\; + cfg_lcommand(14) <= \\; + cfg_lcommand(13) <= \\; + cfg_lcommand(12) <= \\; + cfg_lcommand(11 downto 3) <= \^cfg_lcommand\(11 downto 3); + cfg_lcommand(2) <= \\; + cfg_lcommand(1 downto 0) <= \^cfg_lcommand\(1 downto 0); + cfg_lstatus(15 downto 13) <= \^cfg_lstatus\(15 downto 13); + cfg_lstatus(12) <= \\; + cfg_lstatus(11) <= \^cfg_lstatus\(11); + cfg_lstatus(10) <= \\; + cfg_lstatus(9) <= \\; + cfg_lstatus(8) <= \\; + cfg_lstatus(7 downto 4) <= \^cfg_lstatus\(7 downto 4); + cfg_lstatus(3) <= \\; + cfg_lstatus(2) <= \\; + cfg_lstatus(1 downto 0) <= \^cfg_lstatus\(1 downto 0); + cfg_status(15) <= \\; + cfg_status(14) <= \\; + cfg_status(13) <= \\; + cfg_status(12) <= \\; + cfg_status(11) <= \\; + cfg_status(10) <= \\; + cfg_status(9) <= \\; + cfg_status(8) <= \\; + cfg_status(7) <= \\; + cfg_status(6) <= \\; + cfg_status(5) <= \\; + cfg_status(4) <= \\; + cfg_status(3) <= \\; + cfg_status(2) <= \\; + cfg_status(1) <= \\; + cfg_status(0) <= \\; + m_axis_rx_tkeep(7 downto 4) <= \^m_axis_rx_tkeep\(7 downto 4); + m_axis_rx_tkeep(3) <= \\; + m_axis_rx_tkeep(2) <= \\; + m_axis_rx_tkeep(1) <= \\; + m_axis_rx_tkeep(0) <= \\; + m_axis_rx_tuser(21) <= \^m_axis_rx_tuser\(21); + m_axis_rx_tuser(20) <= \\; + m_axis_rx_tuser(19 downto 17) <= \^m_axis_rx_tuser\(19 downto 17); + m_axis_rx_tuser(16) <= \\; + m_axis_rx_tuser(15) <= \\; + m_axis_rx_tuser(14) <= \^m_axis_rx_tuser\(14); + m_axis_rx_tuser(13) <= \\; + m_axis_rx_tuser(12) <= \\; + m_axis_rx_tuser(11) <= \\; + m_axis_rx_tuser(10) <= \\; + m_axis_rx_tuser(9) <= \\; + m_axis_rx_tuser(8 downto 0) <= \^m_axis_rx_tuser\(8 downto 0); + user_app_rdy <= \\; +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +VCC: unisim.vcomponents.VCC + port map ( + P => \\ + ); +inst: entity work.pcie_7x_0_pcie_7x_0_pcie2_top + port map ( + cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en, + cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en, + cfg_aer_interrupt_msgnum(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0), + cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received, + cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en, + cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received, + cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en, + cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received, + cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en, + cfg_bridge_serr_en => cfg_bridge_serr_en, + cfg_bus_number(7 downto 0) => cfg_bus_number(7 downto 0), + cfg_command(15 downto 11) => NLW_inst_cfg_command_UNCONNECTED(15 downto 11), + cfg_command(10) => \^cfg_command\(10), + cfg_command(9) => NLW_inst_cfg_command_UNCONNECTED(9), + cfg_command(8) => \^cfg_command\(8), + cfg_command(7 downto 3) => NLW_inst_cfg_command_UNCONNECTED(7 downto 3), + cfg_command(2 downto 0) => \^cfg_command\(2 downto 0), + cfg_dcommand(15) => NLW_inst_cfg_dcommand_UNCONNECTED(15), + cfg_dcommand(14 downto 0) => \^cfg_dcommand\(14 downto 0), + cfg_dcommand2(15 downto 12) => NLW_inst_cfg_dcommand2_UNCONNECTED(15 downto 12), + cfg_dcommand2(11 downto 0) => \^cfg_dcommand2\(11 downto 0), + cfg_device_number(4 downto 0) => cfg_device_number(4 downto 0), + cfg_ds_bus_number(7 downto 0) => cfg_ds_bus_number(7 downto 0), + cfg_ds_device_number(4 downto 0) => cfg_ds_device_number(4 downto 0), + cfg_ds_function_number(2 downto 0) => cfg_ds_function_number(2 downto 0), + cfg_dsn(63 downto 0) => cfg_dsn(63 downto 0), + cfg_dstatus(15 downto 6) => NLW_inst_cfg_dstatus_UNCONNECTED(15 downto 6), + cfg_dstatus(5) => \^cfg_dstatus\(5), + cfg_dstatus(4) => NLW_inst_cfg_dstatus_UNCONNECTED(4), + cfg_dstatus(3 downto 0) => \^cfg_dstatus\(3 downto 0), + cfg_err_acs => '0', + cfg_err_aer_headerlog(127 downto 0) => cfg_err_aer_headerlog(127 downto 0), + cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set, + cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked, + cfg_err_cor => cfg_err_cor, + cfg_err_cpl_abort => cfg_err_cpl_abort, + cfg_err_cpl_rdy => cfg_err_cpl_rdy, + cfg_err_cpl_timeout => cfg_err_cpl_timeout, + cfg_err_cpl_unexpect => cfg_err_cpl_unexpect, + cfg_err_ecrc => cfg_err_ecrc, + cfg_err_internal_cor => cfg_err_internal_cor, + cfg_err_internal_uncor => cfg_err_internal_uncor, + cfg_err_locked => cfg_err_locked, + cfg_err_malformed => cfg_err_malformed, + cfg_err_mc_blocked => cfg_err_mc_blocked, + cfg_err_norecovery => cfg_err_norecovery, + cfg_err_poisoned => cfg_err_poisoned, + cfg_err_posted => cfg_err_posted, + cfg_err_tlp_cpl_header(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0), + cfg_err_ur => cfg_err_ur, + cfg_function_number(2 downto 0) => cfg_function_number(2 downto 0), + cfg_interrupt => cfg_interrupt, + cfg_interrupt_assert => cfg_interrupt_assert, + cfg_interrupt_di(7 downto 0) => cfg_interrupt_di(7 downto 0), + cfg_interrupt_do(7 downto 0) => cfg_interrupt_do(7 downto 0), + cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0), + cfg_interrupt_msienable => cfg_interrupt_msienable, + cfg_interrupt_msixenable => cfg_interrupt_msixenable, + cfg_interrupt_msixfm => cfg_interrupt_msixfm, + cfg_interrupt_rdy => cfg_interrupt_rdy, + cfg_interrupt_stat => cfg_interrupt_stat, + cfg_lcommand(15 downto 12) => NLW_inst_cfg_lcommand_UNCONNECTED(15 downto 12), + cfg_lcommand(11 downto 3) => \^cfg_lcommand\(11 downto 3), + cfg_lcommand(2) => NLW_inst_cfg_lcommand_UNCONNECTED(2), + cfg_lcommand(1 downto 0) => \^cfg_lcommand\(1 downto 0), + cfg_lstatus(15 downto 13) => \^cfg_lstatus\(15 downto 13), + cfg_lstatus(12) => NLW_inst_cfg_lstatus_UNCONNECTED(12), + cfg_lstatus(11) => \^cfg_lstatus\(11), + cfg_lstatus(10 downto 8) => NLW_inst_cfg_lstatus_UNCONNECTED(10 downto 8), + cfg_lstatus(7 downto 4) => \^cfg_lstatus\(7 downto 4), + cfg_lstatus(3 downto 2) => NLW_inst_cfg_lstatus_UNCONNECTED(3 downto 2), + cfg_lstatus(1 downto 0) => \^cfg_lstatus\(1 downto 0), + cfg_mgmt_byte_en(3 downto 0) => cfg_mgmt_byte_en(3 downto 0), + cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0), + cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0), + cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0), + cfg_mgmt_rd_en => cfg_mgmt_rd_en, + cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done, + cfg_mgmt_wr_en => cfg_mgmt_wr_en, + cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly, + cfg_mgmt_wr_rw1c_as_rw => cfg_mgmt_wr_rw1c_as_rw, + cfg_msg_data(15 downto 0) => cfg_msg_data(15 downto 0), + cfg_msg_received => cfg_msg_received, + cfg_msg_received_assert_int_a => cfg_msg_received_assert_int_a, + cfg_msg_received_assert_int_b => cfg_msg_received_assert_int_b, + cfg_msg_received_assert_int_c => cfg_msg_received_assert_int_c, + cfg_msg_received_assert_int_d => cfg_msg_received_assert_int_d, + cfg_msg_received_deassert_int_a => cfg_msg_received_deassert_int_a, + cfg_msg_received_deassert_int_b => cfg_msg_received_deassert_int_b, + cfg_msg_received_deassert_int_c => cfg_msg_received_deassert_int_c, + cfg_msg_received_deassert_int_d => cfg_msg_received_deassert_int_d, + cfg_msg_received_err_cor => cfg_msg_received_err_cor, + cfg_msg_received_err_fatal => cfg_msg_received_err_fatal, + cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal, + cfg_msg_received_pm_as_nak => cfg_msg_received_pm_as_nak, + cfg_msg_received_pm_pme => cfg_msg_received_pm_pme, + cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack, + cfg_msg_received_setslotpowerlimit => cfg_msg_received_setslotpowerlimit, + cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0), + cfg_pciecap_interrupt_msgnum(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0), + cfg_pm_force_state(1 downto 0) => cfg_pm_force_state(1 downto 0), + cfg_pm_force_state_en => cfg_pm_force_state_en, + cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s, + cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1, + cfg_pm_send_pme_to => '0', + cfg_pm_wake => cfg_pm_wake, + cfg_pmcsr_pme_en => cfg_pmcsr_pme_en, + cfg_pmcsr_pme_status => cfg_pmcsr_pme_status, + cfg_pmcsr_powerstate(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0), + cfg_received_func_lvl_rst => cfg_received_func_lvl_rst, + cfg_root_control_pme_int_en => cfg_root_control_pme_int_en, + cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en, + cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en, + cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en, + cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse, + cfg_status(15 downto 0) => NLW_inst_cfg_status_UNCONNECTED(15 downto 0), + cfg_to_turnoff => cfg_to_turnoff, + cfg_trn_pending => cfg_trn_pending, + cfg_turnoff_ok => cfg_turnoff_ok, + cfg_vc_tcvc_map(6 downto 0) => cfg_vc_tcvc_map(6 downto 0), + common_commands_in(11 downto 0) => B"000000000000", + common_commands_out(11 downto 0) => NLW_inst_common_commands_out_UNCONNECTED(11 downto 0), + ext_ch_gt_drpaddr(35 downto 0) => B"000000000000000000000000000000000000", + ext_ch_gt_drpclk => NLW_inst_ext_ch_gt_drpclk_UNCONNECTED, + ext_ch_gt_drpdi(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + ext_ch_gt_drpdo(63 downto 0) => NLW_inst_ext_ch_gt_drpdo_UNCONNECTED(63 downto 0), + ext_ch_gt_drpen(3 downto 0) => B"0000", + ext_ch_gt_drprdy(3 downto 0) => NLW_inst_ext_ch_gt_drprdy_UNCONNECTED(3 downto 0), + ext_ch_gt_drpwe(3 downto 0) => B"0000", + fc_cpld(11 downto 0) => fc_cpld(11 downto 0), + fc_cplh(7 downto 0) => fc_cplh(7 downto 0), + fc_npd(11 downto 0) => fc_npd(11 downto 0), + fc_nph(7 downto 0) => fc_nph(7 downto 0), + fc_pd(11 downto 0) => fc_pd(11 downto 0), + fc_ph(7 downto 0) => fc_ph(7 downto 0), + fc_sel(2 downto 0) => fc_sel(2 downto 0), + gt_ch_drp_rdy(3 downto 0) => NLW_inst_gt_ch_drp_rdy_UNCONNECTED(3 downto 0), + icap_clk => '0', + icap_csib => '0', + icap_i(31 downto 0) => B"00000000000000000000000000000000", + icap_o(31 downto 0) => NLW_inst_icap_o_UNCONNECTED(31 downto 0), + icap_rdwrb => '0', + int_dclk_out => NLW_inst_int_dclk_out_UNCONNECTED, + int_mmcm_lock_out => NLW_inst_int_mmcm_lock_out_UNCONNECTED, + int_oobclk_out => NLW_inst_int_oobclk_out_UNCONNECTED, + int_pclk_out_slave => NLW_inst_int_pclk_out_slave_UNCONNECTED, + int_pclk_sel_slave(3 downto 0) => B"0000", + int_pipe_rxusrclk_out => NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED, + int_qplllock_out(1 downto 0) => NLW_inst_int_qplllock_out_UNCONNECTED(1 downto 0), + int_qplloutclk_out(1 downto 0) => NLW_inst_int_qplloutclk_out_UNCONNECTED(1 downto 0), + int_qplloutrefclk_out(1 downto 0) => NLW_inst_int_qplloutrefclk_out_UNCONNECTED(1 downto 0), + int_rxoutclk_out(3 downto 0) => NLW_inst_int_rxoutclk_out_UNCONNECTED(3 downto 0), + int_userclk1_out => NLW_inst_int_userclk1_out_UNCONNECTED, + int_userclk2_out => NLW_inst_int_userclk2_out_UNCONNECTED, + m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0), + m_axis_rx_tkeep(7 downto 4) => \^m_axis_rx_tkeep\(7 downto 4), + m_axis_rx_tkeep(3 downto 0) => NLW_inst_m_axis_rx_tkeep_UNCONNECTED(3 downto 0), + m_axis_rx_tlast => m_axis_rx_tlast, + m_axis_rx_tready => m_axis_rx_tready, + m_axis_rx_tuser(21) => \^m_axis_rx_tuser\(21), + m_axis_rx_tuser(20) => NLW_inst_m_axis_rx_tuser_UNCONNECTED(20), + m_axis_rx_tuser(19 downto 17) => \^m_axis_rx_tuser\(19 downto 17), + m_axis_rx_tuser(16 downto 15) => NLW_inst_m_axis_rx_tuser_UNCONNECTED(16 downto 15), + m_axis_rx_tuser(14) => \^m_axis_rx_tuser\(14), + m_axis_rx_tuser(13 downto 9) => NLW_inst_m_axis_rx_tuser_UNCONNECTED(13 downto 9), + m_axis_rx_tuser(8 downto 0) => \^m_axis_rx_tuser\(8 downto 0), + m_axis_rx_tvalid => m_axis_rx_tvalid, + pci_exp_rxn(3 downto 0) => pci_exp_rxn(3 downto 0), + pci_exp_rxp(3 downto 0) => pci_exp_rxp(3 downto 0), + pci_exp_txn(3 downto 0) => pci_exp_txn(3 downto 0), + pci_exp_txp(3 downto 0) => pci_exp_txp(3 downto 0), + pcie_drp_addr(8 downto 0) => pcie_drp_addr(8 downto 0), + pcie_drp_clk => pcie_drp_clk, + pcie_drp_di(15 downto 0) => pcie_drp_di(15 downto 0), + pcie_drp_do(15 downto 0) => pcie_drp_do(15 downto 0), + pcie_drp_en => pcie_drp_en, + pcie_drp_rdy => pcie_drp_rdy, + pcie_drp_we => pcie_drp_we, + pipe_cpll_lock(3 downto 0) => NLW_inst_pipe_cpll_lock_UNCONNECTED(3 downto 0), + pipe_dclk_in => pipe_dclk_in, + pipe_debug(31 downto 0) => NLW_inst_pipe_debug_UNCONNECTED(31 downto 0), + pipe_debug_0(3 downto 0) => NLW_inst_pipe_debug_0_UNCONNECTED(3 downto 0), + pipe_debug_1(3 downto 0) => NLW_inst_pipe_debug_1_UNCONNECTED(3 downto 0), + pipe_debug_2(3 downto 0) => NLW_inst_pipe_debug_2_UNCONNECTED(3 downto 0), + pipe_debug_3(3 downto 0) => NLW_inst_pipe_debug_3_UNCONNECTED(3 downto 0), + pipe_debug_4(3 downto 0) => NLW_inst_pipe_debug_4_UNCONNECTED(3 downto 0), + pipe_debug_5(3 downto 0) => NLW_inst_pipe_debug_5_UNCONNECTED(3 downto 0), + pipe_debug_6(3 downto 0) => NLW_inst_pipe_debug_6_UNCONNECTED(3 downto 0), + pipe_debug_7(3 downto 0) => NLW_inst_pipe_debug_7_UNCONNECTED(3 downto 0), + pipe_debug_8(3 downto 0) => NLW_inst_pipe_debug_8_UNCONNECTED(3 downto 0), + pipe_debug_9(3 downto 0) => NLW_inst_pipe_debug_9_UNCONNECTED(3 downto 0), + pipe_dmonitorout(59 downto 0) => NLW_inst_pipe_dmonitorout_UNCONNECTED(59 downto 0), + pipe_drp_fsm(27 downto 0) => NLW_inst_pipe_drp_fsm_UNCONNECTED(27 downto 0), + pipe_eyescandataerror(3 downto 0) => NLW_inst_pipe_eyescandataerror_UNCONNECTED(3 downto 0), + pipe_gen3_out => pipe_gen3_out, + pipe_loopback(2 downto 0) => B"000", + pipe_mmcm_lock_in => pipe_mmcm_lock_in, + pipe_mmcm_rst_n => '0', + pipe_oobclk_in => pipe_oobclk_in, + pipe_pclk_in => pipe_pclk_in, + pipe_pclk_sel_out(3 downto 0) => pipe_pclk_sel_out(3 downto 0), + pipe_qpll_lock(0) => NLW_inst_pipe_qpll_lock_UNCONNECTED(0), + pipe_qrst_fsm(11 downto 0) => NLW_inst_pipe_qrst_fsm_UNCONNECTED(11 downto 0), + pipe_qrst_idle => NLW_inst_pipe_qrst_idle_UNCONNECTED, + pipe_rate_fsm(19 downto 0) => NLW_inst_pipe_rate_fsm_UNCONNECTED(19 downto 0), + pipe_rate_idle => NLW_inst_pipe_rate_idle_UNCONNECTED, + pipe_rst_fsm(4 downto 0) => NLW_inst_pipe_rst_fsm_UNCONNECTED(4 downto 0), + pipe_rst_idle => NLW_inst_pipe_rst_idle_UNCONNECTED, + pipe_rx_0_sigs(24 downto 0) => B"0000000000000000000000000", + pipe_rx_1_sigs(24 downto 0) => B"0000000000000000000000000", + pipe_rx_2_sigs(24 downto 0) => B"0000000000000000000000000", + pipe_rx_3_sigs(24 downto 0) => B"0000000000000000000000000", + pipe_rx_4_sigs(24 downto 0) => B"0000000000000000000000000", + pipe_rx_5_sigs(24 downto 0) => B"0000000000000000000000000", + pipe_rx_6_sigs(24 downto 0) => B"0000000000000000000000000", + pipe_rx_7_sigs(24 downto 0) => B"0000000000000000000000000", + pipe_rxbufstatus(11 downto 0) => NLW_inst_pipe_rxbufstatus_UNCONNECTED(11 downto 0), + pipe_rxcommadet(3 downto 0) => NLW_inst_pipe_rxcommadet_UNCONNECTED(3 downto 0), + pipe_rxdisperr(31 downto 0) => NLW_inst_pipe_rxdisperr_UNCONNECTED(31 downto 0), + pipe_rxdlysresetdone(3 downto 0) => NLW_inst_pipe_rxdlysresetdone_UNCONNECTED(3 downto 0), + pipe_rxnotintable(31 downto 0) => NLW_inst_pipe_rxnotintable_UNCONNECTED(31 downto 0), + pipe_rxoutclk_in(3 downto 0) => B"0000", + pipe_rxoutclk_out(3 downto 0) => pipe_rxoutclk_out(3 downto 0), + pipe_rxphaligndone(3 downto 0) => NLW_inst_pipe_rxphaligndone_UNCONNECTED(3 downto 0), + pipe_rxpmaresetdone(3 downto 0) => NLW_inst_pipe_rxpmaresetdone_UNCONNECTED(3 downto 0), + pipe_rxprbscntreset => '0', + pipe_rxprbserr(3 downto 0) => NLW_inst_pipe_rxprbserr_UNCONNECTED(3 downto 0), + pipe_rxprbssel(2 downto 0) => B"000", + pipe_rxstatus(11 downto 0) => NLW_inst_pipe_rxstatus_UNCONNECTED(11 downto 0), + pipe_rxsyncdone(3 downto 0) => NLW_inst_pipe_rxsyncdone_UNCONNECTED(3 downto 0), + pipe_rxusrclk_in => pipe_rxusrclk_in, + pipe_sync_fsm_rx(27 downto 0) => NLW_inst_pipe_sync_fsm_rx_UNCONNECTED(27 downto 0), + pipe_sync_fsm_tx(23 downto 0) => NLW_inst_pipe_sync_fsm_tx_UNCONNECTED(23 downto 0), + pipe_tx_0_sigs(24 downto 0) => NLW_inst_pipe_tx_0_sigs_UNCONNECTED(24 downto 0), + pipe_tx_1_sigs(24 downto 0) => NLW_inst_pipe_tx_1_sigs_UNCONNECTED(24 downto 0), + pipe_tx_2_sigs(24 downto 0) => NLW_inst_pipe_tx_2_sigs_UNCONNECTED(24 downto 0), + pipe_tx_3_sigs(24 downto 0) => NLW_inst_pipe_tx_3_sigs_UNCONNECTED(24 downto 0), + pipe_tx_4_sigs(24 downto 0) => NLW_inst_pipe_tx_4_sigs_UNCONNECTED(24 downto 0), + pipe_tx_5_sigs(24 downto 0) => NLW_inst_pipe_tx_5_sigs_UNCONNECTED(24 downto 0), + pipe_tx_6_sigs(24 downto 0) => NLW_inst_pipe_tx_6_sigs_UNCONNECTED(24 downto 0), + pipe_tx_7_sigs(24 downto 0) => NLW_inst_pipe_tx_7_sigs_UNCONNECTED(24 downto 0), + pipe_txdlysresetdone(3 downto 0) => NLW_inst_pipe_txdlysresetdone_UNCONNECTED(3 downto 0), + pipe_txinhibit(3 downto 0) => B"0000", + pipe_txoutclk_out => pipe_txoutclk_out, + pipe_txphaligndone(3 downto 0) => NLW_inst_pipe_txphaligndone_UNCONNECTED(3 downto 0), + pipe_txphinitdone(3 downto 0) => NLW_inst_pipe_txphinitdone_UNCONNECTED(3 downto 0), + pipe_txprbsforceerr => '0', + pipe_txprbssel(2 downto 0) => B"000", + pipe_userclk1_in => pipe_userclk1_in, + pipe_userclk2_in => pipe_userclk2_in, + pl_directed_change_done => pl_directed_change_done, + pl_directed_link_auton => pl_directed_link_auton, + pl_directed_link_change(1 downto 0) => pl_directed_link_change(1 downto 0), + pl_directed_link_speed => pl_directed_link_speed, + pl_directed_link_width(1 downto 0) => pl_directed_link_width(1 downto 0), + pl_downstream_deemph_source => pl_downstream_deemph_source, + pl_initial_link_width(2 downto 0) => pl_initial_link_width(2 downto 0), + pl_lane_reversal_mode(1 downto 0) => pl_lane_reversal_mode(1 downto 0), + pl_link_gen2_cap => pl_link_gen2_cap, + pl_link_partner_gen2_supported => pl_link_partner_gen2_supported, + pl_link_upcfg_cap => pl_link_upcfg_cap, + pl_ltssm_state(5 downto 0) => pl_ltssm_state(5 downto 0), + pl_phy_lnk_up => pl_phy_lnk_up, + pl_received_hot_rst => pl_received_hot_rst, + pl_rx_pm_state(1 downto 0) => pl_rx_pm_state(1 downto 0), + pl_sel_lnk_rate => pl_sel_lnk_rate, + pl_sel_lnk_width(1 downto 0) => pl_sel_lnk_width(1 downto 0), + pl_transmit_hot_rst => pl_transmit_hot_rst, + pl_tx_pm_state(2 downto 0) => pl_tx_pm_state(2 downto 0), + pl_upstream_prefer_deemph => pl_upstream_prefer_deemph, + qpll_drp_clk => NLW_inst_qpll_drp_clk_UNCONNECTED, + qpll_drp_crscode(11 downto 0) => B"000000000000", + qpll_drp_done(1 downto 0) => B"00", + qpll_drp_fsm(17 downto 0) => B"000000000000000000", + qpll_drp_gen3 => NLW_inst_qpll_drp_gen3_UNCONNECTED, + qpll_drp_ovrd => NLW_inst_qpll_drp_ovrd_UNCONNECTED, + qpll_drp_reset(1 downto 0) => B"00", + qpll_drp_rst_n => NLW_inst_qpll_drp_rst_n_UNCONNECTED, + qpll_drp_start => NLW_inst_qpll_drp_start_UNCONNECTED, + qpll_qplld => NLW_inst_qpll_qplld_UNCONNECTED, + qpll_qplllock(1 downto 0) => B"00", + qpll_qplloutclk(1 downto 0) => B"00", + qpll_qplloutrefclk(1 downto 0) => B"00", + qpll_qpllreset(1 downto 0) => NLW_inst_qpll_qpllreset_UNCONNECTED(1 downto 0), + rx_np_ok => rx_np_ok, + rx_np_req => rx_np_req, + s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0), + s_axis_tx_tkeep(7) => s_axis_tx_tkeep(7), + s_axis_tx_tkeep(6 downto 0) => B"0000000", + s_axis_tx_tlast => s_axis_tx_tlast, + s_axis_tx_tready => s_axis_tx_tready, + s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0), + s_axis_tx_tvalid => s_axis_tx_tvalid, + startup_cfgclk => NLW_inst_startup_cfgclk_UNCONNECTED, + startup_cfgmclk => NLW_inst_startup_cfgmclk_UNCONNECTED, + startup_clk => '0', + startup_eos => NLW_inst_startup_eos_UNCONNECTED, + startup_eos_in => '0', + startup_gsr => '0', + startup_gts => '0', + startup_keyclearb => '1', + startup_pack => '0', + startup_preq => NLW_inst_startup_preq_UNCONNECTED, + startup_usrcclko => '1', + startup_usrcclkts => '0', + startup_usrdoneo => '0', + startup_usrdonets => '1', + sys_clk => sys_clk, + sys_rst_n => sys_rst_n, + tx_buf_av(5 downto 0) => tx_buf_av(5 downto 0), + tx_cfg_gnt => tx_cfg_gnt, + tx_cfg_req => tx_cfg_req, + tx_err_drop => tx_err_drop, + user_app_rdy => NLW_inst_user_app_rdy_UNCONNECTED, + user_clk_out => user_clk_out, + user_lnk_up => user_lnk_up, + user_reset_out => user_reset_out + ); +end STRUCTURE; diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_stub.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_stub.v new file mode 100644 index 0000000..ba049d4 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_stub.v @@ -0,0 +1,241 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Wed Jul 20 13:38:01 2022 +// Host : DESKTOP-4NLVFC8 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top pcie_7x_0 -prefix +// pcie_7x_0_ pcie_7x_0_stub.v +// Design : pcie_7x_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z045ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "pcie_7x_0_pcie2_top,Vivado 2020.2" *) +module pcie_7x_0(pci_exp_txp, pci_exp_txn, pci_exp_rxp, + pci_exp_rxn, pipe_pclk_in, pipe_rxusrclk_in, pipe_rxoutclk_in, pipe_dclk_in, + pipe_userclk1_in, pipe_userclk2_in, pipe_oobclk_in, pipe_mmcm_lock_in, pipe_txoutclk_out, + pipe_rxoutclk_out, pipe_pclk_sel_out, pipe_gen3_out, user_clk_out, user_reset_out, + user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, + s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, + tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, + m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, + fc_ph, fc_sel, cfg_mgmt_do, cfg_mgmt_rd_wr_done, cfg_status, cfg_command, cfg_dstatus, + cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, + cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, + cfg_received_func_lvl_rst, cfg_mgmt_di, cfg_mgmt_byte_en, cfg_mgmt_dwaddr, + cfg_mgmt_wr_en, cfg_mgmt_rd_en, cfg_mgmt_wr_readonly, cfg_err_ecrc, cfg_err_ur, + cfg_err_cpl_timeout, cfg_err_cpl_unexpect, cfg_err_cpl_abort, cfg_err_posted, + cfg_err_cor, cfg_err_atomic_egress_blocked, cfg_err_internal_cor, cfg_err_malformed, + cfg_err_mc_blocked, cfg_err_poisoned, cfg_err_norecovery, cfg_err_tlp_cpl_header, + cfg_err_cpl_rdy, cfg_err_locked, cfg_err_acs, cfg_err_internal_uncor, cfg_trn_pending, + cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, + cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, + cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, + cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, + cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, + cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, + cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, + cfg_mgmt_wr_rw1c_as_rw, cfg_msg_received, cfg_msg_data, cfg_bridge_serr_en, + cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, + cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, + cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, + cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, + cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, + cfg_aer_rooterr_fatal_err_received, cfg_msg_received_err_cor, + cfg_msg_received_err_non_fatal, cfg_msg_received_err_fatal, + cfg_msg_received_pm_as_nak, cfg_msg_received_pm_pme, cfg_msg_received_pme_to_ack, + cfg_msg_received_assert_int_a, cfg_msg_received_assert_int_b, + cfg_msg_received_assert_int_c, cfg_msg_received_assert_int_d, + cfg_msg_received_deassert_int_a, cfg_msg_received_deassert_int_b, + cfg_msg_received_deassert_int_c, cfg_msg_received_deassert_int_d, + cfg_msg_received_setslotpowerlimit, pl_directed_link_change, pl_directed_link_width, + pl_directed_link_speed, pl_directed_link_auton, pl_upstream_prefer_deemph, + pl_sel_lnk_rate, pl_sel_lnk_width, pl_ltssm_state, pl_lane_reversal_mode, pl_phy_lnk_up, + pl_tx_pm_state, pl_rx_pm_state, pl_link_upcfg_cap, pl_link_gen2_cap, + pl_link_partner_gen2_supported, pl_initial_link_width, pl_directed_change_done, + pl_received_hot_rst, pl_transmit_hot_rst, pl_downstream_deemph_source, + cfg_err_aer_headerlog, cfg_aer_interrupt_msgnum, cfg_err_aer_headerlog_set, + cfg_aer_ecrc_check_en, cfg_aer_ecrc_gen_en, cfg_vc_tcvc_map, sys_clk, sys_rst_n, + pipe_mmcm_rst_n, pcie_drp_clk, pcie_drp_en, pcie_drp_we, pcie_drp_addr, pcie_drp_di, + pcie_drp_do, pcie_drp_rdy) +/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[3:0],pci_exp_txn[3:0],pci_exp_rxp[3:0],pci_exp_rxn[3:0],pipe_pclk_in,pipe_rxusrclk_in,pipe_rxoutclk_in[3:0],pipe_dclk_in,pipe_userclk1_in,pipe_userclk2_in,pipe_oobclk_in,pipe_mmcm_lock_in,pipe_txoutclk_out,pipe_rxoutclk_out[3:0],pipe_pclk_sel_out[3:0],pipe_gen3_out,user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[63:0],s_axis_tx_tkeep[7:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[63:0],m_axis_rx_tkeep[7:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_mgmt_do[31:0],cfg_mgmt_rd_wr_done,cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_mgmt_di[31:0],cfg_mgmt_byte_en[3:0],cfg_mgmt_dwaddr[9:0],cfg_mgmt_wr_en,cfg_mgmt_rd_en,cfg_mgmt_wr_readonly,cfg_err_ecrc,cfg_err_ur,cfg_err_cpl_timeout,cfg_err_cpl_unexpect,cfg_err_cpl_abort,cfg_err_posted,cfg_err_cor,cfg_err_atomic_egress_blocked,cfg_err_internal_cor,cfg_err_malformed,cfg_err_mc_blocked,cfg_err_poisoned,cfg_err_norecovery,cfg_err_tlp_cpl_header[47:0],cfg_err_cpl_rdy,cfg_err_locked,cfg_err_acs,cfg_err_internal_uncor,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_mgmt_wr_rw1c_as_rw,cfg_msg_received,cfg_msg_data[15:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_msg_received_err_cor,cfg_msg_received_err_non_fatal,cfg_msg_received_err_fatal,cfg_msg_received_pm_as_nak,cfg_msg_received_pm_pme,cfg_msg_received_pme_to_ack,cfg_msg_received_assert_int_a,cfg_msg_received_assert_int_b,cfg_msg_received_assert_int_c,cfg_msg_received_assert_int_d,cfg_msg_received_deassert_int_a,cfg_msg_received_deassert_int_b,cfg_msg_received_deassert_int_c,cfg_msg_received_deassert_int_d,cfg_msg_received_setslotpowerlimit,pl_directed_link_change[1:0],pl_directed_link_width[1:0],pl_directed_link_speed,pl_directed_link_auton,pl_upstream_prefer_deemph,pl_sel_lnk_rate,pl_sel_lnk_width[1:0],pl_ltssm_state[5:0],pl_lane_reversal_mode[1:0],pl_phy_lnk_up,pl_tx_pm_state[2:0],pl_rx_pm_state[1:0],pl_link_upcfg_cap,pl_link_gen2_cap,pl_link_partner_gen2_supported,pl_initial_link_width[2:0],pl_directed_change_done,pl_received_hot_rst,pl_transmit_hot_rst,pl_downstream_deemph_source,cfg_err_aer_headerlog[127:0],cfg_aer_interrupt_msgnum[4:0],cfg_err_aer_headerlog_set,cfg_aer_ecrc_check_en,cfg_aer_ecrc_gen_en,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n,pipe_mmcm_rst_n,pcie_drp_clk,pcie_drp_en,pcie_drp_we,pcie_drp_addr[8:0],pcie_drp_di[15:0],pcie_drp_do[15:0],pcie_drp_rdy" */; + output [3:0]pci_exp_txp; + output [3:0]pci_exp_txn; + input [3:0]pci_exp_rxp; + input [3:0]pci_exp_rxn; + input pipe_pclk_in; + input pipe_rxusrclk_in; + input [3:0]pipe_rxoutclk_in; + input pipe_dclk_in; + input pipe_userclk1_in; + input pipe_userclk2_in; + input pipe_oobclk_in; + input pipe_mmcm_lock_in; + output pipe_txoutclk_out; + output [3:0]pipe_rxoutclk_out; + output [3:0]pipe_pclk_sel_out; + output pipe_gen3_out; + output user_clk_out; + output user_reset_out; + output user_lnk_up; + output user_app_rdy; + output [5:0]tx_buf_av; + output tx_cfg_req; + output tx_err_drop; + output s_axis_tx_tready; + input [63:0]s_axis_tx_tdata; + input [7:0]s_axis_tx_tkeep; + input s_axis_tx_tlast; + input s_axis_tx_tvalid; + input [3:0]s_axis_tx_tuser; + input tx_cfg_gnt; + output [63:0]m_axis_rx_tdata; + output [7:0]m_axis_rx_tkeep; + output m_axis_rx_tlast; + output m_axis_rx_tvalid; + input m_axis_rx_tready; + output [21:0]m_axis_rx_tuser; + input rx_np_ok; + input rx_np_req; + output [11:0]fc_cpld; + output [7:0]fc_cplh; + output [11:0]fc_npd; + output [7:0]fc_nph; + output [11:0]fc_pd; + output [7:0]fc_ph; + input [2:0]fc_sel; + output [31:0]cfg_mgmt_do; + output cfg_mgmt_rd_wr_done; + output [15:0]cfg_status; + output [15:0]cfg_command; + output [15:0]cfg_dstatus; + output [15:0]cfg_dcommand; + output [15:0]cfg_lstatus; + output [15:0]cfg_lcommand; + output [15:0]cfg_dcommand2; + output [2:0]cfg_pcie_link_state; + output cfg_pmcsr_pme_en; + output [1:0]cfg_pmcsr_powerstate; + output cfg_pmcsr_pme_status; + output cfg_received_func_lvl_rst; + input [31:0]cfg_mgmt_di; + input [3:0]cfg_mgmt_byte_en; + input [9:0]cfg_mgmt_dwaddr; + input cfg_mgmt_wr_en; + input cfg_mgmt_rd_en; + input cfg_mgmt_wr_readonly; + input cfg_err_ecrc; + input cfg_err_ur; + input cfg_err_cpl_timeout; + input cfg_err_cpl_unexpect; + input cfg_err_cpl_abort; + input cfg_err_posted; + input cfg_err_cor; + input cfg_err_atomic_egress_blocked; + input cfg_err_internal_cor; + input cfg_err_malformed; + input cfg_err_mc_blocked; + input cfg_err_poisoned; + input cfg_err_norecovery; + input [47:0]cfg_err_tlp_cpl_header; + output cfg_err_cpl_rdy; + input cfg_err_locked; + input cfg_err_acs; + input cfg_err_internal_uncor; + input cfg_trn_pending; + input cfg_pm_halt_aspm_l0s; + input cfg_pm_halt_aspm_l1; + input cfg_pm_force_state_en; + input [1:0]cfg_pm_force_state; + input [63:0]cfg_dsn; + input cfg_interrupt; + output cfg_interrupt_rdy; + input cfg_interrupt_assert; + input [7:0]cfg_interrupt_di; + output [7:0]cfg_interrupt_do; + output [2:0]cfg_interrupt_mmenable; + output cfg_interrupt_msienable; + output cfg_interrupt_msixenable; + output cfg_interrupt_msixfm; + input cfg_interrupt_stat; + input [4:0]cfg_pciecap_interrupt_msgnum; + output cfg_to_turnoff; + input cfg_turnoff_ok; + output [7:0]cfg_bus_number; + output [4:0]cfg_device_number; + output [2:0]cfg_function_number; + input cfg_pm_wake; + input cfg_pm_send_pme_to; + input [7:0]cfg_ds_bus_number; + input [4:0]cfg_ds_device_number; + input [2:0]cfg_ds_function_number; + input cfg_mgmt_wr_rw1c_as_rw; + output cfg_msg_received; + output [15:0]cfg_msg_data; + output cfg_bridge_serr_en; + output cfg_slot_control_electromech_il_ctl_pulse; + output cfg_root_control_syserr_corr_err_en; + output cfg_root_control_syserr_non_fatal_err_en; + output cfg_root_control_syserr_fatal_err_en; + output cfg_root_control_pme_int_en; + output cfg_aer_rooterr_corr_err_reporting_en; + output cfg_aer_rooterr_non_fatal_err_reporting_en; + output cfg_aer_rooterr_fatal_err_reporting_en; + output cfg_aer_rooterr_corr_err_received; + output cfg_aer_rooterr_non_fatal_err_received; + output cfg_aer_rooterr_fatal_err_received; + output cfg_msg_received_err_cor; + output cfg_msg_received_err_non_fatal; + output cfg_msg_received_err_fatal; + output cfg_msg_received_pm_as_nak; + output cfg_msg_received_pm_pme; + output cfg_msg_received_pme_to_ack; + output cfg_msg_received_assert_int_a; + output cfg_msg_received_assert_int_b; + output cfg_msg_received_assert_int_c; + output cfg_msg_received_assert_int_d; + output cfg_msg_received_deassert_int_a; + output cfg_msg_received_deassert_int_b; + output cfg_msg_received_deassert_int_c; + output cfg_msg_received_deassert_int_d; + output cfg_msg_received_setslotpowerlimit; + input [1:0]pl_directed_link_change; + input [1:0]pl_directed_link_width; + input pl_directed_link_speed; + input pl_directed_link_auton; + input pl_upstream_prefer_deemph; + output pl_sel_lnk_rate; + output [1:0]pl_sel_lnk_width; + output [5:0]pl_ltssm_state; + output [1:0]pl_lane_reversal_mode; + output pl_phy_lnk_up; + output [2:0]pl_tx_pm_state; + output [1:0]pl_rx_pm_state; + output pl_link_upcfg_cap; + output pl_link_gen2_cap; + output pl_link_partner_gen2_supported; + output [2:0]pl_initial_link_width; + output pl_directed_change_done; + output pl_received_hot_rst; + input pl_transmit_hot_rst; + input pl_downstream_deemph_source; + input [127:0]cfg_err_aer_headerlog; + input [4:0]cfg_aer_interrupt_msgnum; + output cfg_err_aer_headerlog_set; + output cfg_aer_ecrc_check_en; + output cfg_aer_ecrc_gen_en; + output [6:0]cfg_vc_tcvc_map; + input sys_clk; + input sys_rst_n; + input pipe_mmcm_rst_n; + input pcie_drp_clk; + input pcie_drp_en; + input pcie_drp_we; + input [8:0]pcie_drp_addr; + input [15:0]pcie_drp_di; + output [15:0]pcie_drp_do; + output pcie_drp_rdy; +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_stub.vhdl b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_stub.vhdl new file mode 100644 index 0000000..fd423ad --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_stub.vhdl @@ -0,0 +1,205 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +-- Date : Wed Jul 20 13:38:01 2022 +-- Host : DESKTOP-4NLVFC8 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top pcie_7x_0 -prefix +-- pcie_7x_0_ pcie_7x_0_stub.vhdl +-- Design : pcie_7x_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z045ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity pcie_7x_0 is + Port ( + pci_exp_txp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_txn : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_rxp : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pci_exp_rxn : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_pclk_in : in STD_LOGIC; + pipe_rxusrclk_in : in STD_LOGIC; + pipe_rxoutclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_dclk_in : in STD_LOGIC; + pipe_userclk1_in : in STD_LOGIC; + pipe_userclk2_in : in STD_LOGIC; + pipe_oobclk_in : in STD_LOGIC; + pipe_mmcm_lock_in : in STD_LOGIC; + pipe_txoutclk_out : out STD_LOGIC; + pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); + pipe_gen3_out : out STD_LOGIC; + user_clk_out : out STD_LOGIC; + user_reset_out : out STD_LOGIC; + user_lnk_up : out STD_LOGIC; + user_app_rdy : out STD_LOGIC; + tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 ); + tx_cfg_req : out STD_LOGIC; + tx_err_drop : out STD_LOGIC; + s_axis_tx_tready : out STD_LOGIC; + s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_tx_tlast : in STD_LOGIC; + s_axis_tx_tvalid : in STD_LOGIC; + s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ); + tx_cfg_gnt : in STD_LOGIC; + m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axis_rx_tlast : out STD_LOGIC; + m_axis_rx_tvalid : out STD_LOGIC; + m_axis_rx_tready : in STD_LOGIC; + m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 ); + rx_np_ok : in STD_LOGIC; + rx_np_req : in STD_LOGIC; + fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 ); + fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 ); + fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_rd_wr_done : out STD_LOGIC; + cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_dcommand2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_pmcsr_pme_en : out STD_LOGIC; + cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_pmcsr_pme_status : out STD_LOGIC; + cfg_received_func_lvl_rst : out STD_LOGIC; + cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 ); + cfg_mgmt_byte_en : in STD_LOGIC_VECTOR ( 3 downto 0 ); + cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); + cfg_mgmt_wr_en : in STD_LOGIC; + cfg_mgmt_rd_en : in STD_LOGIC; + cfg_mgmt_wr_readonly : in STD_LOGIC; + cfg_err_ecrc : in STD_LOGIC; + cfg_err_ur : in STD_LOGIC; + cfg_err_cpl_timeout : in STD_LOGIC; + cfg_err_cpl_unexpect : in STD_LOGIC; + cfg_err_cpl_abort : in STD_LOGIC; + cfg_err_posted : in STD_LOGIC; + cfg_err_cor : in STD_LOGIC; + cfg_err_atomic_egress_blocked : in STD_LOGIC; + cfg_err_internal_cor : in STD_LOGIC; + cfg_err_malformed : in STD_LOGIC; + cfg_err_mc_blocked : in STD_LOGIC; + cfg_err_poisoned : in STD_LOGIC; + cfg_err_norecovery : in STD_LOGIC; + cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); + cfg_err_cpl_rdy : out STD_LOGIC; + cfg_err_locked : in STD_LOGIC; + cfg_err_acs : in STD_LOGIC; + cfg_err_internal_uncor : in STD_LOGIC; + cfg_trn_pending : in STD_LOGIC; + cfg_pm_halt_aspm_l0s : in STD_LOGIC; + cfg_pm_halt_aspm_l1 : in STD_LOGIC; + cfg_pm_force_state_en : in STD_LOGIC; + cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 ); + cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); + cfg_interrupt : in STD_LOGIC; + cfg_interrupt_rdy : out STD_LOGIC; + cfg_interrupt_assert : in STD_LOGIC; + cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_interrupt_msienable : out STD_LOGIC; + cfg_interrupt_msixenable : out STD_LOGIC; + cfg_interrupt_msixfm : out STD_LOGIC; + cfg_interrupt_stat : in STD_LOGIC; + cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_to_turnoff : out STD_LOGIC; + cfg_turnoff_ok : in STD_LOGIC; + cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_pm_wake : in STD_LOGIC; + cfg_pm_send_pme_to : in STD_LOGIC; + cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); + cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); + cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC; + cfg_msg_received : out STD_LOGIC; + cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); + cfg_bridge_serr_en : out STD_LOGIC; + cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC; + cfg_root_control_syserr_corr_err_en : out STD_LOGIC; + cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC; + cfg_root_control_syserr_fatal_err_en : out STD_LOGIC; + cfg_root_control_pme_int_en : out STD_LOGIC; + cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC; + cfg_aer_rooterr_corr_err_received : out STD_LOGIC; + cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC; + cfg_aer_rooterr_fatal_err_received : out STD_LOGIC; + cfg_msg_received_err_cor : out STD_LOGIC; + cfg_msg_received_err_non_fatal : out STD_LOGIC; + cfg_msg_received_err_fatal : out STD_LOGIC; + cfg_msg_received_pm_as_nak : out STD_LOGIC; + cfg_msg_received_pm_pme : out STD_LOGIC; + cfg_msg_received_pme_to_ack : out STD_LOGIC; + cfg_msg_received_assert_int_a : out STD_LOGIC; + cfg_msg_received_assert_int_b : out STD_LOGIC; + cfg_msg_received_assert_int_c : out STD_LOGIC; + cfg_msg_received_assert_int_d : out STD_LOGIC; + cfg_msg_received_deassert_int_a : out STD_LOGIC; + cfg_msg_received_deassert_int_b : out STD_LOGIC; + cfg_msg_received_deassert_int_c : out STD_LOGIC; + cfg_msg_received_deassert_int_d : out STD_LOGIC; + cfg_msg_received_setslotpowerlimit : out STD_LOGIC; + pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_directed_link_speed : in STD_LOGIC; + pl_directed_link_auton : in STD_LOGIC; + pl_upstream_prefer_deemph : in STD_LOGIC; + pl_sel_lnk_rate : out STD_LOGIC; + pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 ); + pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_phy_lnk_up : out STD_LOGIC; + pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 ); + pl_link_upcfg_cap : out STD_LOGIC; + pl_link_gen2_cap : out STD_LOGIC; + pl_link_partner_gen2_supported : out STD_LOGIC; + pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 ); + pl_directed_change_done : out STD_LOGIC; + pl_received_hot_rst : out STD_LOGIC; + pl_transmit_hot_rst : in STD_LOGIC; + pl_downstream_deemph_source : in STD_LOGIC; + cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 ); + cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 ); + cfg_err_aer_headerlog_set : out STD_LOGIC; + cfg_aer_ecrc_check_en : out STD_LOGIC; + cfg_aer_ecrc_gen_en : out STD_LOGIC; + cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 ); + sys_clk : in STD_LOGIC; + sys_rst_n : in STD_LOGIC; + pipe_mmcm_rst_n : in STD_LOGIC; + pcie_drp_clk : in STD_LOGIC; + pcie_drp_en : in STD_LOGIC; + pcie_drp_we : in STD_LOGIC; + pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 ); + pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 ); + pcie_drp_rdy : out STD_LOGIC + ); + +end pcie_7x_0; + +architecture stub of pcie_7x_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "pci_exp_txp[3:0],pci_exp_txn[3:0],pci_exp_rxp[3:0],pci_exp_rxn[3:0],pipe_pclk_in,pipe_rxusrclk_in,pipe_rxoutclk_in[3:0],pipe_dclk_in,pipe_userclk1_in,pipe_userclk2_in,pipe_oobclk_in,pipe_mmcm_lock_in,pipe_txoutclk_out,pipe_rxoutclk_out[3:0],pipe_pclk_sel_out[3:0],pipe_gen3_out,user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[63:0],s_axis_tx_tkeep[7:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[63:0],m_axis_rx_tkeep[7:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_mgmt_do[31:0],cfg_mgmt_rd_wr_done,cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_mgmt_di[31:0],cfg_mgmt_byte_en[3:0],cfg_mgmt_dwaddr[9:0],cfg_mgmt_wr_en,cfg_mgmt_rd_en,cfg_mgmt_wr_readonly,cfg_err_ecrc,cfg_err_ur,cfg_err_cpl_timeout,cfg_err_cpl_unexpect,cfg_err_cpl_abort,cfg_err_posted,cfg_err_cor,cfg_err_atomic_egress_blocked,cfg_err_internal_cor,cfg_err_malformed,cfg_err_mc_blocked,cfg_err_poisoned,cfg_err_norecovery,cfg_err_tlp_cpl_header[47:0],cfg_err_cpl_rdy,cfg_err_locked,cfg_err_acs,cfg_err_internal_uncor,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_mgmt_wr_rw1c_as_rw,cfg_msg_received,cfg_msg_data[15:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_msg_received_err_cor,cfg_msg_received_err_non_fatal,cfg_msg_received_err_fatal,cfg_msg_received_pm_as_nak,cfg_msg_received_pm_pme,cfg_msg_received_pme_to_ack,cfg_msg_received_assert_int_a,cfg_msg_received_assert_int_b,cfg_msg_received_assert_int_c,cfg_msg_received_assert_int_d,cfg_msg_received_deassert_int_a,cfg_msg_received_deassert_int_b,cfg_msg_received_deassert_int_c,cfg_msg_received_deassert_int_d,cfg_msg_received_setslotpowerlimit,pl_directed_link_change[1:0],pl_directed_link_width[1:0],pl_directed_link_speed,pl_directed_link_auton,pl_upstream_prefer_deemph,pl_sel_lnk_rate,pl_sel_lnk_width[1:0],pl_ltssm_state[5:0],pl_lane_reversal_mode[1:0],pl_phy_lnk_up,pl_tx_pm_state[2:0],pl_rx_pm_state[1:0],pl_link_upcfg_cap,pl_link_gen2_cap,pl_link_partner_gen2_supported,pl_initial_link_width[2:0],pl_directed_change_done,pl_received_hot_rst,pl_transmit_hot_rst,pl_downstream_deemph_source,cfg_err_aer_headerlog[127:0],cfg_aer_interrupt_msgnum[4:0],cfg_err_aer_headerlog_set,cfg_aer_ecrc_check_en,cfg_aer_ecrc_gen_en,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n,pipe_mmcm_rst_n,pcie_drp_clk,pcie_drp_en,pcie_drp_we,pcie_drp_addr[8:0],pcie_drp_di[15:0],pcie_drp_do[15:0],pcie_drp_rdy"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "pcie_7x_0_pcie2_top,Vivado 2020.2"; +begin +end; diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/sim/pcie_7x_0.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/sim/pcie_7x_0.v new file mode 100644 index 0000000..cc10708 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/sim/pcie_7x_0.v @@ -0,0 +1,1096 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:pcie_7x:3.3 +// IP Revision: 14 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0 ( + pci_exp_txp, + pci_exp_txn, + pci_exp_rxp, + pci_exp_rxn, + pipe_pclk_in, + pipe_rxusrclk_in, + pipe_rxoutclk_in, + pipe_dclk_in, + pipe_userclk1_in, + pipe_userclk2_in, + pipe_oobclk_in, + pipe_mmcm_lock_in, + pipe_txoutclk_out, + pipe_rxoutclk_out, + pipe_pclk_sel_out, + pipe_gen3_out, + user_clk_out, + user_reset_out, + user_lnk_up, + user_app_rdy, + tx_buf_av, + tx_cfg_req, + tx_err_drop, + s_axis_tx_tready, + s_axis_tx_tdata, + s_axis_tx_tkeep, + s_axis_tx_tlast, + s_axis_tx_tvalid, + s_axis_tx_tuser, + tx_cfg_gnt, + m_axis_rx_tdata, + m_axis_rx_tkeep, + m_axis_rx_tlast, + m_axis_rx_tvalid, + m_axis_rx_tready, + m_axis_rx_tuser, + rx_np_ok, + rx_np_req, + fc_cpld, + fc_cplh, + fc_npd, + fc_nph, + fc_pd, + fc_ph, + fc_sel, + cfg_mgmt_do, + cfg_mgmt_rd_wr_done, + cfg_status, + cfg_command, + cfg_dstatus, + cfg_dcommand, + cfg_lstatus, + cfg_lcommand, + cfg_dcommand2, + cfg_pcie_link_state, + cfg_pmcsr_pme_en, + cfg_pmcsr_powerstate, + cfg_pmcsr_pme_status, + cfg_received_func_lvl_rst, + cfg_mgmt_di, + cfg_mgmt_byte_en, + cfg_mgmt_dwaddr, + cfg_mgmt_wr_en, + cfg_mgmt_rd_en, + cfg_mgmt_wr_readonly, + cfg_err_ecrc, + cfg_err_ur, + cfg_err_cpl_timeout, + cfg_err_cpl_unexpect, + cfg_err_cpl_abort, + cfg_err_posted, + cfg_err_cor, + cfg_err_atomic_egress_blocked, + cfg_err_internal_cor, + cfg_err_malformed, + cfg_err_mc_blocked, + cfg_err_poisoned, + cfg_err_norecovery, + cfg_err_tlp_cpl_header, + cfg_err_cpl_rdy, + cfg_err_locked, + cfg_err_acs, + cfg_err_internal_uncor, + cfg_trn_pending, + cfg_pm_halt_aspm_l0s, + cfg_pm_halt_aspm_l1, + cfg_pm_force_state_en, + cfg_pm_force_state, + cfg_dsn, + cfg_interrupt, + cfg_interrupt_rdy, + cfg_interrupt_assert, + cfg_interrupt_di, + cfg_interrupt_do, + cfg_interrupt_mmenable, + cfg_interrupt_msienable, + cfg_interrupt_msixenable, + cfg_interrupt_msixfm, + cfg_interrupt_stat, + cfg_pciecap_interrupt_msgnum, + cfg_to_turnoff, + cfg_turnoff_ok, + cfg_bus_number, + cfg_device_number, + cfg_function_number, + cfg_pm_wake, + cfg_pm_send_pme_to, + cfg_ds_bus_number, + cfg_ds_device_number, + cfg_ds_function_number, + cfg_mgmt_wr_rw1c_as_rw, + cfg_msg_received, + cfg_msg_data, + cfg_bridge_serr_en, + cfg_slot_control_electromech_il_ctl_pulse, + cfg_root_control_syserr_corr_err_en, + cfg_root_control_syserr_non_fatal_err_en, + cfg_root_control_syserr_fatal_err_en, + cfg_root_control_pme_int_en, + cfg_aer_rooterr_corr_err_reporting_en, + cfg_aer_rooterr_non_fatal_err_reporting_en, + cfg_aer_rooterr_fatal_err_reporting_en, + cfg_aer_rooterr_corr_err_received, + cfg_aer_rooterr_non_fatal_err_received, + cfg_aer_rooterr_fatal_err_received, + cfg_msg_received_err_cor, + cfg_msg_received_err_non_fatal, + cfg_msg_received_err_fatal, + cfg_msg_received_pm_as_nak, + cfg_msg_received_pm_pme, + cfg_msg_received_pme_to_ack, + cfg_msg_received_assert_int_a, + cfg_msg_received_assert_int_b, + cfg_msg_received_assert_int_c, + cfg_msg_received_assert_int_d, + cfg_msg_received_deassert_int_a, + cfg_msg_received_deassert_int_b, + cfg_msg_received_deassert_int_c, + cfg_msg_received_deassert_int_d, + cfg_msg_received_setslotpowerlimit, + pl_directed_link_change, + pl_directed_link_width, + pl_directed_link_speed, + pl_directed_link_auton, + pl_upstream_prefer_deemph, + pl_sel_lnk_rate, + pl_sel_lnk_width, + pl_ltssm_state, + pl_lane_reversal_mode, + pl_phy_lnk_up, + pl_tx_pm_state, + pl_rx_pm_state, + pl_link_upcfg_cap, + pl_link_gen2_cap, + pl_link_partner_gen2_supported, + pl_initial_link_width, + pl_directed_change_done, + pl_received_hot_rst, + pl_transmit_hot_rst, + pl_downstream_deemph_source, + cfg_err_aer_headerlog, + cfg_aer_interrupt_msgnum, + cfg_err_aer_headerlog_set, + cfg_aer_ecrc_check_en, + cfg_aer_ecrc_gen_en, + cfg_vc_tcvc_map, + sys_clk, + sys_rst_n, + pipe_mmcm_rst_n, + pcie_drp_clk, + pcie_drp_en, + pcie_drp_we, + pcie_drp_addr, + pcie_drp_di, + pcie_drp_do, + pcie_drp_rdy +); + +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txp" *) +output wire [3 : 0] pci_exp_txp; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txn" *) +output wire [3 : 0] pci_exp_txn; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxp" *) +input wire [3 : 0] pci_exp_rxp; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxn" *) +input wire [3 : 0] pci_exp_rxn; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock pclk_in" *) +input wire pipe_pclk_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxusrclk_in" *) +input wire pipe_rxusrclk_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxoutclk_in" *) +input wire [3 : 0] pipe_rxoutclk_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock dclk_in" *) +input wire pipe_dclk_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock userclk1_in" *) +input wire pipe_userclk1_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock userclk2_in" *) +input wire pipe_userclk2_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock oobclk_in" *) +input wire pipe_oobclk_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock mmcm_lock_in" *) +input wire pipe_mmcm_lock_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock txoutclk_out" *) +output wire pipe_txoutclk_out; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxoutclk_out" *) +output wire [3 : 0] pipe_rxoutclk_out; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock pclk_sel_out" *) +output wire [3 : 0] pipe_pclk_sel_out; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock gen3_out" *) +output wire pipe_gen3_out; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.user_clk_out, ASSOCIATED_BUSIF m_axis_rx:s_axis_tx, FREQ_HZ 125000000, ASSOCIATED_RESET user_reset_out, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.user_clk_out CLK" *) +output wire user_clk_out; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.user_reset_out, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.user_reset_out RST" *) +output wire user_reset_out; +output wire user_lnk_up; +output wire user_app_rdy; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_buf_av" *) +output wire [5 : 0] tx_buf_av; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_cfg_req" *) +output wire tx_cfg_req; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_err_drop" *) +output wire tx_err_drop; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TREADY" *) +output wire s_axis_tx_tready; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TDATA" *) +input wire [63 : 0] s_axis_tx_tdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TKEEP" *) +input wire [7 : 0] s_axis_tx_tkeep; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TLAST" *) +input wire s_axis_tx_tlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TVALID" *) +input wire s_axis_tx_tvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axis_tx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TUSER" *) +input wire [3 : 0] s_axis_tx_tuser; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control tx_cfg_gnt" *) +input wire tx_cfg_gnt; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TDATA" *) +output wire [63 : 0] m_axis_rx_tdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TKEEP" *) +output wire [7 : 0] m_axis_rx_tkeep; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TLAST" *) +output wire m_axis_rx_tlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TVALID" *) +output wire m_axis_rx_tvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TREADY" *) +input wire m_axis_rx_tready; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis_rx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TUSER" *) +output wire [21 : 0] m_axis_rx_tuser; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_ok" *) +input wire rx_np_ok; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_req" *) +input wire rx_np_req; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLD" *) +output wire [11 : 0] fc_cpld; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLH" *) +output wire [7 : 0] fc_cplh; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPD" *) +output wire [11 : 0] fc_npd; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPH" *) +output wire [7 : 0] fc_nph; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PD" *) +output wire [11 : 0] fc_pd; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PH" *) +output wire [7 : 0] fc_ph; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc SEL" *) +input wire [2 : 0] fc_sel; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_DATA" *) +output wire [31 : 0] cfg_mgmt_do; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_WRITE_DONE" *) +output wire cfg_mgmt_rd_wr_done; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status status" *) +output wire [15 : 0] cfg_status; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status command" *) +output wire [15 : 0] cfg_command; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dstatus" *) +output wire [15 : 0] cfg_dstatus; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand" *) +output wire [15 : 0] cfg_dcommand; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lstatus" *) +output wire [15 : 0] cfg_lstatus; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lcommand" *) +output wire [15 : 0] cfg_lcommand; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand2" *) +output wire [15 : 0] cfg_dcommand2; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pcie_link_state" *) +output wire [2 : 0] cfg_pcie_link_state; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_en" *) +output wire cfg_pmcsr_pme_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_powerstate" *) +output wire [1 : 0] cfg_pmcsr_powerstate; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_status" *) +output wire cfg_pmcsr_pme_status; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status received_func_lvl_rst" *) +output wire cfg_received_func_lvl_rst; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_DATA" *) +input wire [31 : 0] cfg_mgmt_di; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt BYTE_EN" *) +input wire [3 : 0] cfg_mgmt_byte_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt ADDR" *) +input wire [9 : 0] cfg_mgmt_dwaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_EN" *) +input wire cfg_mgmt_wr_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_EN" *) +input wire cfg_mgmt_rd_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READONLY" *) +input wire cfg_mgmt_wr_readonly; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ecrc" *) +input wire cfg_err_ecrc; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ur" *) +input wire cfg_err_ur; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_timeout" *) +input wire cfg_err_cpl_timeout; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_unexpect" *) +input wire cfg_err_cpl_unexpect; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_abort" *) +input wire cfg_err_cpl_abort; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err posted" *) +input wire cfg_err_posted; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cor" *) +input wire cfg_err_cor; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err atomic_egress_blocked" *) +input wire cfg_err_atomic_egress_blocked; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_cor" *) +input wire cfg_err_internal_cor; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err malformed" *) +input wire cfg_err_malformed; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err mc_blocked" *) +input wire cfg_err_mc_blocked; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err poisoned" *) +input wire cfg_err_poisoned; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err norecovery" *) +input wire cfg_err_norecovery; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err tlp_cpl_header" *) +input wire [47 : 0] cfg_err_tlp_cpl_header; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_rdy" *) +output wire cfg_err_cpl_rdy; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err locked" *) +input wire cfg_err_locked; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err acs" *) +input wire cfg_err_acs; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_uncor" *) +input wire cfg_err_internal_uncor; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control trn_pending" *) +input wire cfg_trn_pending; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l0s" *) +input wire cfg_pm_halt_aspm_l0s; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l1" *) +input wire cfg_pm_halt_aspm_l1; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state_en" *) +input wire cfg_pm_force_state_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state" *) +input wire [1 : 0] cfg_pm_force_state; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control dsn" *) +input wire [63 : 0] cfg_dsn; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt interrupt" *) +input wire cfg_interrupt; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt rdy" *) +output wire cfg_interrupt_rdy; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt assert" *) +input wire cfg_interrupt_assert; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt write_data" *) +input wire [7 : 0] cfg_interrupt_di; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt read_data" *) +output wire [7 : 0] cfg_interrupt_do; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt mmenable" *) +output wire [2 : 0] cfg_interrupt_mmenable; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msienable" *) +output wire cfg_interrupt_msienable; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixenable" *) +output wire cfg_interrupt_msixenable; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixfm" *) +output wire cfg_interrupt_msixfm; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt stat" *) +input wire cfg_interrupt_stat; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt pciecap_interrupt_msgnum" *) +input wire [4 : 0] cfg_pciecap_interrupt_msgnum; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status turnoff" *) +output wire cfg_to_turnoff; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control turnoff_ok" *) +input wire cfg_turnoff_ok; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bus_number" *) +output wire [7 : 0] cfg_bus_number; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status device_number" *) +output wire [4 : 0] cfg_device_number; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status function_number" *) +output wire [2 : 0] cfg_function_number; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_wake" *) +input wire cfg_pm_wake; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_send_pme_to" *) +input wire cfg_pm_send_pme_to; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_bus_number" *) +input wire [7 : 0] cfg_ds_bus_number; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_device_number" *) +input wire [4 : 0] cfg_ds_device_number; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_function_number" *) +input wire [2 : 0] cfg_ds_function_number; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt TYPE1_CFG_REG_ACCESS" *) +input wire cfg_mgmt_wr_rw1c_as_rw; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received" *) +output wire cfg_msg_received; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd data" *) +output wire [15 : 0] cfg_msg_data; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bridge_serr_en" *) +output wire cfg_bridge_serr_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status slot_control_electromech_il_ctl_pulse" *) +output wire cfg_slot_control_electromech_il_ctl_pulse; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_corr_err_en" *) +output wire cfg_root_control_syserr_corr_err_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_non_fatal_err_en" *) +output wire cfg_root_control_syserr_non_fatal_err_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_fatal_err_en" *) +output wire cfg_root_control_syserr_fatal_err_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_pme_int_en" *) +output wire cfg_root_control_pme_int_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_reporting_en" *) +output wire cfg_aer_rooterr_corr_err_reporting_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_reporting_en" *) +output wire cfg_aer_rooterr_non_fatal_err_reporting_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_reporting_en" *) +output wire cfg_aer_rooterr_fatal_err_reporting_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_received" *) +output wire cfg_aer_rooterr_corr_err_received; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_received" *) +output wire cfg_aer_rooterr_non_fatal_err_received; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_received" *) +output wire cfg_aer_rooterr_fatal_err_received; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_cor" *) +output wire cfg_msg_received_err_cor; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_non_fatal" *) +output wire cfg_msg_received_err_non_fatal; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_fatal" *) +output wire cfg_msg_received_err_fatal; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_pm_as_nak" *) +output wire cfg_msg_received_pm_as_nak; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pm_pme" *) +output wire cfg_msg_received_pm_pme; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pme_to_ack" *) +output wire cfg_msg_received_pme_to_ack; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_a" *) +output wire cfg_msg_received_assert_int_a; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_b" *) +output wire cfg_msg_received_assert_int_b; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_c" *) +output wire cfg_msg_received_assert_int_c; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_d" *) +output wire cfg_msg_received_assert_int_d; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_a" *) +output wire cfg_msg_received_deassert_int_a; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_b" *) +output wire cfg_msg_received_deassert_int_b; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_c" *) +output wire cfg_msg_received_deassert_int_c; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_d" *) +output wire cfg_msg_received_deassert_int_d; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_setslotpowerlimit" *) +output wire cfg_msg_received_setslotpowerlimit; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_change" *) +input wire [1 : 0] pl_directed_link_change; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_width" *) +input wire [1 : 0] pl_directed_link_width; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_speed" *) +input wire pl_directed_link_speed; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_auton" *) +input wire pl_directed_link_auton; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl upstream_prefer_deemph" *) +input wire pl_upstream_prefer_deemph; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_rate" *) +output wire pl_sel_lnk_rate; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_width" *) +output wire [1 : 0] pl_sel_lnk_width; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl ltssm_state" *) +output wire [5 : 0] pl_ltssm_state; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl lane_reversal_mode" *) +output wire [1 : 0] pl_lane_reversal_mode; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl phy_lnk_up" *) +output wire pl_phy_lnk_up; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl tx_pm_state" *) +output wire [2 : 0] pl_tx_pm_state; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl rx_pm_state" *) +output wire [1 : 0] pl_rx_pm_state; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_upcfg_cap" *) +output wire pl_link_upcfg_cap; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_gen2_cap" *) +output wire pl_link_gen2_cap; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_partner_gen2_supported" *) +output wire pl_link_partner_gen2_supported; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl initial_link_width" *) +output wire [2 : 0] pl_initial_link_width; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_change_done" *) +output wire pl_directed_change_done; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl received_hot_rst" *) +output wire pl_received_hot_rst; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl transmit_hot_rst" *) +input wire pl_transmit_hot_rst; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl downstream_deemph_source" *) +input wire pl_downstream_deemph_source; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog" *) +input wire [127 : 0] cfg_err_aer_headerlog; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_interrupt_msgnum" *) +input wire [4 : 0] cfg_aer_interrupt_msgnum; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog_set" *) +output wire cfg_err_aer_headerlog_set; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_check_en" *) +output wire cfg_aer_ecrc_check_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_gen_en" *) +output wire cfg_aer_ecrc_gen_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status vc_tcvc_map" *) +output wire [6 : 0] cfg_vc_tcvc_map; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.sys_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.sys_clk CLK" *) +input wire sys_clk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.sys_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.sys_rst_n RST" *) +input wire sys_rst_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock mmcm_rst_n" *) +input wire pipe_mmcm_rst_n; +input wire pcie_drp_clk; +(* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DEN" *) +input wire pcie_drp_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DWE" *) +input wire pcie_drp_we; +(* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DADDR" *) +input wire [8 : 0] pcie_drp_addr; +(* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DI" *) +input wire [15 : 0] pcie_drp_di; +(* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DO" *) +output wire [15 : 0] pcie_drp_do; +(* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DRDY" *) +output wire pcie_drp_rdy; + + pcie_7x_0_pcie2_top #( + .c_component_name("pcie_7x_0"), + .dev_port_type("0000"), + .c_dev_port_type("0"), + .c_header_type("00"), + .c_upstream_facing("TRUE"), + .max_lnk_wdt("000100"), + .max_lnk_spd("2"), + .c_gen1(1'B1), + .pci_exp_int_freq(3), + .c_pcie_fast_config(0), + .bar_0("FFFF0000"), + .bar_1("00000000"), + .bar_2("00000000"), + .bar_3("00000000"), + .bar_4("00000000"), + .bar_5("00000000"), + .xrom_bar("00000000"), + .cost_table(1), + .ven_id("10EE"), + .dev_id("7024"), + .rev_id("00"), + .subsys_ven_id("10EE"), + .subsys_id("0007"), + .class_code("050000"), + .cardbus_cis_ptr("00000000"), + .cap_ver("2"), + .c_pcie_cap_slot_implemented("FALSE"), + .mps("011"), + .cmps("3"), + .ext_tag_fld_sup("FALSE"), + .c_dev_control_ext_tag_default("FALSE"), + .phantm_func_sup("00"), + .c_phantom_functions("0"), + .ep_l0s_accpt_lat("000"), + .c_ep_l0s_accpt_lat("0"), + .ep_l1_accpt_lat("111"), + .c_ep_l1_accpt_lat("7"), + .c_cpl_timeout_disable_sup("FALSE"), + .c_cpl_timeout_range("0010"), + .c_cpl_timeout_ranges_sup("2"), + .c_buf_opt_bma("TRUE"), + .c_perf_level_high("TRUE"), + .c_tx_last_tlp("30"), + .c_rx_ram_limit("FFF"), + .c_fc_ph("32"), + .c_fc_pd("949"), + .c_fc_nph("12"), + .c_fc_npd("24"), + .c_fc_cplh("36"), + .c_fc_cpld("973"), + .c_cpl_inf("TRUE"), + .c_cpl_infinite("TRUE"), + .c_dll_lnk_actv_cap("FALSE"), + .c_trgt_lnk_spd("2"), + .c_hw_auton_spd_disable("FALSE"), + .c_de_emph("FALSE"), + .slot_clk("TRUE"), + .c_rcb("0"), + .c_root_cap_crs("FALSE"), + .c_slot_cap_attn_butn("FALSE"), + .c_slot_cap_attn_ind("FALSE"), + .c_slot_cap_pwr_ctrl("FALSE"), + .c_slot_cap_pwr_ind("FALSE"), + .c_slot_cap_hotplug_surprise("FALSE"), + .c_slot_cap_hotplug_cap("FALSE"), + .c_slot_cap_mrl("FALSE"), + .c_slot_cap_elec_interlock("FALSE"), + .c_slot_cap_no_cmd_comp_sup("FALSE"), + .c_slot_cap_pwr_limit_value("0"), + .c_slot_cap_pwr_limit_scale("0"), + .c_slot_cap_physical_slot_num("0"), + .intx("TRUE"), + .int_pin("1"), + .c_msi_cap_on("FALSE"), + .c_pm_cap_next_ptr("60"), + .c_msi_64b_addr("TRUE"), + .c_msi("0"), + .c_msi_mult_msg_extn("0"), + .c_msi_per_vctr_mask_cap("FALSE"), + .c_msix_cap_on("FALSE"), + .c_msix_next_ptr("00"), + .c_pcie_cap_next_ptr("00"), + .c_msix_table_size("000"), + .c_msix_table_offset("0"), + .c_msix_table_bir("0"), + .c_msix_pba_offset("0"), + .c_msix_pba_bir("0"), + .dsi("0"), + .c_dsi_bool("FALSE"), + .d1_sup("0"), + .c_d1_support("FALSE"), + .d2_sup("0"), + .c_d2_support("FALSE"), + .pme_sup("0F"), + .c_pme_support("0F"), + .no_soft_rst("TRUE"), + .pwr_con_d0_state("00"), + .con_scl_fctr_d0_state("0"), + .pwr_con_d1_state("00"), + .con_scl_fctr_d1_state("0"), + .pwr_con_d2_state("00"), + .con_scl_fctr_d2_state("0"), + .pwr_con_d3_state("00"), + .con_scl_fctr_d3_state("0"), + .pwr_dis_d0_state("00"), + .dis_scl_fctr_d0_state("0"), + .pwr_dis_d1_state("00"), + .dis_scl_fctr_d1_state("0"), + .pwr_dis_d2_state("00"), + .dis_scl_fctr_d2_state("0"), + .pwr_dis_d3_state("00"), + .dis_scl_fctr_d3_state("0"), + .c_dsn_cap_enabled("TRUE"), + .c_dsn_base_ptr("100"), + .c_vc_cap_enabled("FALSE"), + .c_vc_base_ptr("000"), + .c_vc_cap_reject_snoop("FALSE"), + .c_vsec_cap_enabled("FALSE"), + .c_vsec_base_ptr("000"), + .c_vsec_next_ptr("000"), + .c_dsn_next_ptr("000"), + .c_vc_next_ptr("000"), + .c_pci_cfg_space_addr("3F"), + .c_ext_pci_cfg_space_addr("3FF"), + .c_last_cfg_dw("10C"), + .c_enable_msg_route("00000000000"), + .bram_lat("0"), + .c_rx_raddr_lat("0"), + .c_rx_rdata_lat("2"), + .c_rx_write_lat("0"), + .c_tx_raddr_lat("0"), + .c_tx_rdata_lat("2"), + .c_tx_write_lat("0"), + .c_ll_ack_timeout_enable("FALSE"), + .c_ll_ack_timeout_function("0"), + .c_ll_ack_timeout("0000"), + .c_ll_replay_timeout_enable("FALSE"), + .c_ll_replay_timeout_func("1"), + .c_ll_replay_timeout("0000"), + .c_dis_lane_reverse("TRUE"), + .c_upconfig_capable("TRUE"), + .c_disable_scrambling("FALSE"), + .c_disable_tx_aspm_l0s("FALSE"), + .c_pcie_dbg_ports("TRUE"), + .pci_exp_ref_freq("0"), + .c_xlnx_ref_board("ZC706"), + .c_pcie_blk_locn("0"), + .c_ur_atomic("FALSE"), + .c_dev_cap2_atomicop32_completer_supported("FALSE"), + .c_dev_cap2_atomicop64_completer_supported("FALSE"), + .c_dev_cap2_cas128_completer_supported("FALSE"), + .c_dev_cap2_tph_completer_supported("00"), + .c_dev_cap2_ari_forwarding_supported("FALSE"), + .c_dev_cap2_atomicop_routing_supported("FALSE"), + .c_link_cap_aspm_optionality("FALSE"), + .c_aer_cap_on("FALSE"), + .c_aer_base_ptr("000"), + .c_aer_cap_nextptr("000"), + .c_aer_cap_ecrc_check_capable("FALSE"), + .c_aer_cap_ecrc_gen_capable("FALSE"), + .c_aer_cap_multiheader("FALSE"), + .c_aer_cap_permit_rooterr_update("FALSE"), + .c_rbar_cap_on("FALSE"), + .c_rbar_base_ptr("000"), + .c_rbar_cap_nextptr("000"), + .c_rbar_num("0"), + .c_rbar_cap_sup0("00001"), + .c_rbar_cap_index0("0"), + .c_rbar_cap_control_encodedbar0("00"), + .c_rbar_cap_sup1("00001"), + .c_rbar_cap_index1("0"), + .c_rbar_cap_control_encodedbar1("00"), + .c_rbar_cap_sup2("00001"), + .c_rbar_cap_index2("0"), + .c_rbar_cap_control_encodedbar2("00"), + .c_rbar_cap_sup3("00001"), + .c_rbar_cap_index3("0"), + .c_rbar_cap_control_encodedbar3("00"), + .c_rbar_cap_sup4("00001"), + .c_rbar_cap_index4("0"), + .c_rbar_cap_control_encodedbar4("00"), + .c_rbar_cap_sup5("00001"), + .c_rbar_cap_index5("0"), + .c_rbar_cap_control_encodedbar5("00"), + .c_recrc_check("0"), + .c_recrc_check_trim("FALSE"), + .c_disable_rx_poisoned_resp("FALSE"), + .c_trn_np_fc("TRUE"), + .c_ur_inv_req("TRUE"), + .c_ur_prs_response("TRUE"), + .c_silicon_rev("2"), + .c_aer_cap_optional_err_support("000000"), + .LINK_CAP_MAX_LINK_WIDTH(4), + .C_DATA_WIDTH(64), + .PIPE_SIM("FALSE"), + .PCIE_EXT_CLK("TRUE"), + .PCIE_EXT_GT_COMMON("FALSE"), + .EXT_CH_GT_DRP("FALSE"), + .TRANSCEIVER_CTRL_STATUS_PORTS("FALSE"), + .SHARED_LOGIC_IN_CORE("FALSE"), + .ERR_REPORTING_IF("TRUE"), + .PL_INTERFACE("TRUE"), + .CFG_MGMT_IF("TRUE"), + .CFG_CTL_IF("TRUE"), + .CFG_STATUS_IF("TRUE"), + .RCV_MSG_IF("TRUE"), + .CFG_FC_IF("TRUE"), + .EXT_PIPE_INTERFACE("FALSE"), + .EXT_STARTUP_PRIMITIVE("FALSE"), + .KEEP_WIDTH(8), + .PCIE_ASYNC_EN("FALSE"), + .ENABLE_JTAG_DBG("FALSE"), + .REDUCE_OOB_FREQ("FALSE") + ) inst ( + .pci_exp_txp(pci_exp_txp), + .pci_exp_txn(pci_exp_txn), + .pci_exp_rxp(pci_exp_rxp), + .pci_exp_rxn(pci_exp_rxn), + .int_pclk_out_slave(), + .int_pipe_rxusrclk_out(), + .int_rxoutclk_out(), + .int_dclk_out(), + .int_mmcm_lock_out(), + .int_userclk1_out(), + .int_userclk2_out(), + .int_oobclk_out(), + .int_qplllock_out(), + .int_qplloutclk_out(), + .int_qplloutrefclk_out(), + .int_pclk_sel_slave(4'B0), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .pipe_rxoutclk_in(pipe_rxoutclk_in), + .pipe_dclk_in(pipe_dclk_in), + .pipe_userclk1_in(pipe_userclk1_in), + .pipe_userclk2_in(pipe_userclk2_in), + .pipe_oobclk_in(pipe_oobclk_in), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_txoutclk_out(pipe_txoutclk_out), + .pipe_rxoutclk_out(pipe_rxoutclk_out), + .pipe_pclk_sel_out(pipe_pclk_sel_out), + .pipe_gen3_out(pipe_gen3_out), + .user_clk_out(user_clk_out), + .user_reset_out(user_reset_out), + .user_lnk_up(user_lnk_up), + .user_app_rdy(user_app_rdy), + .tx_buf_av(tx_buf_av), + .tx_cfg_req(tx_cfg_req), + .tx_err_drop(tx_err_drop), + .s_axis_tx_tready(s_axis_tx_tready), + .s_axis_tx_tdata(s_axis_tx_tdata), + .s_axis_tx_tkeep(s_axis_tx_tkeep), + .s_axis_tx_tlast(s_axis_tx_tlast), + .s_axis_tx_tvalid(s_axis_tx_tvalid), + .s_axis_tx_tuser(s_axis_tx_tuser), + .tx_cfg_gnt(tx_cfg_gnt), + .m_axis_rx_tdata(m_axis_rx_tdata), + .m_axis_rx_tkeep(m_axis_rx_tkeep), + .m_axis_rx_tlast(m_axis_rx_tlast), + .m_axis_rx_tvalid(m_axis_rx_tvalid), + .m_axis_rx_tready(m_axis_rx_tready), + .m_axis_rx_tuser(m_axis_rx_tuser), + .rx_np_ok(rx_np_ok), + .rx_np_req(rx_np_req), + .fc_cpld(fc_cpld), + .fc_cplh(fc_cplh), + .fc_npd(fc_npd), + .fc_nph(fc_nph), + .fc_pd(fc_pd), + .fc_ph(fc_ph), + .fc_sel(fc_sel), + .cfg_mgmt_do(cfg_mgmt_do), + .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done), + .cfg_status(cfg_status), + .cfg_command(cfg_command), + .cfg_dstatus(cfg_dstatus), + .cfg_dcommand(cfg_dcommand), + .cfg_lstatus(cfg_lstatus), + .cfg_lcommand(cfg_lcommand), + .cfg_dcommand2(cfg_dcommand2), + .cfg_pcie_link_state(cfg_pcie_link_state), + .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en), + .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate), + .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status), + .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst), + .cfg_mgmt_di(cfg_mgmt_di), + .cfg_mgmt_byte_en(cfg_mgmt_byte_en), + .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr), + .cfg_mgmt_wr_en(cfg_mgmt_wr_en), + .cfg_mgmt_rd_en(cfg_mgmt_rd_en), + .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly), + .cfg_err_ecrc(cfg_err_ecrc), + .cfg_err_ur(cfg_err_ur), + .cfg_err_cpl_timeout(cfg_err_cpl_timeout), + .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect), + .cfg_err_cpl_abort(cfg_err_cpl_abort), + .cfg_err_posted(cfg_err_posted), + .cfg_err_cor(cfg_err_cor), + .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked), + .cfg_err_internal_cor(cfg_err_internal_cor), + .cfg_err_malformed(cfg_err_malformed), + .cfg_err_mc_blocked(cfg_err_mc_blocked), + .cfg_err_poisoned(cfg_err_poisoned), + .cfg_err_norecovery(cfg_err_norecovery), + .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header), + .cfg_err_cpl_rdy(cfg_err_cpl_rdy), + .cfg_err_locked(cfg_err_locked), + .cfg_err_acs(cfg_err_acs), + .cfg_err_internal_uncor(cfg_err_internal_uncor), + .cfg_trn_pending(cfg_trn_pending), + .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s), + .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1), + .cfg_pm_force_state_en(cfg_pm_force_state_en), + .cfg_pm_force_state(cfg_pm_force_state), + .cfg_dsn(cfg_dsn), + .cfg_interrupt(cfg_interrupt), + .cfg_interrupt_rdy(cfg_interrupt_rdy), + .cfg_interrupt_assert(cfg_interrupt_assert), + .cfg_interrupt_di(cfg_interrupt_di), + .cfg_interrupt_do(cfg_interrupt_do), + .cfg_interrupt_mmenable(cfg_interrupt_mmenable), + .cfg_interrupt_msienable(cfg_interrupt_msienable), + .cfg_interrupt_msixenable(cfg_interrupt_msixenable), + .cfg_interrupt_msixfm(cfg_interrupt_msixfm), + .cfg_interrupt_stat(cfg_interrupt_stat), + .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum), + .cfg_to_turnoff(cfg_to_turnoff), + .cfg_turnoff_ok(cfg_turnoff_ok), + .cfg_bus_number(cfg_bus_number), + .cfg_device_number(cfg_device_number), + .cfg_function_number(cfg_function_number), + .cfg_pm_wake(cfg_pm_wake), + .cfg_pm_send_pme_to(cfg_pm_send_pme_to), + .cfg_ds_bus_number(cfg_ds_bus_number), + .cfg_ds_device_number(cfg_ds_device_number), + .cfg_ds_function_number(cfg_ds_function_number), + .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw), + .cfg_msg_received(cfg_msg_received), + .cfg_msg_data(cfg_msg_data), + .cfg_bridge_serr_en(cfg_bridge_serr_en), + .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse), + .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en), + .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en), + .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en), + .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en), + .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en), + .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en), + .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en), + .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received), + .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received), + .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received), + .cfg_msg_received_err_cor(cfg_msg_received_err_cor), + .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal), + .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal), + .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak), + .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme), + .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack), + .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a), + .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b), + .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c), + .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d), + .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a), + .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b), + .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c), + .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d), + .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit), + .pl_directed_link_change(pl_directed_link_change), + .pl_directed_link_width(pl_directed_link_width), + .pl_directed_link_speed(pl_directed_link_speed), + .pl_directed_link_auton(pl_directed_link_auton), + .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph), + .pl_sel_lnk_rate(pl_sel_lnk_rate), + .pl_sel_lnk_width(pl_sel_lnk_width), + .pl_ltssm_state(pl_ltssm_state), + .pl_lane_reversal_mode(pl_lane_reversal_mode), + .pl_phy_lnk_up(pl_phy_lnk_up), + .pl_tx_pm_state(pl_tx_pm_state), + .pl_rx_pm_state(pl_rx_pm_state), + .pl_link_upcfg_cap(pl_link_upcfg_cap), + .pl_link_gen2_cap(pl_link_gen2_cap), + .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported), + .pl_initial_link_width(pl_initial_link_width), + .pl_directed_change_done(pl_directed_change_done), + .pl_received_hot_rst(pl_received_hot_rst), + .pl_transmit_hot_rst(pl_transmit_hot_rst), + .pl_downstream_deemph_source(pl_downstream_deemph_source), + .cfg_err_aer_headerlog(cfg_err_aer_headerlog), + .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum), + .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set), + .cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en), + .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en), + .cfg_vc_tcvc_map(cfg_vc_tcvc_map), + .sys_clk(sys_clk), + .sys_rst_n(sys_rst_n), + .pipe_mmcm_rst_n(pipe_mmcm_rst_n), + .startup_eos_in(1'B0), + .startup_cfgclk(), + .startup_cfgmclk(), + .startup_eos(), + .startup_preq(), + .startup_clk(1'B0), + .startup_gsr(1'B0), + .startup_gts(1'B0), + .startup_keyclearb(1'B1), + .startup_pack(1'B0), + .startup_usrcclko(1'B1), + .startup_usrcclkts(1'B0), + .startup_usrdoneo(1'B0), + .startup_usrdonets(1'B1), + .icap_clk(1'B0), + .icap_csib(1'B0), + .icap_rdwrb(1'B0), + .icap_i(32'B0), + .icap_o(), + .qpll_drp_crscode(12'B0), + .qpll_drp_fsm(18'B0), + .qpll_drp_done(2'B0), + .qpll_drp_reset(2'B0), + .qpll_qplllock(2'B0), + .qpll_qplloutclk(2'B0), + .qpll_qplloutrefclk(2'B0), + .qpll_qplld(), + .qpll_qpllreset(), + .qpll_drp_clk(), + .qpll_drp_rst_n(), + .qpll_drp_ovrd(), + .qpll_drp_gen3(), + .qpll_drp_start(), + .pipe_txprbssel(3'B0), + .pipe_rxprbssel(3'B0), + .pipe_txprbsforceerr(1'B0), + .pipe_rxprbscntreset(1'B0), + .pipe_loopback(3'B0), + .pipe_rxprbserr(), + .pipe_txinhibit(4'B0), + .pipe_rst_fsm(), + .pipe_qrst_fsm(), + .pipe_rate_fsm(), + .pipe_sync_fsm_tx(), + .pipe_sync_fsm_rx(), + .pipe_drp_fsm(), + .pipe_rst_idle(), + .pipe_qrst_idle(), + .pipe_rate_idle(), + .pipe_eyescandataerror(), + .pipe_rxstatus(), + .pipe_dmonitorout(), + .pipe_cpll_lock(), + .pipe_qpll_lock(), + .pipe_rxpmaresetdone(), + .pipe_rxbufstatus(), + .pipe_txphaligndone(), + .pipe_txphinitdone(), + .pipe_txdlysresetdone(), + .pipe_rxphaligndone(), + .pipe_rxdlysresetdone(), + .pipe_rxsyncdone(), + .pipe_rxdisperr(), + .pipe_rxnotintable(), + .pipe_rxcommadet(), + .gt_ch_drp_rdy(), + .pipe_debug_1(), + .pipe_debug_2(), + .pipe_debug_3(), + .pipe_debug_4(), + .pipe_debug_5(), + .pipe_debug_6(), + .pipe_debug_7(), + .pipe_debug_8(), + .pipe_debug_9(), + .pipe_debug(), + .ext_ch_gt_drpclk(), + .ext_ch_gt_drpaddr(36'B0), + .ext_ch_gt_drpen(4'B0), + .ext_ch_gt_drpdi(64'B0), + .ext_ch_gt_drpwe(4'B0), + .ext_ch_gt_drpdo(), + .ext_ch_gt_drprdy(), + .pcie_drp_clk(pcie_drp_clk), + .pcie_drp_en(pcie_drp_en), + .pcie_drp_we(pcie_drp_we), + .pcie_drp_addr(pcie_drp_addr), + .pcie_drp_di(pcie_drp_di), + .pcie_drp_do(pcie_drp_do), + .pcie_drp_rdy(pcie_drp_rdy), + .common_commands_in(12'B0), + .pipe_rx_0_sigs(25'B0), + .pipe_rx_1_sigs(25'B0), + .pipe_rx_2_sigs(25'B0), + .pipe_rx_3_sigs(25'B0), + .pipe_rx_4_sigs(25'B0), + .pipe_rx_5_sigs(25'B0), + .pipe_rx_6_sigs(25'B0), + .pipe_rx_7_sigs(25'B0), + .common_commands_out(), + .pipe_tx_0_sigs(), + .pipe_tx_1_sigs(), + .pipe_tx_2_sigs(), + .pipe_tx_3_sigs(), + .pipe_tx_4_sigs(), + .pipe_tx_5_sigs(), + .pipe_tx_6_sigs(), + .pipe_tx_7_sigs() + ); +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0-PCIE_X0Y0.xdc b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0-PCIE_X0Y0.xdc new file mode 100644 index 0000000..5c630b4 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0-PCIE_X0Y0.xdc @@ -0,0 +1,156 @@ +##----------------------------------------------------------------------------- +## +## (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. +## +##----------------------------------------------------------------------------- +## Project : Series-7 Integrated Block for PCI Express +## File : pcie_7x_0-PCIE_X0Y0.xdc +## Version : 3.3 +# +############################################################################### +# Vivado - PCIe GUI / User Configuration +############################################################################### +# +# Family - zynq +# Part - xc7z045 +# Package - ffg900 +# Speed grade - -2 +# PCIe Block - PCIE_X0Y0 +# +# Link Speed - 2 +# Link Width - X4 +# AXIST Width - 64-bit +# AXIST Frequ - 3 +# +############################################################################### +# User Time Names / User Time Groups / Time Specs +############################################################################### + +############################################################################### +# User Physical Constraints +############################################################################### + + +############################################################################### +# Pinout and Related I/O Constraints +############################################################################### + + +############################################################################### +# Physical Constraints +############################################################################### +# +# Transceiver instance placement. This constraint selects the +# transceivers to be used, which also dictates the pinout for the +# transmit and receive differential pairs. Please refer to the +# Virtex-7 GT Transceiver User Guide (UG) for more information. +# + +# PCIe Lane 0 +set_property LOC GTXE2_CHANNEL_X0Y15 [get_cells {inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] +# PCIe Lane 1 +set_property LOC GTXE2_CHANNEL_X0Y14 [get_cells {inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] +# PCIe Lane 2 +set_property LOC GTXE2_CHANNEL_X0Y13 [get_cells {inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] +# PCIe Lane 3 +set_property LOC GTXE2_CHANNEL_X0Y12 [get_cells {inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] + + +# +# PCI Express Block placement. This constraint selects the PCI Express +# Block to be used. +# + +set_property LOC PCIE_X0Y0 [get_cells inst/pcie_top_i/pcie_7x_i/pcie_block_i] + +# +# BlockRAM placement +# +set_property LOC RAMB36_X7Y35 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[7].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X7Y36 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[6].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X7Y27 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[5].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X7Y28 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[6].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X7Y29 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[7].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X6Y37 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[5].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X6Y36 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[4].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X6Y35 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[3].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X6Y34 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[2].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X6Y33 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[1].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X6Y32 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[0].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X6Y31 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X6Y30 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[1].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X6Y29 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[2].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X6Y28 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[3].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] +set_property LOC RAMB36_X6Y27 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[4].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] + +############################################################################### +# Timing Constraints +############################################################################### +# +create_clock -name txoutclk_x0y0 -period 10 [get_pins {inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i/TXOUTCLK}] +# +# +set_false_path -through [get_pins -filter {REF_PIN_NAME=~PLPHYLNKUPN} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ * }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~PLRECEIVEDHOTRST} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ * }]] + +#------------------------------------------------------------------------------ +# Asynchronous Paths +#------------------------------------------------------------------------------ +set_false_path -through [get_pins -filter {REF_PIN_NAME=~RXELECIDLE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~TXPHINITDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~TXPHALIGNDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~TXDLYSRESETDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~RXDLYSRESETDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~RXPHALIGNDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~RXCDRLOCK} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~CFGMSGRECEIVEDPMETO} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ * }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~CPLLLOCK} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~QPLLLOCK} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]] + +############################################################################### +# End +############################################################################### diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_rx.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_rx.v new file mode 100644 index 0000000..52c3895 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_rx.v @@ -0,0 +1,212 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_axi_basic_rx.v +// Version : 3.3 +// // +// Description: // +// TRN to AXI RX module. Instantiates pipeline and null generator RX // +// submodules. // +// // +// Notes: // +// Optional notes section. // +// // +// Hierarchical: // +// axi_basic_top // +// axi_basic_rx // +// // +//----------------------------------------------------------------------------// + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_axi_basic_rx #( + parameter C_DATA_WIDTH = 128, // RX/TX interface data width + parameter C_FAMILY = "X7", // Targeted FPGA family + parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode + parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl + parameter TCQ = 1, // Clock to Q time + + // Do not override parameters below this line + parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width + parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width + ) ( + //---------------------------------------------// + // User Design I/O // + //---------------------------------------------// + + // AXI RX + //----------- + output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user + output m_axis_rx_tvalid, // RX data is valid + input m_axis_rx_tready, // RX ready for data + output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables + output m_axis_rx_tlast, // RX data is last + output [21:0] m_axis_rx_tuser, // RX user signals + + //---------------------------------------------// + // PCIe Block I/O // + //---------------------------------------------// + + // TRN RX + //----------- + input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block + input trn_rsof, // RX start of packet + input trn_reof, // RX end of packet + input trn_rsrc_rdy, // RX source ready + output trn_rdst_rdy, // RX destination ready + input trn_rsrc_dsc, // RX source discontinue + input [REM_WIDTH-1:0] trn_rrem, // RX remainder + input trn_rerrfwd, // RX error forward + input [6:0] trn_rbar_hit, // RX BAR hit + input trn_recrc_err, // RX ECRC error + + // System + //----------- + output [2:0] np_counter, // Non-posted counter + input user_clk, // user clock from block + input user_rst // user reset from block +); + + +// Wires +wire null_rx_tvalid; +wire null_rx_tlast; +wire [KEEP_WIDTH-1:0] null_rx_tkeep; +wire null_rdst_rdy; +wire [4:0] null_is_eof; + +//---------------------------------------------// +// RX Data Pipeline // +//---------------------------------------------// + +pcie_7x_0_axi_basic_rx_pipeline #( + .C_DATA_WIDTH( C_DATA_WIDTH ), + .C_FAMILY( C_FAMILY ), + .TCQ( TCQ ), + + .REM_WIDTH( REM_WIDTH ), + .KEEP_WIDTH( KEEP_WIDTH ) + +) rx_pipeline_inst ( + + // Outgoing AXI TX + //----------- + .m_axis_rx_tdata( m_axis_rx_tdata ), + .m_axis_rx_tvalid( m_axis_rx_tvalid ), + .m_axis_rx_tready( m_axis_rx_tready ), + .m_axis_rx_tkeep( m_axis_rx_tkeep ), + .m_axis_rx_tlast( m_axis_rx_tlast ), + .m_axis_rx_tuser( m_axis_rx_tuser ), + + // Incoming TRN RX + //----------- + .trn_rd( trn_rd ), + .trn_rsof( trn_rsof ), + .trn_reof( trn_reof ), + .trn_rsrc_rdy( trn_rsrc_rdy ), + .trn_rdst_rdy( trn_rdst_rdy ), + .trn_rsrc_dsc( trn_rsrc_dsc ), + .trn_rrem( trn_rrem ), + .trn_rerrfwd( trn_rerrfwd ), + .trn_rbar_hit( trn_rbar_hit ), + .trn_recrc_err( trn_recrc_err ), + + // Null Inputs + //----------- + .null_rx_tvalid( null_rx_tvalid ), + .null_rx_tlast( null_rx_tlast ), + .null_rx_tkeep( null_rx_tkeep ), + .null_rdst_rdy( null_rdst_rdy ), + .null_is_eof( null_is_eof ), + + // System + //----------- + .np_counter( np_counter ), + .user_clk( user_clk ), + .user_rst( user_rst ) +); + + + //---------------------------------------------// + // RX Null Packet Generator // + //---------------------------------------------// + +pcie_7x_0_axi_basic_rx_null_gen #( + .C_DATA_WIDTH( C_DATA_WIDTH ), + .TCQ( TCQ ), + + .KEEP_WIDTH( KEEP_WIDTH ) + + ) rx_null_gen_inst ( + + // Inputs + //----------- + .m_axis_rx_tdata( m_axis_rx_tdata ), + .m_axis_rx_tvalid( m_axis_rx_tvalid ), + .m_axis_rx_tready( m_axis_rx_tready ), + .m_axis_rx_tlast( m_axis_rx_tlast ), + .m_axis_rx_tuser( m_axis_rx_tuser ), + + // Null Outputs + //----------- + .null_rx_tvalid( null_rx_tvalid ), + .null_rx_tlast( null_rx_tlast ), + .null_rx_tkeep( null_rx_tkeep ), + .null_rdst_rdy( null_rdst_rdy ), + .null_is_eof( null_is_eof ), + + // System + //----------- + .user_clk( user_clk ), + .user_rst( user_rst ) + ); + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_rx_null_gen.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_rx_null_gen.v new file mode 100644 index 0000000..f23efe4 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_rx_null_gen.v @@ -0,0 +1,383 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_axi_basic_rx_null_gen.v +// Version : 3.3 +// // +// Description: // +// TRN to AXI RX null generator. Generates null packets for use in // +// discontinue situations. // +// // +// Notes: // +// Optional notes section. // +// // +// Hierarchical: // +// axi_basic_top // +// axi_basic_rx // +// axi_basic_rx_null_gen // +// // +//----------------------------------------------------------------------------// + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_axi_basic_rx_null_gen # ( + parameter C_DATA_WIDTH = 128, // RX/TX interface data width + parameter TCQ = 1, // Clock to Q time + + // Do not override parameters below this line + parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width + ) ( + + // AXI RX + //----------- + input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user + input m_axis_rx_tvalid, // RX data is valid + input m_axis_rx_tready, // RX ready for data + input m_axis_rx_tlast, // RX data is last + input [21:0] m_axis_rx_tuser, // RX user signals + + // Null Inputs + //----------- + output null_rx_tvalid, // NULL generated tvalid + output null_rx_tlast, // NULL generated tlast + output [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep + output null_rdst_rdy, // NULL generated rdst_rdy + output reg [4:0] null_is_eof, // NULL generated is_eof + + // System + //----------- + input user_clk, // user clock from block + input user_rst // user reset from block +); + + +localparam INTERFACE_WIDTH_DWORDS = (C_DATA_WIDTH == 128) ? 11'd4 : + (C_DATA_WIDTH == 64) ? 11'd2 : 11'd1; + +//----------------------------------------------------------------------------// +// NULL packet generator state machine // +// This state machine shadows the AXI RX interface, tracking each packet as // +// it's passed to the AXI user. When a multi-cycle packet is detected, the // +// state machine automatically generates a "null" packet. In the event of a // +// discontinue, the RX pipeline can switch over to this null packet as // +// necessary. // +//----------------------------------------------------------------------------// + +// State machine variables and states +localparam IDLE = 0; +localparam IN_PACKET = 1; +reg cur_state; +reg next_state; + +// Signals for tracking a packet on the AXI interface +reg [11:0] reg_pkt_len_counter; +reg [11:0] pkt_len_counter; +wire [11:0] pkt_len_counter_dec; +wire pkt_done; + +// Calculate packet fields, which are needed to determine total packet length. +wire [11:0] new_pkt_len; +wire [9:0] payload_len; +wire [1:0] packet_fmt; +wire packet_td; +reg [3:0] packet_overhead; + +// Misc. +wire [KEEP_WIDTH-1:0] eof_tkeep; +wire straddle_sof; +wire eof; + + +// Create signals to detect sof and eof situations. These signals vary depending +// on data width. +assign eof = m_axis_rx_tuser[21]; +generate + if(C_DATA_WIDTH == 128) begin : sof_eof_128 + assign straddle_sof = (m_axis_rx_tuser[14:13] == 2'b11); + end + else begin : sof_eof_64_32 + assign straddle_sof = 1'b0; + end +endgenerate + + +//----------------------------------------------------------------------------// +// Calculate the length of the packet being presented on the RX interface. To // +// do so, we need the relevent packet fields that impact total packet length. // +// These are: // +// - Header length: obtained from bit 1 of FMT field in 1st DWORD of header // +// - Payload length: obtained from LENGTH field in 1st DWORD of header // +// - TLP digest: obtained from TD field in 1st DWORD of header // +// - Current data: the number of bytes that have already been presented // +// on the data interface // +// // +// packet length = header + payload + tlp digest - # of DWORDS already // +// transmitted // +// // +// packet_overhead is where we calculate everything except payload. // +//----------------------------------------------------------------------------// +generate + if(C_DATA_WIDTH == 128) begin : len_calc_128 + assign packet_fmt = straddle_sof ? + m_axis_rx_tdata[94:93] : m_axis_rx_tdata[30:29]; + assign packet_td = straddle_sof ? + m_axis_rx_tdata[79] : m_axis_rx_tdata[15]; + assign payload_len = packet_fmt[1] ? + (straddle_sof ? m_axis_rx_tdata[73:64] : m_axis_rx_tdata[9:0]) : 10'h0; + + always @(*) begin + // In 128-bit mode, the amount of data currently on the interface + // depends on whether we're straddling or not. If so, 2 DWORDs have been + // seen. If not, 4 DWORDs. + case({packet_fmt[0], packet_td, straddle_sof}) + // Header + TD - Data currently on interface + 3'b0_0_0: packet_overhead = 4'd3 + 4'd0 - 4'd4; + 3'b0_0_1: packet_overhead = 4'd3 + 4'd0 - 4'd2; + 3'b0_1_0: packet_overhead = 4'd3 + 4'd1 - 4'd4; + 3'b0_1_1: packet_overhead = 4'd3 + 4'd1 - 4'd2; + 3'b1_0_0: packet_overhead = 4'd4 + 4'd0 - 4'd4; + 3'b1_0_1: packet_overhead = 4'd4 + 4'd0 - 4'd2; + 3'b1_1_0: packet_overhead = 4'd4 + 4'd1 - 4'd4; + 3'b1_1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2; + endcase + end +assign new_pkt_len = + {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len}; + end + else if(C_DATA_WIDTH == 64) begin : len_calc_64 + assign packet_fmt = m_axis_rx_tdata[30:29]; + assign packet_td = m_axis_rx_tdata[15]; + assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0; + + always @(*) begin + // 64-bit mode: no straddling, so always 2 DWORDs + case({packet_fmt[0], packet_td}) + // Header + TD - Data currently on interface + 2'b0_0: packet_overhead[1:0] = 2'b01 ;//4'd3 + 4'd0 - 4'd2; // 1 + 2'b0_1: packet_overhead[1:0] = 2'b10 ;//4'd3 + 4'd1 - 4'd2; // 2 + 2'b1_0: packet_overhead[1:0] = 2'b10 ;//4'd4 + 4'd0 - 4'd2; // 2 + 2'b1_1: packet_overhead[1:0] = 2'b11 ;//4'd4 + 4'd1 - 4'd2; // 3 + endcase + end +assign new_pkt_len = + {{10{1'b0}}, packet_overhead[1:0]} + {2'b0, payload_len}; + end + else begin : len_calc_32 + assign packet_fmt = m_axis_rx_tdata[30:29]; + assign packet_td = m_axis_rx_tdata[15]; + assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0; + + always @(*) begin + // 32-bit mode: no straddling, so always 1 DWORD + case({packet_fmt[0], packet_td}) + // Header + TD - Data currently on interface + 2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd1; + 2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd1; + 2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd1; + 2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd1; + endcase + end +assign new_pkt_len = + {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len}; + end +endgenerate + +// Now calculate actual packet length, adding the packet overhead and the +// payload length. This is signed math, so sign-extend packet_overhead. +// NOTE: a payload length of zero means 1024 DW in the PCIe spec, but this +// behavior isn't supported in our block. +//assign new_pkt_len = +// {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len}; + + +// Math signals needed in the state machine below. These are seperate wires to +// help ensure synthesis tools sre smart about optimizing them. +assign pkt_len_counter_dec = reg_pkt_len_counter - INTERFACE_WIDTH_DWORDS; +assign pkt_done = (reg_pkt_len_counter <= INTERFACE_WIDTH_DWORDS); + +//----------------------------------------------------------------------------// +// Null generator Mealy state machine. Determine outputs based on: // +// 1) current st // +// 2) current inp // +//----------------------------------------------------------------------------// +always @(*) begin + case (cur_state) + + // IDLE state: the interface is IDLE and we're waiting for a packet to + // start. If a packet starts, move to state IN_PACKET and begin tracking + // it as long as it's NOT a single cycle packet (indicated by assertion of + // eof at packet start) + IDLE: begin + if(m_axis_rx_tvalid && m_axis_rx_tready && !eof) begin + next_state = IN_PACKET; + end + else begin + next_state = IDLE; + end + + pkt_len_counter = new_pkt_len; + end + + // IN_PACKET: a mutli-cycle packet is in progress and we're tracking it. We + // are in lock-step with the AXI interface decrementing our packet length + // tracking reg, and waiting for the packet to finish. + // + // * If packet finished and a new one starts, this is a straddle situation. + // Next state is IN_PACKET (128-bit only). + // * If the current packet is done, next state is IDLE. + // * Otherwise, next state is IN_PACKET. + IN_PACKET: begin + // Straddle packet + if((C_DATA_WIDTH == 128) && straddle_sof && m_axis_rx_tvalid) begin + pkt_len_counter = new_pkt_len; + next_state = IN_PACKET; + end + + // Current packet finished + else if(m_axis_rx_tready && pkt_done) + begin + pkt_len_counter = new_pkt_len; + next_state = IDLE; + end + + // Packet in progress + else begin + if(m_axis_rx_tready) begin + // Not throttled + pkt_len_counter = pkt_len_counter_dec; + end + else begin + // Throttled + pkt_len_counter = reg_pkt_len_counter; + end + + next_state = IN_PACKET; + end + end + + default: begin + pkt_len_counter = reg_pkt_len_counter; + next_state = IDLE; + end + endcase +end + + +// Synchronous NULL packet generator state machine logic +always @(posedge user_clk) begin + if(user_rst) begin + cur_state <= #TCQ IDLE; + reg_pkt_len_counter <= #TCQ 12'h0; + end + else begin + cur_state <= #TCQ next_state; + reg_pkt_len_counter <= #TCQ pkt_len_counter; + end +end + + +// Generate tkeep/is_eof for an end-of-packet situation. +generate + if(C_DATA_WIDTH == 128) begin : strb_calc_128 + always @(*) begin + // Assign null_is_eof depending on how many DWORDs are left in the + // packet. + case(pkt_len_counter) + 10'd1: null_is_eof = 5'b10011; + 10'd2: null_is_eof = 5'b10111; + 10'd3: null_is_eof = 5'b11011; + 10'd4: null_is_eof = 5'b11111; + default: null_is_eof = 5'b00011; + endcase + end + + // tkeep not used in 128-bit interface + assign eof_tkeep = {KEEP_WIDTH{1'b0}}; + end + else if(C_DATA_WIDTH == 64) begin : strb_calc_64 + always @(*) begin + // Assign null_is_eof depending on how many DWORDs are left in the + // packet. + case(pkt_len_counter) + 10'd1: null_is_eof = 5'b10011; + 10'd2: null_is_eof = 5'b10111; + default: null_is_eof = 5'b00011; + endcase + end + + // Assign tkeep to 0xFF or 0x0F depending on how many DWORDs are left in + // the current packet. + assign eof_tkeep = { ((pkt_len_counter == 12'd2) ? 4'hF:4'h0), 4'hF }; + end + else begin : strb_calc_32 + always @(*) begin + // is_eof is either on or off for 32-bit + if(pkt_len_counter == 12'd1) begin + null_is_eof = 5'b10011; + end + else begin + null_is_eof = 5'b00011; + end + end + + // The entire DWORD is always valid in 32-bit mode, so tkeep is always 0xF + assign eof_tkeep = 4'hF; + end +endgenerate + + +// Finally, use everything we've generated to calculate our NULL outputs +assign null_rx_tvalid = 1'b1; +assign null_rx_tlast = (pkt_len_counter <= INTERFACE_WIDTH_DWORDS); +assign null_rx_tkeep = null_rx_tlast ? eof_tkeep : {KEEP_WIDTH{1'b1}}; +assign null_rdst_rdy = null_rx_tlast; + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_rx_pipeline.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_rx_pipeline.v new file mode 100644 index 0000000..2f81823 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_rx_pipeline.v @@ -0,0 +1,623 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_axi_basic_rx_pipeline.v +// Version : 3.3 +// // +// Description: // +// TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI. // +// // +// Notes: // +// Optional notes section. // +// // +// Hierarchical: // +// axi_basic_top // +// axi_basic_rx // +// axi_basic_rx_pipeline // +// // +//----------------------------------------------------------------------------// + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_axi_basic_rx_pipeline #( + parameter C_DATA_WIDTH = 128, // RX/TX interface data width + parameter C_FAMILY = "X7", // Targeted FPGA family + parameter TCQ = 1, // Clock to Q time + + // Do not override parameters below this line + parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width + parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width + ) ( + + // AXI RX + //----------- + output reg [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user + output reg m_axis_rx_tvalid, // RX data is valid + input m_axis_rx_tready, // RX ready for data + output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables + output m_axis_rx_tlast, // RX data is last + output reg [21:0] m_axis_rx_tuser, // RX user signals + + // TRN RX + //----------- + input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block + input trn_rsof, // RX start of packet + input trn_reof, // RX end of packet + input trn_rsrc_rdy, // RX source ready + output reg trn_rdst_rdy, // RX destination ready + input trn_rsrc_dsc, // RX source discontinue + input [REM_WIDTH-1:0] trn_rrem, // RX remainder + input trn_rerrfwd, // RX error forward + input [6:0] trn_rbar_hit, // RX BAR hit + input trn_recrc_err, // RX ECRC error + + // Null Inputs + //----------- + input null_rx_tvalid, // NULL generated tvalid + input null_rx_tlast, // NULL generated tlast + input [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep + input null_rdst_rdy, // NULL generated rdst_rdy + input [4:0] null_is_eof, // NULL generated is_eof + + // System + //----------- + output [2:0] np_counter, // Non-posted counter + input user_clk, // user clock from block + input user_rst // user reset from block +); + + +// Wires and regs for creating AXI signals +wire [4:0] is_sof; +wire [4:0] is_sof_prev; + +wire [4:0] is_eof; +wire [4:0] is_eof_prev; + +reg [KEEP_WIDTH-1:0] reg_tkeep; +wire [KEEP_WIDTH-1:0] tkeep; +wire [KEEP_WIDTH-1:0] tkeep_prev; + +reg reg_tlast; +wire rsrc_rdy_filtered; + +// Wires and regs for previous value buffer +wire [C_DATA_WIDTH-1:0] trn_rd_DW_swapped; +reg [C_DATA_WIDTH-1:0] trn_rd_prev; + +wire data_hold; +reg data_prev; + +reg trn_reof_prev; +reg [REM_WIDTH-1:0] trn_rrem_prev; +reg trn_rsrc_rdy_prev; +reg trn_rsrc_dsc_prev; +reg trn_rsof_prev; +reg [6:0] trn_rbar_hit_prev; +reg trn_rerrfwd_prev; +reg trn_recrc_err_prev; + +// Null packet handling signals +reg null_mux_sel; +reg trn_in_packet; +wire dsc_flag; +wire dsc_detect; +reg reg_dsc_detect; +reg trn_rsrc_dsc_d; + + +// Create "filtered" version of rsrc_rdy, where discontinued SOFs are removed. +assign rsrc_rdy_filtered = trn_rsrc_rdy && + (trn_in_packet || (trn_rsof && !trn_rsrc_dsc)); + +//----------------------------------------------------------------------------// +// Previous value buffer // +// --------------------- // +// We are inserting a pipeline stage in between TRN and AXI, which causes // +// some issues with handshaking signals m_axis_rx_tready/trn_rdst_rdy. The // +// added cycle of latency in the path causes the user design to fall behind // +// the TRN interface whenever it throttles. // +// // +// To avoid loss of data, we must keep the previous value of all trn_r* // +// signals in case the user throttles. // +//----------------------------------------------------------------------------// +always @(posedge user_clk) begin + if(user_rst) begin + trn_rd_prev <= #TCQ {C_DATA_WIDTH{1'b0}}; + trn_rsof_prev <= #TCQ 1'b0; + trn_rrem_prev <= #TCQ {REM_WIDTH{1'b0}}; + trn_rsrc_rdy_prev <= #TCQ 1'b0; + trn_rbar_hit_prev <= #TCQ 7'h00; + trn_rerrfwd_prev <= #TCQ 1'b0; + trn_recrc_err_prev <= #TCQ 1'b0; + trn_reof_prev <= #TCQ 1'b0; + trn_rsrc_dsc_prev <= #TCQ 1'b0; + end + else begin + // prev buffer works by checking trn_rdst_rdy. When trn_rdst_rdy is + // asserted, a new value is present on the interface. + if(trn_rdst_rdy) begin + trn_rd_prev <= #TCQ trn_rd_DW_swapped; + trn_rsof_prev <= #TCQ trn_rsof; + trn_rrem_prev <= #TCQ trn_rrem; + trn_rbar_hit_prev <= #TCQ trn_rbar_hit; + trn_rerrfwd_prev <= #TCQ trn_rerrfwd; + trn_recrc_err_prev <= #TCQ trn_recrc_err; + trn_rsrc_rdy_prev <= #TCQ rsrc_rdy_filtered; + trn_reof_prev <= #TCQ trn_reof; + trn_rsrc_dsc_prev <= #TCQ trn_rsrc_dsc || dsc_flag; + end + end +end + + +//----------------------------------------------------------------------------// +// Create TDATA // +//----------------------------------------------------------------------------// + +// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN +// 128-bit: 64-bit: 32-bit: +// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0 +// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0 +// TRN DW2 maps to AXI DW1 +// TRN DW3 maps to AXI DW0 +generate + if(C_DATA_WIDTH == 128) begin : rd_DW_swap_128 + assign trn_rd_DW_swapped = {trn_rd[31:0], + trn_rd[63:32], + trn_rd[95:64], + trn_rd[127:96]}; + end + else if(C_DATA_WIDTH == 64) begin : rd_DW_swap_64 + assign trn_rd_DW_swapped = {trn_rd[31:0], trn_rd[63:32]}; + end + else begin : rd_DW_swap_32 + assign trn_rd_DW_swapped = trn_rd; + end +endgenerate + + +// Create special buffer which locks in the proper value of TDATA depending +// on whether the user is throttling or not. This buffer has three states: +// +// HOLD state: TDATA maintains its current value +// - the user has throttled the PCIe block +// PREVIOUS state: the buffer provides the previous value on trn_rd +// - the user has finished throttling, and is a little behind +// the PCIe block +// CURRENT state: the buffer passes the current value on trn_rd +// - the user is caught up and ready to receive the latest +// data from the PCIe block +always @(posedge user_clk) begin + if(user_rst) begin + m_axis_rx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}}; + end + else begin + if(!data_hold) begin + // PREVIOUS state + if(data_prev) begin + m_axis_rx_tdata <= #TCQ trn_rd_prev; + end + + // CURRENT state + else begin + m_axis_rx_tdata <= #TCQ trn_rd_DW_swapped; + end + end + // else HOLD state + end +end + +// Logic to instruct pipeline to hold its value +assign data_hold = (!m_axis_rx_tready && m_axis_rx_tvalid); + +// Logic to instruct pipeline to use previous bus values. Always use previous +// value after holding a value. +always @(posedge user_clk) begin + if(user_rst) begin + data_prev <= #TCQ 1'b0; + end + else begin + data_prev <= #TCQ data_hold; + end +end + + +//----------------------------------------------------------------------------// +// Create TVALID, TLAST, tkeep, TUSER // +// ----------------------------------- // +// Use the same strategy for these signals as for TDATA, except here we need // +// an extra provision for null packets. // +//----------------------------------------------------------------------------// +always @(posedge user_clk) begin + if(user_rst) begin + m_axis_rx_tvalid <= #TCQ 1'b0; + reg_tlast <= #TCQ 1'b0; + reg_tkeep <= #TCQ {KEEP_WIDTH{1'b1}}; + m_axis_rx_tuser <= #TCQ 22'h0; + end + else begin + if(!data_hold) begin + // If in a null packet, use null generated value + if(null_mux_sel) begin + m_axis_rx_tvalid <= #TCQ null_rx_tvalid; + reg_tlast <= #TCQ null_rx_tlast; + reg_tkeep <= #TCQ null_rx_tkeep; + m_axis_rx_tuser <= #TCQ {null_is_eof, 17'h0000}; + end + + // PREVIOUS state + else if(data_prev) begin + m_axis_rx_tvalid <= #TCQ (trn_rsrc_rdy_prev || dsc_flag); + reg_tlast <= #TCQ trn_reof_prev; + reg_tkeep <= #TCQ tkeep_prev; + m_axis_rx_tuser <= #TCQ {is_eof_prev, // TUSER bits [21:17] + 2'b00, // TUSER bits [16:15] + is_sof_prev, // TUSER bits [14:10] + 1'b0, // TUSER bit [9] + trn_rbar_hit_prev, // TUSER bits [8:2] + trn_rerrfwd_prev, // TUSER bit [1] + trn_recrc_err_prev}; // TUSER bit [0] + end + + // CURRENT state + else begin + m_axis_rx_tvalid <= #TCQ (rsrc_rdy_filtered || dsc_flag); + reg_tlast <= #TCQ trn_reof; + reg_tkeep <= #TCQ tkeep; + m_axis_rx_tuser <= #TCQ {is_eof, // TUSER bits [21:17] + 2'b00, // TUSER bits [16:15] + is_sof, // TUSER bits [14:10] + 1'b0, // TUSER bit [9] + trn_rbar_hit, // TUSER bits [8:2] + trn_rerrfwd, // TUSER bit [1] + trn_recrc_err}; // TUSER bit [0] + end + end + // else HOLD state + end +end + +// Hook up TLAST and tkeep depending on interface width +generate + // For 128-bit interface, don't pass TLAST and tkeep to user (is_eof and + // is_data passed to user instead). reg_tlast is still used internally. + if(C_DATA_WIDTH == 128) begin : tlast_tkeep_hookup_128 + assign m_axis_rx_tlast = 1'b0; + assign m_axis_rx_tkeep = {KEEP_WIDTH{1'b1}}; + end + + // For 64/32-bit interface, pass TLAST to user. + else begin : tlast_tkeep_hookup_64_32 + assign m_axis_rx_tlast = reg_tlast; + assign m_axis_rx_tkeep = reg_tkeep; + end +endgenerate + + +//----------------------------------------------------------------------------// +// Create tkeep // +// ------------ // +// Convert RREM to STRB. Here, we are converting the encoding method for the // +// location of the EOF from TRN flavor (rrem) to AXI (tkeep). // +// // +// NOTE: for each configuration, we need two values of tkeep, the current and // +// previous values. The need for these two values is described below. // +//----------------------------------------------------------------------------// +generate + if(C_DATA_WIDTH == 128) begin : rrem_to_tkeep_128 + // TLAST and tkeep not used in 128-bit interface. is_sof and is_eof used + // instead. + assign tkeep = 16'h0000; + assign tkeep_prev = 16'h0000; + end + else if(C_DATA_WIDTH == 64) begin : rrem_to_tkeep_64 + // 64-bit interface: contains 2 DWORDs per cycle, for a total of 8 bytes + // - tkeep has only two possible values here, 0xFF or 0x0F + assign tkeep = trn_rrem ? 8'hFF : 8'h0F; + assign tkeep_prev = trn_rrem_prev ? 8'hFF : 8'h0F; + end + else begin : rrem_to_tkeep_32 + // 32-bit interface: contains 1 DWORD per cycle, for a total of 4 bytes + // - tkeep is always 0xF in this case, due to the nature of the PCIe block + assign tkeep = 4'hF; + assign tkeep_prev = 4'hF; + end +endgenerate + + +//----------------------------------------------------------------------------// +// Create is_sof // +// ------------- // +// is_sof is a signal to the user indicating the location of SOF in TDATA . // +// Due to inherent 64-bit alignment of packets from the block, the only // +// possible values are: // +// Value Valid data widths // +// 5'b11000 (sof @ byte 8) 128 // +// 5'b10000 (sof @ byte 0) 128, 64, 32 // +// 5'b00000 (sof not present) 128, 64, 32 // +//----------------------------------------------------------------------------// +generate + if(C_DATA_WIDTH == 128) begin : is_sof_128 + assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable + (trn_rsof && !trn_rrem[1]), // bit 3: sof @ byte 8? + 3'b000}; // bit 2-0: hardwired 0 + + assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4 + (trn_rsof_prev && !trn_rrem_prev[1]), // bit 3 + 3'b000}; // bit 2-0 + end + else begin : is_sof_64_32 + assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable + 4'b0000}; // bit 3-0: hardwired 0 + + assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4 + 4'b0000}; // bit 3-0 + end +endgenerate + + +//----------------------------------------------------------------------------// +// Create is_eof // +// ------------- // +// is_eof is a signal to the user indicating the location of EOF in TDATA . // +// Due to DWORD granularity of packets from the block, the only // +// possible values are: // +// Value Valid data widths // +// 5'b11111 (eof @ byte 15) 128 // +// 5'b11011 (eof @ byte 11) 128 // +// 5'b10111 (eof @ byte 7) 128, 64 // +// 5'b10011 (eof @ byte 3)` 128, 64, 32 // +// 5'b00011 (eof not present) 128, 64, 32 // +//----------------------------------------------------------------------------// +generate + if(C_DATA_WIDTH == 128) begin : is_eof_128 + assign is_eof = {trn_reof, // bit 4: enable + trn_rrem, // bit 3-2: encoded eof loc rom block + 2'b11}; // bit 1-0: hardwired 1 + + assign is_eof_prev = {trn_reof_prev, // bit 4: enable + trn_rrem_prev, // bit 3-2: encoded eof loc from block + 2'b11}; // bit 1-0: hardwired 1 + end + else if(C_DATA_WIDTH == 64) begin : is_eof_64 + assign is_eof = {trn_reof, // bit 4: enable + 1'b0, // bit 3: hardwired 0 + trn_rrem, // bit 2: encoded eof loc from block + 2'b11}; // bit 1-0: hardwired 1 + + assign is_eof_prev = {trn_reof_prev, // bit 4: enable + 1'b0, // bit 3: hardwired 0 + trn_rrem_prev, // bit 2: encoded eof loc from block + 2'b11}; // bit 1-0: hardwired 1 + end + else begin : is_eof_32 + assign is_eof = {trn_reof, // bit 4: enable + 4'b0011}; // bit 3-0: hardwired to byte 3 + + assign is_eof_prev = {trn_reof_prev, // bit 4: enable + 4'b0011}; // bit 3-0: hardwired to byte 3 + end +endgenerate + + + +//----------------------------------------------------------------------------// +// Create trn_rdst_rdy // +//----------------------------------------------------------------------------// +always @(posedge user_clk) begin + if(user_rst) begin + trn_rdst_rdy <= #TCQ 1'b0; + end + else begin + // If in a null packet, use null generated value + if(null_mux_sel && m_axis_rx_tready) begin + trn_rdst_rdy <= #TCQ null_rdst_rdy; + end + + // If a discontinue needs to be serviced, throttle the block until we are + // ready to pad out the packet. + else if(dsc_flag) begin + trn_rdst_rdy <= #TCQ 1'b0; + end + + // If in a packet, pass user back-pressure directly to block + else if(m_axis_rx_tvalid) begin + trn_rdst_rdy <= #TCQ m_axis_rx_tready; + end + + // If idle, default to no back-pressure. We need to default to the + // "ready to accept data" state to make sure we catch the first + // clock of data of a new packet. + else begin + trn_rdst_rdy <= #TCQ 1'b1; + end + end +end + +//----------------------------------------------------------------------------// +// Create null_mux_sel // +// null_mux_sel is the signal used to detect a discontinue situation and // +// mux in the null packet generated in rx_null_gen. Only mux in null data // +// when not at the beginningof a packet. SOF discontinues do not require // +// padding, as the whole packet is simply squashed instead. // +//----------------------------------------------------------------------------// +always @(posedge user_clk) begin + if(user_rst) begin + null_mux_sel <= #TCQ 1'b0; + end + else begin + // NULL packet done + if(null_mux_sel && null_rx_tlast && m_axis_rx_tready) + begin + null_mux_sel <= #TCQ 1'b0; + end + + // Discontinue detected and we're in packet, so switch to NULL packet + else if(dsc_flag && !data_hold) begin + null_mux_sel <= #TCQ 1'b1; + end + end +end + + +//----------------------------------------------------------------------------// +// Create discontinue tracking signals // +//----------------------------------------------------------------------------// +// Create signal trn_in_packet, which is needed to validate trn_rsrc_dsc. We +// should ignore trn_rsrc_dsc when it's asserted out-of-packet. +always @(posedge user_clk) begin + if(user_rst) begin + trn_in_packet <= #TCQ 1'b0; + end + else begin + if(trn_rsof && !trn_reof && rsrc_rdy_filtered && trn_rdst_rdy) + begin + trn_in_packet <= #TCQ 1'b1; + end + else if(trn_rsrc_dsc) begin + trn_in_packet <= #TCQ 1'b0; + end + else if(trn_reof && !trn_rsof && trn_rsrc_rdy && trn_rdst_rdy) begin + trn_in_packet <= #TCQ 1'b0; + end + end +end + + +// Create dsc_flag, which identifies and stores mid-packet discontinues that +// require null packet padding. This signal is edge sensitive to trn_rsrc_dsc, +// to make sure we don't service the same dsc twice in the event that +// trn_rsrc_dsc stays asserted for longer than it takes to pad out the packet. +assign dsc_detect = trn_rsrc_dsc && !trn_rsrc_dsc_d && trn_in_packet && + (!trn_rsof || trn_reof) && !(trn_rdst_rdy && trn_reof); + +always @(posedge user_clk) begin + if(user_rst) begin + reg_dsc_detect <= #TCQ 1'b0; + trn_rsrc_dsc_d <= #TCQ 1'b0; + end + else begin + if(dsc_detect) begin + reg_dsc_detect <= #TCQ 1'b1; + end + else if(null_mux_sel) begin + reg_dsc_detect <= #TCQ 1'b0; + end + + trn_rsrc_dsc_d <= #TCQ trn_rsrc_dsc; + end +end + +assign dsc_flag = dsc_detect || reg_dsc_detect; + + + +//----------------------------------------------------------------------------// +// Create np_counter (V6 128-bit only). This counter tells the V6 128-bit // +// interface core how many NP packets have left the RX pipeline. The V6 // +// 128-bit interface uses this count to perform rnp_ok modulation. // +//----------------------------------------------------------------------------// +generate + if(C_FAMILY == "V6" && C_DATA_WIDTH == 128) begin : np_cntr_to_128_enabled + reg [2:0] reg_np_counter; + + // Look for NP packets beginning on lower (i.e. unaligned) start + wire mrd_lower = (!(|m_axis_rx_tdata[92:88]) && !m_axis_rx_tdata[94]); + wire mrd_lk_lower = (m_axis_rx_tdata[92:88] == 5'b00001); + wire io_rdwr_lower = (m_axis_rx_tdata[92:88] == 5'b00010); + wire cfg_rdwr_lower = (m_axis_rx_tdata[92:89] == 4'b0010); + wire atomic_lower = ((&m_axis_rx_tdata[91:90]) && m_axis_rx_tdata[94]); + + wire np_pkt_lower = (mrd_lower || + mrd_lk_lower || + io_rdwr_lower || + cfg_rdwr_lower || + atomic_lower) && m_axis_rx_tuser[13]; + + // Look for NP packets beginning on upper (i.e. aligned) start + wire mrd_upper = (!(|m_axis_rx_tdata[28:24]) && !m_axis_rx_tdata[30]); + wire mrd_lk_upper = (m_axis_rx_tdata[28:24] == 5'b00001); + wire io_rdwr_upper = (m_axis_rx_tdata[28:24] == 5'b00010); + wire cfg_rdwr_upper = (m_axis_rx_tdata[28:25] == 4'b0010); + wire atomic_upper = ((&m_axis_rx_tdata[27:26]) && m_axis_rx_tdata[30]); + + wire np_pkt_upper = (mrd_upper || + mrd_lk_upper || + io_rdwr_upper || + cfg_rdwr_upper || + atomic_upper) && !m_axis_rx_tuser[13]; + + wire pkt_accepted = + m_axis_rx_tuser[14] && m_axis_rx_tready && m_axis_rx_tvalid; + + // Increment counter whenever an NP packet leaves the RX pipeline + always @(posedge user_clk) begin + if (user_rst) begin + reg_np_counter <= #TCQ 0; + end + else begin + if((np_pkt_lower || np_pkt_upper) && pkt_accepted) + begin + reg_np_counter <= #TCQ reg_np_counter + 3'h1; + end + end + end + + assign np_counter = reg_np_counter; + end + else begin : np_cntr_to_128_disabled + assign np_counter = 3'h0; + end +endgenerate + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_top.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_top.v new file mode 100644 index 0000000..f180020 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_top.v @@ -0,0 +1,282 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_axi_basic_top.v +// Version : 3.3 +// // +// Description: // +// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. // +// // +// Notes: // +// Optional notes section. // +// // +// Hierarchical: // +// axi_basic_top // +// // +//----------------------------------------------------------------------------// + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_axi_basic_top #( + parameter C_DATA_WIDTH = 128, // RX/TX interface data width + parameter C_FAMILY = "X7", // Targeted FPGA family + parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode + parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl + parameter TCQ = 1, // Clock to Q time + + // Do not override parameters below this line + parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width + parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width + ) ( + //---------------------------------------------// + // User Design I/O // + //---------------------------------------------// + + // AXI TX + //----------- + input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user + input s_axis_tx_tvalid, // TX data is valid + output s_axis_tx_tready, // TX ready for data + input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables + input s_axis_tx_tlast, // TX data is last + input [3:0] s_axis_tx_tuser, // TX user signals + + // AXI RX + //----------- + output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user + output m_axis_rx_tvalid, // RX data is valid + input m_axis_rx_tready, // RX ready for data + output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables + output m_axis_rx_tlast, // RX data is last + output [21:0] m_axis_rx_tuser, // RX user signals + + // User Misc. + //----------- + input user_turnoff_ok, // Turnoff OK from user + input user_tcfg_gnt, // Send cfg OK from user + + //---------------------------------------------// + // PCIe Block I/O // + //---------------------------------------------// + + // TRN TX + //----------- + output [C_DATA_WIDTH-1:0] trn_td, // TX data from block + output trn_tsof, // TX start of packet + output trn_teof, // TX end of packet + output trn_tsrc_rdy, // TX source ready + input trn_tdst_rdy, // TX destination ready + output trn_tsrc_dsc, // TX source discontinue + output [REM_WIDTH-1:0] trn_trem, // TX remainder + output trn_terrfwd, // TX error forward + output trn_tstr, // TX streaming enable + input [5:0] trn_tbuf_av, // TX buffers available + output trn_tecrc_gen, // TX ECRC generate + + // TRN RX + //----------- + input [127:0] trn_rd, // RX data from block + input trn_rsof, // RX start of packet + input trn_reof, // RX end of packet + input trn_rsrc_rdy, // RX source ready + output trn_rdst_rdy, // RX destination ready + input trn_rsrc_dsc, // RX source discontinue + input [1:0] trn_rrem, // RX remainder + input trn_rerrfwd, // RX error forward + input [6:0] trn_rbar_hit, // RX BAR hit + input trn_recrc_err, // RX ECRC error + + // TRN Misc. + //----------- + input trn_tcfg_req, // TX config request + output trn_tcfg_gnt, // RX config grant + input trn_lnk_up, // PCIe link up + + // 7 Series/Virtex6 PM + //----------- + input [2:0] cfg_pcie_link_state, // Encoded PCIe link state + + // Virtex6 PM + //----------- + input cfg_pm_send_pme_to, // PM send PME turnoff msg + input [1:0] cfg_pmcsr_powerstate, // PMCSR power state + input [31:0] trn_rdllp_data, // RX DLLP data + input trn_rdllp_src_rdy, // RX DLLP source ready + + // Virtex6/Spartan6 PM + //----------- + input cfg_to_turnoff, // Turnoff request + output cfg_turnoff_ok, // Turnoff grant + + // System + //----------- + output [2:0] np_counter, // Non-posted counter + input user_clk, // user clock from block + input user_rst // user reset from block +); + + +//---------------------------------------------// +// RX Data Pipeline // +//---------------------------------------------// + +pcie_7x_0_axi_basic_rx #( + .C_DATA_WIDTH( C_DATA_WIDTH ), + .C_FAMILY( C_FAMILY ), + + .TCQ( TCQ ), + .REM_WIDTH( REM_WIDTH ), + .KEEP_WIDTH( KEEP_WIDTH ) +) rx_inst ( + + // Outgoing AXI TX + //----------- + .m_axis_rx_tdata( m_axis_rx_tdata ), + .m_axis_rx_tvalid( m_axis_rx_tvalid ), + .m_axis_rx_tready( m_axis_rx_tready ), + .m_axis_rx_tkeep( m_axis_rx_tkeep ), + .m_axis_rx_tlast( m_axis_rx_tlast ), + .m_axis_rx_tuser( m_axis_rx_tuser ), + + // Incoming TRN RX + //----------- + .trn_rd( trn_rd[C_DATA_WIDTH-1:0] ), + .trn_rsof( trn_rsof ), + .trn_reof( trn_reof ), + .trn_rsrc_rdy( trn_rsrc_rdy ), + .trn_rdst_rdy( trn_rdst_rdy ), + .trn_rsrc_dsc( trn_rsrc_dsc ), + .trn_rrem( trn_rrem[REM_WIDTH-1:0] ), + .trn_rerrfwd( trn_rerrfwd ), + .trn_rbar_hit( trn_rbar_hit ), + .trn_recrc_err( trn_recrc_err ), + + // System + //----------- + .np_counter( np_counter ), + .user_clk( user_clk ), + .user_rst( user_rst ) +); + + + +//---------------------------------------------// +// TX Data Pipeline // +//---------------------------------------------// + +pcie_7x_0_axi_basic_tx #( + .C_DATA_WIDTH( C_DATA_WIDTH ), + .C_FAMILY( C_FAMILY ), + .C_ROOT_PORT( C_ROOT_PORT ), + .C_PM_PRIORITY( C_PM_PRIORITY ), + + .TCQ( TCQ ), + .REM_WIDTH( REM_WIDTH ), + .KEEP_WIDTH( KEEP_WIDTH ) +) tx_inst ( + + // Incoming AXI RX + //----------- + .s_axis_tx_tdata( s_axis_tx_tdata ), + .s_axis_tx_tvalid( s_axis_tx_tvalid ), + .s_axis_tx_tready( s_axis_tx_tready ), + .s_axis_tx_tkeep( s_axis_tx_tkeep ), + .s_axis_tx_tlast( s_axis_tx_tlast ), + .s_axis_tx_tuser( s_axis_tx_tuser ), + + // User Misc. + //----------- + .user_turnoff_ok( user_turnoff_ok ), + .user_tcfg_gnt( user_tcfg_gnt ), + + // Outgoing TRN TX + //----------- + .trn_td( trn_td ), + .trn_tsof( trn_tsof ), + .trn_teof( trn_teof ), + .trn_tsrc_rdy( trn_tsrc_rdy ), + .trn_tdst_rdy( trn_tdst_rdy ), + .trn_tsrc_dsc( trn_tsrc_dsc ), + .trn_trem( trn_trem ), + .trn_terrfwd( trn_terrfwd ), + .trn_tstr( trn_tstr ), + .trn_tbuf_av( trn_tbuf_av ), + .trn_tecrc_gen( trn_tecrc_gen ), + + // TRN Misc. + //----------- + .trn_tcfg_req( trn_tcfg_req ), + .trn_tcfg_gnt( trn_tcfg_gnt ), + .trn_lnk_up( trn_lnk_up ), + + // 7 Series/Virtex6 PM + //----------- + .cfg_pcie_link_state( cfg_pcie_link_state ), + + // Virtex6 PM + //----------- + .cfg_pm_send_pme_to( cfg_pm_send_pme_to ), + .cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ), + .trn_rdllp_data( trn_rdllp_data ), + .trn_rdllp_src_rdy( trn_rdllp_src_rdy ), + + // Spartan6 PM + //----------- + .cfg_to_turnoff( cfg_to_turnoff ), + .cfg_turnoff_ok( cfg_turnoff_ok ), + + // System + //----------- + .user_clk( user_clk ), + .user_rst( user_rst ) +); + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_tx.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_tx.v new file mode 100644 index 0000000..b1c1899 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_tx.v @@ -0,0 +1,260 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_axi_basic_tx.v +// Version : 3.3 +// // +// Description: // +// AXI to TRN TX module. Instantiates pipeline and throttle control TX // +// submodules. // +// // +// Notes: // +// Optional notes section. // +// // +// Hierarchical: // +// axi_basic_top // +// axi_basic_tx // +// // +//----------------------------------------------------------------------------// + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_axi_basic_tx #( + parameter C_DATA_WIDTH = 128, // RX/TX interface data width + parameter C_FAMILY = "X7", // Targeted FPGA family + parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode + parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl + parameter TCQ = 1, // Clock to Q time + + // Do not override parameters below this line + parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width + parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width + ) ( + //---------------------------------------------// + // User Design I/O // + //---------------------------------------------// + + // AXI TX + //----------- + input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user + input s_axis_tx_tvalid, // TX data is valid + output s_axis_tx_tready, // TX ready for data + input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables + input s_axis_tx_tlast, // TX data is last + input [3:0] s_axis_tx_tuser, // TX user signals + + // User Misc. + //----------- + input user_turnoff_ok, // Turnoff OK from user + input user_tcfg_gnt, // Send cfg OK from user + + //---------------------------------------------// + // PCIe Block I/O // + //---------------------------------------------// + + // TRN TX + //----------- + output [C_DATA_WIDTH-1:0] trn_td, // TX data from block + output trn_tsof, // TX start of packet + output trn_teof, // TX end of packet + output trn_tsrc_rdy, // TX source ready + input trn_tdst_rdy, // TX destination ready + output trn_tsrc_dsc, // TX source discontinue + output [REM_WIDTH-1:0] trn_trem, // TX remainder + output trn_terrfwd, // TX error forward + output trn_tstr, // TX streaming enable + input [5:0] trn_tbuf_av, // TX buffers available + output trn_tecrc_gen, // TX ECRC generate + + // TRN Misc. + //----------- + input trn_tcfg_req, // TX config request + output trn_tcfg_gnt, // RX config grant + input trn_lnk_up, // PCIe link up + + // 7 Series/Virtex6 PM + //----------- + input [2:0] cfg_pcie_link_state, // Encoded PCIe link state + + // Virtex6 PM + //----------- + input cfg_pm_send_pme_to, // PM send PME turnoff msg + input [1:0] cfg_pmcsr_powerstate, // PMCSR power state + input [31:0] trn_rdllp_data, // RX DLLP data + input trn_rdllp_src_rdy, // RX DLLP source ready + + // Virtex6/Spartan6 PM + //----------- + input cfg_to_turnoff, // Turnoff request + output cfg_turnoff_ok, // Turnoff grant + + // System + //----------- + input user_clk, // user clock from block + input user_rst // user reset from block +); + + +wire tready_thrtl; + +//---------------------------------------------// +// TX Data Pipeline // +//---------------------------------------------// + +pcie_7x_0_axi_basic_tx_pipeline #( + .C_DATA_WIDTH( C_DATA_WIDTH ), + .C_PM_PRIORITY( C_PM_PRIORITY ), + .TCQ( TCQ ), + + .REM_WIDTH( REM_WIDTH ), + .KEEP_WIDTH( KEEP_WIDTH ) +) tx_pipeline_inst ( + + // Incoming AXI RX + //----------- + .s_axis_tx_tdata( s_axis_tx_tdata ), + .s_axis_tx_tready( s_axis_tx_tready ), + .s_axis_tx_tvalid( s_axis_tx_tvalid ), + .s_axis_tx_tkeep( s_axis_tx_tkeep ), + .s_axis_tx_tlast( s_axis_tx_tlast ), + .s_axis_tx_tuser( s_axis_tx_tuser ), + + // Outgoing TRN TX + //----------- + .trn_td( trn_td ), + .trn_tsof( trn_tsof ), + .trn_teof( trn_teof ), + .trn_tsrc_rdy( trn_tsrc_rdy ), + .trn_tdst_rdy( trn_tdst_rdy ), + .trn_tsrc_dsc( trn_tsrc_dsc ), + .trn_trem( trn_trem ), + .trn_terrfwd( trn_terrfwd ), + .trn_tstr( trn_tstr ), + .trn_tecrc_gen( trn_tecrc_gen ), + .trn_lnk_up( trn_lnk_up ), + + // System + //----------- + .tready_thrtl( tready_thrtl ), + .user_clk( user_clk ), + .user_rst( user_rst ) +); + + +//---------------------------------------------// +// TX Throttle Controller // +//---------------------------------------------// + +generate + if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled +pcie_7x_0_axi_basic_tx_thrtl_ctl #( + .C_DATA_WIDTH( C_DATA_WIDTH ), + .C_FAMILY( C_FAMILY ), + .C_ROOT_PORT( C_ROOT_PORT ), + .TCQ( TCQ ) + + ) tx_thrl_ctl_inst ( + + // Outgoing AXI TX + //----------- + .s_axis_tx_tdata( s_axis_tx_tdata ), + .s_axis_tx_tvalid( s_axis_tx_tvalid ), + .s_axis_tx_tuser( s_axis_tx_tuser ), + .s_axis_tx_tlast( s_axis_tx_tlast ), + + // User Misc. + //----------- + .user_turnoff_ok( user_turnoff_ok ), + .user_tcfg_gnt( user_tcfg_gnt ), + + // Incoming TRN RX + //----------- + .trn_tbuf_av( trn_tbuf_av ), + .trn_tdst_rdy( trn_tdst_rdy ), + + // TRN Misc. + //----------- + .trn_tcfg_req( trn_tcfg_req ), + .trn_tcfg_gnt( trn_tcfg_gnt ), + .trn_lnk_up( trn_lnk_up ), + + // 7 Seriesq/Virtex6 PM + //----------- + .cfg_pcie_link_state( cfg_pcie_link_state ), + + // Virtex6 PM + //----------- + .cfg_pm_send_pme_to( cfg_pm_send_pme_to ), + .cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ), + .trn_rdllp_data( trn_rdllp_data ), + .trn_rdllp_src_rdy( trn_rdllp_src_rdy ), + + // Spartan6 PM + //----------- + .cfg_to_turnoff( cfg_to_turnoff ), + .cfg_turnoff_ok( cfg_turnoff_ok ), + + // System + //----------- + .tready_thrtl( tready_thrtl ), + .user_clk( user_clk ), + .user_rst( user_rst ) + ); + end + else begin : thrtl_ctl_disabled + assign tready_thrtl = 1'b0; + + assign cfg_turnoff_ok = user_turnoff_ok; + assign trn_tcfg_gnt = user_tcfg_gnt; + end +endgenerate + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_tx_pipeline.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_tx_pipeline.v new file mode 100644 index 0000000..efa08af --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_tx_pipeline.v @@ -0,0 +1,543 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_axi_basic_tx_pipeline.v +// Version : 3.3 +// // +// Description: // +// AXI to TRN TX pipeline. Converts transmitted data from AXI protocol to // +// TRN. // +// // +// Notes: // +// Optional notes section. // +// // +// Hierarchical: // +// axi_basic_top // +// axi_basic_tx // +// axi_basic_tx_pipeline // +// // +//----------------------------------------------------------------------------// + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_axi_basic_tx_pipeline #( + parameter C_DATA_WIDTH = 128, // RX/TX interface data width + parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl + parameter TCQ = 1, // Clock to Q time + + // Do not override parameters below this line + parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width + parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width + ) ( + //---------------------------------------------// + // User Design I/O // + //---------------------------------------------// + + // AXI TX + //----------- + input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user + input s_axis_tx_tvalid, // TX data is valid + output s_axis_tx_tready, // TX ready for data + input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables + input s_axis_tx_tlast, // TX data is last + input [3:0] s_axis_tx_tuser, // TX user signals + + //---------------------------------------------// + // PCIe Block I/O // + //---------------------------------------------// + + // TRN TX + //----------- + output [C_DATA_WIDTH-1:0] trn_td, // TX data from block + output trn_tsof, // TX start of packet + output trn_teof, // TX end of packet + output trn_tsrc_rdy, // TX source ready + input trn_tdst_rdy, // TX destination ready + output trn_tsrc_dsc, // TX source discontinue + output [REM_WIDTH-1:0] trn_trem, // TX remainder + output trn_terrfwd, // TX error forward + output trn_tstr, // TX streaming enable + output trn_tecrc_gen, // TX ECRC generate + input trn_lnk_up, // PCIe link up + + // System + //----------- + input tready_thrtl, // TREADY from thrtl ctl + input user_clk, // user clock from block + input user_rst // user reset from block +); + + +// Input register stage +reg [C_DATA_WIDTH-1:0] reg_tdata; +reg reg_tvalid; +reg [KEEP_WIDTH-1:0] reg_tkeep; +reg [3:0] reg_tuser; +reg reg_tlast; +reg reg_tready; + +// Pipeline utility signals +reg trn_in_packet; +reg axi_in_packet; +reg flush_axi; +wire disable_trn; +reg reg_disable_trn; + +wire axi_beat_live = s_axis_tx_tvalid && s_axis_tx_tready; +wire axi_end_packet = axi_beat_live && s_axis_tx_tlast; + + +//----------------------------------------------------------------------------// +// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN. // +// 128-bit: 64-bit: 32-bit: // +// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0 // +// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0 // +// TRN DW2 maps to AXI DW1 // +// TRN DW3 maps to AXI DW0 // +//----------------------------------------------------------------------------// +generate + if(C_DATA_WIDTH == 128) begin : td_DW_swap_128 + assign trn_td = {reg_tdata[31:0], + reg_tdata[63:32], + reg_tdata[95:64], + reg_tdata[127:96]}; + end + else if(C_DATA_WIDTH == 64) begin : td_DW_swap_64 + assign trn_td = {reg_tdata[31:0], reg_tdata[63:32]}; + end + else begin : td_DW_swap_32 + assign trn_td = reg_tdata; + end +endgenerate + + +//----------------------------------------------------------------------------// +// Create trn_tsof. If we're not currently in a packet and TVALID goes high, // +// assert TSOF. // +//----------------------------------------------------------------------------// +assign trn_tsof = reg_tvalid && !trn_in_packet; + + +//----------------------------------------------------------------------------// +// Create trn_in_packet. This signal tracks if the TRN interface is currently // +// in the middle of a packet, which is needed to generate trn_tsof // +//----------------------------------------------------------------------------// +always @(posedge user_clk) begin + if(user_rst) begin + trn_in_packet <= #TCQ 1'b0; + end + else begin + if(trn_tsof && trn_tsrc_rdy && trn_tdst_rdy && !trn_teof) begin + trn_in_packet <= #TCQ 1'b1; + end + else if((trn_in_packet && trn_teof && trn_tsrc_rdy) || !trn_lnk_up) begin + trn_in_packet <= #TCQ 1'b0; + end + end +end + + +//----------------------------------------------------------------------------// +// Create axi_in_packet. This signal tracks if the AXI interface is currently // +// in the middle of a packet, which is needed in case the link goes down. // +//----------------------------------------------------------------------------// +always @(posedge user_clk) begin + if(user_rst) begin + axi_in_packet <= #TCQ 1'b0; + end + else begin + if(axi_beat_live && !s_axis_tx_tlast) begin + axi_in_packet <= #TCQ 1'b1; + end + else if(axi_beat_live) begin + axi_in_packet <= #TCQ 1'b0; + end + end +end + + +//----------------------------------------------------------------------------// +// Create disable_trn. This signal asserts when the link goes down and // +// triggers the deassertiong of trn_tsrc_rdy. The deassertion of disable_trn // +// depends on C_PM_PRIORITY, as described below. // +//----------------------------------------------------------------------------// +generate + // In the C_PM_PRIORITY pipeline, we disable the TRN interfacefrom the time + // the link goes down until the the AXI interface is ready to accept packets + // again (via assertion of TREADY). By waiting for TREADY, we allow the + // previous value buffer to fill, so we're ready for any throttling by the + // user or the block. + if(C_PM_PRIORITY == "TRUE") begin : pm_priority_trn_flush + always @(posedge user_clk) begin + if(user_rst) begin + reg_disable_trn <= #TCQ 1'b1; + end + else begin + // When the link goes down, disable the TRN interface. + if(!trn_lnk_up) + begin + reg_disable_trn <= #TCQ 1'b1; + end + + // When the link comes back up and the AXI interface is ready, we can + // release the pipeline and return to normal operation. + else if(!flush_axi && s_axis_tx_tready) begin + reg_disable_trn <= #TCQ 1'b0; + end + end + end + + assign disable_trn = reg_disable_trn; + end + + // In the throttle-controlled pipeline, we don't have a previous value buffer. + // The throttle control mechanism handles TREADY, so all we need to do is + // detect when the link goes down and disable the TRN interface until the link + // comes back up and the AXI interface is finished flushing any packets. + else begin : thrtl_ctl_trn_flush + always @(posedge user_clk) begin + if(user_rst) begin + reg_disable_trn <= #TCQ 1'b0; + end + else begin + // If the link is down and AXI is in packet, disable TRN and look for + // the end of the packet + if(axi_in_packet && !trn_lnk_up && !axi_end_packet) + begin + reg_disable_trn <= #TCQ 1'b1; + end + + // AXI packet is ending, so we're done flushing + else if(axi_end_packet) begin + reg_disable_trn <= #TCQ 1'b0; + end + end + end + + // Disable the TRN interface if link is down or we're still flushing the AXI + // interface. + assign disable_trn = reg_disable_trn || !trn_lnk_up; + end +endgenerate + + +//----------------------------------------------------------------------------// +// Convert STRB to RREM. Here, we are converting the encoding method for the // +// location of the EOF from AXI (tkeep) to TRN flavor (rrem). // +//----------------------------------------------------------------------------// +generate + if(C_DATA_WIDTH == 128) begin : tkeep_to_trem_128 + //---------------------------------------// + // Conversion table: // + // trem | tkeep // + // [1] [0] | [15:12] [11:8] [7:4] [3:0] // + // ------------------------------------- // + // 1 1 | D3 D2 D1 D0 // + // 1 0 | -- D2 D1 D0 // + // 0 1 | -- -- D1 D0 // + // 0 0 | -- -- -- D0 // + //---------------------------------------// + + wire axi_DW_1 = reg_tkeep[7]; + wire axi_DW_2 = reg_tkeep[11]; + wire axi_DW_3 = reg_tkeep[15]; + assign trn_trem[1] = axi_DW_2; + assign trn_trem[0] = axi_DW_3 || (axi_DW_1 && !axi_DW_2); + end + else if(C_DATA_WIDTH == 64) begin : tkeep_to_trem_64 + assign trn_trem = reg_tkeep[7]; + end + else begin : tkeep_to_trem_32 + assign trn_trem = 1'b0; + end +endgenerate + + +//----------------------------------------------------------------------------// +// Create remaining TRN signals // +//----------------------------------------------------------------------------// +assign trn_teof = reg_tlast; +assign trn_tecrc_gen = reg_tuser[0]; +assign trn_terrfwd = reg_tuser[1]; +assign trn_tstr = reg_tuser[2]; +assign trn_tsrc_dsc = reg_tuser[3]; + + +//----------------------------------------------------------------------------// +// Pipeline stage // +//----------------------------------------------------------------------------// +// We need one of two approaches for the pipeline stage depending on the +// C_PM_PRIORITY parameter. +generate + reg reg_tsrc_rdy; + + // If set to FALSE, that means the user wants to use the TX packet boundary + // throttling feature. Since all Block throttling will now be predicted, we + // can use a simple straight-through pipeline. + if(C_PM_PRIORITY == "FALSE") begin : throttle_ctl_pipeline + always @(posedge user_clk) begin + if(user_rst) begin + reg_tdata <= #TCQ {C_DATA_WIDTH{1'b0}}; + reg_tvalid <= #TCQ 1'b0; + reg_tkeep <= #TCQ {KEEP_WIDTH{1'b0}}; + reg_tlast <= #TCQ 1'b0; + reg_tuser <= #TCQ 4'h0; + reg_tsrc_rdy <= #TCQ 1'b0; + end + else begin + reg_tdata <= #TCQ s_axis_tx_tdata; + reg_tvalid <= #TCQ s_axis_tx_tvalid; + reg_tkeep <= #TCQ s_axis_tx_tkeep; + reg_tlast <= #TCQ s_axis_tx_tlast; + reg_tuser <= #TCQ s_axis_tx_tuser; + + // Hold trn_tsrc_rdy low when flushing a packet. + reg_tsrc_rdy <= #TCQ axi_beat_live && !disable_trn; + end + end + + assign trn_tsrc_rdy = reg_tsrc_rdy; + + // With TX packet boundary throttling, TREADY is pipelined in + // axi_basic_tx_thrtl_ctl and wired through here. + assign s_axis_tx_tready = tready_thrtl; + end + + //**************************************************************************// + + // If C_PM_PRIORITY is set to TRUE, that means the user prefers to have all PM + // functionality intact isntead of TX packet boundary throttling. Now the + // Block could back-pressure at any time, which creates the standard problem + // of potential data loss due to the handshaking latency. Here we need a + // previous value buffer, just like the RX data path. + else begin : pm_prioity_pipeline + reg [C_DATA_WIDTH-1:0] tdata_prev; + reg tvalid_prev; + reg [KEEP_WIDTH-1:0] tkeep_prev; + reg tlast_prev; + reg [3:0] tuser_prev; + reg reg_tdst_rdy; + + wire data_hold; + reg data_prev; + + + //------------------------------------------------------------------------// + // Previous value buffer // + // --------------------- // + // We are inserting a pipeline stage in between AXI and TRN, which causes // + // some issues with handshaking signals trn_tsrc_rdy/s_axis_tx_tready. // + // The added cycle of latency in the path causes the Block to fall behind // + // the AXI interface whenever it throttles. // + // // + // To avoid loss of data, we must keep the previous value of all // + // s_axis_tx_* signals in case the Block throttles. // + //------------------------------------------------------------------------// + always @(posedge user_clk) begin + if(user_rst) begin + tdata_prev <= #TCQ {C_DATA_WIDTH{1'b0}}; + tvalid_prev <= #TCQ 1'b0; + tkeep_prev <= #TCQ {KEEP_WIDTH{1'b0}}; + tlast_prev <= #TCQ 1'b0; + tuser_prev <= #TCQ 4'h 0; + end + else begin + // prev buffer works by checking s_axis_tx_tready. When + // s_axis_tx_tready is asserted, a new value is present on the + // interface. + if(!s_axis_tx_tready) begin + tdata_prev <= #TCQ tdata_prev; + tvalid_prev <= #TCQ tvalid_prev; + tkeep_prev <= #TCQ tkeep_prev; + tlast_prev <= #TCQ tlast_prev; + tuser_prev <= #TCQ tuser_prev; + end + else begin + tdata_prev <= #TCQ s_axis_tx_tdata; + tvalid_prev <= #TCQ s_axis_tx_tvalid; + tkeep_prev <= #TCQ s_axis_tx_tkeep; + tlast_prev <= #TCQ s_axis_tx_tlast; + tuser_prev <= #TCQ s_axis_tx_tuser; + end + end + end + + // Create special buffer which locks in the proper value of TDATA depending + // on whether the user is throttling or not. This buffer has three states: + // + // HOLD state: TDATA maintains its current value + // - the Block has throttled the PCIe block + // PREVIOUS state: the buffer provides the previous value on TDATA + // - the Block has finished throttling, and is a little + // behind the user + // CURRENT state: the buffer passes the current value on TDATA + // - the Block is caught up and ready to receive the + // latest data from the user + always @(posedge user_clk) begin + if(user_rst) begin + reg_tdata <= #TCQ {C_DATA_WIDTH{1'b0}}; + reg_tvalid <= #TCQ 1'b0; + reg_tkeep <= #TCQ {KEEP_WIDTH{1'b0}}; + reg_tlast <= #TCQ 1'b0; + reg_tuser <= #TCQ 4'h0; + + reg_tdst_rdy <= #TCQ 1'b0; + end + else begin + reg_tdst_rdy <= #TCQ trn_tdst_rdy; + + if(!data_hold) begin + // PREVIOUS state + if(data_prev) begin + reg_tdata <= #TCQ tdata_prev; + reg_tvalid <= #TCQ tvalid_prev; + reg_tkeep <= #TCQ tkeep_prev; + reg_tlast <= #TCQ tlast_prev; + reg_tuser <= #TCQ tuser_prev; + end + + // CURRENT state + else begin + reg_tdata <= #TCQ s_axis_tx_tdata; + reg_tvalid <= #TCQ s_axis_tx_tvalid; + reg_tkeep <= #TCQ s_axis_tx_tkeep; + reg_tlast <= #TCQ s_axis_tx_tlast; + reg_tuser <= #TCQ s_axis_tx_tuser; + end + end + // else HOLD state + end + end + + + // Logic to instruct pipeline to hold its value + assign data_hold = trn_tsrc_rdy && !trn_tdst_rdy; + + + // Logic to instruct pipeline to use previous bus values. Always use + // previous value after holding a value. + always @(posedge user_clk) begin + if(user_rst) begin + data_prev <= #TCQ 1'b0; + end + else begin + data_prev <= #TCQ data_hold; + end + end + + + //------------------------------------------------------------------------// + // Create trn_tsrc_rdy. If we're flushing the TRN hold trn_tsrc_rdy low. // + //------------------------------------------------------------------------// + assign trn_tsrc_rdy = reg_tvalid && !disable_trn; + + + //------------------------------------------------------------------------// + // Create TREADY // + //------------------------------------------------------------------------// + always @(posedge user_clk) begin + if(user_rst) begin + reg_tready <= #TCQ 1'b0; + end + else begin + // If the link went down and we need to flush a packet in flight, hold + // TREADY high + if(flush_axi && !axi_end_packet) begin + reg_tready <= #TCQ 1'b1; + end + + // If the link is up, TREADY is as follows: + // TREADY = 1 when trn_tsrc_rdy == 0 + // - While idle, keep the pipeline primed and ready for the next + // packet + // + // TREADY = trn_tdst_rdy when trn_tsrc_rdy == 1 + // - While in packet, throttle pipeline based on state of TRN + else if(trn_lnk_up) begin + reg_tready <= #TCQ trn_tdst_rdy || !trn_tsrc_rdy; + end + + // If the link is down and we're not flushing a packet, hold TREADY low + // wait for link to come back up + else begin + reg_tready <= #TCQ 1'b0; + end + end + end + + assign s_axis_tx_tready = reg_tready; + end + + + //--------------------------------------------------------------------------// + // Create flush_axi. This signal detects if the link goes down while the // + // AXI interface is in packet. In this situation, we need to flush the // + // packet through the AXI interface and discard it. // + //--------------------------------------------------------------------------// + always @(posedge user_clk) begin + if(user_rst) begin + flush_axi <= #TCQ 1'b0; + end + else begin + // If the AXI interface is in packet and the link goes down, purge it. + if(axi_in_packet && !trn_lnk_up && !axi_end_packet) begin + flush_axi <= #TCQ 1'b1; + end + + // The packet is finished, so we're done flushing. + else if(axi_end_packet) begin + flush_axi <= #TCQ 1'b0; + end + end + end +endgenerate + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_tx_thrtl_ctl.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_tx_thrtl_ctl.v new file mode 100644 index 0000000..d1feee2 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_tx_thrtl_ctl.v @@ -0,0 +1,784 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_axi_basic_tx_thrtl_ctl.v +// Version : 3.3 +// // +// Description: // +// TX throttle controller. Anticipates back-pressure from PCIe block and // +// preemptively back-pressures user design (packet boundary throttling). // +// // +// Notes: // +// Optional notes section. // +// // +// Hierarchical: // +// axi_basic_top // +// axi_basic_tx // +// axi_basic_tx_thrtl_ctl // +// // +//----------------------------------------------------------------------------// + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_axi_basic_tx_thrtl_ctl #( + parameter C_DATA_WIDTH = 128, // RX/TX interface data width + parameter C_FAMILY = "X7", // Targeted FPGA family + parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode + parameter TCQ = 1 // Clock to Q time + ) ( + + // AXI TX + //----------- + input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user + input s_axis_tx_tvalid, // TX data is valid + input [3:0] s_axis_tx_tuser, // TX user signals + input s_axis_tx_tlast, // TX data is last + + // User Misc. + //----------- + input user_turnoff_ok, // Turnoff OK from user + input user_tcfg_gnt, // Send cfg OK from user + + // TRN TX + //----------- + input [5:0] trn_tbuf_av, // TX buffers available + input trn_tdst_rdy, // TX destination ready + + // TRN Misc. + //----------- + input trn_tcfg_req, // TX config request + output trn_tcfg_gnt, // TX config grant + input trn_lnk_up, // PCIe link up + + // 7 Series/Virtex6 PM + //----------- + input [2:0] cfg_pcie_link_state, // Encoded PCIe link state + + // Virtex6 PM + //----------- + input cfg_pm_send_pme_to, // PM send PME turnoff msg + input [1:0] cfg_pmcsr_powerstate, // PMCSR power state + input [31:0] trn_rdllp_data, // RX DLLP data + input trn_rdllp_src_rdy, // RX DLLP source ready + + // Virtex6/Spartan6 PM + //----------- + input cfg_to_turnoff, // Turnoff request + output reg cfg_turnoff_ok, // Turnoff grant + + // System + //----------- + output reg tready_thrtl, // TREADY to pipeline + input user_clk, // user clock from block + input user_rst // user reset from block +); + +// Thrtl user when TBUF hits this val +localparam TBUF_AV_MIN = (C_DATA_WIDTH == 128) ? 5 : + (C_DATA_WIDTH == 64) ? 1 : 0; + +// Pause user when TBUF hits this val +localparam TBUF_AV_GAP = TBUF_AV_MIN + 1; + +// GAP pause time - the latency from the time a packet is accepted on the TRN +// interface to the time trn_tbuf_av from the Block will decrement. +localparam TBUF_GAP_TIME = (C_DATA_WIDTH == 128) ? 4 : 1; + +// Latency time from when tcfg_gnt is asserted to when PCIe block will throttle +localparam TCFG_LATENCY_TIME = 2'd2; + +// Number of pipeline stages to delay trn_tcfg_gnt. For V6 128-bit only +localparam TCFG_GNT_PIPE_STAGES = 3; + +// Throttle condition registers and constants +reg lnk_up_thrtl; +wire lnk_up_trig; +wire lnk_up_exit; + +reg tbuf_av_min_thrtl; +wire tbuf_av_min_trig; + +reg tbuf_av_gap_thrtl; +reg [2:0] tbuf_gap_cnt; +wire tbuf_av_gap_trig; +wire tbuf_av_gap_exit; +wire gap_trig_tlast; +wire gap_trig_decr; +wire gap_trig_tcfg; +reg [5:0] tbuf_av_d; + +reg tcfg_req_thrtl; +reg [1:0] tcfg_req_cnt; +reg trn_tdst_rdy_d; +wire tcfg_req_trig; +wire tcfg_req_exit; +reg tcfg_gnt_log; + +wire pre_throttle; +wire reg_throttle; +wire exit_crit; +reg reg_tcfg_gnt; +reg trn_tcfg_req_d; +reg tcfg_gnt_pending; +wire wire_to_turnoff; +reg reg_turnoff_ok; + +reg tready_thrtl_mux; + +localparam LINKSTATE_L0 = 3'b000; +localparam LINKSTATE_PPM_L1 = 3'b001; +localparam LINKSTATE_PPM_L1_TRANS = 3'b101; +localparam LINKSTATE_PPM_L23R_TRANS = 3'b110; +localparam PM_ENTER_L1 = 8'h20; +localparam POWERSTATE_D0 = 2'b00; + +reg ppm_L1_thrtl; +wire ppm_L1_trig; +wire ppm_L1_exit; +reg [2:0] cfg_pcie_link_state_d; +reg trn_rdllp_src_rdy_d; + +reg ppm_L23_thrtl; +wire ppm_L23_trig; +reg cfg_turnoff_ok_pending; + +reg reg_tlast; + +// Throttle control state machine states and registers +localparam IDLE = 0; +localparam THROTTLE = 1; +reg cur_state; +reg next_state; + +reg reg_axi_in_pkt; +wire axi_in_pkt; +wire axi_pkt_ending; +wire axi_throttled; +wire axi_thrtl_ok; +wire tx_ecrc_pause; + +//----------------------------------------------------------------------------// +// THROTTLE REASON: PCIe link is down // +// - When to throttle: trn_lnk_up deasserted // +// - When to stop: trn_tdst_rdy assesrted // +//----------------------------------------------------------------------------// +assign lnk_up_trig = !trn_lnk_up; +assign lnk_up_exit = trn_tdst_rdy; + +always @(posedge user_clk) begin + if(user_rst) begin + lnk_up_thrtl <= #TCQ 1'b1; + end + else begin + if(lnk_up_trig) begin + lnk_up_thrtl <= #TCQ 1'b1; + end + else if(lnk_up_exit) begin + lnk_up_thrtl <= #TCQ 1'b0; + end + end +end + + +//----------------------------------------------------------------------------// +// THROTTLE REASON: Transmit buffers depleted // +// - When to throttle: trn_tbuf_av falls to 0 // +// - When to stop: trn_tbuf_av rises above 0 again // +//----------------------------------------------------------------------------// +assign tbuf_av_min_trig = (trn_tbuf_av <= TBUF_AV_MIN); + +always @(posedge user_clk) begin + if(user_rst) begin + tbuf_av_min_thrtl <= #TCQ 1'b0; + end + else begin + if(tbuf_av_min_trig) begin + tbuf_av_min_thrtl <= #TCQ 1'b1; + end + + // The exit condition for tbuf_av_min_thrtl is !tbuf_av_min_trig + else begin + tbuf_av_min_thrtl <= #TCQ 1'b0; + end + end +end + + +//----------------------------------------------------------------------------// +// THROTTLE REASON: Transmit buffers getting low // +// - When to throttle: trn_tbuf_av falls below "gap" threshold TBUF_AV_GAP // +// - When to stop: after TBUF_GAP_TIME cycles elapse // +// // +// If we're about to run out of transmit buffers, throttle the user for a // +// few clock cycles to give the PCIe block time to catch up. This is // +// needed to compensate for latency in decrementing trn_tbuf_av in the PCIe // +// Block transmit path. // +//----------------------------------------------------------------------------// + +// Detect two different scenarios for buffers getting low: +// 1) If we see a TLAST. a new packet has been inserted into the buffer, and +// we need to pause and let that packet "soak in" +assign gap_trig_tlast = (trn_tbuf_av <= TBUF_AV_GAP) && + s_axis_tx_tvalid && tready_thrtl && s_axis_tx_tlast; + +// 2) Any time tbug_avail decrements to the TBUF_AV_GAP threshold, we need to +// pause and make sure no other packets are about to soak in and cause the +// buffer availability to drop further. +assign gap_trig_decr = (trn_tbuf_av == (TBUF_AV_GAP)) && + (tbuf_av_d == (TBUF_AV_GAP+1)); + +assign gap_trig_tcfg = (tcfg_req_thrtl && tcfg_req_exit); +assign tbuf_av_gap_trig = gap_trig_tlast || gap_trig_decr || gap_trig_tcfg; +assign tbuf_av_gap_exit = (tbuf_gap_cnt == 0); + +always @(posedge user_clk) begin + if(user_rst) begin + tbuf_av_gap_thrtl <= #TCQ 1'b0; + tbuf_gap_cnt <= #TCQ 3'h0; + tbuf_av_d <= #TCQ 6'h00; + end + else begin + if(tbuf_av_gap_trig) begin + tbuf_av_gap_thrtl <= #TCQ 1'b1; + end + else if(tbuf_av_gap_exit) begin + tbuf_av_gap_thrtl <= #TCQ 1'b0; + end + + // tbuf gap counter: + // This logic controls the length of the throttle condition when tbufs are + // getting low. + if(tbuf_av_gap_thrtl && (cur_state == THROTTLE)) begin + if(tbuf_gap_cnt > 0) begin + tbuf_gap_cnt <= #TCQ tbuf_gap_cnt - 3'd1; + end + end + else begin + tbuf_gap_cnt <= #TCQ TBUF_GAP_TIME; + end + + tbuf_av_d <= #TCQ trn_tbuf_av; + end +end + + +//----------------------------------------------------------------------------// +// THROTTLE REASON: Block needs to send a CFG response // +// - When to throttle: trn_tcfg_req and user_tcfg_gnt asserted // +// - When to stop: after trn_tdst_rdy transitions to unasserted // +// // +// If the block needs to send a response to a CFG packet, this will cause // +// the subsequent deassertion of trn_tdst_rdy. When the user design permits, // +// grant permission to the block to service request and throttle the user. // +//----------------------------------------------------------------------------// +assign tcfg_req_trig = trn_tcfg_req && reg_tcfg_gnt; +assign tcfg_req_exit = (tcfg_req_cnt == 2'd0) && !trn_tdst_rdy_d && + trn_tdst_rdy; +always @(posedge user_clk) begin + if(user_rst) begin + tcfg_req_thrtl <= #TCQ 1'b0; + trn_tcfg_req_d <= #TCQ 1'b0; + trn_tdst_rdy_d <= #TCQ 1'b1; + reg_tcfg_gnt <= #TCQ 1'b0; + tcfg_req_cnt <= #TCQ 2'd0; + tcfg_gnt_pending <= #TCQ 1'b0; + end + else begin + if(tcfg_req_trig) begin + tcfg_req_thrtl <= #TCQ 1'b1; + end + else if(tcfg_req_exit) begin + tcfg_req_thrtl <= #TCQ 1'b0; + end + + // We need to wait the appropriate amount of time for the tcfg_gnt to + // "sink in" to the PCIe block. After that, we know that the PCIe block will + // not reassert trn_tdst_rdy until the CFG request has been serviced. If a + // new request is being service (tcfg_gnt_log == 1), then reset the timer. + if((trn_tcfg_req && !trn_tcfg_req_d) || tcfg_gnt_pending) begin + tcfg_req_cnt <= #TCQ TCFG_LATENCY_TIME; + end + else begin + if(tcfg_req_cnt > 0) begin + tcfg_req_cnt <= #TCQ tcfg_req_cnt - 2'd1; + end + end + + // Make sure tcfg_gnt_log pulses once for one clock cycle for every + // cfg packet request. + if(trn_tcfg_req && !trn_tcfg_req_d) begin + tcfg_gnt_pending <= #TCQ 1'b1; + end + else if(tcfg_gnt_log) begin + tcfg_gnt_pending <= #TCQ 1'b0; + end + + trn_tcfg_req_d <= #TCQ trn_tcfg_req; + trn_tdst_rdy_d <= #TCQ trn_tdst_rdy; + reg_tcfg_gnt <= #TCQ user_tcfg_gnt; + end +end + + +//----------------------------------------------------------------------------// +// THROTTLE REASON: Block needs to transition to low power state PPM L1 // +// - When to throttle: appropriate low power state signal asserted // +// (architecture dependent) // +// - When to stop: cfg_pcie_link_state goes to proper value (C_ROOT_PORT // +// dependent) // +// // +// If the block needs to transition to PM state PPM L1, we need to finish // +// up what we're doing and throttle immediately. // +//----------------------------------------------------------------------------// +generate + // PPM L1 signals for 7 Series in RC mode + if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L1_thrtl_rp + assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) && + (cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS); + assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1; + end + + // PPM L1 signals for 7 Series in EP mode + else if((C_FAMILY == "X7") && (C_ROOT_PORT == "FALSE")) begin : x7_L1_thrtl_ep + assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) && + (cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS); + assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0; + end + + // PPM L1 signals for V6 in RC mode + else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L1_thrtl_rp + assign ppm_L1_trig = (trn_rdllp_data[31:24] == PM_ENTER_L1) && + trn_rdllp_src_rdy && !trn_rdllp_src_rdy_d; + assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1; + end + + // PPM L1 signals for V6 in EP mode + else if((C_FAMILY == "V6") && (C_ROOT_PORT == "FALSE")) begin : v6_L1_thrtl_ep + assign ppm_L1_trig = (cfg_pmcsr_powerstate != POWERSTATE_D0); + assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0; + end + + // PPM L1 detection not supported for S6 + else begin : s6_L1_thrtl + assign ppm_L1_trig = 1'b0; + assign ppm_L1_exit = 1'b1; + end +endgenerate + +always @(posedge user_clk) begin + if(user_rst) begin + ppm_L1_thrtl <= #TCQ 1'b0; + cfg_pcie_link_state_d <= #TCQ 3'b0; + trn_rdllp_src_rdy_d <= #TCQ 1'b0; + end + else begin + if(ppm_L1_trig) begin + ppm_L1_thrtl <= #TCQ 1'b1; + end + else if(ppm_L1_exit) begin + ppm_L1_thrtl <= #TCQ 1'b0; + end + cfg_pcie_link_state_d <= #TCQ cfg_pcie_link_state; + trn_rdllp_src_rdy_d <= #TCQ trn_rdllp_src_rdy; + end +end + + +//----------------------------------------------------------------------------// +// THROTTLE REASON: Block needs to transition to low power state PPM L2/3 // +// - When to throttle: appropriate PM signal indicates a transition to // +// L2/3 is pending or in progress (family and role dependent) // +// - When to stop: never (the only path out of L2/3 is a full reset) // +// // +// If the block needs to transition to PM state PPM L2/3, we need to finish // +// up what we're doing and throttle when the user gives permission. // +//----------------------------------------------------------------------------// +generate + // PPM L2/3 signals for 7 Series in RC mode + if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L23_thrtl_rp + assign ppm_L23_trig = (cfg_pcie_link_state_d == LINKSTATE_PPM_L23R_TRANS); + assign wire_to_turnoff = 1'b0; + end + + // PPM L2/3 signals for V6 in RC mode + else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L23_thrtl_rp + assign ppm_L23_trig = cfg_pm_send_pme_to; + assign wire_to_turnoff = 1'b0; + end + + // PPM L2/3 signals in EP mode + else begin : L23_thrtl_ep + assign ppm_L23_trig = wire_to_turnoff && reg_turnoff_ok; + + // PPM L2/3 signals for 7 Series in EP mode + // For 7 Series, cfg_to_turnoff pulses once when a turnoff request is + // outstanding, so we need a "sticky" register that grabs the request. + if(C_FAMILY == "X7") begin : x7_L23_thrtl_ep + reg reg_to_turnoff; + + always @(posedge user_clk) begin + if(user_rst) begin + reg_to_turnoff <= #TCQ 1'b0; + end + else begin + if(cfg_to_turnoff) begin + reg_to_turnoff <= #TCQ 1'b1; + end + end + end + + assign wire_to_turnoff = reg_to_turnoff; + end + + // PPM L2/3 signals for V6/S6 in EP mode + // In V6 and S6, the to_turnoff signal asserts and remains asserted until + // turnoff_ok is asserted, so a sticky reg is not necessary. + else begin : v6_s6_L23_thrtl_ep + assign wire_to_turnoff = cfg_to_turnoff; + end + + always @(posedge user_clk) begin + if(user_rst) begin + reg_turnoff_ok <= #TCQ 1'b0; + end + else begin + reg_turnoff_ok <= #TCQ user_turnoff_ok; + end + end + end +endgenerate + +always @(posedge user_clk) begin + if(user_rst) begin + ppm_L23_thrtl <= #TCQ 1'b0; + cfg_turnoff_ok_pending <= #TCQ 1'b0; + end + else begin + if(ppm_L23_trig) begin + ppm_L23_thrtl <= #TCQ 1'b1; + end + + // Make sure cfg_turnoff_ok pulses once for one clock cycle for every + // turnoff request. + if(ppm_L23_trig && !ppm_L23_thrtl) begin + cfg_turnoff_ok_pending <= #TCQ 1'b1; + end + else if(cfg_turnoff_ok) begin + cfg_turnoff_ok_pending <= #TCQ 1'b0; + end + end +end + + +//----------------------------------------------------------------------------// +// Create axi_thrtl_ok. This signal determines if it's OK to throttle the // +// user design on the AXI interface. Since TREADY is registered, this signal // +// needs to assert on the cycle ~before~ we actually intend to throttle. // +// The only time it's OK to throttle when TVALID is asserted is on the first // +// beat of a new packet. Therefore, assert axi_thrtl_ok if one of the // +// is true: // +// 1) The user is not in a packet and is not starting one // +// 2) The user is just finishing a packet // +// 3) We're already throttled, so it's OK to continue throttling // +//----------------------------------------------------------------------------// +always @(posedge user_clk) begin + if(user_rst) begin + reg_axi_in_pkt <= #TCQ 1'b0; + end + else begin + if(s_axis_tx_tvalid && s_axis_tx_tlast) begin + reg_axi_in_pkt <= #TCQ 1'b0; + end + else if(tready_thrtl && s_axis_tx_tvalid) begin + reg_axi_in_pkt <= #TCQ 1'b1; + end + end +end + +assign axi_in_pkt = s_axis_tx_tvalid || reg_axi_in_pkt; +assign axi_pkt_ending = s_axis_tx_tvalid && s_axis_tx_tlast; +assign axi_throttled = !tready_thrtl; +assign axi_thrtl_ok = !axi_in_pkt || axi_pkt_ending || axi_throttled; + + +//----------------------------------------------------------------------------// +// Throttle CTL State Machine: // +// Throttle user design when a throttle trigger (or triggers) occur. // +// Keep user throttled until all exit criteria have been met. // +//----------------------------------------------------------------------------// + +// Immediate throttle signal. Used to "pounce" on a throttle opportunity when +// we're seeking one +assign pre_throttle = tbuf_av_min_trig || tbuf_av_gap_trig || lnk_up_trig + || tcfg_req_trig || ppm_L1_trig || ppm_L23_trig; + + +// Registered throttle signals. Used to control throttle state machine +assign reg_throttle = tbuf_av_min_thrtl || tbuf_av_gap_thrtl || lnk_up_thrtl + || tcfg_req_thrtl || ppm_L1_thrtl || ppm_L23_thrtl; + +assign exit_crit = !tbuf_av_min_thrtl && !tbuf_av_gap_thrtl && !lnk_up_thrtl + && !tcfg_req_thrtl && !ppm_L1_thrtl && !ppm_L23_thrtl; + +always @(*) begin + case(cur_state) + // IDLE: in this state we're waiting for a trigger event to occur. As + // soon as an event occurs and the user isn't transmitting a packet, we + // throttle the PCIe block and the user and next state is THROTTLE. + IDLE: begin + if(reg_throttle && axi_thrtl_ok) begin + // Throttle user + tready_thrtl_mux = 1'b0; + next_state = THROTTLE; + + // Assert appropriate grant signal depending on the throttle type. + if(tcfg_req_thrtl) begin + tcfg_gnt_log = 1'b1; // For cfg request, grant the request + cfg_turnoff_ok = 1'b0; // + end + else if(ppm_L23_thrtl) begin + tcfg_gnt_log = 1'b0; // + cfg_turnoff_ok = 1'b1; // For PM request, permit transition + end + else begin + tcfg_gnt_log = 1'b0; // Otherwise do nothing + cfg_turnoff_ok = 1'b0; // + end + end + + // If there's not throttle event, do nothing + else begin + // Throttle user as soon as possible + tready_thrtl_mux = !(axi_thrtl_ok && pre_throttle); + next_state = IDLE; + + tcfg_gnt_log = 1'b0; + cfg_turnoff_ok = 1'b0; + end + end + + // THROTTLE: in this state the user is throttle and we're waiting for + // exit criteria, which tells us that the throttle event is over. When + // the exit criteria is satisfied, de-throttle the user and next state + // is IDLE. + THROTTLE: begin + if(exit_crit) begin + // Dethrottle user + tready_thrtl_mux = !pre_throttle; + next_state = IDLE; + end + else begin + // Throttle user + tready_thrtl_mux = 1'b0; + next_state = THROTTLE; + end + + // Assert appropriate grant signal depending on the throttle type. + if(tcfg_req_thrtl && tcfg_gnt_pending) begin + tcfg_gnt_log = 1'b1; // For cfg request, grant the request + cfg_turnoff_ok = 1'b0; // + end + else if(cfg_turnoff_ok_pending) begin + tcfg_gnt_log = 1'b0; // + cfg_turnoff_ok = 1'b1; // For PM request, permit transition + end + else begin + tcfg_gnt_log = 1'b0; // Otherwise do nothing + cfg_turnoff_ok = 1'b0; // + end + end + + default: begin + tready_thrtl_mux = 1'b0; + next_state = IDLE; + tcfg_gnt_log = 1'b0; + cfg_turnoff_ok = 1'b0; + end + endcase +end + +// Synchronous logic +always @(posedge user_clk) begin + if(user_rst) begin + // Throttle user by default until link comes up + cur_state <= #TCQ THROTTLE; + + reg_tlast <= #TCQ 1'b0; + + tready_thrtl <= #TCQ 1'b0; + end + else begin + cur_state <= #TCQ next_state; + + tready_thrtl <= #TCQ tready_thrtl_mux && !tx_ecrc_pause; + reg_tlast <= #TCQ s_axis_tx_tlast; + end +end + +// For X7, the PCIe block will generate the ECRC for a packet if trn_tecrc_gen +// is asserted at SOF. In this case, the Block needs an extra data beat to +// calculate the ECRC, but only if the following conditions are met: +// 1) there is no empty DWORDS at the end of the packet +// (i.e. packet length % C_DATA_WIDTH == 0) +// +// 2) There isn't a ECRC in the TLP already, as indicated by the TD bit in the +// TLP header +// +// If both conditions are met, the Block will stall the TRN interface for one +// data beat after EOF. We need to predict this stall and preemptively stall the +// User for one beat. +generate + if(C_FAMILY == "X7") begin : ecrc_pause_enabled + wire tx_ecrc_pkt; + reg reg_tx_ecrc_pkt; + + wire [1:0] packet_fmt; + wire packet_td; + wire [2:0] header_len; + wire [9:0] payload_len; + wire [13:0] packet_len; + wire pause_needed; + + // Grab necessary packet fields + assign packet_fmt = s_axis_tx_tdata[30:29]; + assign packet_td = s_axis_tx_tdata[15]; + + // Calculate total packet length + assign header_len = packet_fmt[0] ? 3'd4 : 3'd3; + assign payload_len = packet_fmt[1] ? s_axis_tx_tdata[9:0] : 10'h0; + assign packet_len = {10'h000, header_len} + {4'h0, payload_len}; + + + // Determine if packet a ECRC pause is needed + if(C_DATA_WIDTH == 128) begin : packet_len_check_128 + assign pause_needed = (packet_len[1:0] == 2'b00) && !packet_td; + end + else begin : packet_len_check_64 + assign pause_needed = (packet_len[0] == 1'b0) && !packet_td; + end + + + // Create flag to alert TX pipeline to insert a stall + assign tx_ecrc_pkt = s_axis_tx_tuser[0] && pause_needed && + tready_thrtl && s_axis_tx_tvalid && !reg_axi_in_pkt; + + always @(posedge user_clk) begin + if(user_rst) begin + reg_tx_ecrc_pkt <= #TCQ 1'b0; + end + else begin + if(tx_ecrc_pkt && !s_axis_tx_tlast) begin + reg_tx_ecrc_pkt <= #TCQ 1'b1; + end + else if(tready_thrtl && s_axis_tx_tvalid && s_axis_tx_tlast) begin + reg_tx_ecrc_pkt <= #TCQ 1'b0; + end + end + end + + + // Insert the stall now + assign tx_ecrc_pause = ((tx_ecrc_pkt || reg_tx_ecrc_pkt) && + s_axis_tx_tlast && s_axis_tx_tvalid && tready_thrtl); + + end + else begin : ecrc_pause_disabled + assign tx_ecrc_pause = 1'b0; + end +endgenerate + + +// Logic for 128-bit single cycle bug fix. +// This tcfg_gnt pipeline addresses an issue with 128-bit V6 designs where a +// single cycle packet transmitted simultaneously with an assertion of tcfg_gnt +// from AXI Basic causes the packet to be dropped. The packet drop occurs +// because the 128-bit shim doesn't know about the tcfg_req/gnt, and therefor +// isn't expecting trn_tdst_rdy to go low. Since the 128-bit shim does throttle +// prediction just as we do, it ignores the value of trn_tdst_rdy, and +// ultimately drops the packet when transmitting the packet to the block. +generate + if(C_DATA_WIDTH == 128 && C_FAMILY == "V6") begin : tcfg_gnt_pipeline + genvar stage; + reg tcfg_gnt_pipe [TCFG_GNT_PIPE_STAGES:0]; + + // Create a configurable depth FF delay pipeline + for(stage = 0; stage < TCFG_GNT_PIPE_STAGES; stage = stage + 1) + begin : tcfg_gnt_pipeline_stage + + always @(posedge user_clk) begin + if(user_rst) begin + tcfg_gnt_pipe[stage] <= #TCQ 1'b0; + end + else begin + // For stage 0, insert the actual tcfg_gnt signal from logic + if(stage == 0) begin + tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_log; + end + + // For stages 1+, chain together + else begin + tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_pipe[stage - 1]; + end + end + end + + // tcfg_gnt output to block assigned the last pipeline stage + assign trn_tcfg_gnt = tcfg_gnt_pipe[TCFG_GNT_PIPE_STAGES-1]; + end + end + else begin : tcfg_gnt_no_pipeline + + // For all other architectures, no pipeline delay needed for tcfg_gnt + assign trn_tcfg_gnt = tcfg_gnt_log; + end +endgenerate + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_core_top.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_core_top.v new file mode 100644 index 0000000..8d714e6 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_core_top.v @@ -0,0 +1,2152 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_core_top.v +// Version : 3.3 +// +// Description: 7-series solution wrapper : Endpoint for PCI Express +// +// +// +//-------------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "pcie_7x_0,pcie_7x_v3_3_14,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=4,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=3,USER_CLK_FREQ=3,REF_CLK_FREQ=0,MSI_CAP_ON=FALSE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,\ +VC0_TX_LASTPACKET=30,VC0_RX_RAM_LIMIT=FFF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=949,VC0_TOTAL_CREDITS_NPH=12,VC0_TOTAL_CREDITS_NPD=24,VC0_TOTAL_CREDITS_CH=36,VC0_TOTAL_CREDITS_CD=973,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,REVISION_ID=00,VC_CAP_ON=FALSE}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_core_top # ( + parameter CFG_VEND_ID = 16'h10EE, + parameter CFG_DEV_ID = 16'h7024, + parameter CFG_REV_ID = 8'h00, + parameter CFG_SUBSYS_VEND_ID = 16'h10EE, + parameter CFG_SUBSYS_ID = 16'h0007, + + parameter EXT_PIPE_SIM = "FALSE", + + parameter ALLOW_X8_GEN2 = "FALSE", + parameter PIPE_PIPELINE_STAGES = 1, + parameter [11:0] AER_BASE_PTR = 12'h000, + parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE", + parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE", + parameter AER_CAP_MULTIHEADER = "FALSE", + parameter [11:0] AER_CAP_NEXTPTR = 12'h000, + parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000, + parameter AER_CAP_ON = "FALSE", + parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "FALSE", + + parameter [31:0] BAR0 = 32'hFFFF0000, + parameter [31:0] BAR1 = 32'h00000000, + parameter [31:0] BAR2 = 32'h00000000, + parameter [31:0] BAR3 = 32'h00000000, + parameter [31:0] BAR4 = 32'h00000000, + parameter [31:0] BAR5 = 32'h00000000, + + parameter C_DATA_WIDTH = 64, + parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000, + parameter [23:0] CLASS_CODE = 24'h050000, + parameter CMD_INTX_IMPLEMENTED = "TRUE", + parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE", + parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2, + + parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0, + parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 7, + parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE", + parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 3, + parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0, + + parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE", + parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE", + parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE", + parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE", + parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE", + parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'b00, + parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE", + + parameter DISABLE_LANE_REVERSAL = "TRUE", + parameter DISABLE_RX_POISONED_RESP = "FALSE", + parameter DISABLE_SCRAMBLING = "FALSE", + parameter [11:0] DSN_BASE_PTR = 12'h100, + parameter [11:0] DSN_CAP_NEXTPTR = 12'h000, + parameter DSN_CAP_ON = "TRUE", + + parameter [10:0] ENABLE_MSG_ROUTE = 11'b00000000000, + parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE", + parameter [31:0] EXPANSION_ROM = 32'h00000000, + parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F, + parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF, + parameter [7:0] HEADER_TYPE = 8'h00, + parameter [7:0] INTERRUPT_PIN = 8'h1, + + parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF, + parameter LINK_CAP_ASPM_OPTIONALITY = "FALSE", + parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE", + parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE", + parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h2, + parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h4, + + parameter LINK_CTRL2_DEEMPHASIS = "FALSE", + parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE", + parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2, + parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE", + + parameter [14:0] LL_ACK_TIMEOUT = 15'h0000, + parameter LL_ACK_TIMEOUT_EN = "FALSE", + parameter integer LL_ACK_TIMEOUT_FUNC = 0, + parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000, + parameter LL_REPLAY_TIMEOUT_EN = "FALSE", + parameter integer LL_REPLAY_TIMEOUT_FUNC = 1, + + parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h4, + parameter MSI_CAP_MULTIMSGCAP = 0, + parameter MSI_CAP_MULTIMSG_EXTENSION = 0, + parameter MSI_CAP_ON = "FALSE", + parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE", + parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE", + + parameter MSIX_CAP_ON = "FALSE", + parameter MSIX_CAP_PBA_BIR = 0, + parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h0, + parameter MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h0, + parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000, + + parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0, + parameter [7:0] PCIE_CAP_NEXTPTR = 8'h00, + + parameter PM_CAP_DSI = "FALSE", + parameter PM_CAP_D1SUPPORT = "FALSE", + parameter PM_CAP_D2SUPPORT = "FALSE", + parameter [7:0] PM_CAP_NEXTPTR = 8'h60, + parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F, + parameter PM_CSR_NOSOFTRST = "TRUE", + + parameter [1:0] PM_DATA_SCALE0 = 2'h0, + parameter [1:0] PM_DATA_SCALE1 = 2'h0, + parameter [1:0] PM_DATA_SCALE2 = 2'h0, + parameter [1:0] PM_DATA_SCALE3 = 2'h0, + parameter [1:0] PM_DATA_SCALE4 = 2'h0, + parameter [1:0] PM_DATA_SCALE5 = 2'h0, + parameter [1:0] PM_DATA_SCALE6 = 2'h0, + parameter [1:0] PM_DATA_SCALE7 = 2'h0, + + parameter [7:0] PM_DATA0 = 8'h00, + parameter [7:0] PM_DATA1 = 8'h00, + parameter [7:0] PM_DATA2 = 8'h00, + parameter [7:0] PM_DATA3 = 8'h00, + parameter [7:0] PM_DATA4 = 8'h00, + parameter [7:0] PM_DATA5 = 8'h00, + parameter [7:0] PM_DATA6 = 8'h00, + parameter [7:0] PM_DATA7 = 8'h00, + + parameter [11:0] RBAR_BASE_PTR = 12'h000, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00, + parameter [2:0] RBAR_CAP_INDEX0 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX1 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX2 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX3 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX4 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX5 = 3'h0, + parameter RBAR_CAP_ON = "FALSE", + parameter [31:0] RBAR_CAP_SUP0 = 32'h00001, + parameter [31:0] RBAR_CAP_SUP1 = 32'h00001, + parameter [31:0] RBAR_CAP_SUP2 = 32'h00001, + parameter [31:0] RBAR_CAP_SUP3 = 32'h00001, + parameter [31:0] RBAR_CAP_SUP4 = 32'h00001, + parameter [31:0] RBAR_CAP_SUP5 = 32'h00001, + parameter [2:0] RBAR_NUM = 3'h0, + + parameter RECRC_CHK = 0, + parameter RECRC_CHK_TRIM = "FALSE", + parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz + parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, + parameter KEEP_WIDTH = C_DATA_WIDTH / 8, + + parameter TL_RX_RAM_RADDR_LATENCY = 0, + parameter TL_RX_RAM_WRITE_LATENCY = 0, + parameter TL_TX_RAM_RADDR_LATENCY = 0, + parameter TL_TX_RAM_WRITE_LATENCY = 0, + parameter TL_RX_RAM_RDATA_LATENCY = 2, + parameter TL_TX_RAM_RDATA_LATENCY = 2, + parameter TRN_NP_FC = "TRUE", + parameter TRN_DW = "FALSE", + + parameter UPCONFIG_CAPABLE = "TRUE", + parameter UPSTREAM_FACING = "TRUE", + parameter UR_ATOMIC = "FALSE", + parameter UR_INV_REQ = "TRUE", + parameter UR_PRS_RESPONSE = "TRUE", + parameter USER_CLK_FREQ = 3, + parameter USER_CLK2_DIV2 = "FALSE", + + parameter [11:0] VC_BASE_PTR = 12'h000, + parameter [11:0] VC_CAP_NEXTPTR = 12'h000, + parameter VC_CAP_ON = "FALSE", + parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE", + + parameter VC0_CPL_INFINITE = "TRUE", + parameter [12:0] VC0_RX_RAM_LIMIT = 13'hFFF, + parameter VC0_TOTAL_CREDITS_CD = 973, + parameter VC0_TOTAL_CREDITS_CH = 36, + parameter VC0_TOTAL_CREDITS_NPH = 12, + parameter VC0_TOTAL_CREDITS_NPD = 24, + parameter VC0_TOTAL_CREDITS_PD = 949, + parameter VC0_TOTAL_CREDITS_PH = 32, + parameter VC0_TX_LASTPACKET = 30, + + parameter [11:0] VSEC_BASE_PTR = 12'h000, + parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000, + parameter VSEC_CAP_ON = "FALSE", + + parameter DISABLE_ASPM_L1_TIMER = "FALSE", + parameter DISABLE_BAR_FILTERING = "FALSE", + parameter DISABLE_ID_CHECK = "FALSE", + parameter DISABLE_RX_TC_FILTER = "FALSE", + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00, + + parameter [15:0] DSN_CAP_ID = 16'h0003, + parameter [3:0] DSN_CAP_VERSION = 4'h1, + parameter ENTER_RVRY_EI_L0 = "TRUE", + parameter [4:0] INFER_EI = 5'h00, + parameter IS_SWITCH = "FALSE", + + parameter LINK_CAP_ASPM_SUPPORT = 1, + parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE", + parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7, + parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7, + parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7, + parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7, + parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7, + parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7, + parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7, + parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7, + parameter LINK_CAP_RSVD_23 = 0, + parameter LINK_CONTROL_RCB = 0, + + parameter [7:0] MSI_BASE_PTR = 8'h48, + parameter [7:0] MSI_CAP_ID = 8'h05, + parameter [7:0] MSI_CAP_NEXTPTR = 8'h60, + parameter [7:0] MSIX_BASE_PTR = 8'h9C, + parameter [7:0] MSIX_CAP_ID = 8'h11, + parameter [7:0] MSIX_CAP_NEXTPTR =8'h00, + + parameter N_FTS_COMCLK_GEN1 = 255, + parameter N_FTS_COMCLK_GEN2 = 255, + parameter N_FTS_GEN1 = 255, + parameter N_FTS_GEN2 = 255, + + parameter [7:0] PCIE_BASE_PTR = 8'h60, + parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10, + parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2, + parameter PCIE_CAP_ON = "TRUE", + parameter PCIE_CAP_RSVD_15_14 = 0, + parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE", + parameter PCIE_REVISION = 2, + + parameter PL_AUTO_CONFIG = 0, + parameter PL_FAST_TRAIN = "FALSE", + parameter PCIE_EXT_CLK = "TRUE", + + parameter PCIE_EXT_GT_COMMON = "FALSE", + parameter EXT_CH_GT_DRP = "FALSE", + parameter TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE", + parameter SHARED_LOGIC_IN_CORE = "FALSE", + + parameter [7:0] PM_BASE_PTR = 8'h40, + parameter PM_CAP_AUXCURRENT = 0, + parameter [7:0] PM_CAP_ID = 8'h01, + parameter PM_CAP_ON = "TRUE", + parameter PM_CAP_PME_CLOCK = "FALSE", + parameter PM_CAP_RSVD_04 = 0, + parameter PM_CAP_VERSION = 3, + parameter PM_CSR_BPCCEN = "FALSE", + parameter PM_CSR_B2B3 = "FALSE", + + parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE", + parameter SELECT_DLL_IF = "FALSE", + parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE", + parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE", + parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE", + parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE", + parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE", + parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE", + parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE", + parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000, + parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE", + parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE", + parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0, + parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00, + + parameter integer SPARE_BIT0 = 0, + + parameter integer SPARE_BIT1 = 0, + parameter integer SPARE_BIT2 = 0, + parameter integer SPARE_BIT3 = 0, + parameter integer SPARE_BIT4 = 0, + parameter integer SPARE_BIT5 = 0, + parameter integer SPARE_BIT6 = 0, + parameter integer SPARE_BIT7 = 0, + parameter integer SPARE_BIT8 = 0, + parameter [7:0] SPARE_BYTE0 = 8'h00, + parameter [7:0] SPARE_BYTE1 = 8'h00, + parameter [7:0] SPARE_BYTE2 = 8'h00, + parameter [7:0] SPARE_BYTE3 = 8'h00, + parameter [31:0] SPARE_WORD0 = 32'h00000000, + parameter [31:0] SPARE_WORD1 = 32'h00000000, + parameter [31:0] SPARE_WORD2 = 32'h00000000, + parameter [31:0] SPARE_WORD3 = 32'h00000000, + + parameter TL_RBYPASS = "FALSE", + parameter TL_TFC_DISABLE = "FALSE", + parameter TL_TX_CHECKS_DISABLE = "FALSE", + parameter EXIT_LOOPBACK_ON_EI = "TRUE", + + parameter CFG_ECRC_ERR_CPLSTAT = 0, + parameter [7:0] CAPABILITIES_PTR = 8'h40, + parameter [6:0] CRM_MODULE_RSTS = 7'h00, + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE", + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE", + parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE", + parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE", + parameter DEV_CAP_RSVD_14_12 = 0, + parameter DEV_CAP_RSVD_17_16 = 0, + parameter DEV_CAP_RSVD_31_29 = 0, + parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE", + + parameter [15:0] VC_CAP_ID = 16'h0002, + parameter [3:0] VC_CAP_VERSION = 4'h1, + parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234, + parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018, + parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1, + parameter [15:0] VSEC_CAP_ID = 16'h000B, + parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE", + parameter [3:0] VSEC_CAP_VERSION = 4'h1, + + parameter DISABLE_ERR_MSG = "FALSE", + parameter DISABLE_LOCKED_FILTER = "FALSE", + parameter DISABLE_PPM_FILTER = "FALSE", + parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE", + parameter INTERRUPT_STAT_AUTO = "TRUE", + parameter MPS_FORCE = "FALSE", + parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000, + parameter PM_ASPML0S_TIMEOUT_EN = "FALSE", + parameter PM_ASPML0S_TIMEOUT_FUNC = 0, + parameter PM_ASPM_FASTEXIT = "FALSE", + parameter PM_MF = "FALSE", + + parameter [1:0] RP_AUTO_SPD = 2'h1, + parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f, + parameter SIM_VERSION = "1.0", + parameter SSL_MESSAGE_AUTO = "FALSE", + parameter TECRC_EP_INV = "FALSE", + parameter UR_CFG1 = "TRUE", + parameter USE_RID_PINS = "FALSE", + +// New Parameters + parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE", + parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE", + parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE", + parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0, + parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE", + + parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE", + + parameter [15:0] AER_CAP_ID = 16'h0001, + parameter [3:0] AER_CAP_VERSION = 4'h1, + + parameter [15:0] RBAR_CAP_ID = 16'h0015, + parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000, + parameter [3:0] RBAR_CAP_VERSION = 4'h1, + parameter PCIE_USE_MODE = "3.0", + parameter PCIE_GT_DEVICE = "GTX", + parameter PCIE_CHAN_BOND = 0, + parameter PCIE_PLL_SEL = "CPLL", + parameter PCIE_ASYNC_EN = "FALSE", + parameter PCIE_TXBUF_EN = "FALSE", + parameter PL_INTERFACE = "TRUE", + parameter CFG_MGMT_IF = "TRUE", + parameter CFG_CTL_IF = "TRUE", + parameter CFG_STATUS_IF = "TRUE", + parameter RCV_MSG_IF = "TRUE", + parameter CFG_FC_IF = "TRUE", + parameter EXT_PIPE_INTERFACE = "FALSE", + + parameter TX_MARGIN_FULL_0 = 7'b1001111, + parameter TX_MARGIN_FULL_1 = 7'b1001110, + parameter TX_MARGIN_FULL_2 = 7'b1001101, + parameter TX_MARGIN_FULL_3 = 7'b1001100, + parameter TX_MARGIN_FULL_4 = 7'b1000011, + parameter TX_MARGIN_LOW_0 = 7'b1000101, + parameter TX_MARGIN_LOW_1 = 7'b1000110, + parameter TX_MARGIN_LOW_2 = 7'b1000011, + parameter TX_MARGIN_LOW_3 = 7'b1000010, + parameter TX_MARGIN_LOW_4 = 7'b1000000, + parameter ENABLE_JTAG_DBG = "FALSE", + parameter REDUCE_OOB_FREQ = "FALSE" +) +( + + //----------------------------------------------------------------------------------------------------------------// + // 1. PCI Express (pci_exp) Interface // + //----------------------------------------------------------------------------------------------------------------// + + // Tx + output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn, + output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp, + + // Rx + input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn, + input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp, + + //----------------------------------------------------------------------------------------------------------------// + // 2. Clock & GT COMMON Sharing Interface // + //----------------------------------------------------------------------------------------------------------------// + + // Shared Logic Internal + output int_pclk_out_slave, + output int_pipe_rxusrclk_out, + output [(LINK_CAP_MAX_LINK_WIDTH-1):0] int_rxoutclk_out, + output int_dclk_out, + output int_userclk1_out, + output int_userclk2_out, + output int_oobclk_out, + output int_mmcm_lock_out, + output [1:0] int_qplllock_out, + output [1:0] int_qplloutclk_out, + output [1:0] int_qplloutrefclk_out, + input [(LINK_CAP_MAX_LINK_WIDTH-1):0] int_pclk_sel_slave, + + // Shared Logic External - Clocks + input pipe_pclk_in, + input pipe_rxusrclk_in, + input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_in, + input pipe_dclk_in, + input pipe_userclk1_in, + input pipe_userclk2_in, + input pipe_oobclk_in, + input pipe_mmcm_lock_in, + + output pipe_txoutclk_out, + output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_out, + output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_pclk_sel_out, + output pipe_gen3_out, + + // Shared Logic External - GT COMMON + + input [11:0] qpll_drp_crscode, + input [17:0] qpll_drp_fsm, + input [1:0] qpll_drp_done, + input [1:0] qpll_drp_reset, + input [1:0] qpll_qplllock, + input [1:0] qpll_qplloutclk, + input [1:0] qpll_qplloutrefclk, + output qpll_qplld, + output [1:0] qpll_qpllreset, + output qpll_drp_clk, + output qpll_drp_rst_n, + output qpll_drp_ovrd, + output qpll_drp_gen3, + output qpll_drp_start, + + //----------------------------------------------------------------------------------------------------------------// + // 3. AXI-S Interface // + //----------------------------------------------------------------------------------------------------------------// + + // Common + output user_clk_out, + output reg user_reset_out, + output user_lnk_up, + output wire user_app_rdy, + + // AXI TX + //----------- + output [5:0] tx_buf_av, + output tx_err_drop, + output tx_cfg_req, + input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, + input s_axis_tx_tvalid, + output s_axis_tx_tready, + input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, + input s_axis_tx_tlast, + input [3:0] s_axis_tx_tuser, + input tx_cfg_gnt, + + // AXI RX + //----------- + output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, + output m_axis_rx_tvalid, + input m_axis_rx_tready, + output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, + output m_axis_rx_tlast, + output [21:0] m_axis_rx_tuser, + input rx_np_ok, + input rx_np_req, + + // Flow Control + output [11:0] fc_cpld, + output [7:0] fc_cplh, + output [11:0] fc_npd, + output [7:0] fc_nph, + output [11:0] fc_pd, + output [7:0] fc_ph, + input [2:0] fc_sel, + + + //----------------------------------------------------------------------------------------------------------------// + // 4. Configuration (CFG) Interface // + //----------------------------------------------------------------------------------------------------------------// + + //------------------------------------------------// + // EP and RP // + //------------------------------------------------// + output wire [31:0] cfg_mgmt_do, + output wire cfg_mgmt_rd_wr_done, + + output wire [15:0] cfg_status, + output wire [15:0] cfg_command, + output wire [15:0] cfg_dstatus, + output wire [15:0] cfg_dcommand, + output wire [15:0] cfg_lstatus, + output wire [15:0] cfg_lcommand, + output wire [15:0] cfg_dcommand2, + output [2:0] cfg_pcie_link_state, + + output wire cfg_pmcsr_pme_en, + output wire [1:0] cfg_pmcsr_powerstate, + output wire cfg_pmcsr_pme_status, + output wire cfg_received_func_lvl_rst, + + // Management Interface + input wire [31:0] cfg_mgmt_di, + input wire [3:0] cfg_mgmt_byte_en, + input wire [9:0] cfg_mgmt_dwaddr, + input wire cfg_mgmt_wr_en, + input wire cfg_mgmt_rd_en, + input wire cfg_mgmt_wr_readonly, + + // Error Reporting Interface + input wire cfg_err_ecrc, + input wire cfg_err_ur, + input wire cfg_err_cpl_timeout, + input wire cfg_err_cpl_unexpect, + input wire cfg_err_cpl_abort, + input wire cfg_err_posted, + input wire cfg_err_cor, + input wire cfg_err_atomic_egress_blocked, + input wire cfg_err_internal_cor, + input wire cfg_err_malformed, + input wire cfg_err_mc_blocked, + input wire cfg_err_poisoned, + input wire cfg_err_norecovery, + input wire [47:0] cfg_err_tlp_cpl_header, + output wire cfg_err_cpl_rdy, + input wire cfg_err_locked, + input wire cfg_err_acs, + input wire cfg_err_internal_uncor, + + input wire cfg_trn_pending, + input wire cfg_pm_halt_aspm_l0s, + input wire cfg_pm_halt_aspm_l1, + input wire cfg_pm_force_state_en, + input wire [1:0] cfg_pm_force_state, + + input wire [63:0] cfg_dsn, + output cfg_msg_received, + output [15:0] cfg_msg_data, + + //------------------------------------------------// + // EP Only // + //------------------------------------------------// + + // Interrupt Interface Signals + input wire cfg_interrupt, + output wire cfg_interrupt_rdy, + input wire cfg_interrupt_assert, + input wire [7:0] cfg_interrupt_di, + output wire [7:0] cfg_interrupt_do, + output wire [2:0] cfg_interrupt_mmenable, + output wire cfg_interrupt_msienable, + output wire cfg_interrupt_msixenable, + output wire cfg_interrupt_msixfm, + input wire cfg_interrupt_stat, + input wire [4:0] cfg_pciecap_interrupt_msgnum, + + + output cfg_to_turnoff, + input wire cfg_turnoff_ok, + output wire [7:0] cfg_bus_number, + output wire [4:0] cfg_device_number, + output wire [2:0] cfg_function_number, + input wire cfg_pm_wake, + + output wire cfg_msg_received_pm_as_nak, + output wire cfg_msg_received_setslotpowerlimit, + + //------------------------------------------------// + // RP Only // + //------------------------------------------------// + input wire cfg_pm_send_pme_to, + input wire [7:0] cfg_ds_bus_number, + input wire [4:0] cfg_ds_device_number, + input wire [2:0] cfg_ds_function_number, + + input wire cfg_mgmt_wr_rw1c_as_rw, + + output wire cfg_bridge_serr_en, + output wire cfg_slot_control_electromech_il_ctl_pulse, + output wire cfg_root_control_syserr_corr_err_en, + output wire cfg_root_control_syserr_non_fatal_err_en, + output wire cfg_root_control_syserr_fatal_err_en, + output wire cfg_root_control_pme_int_en, + output wire cfg_aer_rooterr_corr_err_reporting_en, + output wire cfg_aer_rooterr_non_fatal_err_reporting_en, + output wire cfg_aer_rooterr_fatal_err_reporting_en, + output wire cfg_aer_rooterr_corr_err_received, + output wire cfg_aer_rooterr_non_fatal_err_received, + output wire cfg_aer_rooterr_fatal_err_received, + + output wire cfg_msg_received_err_cor, + output wire cfg_msg_received_err_non_fatal, + output wire cfg_msg_received_err_fatal, + output wire cfg_msg_received_pm_pme, + output wire cfg_msg_received_pme_to_ack, + output wire cfg_msg_received_assert_int_a, + output wire cfg_msg_received_assert_int_b, + output wire cfg_msg_received_assert_int_c, + output wire cfg_msg_received_assert_int_d, + output wire cfg_msg_received_deassert_int_a, + output wire cfg_msg_received_deassert_int_b, + output wire cfg_msg_received_deassert_int_c, + output wire cfg_msg_received_deassert_int_d, + + //----------------------------------------------------------------------------------------------------------------// + // 5. Physical Layer Control and Status (PL) Interface // + //----------------------------------------------------------------------------------------------------------------// + + //------------------------------------------------// + // EP and RP // + //------------------------------------------------// + input wire [1:0] pl_directed_link_change, + input wire [1:0] pl_directed_link_width, + input wire pl_directed_link_speed, + input wire pl_directed_link_auton, + input wire pl_upstream_prefer_deemph, + + + + output wire pl_sel_lnk_rate, + output wire [1:0] pl_sel_lnk_width, + output wire [5:0] pl_ltssm_state, + output wire [1:0] pl_lane_reversal_mode, + + output wire pl_phy_lnk_up, + output wire [2:0] pl_tx_pm_state, + output wire [1:0] pl_rx_pm_state, + + output wire pl_link_upcfg_cap, + output wire pl_link_gen2_cap, + output wire pl_link_partner_gen2_supported, + output wire [2:0] pl_initial_link_width, + + output wire pl_directed_change_done, + + //------------------------------------------------// + // EP Only // + //------------------------------------------------// + output wire pl_received_hot_rst, + + //------------------------------------------------// + // RP Only // + //------------------------------------------------// + input wire pl_transmit_hot_rst, + input wire pl_downstream_deemph_source, + + //----------------------------------------------------------------------------------------------------------------// + // 6. AER interface // + //----------------------------------------------------------------------------------------------------------------// + + input wire [127:0] cfg_err_aer_headerlog, + input wire [4:0] cfg_aer_interrupt_msgnum, + output wire cfg_err_aer_headerlog_set, + output wire cfg_aer_ecrc_check_en, + output wire cfg_aer_ecrc_gen_en, + + //----------------------------------------------------------------------------------------------------------------// + // 7. VC interface // + //----------------------------------------------------------------------------------------------------------------// + + output wire [6:0] cfg_vc_tcvc_map, + + //----------------------------------------------------------------------------------------------------------------// + // PCIe Fast Config: ICAP primitive Interface // + //----------------------------------------------------------------------------------------------------------------// + + input wire icap_clk, + input wire icap_csib, + input wire icap_rdwrb, + input wire [31:0] icap_i, + output wire [31:0] icap_o, + + + + input [ 2:0] pipe_txprbssel, + input [ 2:0] pipe_rxprbssel, + input pipe_txprbsforceerr, + input pipe_rxprbscntreset, + input [ 2:0] pipe_loopback, + + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_rxprbserr, + input [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_txinhibit, + + + output [4:0] pipe_rst_fsm, + output [11:0] pipe_qrst_fsm, + output [(LINK_CAP_MAX_LINK_WIDTH*5)-1:0] pipe_rate_fsm, + output [(LINK_CAP_MAX_LINK_WIDTH*6)-1:0] pipe_sync_fsm_tx, + output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_sync_fsm_rx, + output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_drp_fsm, + + output pipe_rst_idle, + output pipe_qrst_idle, + output pipe_rate_idle, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_eyescandataerror, + output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxstatus, + output [(LINK_CAP_MAX_LINK_WIDTH*15)-1:0] pipe_dmonitorout, + + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_cpll_lock, + output [(LINK_CAP_MAX_LINK_WIDTH-1)>>2:0] pipe_qpll_lock, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxpmaresetdone, + output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxbufstatus, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphaligndone, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphinitdone, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txdlysresetdone, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxphaligndone, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxdlysresetdone, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxsyncdone, + output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxdisperr, + output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxnotintable, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxcommadet, + + output [LINK_CAP_MAX_LINK_WIDTH-1:0] gt_ch_drp_rdy, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_0, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_1, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_2, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_3, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_4, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_5, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_6, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_7, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_8, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_9, + output [31:0] pipe_debug, + + //--------------Channel DRP--------------------------------- + output ext_ch_gt_drpclk, + input [(LINK_CAP_MAX_LINK_WIDTH*9)-1:0] ext_ch_gt_drpaddr, + input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpen, + input [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0] ext_ch_gt_drpdi, + input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpwe, + + output [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0] ext_ch_gt_drpdo, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drprdy, + + + //----------------------------------------------------------------------------------------------------------------// + // PCIe Fast Config: STARTUP primitive Interface // + //----------------------------------------------------------------------------------------------------------------// + + // This input should be used when the startup block is generated exteranl to the PCI Express Core + input startup_eos_in, // 1-bit input: This signal should be driven by the EOS output of the STARTUP primitive. + // These inputs and outputs may be use when the startup block is generated internal to the PCI Express Core. + output startup_cfgclk, // 1-bit output: Configuration main clock output + output startup_cfgmclk, // 1-bit output: Configuration internal oscillator clock output + output startup_eos, // 1-bit output: Active high output signal indicating the End Of Startup + output startup_preq, // 1-bit output: PROGRAM request to fabric output + input startup_clk, // 1-bit input: User start-up clock input + input startup_gsr, // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name) + input startup_gts, // 1-bit input: Global 3-state input (GTS cannot be used for the port name) + input startup_keyclearb, // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) + input startup_pack, // 1-bit input: PROGRAM acknowledge input + input startup_usrcclko, // 1-bit input: User CCLK input + input startup_usrcclkts, // 1-bit input: User CCLK 3-state enable input + input startup_usrdoneo, // 1-bit input: User DONE pin output control + input startup_usrdonets, // 1-bit input: User DONE 3-state enable output + + //----------------------------------------------------------------------------------------------------------------// + // 8. PCIe DRP (PCIe DRP) Interface // + //----------------------------------------------------------------------------------------------------------------// + + input wire pcie_drp_clk, + input wire pcie_drp_en, + input wire pcie_drp_we, + input wire [8:0] pcie_drp_addr, + input wire [15:0] pcie_drp_di, + output wire pcie_drp_rdy, + output wire [15:0] pcie_drp_do, + //----------------------------------------------------------------------------------------------------------------// + // PIPE PORTS to TOP Level For PIPE SIMULATION with 3rd Party IP/BFM/Xilinx BFM + //----------------------------------------------------------------------------------------------------------------// + input wire [11:0] common_commands_in, + input wire [24:0] pipe_rx_0_sigs, + input wire [24:0] pipe_rx_1_sigs, + input wire [24:0] pipe_rx_2_sigs, + input wire [24:0] pipe_rx_3_sigs, + input wire [24:0] pipe_rx_4_sigs, + input wire [24:0] pipe_rx_5_sigs, + input wire [24:0] pipe_rx_6_sigs, + input wire [24:0] pipe_rx_7_sigs, + + output wire [11:0] common_commands_out, + output wire [24:0] pipe_tx_0_sigs, + output wire [24:0] pipe_tx_1_sigs, + output wire [24:0] pipe_tx_2_sigs, + output wire [24:0] pipe_tx_3_sigs, + output wire [24:0] pipe_tx_4_sigs, + output wire [24:0] pipe_tx_5_sigs, + output wire [24:0] pipe_tx_6_sigs, + output wire [24:0] pipe_tx_7_sigs, + //----------------------------------------------------------------------------------------------------------------// + // 9. System(SYS) Interface // + //----------------------------------------------------------------------------------------------------------------// + + input wire pipe_mmcm_rst_n, // Async | Async + input wire sys_clk, + input wire sys_rst_n +); + + wire user_clk; + wire user_clk2; + wire pipe_clk; + wire [15:0] cfg_vend_id = CFG_VEND_ID; + wire [15:0] cfg_dev_id = CFG_DEV_ID; + wire [7:0] cfg_rev_id = CFG_REV_ID; + wire [15:0] cfg_subsys_vend_id = CFG_SUBSYS_VEND_ID; + wire [15:0] cfg_subsys_id = CFG_SUBSYS_ID; + + // PIPE Interface Wires + wire phy_rdy_n; + wire pipe_rx0_polarity_gt; + wire pipe_rx1_polarity_gt; + wire pipe_rx2_polarity_gt; + wire pipe_rx3_polarity_gt; + wire pipe_rx4_polarity_gt; + wire pipe_rx5_polarity_gt; + wire pipe_rx6_polarity_gt; + wire pipe_rx7_polarity_gt; + wire pipe_tx_deemph_gt; + wire [2:0] pipe_tx_margin_gt; + wire pipe_tx_rate_gt; + wire pipe_tx_rcvr_det_gt; + wire [1:0] pipe_tx0_char_is_k_gt; + wire pipe_tx0_compliance_gt; + wire [15:0] pipe_tx0_data_gt; + wire pipe_tx0_elec_idle_gt; + wire [1:0] pipe_tx0_powerdown_gt; + wire [1:0] pipe_tx1_char_is_k_gt; + wire pipe_tx1_compliance_gt; + wire [15:0] pipe_tx1_data_gt; + wire pipe_tx1_elec_idle_gt; + wire [1:0] pipe_tx1_powerdown_gt; + wire [1:0] pipe_tx2_char_is_k_gt; + wire pipe_tx2_compliance_gt; + wire [15:0] pipe_tx2_data_gt; + wire pipe_tx2_elec_idle_gt; + wire [1:0] pipe_tx2_powerdown_gt; + wire [1:0] pipe_tx3_char_is_k_gt; + wire pipe_tx3_compliance_gt; + wire [15:0] pipe_tx3_data_gt; + wire pipe_tx3_elec_idle_gt; + wire [1:0] pipe_tx3_powerdown_gt; + wire [1:0] pipe_tx4_char_is_k_gt; + wire pipe_tx4_compliance_gt; + wire [15:0] pipe_tx4_data_gt; + wire pipe_tx4_elec_idle_gt; + wire [1:0] pipe_tx4_powerdown_gt; + wire [1:0] pipe_tx5_char_is_k_gt; + wire pipe_tx5_compliance_gt; + wire [15:0] pipe_tx5_data_gt; + wire pipe_tx5_elec_idle_gt; + wire [1:0] pipe_tx5_powerdown_gt; + wire [1:0] pipe_tx6_char_is_k_gt; + wire pipe_tx6_compliance_gt; + wire [15:0] pipe_tx6_data_gt; + wire pipe_tx6_elec_idle_gt; + wire [1:0] pipe_tx6_powerdown_gt; + wire [1:0] pipe_tx7_char_is_k_gt; + wire pipe_tx7_compliance_gt; + wire [15:0] pipe_tx7_data_gt; + wire pipe_tx7_elec_idle_gt; + wire [1:0] pipe_tx7_powerdown_gt; + + wire pipe_rx0_chanisaligned_gt; + wire [1:0] pipe_rx0_char_is_k_gt; + wire [15:0] pipe_rx0_data_gt; + wire pipe_rx0_elec_idle_gt; + wire pipe_rx0_phy_status_gt; + wire [2:0] pipe_rx0_status_gt; + wire pipe_rx0_valid_gt; + wire pipe_rx1_chanisaligned_gt; + wire [1:0] pipe_rx1_char_is_k_gt; + wire [15:0] pipe_rx1_data_gt; + wire pipe_rx1_elec_idle_gt; + wire pipe_rx1_phy_status_gt; + wire [2:0] pipe_rx1_status_gt; + wire pipe_rx1_valid_gt; + wire pipe_rx2_chanisaligned_gt; + wire [1:0] pipe_rx2_char_is_k_gt; + wire [15:0] pipe_rx2_data_gt; + wire pipe_rx2_elec_idle_gt; + wire pipe_rx2_phy_status_gt; + wire [2:0] pipe_rx2_status_gt; + wire pipe_rx2_valid_gt; + wire pipe_rx3_chanisaligned_gt; + wire [1:0] pipe_rx3_char_is_k_gt; + wire [15:0] pipe_rx3_data_gt; + wire pipe_rx3_elec_idle_gt; + wire pipe_rx3_phy_status_gt; + wire [2:0] pipe_rx3_status_gt; + wire pipe_rx3_valid_gt; + wire pipe_rx4_chanisaligned_gt; + wire [1:0] pipe_rx4_char_is_k_gt; + wire [15:0] pipe_rx4_data_gt; + wire pipe_rx4_elec_idle_gt; + wire pipe_rx4_phy_status_gt; + wire [2:0] pipe_rx4_status_gt; + wire pipe_rx4_valid_gt; + wire pipe_rx5_chanisaligned_gt; + wire [1:0] pipe_rx5_char_is_k_gt; + wire [15:0] pipe_rx5_data_gt; + wire pipe_rx5_elec_idle_gt; + wire pipe_rx5_phy_status_gt; + wire [2:0] pipe_rx5_status_gt; + wire pipe_rx5_valid_gt; + wire pipe_rx6_chanisaligned_gt; + wire [1:0] pipe_rx6_char_is_k_gt; + wire [15:0] pipe_rx6_data_gt; + wire pipe_rx6_elec_idle_gt; + wire pipe_rx6_phy_status_gt; + wire [2:0] pipe_rx6_status_gt; + wire pipe_rx6_valid_gt; + wire pipe_rx7_chanisaligned_gt; + wire [1:0] pipe_rx7_char_is_k_gt; + wire [15:0] pipe_rx7_data_gt; + wire pipe_rx7_elec_idle_gt; + wire pipe_rx7_phy_status_gt; + wire [2:0] pipe_rx7_status_gt; + wire pipe_rx7_valid_gt; + wire [3:0] cfg_link_status_negotiated_width; + wire [1:0] cfg_link_status_current_speed; + + + (* ASYNC_REG = "TRUE" *) reg user_lnk_up_mux; + (* KEEP = "TRUE", ASYNC_REG = "TRUE" *) reg user_lnk_up_int; + reg user_reset_int; + + reg bridge_reset_int; + reg bridge_reset_d; + wire user_rst_n; + reg pl_received_hot_rst_q; + wire pl_received_hot_rst_wire; + wire pl_received_hot_rst_sync; + reg pl_phy_lnk_up_q; + wire pl_phy_lnk_up_wire; + wire pl_phy_lnk_up_sync; + wire sys_or_hot_rst; + wire trn_lnk_up; + + wire [5:0] pl_ltssm_state_int; + wire user_app_rdy_req; + + localparam TCQ = 100; + localparam ENABLE_FAST_SIM_TRAINING = "TRUE"; + + assign user_lnk_up = user_lnk_up_int; + + + assign user_app_rdy = 1'b1; + assign pl_ltssm_state = pl_ltssm_state_int; + assign pl_phy_lnk_up = pl_phy_lnk_up_q; + assign pl_received_hot_rst = pl_received_hot_rst_q; + + // CDC on PCIe block outputs The source clock of these pins is in + // the pipe_clk domain. + xpm_cdc_single #( + .DEST_SYNC_FF (2), + .SRC_INPUT_REG (0) + ) phy_lnk_up_cdc ( + .src_clk (pipe_clk), + .src_in (pl_phy_lnk_up_wire), + .dest_clk (user_clk_out), + .dest_out (pl_phy_lnk_up_sync) + ); + xpm_cdc_single #( + .DEST_SYNC_FF (2), + .SRC_INPUT_REG (0) + ) pl_received_hot_rst_cdc ( + .src_clk (pipe_clk), + .src_in (pl_received_hot_rst_wire), + .dest_clk (user_clk_out), + .dest_out (pl_received_hot_rst_sync) + ); + + // Register block outputs pl_received_hot_rst and phy_lnk_up to ease timing on block output + assign sys_or_hot_rst = !sys_rst_n || pl_received_hot_rst_q; + always @(posedge user_clk_out) + begin + if (!sys_rst_n) begin + pl_received_hot_rst_q <= #TCQ 1'b0; + pl_phy_lnk_up_q <= #TCQ 1'b0; + end else begin + pl_received_hot_rst_q <= #TCQ pl_received_hot_rst_sync; + pl_phy_lnk_up_q <= #TCQ pl_phy_lnk_up_sync; + end + end + // Generate user_lnk_up_mux + always @(posedge user_clk_out) + begin + if (!sys_rst_n) begin + user_lnk_up_mux <= #TCQ 1'b0; + end else begin + user_lnk_up_mux <= #TCQ user_lnk_up_int; + end + end + + always @(posedge user_clk_out) + begin + if (!sys_rst_n) begin + user_lnk_up_int <= #TCQ 1'b0; + end else begin + user_lnk_up_int <= #TCQ trn_lnk_up; + end + end + + + // Generate user_reset_out // + // Once user reset output of PCIE and Phy Layer is active, de-assert reset // + // Only assert reset if system reset or hot reset is seen. Keep AXI backend/user application alive otherwise // + //------------------------------------------------------------------------------------------------------------------// + + always @(posedge user_clk_out or posedge sys_or_hot_rst) + begin + if (sys_or_hot_rst) begin + user_reset_int <= #TCQ 1'b1; + end else if (user_rst_n && pl_phy_lnk_up_q) begin + user_reset_int <= #TCQ 1'b0; + end + end + + // Invert active low reset to active high AXI reset + always @(posedge user_clk_out or posedge sys_or_hot_rst) + begin + if (sys_or_hot_rst) begin + user_reset_out <= #TCQ 1'b1; + end else begin + user_reset_out <= #TCQ user_reset_int; + end + end + always @(posedge user_clk_out or posedge sys_or_hot_rst) + begin + if (sys_or_hot_rst) begin + bridge_reset_int <= #TCQ 1'b1; + end else if (user_rst_n && pl_phy_lnk_up_q) begin + bridge_reset_int <= #TCQ 1'b0; + end + end + + // Invert active low reset to active high AXI reset + always @(posedge user_clk_out or posedge sys_or_hot_rst) + begin + if (sys_or_hot_rst) begin + bridge_reset_d <= #TCQ 1'b1; + end else begin + bridge_reset_d <= #TCQ bridge_reset_int; + end + end + + //------------------------------------------------------------------------------------------------------------------// + // **** PCI Express Core Wrapper **** // + // The PCI Express Core Wrapper includes the following: // + // 1) AXI Streaming Bridge // + // 2) PCIE 2_1 Hard Block // + // 3) PCIE PIPE Interface Pipeline // + //------------------------------------------------------------------------------------------------------------------// +pcie_7x_0_pcie_top # ( + .PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ), + .AER_BASE_PTR ( AER_BASE_PTR ), + .AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ), + .AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ), + .AER_CAP_ID ( AER_CAP_ID ), + .AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ), + .AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ), + .AER_CAP_ON ( AER_CAP_ON ), + .AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ), + .AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ), + .AER_CAP_VERSION ( AER_CAP_VERSION ), + .ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ), + .BAR0 ( BAR0 ), + .BAR1 ( BAR1 ), + .BAR2 ( BAR2 ), + .BAR3 ( BAR3 ), + .BAR4 ( BAR4 ), + .BAR5 ( BAR5 ), + .C_DATA_WIDTH ( C_DATA_WIDTH ), + .CAPABILITIES_PTR ( CAPABILITIES_PTR ), + .CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ), + .CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ), + .CLASS_CODE ( CLASS_CODE ), + .CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ), + .CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ), + .CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ), + .CRM_MODULE_RSTS ( CRM_MODULE_RSTS ), + .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ), + .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ), + .DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ), + .DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ), + .DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ), + .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ), + .DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ), + .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ), + .DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ), + .DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ), + .DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ), + .DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ), + .DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ), + .DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ), + .DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ), + .DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ), + .DISABLE_ID_CHECK ( DISABLE_ID_CHECK ), + .DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ), + .DISABLE_RX_POISONED_RESP ( DISABLE_RX_POISONED_RESP ), + .DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ), + .DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ), + .DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ), + .DSN_BASE_PTR ( DSN_BASE_PTR ), + .DSN_CAP_ID ( DSN_CAP_ID ), + .DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ), + .DSN_CAP_ON ( DSN_CAP_ON ), + .DSN_CAP_VERSION ( DSN_CAP_VERSION ), + .DEV_CAP2_ARI_FORWARDING_SUPPORTED ( DEV_CAP2_ARI_FORWARDING_SUPPORTED ), + .DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ), + .DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ), + .DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ( DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ), + .DEV_CAP2_CAS128_COMPLETER_SUPPORTED ( DEV_CAP2_CAS128_COMPLETER_SUPPORTED ), + .DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ( DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ), + .DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ( DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ), + .DEV_CAP2_LTR_MECHANISM_SUPPORTED ( DEV_CAP2_LTR_MECHANISM_SUPPORTED ), + .DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ( DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ), + .DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ( DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ), + .DEV_CAP2_TPH_COMPLETER_SUPPORTED ( DEV_CAP2_TPH_COMPLETER_SUPPORTED ), + .DISABLE_ERR_MSG ( DISABLE_ERR_MSG ), + .DISABLE_LOCKED_FILTER ( DISABLE_LOCKED_FILTER ), + .DISABLE_PPM_FILTER ( DISABLE_PPM_FILTER ), + .ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ( ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ), + .ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ), + .ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ), + .ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ), + .EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ), + .EXPANSION_ROM ( EXPANSION_ROM ), + .EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ), + .EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ), + .HEADER_TYPE ( HEADER_TYPE ), + .INFER_EI ( INFER_EI ), + .INTERRUPT_PIN ( INTERRUPT_PIN ), + .INTERRUPT_STAT_AUTO ( INTERRUPT_STAT_AUTO ), + .IS_SWITCH ( IS_SWITCH ), + .LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ), + .LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ), + .LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ), + .LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ), + .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ), + .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ), + .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ), + .LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ), + .LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ), + .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ), + .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ), + .LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ), + .LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ), + .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ), + .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ), + .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), + .LINK_CAP_RSVD_23 ( LINK_CAP_RSVD_23 ), + .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ), + .LINK_CONTROL_RCB ( LINK_CONTROL_RCB ), + .LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ), + .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ), + .LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ), + .LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ), + .LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ), + .LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ), + .LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ), + .LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ), + .LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ), + .LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ), + .LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ), + .MPS_FORCE ( MPS_FORCE), + .MSI_BASE_PTR ( MSI_BASE_PTR ), + .MSI_CAP_ID ( MSI_CAP_ID ), + .MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ), + .MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ), + .MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ), + .MSI_CAP_ON ( MSI_CAP_ON ), + .MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ), + .MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ), + .MSIX_BASE_PTR ( MSIX_BASE_PTR ), + .MSIX_CAP_ID ( MSIX_CAP_ID ), + .MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ), + .MSIX_CAP_ON ( MSIX_CAP_ON ), + .MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ), + .MSIX_CAP_PBA_OFFSET ( {3'b000,MSIX_CAP_PBA_OFFSET[28:3]} ), + .MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ), + .MSIX_CAP_TABLE_OFFSET ( {3'b000,MSIX_CAP_TABLE_OFFSET[28:3]} ), + .MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ), + .N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ), + .N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ), + .N_FTS_GEN1 ( N_FTS_GEN1 ), + .N_FTS_GEN2 ( N_FTS_GEN2 ), + .PCIE_BASE_PTR ( PCIE_BASE_PTR ), + .PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ), + .PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ), + .PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ), + .PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ), + .PCIE_CAP_ON ( PCIE_CAP_ON ), + .PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ), + .PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ), + .PCIE_REVISION ( PCIE_REVISION ), + .PL_AUTO_CONFIG ( PL_AUTO_CONFIG ), + + // synthesis translate_off + .PL_FAST_TRAIN ( ENABLE_FAST_SIM_TRAINING ), + // synthesis translate_on + + .PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ), + .PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ), + .PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ), + .PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ), + .PM_BASE_PTR ( PM_BASE_PTR ), + .PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ), + .PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ), + .PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ), + .PM_CAP_DSI ( PM_CAP_DSI ), + .PM_CAP_ID ( PM_CAP_ID ), + .PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ), + .PM_CAP_ON ( PM_CAP_ON ), + .PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ), + .PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ), + .PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ), + .PM_CAP_VERSION ( PM_CAP_VERSION ), + .PM_CSR_B2B3 ( PM_CSR_B2B3 ), + .PM_CSR_BPCCEN ( PM_CSR_BPCCEN ), + .PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ), + .PM_DATA0 ( PM_DATA0 ), + .PM_DATA1 ( PM_DATA1 ), + .PM_DATA2 ( PM_DATA2 ), + .PM_DATA3 ( PM_DATA3 ), + .PM_DATA4 ( PM_DATA4 ), + .PM_DATA5 ( PM_DATA5 ), + .PM_DATA6 ( PM_DATA6 ), + .PM_DATA7 ( PM_DATA7 ), + .PM_DATA_SCALE0 ( PM_DATA_SCALE0 ), + .PM_DATA_SCALE1 ( PM_DATA_SCALE1 ), + .PM_DATA_SCALE2 ( PM_DATA_SCALE2 ), + .PM_DATA_SCALE3 ( PM_DATA_SCALE3 ), + .PM_DATA_SCALE4 ( PM_DATA_SCALE4 ), + .PM_DATA_SCALE5 ( PM_DATA_SCALE5 ), + .PM_DATA_SCALE6 ( PM_DATA_SCALE6 ), + .PM_DATA_SCALE7 ( PM_DATA_SCALE7 ), + .PM_MF ( PM_MF ), + .RBAR_BASE_PTR ( RBAR_BASE_PTR ), + .RBAR_CAP_CONTROL_ENCODEDBAR0 ( RBAR_CAP_CONTROL_ENCODEDBAR0 ), + .RBAR_CAP_CONTROL_ENCODEDBAR1 ( RBAR_CAP_CONTROL_ENCODEDBAR1 ), + .RBAR_CAP_CONTROL_ENCODEDBAR2 ( RBAR_CAP_CONTROL_ENCODEDBAR2 ), + .RBAR_CAP_CONTROL_ENCODEDBAR3 ( RBAR_CAP_CONTROL_ENCODEDBAR3 ), + .RBAR_CAP_CONTROL_ENCODEDBAR4 ( RBAR_CAP_CONTROL_ENCODEDBAR4 ), + .RBAR_CAP_CONTROL_ENCODEDBAR5 ( RBAR_CAP_CONTROL_ENCODEDBAR5 ), + .RBAR_CAP_ID ( RBAR_CAP_ID), + .RBAR_CAP_INDEX0 ( RBAR_CAP_INDEX0 ), + .RBAR_CAP_INDEX1 ( RBAR_CAP_INDEX1 ), + .RBAR_CAP_INDEX2 ( RBAR_CAP_INDEX2 ), + .RBAR_CAP_INDEX3 ( RBAR_CAP_INDEX3 ), + .RBAR_CAP_INDEX4 ( RBAR_CAP_INDEX4 ), + .RBAR_CAP_INDEX5 ( RBAR_CAP_INDEX5 ), + .RBAR_CAP_NEXTPTR ( RBAR_CAP_NEXTPTR ), + .RBAR_CAP_ON ( RBAR_CAP_ON ), + .RBAR_CAP_SUP0 ( RBAR_CAP_SUP0 ), + .RBAR_CAP_SUP1 ( RBAR_CAP_SUP1 ), + .RBAR_CAP_SUP2 ( RBAR_CAP_SUP2 ), + .RBAR_CAP_SUP3 ( RBAR_CAP_SUP3 ), + .RBAR_CAP_SUP4 ( RBAR_CAP_SUP4 ), + .RBAR_CAP_SUP5 ( RBAR_CAP_SUP5 ), + .RBAR_CAP_VERSION ( RBAR_CAP_VERSION ), + .RBAR_NUM ( RBAR_NUM ), + .RECRC_CHK ( RECRC_CHK ), + .RECRC_CHK_TRIM ( RECRC_CHK_TRIM ), + .ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ), + .RP_AUTO_SPD ( RP_AUTO_SPD ), + .RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ), + .SELECT_DLL_IF ( SELECT_DLL_IF ), + .SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ), + .SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ), + .SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ), + .SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ), + .SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ), + .SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ), + .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ), + .SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ), + .SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ), + .SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ), + .SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ), + .SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ), + .SPARE_BIT0 ( SPARE_BIT0 ), + .SPARE_BIT1 ( SPARE_BIT1 ), + .SPARE_BIT2 ( SPARE_BIT2 ), + .SPARE_BIT3 ( SPARE_BIT3 ), + .SPARE_BIT4 ( SPARE_BIT4 ), + .SPARE_BIT5 ( SPARE_BIT5 ), + .SPARE_BIT6 ( SPARE_BIT6 ), + .SPARE_BIT7 ( SPARE_BIT7 ), + .SPARE_BIT8 ( SPARE_BIT8 ), + .SPARE_BYTE0 ( SPARE_BYTE0 ), + .SPARE_BYTE1 ( SPARE_BYTE1 ), + .SPARE_BYTE2 ( SPARE_BYTE2 ), + .SPARE_BYTE3 ( SPARE_BYTE3 ), + .SPARE_WORD0 ( SPARE_WORD0 ), + .SPARE_WORD1 ( SPARE_WORD1 ), + .SPARE_WORD2 ( SPARE_WORD2 ), + .SPARE_WORD3 ( SPARE_WORD3 ), + .SSL_MESSAGE_AUTO ( SSL_MESSAGE_AUTO ), + .TECRC_EP_INV ( TECRC_EP_INV ), + .TL_RBYPASS ( TL_RBYPASS ), + .TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ), + .TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ), + .TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ), + .TL_TFC_DISABLE ( TL_TFC_DISABLE ), + .TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ), + .TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ), + .TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ), + .TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ), + .TRN_DW ( TRN_DW ), + .TRN_NP_FC ( TRN_NP_FC ), + .UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ), + .UPSTREAM_FACING ( UPSTREAM_FACING ), + .UR_ATOMIC ( UR_ATOMIC ), + .UR_CFG1 ( UR_CFG1 ), + .UR_INV_REQ ( UR_INV_REQ ), + .UR_PRS_RESPONSE ( UR_PRS_RESPONSE ), + .USER_CLK2_DIV2 ( USER_CLK2_DIV2 ), + .USER_CLK_FREQ ( USER_CLK_FREQ ), + .USE_RID_PINS ( USE_RID_PINS ), + .VC0_CPL_INFINITE ( VC0_CPL_INFINITE ), + .VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ), + .VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ), + .VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ), + .VC0_TOTAL_CREDITS_NPD ( VC0_TOTAL_CREDITS_NPD), + .VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ), + .VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ), + .VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ), + .VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ), + .VC_BASE_PTR ( VC_BASE_PTR ), + .VC_CAP_ID ( VC_CAP_ID ), + .VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ), + .VC_CAP_ON ( VC_CAP_ON ), + .VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ), + .VC_CAP_VERSION ( VC_CAP_VERSION ), + .VSEC_BASE_PTR ( VSEC_BASE_PTR ), + .VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ), + .VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ), + .VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ), + .VSEC_CAP_ID ( VSEC_CAP_ID ), + .VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ), + .VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ), + .VSEC_CAP_ON ( VSEC_CAP_ON ), + .VSEC_CAP_VERSION ( VSEC_CAP_VERSION ) + // I/O + ) pcie_top_i ( + + // AXI Interface + .user_clk_out ( user_clk_out ), + .user_reset ( bridge_reset_d ), + .user_lnk_up ( user_lnk_up ), + + .user_rst_n ( user_rst_n ), + .trn_lnk_up ( trn_lnk_up ), + + .tx_buf_av ( tx_buf_av ), + .tx_err_drop ( tx_err_drop ), + .tx_cfg_req ( tx_cfg_req ), + .s_axis_tx_tready ( s_axis_tx_tready ), + .s_axis_tx_tdata ( s_axis_tx_tdata ), + .s_axis_tx_tkeep ( s_axis_tx_tkeep ), + .s_axis_tx_tuser ( s_axis_tx_tuser ), + .s_axis_tx_tlast ( s_axis_tx_tlast ), + .s_axis_tx_tvalid ( s_axis_tx_tvalid ), + .tx_cfg_gnt ( tx_cfg_gnt ), + + .m_axis_rx_tdata ( m_axis_rx_tdata ), + .m_axis_rx_tkeep ( m_axis_rx_tkeep ), + .m_axis_rx_tlast ( m_axis_rx_tlast ), + .m_axis_rx_tvalid ( m_axis_rx_tvalid ), + .m_axis_rx_tready ( m_axis_rx_tready ), + .m_axis_rx_tuser ( m_axis_rx_tuser ), + .rx_np_ok ( rx_np_ok ), + .rx_np_req ( rx_np_req ), + + .fc_cpld ( fc_cpld ), + .fc_cplh ( fc_cplh ), + .fc_npd ( fc_npd ), + .fc_nph ( fc_nph ), + .fc_pd ( fc_pd ), + .fc_ph ( fc_ph ), + .fc_sel ( fc_sel ), + .cfg_turnoff_ok ( cfg_turnoff_ok ), + .cfg_received_func_lvl_rst ( cfg_received_func_lvl_rst ), + + .cm_rst_n ( 1'b1 ), + .func_lvl_rst_n ( 1'b1 ), + .lnk_clk_en ( ), + .cfg_dev_id ( cfg_dev_id ), + .cfg_vend_id ( cfg_vend_id ), + .cfg_rev_id ( cfg_rev_id ), + .cfg_subsys_id ( cfg_subsys_id ), + .cfg_subsys_vend_id ( cfg_subsys_vend_id ), + .cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ), + + .cfg_bridge_serr_en ( cfg_bridge_serr_en ), + + .cfg_command_bus_master_enable ( ), + .cfg_command_interrupt_disable ( ), + .cfg_command_io_enable ( ), + .cfg_command_mem_enable ( ), + .cfg_command_serr_en ( ), + .cfg_dev_control_aux_power_en ( ), + .cfg_dev_control_corr_err_reporting_en ( ), + .cfg_dev_control_enable_ro ( ), + .cfg_dev_control_ext_tag_en ( ), + .cfg_dev_control_fatal_err_reporting_en ( ), + .cfg_dev_control_max_payload ( ), + .cfg_dev_control_max_read_req ( ), + .cfg_dev_control_non_fatal_reporting_en ( ), + .cfg_dev_control_no_snoop_en ( ), + .cfg_dev_control_phantom_en ( ), + .cfg_dev_control_ur_err_reporting_en ( ), + .cfg_dev_control2_cpl_timeout_dis ( ), + .cfg_dev_control2_cpl_timeout_val ( ), + .cfg_dev_control2_ari_forward_en ( ), + .cfg_dev_control2_atomic_requester_en ( ), + .cfg_dev_control2_atomic_egress_block ( ), + .cfg_dev_control2_ido_req_en ( ), + .cfg_dev_control2_ido_cpl_en ( ), + .cfg_dev_control2_ltr_en ( ), + .cfg_dev_control2_tlp_prefix_block ( ), + .cfg_dev_status_corr_err_detected ( ), + .cfg_dev_status_fatal_err_detected ( ), + .cfg_dev_status_non_fatal_err_detected ( ), + .cfg_dev_status_ur_detected ( ), + + .cfg_mgmt_do ( cfg_mgmt_do ), + .cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ), + .cfg_err_aer_headerlog ( cfg_err_aer_headerlog ), + .cfg_err_cpl_rdy ( cfg_err_cpl_rdy ), + .cfg_interrupt_do ( cfg_interrupt_do ), + .cfg_interrupt_mmenable ( cfg_interrupt_mmenable ), + .cfg_interrupt_msienable ( cfg_interrupt_msienable ), + .cfg_interrupt_msixenable ( cfg_interrupt_msixenable ), + .cfg_interrupt_msixfm ( cfg_interrupt_msixfm ), + .cfg_interrupt_rdy ( cfg_interrupt_rdy ), + .cfg_link_control_rcb ( ), + .cfg_link_control_aspm_control ( ), + .cfg_link_control_auto_bandwidth_int_en ( ), + .cfg_link_control_bandwidth_int_en ( ), + .cfg_link_control_clock_pm_en ( ), + .cfg_link_control_common_clock ( ), + .cfg_link_control_extended_sync ( ), + .cfg_link_control_hw_auto_width_dis ( ), + .cfg_link_control_link_disable ( ), + .cfg_link_control_retrain_link ( ), + .cfg_link_status_auto_bandwidth_status ( ), + .cfg_link_status_bandwidth_status ( ), + .cfg_link_status_current_speed ( cfg_link_status_current_speed ), + .cfg_link_status_dll_active ( ), + .cfg_link_status_link_training ( ), + .cfg_link_status_negotiated_width ( cfg_link_status_negotiated_width ), + .cfg_msg_data ( cfg_msg_data ), + .cfg_msg_received ( cfg_msg_received ), + .cfg_msg_received_assert_int_a ( cfg_msg_received_assert_int_a ), + .cfg_msg_received_assert_int_b ( cfg_msg_received_assert_int_b ), + .cfg_msg_received_assert_int_c ( cfg_msg_received_assert_int_c ), + .cfg_msg_received_assert_int_d ( cfg_msg_received_assert_int_d ), + .cfg_msg_received_deassert_int_a ( cfg_msg_received_deassert_int_a ), + .cfg_msg_received_deassert_int_b ( cfg_msg_received_deassert_int_b ), + .cfg_msg_received_deassert_int_c ( cfg_msg_received_deassert_int_c ), + .cfg_msg_received_deassert_int_d ( cfg_msg_received_deassert_int_d ), + .cfg_msg_received_err_cor ( cfg_msg_received_err_cor ), + .cfg_msg_received_err_fatal ( cfg_msg_received_err_fatal ), + .cfg_msg_received_err_non_fatal ( cfg_msg_received_err_non_fatal ), + .cfg_msg_received_pm_as_nak ( cfg_msg_received_pm_as_nak ), + .cfg_msg_received_pme_to ( ), + .cfg_msg_received_pme_to_ack ( cfg_msg_received_pme_to_ack ), + .cfg_msg_received_pm_pme ( cfg_msg_received_pm_pme ), + .cfg_msg_received_setslotpowerlimit ( cfg_msg_received_setslotpowerlimit ), + .cfg_msg_received_unlock ( ), + .cfg_to_turnoff ( cfg_to_turnoff ), + .cfg_status ( cfg_status ), + .cfg_command ( cfg_command ), + .cfg_dstatus ( cfg_dstatus ), + .cfg_dcommand ( cfg_dcommand ), + .cfg_lstatus ( cfg_lstatus ), + .cfg_lcommand ( cfg_lcommand ), + .cfg_dcommand2 ( cfg_dcommand2 ), + .cfg_pcie_link_state ( cfg_pcie_link_state ), + .cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ), + .cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ), + .cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ), + .cfg_pm_rcv_as_req_l1_n ( ), + .cfg_pm_rcv_enter_l1_n ( ), + .cfg_pm_rcv_enter_l23_n ( ), + .cfg_pm_rcv_req_ack_n ( ), + .cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ), + .cfg_slot_control_electromech_il_ctl_pulse ( cfg_slot_control_electromech_il_ctl_pulse ), + .cfg_root_control_syserr_corr_err_en ( cfg_root_control_syserr_corr_err_en ), + .cfg_root_control_syserr_non_fatal_err_en ( cfg_root_control_syserr_non_fatal_err_en ), + .cfg_root_control_syserr_fatal_err_en ( cfg_root_control_syserr_fatal_err_en ), + .cfg_root_control_pme_int_en ( cfg_root_control_pme_int_en), + .cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ), + .cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ), + .cfg_aer_rooterr_corr_err_reporting_en ( cfg_aer_rooterr_corr_err_reporting_en ), + .cfg_aer_rooterr_non_fatal_err_reporting_en ( cfg_aer_rooterr_non_fatal_err_reporting_en ), + .cfg_aer_rooterr_fatal_err_reporting_en ( cfg_aer_rooterr_fatal_err_reporting_en ), + .cfg_aer_rooterr_corr_err_received ( cfg_aer_rooterr_corr_err_received ), + .cfg_aer_rooterr_non_fatal_err_received ( cfg_aer_rooterr_non_fatal_err_received ), + .cfg_aer_rooterr_fatal_err_received ( cfg_aer_rooterr_fatal_err_received ), + .cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ), + .cfg_transaction ( ), + .cfg_transaction_addr ( ), + .cfg_transaction_type ( ), + .cfg_vc_tcvc_map ( cfg_vc_tcvc_map ), + .cfg_mgmt_byte_en_n ( ~cfg_mgmt_byte_en ), + .cfg_mgmt_di ( cfg_mgmt_di ), + .cfg_dsn ( cfg_dsn ), + .cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ), + .cfg_err_acs_n ( 1'b1 ), + .cfg_err_cor_n ( ~cfg_err_cor ), + .cfg_err_cpl_abort_n ( ~cfg_err_cpl_abort ), + .cfg_err_cpl_timeout_n ( ~cfg_err_cpl_timeout ), + .cfg_err_cpl_unexpect_n ( ~cfg_err_cpl_unexpect ), + .cfg_err_ecrc_n ( ~cfg_err_ecrc ), + .cfg_err_locked_n ( ~cfg_err_locked ), + .cfg_err_posted_n ( ~cfg_err_posted ), + .cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ), + .cfg_err_ur_n ( ~cfg_err_ur ), + .cfg_err_malformed_n ( ~cfg_err_malformed ), + .cfg_err_poisoned_n ( ~cfg_err_poisoned ), + .cfg_err_atomic_egress_blocked_n ( ~cfg_err_atomic_egress_blocked ), + .cfg_err_mc_blocked_n ( ~cfg_err_mc_blocked ), + .cfg_err_internal_uncor_n ( ~cfg_err_internal_uncor ), + .cfg_err_internal_cor_n ( ~cfg_err_internal_cor ), + .cfg_err_norecovery_n ( ~cfg_err_norecovery ), + + .cfg_interrupt_assert_n ( ~cfg_interrupt_assert ), + .cfg_interrupt_di ( cfg_interrupt_di ), + .cfg_interrupt_n ( ~cfg_interrupt ), + .cfg_interrupt_stat_n ( ~cfg_interrupt_stat ), + .cfg_bus_number ( cfg_bus_number ), + .cfg_device_number ( cfg_device_number ), + .cfg_function_number ( cfg_function_number ), + .cfg_ds_bus_number ( cfg_ds_bus_number ), + .cfg_ds_device_number ( cfg_ds_device_number ), + .cfg_ds_function_number ( cfg_ds_function_number ), + .cfg_pm_send_pme_to_n ( 1'b1 ), + .cfg_pm_wake_n ( ~cfg_pm_wake ), + .cfg_pm_halt_aspm_l0s_n ( ~cfg_pm_halt_aspm_l0s ), + .cfg_pm_halt_aspm_l1_n ( ~cfg_pm_halt_aspm_l1 ), + .cfg_pm_force_state_en_n ( ~cfg_pm_force_state_en), + .cfg_pm_force_state ( cfg_pm_force_state ), + .cfg_force_mps ( 3'b0 ), + .cfg_force_common_clock_off ( 1'b0 ), + .cfg_force_extended_sync_on ( 1'b0 ), + .cfg_port_number ( 8'b0 ), + .cfg_mgmt_rd_en_n ( ~cfg_mgmt_rd_en ), + .cfg_trn_pending ( cfg_trn_pending ), + .cfg_mgmt_wr_en_n ( ~cfg_mgmt_wr_en ), + .cfg_mgmt_wr_readonly_n ( ~cfg_mgmt_wr_readonly ), + .cfg_mgmt_wr_rw1c_as_rw_n ( ~cfg_mgmt_wr_rw1c_as_rw ), + + .pl_initial_link_width ( pl_initial_link_width ), + .pl_lane_reversal_mode ( pl_lane_reversal_mode ), + .pl_link_gen2_cap ( pl_link_gen2_cap ), + .pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ), + .pl_link_upcfg_cap ( pl_link_upcfg_cap ), + .pl_ltssm_state ( pl_ltssm_state_int ), + .pl_phy_lnk_up ( pl_phy_lnk_up_wire ), + .pl_received_hot_rst ( pl_received_hot_rst_wire ), + .pl_rx_pm_state ( pl_rx_pm_state ), + .pl_sel_lnk_rate ( pl_sel_lnk_rate ), + .pl_sel_lnk_width ( pl_sel_lnk_width ), + .pl_tx_pm_state ( pl_tx_pm_state ), + .pl_directed_link_auton ( pl_directed_link_auton ), + .pl_directed_link_change ( pl_directed_link_change ), + .pl_directed_link_speed ( pl_directed_link_speed ), + .pl_directed_link_width ( pl_directed_link_width ), + .pl_downstream_deemph_source ( pl_downstream_deemph_source ), + .pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ), + .pl_transmit_hot_rst ( pl_transmit_hot_rst ), + .pl_directed_ltssm_new_vld ( 1'b0 ), + .pl_directed_ltssm_new ( 6'b0 ), + .pl_directed_ltssm_stall ( 1'b0 ), + .pl_directed_change_done ( pl_directed_change_done ), + + .phy_rdy_n ( phy_rdy_n ), + .dbg_sclr_a ( ), + .dbg_sclr_b ( ), + .dbg_sclr_c ( ), + .dbg_sclr_d ( ), + .dbg_sclr_e ( ), + .dbg_sclr_f ( ), + .dbg_sclr_g ( ), + .dbg_sclr_h ( ), + .dbg_sclr_i ( ), + .dbg_sclr_j ( ), + .dbg_sclr_k ( ), + + .dbg_vec_a ( ), + .dbg_vec_b ( ), + .dbg_vec_c ( ), + .pl_dbg_vec ( ), + .trn_rdllp_data ( ), + .trn_rdllp_src_rdy ( ), + .dbg_mode ( 2'b0 ), + .dbg_sub_mode ( 1'b0 ), + .pl_dbg_mode ( 3'b0 ), + + .drp_clk ( pcie_drp_clk ), + .drp_do ( pcie_drp_do ), + .drp_rdy ( pcie_drp_rdy ), + .drp_addr ( pcie_drp_addr ), + .drp_en ( pcie_drp_en ), + .drp_di ( pcie_drp_di ), + .drp_we ( pcie_drp_we ), + + // Pipe Interface + + .pipe_clk ( pipe_clk ), + .user_clk ( user_clk ), + .user_clk2 ( user_clk2 ), + .pipe_rx0_polarity_gt ( pipe_rx0_polarity_gt ), + .pipe_rx1_polarity_gt ( pipe_rx1_polarity_gt ), + .pipe_rx2_polarity_gt ( pipe_rx2_polarity_gt ), + .pipe_rx3_polarity_gt ( pipe_rx3_polarity_gt ), + .pipe_rx4_polarity_gt ( pipe_rx4_polarity_gt ), + .pipe_rx5_polarity_gt ( pipe_rx5_polarity_gt ), + .pipe_rx6_polarity_gt ( pipe_rx6_polarity_gt ), + .pipe_rx7_polarity_gt ( pipe_rx7_polarity_gt ), + .pipe_tx_deemph_gt ( pipe_tx_deemph_gt ), + .pipe_tx_margin_gt ( pipe_tx_margin_gt ), + .pipe_tx_rate_gt ( pipe_tx_rate_gt ), + .pipe_tx_rcvr_det_gt ( pipe_tx_rcvr_det_gt ), + .pipe_tx0_char_is_k_gt ( pipe_tx0_char_is_k_gt ), + .pipe_tx0_compliance_gt ( pipe_tx0_compliance_gt ), + .pipe_tx0_data_gt ( pipe_tx0_data_gt ), + .pipe_tx0_elec_idle_gt ( pipe_tx0_elec_idle_gt ), + .pipe_tx0_powerdown_gt ( pipe_tx0_powerdown_gt ), + .pipe_tx1_char_is_k_gt ( pipe_tx1_char_is_k_gt ), + .pipe_tx1_compliance_gt ( pipe_tx1_compliance_gt ), + .pipe_tx1_data_gt ( pipe_tx1_data_gt ), + .pipe_tx1_elec_idle_gt ( pipe_tx1_elec_idle_gt ), + .pipe_tx1_powerdown_gt ( pipe_tx1_powerdown_gt ), + .pipe_tx2_char_is_k_gt ( pipe_tx2_char_is_k_gt ), + .pipe_tx2_compliance_gt ( pipe_tx2_compliance_gt ), + .pipe_tx2_data_gt ( pipe_tx2_data_gt ), + .pipe_tx2_elec_idle_gt ( pipe_tx2_elec_idle_gt ), + .pipe_tx2_powerdown_gt ( pipe_tx2_powerdown_gt ), + .pipe_tx3_char_is_k_gt ( pipe_tx3_char_is_k_gt ), + .pipe_tx3_compliance_gt ( pipe_tx3_compliance_gt ), + .pipe_tx3_data_gt ( pipe_tx3_data_gt ), + .pipe_tx3_elec_idle_gt ( pipe_tx3_elec_idle_gt ), + .pipe_tx3_powerdown_gt ( pipe_tx3_powerdown_gt ), + .pipe_tx4_char_is_k_gt ( pipe_tx4_char_is_k_gt ), + .pipe_tx4_compliance_gt ( pipe_tx4_compliance_gt ), + .pipe_tx4_data_gt ( pipe_tx4_data_gt ), + .pipe_tx4_elec_idle_gt ( pipe_tx4_elec_idle_gt ), + .pipe_tx4_powerdown_gt ( pipe_tx4_powerdown_gt ), + .pipe_tx5_char_is_k_gt ( pipe_tx5_char_is_k_gt ), + .pipe_tx5_compliance_gt ( pipe_tx5_compliance_gt ), + .pipe_tx5_data_gt ( pipe_tx5_data_gt ), + .pipe_tx5_elec_idle_gt ( pipe_tx5_elec_idle_gt ), + .pipe_tx5_powerdown_gt ( pipe_tx5_powerdown_gt ), + .pipe_tx6_char_is_k_gt ( pipe_tx6_char_is_k_gt ), + .pipe_tx6_compliance_gt ( pipe_tx6_compliance_gt ), + .pipe_tx6_data_gt ( pipe_tx6_data_gt ), + .pipe_tx6_elec_idle_gt ( pipe_tx6_elec_idle_gt ), + .pipe_tx6_powerdown_gt ( pipe_tx6_powerdown_gt ), + .pipe_tx7_char_is_k_gt ( pipe_tx7_char_is_k_gt ), + .pipe_tx7_compliance_gt ( pipe_tx7_compliance_gt ), + .pipe_tx7_data_gt ( pipe_tx7_data_gt ), + .pipe_tx7_elec_idle_gt ( pipe_tx7_elec_idle_gt ), + .pipe_tx7_powerdown_gt ( pipe_tx7_powerdown_gt ), + + .pipe_rx0_chanisaligned_gt ( pipe_rx0_chanisaligned_gt ), + .pipe_rx0_char_is_k_gt ( pipe_rx0_char_is_k_gt ), + .pipe_rx0_data_gt ( pipe_rx0_data_gt ), + .pipe_rx0_elec_idle_gt ( pipe_rx0_elec_idle_gt ), + .pipe_rx0_phy_status_gt ( pipe_rx0_phy_status_gt ), + .pipe_rx0_status_gt ( pipe_rx0_status_gt ), + .pipe_rx0_valid_gt ( pipe_rx0_valid_gt ), + .pipe_rx1_chanisaligned_gt ( pipe_rx1_chanisaligned_gt ), + .pipe_rx1_char_is_k_gt ( pipe_rx1_char_is_k_gt ), + .pipe_rx1_data_gt ( pipe_rx1_data_gt ), + .pipe_rx1_elec_idle_gt ( pipe_rx1_elec_idle_gt ), + .pipe_rx1_phy_status_gt ( pipe_rx1_phy_status_gt ), + .pipe_rx1_status_gt ( pipe_rx1_status_gt ), + .pipe_rx1_valid_gt ( pipe_rx1_valid_gt ), + .pipe_rx2_chanisaligned_gt ( pipe_rx2_chanisaligned_gt ), + .pipe_rx2_char_is_k_gt ( pipe_rx2_char_is_k_gt ), + .pipe_rx2_data_gt ( pipe_rx2_data_gt ), + .pipe_rx2_elec_idle_gt ( pipe_rx2_elec_idle_gt ), + .pipe_rx2_phy_status_gt ( pipe_rx2_phy_status_gt ), + .pipe_rx2_status_gt ( pipe_rx2_status_gt ), + .pipe_rx2_valid_gt ( pipe_rx2_valid_gt ), + .pipe_rx3_chanisaligned_gt ( pipe_rx3_chanisaligned_gt ), + .pipe_rx3_char_is_k_gt ( pipe_rx3_char_is_k_gt ), + .pipe_rx3_data_gt ( pipe_rx3_data_gt ), + .pipe_rx3_elec_idle_gt ( pipe_rx3_elec_idle_gt ), + .pipe_rx3_phy_status_gt ( pipe_rx3_phy_status_gt ), + .pipe_rx3_status_gt ( pipe_rx3_status_gt ), + .pipe_rx3_valid_gt ( pipe_rx3_valid_gt ), + .pipe_rx4_chanisaligned_gt ( pipe_rx4_chanisaligned_gt ), + .pipe_rx4_char_is_k_gt ( pipe_rx4_char_is_k_gt ), + .pipe_rx4_data_gt ( pipe_rx4_data_gt ), + .pipe_rx4_elec_idle_gt ( pipe_rx4_elec_idle_gt ), + .pipe_rx4_phy_status_gt ( pipe_rx4_phy_status_gt ), + .pipe_rx4_status_gt ( pipe_rx4_status_gt ), + .pipe_rx4_valid_gt ( pipe_rx4_valid_gt ), + .pipe_rx5_chanisaligned_gt ( pipe_rx5_chanisaligned_gt ), + .pipe_rx5_char_is_k_gt ( pipe_rx5_char_is_k_gt ), + .pipe_rx5_data_gt ( pipe_rx5_data_gt ), + .pipe_rx5_elec_idle_gt ( pipe_rx5_elec_idle_gt ), + .pipe_rx5_phy_status_gt ( pipe_rx5_phy_status_gt ), + .pipe_rx5_status_gt ( pipe_rx5_status_gt ), + .pipe_rx5_valid_gt ( pipe_rx5_valid_gt ), + .pipe_rx6_chanisaligned_gt ( pipe_rx6_chanisaligned_gt ), + .pipe_rx6_char_is_k_gt ( pipe_rx6_char_is_k_gt ), + .pipe_rx6_data_gt ( pipe_rx6_data_gt ), + .pipe_rx6_elec_idle_gt ( pipe_rx6_elec_idle_gt ), + .pipe_rx6_phy_status_gt ( pipe_rx6_phy_status_gt ), + .pipe_rx6_status_gt ( pipe_rx6_status_gt ), + .pipe_rx6_valid_gt ( pipe_rx6_valid_gt ), + .pipe_rx7_chanisaligned_gt ( pipe_rx7_chanisaligned_gt ), + .pipe_rx7_char_is_k_gt ( pipe_rx7_char_is_k_gt ), + .pipe_rx7_data_gt ( pipe_rx7_data_gt ), + .pipe_rx7_elec_idle_gt ( pipe_rx7_elec_idle_gt ), + .pipe_rx7_phy_status_gt ( pipe_rx7_phy_status_gt ), + .pipe_rx7_status_gt ( pipe_rx7_status_gt ), + .pipe_rx7_valid_gt ( pipe_rx7_valid_gt ) + + ); + assign common_commands_out = 12'b0; + assign pipe_tx_0_sigs = 25'b0; + assign pipe_tx_1_sigs = 25'b0; + assign pipe_tx_2_sigs = 25'b0; + assign pipe_tx_3_sigs = 25'b0; + assign pipe_tx_4_sigs = 25'b0; + assign pipe_tx_5_sigs = 25'b0; + assign pipe_tx_6_sigs = 25'b0; + assign pipe_tx_7_sigs = 25'b0; + + + //------------------------------------------------------------------------------------------------------------------// + // **** V7/K7/A7 GTX Wrapper **** // + // The 7-Series GTX Wrapper includes the following: // + // 1) Virtex-7 GTX // + // 2) Kintex-7 GTX // + // 3) Artix-7 GTP // + //------------------------------------------------------------------------------------------------------------------// +pcie_7x_0_gt_top #( + .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), + .REF_CLK_FREQ ( REF_CLK_FREQ ), + .USER_CLK_FREQ ( USER_CLK_FREQ ), + .USER_CLK2_DIV2 ( USER_CLK2_DIV2 ), + + // synthesis translate_off + .PL_FAST_TRAIN ( ENABLE_FAST_SIM_TRAINING ), + // synthesis translate_on + + .PCIE_EXT_CLK ( PCIE_EXT_CLK ), + .PCIE_USE_MODE ( PCIE_USE_MODE ), + .PCIE_GT_DEVICE ( PCIE_GT_DEVICE ), + .PCIE_PLL_SEL ( PCIE_PLL_SEL ), + .PCIE_ASYNC_EN ( PCIE_ASYNC_EN ), + .PCIE_TXBUF_EN ( PCIE_TXBUF_EN ), + .PCIE_EXT_GT_COMMON ( PCIE_EXT_GT_COMMON ), + .EXT_CH_GT_DRP ( EXT_CH_GT_DRP ), + .TX_MARGIN_FULL_0 ( TX_MARGIN_FULL_0 ), + .TX_MARGIN_FULL_1 ( TX_MARGIN_FULL_1 ), + .TX_MARGIN_FULL_2 ( TX_MARGIN_FULL_2 ), + .TX_MARGIN_FULL_3 ( TX_MARGIN_FULL_3 ), + .TX_MARGIN_FULL_4 ( TX_MARGIN_FULL_4 ), + .TX_MARGIN_LOW_0 ( TX_MARGIN_LOW_0 ), + .TX_MARGIN_LOW_1 ( TX_MARGIN_LOW_1 ), + .TX_MARGIN_LOW_2 ( TX_MARGIN_LOW_2 ), + .TX_MARGIN_LOW_3 ( TX_MARGIN_LOW_3 ), + .TX_MARGIN_LOW_4 ( TX_MARGIN_LOW_4 ), + .PCIE_CHAN_BOND ( PCIE_CHAN_BOND ) + + ) gt_top_i ( + // pl ltssm + .pl_ltssm_state ( pl_ltssm_state_int ), + + // Pipe Common Signals + .pipe_tx_rcvr_det ( pipe_tx_rcvr_det_gt ), + .pipe_tx_reset ( 1'b0 ), + .pipe_tx_rate ( pipe_tx_rate_gt ), + .pipe_tx_deemph ( pipe_tx_deemph_gt ), + .pipe_tx_margin ( pipe_tx_margin_gt ), + .pipe_tx_swing ( 1'b0 ), + + // Pipe Per-Lane Signals - Lane 0 + .pipe_rx0_char_is_k ( pipe_rx0_char_is_k_gt), + .pipe_rx0_data ( pipe_rx0_data_gt ), + .pipe_rx0_valid ( pipe_rx0_valid_gt ), + .pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned_gt ), + .pipe_rx0_status ( pipe_rx0_status_gt ), + .pipe_rx0_phy_status ( pipe_rx0_phy_status_gt ), + .pipe_rx0_elec_idle ( pipe_rx0_elec_idle_gt ), + .pipe_rx0_polarity ( pipe_rx0_polarity_gt ), + .pipe_tx0_compliance ( pipe_tx0_compliance_gt ), + .pipe_tx0_char_is_k ( pipe_tx0_char_is_k_gt ), + .pipe_tx0_data ( pipe_tx0_data_gt ), + .pipe_tx0_elec_idle ( pipe_tx0_elec_idle_gt ), + .pipe_tx0_powerdown ( pipe_tx0_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 1 + + .pipe_rx1_char_is_k ( pipe_rx1_char_is_k_gt), + .pipe_rx1_data ( pipe_rx1_data_gt ), + .pipe_rx1_valid ( pipe_rx1_valid_gt ), + .pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned_gt ), + .pipe_rx1_status ( pipe_rx1_status_gt ), + .pipe_rx1_phy_status ( pipe_rx1_phy_status_gt ), + .pipe_rx1_elec_idle ( pipe_rx1_elec_idle_gt ), + .pipe_rx1_polarity ( pipe_rx1_polarity_gt ), + .pipe_tx1_compliance ( pipe_tx1_compliance_gt ), + .pipe_tx1_char_is_k ( pipe_tx1_char_is_k_gt ), + .pipe_tx1_data ( pipe_tx1_data_gt ), + .pipe_tx1_elec_idle ( pipe_tx1_elec_idle_gt ), + .pipe_tx1_powerdown ( pipe_tx1_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 2 + + .pipe_rx2_char_is_k ( pipe_rx2_char_is_k_gt), + .pipe_rx2_data ( pipe_rx2_data_gt ), + .pipe_rx2_valid ( pipe_rx2_valid_gt ), + .pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned_gt ), + .pipe_rx2_status ( pipe_rx2_status_gt ), + .pipe_rx2_phy_status ( pipe_rx2_phy_status_gt ), + .pipe_rx2_elec_idle ( pipe_rx2_elec_idle_gt ), + .pipe_rx2_polarity ( pipe_rx2_polarity_gt ), + .pipe_tx2_compliance ( pipe_tx2_compliance_gt ), + .pipe_tx2_char_is_k ( pipe_tx2_char_is_k_gt ), + .pipe_tx2_data ( pipe_tx2_data_gt ), + .pipe_tx2_elec_idle ( pipe_tx2_elec_idle_gt ), + .pipe_tx2_powerdown ( pipe_tx2_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 3 + + .pipe_rx3_char_is_k ( pipe_rx3_char_is_k_gt), + .pipe_rx3_data ( pipe_rx3_data_gt ), + .pipe_rx3_valid ( pipe_rx3_valid_gt ), + .pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned_gt ), + .pipe_rx3_status ( pipe_rx3_status_gt ), + .pipe_rx3_phy_status ( pipe_rx3_phy_status_gt ), + .pipe_rx3_elec_idle ( pipe_rx3_elec_idle_gt ), + .pipe_rx3_polarity ( pipe_rx3_polarity_gt ), + .pipe_tx3_compliance ( pipe_tx3_compliance_gt ), + .pipe_tx3_char_is_k ( pipe_tx3_char_is_k_gt ), + .pipe_tx3_data ( pipe_tx3_data_gt ), + .pipe_tx3_elec_idle ( pipe_tx3_elec_idle_gt ), + .pipe_tx3_powerdown ( pipe_tx3_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 4 + + .pipe_rx4_char_is_k ( pipe_rx4_char_is_k_gt), + .pipe_rx4_data ( pipe_rx4_data_gt ), + .pipe_rx4_valid ( pipe_rx4_valid_gt ), + .pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned_gt ), + .pipe_rx4_status ( pipe_rx4_status_gt ), + .pipe_rx4_phy_status ( pipe_rx4_phy_status_gt ), + .pipe_rx4_elec_idle ( pipe_rx4_elec_idle_gt ), + .pipe_rx4_polarity ( pipe_rx4_polarity_gt ), + .pipe_tx4_compliance ( pipe_tx4_compliance_gt ), + .pipe_tx4_char_is_k ( pipe_tx4_char_is_k_gt ), + .pipe_tx4_data ( pipe_tx4_data_gt ), + .pipe_tx4_elec_idle ( pipe_tx4_elec_idle_gt ), + .pipe_tx4_powerdown ( pipe_tx4_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 5 + + .pipe_rx5_char_is_k ( pipe_rx5_char_is_k_gt), + .pipe_rx5_data ( pipe_rx5_data_gt ), + .pipe_rx5_valid ( pipe_rx5_valid_gt ), + .pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned_gt ), + .pipe_rx5_status ( pipe_rx5_status_gt ), + .pipe_rx5_phy_status ( pipe_rx5_phy_status_gt ), + .pipe_rx5_elec_idle ( pipe_rx5_elec_idle_gt ), + .pipe_rx5_polarity ( pipe_rx5_polarity_gt ), + .pipe_tx5_compliance ( pipe_tx5_compliance_gt ), + .pipe_tx5_char_is_k ( pipe_tx5_char_is_k_gt ), + .pipe_tx5_data ( pipe_tx5_data_gt ), + .pipe_tx5_elec_idle ( pipe_tx5_elec_idle_gt ), + .pipe_tx5_powerdown ( pipe_tx5_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 6 + + .pipe_rx6_char_is_k ( pipe_rx6_char_is_k_gt), + .pipe_rx6_data ( pipe_rx6_data_gt ), + .pipe_rx6_valid ( pipe_rx6_valid_gt ), + .pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned_gt ), + .pipe_rx6_status ( pipe_rx6_status_gt ), + .pipe_rx6_phy_status ( pipe_rx6_phy_status_gt ), + .pipe_rx6_elec_idle ( pipe_rx6_elec_idle_gt ), + .pipe_rx6_polarity ( pipe_rx6_polarity_gt ), + .pipe_tx6_compliance ( pipe_tx6_compliance_gt ), + .pipe_tx6_char_is_k ( pipe_tx6_char_is_k_gt ), + .pipe_tx6_data ( pipe_tx6_data_gt ), + .pipe_tx6_elec_idle ( pipe_tx6_elec_idle_gt ), + .pipe_tx6_powerdown ( pipe_tx6_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 7 + + .pipe_rx7_char_is_k ( pipe_rx7_char_is_k_gt), + .pipe_rx7_data ( pipe_rx7_data_gt ), + .pipe_rx7_valid ( pipe_rx7_valid_gt ), + .pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned_gt ), + .pipe_rx7_status ( pipe_rx7_status_gt ), + .pipe_rx7_phy_status ( pipe_rx7_phy_status_gt ), + .pipe_rx7_elec_idle ( pipe_rx7_elec_idle_gt ), + .pipe_rx7_polarity ( pipe_rx7_polarity_gt ), + .pipe_tx7_compliance ( pipe_tx7_compliance_gt ), + .pipe_tx7_char_is_k ( pipe_tx7_char_is_k_gt ), + .pipe_tx7_data ( pipe_tx7_data_gt ), + .pipe_tx7_elec_idle ( pipe_tx7_elec_idle_gt ), + .pipe_tx7_powerdown ( pipe_tx7_powerdown_gt ), + + // PCI Express Signals + .pci_exp_txn ( pci_exp_txn ), + .pci_exp_txp ( pci_exp_txp ), + .pci_exp_rxn ( pci_exp_rxn ), + .pci_exp_rxp ( pci_exp_rxp ), + + // Non PIPE Signals + .sys_clk ( sys_clk ), + .sys_rst_n ( sys_rst_n ), + .PIPE_MMCM_RST_N ( pipe_mmcm_rst_n ), // Async | Async + .pipe_clk ( pipe_clk ), + + .user_clk ( user_clk ), + .user_clk2 ( user_clk2 ), + .phy_rdy_n ( phy_rdy_n ), + + // ---------- Shared Logic Internal------------------ + .INT_PCLK_OUT_SLAVE ( int_pclk_out_slave ), + .INT_RXUSRCLK_OUT ( int_pipe_rxusrclk_out ), + .INT_RXOUTCLK_OUT ( int_rxoutclk_out ), + .INT_DCLK_OUT ( int_dclk_out ), + .INT_USERCLK1_OUT ( int_userclk1_out ), + .INT_USERCLK2_OUT ( int_userclk2_out), + .INT_OOBCLK_OUT ( int_oobclk_out), + .INT_MMCM_LOCK_OUT ( int_mmcm_lock_out ), + .INT_QPLLLOCK_OUT ( int_qplllock_out ), + .INT_QPLLOUTCLK_OUT ( int_qplloutclk_out ), + .INT_QPLLOUTREFCLK_OUT ( int_qplloutrefclk_out ), + .INT_PCLK_SEL_SLAVE ( int_pclk_sel_slave ), + + // ---------- Shared Logic External------------------ + //External Clock Ports + .PIPE_PCLK_IN ( pipe_pclk_in ), + .PIPE_RXUSRCLK_IN ( pipe_rxusrclk_in ), + .PIPE_RXOUTCLK_IN ( pipe_rxoutclk_in ), + .PIPE_DCLK_IN ( pipe_dclk_in ), + .PIPE_USERCLK1_IN ( pipe_userclk1_in ), + .PIPE_USERCLK2_IN ( pipe_userclk2_in ), + .PIPE_OOBCLK_IN ( pipe_oobclk_in ), + .PIPE_MMCM_LOCK_IN ( pipe_mmcm_lock_in ), + + .PIPE_TXOUTCLK_OUT ( pipe_txoutclk_out ), + .PIPE_RXOUTCLK_OUT ( pipe_rxoutclk_out ), + .PIPE_PCLK_SEL_OUT ( pipe_pclk_sel_out ), + .PIPE_GEN3_OUT ( pipe_gen3_out ), + + //External GT COMMON Ports + + .qpll_drp_crscode ( qpll_drp_crscode ), + .qpll_drp_fsm ( qpll_drp_fsm ), + .qpll_drp_done ( qpll_drp_done ), + .qpll_drp_reset ( qpll_drp_reset ), + .qpll_qplllock ( qpll_qplllock ), + .qpll_qplloutclk ( qpll_qplloutclk ), + .qpll_qplloutrefclk ( qpll_qplloutrefclk ), + .qpll_qplld ( qpll_qplld ), + .qpll_qpllreset ( qpll_qpllreset ), + .qpll_drp_clk ( qpll_drp_clk ), + .qpll_drp_rst_n ( qpll_drp_rst_n ), + .qpll_drp_ovrd ( qpll_drp_ovrd ), + .qpll_drp_gen3 ( qpll_drp_gen3), + .qpll_drp_start ( qpll_drp_start ), + + //TRANSCEIVER DEBUG EOU + .ext_ch_gt_drpclk ( ext_ch_gt_drpclk ), + .ext_ch_gt_drpaddr ( ext_ch_gt_drpaddr ), + .ext_ch_gt_drpen ( ext_ch_gt_drpen ), + .ext_ch_gt_drpdi ( ext_ch_gt_drpdi ), + .ext_ch_gt_drpwe ( ext_ch_gt_drpwe ), + .ext_ch_gt_drpdo ( ext_ch_gt_drpdo ), + .ext_ch_gt_drprdy ( ext_ch_gt_drprdy ), + +//---------- PRBS/Loopback Ports ----------------------- + .PIPE_TXPRBSSEL ( pipe_txprbssel ), + .PIPE_RXPRBSSEL ( pipe_rxprbssel ), + .PIPE_TXPRBSFORCEERR ( pipe_txprbsforceerr ), + .PIPE_RXPRBSCNTRESET ( pipe_rxprbscntreset ), + .PIPE_LOOPBACK ( pipe_loopback ), + + .PIPE_RXPRBSERR ( pipe_rxprbserr ), + .PIPE_TXINHIBIT ( pipe_txinhibit ), + +//---------- Transceiver Debug FSM Ports --------------------------------- + .PIPE_RST_FSM ( pipe_rst_fsm ), + .PIPE_QRST_FSM ( pipe_qrst_fsm ), + .PIPE_RATE_FSM ( pipe_rate_fsm ), + .PIPE_SYNC_FSM_TX ( pipe_sync_fsm_tx ), + .PIPE_SYNC_FSM_RX ( pipe_sync_fsm_rx ), + .PIPE_DRP_FSM ( pipe_drp_fsm ), + + .PIPE_RST_IDLE ( pipe_rst_idle ), + .PIPE_QRST_IDLE ( pipe_qrst_idle ), + .PIPE_RATE_IDLE ( pipe_rate_idle ), + .PIPE_EYESCANDATAERROR ( pipe_eyescandataerror ), + .PIPE_RXSTATUS ( pipe_rxstatus ), + .PIPE_DMONITOROUT ( pipe_dmonitorout ), + + .PIPE_CPLL_LOCK ( pipe_cpll_lock ), + .PIPE_QPLL_LOCK ( pipe_qpll_lock ), + .PIPE_RXPMARESETDONE ( pipe_rxpmaresetdone ), + .PIPE_RXBUFSTATUS ( pipe_rxbufstatus ), + .PIPE_TXPHALIGNDONE ( pipe_txphaligndone ), + .PIPE_TXPHINITDONE ( pipe_txphinitdone ), + .PIPE_TXDLYSRESETDONE ( pipe_txdlysresetdone ), + .PIPE_RXPHALIGNDONE ( pipe_rxphaligndone ), + .PIPE_RXDLYSRESETDONE ( pipe_rxdlysresetdone ), + .PIPE_RXSYNCDONE ( pipe_rxsyncdone ), + .PIPE_RXDISPERR ( pipe_rxdisperr ), + .PIPE_RXNOTINTABLE ( pipe_rxnotintable ), + .PIPE_RXCOMMADET ( pipe_rxcommadet ), + //---------- JTAG Ports -------------------------------- + .PIPE_JTAG_RDY (gt_ch_drp_rdy ), + + + //---------- Debug Ports ------------------------------- + .PIPE_DEBUG_0 ( pipe_debug_0 ), + .PIPE_DEBUG_1 ( pipe_debug_1 ), + .PIPE_DEBUG_2 ( pipe_debug_2 ), + .PIPE_DEBUG_3 ( pipe_debug_3 ), + .PIPE_DEBUG_4 ( pipe_debug_4 ), + .PIPE_DEBUG_5 ( pipe_debug_5 ), + .PIPE_DEBUG_6 ( pipe_debug_6 ), + .PIPE_DEBUG_7 ( pipe_debug_7 ), + .PIPE_DEBUG_8 ( pipe_debug_8 ), + .PIPE_DEBUG_9 ( pipe_debug_9 ), + .PIPE_DEBUG ( pipe_debug ) + ); + + assign common_commands_out = 12'b0; + assign pipe_tx_0_sigs = 25'b0; + assign pipe_tx_1_sigs = 25'b0; + assign pipe_tx_2_sigs = 25'b0; + assign pipe_tx_3_sigs = 25'b0; + assign pipe_tx_4_sigs = 25'b0; + assign pipe_tx_5_sigs = 25'b0; + assign pipe_tx_6_sigs = 25'b0; + assign pipe_tx_7_sigs = 25'b0; + //------------------------------------------------------------------------------------------------------------------// + + // Tie-Off Unused Tandem Outputs + assign icap_o = 32'b0; + assign startup_cfgclk = 1'b0; + assign startup_cfgmclk = 1'b0; + assign startup_eos = 1'b0; + assign startup_preq = 1'b0; + +//////////////////////////////////////////////STORE_LTSSM////////////////////////////////////////////////// + + (* dont_touch = "true" *) wire store_ltssm; + reg [5:0] ltssm_reg0 = 6'b0; + reg [5:0] ltssm_reg1 = 6'b0; + reg [5:0] ltssm_reg2 = 6'b0; + + always@ (posedge pipe_clk) + begin + ltssm_reg0 <= pl_ltssm_state; + ltssm_reg1 <= ltssm_reg0; + ltssm_reg2 <= ltssm_reg1; + end + + assign store_ltssm = (ltssm_reg2 != pl_ltssm_state) ? 1'b1 : 1'b0; + +/////////////////////////////////////////////////////////////////////////////////////////////////////////// +//enable_jtag_dbg = FALSE + + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_common.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_common.v new file mode 100644 index 0000000..e8f61e7 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_common.v @@ -0,0 +1,166 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_gt_common.v +// Version : 3.3 +`timescale 1ns / 1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_gt_common #( + +parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode +parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device +parameter PCIE_USE_MODE = "2.1", // PCIe use mode +parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only +parameter PCIE_REFCLK_FREQ = 0 // PCIe reference clock frequency +) + +( +input CPLLPDREFCLK, +input PIPE_CLK, +input QPLL_QPLLPD, +input QPLL_QPLLRESET, +input QPLL_DRP_CLK, +input QPLL_DRP_RST_N, +input QPLL_DRP_OVRD, +input QPLL_DRP_GEN3, +input QPLL_DRP_START, +output [5:0] QPLL_DRP_CRSCODE, +output [8:0] QPLL_DRP_FSM, +output QPLL_DRP_DONE, +output QPLL_DRP_RESET, +output QPLL_QPLLLOCK, +output QPLL_QPLLOUTCLK, +output QPLL_QPLLOUTREFCLK +); + + //---------- QPLL DRP Module Output -------------------- + +wire [7:0] qpll_drp_addr; +wire qpll_drp_en; +wire [15:0] qpll_drp_di; +wire qpll_drp_we; + + //---------- QPLL Wrapper Output ----------------------- + +wire [15:0] qpll_drp_do; +wire qpll_drp_rdy; + + //---------- QPLL Resets ----------------------- + + + //---------- QPLL DRP Module --------------------------------------- + +pcie_7x_0_qpll_drp # + ( + + .PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device + .PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode + .PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only + .PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency + + ) + qpll_drp_i + ( + + //---------- Input ------------------------- + .DRP_CLK (QPLL_DRP_CLK), + .DRP_RST_N (!QPLL_DRP_RST_N), + .DRP_OVRD (QPLL_DRP_OVRD), + .DRP_GEN3 (&QPLL_DRP_GEN3), + .DRP_QPLLLOCK (QPLL_QPLLLOCK), + .DRP_START (QPLL_DRP_START), + .DRP_DO (qpll_drp_do), + .DRP_RDY (qpll_drp_rdy), + + //---------- Output ------------------------ + .DRP_ADDR (qpll_drp_addr), + .DRP_EN (qpll_drp_en), + .DRP_DI (qpll_drp_di), + .DRP_WE (qpll_drp_we), + .DRP_DONE (QPLL_DRP_DONE), + .DRP_QPLLRESET (QPLL_DRP_RESET), + .DRP_CRSCODE (QPLL_DRP_CRSCODE), + .DRP_FSM (QPLL_DRP_FSM) + ); + + + //---------- QPLL Wrapper ------------------------------------------ +pcie_7x_0_qpll_wrapper # + ( + .PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode + .PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device + .PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode + .PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only + .PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency + ) + qpll_wrapper_i + ( + //---------- QPLL Clock Ports -------------- + .QPLL_CPLLPDREFCLK (CPLLPDREFCLK), + .QPLL_GTGREFCLK (PIPE_CLK), + .QPLL_QPLLLOCKDETCLK (1'd0), + .QPLL_QPLLOUTCLK (QPLL_QPLLOUTCLK), + .QPLL_QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), + .QPLL_QPLLLOCK (QPLL_QPLLLOCK), + //---------- QPLL Reset Ports -------------- + .QPLL_QPLLPD (QPLL_QPLLPD), + .QPLL_QPLLRESET (QPLL_QPLLRESET), + //---------- QPLL DRP Ports ---------------- + .QPLL_DRPCLK (QPLL_DRP_CLK), + .QPLL_DRPADDR (qpll_drp_addr), + .QPLL_DRPEN (qpll_drp_en), + .QPLL_DRPDI (qpll_drp_di), + .QPLL_DRPWE (qpll_drp_we), + .QPLL_DRPDO (qpll_drp_do), + .QPLL_DRPRDY (qpll_drp_rdy) + ); + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_rx_valid_filter_7x.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_rx_valid_filter_7x.v new file mode 100644 index 0000000..7beb2b9 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_rx_valid_filter_7x.v @@ -0,0 +1,285 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_gt_rx_valid_filter_7x.v +// Version : 3.3 +//-- Description: GTX module for 7-series Integrated PCIe Block +//-- +//-- +//-- +//-------------------------------------------------------------------------------- + +`timescale 1ns / 1ns + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_gt_rx_valid_filter_7x #( + + parameter CLK_COR_MIN_LAT = 28, + parameter TCQ = 1 + +) +( + output [1:0] USER_RXCHARISK, + output [15:0] USER_RXDATA, + output USER_RXVALID, + output USER_RXELECIDLE, + output [ 2:0] USER_RX_STATUS, + output USER_RX_PHY_STATUS, + input [1:0] GT_RXCHARISK, + input [15:0] GT_RXDATA, + input GT_RXVALID, + input GT_RXELECIDLE, + input [ 2:0] GT_RX_STATUS, + input GT_RX_PHY_STATUS, + + input PLM_IN_L0, + input PLM_IN_RS, + + input USER_CLK, + input RESET + +); + + + + localparam EIOS_DET_IDL = 5'b00001; + localparam EIOS_DET_NO_STR0 = 5'b00010; + localparam EIOS_DET_STR0 = 5'b00100; + localparam EIOS_DET_STR1 = 5'b01000; + localparam EIOS_DET_DONE = 5'b10000; + + localparam EIOS_COM = 8'hBC; + localparam EIOS_IDL = 8'h7C; + localparam FTSOS_COM = 8'hBC; + localparam FTSOS_FTS = 8'h3C; + + reg [4:0] reg_state_eios_det; + wire [4:0] state_eios_det; + + reg reg_eios_detected; + wire eios_detected; + + reg reg_symbol_after_eios; + wire symbol_after_eios; + + localparam USER_RXVLD_IDL = 4'b0001; + localparam USER_RXVLD_EI = 4'b0010; + localparam USER_RXVLD_EI_DB0 = 4'b0100; + localparam USER_RXVLD_EI_DB1 = 4'b1000; + + + reg [1:0] gt_rxcharisk_q; + reg [15:0] gt_rxdata_q; + reg gt_rxvalid_q; + reg gt_rxelecidle_q; + + reg [ 2:0] gt_rx_status_q; + reg gt_rx_phy_status_q; + reg gt_rx_is_skp0_q; + reg gt_rx_is_skp1_q; + + // EIOS detector + + always @(posedge USER_CLK) begin + + if (RESET) begin + + reg_eios_detected <= #TCQ 1'b0; + reg_state_eios_det <= #TCQ EIOS_DET_IDL; + reg_symbol_after_eios <= #TCQ 1'b0; + gt_rxcharisk_q <= #TCQ 2'b00; + gt_rxdata_q <= #TCQ 16'h0; + gt_rxvalid_q <= #TCQ 1'b0; + gt_rxelecidle_q <= #TCQ 1'b0; + gt_rx_status_q <= #TCQ 3'b000; + gt_rx_phy_status_q <= #TCQ 1'b0; + gt_rx_is_skp0_q <= #TCQ 1'b0; + gt_rx_is_skp1_q <= #TCQ 1'b0; + + end else begin + reg_eios_detected <= #TCQ 1'b0; + reg_symbol_after_eios <= #TCQ 1'b0; + gt_rxcharisk_q <= #TCQ GT_RXCHARISK; + gt_rxelecidle_q <= #TCQ GT_RXELECIDLE; + gt_rxdata_q <= #TCQ GT_RXDATA; + gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS; + + //De-assert rx_valid signal when EIOS is detected on RXDATA + if(((reg_state_eios_det == 5'b10000)) && (PLM_IN_L0) + ) begin + + gt_rxvalid_q <= #TCQ 1'b0; + end + else if (GT_RXELECIDLE && !gt_rxvalid_q) begin + gt_rxvalid_q <= #TCQ 1'b0; + end + else begin + gt_rxvalid_q <= GT_RXVALID; + end + + if (gt_rxvalid_q) begin + gt_rx_status_q <= #TCQ GT_RX_STATUS; + + end + else if (!gt_rxvalid_q && PLM_IN_L0) begin + gt_rx_status_q <= #TCQ 3'b0; + end + else begin + gt_rx_status_q <= #TCQ GT_RX_STATUS; + end + + + + if (GT_RXCHARISK[0] && GT_RXDATA[7:0] == FTSOS_FTS) + gt_rx_is_skp0_q <= #TCQ 1'b1; + else + gt_rx_is_skp0_q <= #TCQ 1'b0; + + if (GT_RXCHARISK[1] && GT_RXDATA[15:8] == FTSOS_FTS) + gt_rx_is_skp1_q <= #TCQ 1'b1; + else + gt_rx_is_skp1_q <= #TCQ 1'b0; + + case ( state_eios_det ) + + EIOS_DET_IDL : begin + + if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) && + (gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin + + reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0; + reg_eios_detected <= #TCQ 1'b1; + // gt_rxvalid_q <= #TCQ 1'b0; + + end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM)) + reg_state_eios_det <= #TCQ EIOS_DET_STR0; + else + reg_state_eios_det <= #TCQ EIOS_DET_IDL; + + end + + EIOS_DET_NO_STR0 : begin + + if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) && + (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) + begin + reg_state_eios_det <= #TCQ EIOS_DET_DONE; + gt_rxvalid_q <= #TCQ 1'b0; + end + else if (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) begin + + reg_state_eios_det <= #TCQ EIOS_DET_DONE; + gt_rxvalid_q <= #TCQ 1'b0; + end + else + reg_state_eios_det <= #TCQ EIOS_DET_IDL; + + end + + EIOS_DET_STR0 : begin + + if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) && + (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin + + reg_state_eios_det <= #TCQ EIOS_DET_STR1; + reg_eios_detected <= #TCQ 1'b1; + gt_rxvalid_q <= #TCQ 1'b0; + reg_symbol_after_eios <= #TCQ 1'b1; + + end else + reg_state_eios_det <= #TCQ EIOS_DET_IDL; + + end + + EIOS_DET_STR1 : begin + + if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL)) + begin + reg_state_eios_det <= #TCQ EIOS_DET_DONE; + gt_rxvalid_q <= #TCQ 1'b0; + end + else + reg_state_eios_det <= #TCQ EIOS_DET_IDL; + + end + + EIOS_DET_DONE : begin + + reg_state_eios_det <= #TCQ EIOS_DET_IDL; + + end + + endcase + + end + + end + assign state_eios_det = reg_state_eios_det; + assign eios_detected = reg_eios_detected; + assign symbol_after_eios = reg_symbol_after_eios; + /*SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE), + .D(gt_rxelecidle_q), + .CLK(USER_CLK), + .CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1)); +*/ +wire rst_l = ~RESET; + + +assign USER_RXVALID = gt_rxvalid_q; +assign USER_RXCHARISK[0] = gt_rxvalid_q ? gt_rxcharisk_q[0] : 1'b0; +assign USER_RXCHARISK[1] = (gt_rxvalid_q && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0; +assign USER_RXDATA[7:0] = gt_rxdata_q[7:0]; +assign USER_RXDATA[15:8] = gt_rxdata_q[15:8]; +assign USER_RX_STATUS = gt_rx_status_q; +assign USER_RX_PHY_STATUS = gt_rx_phy_status_q; +assign USER_RXELECIDLE = gt_rxelecidle_q; + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_top.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_top.v new file mode 100644 index 0000000..a7b0f0a --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_top.v @@ -0,0 +1,1027 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_gt_top.v +// Version : 3.3 +//-- Description: GTX module for 7-series Integrated PCIe Block +//-- +//-- +//-- +//-------------------------------------------------------------------------------- + +`timescale 1ns/1ns + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_gt_top # +( + parameter LINK_CAP_MAX_LINK_WIDTH = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8 + parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz + parameter USER_CLK2_DIV2 = "FALSE", // "FALSE" => user_clk2 = user_clk + // "TRUE" => user_clk2 = user_clk/2, where user_clk = 500 or 250 MHz. + parameter integer USER_CLK_FREQ = 3, // 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz + parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup + parameter PCIE_EXT_CLK = "FALSE", // Use External Clocking + parameter PCIE_USE_MODE = "1.0", // 1.0 = K325T IES, 1.1 = VX485T IES, 3.0 = K325T GES + parameter PCIE_GT_DEVICE = "GTX", // Select the GT to use (GTP for Artix-7, GTX for K7/V7) + parameter PCIE_PLL_SEL = "CPLL", // Select the PLL (CPLL or QPLL) + parameter PCIE_ASYNC_EN = "FALSE", // Asynchronous Clocking Enable + parameter PCIE_TXBUF_EN = "FALSE", // Use the Tansmit Buffer + parameter PCIE_EXT_GT_COMMON = "FALSE", + parameter EXT_CH_GT_DRP = "FALSE", + parameter TX_MARGIN_FULL_0 = 7'b1001111, // 1000 mV + parameter TX_MARGIN_FULL_1 = 7'b1001110, // 950 mV + parameter TX_MARGIN_FULL_2 = 7'b1001101, // 900 mV + parameter TX_MARGIN_FULL_3 = 7'b1001100, // 850 mV + parameter TX_MARGIN_FULL_4 = 7'b1000011, // 400 mV + parameter TX_MARGIN_LOW_0 = 7'b1000101, // 500 mV + parameter TX_MARGIN_LOW_1 = 7'b1000110, // 450 mV + parameter TX_MARGIN_LOW_2 = 7'b1000011, // 400 mV + parameter TX_MARGIN_LOW_3 = 7'b1000010, // 350 mV + parameter TX_MARGIN_LOW_4 = 7'b1000000, + + parameter PCIE_CHAN_BOND = 0, + parameter TCQ = 1 //synthesis warning solved: parameter declaration becomes local +) +( + //-----------------------------------------------------------------------------------------------------------------// + // pl ltssm + input wire [5:0] pl_ltssm_state , + // Pipe Per-Link Signals + input wire pipe_tx_rcvr_det , + input wire pipe_tx_reset , + input wire pipe_tx_rate , + input wire pipe_tx_deemph , + input wire [2:0] pipe_tx_margin , + input wire pipe_tx_swing , + + //-----------------------------------------------------------------------------------------------------------------// + // Pipe Per-Lane Signals // + //-----------------------------------------------------------------------------------------------------------------// + + + // Pipe Per-Lane Signals - Lane 0 + output wire [ 1:0] pipe_rx0_char_is_k , + output wire [15:0] pipe_rx0_data , + output wire pipe_rx0_valid , + output wire pipe_rx0_chanisaligned , + output wire [ 2:0] pipe_rx0_status , + output wire pipe_rx0_phy_status , + output wire pipe_rx0_elec_idle , + input wire pipe_rx0_polarity , + input wire pipe_tx0_compliance , + input wire [ 1:0] pipe_tx0_char_is_k , + input wire [15:0] pipe_tx0_data , + input wire pipe_tx0_elec_idle , + input wire [ 1:0] pipe_tx0_powerdown , + + // Pipe Per-Lane Signals - Lane 1 + output wire [ 1:0] pipe_rx1_char_is_k , + output wire [15:0] pipe_rx1_data , + output wire pipe_rx1_valid , + output wire pipe_rx1_chanisaligned , + output wire [ 2:0] pipe_rx1_status , + output wire pipe_rx1_phy_status , + output wire pipe_rx1_elec_idle , + input wire pipe_rx1_polarity , + input wire pipe_tx1_compliance , + input wire [ 1:0] pipe_tx1_char_is_k , + input wire [15:0] pipe_tx1_data , + input wire pipe_tx1_elec_idle , + input wire [ 1:0] pipe_tx1_powerdown , + + // Pipe Per-Lane Signals - Lane 2 + output wire [ 1:0] pipe_rx2_char_is_k , + output wire [15:0] pipe_rx2_data , + output wire pipe_rx2_valid , + output wire pipe_rx2_chanisaligned , + output wire [ 2:0] pipe_rx2_status , + output wire pipe_rx2_phy_status , + output wire pipe_rx2_elec_idle , + input wire pipe_rx2_polarity , + input wire pipe_tx2_compliance , + input wire [ 1:0] pipe_tx2_char_is_k , + input wire [15:0] pipe_tx2_data , + input wire pipe_tx2_elec_idle , + input wire [ 1:0] pipe_tx2_powerdown , + + // Pipe Per-Lane Signals - Lane 3 + output wire [ 1:0] pipe_rx3_char_is_k , + output wire [15:0] pipe_rx3_data , + output wire pipe_rx3_valid , + output wire pipe_rx3_chanisaligned , + output wire [ 2:0] pipe_rx3_status , + output wire pipe_rx3_phy_status , + output wire pipe_rx3_elec_idle , + input wire pipe_rx3_polarity , + input wire pipe_tx3_compliance , + input wire [ 1:0] pipe_tx3_char_is_k , + input wire [15:0] pipe_tx3_data , + input wire pipe_tx3_elec_idle , + input wire [ 1:0] pipe_tx3_powerdown , + + // Pipe Per-Lane Signals - Lane 4 + output wire [ 1:0] pipe_rx4_char_is_k , + output wire [15:0] pipe_rx4_data , + output wire pipe_rx4_valid , + output wire pipe_rx4_chanisaligned , + output wire [ 2:0] pipe_rx4_status , + output wire pipe_rx4_phy_status , + output wire pipe_rx4_elec_idle , + input wire pipe_rx4_polarity , + input wire pipe_tx4_compliance , + input wire [ 1:0] pipe_tx4_char_is_k , + input wire [15:0] pipe_tx4_data , + input wire pipe_tx4_elec_idle , + input wire [ 1:0] pipe_tx4_powerdown , + + // Pipe Per-Lane Signals - Lane 5 + output wire [ 1:0] pipe_rx5_char_is_k , + output wire [15:0] pipe_rx5_data , + output wire pipe_rx5_valid , + output wire pipe_rx5_chanisaligned , + output wire [ 2:0] pipe_rx5_status , + output wire pipe_rx5_phy_status , + output wire pipe_rx5_elec_idle , + input wire pipe_rx5_polarity , + input wire pipe_tx5_compliance , + input wire [ 1:0] pipe_tx5_char_is_k , + input wire [15:0] pipe_tx5_data , + input wire pipe_tx5_elec_idle , + input wire [ 1:0] pipe_tx5_powerdown , + + // Pipe Per-Lane Signals - Lane 6 + output wire [ 1:0] pipe_rx6_char_is_k , + output wire [15:0] pipe_rx6_data , + output wire pipe_rx6_valid , + output wire pipe_rx6_chanisaligned , + output wire [ 2:0] pipe_rx6_status , + output wire pipe_rx6_phy_status , + output wire pipe_rx6_elec_idle , + input wire pipe_rx6_polarity , + input wire pipe_tx6_compliance , + input wire [ 1:0] pipe_tx6_char_is_k , + input wire [15:0] pipe_tx6_data , + input wire pipe_tx6_elec_idle , + input wire [ 1:0] pipe_tx6_powerdown , + + // Pipe Per-Lane Signals - Lane 7 + output wire [ 1:0] pipe_rx7_char_is_k , + output wire [15:0] pipe_rx7_data , + output wire pipe_rx7_valid , + output wire pipe_rx7_chanisaligned , + output wire [ 2:0] pipe_rx7_status , + output wire pipe_rx7_phy_status , + output wire pipe_rx7_elec_idle , + input wire pipe_rx7_polarity , + input wire pipe_tx7_compliance , + input wire [ 1:0] pipe_tx7_char_is_k , + input wire [15:0] pipe_tx7_data , + input wire pipe_tx7_elec_idle , + input wire [ 1:0] pipe_tx7_powerdown , + + // PCI Express signals + output wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txn , + output wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txp , + input wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxn , + input wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxp , + + // Non PIPE signals + input wire sys_clk , + input wire sys_rst_n , + input wire PIPE_MMCM_RST_N , + output wire pipe_clk , + output wire user_clk , + output wire user_clk2 , + +//----------- Shared Logic Internal-------------------------------------- + + output INT_PCLK_OUT_SLAVE, // PCLK | PCLK + output INT_RXUSRCLK_OUT, // RXUSERCLK + output [(LINK_CAP_MAX_LINK_WIDTH-1):0] INT_RXOUTCLK_OUT, // RX recovered clock + output INT_DCLK_OUT, // DCLK | DCLK + output INT_USERCLK1_OUT, // Optional user clock + output INT_USERCLK2_OUT, // Optional user clock + output INT_OOBCLK_OUT, // OOB | OOB + output INT_MMCM_LOCK_OUT, // Async | Async + output [1:0] INT_QPLLLOCK_OUT, + output [1:0] INT_QPLLOUTCLK_OUT, + output [1:0] INT_QPLLOUTREFCLK_OUT, + input [(LINK_CAP_MAX_LINK_WIDTH-1):0] INT_PCLK_SEL_SLAVE, + + // Shared Logic External + + //---------- External GT COMMON Ports ---------------------- + input [11:0] qpll_drp_crscode, + input [17:0] qpll_drp_fsm, + input [1:0] qpll_drp_done, + input [1:0] qpll_drp_reset, + input [1:0] qpll_qplllock, + input [1:0] qpll_qplloutclk, + input [1:0] qpll_qplloutrefclk, + output qpll_qplld, + output [1:0] qpll_qpllreset, + output qpll_drp_clk, + output qpll_drp_rst_n, + output qpll_drp_ovrd, + output qpll_drp_gen3, + output qpll_drp_start, + + //---------- External Clock Ports ---------------------- + input PIPE_PCLK_IN, // PCLK | PCLK + input PIPE_RXUSRCLK_IN, // RXUSERCLK + input [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_RXOUTCLK_IN, // RX recovered clock + input PIPE_DCLK_IN, // DCLK | DCLK + input PIPE_USERCLK1_IN, // Optional user clock + input PIPE_USERCLK2_IN, // Optional user clock + input PIPE_OOBCLK_IN, // OOB | OOB + input PIPE_MMCM_LOCK_IN, // Async | Async + output PIPE_TXOUTCLK_OUT, // PCLK | PCLK + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_RXOUTCLK_OUT, // RX recovered clock (for debug only) + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_PCLK_SEL_OUT, // PCLK | PCLK + output PIPE_GEN3_OUT , // PCLK | PCLK + +//-----------TRANSCEIVER DEBUG-------------------------------- + + output [4:0] PIPE_RST_FSM, + output [11:0] PIPE_QRST_FSM, + output [(LINK_CAP_MAX_LINK_WIDTH*5)-1:0] PIPE_RATE_FSM, + output [(LINK_CAP_MAX_LINK_WIDTH*6)-1:0] PIPE_SYNC_FSM_TX, + output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] PIPE_SYNC_FSM_RX, + output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] PIPE_DRP_FSM, + + output PIPE_RST_IDLE, + output PIPE_QRST_IDLE, + output PIPE_RATE_IDLE, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_EYESCANDATAERROR, + output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] PIPE_RXSTATUS, + output [(LINK_CAP_MAX_LINK_WIDTH*15)-1:0] PIPE_DMONITOROUT, + + //---------- Debug Ports ------------------------------- + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_CPLL_LOCK, + output [(LINK_CAP_MAX_LINK_WIDTH-1)>>2:0] PIPE_QPLL_LOCK, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_RXPMARESETDONE, + output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] PIPE_RXBUFSTATUS, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_TXPHALIGNDONE, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_TXPHINITDONE, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_TXDLYSRESETDONE, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_RXPHALIGNDONE, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_RXDLYSRESETDONE, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_RXSYNCDONE, + output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] PIPE_RXDISPERR, + output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] PIPE_RXNOTINTABLE, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] PIPE_RXCOMMADET, + + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_0, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_1, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_2, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_3, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_4, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_5, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_6, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_7, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_8, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_DEBUG_9, + output [31:0] PIPE_DEBUG, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_JTAG_RDY, + + input [ 2:0] PIPE_TXPRBSSEL, + input [ 2:0] PIPE_RXPRBSSEL, + input PIPE_TXPRBSFORCEERR, + input PIPE_RXPRBSCNTRESET, + input [ 2:0] PIPE_LOOPBACK, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_RXPRBSERR, + input [LINK_CAP_MAX_LINK_WIDTH-1:0] PIPE_TXINHIBIT, + + //-----------Channel DRP---------------------------------------- + output ext_ch_gt_drpclk, + input [(LINK_CAP_MAX_LINK_WIDTH*9)-1:0] ext_ch_gt_drpaddr, + input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpen, + input [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0]ext_ch_gt_drpdi, + input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpwe, + + output [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0]ext_ch_gt_drpdo, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drprdy, + + output wire phy_rdy_n +); + + + localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "FALSE") ? USER_CLK_FREQ : + (USER_CLK_FREQ == 4) ? 3 : + (USER_CLK_FREQ == 3) ? 2 : + USER_CLK_FREQ; + + localparam PCIE_LPM_DFE = (PL_FAST_TRAIN == "TRUE") ? "DFE" : "LPM"; + localparam PCIE_LINK_SPEED = (PL_FAST_TRAIN == "TRUE") ? 2 : 3; + + // The parameter PCIE_OOBCLK_MODE_ENABLE value should be "0" for simulation and for synthesis it should be 1 + //localparam PCIE_OOBCLK_MODE_ENABLE = (PL_FAST_TRAIN == "TRUE") ? 0 : 1; + localparam PCIE_OOBCLK_MODE_ENABLE = 1; + + localparam PCIE_TX_EIDLE_ASSERT_DELAY = (PL_FAST_TRAIN == "TRUE") ? 3'd4 : 3'd2; + + wire [ 7:0] gt_rx_phy_status_wire ; + wire [ 7:0] gt_rxchanisaligned_wire ; + wire [ 31:0] gt_rx_data_k_wire ; + wire [255:0] gt_rx_data_wire ; + wire [ 7:0] gt_rx_elec_idle_wire ; + wire [ 23:0] gt_rx_status_wire ; + wire [ 7:0] gt_rx_valid_wire ; + wire [ 7:0] gt_rx_polarity ; + wire [ 15:0] gt_power_down ; + wire [ 7:0] gt_tx_char_disp_mode ; + wire [ 31:0] gt_tx_data_k ; + wire [255:0] gt_tx_data ; + wire gt_tx_detect_rx_loopback ; + wire [ 7:0] gt_tx_elec_idle ; + wire [ 7:0] gt_rx_elec_idle_reset ; + wire [LINK_CAP_MAX_LINK_WIDTH-1:0] phystatus_rst ; + wire clock_locked ; + + wire [ 7:0] gt_rx_phy_status_wire_filter ; + wire [ 31:0] gt_rx_data_k_wire_filter ; + wire [255:0] gt_rx_data_wire_filter ; + wire [ 7:0] gt_rx_elec_idle_wire_filter ; + wire [ 23:0] gt_rx_status_wire_filter ; + wire [ 7:0] gt_rx_valid_wire_filter ; + + wire [LINK_CAP_MAX_LINK_WIDTH-1:0] gt_eyescandataerror ; + wire pipe_clk_int; + reg phy_rdy_n_int; + + reg reg_clock_locked; + wire all_phystatus_rst; + +reg [5:0] pl_ltssm_state_q; + +always @(posedge pipe_clk_int or negedge clock_locked) begin + + if (!clock_locked) + pl_ltssm_state_q <= #TCQ 6'b0; + else + pl_ltssm_state_q <= #TCQ pl_ltssm_state; + +end + + assign pipe_clk = pipe_clk_int ; + + wire plm_in_l0 = (pl_ltssm_state_q == 6'h16); + wire plm_in_rl = (pl_ltssm_state_q == 6'h1c); + wire plm_in_dt = (pl_ltssm_state_q == 6'h2d); + wire plm_in_rs = (pl_ltssm_state_q == 6'h1f); + +//-------------RX FILTER Instantiation----------------------------------------------------------// +genvar i; +generate for (i=0; i= 2 ) ? gt_rx_phy_status_wire[1] : 1'b0; +assign pipe_rx2_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[2] : 1'b0; +assign pipe_rx3_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[3] : 1'b0; +assign pipe_rx4_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[4] : 1'b0; +assign pipe_rx5_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[5] : 1'b0; +assign pipe_rx6_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[6] : 1'b0; +assign pipe_rx7_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[7] : 1'b0; + +assign pipe_rx0_chanisaligned = gt_rxchanisaligned_wire[0]; +assign pipe_rx1_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rxchanisaligned_wire[1] : 1'b0 ; +assign pipe_rx2_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rxchanisaligned_wire[2] : 1'b0 ; +assign pipe_rx3_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rxchanisaligned_wire[3] : 1'b0 ; +assign pipe_rx4_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[4] : 1'b0 ; +assign pipe_rx5_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[5] : 1'b0 ; +assign pipe_rx6_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[6] : 1'b0 ; +assign pipe_rx7_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[7] : 1'b0 ; + +//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< + +generate + if (LINK_CAP_MAX_LINK_WIDTH == 1) + begin : rx_link_width_x1 + + assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]}; + assign pipe_rx1_char_is_k = 2'b0 ; + assign pipe_rx2_char_is_k = 2'b0 ; + assign pipe_rx3_char_is_k = 2'b0 ; + assign pipe_rx4_char_is_k = 2'b0 ; + assign pipe_rx5_char_is_k = 2'b0 ; + assign pipe_rx6_char_is_k = 2'b0 ; + assign pipe_rx7_char_is_k = 2'b0 ; + + //synthesis warning solved: for nets below does not have driver; --assigned remaining bits of net gt_rx_data_wire to '0' + assign gt_rx_data_k_wire[3:2] = 2'b0; + assign gt_rx_data_k_wire[5:4] = 2'b0; + assign gt_rx_data_k_wire[7:6] = 2'b0; + assign gt_rx_data_k_wire[9:8] = 2'b0; + assign gt_rx_data_k_wire[11:10] = 2'b0; + assign gt_rx_data_k_wire[13:12] = 2'b0; + assign gt_rx_data_k_wire[15:14] = 2'b0; + assign gt_rx_data_k_wire[17:16] = 2'b0; + assign gt_rx_data_k_wire[19:18] = 2'b0; + assign gt_rx_data_k_wire[21:20] = 2'b0; + assign gt_rx_data_k_wire[23:22] = 2'b0; + assign gt_rx_data_k_wire[25:24] = 2'b0; + assign gt_rx_data_k_wire[27:26] = 2'b0; + assign gt_rx_data_k_wire[29:28] = 2'b0; + assign gt_rx_data_k_wire[31:30] = 2'b0; + + assign pipe_rx0_data = {gt_rx_data_wire[ 15: 8], gt_rx_data_wire[ 7: 0]}; + assign pipe_rx1_data = 16'h0 ; + assign pipe_rx2_data = 16'h0 ; + assign pipe_rx3_data = 16'h0 ; + assign pipe_rx4_data = 16'h0 ; + assign pipe_rx5_data = 16'h0 ; + assign pipe_rx6_data = 16'h0 ; + assign pipe_rx7_data = 16'h0 ; + + //synthesis warning solved: for nets below does not have driver; --assigned remaining bits of net gt_rx_data_wire to '0' + assign gt_rx_data_wire[31:16] = 16'b0; + assign gt_rx_data_wire[47:32] = 16'b0; + assign gt_rx_data_wire[63:48] = 16'b0; + assign gt_rx_data_wire[79:64] = 16'b0; + assign gt_rx_data_wire[95:80] = 16'b0; + assign gt_rx_data_wire[111:96] = 16'b0; + assign gt_rx_data_wire[127:112] = 16'b0; + assign gt_rx_data_wire[143:128] = 16'b0; + assign gt_rx_data_wire[159:144] = 16'b0; + assign gt_rx_data_wire[175:160] = 16'b0; + assign gt_rx_data_wire[191:176] = 16'b0; + assign gt_rx_data_wire[207:192] = 16'b0; + assign gt_rx_data_wire[223:208] = 16'b0; + assign gt_rx_data_wire[239:224] = 16'b0; + assign gt_rx_data_wire[255:240] = 16'b0; + + end // rx_link_width_x1 + else if (LINK_CAP_MAX_LINK_WIDTH == 2) + begin : rx_link_width_x2 + + assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]}; + assign pipe_rx1_char_is_k = {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]}; + assign pipe_rx2_char_is_k = 2'b0 ; + assign pipe_rx3_char_is_k = 2'b0 ; + assign pipe_rx4_char_is_k = 2'b0 ; + assign pipe_rx5_char_is_k = 2'b0 ; + assign pipe_rx6_char_is_k = 2'b0 ; + assign pipe_rx7_char_is_k = 2'b0 ; + + //synthesis warning solved: for nets below does not have driver; --assigned remaining bits of net gt_rx_data_wire to '0' + assign gt_rx_data_k_wire[3:2] = 2'b0; + assign gt_rx_data_k_wire[7:6] = 2'b0; + assign gt_rx_data_k_wire[9:8] = 2'b0; + assign gt_rx_data_k_wire[11:10] = 2'b0; + assign gt_rx_data_k_wire[13:12] = 2'b0; + assign gt_rx_data_k_wire[15:14] = 2'b0; + assign gt_rx_data_k_wire[17:16] = 2'b0; + assign gt_rx_data_k_wire[19:18] = 2'b0; + assign gt_rx_data_k_wire[21:20] = 2'b0; + assign gt_rx_data_k_wire[23:22] = 2'b0; + assign gt_rx_data_k_wire[25:24] = 2'b0; + assign gt_rx_data_k_wire[27:26] = 2'b0; + assign gt_rx_data_k_wire[29:28] = 2'b0; + assign gt_rx_data_k_wire[31:30] = 2'b0; + + assign pipe_rx0_data = {gt_rx_data_wire[15: 8], gt_rx_data_wire[ 7: 0]}; + assign pipe_rx1_data = {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]} ; + assign pipe_rx2_data = 16'h0 ; + assign pipe_rx3_data = 16'h0 ; + assign pipe_rx4_data = 16'h0 ; + assign pipe_rx5_data = 16'h0 ; + assign pipe_rx6_data = 16'h0 ; + assign pipe_rx7_data = 16'h0 ; + + //synthesis warning solved: for nets below does not have driver; --assigned remaining bits of net gt_rx_data_wire to '0' + assign gt_rx_data_wire[31:16] = 16'b0; + assign gt_rx_data_wire[63:48] = 16'b0; + assign gt_rx_data_wire[79:64] = 16'b0; + assign gt_rx_data_wire[95:80] = 16'b0; + assign gt_rx_data_wire[111:96] = 16'b0; + assign gt_rx_data_wire[127:112] = 16'b0; + assign gt_rx_data_wire[143:128] = 16'b0; + assign gt_rx_data_wire[159:144] = 16'b0; + assign gt_rx_data_wire[175:160] = 16'b0; + assign gt_rx_data_wire[191:176] = 16'b0; + assign gt_rx_data_wire[207:192] = 16'b0; + assign gt_rx_data_wire[223:208] = 16'b0; + assign gt_rx_data_wire[239:224] = 16'b0; + assign gt_rx_data_wire[255:240] = 16'b0; + + end // rx_link_width_x2 + else if (LINK_CAP_MAX_LINK_WIDTH == 4) + begin : rx_link_width_x4 + + assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]}; + assign pipe_rx1_char_is_k = {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]}; + assign pipe_rx2_char_is_k = {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]}; + assign pipe_rx3_char_is_k = {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]}; + assign pipe_rx4_char_is_k = 2'b0 ; + assign pipe_rx5_char_is_k = 2'b0 ; + assign pipe_rx6_char_is_k = 2'b0 ; + assign pipe_rx7_char_is_k = 2'b0 ; + + //synthesis warning solved: for nets below does not have driver; --assigned remaining bits of net gt_rx_data_wire to '0' + assign gt_rx_data_k_wire[3:2] = 2'b0; + assign gt_rx_data_k_wire[7:6] = 2'b0; + assign gt_rx_data_k_wire[11:10] = 2'b0; + assign gt_rx_data_k_wire[15:14] = 2'b0; + assign gt_rx_data_k_wire[17:16] = 2'b0; + assign gt_rx_data_k_wire[19:18] = 2'b0; + assign gt_rx_data_k_wire[21:20] = 2'b0; + assign gt_rx_data_k_wire[23:22] = 2'b0; + assign gt_rx_data_k_wire[25:24] = 2'b0; + assign gt_rx_data_k_wire[27:26] = 2'b0; + assign gt_rx_data_k_wire[29:28] = 2'b0; + assign gt_rx_data_k_wire[31:30] = 2'b0; + + assign pipe_rx0_data = {gt_rx_data_wire[15: 8], gt_rx_data_wire[ 7: 0]}; + assign pipe_rx1_data = {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]}; + assign pipe_rx2_data = {gt_rx_data_wire[79:72], gt_rx_data_wire[71:64]}; + assign pipe_rx3_data = {gt_rx_data_wire[111:104], gt_rx_data_wire[103:96]}; + assign pipe_rx4_data = 16'h0 ; + assign pipe_rx5_data = 16'h0 ; + assign pipe_rx6_data = 16'h0 ; + assign pipe_rx7_data = 16'h0 ; + + //synthesis warning solved: for nets below does not have driver; --assigned remaining bits of net gt_rx_data_wire to '0' + assign gt_rx_data_wire[31:16] = 16'b0; + assign gt_rx_data_wire[63:48] = 16'b0; + assign gt_rx_data_wire[95:80] = 16'b0; + assign gt_rx_data_wire[127:112] = 16'b0; + assign gt_rx_data_wire[143:128] = 16'b0; + assign gt_rx_data_wire[159:144] = 16'b0; + assign gt_rx_data_wire[175:160] = 16'b0; + assign gt_rx_data_wire[191:176] = 16'b0; + assign gt_rx_data_wire[207:192] = 16'b0; + assign gt_rx_data_wire[223:208] = 16'b0; + assign gt_rx_data_wire[239:224] = 16'b0; + assign gt_rx_data_wire[255:240] = 16'b0; + + end // rx_link_width_x4 + else + begin : rx_link_width_x8 + + assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]}; + assign pipe_rx1_char_is_k = {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]}; + assign pipe_rx2_char_is_k = {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]}; + assign pipe_rx3_char_is_k = {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]}; + assign pipe_rx4_char_is_k = {gt_rx_data_k_wire[17], gt_rx_data_k_wire[16]}; + assign pipe_rx5_char_is_k = {gt_rx_data_k_wire[21], gt_rx_data_k_wire[20]}; + assign pipe_rx6_char_is_k = {gt_rx_data_k_wire[25], gt_rx_data_k_wire[24]}; + assign pipe_rx7_char_is_k = {gt_rx_data_k_wire[29], gt_rx_data_k_wire[28]}; + + //synthesis warning solved: for nets below does not have driver; --assigned remaining bits of net gt_rx_data_wire to '0' + assign gt_rx_data_k_wire[3:2] = 2'b0; + assign gt_rx_data_k_wire[7:6] = 2'b0; + assign gt_rx_data_k_wire[11:10] = 2'b0; + assign gt_rx_data_k_wire[15:14] = 2'b0; + assign gt_rx_data_k_wire[19:18] = 2'b0; + assign gt_rx_data_k_wire[23:22] = 2'b0; + assign gt_rx_data_k_wire[27:26] = 2'b0; + assign gt_rx_data_k_wire[31:30] = 2'b0; + + assign pipe_rx0_data = {gt_rx_data_wire[15: 8], gt_rx_data_wire[ 7: 0]}; + assign pipe_rx1_data = {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]}; + assign pipe_rx2_data = {gt_rx_data_wire[79:72], gt_rx_data_wire[71:64]}; + assign pipe_rx3_data = {gt_rx_data_wire[111:104], gt_rx_data_wire[103:96]}; + assign pipe_rx4_data = {gt_rx_data_wire[143:136], gt_rx_data_wire[135:128]}; + assign pipe_rx5_data = {gt_rx_data_wire[175:168], gt_rx_data_wire[167:160]}; + assign pipe_rx6_data = {gt_rx_data_wire[207:200], gt_rx_data_wire[199:192]}; + assign pipe_rx7_data = {gt_rx_data_wire[239:232], gt_rx_data_wire[231:224]}; + + //synthesis warning solved: for nets below does not have driver; --assigned remaining bits of net gt_rx_data_wire to '0' + assign gt_rx_data_wire[31:16] = 16'b0; + assign gt_rx_data_wire[63:48] = 16'b0; + assign gt_rx_data_wire[95:80] = 16'b0; + assign gt_rx_data_wire[127:112] = 16'b0; + assign gt_rx_data_wire[159:144] = 16'b0; + assign gt_rx_data_wire[191:176] = 16'b0; + assign gt_rx_data_wire[223:208] = 16'b0; + assign gt_rx_data_wire[255:240] = 16'b0; + + end // rx_link_width_x8 +endgenerate + +assign pipe_rx0_status = gt_rx_status_wire[ 2: 0]; +assign pipe_rx1_status = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_status_wire[ 5: 3] : 3'b0 ; +assign pipe_rx2_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[ 8: 6] : 3'b0 ; +assign pipe_rx3_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[11: 9] : 3'b0 ; +assign pipe_rx4_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[14:12] : 3'b0 ; +assign pipe_rx5_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[17:15] : 3'b0 ; +assign pipe_rx6_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[20:18] : 3'b0 ; +assign pipe_rx7_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[23:21] : 3'b0 ; + +//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< + +assign pipe_rx0_elec_idle = gt_rx_elec_idle_wire[0]; +assign pipe_rx1_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_elec_idle_wire[1] : 1'b1 ; +assign pipe_rx2_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[2] : 1'b1 ; +assign pipe_rx3_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[3] : 1'b1 ; +assign pipe_rx4_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[4] : 1'b1 ; +assign pipe_rx5_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[5] : 1'b1 ; +assign pipe_rx6_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[6] : 1'b1 ; +assign pipe_rx7_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[7] : 1'b1 ; + +assign pipe_rx0_valid = gt_rx_valid_wire[0]; +assign pipe_rx1_valid = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_valid_wire[1] : 1'b0 ; +assign pipe_rx2_valid = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[2] : 1'b0 ; +assign pipe_rx3_valid = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[3] : 1'b0 ; +assign pipe_rx4_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[4] : 1'b0 ; +assign pipe_rx5_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[5] : 1'b0 ; +assign pipe_rx6_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[6] : 1'b0 ; +assign pipe_rx7_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[7] : 1'b0 ; + +assign gt_rx_polarity[0] = pipe_rx0_polarity; +assign gt_rx_polarity[1] = pipe_rx1_polarity; +assign gt_rx_polarity[2] = pipe_rx2_polarity; +assign gt_rx_polarity[3] = pipe_rx3_polarity; +assign gt_rx_polarity[4] = pipe_rx4_polarity; +assign gt_rx_polarity[5] = pipe_rx5_polarity; +assign gt_rx_polarity[6] = pipe_rx6_polarity; +assign gt_rx_polarity[7] = pipe_rx7_polarity; + +assign gt_power_down[ 1: 0] = pipe_tx0_powerdown; +assign gt_power_down[ 3: 2] = pipe_tx1_powerdown; +assign gt_power_down[ 5: 4] = pipe_tx2_powerdown; +assign gt_power_down[ 7: 6] = pipe_tx3_powerdown; +assign gt_power_down[ 9: 8] = pipe_tx4_powerdown; +assign gt_power_down[11:10] = pipe_tx5_powerdown; +assign gt_power_down[13:12] = pipe_tx6_powerdown; +assign gt_power_down[15:14] = pipe_tx7_powerdown; + +assign gt_tx_char_disp_mode = {pipe_tx7_compliance, + pipe_tx6_compliance, + pipe_tx5_compliance, + pipe_tx4_compliance, + pipe_tx3_compliance, + pipe_tx2_compliance, + pipe_tx1_compliance, + pipe_tx0_compliance}; + + +assign gt_tx_data_k = {2'd0, + pipe_tx7_char_is_k, + 2'd0, + pipe_tx6_char_is_k, + 2'd0, + pipe_tx5_char_is_k, + 2'd0, + pipe_tx4_char_is_k, + 2'd0, + pipe_tx3_char_is_k, + 2'd0, + pipe_tx2_char_is_k, + 2'd0, + pipe_tx1_char_is_k, + 2'd0, + pipe_tx0_char_is_k}; + +assign gt_tx_data = {16'd0, + pipe_tx7_data, + 16'd0, + pipe_tx6_data, + 16'd0, + pipe_tx5_data, + 16'd0, + pipe_tx4_data, + 16'd0, + pipe_tx3_data, + 16'd0, + pipe_tx2_data, + 16'd0, + pipe_tx1_data, + 16'd0, + pipe_tx0_data}; + +assign gt_tx_detect_rx_loopback = pipe_tx_rcvr_det; + +assign gt_tx_elec_idle = {pipe_tx7_elec_idle, + pipe_tx6_elec_idle, + pipe_tx5_elec_idle, + pipe_tx4_elec_idle, + pipe_tx3_elec_idle, + pipe_tx2_elec_idle, + pipe_tx1_elec_idle, + pipe_tx0_elec_idle}; + +always @(posedge pipe_clk_int or negedge clock_locked) begin + if (!clock_locked) + reg_clock_locked <= #TCQ 1'b0; + else + reg_clock_locked <= #TCQ 1'b1; +end + +always @(posedge pipe_clk_int) begin + if (!reg_clock_locked) + phy_rdy_n_int <= #TCQ 1'b0; + else + phy_rdy_n_int <= #TCQ all_phystatus_rst; +end + +assign all_phystatus_rst = (&phystatus_rst[LINK_CAP_MAX_LINK_WIDTH-1:0]); +assign phy_rdy_n = phy_rdy_n_int; + +endmodule + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_wrapper.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_wrapper.v new file mode 100644 index 0000000..2507de4 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_wrapper.v @@ -0,0 +1,2369 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_gt_wrapper.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : gt_wrapper.v +// Description : GT Wrapper Module for 7 Series Transceiver +// Version : 19.0 +//------------------------------------------------------------------------------ + + + +`timescale 1ns / 1ps + + + +//---------- GT Wrapper -------------------------------------------------------- +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_gt_wrapper # +( + parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode + parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup + parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level + parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device + parameter PCIE_USE_MODE = "3.0", // PCIe use mode + parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 + parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only + parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only + parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable + parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only + parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode + parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode + parameter PCIE_CHAN_BOND = 0, // PCIe channel bonding mode + parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only + parameter PCIE_LANE = 1, // PCIe number of lane + parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency + parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd4, // PCIe TX electrical idle assert delay + parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode + parameter TX_MARGIN_FULL_0 = 7'b1001111, // 1000 mV + parameter TX_MARGIN_FULL_1 = 7'b1001110, // 950 mV + parameter TX_MARGIN_FULL_2 = 7'b1001101, // 900 mV + parameter TX_MARGIN_FULL_3 = 7'b1001100, // 850 mV + parameter TX_MARGIN_FULL_4 = 7'b1000011, // 400 mV + parameter TX_MARGIN_LOW_0 = 7'b1000101, // 500 mV + parameter TX_MARGIN_LOW_1 = 7'b1000110 , // 450 mV + parameter TX_MARGIN_LOW_2 = 7'b1000011, // 400 mV + parameter TX_MARGIN_LOW_3 = 7'b1000010 , // 350 mV + parameter TX_MARGIN_LOW_4 = 7'b1000000 , + parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode +) + +( + //---------- GT User Ports ----------------------------- + input GT_MASTER, + input GT_GEN3, + input GT_RX_CONVERGE, + + //---------- GT Clock Ports ---------------------------- + input GT_GTREFCLK0, + input GT_QPLLCLK, + input GT_QPLLREFCLK, + input GT_TXUSRCLK, + input GT_RXUSRCLK, + input GT_TXUSRCLK2, + input GT_RXUSRCLK2, + input GT_OOBCLK, + input [ 1:0] GT_TXSYSCLKSEL, + input [ 1:0] GT_RXSYSCLKSEL, + input GT_CPLLPDREFCLK, + output GT_TXOUTCLK, + output GT_RXOUTCLK, + output GT_CPLLLOCK, + output GT_RXCDRLOCK, + + //---------- GT Reset Ports ---------------------------- + input GT_CPLLPD, + input GT_CPLLRESET, + input GT_TXUSERRDY, + input GT_RXUSERRDY, + input GT_RESETOVRD, + input GT_GTTXRESET, + input GT_GTRXRESET, + input GT_TXPMARESET, + input GT_RXPMARESET, + input GT_RXCDRRESET, + input GT_RXCDRFREQRESET, + input GT_RXDFELPMRESET, + input GT_EYESCANRESET, + input GT_TXPCSRESET, + input GT_RXPCSRESET, + input GT_RXBUFRESET, + + output GT_EYESCANDATAERROR, + output GT_TXRESETDONE, + output GT_RXRESETDONE, + output GT_RXPMARESETDONE, + + //---------- GT TX Data Ports -------------------------- + input [31:0] GT_TXDATA, + input [ 3:0] GT_TXDATAK, + + output GT_TXP, + output GT_TXN, + + //---------- GT RX Data Ports -------------------------- + input GT_RXN, + input GT_RXP, + + output [31:0] GT_RXDATA, + output [ 3:0] GT_RXDATAK, + + //---------- GT Command Ports -------------------------- + input GT_TXDETECTRX, + input GT_TXELECIDLE, + input GT_TXCOMPLIANCE, + input GT_RXPOLARITY, + input [ 1:0] GT_TXPOWERDOWN, + input [ 1:0] GT_RXPOWERDOWN, + input [ 2:0] GT_TXRATE, + input [ 2:0] GT_RXRATE, + + //---------- GT Electrical Command Ports --------------- + input [ 2:0] GT_TXMARGIN, + input GT_TXSWING, + input GT_TXDEEMPH, + input GT_TXINHIBIT, + input [ 4:0] GT_TXPRECURSOR, + input [ 6:0] GT_TXMAINCURSOR, + input [ 4:0] GT_TXPOSTCURSOR, + + //---------- GT Status Ports --------------------------- + output GT_RXVALID, + output GT_PHYSTATUS, + output GT_RXELECIDLE, + output [ 2:0] GT_RXSTATUS, + output [ 2:0] GT_RXBUFSTATUS, + output GT_TXRATEDONE, + output GT_RXRATEDONE, + + output [7:0] GT_RXDISPERR, + output [7:0] GT_RXNOTINTABLE, + + //---------- GT DRP Ports ------------------------------ + input GT_DRPCLK, + input [ 8:0] GT_DRPADDR, + input GT_DRPEN, + input [15:0] GT_DRPDI, + input GT_DRPWE, + + output [15:0] GT_DRPDO, + output GT_DRPRDY, + + //---------- GT TX Sync Ports -------------------------- + input GT_TXPHALIGN, + input GT_TXPHALIGNEN, + input GT_TXPHINIT, + input GT_TXDLYBYPASS, + input GT_TXDLYSRESET, + input GT_TXDLYEN, + + output GT_TXDLYSRESETDONE, + output GT_TXPHINITDONE, + output GT_TXPHALIGNDONE, + + input GT_TXPHDLYRESET, + input GT_TXSYNCMODE, // GTH + input GT_TXSYNCIN, // GTH + input GT_TXSYNCALLIN, // GTH + + output GT_TXSYNCOUT, // GTH + output GT_TXSYNCDONE, // GTH + + //---------- GT RX Sync Ports -------------------------- + input GT_RXPHALIGN, + input GT_RXPHALIGNEN, + input GT_RXDLYBYPASS, + input GT_RXDLYSRESET, + input GT_RXDLYEN, + input GT_RXDDIEN, + + output GT_RXDLYSRESETDONE, + output GT_RXPHALIGNDONE, + + input GT_RXSYNCMODE, // GTH + input GT_RXSYNCIN, // GTH + input GT_RXSYNCALLIN, // GTH + + output GT_RXSYNCOUT, // GTH + output GT_RXSYNCDONE, // GTH + + //---------- GT Comma Alignment Ports ------------------ + input GT_RXSLIDE, + + output GT_RXCOMMADET, + output [ 3:0] GT_RXCHARISCOMMA, + output GT_RXBYTEISALIGNED, + output GT_RXBYTEREALIGN, + + //---------- GT Channel Bonding Ports ------------------ + input GT_RXCHBONDEN, + input [ 4:0] GT_RXCHBONDI, + input [ 2:0] GT_RXCHBONDLEVEL, + input GT_RXCHBONDMASTER, + input GT_RXCHBONDSLAVE, + + output GT_RXCHANISALIGNED, + output [ 4:0] GT_RXCHBONDO, + + //---------- GT PRBS/Loopback Ports -------------------- + input [ 2:0] GT_TXPRBSSEL, + input [ 2:0] GT_RXPRBSSEL, + input GT_TXPRBSFORCEERR, + input GT_RXPRBSCNTRESET, + input [ 2:0] GT_LOOPBACK, + + output GT_RXPRBSERR, + + //---------- GT Debug Ports ---------------------------- + output [14:0] GT_DMONITOROUT + +); + + //---------- Internal Signals -------------------------- + wire [ 2:0] txoutclksel; + wire [ 2:0] rxoutclksel; + wire [63:0] rxdata; + wire [ 7:0] rxdatak; + wire [ 7:0] rxchariscomma; + wire rxlpmen; + wire [14:0] dmonitorout; + wire dmonitorclk; + + wire cpllpd; + wire cpllrst; + + //---------- Select CPLL and Clock Dividers ------------ + localparam CPLL_REFCLK_DIV = 1; + localparam CPLL_FBDIV_45 = 5; + localparam CPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 2 : + (PCIE_REFCLK_FREQ == 1) ? 4 : 5; + localparam OUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 4 : 2; + localparam CLK25_DIV = (PCIE_REFCLK_FREQ == 2) ? 10 : + (PCIE_REFCLK_FREQ == 1) ? 5 : 4; + + //---------- Select IES vs. GES ------------------------ + localparam CLKMUX_PD = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 1'd0 : 1'd1; + + //---------- Select GTP CPLL configuration ------------- + // PLL0/1_CFG[ 5:2] = CP1 : [ 8, 4, 2, 1] units + // PLL0/1_CFG[10:6] = CP2 : [16, 8, 4, 2, 1] units + // CP2/CP1 = 2 to 3 + // (8/4=2) = 27'h01F0210 = 0000_0001_1111_0000_0010_0001_0000 + // (9/3=3) = 27'h01F024C = 0000_0001_1111_0000_0010_0100_1100 + // (8/3=2.67) = 27'h01F020C = 0000_0001_1111_0000_0010_0000_1100 + // (7/3=2.33) = 27'h01F01CC = 0000_0001_1111_0000_0001_1100_1100 + // (6/3=2) = 27'h01F018C = 0000_0001_1111_0000_0001_1000_1100 + // (5/3=1.67) = 27'h01F014C = 0000_0001_1111_0000_0001_0100_1100 + // (6/2=3) = 27'h01F0188 = 0000_0001_1111_0000_0001_1000_1000 + //---------- Select GTX CPLL configuration ------------- + // CPLL_CFG[ 5: 2] = CP1 : [ 8, 4, 2, 1] units + // CPLL_CFG[22:18] = CP2 : [16, 8, 4, 2, 1] units + // CP2/CP1 = 2 to 3 + // (9/3=3) = 1010_0100_0000_0111_1100_1100 + //------------------------------------------------------ + localparam CPLL_CFG = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 24'hB407CC : 24'hA407CC; + + //---------- Select TX XCLK ---------------------------- + // TXOUT for TX Buffer Use + // TXUSR for TX Buffer Bypass + //------------------------------------------------------ + localparam TX_XCLK_SEL = (PCIE_TXBUF_EN == "TRUE") ? "TXOUT" : "TXUSR"; + + //---------- Select TX Receiver Detection Configuration + localparam TX_RXDETECT_CFG = (PCIE_REFCLK_FREQ == 2) ? 14'd250 : + (PCIE_REFCLK_FREQ == 1) ? 14'd125 : 14'd100; + localparam TX_RXDETECT_REF = (((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) && (PCIE_SIM_MODE == "FALSE")) ? 3'b000 : 3'b011; + + //---------- Select PCS_RSVD_ATTR ---------------------- + // [0]: 1 = enable latch when bypassing TX buffer, 0 = disable latch when using TX buffer + // [1]: 1 = enable manual TX sync, 0 = enable auto TX sync + // [2]: 1 = enable manual RX sync, 0 = enable auto RX sync + // [3]: 1 = select external clock for OOB 0 = select reference clock for OOB + // [6]: 1 = enable DMON 0 = disable DMON + // [7]: 1 = filter stale TX[P/N] data when exiting TX electrical idle + // [8]: 1 = power up OOB 0 = power down OOB + //------------------------------------------------------ + localparam OOBCLK_SEL = (PCIE_OOBCLK_MODE == 0) ? 1'd0 : 1'd1; // GTX + localparam RXOOB_CLK_CFG = (PCIE_OOBCLK_MODE == 0) ? "PMA" : "FABRIC"; // GTH/GTP + + localparam PCS_RSVD_ATTR = ((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} : + ((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} : + ((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd7} : + ((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd6} : + ((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd5} : + ((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd4} : + ((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd3} : + ((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd2} : + ((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} : + ((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} : {44'h0000000001C, OOBCLK_SEL, 3'd7}; + + //---------- Select RXCDR_CFG -------------------------- + + //---------- GTX Note ---------------------------------- + // For GTX PCIe Gen1/Gen2 with 8B/10B, the following CDR setting may provide more margin + // Async 72'h03_8000_23FF_1040_0020 + // Sync: 72'h03_0000_23FF_1040_0020 + //------------------------------------------------------ + + localparam RXCDR_CFG_GTX = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? + ((PCIE_ASYNC_EN == "TRUE") ? 72'b0000_0010_0000_0111_1111_1110_0010_0000_0110_0000_0010_0001_0001_0000_0000000000010000 + : 72'h11_07FE_4060_0104_0000): // IES setting + ((PCIE_ASYNC_EN == "TRUE") ? 72'h03_8000_23FF_1020_0020 // + : 72'h03_0000_23FF_1020_0020); // optimized for GES silicon + + localparam RXCDR_CFG_GTH = (PCIE_USE_MODE == "2.0") ? + ((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0011_07FE_4060_2104_1010 + : 83'h0_0011_07FE_4060_0104_1010): // Optimized for IES silicon + ((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0020_07FE_2000_C208_8018 + : 83'h0_0020_07FE_2000_C208_0018); // Optimized for 1.2 silicon + + localparam RXCDR_CFG_GTP = ((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0001_07FE_4060_2104_1010 + : 83'h0_0001_07FE_4060_0104_1010); // Optimized for IES silicon + + + + + //---------- Select TX and RX Sync Mode ---------------- + localparam TXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1; + localparam RXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1; + + localparam TXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1; + localparam RXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1; + + //---------- Select Clock Correction Min and Max Latency + // CLK_COR_MIN_LAT = Larger of (2 * RXCHBONDLEVEL + 13) or (CHAN_BOND_MAX_SKEW + 11) + // = 13 when PCIE_LANE = 1 + // CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + CLK_COR_SEQ_LEN + 1 + // = CLK_COR_MIN_LAT + 2 + //------------------------------------------------------ + + //---------- CLK_COR_MIN_LAT Look-up Table ------------- + // Lane | One-Hop | Daisy-Chain | Binary-Tree + //------------------------------------------------------ + // 0 | 13 | 13 | 13 + // 1 | 15 to 18 | 15 to 18 | 15 to 18 + // 2 | 15 to 18 | 17 to 18 | 15 to 18 + // 3 | 15 to 18 | 19 | 17 to 18 + // 4 | 15 to 18 | 21 | 17 to 18 + // 5 | 15 to 18 | 23 | 19 + // 6 | 15 to 18 | 25 | 19 + // 7 | 15 to 18 | 27 | 21 + //------------------------------------------------------ + + localparam CLK_COR_MIN_LAT = ((PCIE_LANE == 8) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 27 : 21) : + ((PCIE_LANE == 7) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 25 : 19) : + ((PCIE_LANE == 6) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 23 : 19) : + ((PCIE_LANE == 5) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 21 : 18) : + ((PCIE_LANE == 4) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 19 : 18) : + ((PCIE_LANE == 3) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) : + ((PCIE_LANE == 2) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) : + ((PCIE_LANE == 1) || (PCIE_CHAN_BOND_EN == "FALSE")) ? 13 : 18; + + localparam CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + 2; + + //---------- Simulation Speedup ------------------------ + //localparam CFOK_CFG_GTH = (PCIE_SIM_MODE == "TRUE") ? 42'h240_0004_0F80 : 42'h248_0004_0E80; // [8] : 1 = Skip CFOK + //localparam CFOK_CFG_GTP = (PCIE_SIM_MODE == "TRUE") ? 43'h000_0000_0000 : 43'h000_0000_0100; // [2] : 1 = Skip CFOK + + //---------- Select [TX/RX]OUTCLK ---------------------- + assign txoutclksel = GT_MASTER ? 3'd3 : 3'd0; + assign rxoutclksel = ((PCIE_DEBUG_MODE == 1) || ((PCIE_ASYNC_EN == "TRUE") && GT_MASTER)) ? 3'd2 : 3'd0; + + //---------- Select DFE vs. LPM ------------------------ + // Gen1/2 = Use LPM by default. Option to use DFE. + // Gen3 = Use DFE by default. Option to use LPM. + //------------------------------------------------------ + assign rxlpmen = GT_GEN3 ? ((PCIE_LPM_DFE_GEN3 == "LPM") ? 1'd1 : 1'd0) : ((PCIE_LPM_DFE == "LPM") ? 1'd1 : 1'd0); + + + +//---------- Generate DMONITOR Clock Buffer for Debug ------ +generate if (PCIE_DEBUG_MODE == 1) + + begin : dmonitorclk_i + //---------- DMONITOR CLK ------------------------------ + BUFG dmonitorclk_i + ( + //---------- Input --------------------------------- + .I (dmonitorout[7]), + //---------- Output -------------------------------- + .O (dmonitorclk) + ); + end + +else + + begin : dmonitorclk_i_disable + assign dmonitorclk = 1'd0; + end + +endgenerate + + +pcie_7x_0_gtx_cpllpd_ovrd cpllPDInst ( + .i_ibufds_gte2(GT_CPLLPDREFCLK), + .o_cpllpd_ovrd(cpllpd), + .o_cpllreset_ovrd(cpllrst)); + +//---------- Select GTX or GTH or GTP ------------------------------------------ +// Notes : Attributes that are commented out always use the GT default settings +//------------------------------------------------------------------------------ +generate if (PCIE_GT_DEVICE == "GTP") + + begin : gtp_channel + + //---------- GTP Channel Module -------------------------------------------- + GTPE2_CHANNEL # + ( + + //---------- Simulation Attributes ------------------------------------- + .SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), // + .SIM_RECEIVER_DETECT_PASS ("TRUE"), // + .SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), // + .SIM_VERSION (PCIE_USE_MODE), // + + //---------- Clock Attributes ------------------------------------------ + .TXOUT_DIV (OUT_DIV), // + .RXOUT_DIV (OUT_DIV), // + .TX_CLK25_DIV (CLK25_DIV), // + .RX_CLK25_DIV (CLK25_DIV), // + //.TX_CLKMUX_EN ( 1'b1), // GTP rename + //.RX_CLKMUX_EN ( 1'b1), // GTP rename + .TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer + .RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer + //.OUTREFCLK_SEL_INV ( 2'b11), // + + //---------- Reset Attributes ------------------------------------------ + .TXPCSRESET_TIME ( 5'b00001), // + .RXPCSRESET_TIME ( 5'b00001), // + .TXPMARESET_TIME ( 5'b00011), // + .RXPMARESET_TIME ( 5'b00011), // Optimized for sim + //.RXISCANRESET_TIME ( 5'b00001), // + + //---------- TX Data Attributes ---------------------------------------- + .TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2 + + //---------- RX Data Attributes ---------------------------------------- + .RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2 + + //---------- Command Attributes ---------------------------------------- + .TX_RXDETECT_CFG (TX_RXDETECT_CFG), // + .TX_RXDETECT_REF ( 3'b011), // + .RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable + .RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for IES + .TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim + .TX_EIDLE_DEASSERT_DELAY ( 3'b010), // Optimized for sim + //.PD_TRANS_TIME_FROM_P2 (12'h03C), // + .PD_TRANS_TIME_NONE_P2 ( 8'h09), // + //.PD_TRANS_TIME_TO_P2 ( 8'h64), // + //.TRANS_TIME_RATE ( 8'h0E), // + + //---------- Electrical Command Attributes ----------------------------- + .TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3 + .TX_DEEMPH0 ( 5'b10100), // 6.0 dB + .TX_DEEMPH1 ( 5'b01011), // 3.5 dB + .TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV + .TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV + .TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV + .TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV + .TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV + .TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV + .TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV + .TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV + .TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV + .TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV + .TX_MAINCURSOR_SEL ( 1'b0), // + .TX_PREDRIVER_MODE ( 1'b0), // GTP + + //---------- Status Attributes ----------------------------------------- + //.RX_SIG_VALID_DLY ( 4), // CHECK + + //---------- DRP Attributes -------------------------------------------- + + //---------- PCS Attributes -------------------------------------------- + .PCS_PCIE_EN ("TRUE"), // PCIe + .PCS_RSVD_ATTR (48'h0000_0000_0100), // [8] : 1 = OOB power-up + + //---------- PMA Attributes ------------------------------------------- + //.CLK_COMMON_SWING ( 1'b0), // GTP new + //.PMA_RSV (32'd0), // + .PMA_RSV2 (32'h00002040), // Optimized for GES + //.PMA_RSV3 ( 2'd0), // + //.PMA_RSV4 ( 4'd0), // Changed from 15 to 4-bits + //.PMA_RSV5 ( 1'd0), // Changed from 4 to 1-bit + //.PMA_RSV6 ( 1'd0), // GTP new + //.PMA_RSV7 ( 1'd0), // GTP new + .RX_BIAS_CFG (16'h0F33), // Optimized for IES + .TERM_RCAL_CFG (15'b100001000010000), // Optimized for IES + .TERM_RCAL_OVRD ( 3'b000), // Optimized for IES + + //---------- TX PI ---------------------------------------------------- + //.TXPI_CFG0 ( 2'd0), // + //.TXPI_CFG1 ( 2'd0), // + //.TXPI_CFG2 ( 2'd0), // + //.TXPI_CFG3 ( 1'd0), // + //.TXPI_CFG4 ( 1'd0), // + //.TXPI_CFG5 ( 3'd000), // + //.TXPI_GREY_SEL ( 1'd0), // + //.TXPI_INVSTROBE_SEL ( 1'd0), // + //.TXPI_PPMCLK_SEL ("TXUSRCLK2"), // + //.TXPI_PPM_CFG ( 8'd0), // + //.TXPI_SYNFREQ_PPM ( 3'd0), // + + //---------- RX PI ----------------------------------------------------- + .RXPI_CFG0 ( 3'd0), // Changed from 3 to 2-bits, Optimized for IES + .RXPI_CFG1 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES + .RXPI_CFG2 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES + + //---------- CDR Attributes --------------------------------------------- + //.RXCDR_CFG (72'b0000_001000000_11111_11111_001000000_011_0000111_000_001000_010000_100000000000000), // CHECK + .RXCDR_CFG (RXCDR_CFG_GTP), // Optimized for IES + .RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001) CHECK + .RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2 + .RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3 + .RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3 + //.RXCDRFREQRESET_TIME ( 5'b00001), // + //.RXCDRPHRESET_TIME ( 5'b00001), // + + //---------- LPM Attributes -------------------------------------------- + //.RXLPMRESET_TIME ( 7'b0001111), // GTP new + //.RXLPM_BIAS_STARTUP_DISABLE ( 1'b0), // GTP new + .RXLPM_CFG ( 4'b0110), // GTP new, optimized for IES + //.RXLPM_CFG1 ( 1'b0), // GTP new + //.RXLPM_CM_CFG ( 1'b0), // GTP new + .RXLPM_GC_CFG ( 9'b111100010), // GTP new, optimized for IES + .RXLPM_GC_CFG2 ( 3'b001), // GTP new, optimized for IES + //.RXLPM_HF_CFG (14'b00001111110000), // + .RXLPM_HF_CFG2 ( 5'b01010), // GTP new + //.RXLPM_HF_CFG3 ( 4'b0000), // GTP new + .RXLPM_HOLD_DURING_EIDLE ( 1'b1), // GTP new + .RXLPM_INCM_CFG ( 1'b1), // GTP new, optimized for IES + .RXLPM_IPCM_CFG ( 1'b0), // GTP new, optimized for IES + //.RXLPM_LF_CFG (18'b000000001111110000), // + .RXLPM_LF_CFG2 ( 5'b01010), // GTP new, optimized for IES + .RXLPM_OSINT_CFG ( 3'b100), // GTP new, optimized for IES + + //---------- OS Attributes --------------------------------------------- + .RX_OS_CFG (13'h0080), // CHECK + .RXOSCALRESET_TIME (5'b00011), // Optimized for IES + .RXOSCALRESET_TIMEOUT (5'b00000), // Disable timeout, Optimized for IES + + //---------- Eye Scan Attributes --------------------------------------- + //.ES_CLK_PHASE_SEL ( 1'b0), // + //.ES_CONTROL ( 6'd0), // + //.ES_ERRDET_EN ("FALSE"), // + .ES_EYE_SCAN_EN ("FALSE"), // + //.ES_HORZ_OFFSET (12'd0), // + //.ES_PMA_CFG (10'd0), // + //.ES_PRESCALE ( 5'd0), // + //.ES_QUAL_MASK (80'd0), // + //.ES_QUALIFIER (80'd0), // + //.ES_SDATA_MASK (80'd0), // + //.ES_VERT_OFFSET ( 9'd0), // + + //---------- TX Buffer Attributes -------------------------------------- + .TXBUF_EN (PCIE_TXBUF_EN), // + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), // + + //---------- RX Buffer Attributes -------------------------------------- + .RXBUF_EN ("TRUE"), // + //.RX_BUFFER_CFG ( 6'd0), // + .RX_DEFER_RESET_BUF_EN ("TRUE"), // + .RXBUF_ADDR_MODE ("FULL"), // + .RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim + .RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), // + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), // + .RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), // + .RXBUF_THRESH_OVRD ("FALSE"), // + .RXBUF_THRESH_OVFLW (61), // + .RXBUF_THRESH_UNDFLW ( 4), // + //.RXBUFRESET_TIME ( 5'b00001), // + + //---------- TX Sync Attributes ---------------------------------------- + .TXPH_CFG (16'h0780), // + .TXPH_MONITOR_SEL ( 5'd0), // + .TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range + .TXDLY_CFG (16'h001F), // + .TXDLY_LCFG ( 9'h030), // + .TXDLY_TAP_CFG (16'd0), // + + .TXSYNC_OVRD (TXSYNC_OVRD), // + .TXSYNC_MULTILANE (TXSYNC_MULTILANE), // + .TXSYNC_SKIP_DA (1'b0), // + + //---------- RX Sync Attributes ---------------------------------------- + .RXPH_CFG (24'd0), // + .RXPH_MONITOR_SEL ( 5'd0), // + .RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range + .RXDLY_CFG (16'h001F), // + .RXDLY_LCFG ( 9'h030), // + .RXDLY_TAP_CFG (16'd0), // + .RX_DDI_SEL ( 6'd0), // + + .RXSYNC_OVRD (RXSYNC_OVRD), // + .RXSYNC_MULTILANE (RXSYNC_MULTILANE), // + .RXSYNC_SKIP_DA (1'b0), // + + //---------- Comma Alignment Attributes -------------------------------- + .ALIGN_COMMA_DOUBLE ("FALSE"), // + .ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe + .ALIGN_COMMA_WORD ( 1), // + .ALIGN_MCOMMA_DET ("TRUE"), // + .ALIGN_MCOMMA_VALUE (10'b1010000011), // + .ALIGN_PCOMMA_DET ("TRUE"), // + .ALIGN_PCOMMA_VALUE (10'b0101111100), // + .DEC_MCOMMA_DETECT ("TRUE"), // + .DEC_PCOMMA_DETECT ("TRUE"), // + .DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe + .SHOW_REALIGN_COMMA ("FALSE"), // PCIe + .RXSLIDE_AUTO_WAIT ( 7), // + .RXSLIDE_MODE ("PMA"), // PCIe + + //---------- Channel Bonding Attributes -------------------------------- + .CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe + .CHAN_BOND_MAX_SKEW ( 7), // + .CHAN_BOND_SEQ_LEN ( 4), // PCIe + .CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), // + .CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1 + .CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1 + .CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1 + .CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM + .CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe + .CHAN_BOND_SEQ_2_ENABLE (4'b1111), // + .CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2 + .CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2 + .CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2 + .CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM + .FTS_DESKEW_SEQ_ENABLE ( 4'b1111), // + .FTS_LANE_DESKEW_EN ("TRUE"), // PCIe + .FTS_LANE_DESKEW_CFG ( 4'b1111), // + + //---------- Clock Correction Attributes ------------------------------- + .CBCC_DATA_SOURCE_SEL ("DECODED"), // + .CLK_CORRECT_USE ("TRUE"), // + .CLK_COR_KEEP_IDLE ("TRUE"), // PCIe + .CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), // + .CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), // + .CLK_COR_PRECEDENCE ("TRUE"), // + .CLK_COR_REPEAT_WAIT ( 0), // + .CLK_COR_SEQ_LEN ( 1), // + .CLK_COR_SEQ_1_ENABLE ( 4'b1111), // + .CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP + .CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled + .CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled + .CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled + .CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled + .CLK_COR_SEQ_2_USE ("FALSE"), // + .CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled + .CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled + .CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled + .CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled + + //---------- 8b10b Attributes ------------------------------------------ + .RX_DISPERR_SEQ_MATCH ("TRUE"), // + + //---------- 64b/66b & 64b/67b Attributes ------------------------------ + .GEARBOX_MODE ( 3'd0), // + .TXGEARBOX_EN ("FALSE"), // + .RXGEARBOX_EN ("FALSE"), // + + //---------- PRBS & Loopback Attributes --------------------------------- + .LOOPBACK_CFG ( 1'd0), // Enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0] + .RXPRBS_ERR_LOOPBACK ( 1'd0), // + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), // + + //---------- OOB & SATA Attributes -------------------------------------- + .TXOOB_CFG ( 1'd1), // Filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7] + //.RXOOB_CFG ( 7'b0000110), // + .RXOOB_CLK_CFG (RXOOB_CLK_CFG), // + //.SAS_MAX_COM (64), // + //.SAS_MIN_COM (36), // + //.SATA_BURST_SEQ_LEN ( 4'b1111), // + //.SATA_BURST_VAL ( 3'b100), // + //.SATA_PLL_CFG ("VCO_3000MHZ"), // + //.SATA_EIDLE_VAL ( 3'b100), // + //.SATA_MAX_BURST ( 8), // + //.SATA_MAX_INIT (21), // + //.SATA_MAX_WAKE ( 7), // + //.SATA_MIN_BURST ( 4), // + //.SATA_MIN_INIT (12), // + //.SATA_MIN_WAKE ( 4), // + + //---------- MISC ------------------------------------------------------ + .DMONITOR_CFG (24'h000B01), // + .RX_DEBUG_CFG (14'h0000), // Optimized for IES + //.TST_RSV (32'd0), // + //.UCODEER_CLR ( 1'd0) // + + //---------- GTP ------------------------------------------------------- + //.ACJTAG_DEBUG_MODE (1'd0), // + //.ACJTAG_MODE (1'd0), // + //.ACJTAG_RESET (1'd0), // + //.ADAPT_CFG0 (20'd0), // + .CFOK_CFG (43'h490_0004_0E80), // Changed from 42 to 43-bits, Optimized for IES + .CFOK_CFG2 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES + .CFOK_CFG3 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES + .CFOK_CFG4 ( 1'd0), // GTP new, Optimized for IES + .CFOK_CFG5 ( 2'd0), // GTP new, Optimized for IES + .CFOK_CFG6 ( 4'd0) // GTP new, Optimized for IES + + ) + gtpe2_channel_i + ( + + //---------- Clock ----------------------------------------------------- + .PLL0CLK (GT_QPLLCLK), // + .PLL1CLK (1'd0), // + .PLL0REFCLK (GT_QPLLREFCLK), // + .PLL1REFCLK (1'd0), // + .TXUSRCLK (GT_TXUSRCLK), // + .RXUSRCLK (GT_RXUSRCLK), // + .TXUSRCLK2 (GT_TXUSRCLK2), // + .RXUSRCLK2 (GT_RXUSRCLK2), // + .TXSYSCLKSEL (GT_TXSYSCLKSEL), // + .RXSYSCLKSEL (GT_RXSYSCLKSEL), // + .TXOUTCLKSEL (txoutclksel), // + .RXOUTCLKSEL (rxoutclksel), // + .CLKRSVD0 (1'd0), // + .CLKRSVD1 (1'd0), // + + .TXOUTCLK (GT_TXOUTCLK), // + .RXOUTCLK (GT_RXOUTCLK), // + .TXOUTCLKFABRIC (), // + .RXOUTCLKFABRIC (), // + .TXOUTCLKPCS (), // + .RXOUTCLKPCS (), // + .RXCDRLOCK (GT_RXCDRLOCK), // + + //---------- Reset ----------------------------------------------------- + .TXUSERRDY (GT_TXUSERRDY), // + .RXUSERRDY (GT_RXUSERRDY), // + .CFGRESET (1'd0), // + .GTRESETSEL (1'd0), // + .RESETOVRD (GT_RESETOVRD), // + .GTTXRESET (GT_GTTXRESET), // + .GTRXRESET (GT_GTRXRESET), // + + .TXRESETDONE (GT_TXRESETDONE), // + .RXRESETDONE (GT_RXRESETDONE), // + + //---------- TX Data --------------------------------------------------- + .TXDATA (GT_TXDATA), // + .TXCHARISK (GT_TXDATAK), // + + .GTPTXP (GT_TXP), // GTP + .GTPTXN (GT_TXN), // GTP + + //---------- RX Data --------------------------------------------------- + .GTPRXP (GT_RXP), // GTP + .GTPRXN (GT_RXN), // GTP + + .RXDATA (rxdata[31:0]), // + .RXCHARISK (rxdatak[3:0]), // + + //---------- Command --------------------------------------------------- + .TXDETECTRX (GT_TXDETECTRX), // + .TXPDELECIDLEMODE ( 1'd0), // + .RXELECIDLEMODE ( 2'd0), // + .TXELECIDLE (GT_TXELECIDLE), // + .TXCHARDISPMODE ({3'd0, GT_TXCOMPLIANCE}), // Changed from 8 to 4-bits + .TXCHARDISPVAL ( 4'd0), // Changed from 8 to 4-bits + .TXPOLARITY ( 1'b0), // + .RXPOLARITY (GT_RXPOLARITY), // + .TXPD (GT_TXPOWERDOWN), // + .RXPD (GT_RXPOWERDOWN), // + .TXRATE (GT_TXRATE), // + .RXRATE (GT_RXRATE), // + .TXRATEMODE (1'b0), // + .RXRATEMODE (1'b0), // + + //---------- Electrical Command ---------------------------------------- + .TXMARGIN (GT_TXMARGIN), // + .TXSWING (GT_TXSWING), // + .TXDEEMPH (GT_TXDEEMPH), // + .TXINHIBIT (GT_TXINHIBIT), // + .TXBUFDIFFCTRL (3'b100), // + .TXDIFFCTRL (4'b1100), // Select 850mV + .TXPRECURSOR (GT_TXPRECURSOR), // + .TXPRECURSORINV (1'd0), // + .TXMAINCURSOR (GT_TXMAINCURSOR), // + .TXPOSTCURSOR (GT_TXPOSTCURSOR), // + .TXPOSTCURSORINV (1'd0), // + + //---------- Status ---------------------------------------------------- + .RXVALID (GT_RXVALID), // + .PHYSTATUS (GT_PHYSTATUS), // + .RXELECIDLE (GT_RXELECIDLE), // + .RXSTATUS (GT_RXSTATUS), // + .TXRATEDONE (GT_TXRATEDONE), // + .RXRATEDONE (GT_RXRATEDONE), // + + //---------- DRP ------------------------------------------------------- + .DRPCLK (GT_DRPCLK), // + .DRPADDR (GT_DRPADDR), // + .DRPEN (GT_DRPEN), // + .DRPDI (GT_DRPDI), // + .DRPWE (GT_DRPWE), // + + .DRPDO (GT_DRPDO), // + .DRPRDY (GT_DRPRDY), // + + //---------- PMA ------------------------------------------------------- + .TXPMARESET (GT_TXPMARESET), // + .RXPMARESET (GT_RXPMARESET), // + .RXLPMRESET ( 1'd0), // GTP new + .RXLPMOSINTNTRLEN ( 1'd0), // GTP new + .RXLPMHFHOLD ( 1'd0), // + .RXLPMHFOVRDEN ( 1'd0), // + .RXLPMLFHOLD ( 1'd0), // + .RXLPMLFOVRDEN ( 1'd0), // + .PMARSVDIN0 ( 1'd0), // GTP new + .PMARSVDIN1 ( 1'd0), // GTP new + .PMARSVDIN2 ( 1'd0), // GTP new + .PMARSVDIN3 ( 1'd0), // GTP new + .PMARSVDIN4 ( 1'd0), // GTP new + .GTRSVD (16'd0), // + + .PMARSVDOUT0 (), // GTP new + .PMARSVDOUT1 (), // GTP new + .DMONITOROUT (dmonitorout), // GTP 15-bits + + //---------- PCS ------------------------------------------------------- + .TXPCSRESET (GT_TXPCSRESET), // + .RXPCSRESET (GT_RXPCSRESET), // + .PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async + + .PCSRSVDOUT (), // + + //---------- CDR ------------------------------------------------------- + .RXCDRRESET (GT_RXCDRRESET), // + .RXCDRRESETRSV (1'd0), // + .RXCDRFREQRESET (GT_RXCDRFREQRESET), // + .RXCDRHOLD (1'b0), // + .RXCDROVRDEN (1'd0), // + + //---------- PI -------------------------------------------------------- + .TXPIPPMEN (1'd0), // + .TXPIPPMOVRDEN (1'd0), // + .TXPIPPMPD (1'd0), // + .TXPIPPMSEL (1'd0), // + .TXPIPPMSTEPSIZE (5'd0), // + .TXPISOPD (1'd0), // GTP new + + //---------- DFE ------------------------------------------------------- + .RXDFEXYDEN (1'd0), // + + //---------- OS -------------------------------------------------------- + .RXOSHOLD (1'd0), // Optimized for IES + .RXOSOVRDEN (1'd0), // Optimized for IES + .RXOSINTEN (1'd1), // Optimized for IES + .RXOSINTHOLD (1'd0), // Optimized for IES + .RXOSINTNTRLEN (1'd0), // Optimized for IES + .RXOSINTOVRDEN (1'd0), // Optimized for IES + .RXOSINTPD (1'd0), // GTP new, Optimized for IES + .RXOSINTSTROBE (1'd0), // Optimized for IES + .RXOSINTTESTOVRDEN (1'd0), // Optimized for IES + .RXOSINTCFG (4'b0010), // Optimized for IES + .RXOSINTID0 (4'd0), // Optimized for IES + + .RXOSINTDONE (), // + .RXOSINTSTARTED (), // + .RXOSINTSTROBEDONE (), // + .RXOSINTSTROBESTARTED (), // + + //---------- Eye Scan -------------------------------------------------- + .EYESCANRESET (GT_EYESCANRESET), // + .EYESCANMODE (1'd0), // + .EYESCANTRIGGER (1'b0), // + + .EYESCANDATAERROR (GT_EYESCANDATAERROR), // + + //---------- TX Buffer ------------------------------------------------- + .TXBUFSTATUS (), // + + //---------- RX Buffer ------------------------------------------------- + .RXBUFRESET (GT_RXBUFRESET), // + + .RXBUFSTATUS (GT_RXBUFSTATUS), // + + //---------- TX Sync --------------------------------------------------- + .TXPHDLYRESET (GT_TXPHDLYRESET), // + .TXPHDLYTSTCLK (1'd0), // + .TXPHALIGN (GT_TXPHALIGN), // + .TXPHALIGNEN (GT_TXPHALIGNEN), // + .TXPHDLYPD (1'd0), // + .TXPHINIT (GT_TXPHINIT), // + .TXPHOVRDEN (1'd0), // + .TXDLYBYPASS (GT_TXDLYBYPASS), // + .TXDLYSRESET (GT_TXDLYSRESET), // + .TXDLYEN (GT_TXDLYEN), // + .TXDLYOVRDEN (1'd0), // + .TXDLYHOLD (1'd0), // + .TXDLYUPDOWN (1'd0), // + + .TXPHALIGNDONE (GT_TXPHALIGNDONE), // + .TXPHINITDONE (GT_TXPHINITDONE), // + .TXDLYSRESETDONE (GT_TXDLYSRESETDONE), // + + .TXSYNCMODE (GT_TXSYNCMODE), // + .TXSYNCIN (GT_TXSYNCIN), // + .TXSYNCALLIN (GT_TXSYNCALLIN), // + + .TXSYNCDONE (GT_TXSYNCDONE), // + .TXSYNCOUT (GT_TXSYNCOUT), // + + //---------- RX Sync --------------------------------------------------- + .RXPHDLYRESET (1'd0), // + .RXPHALIGN (GT_RXPHALIGN), // + .RXPHALIGNEN (GT_RXPHALIGNEN), // + .RXPHDLYPD (1'd0), // + .RXPHOVRDEN (1'd0), // + .RXDLYBYPASS (GT_RXDLYBYPASS), // + .RXDLYSRESET (GT_RXDLYSRESET), // + .RXDLYEN (GT_RXDLYEN), // + .RXDLYOVRDEN (1'd0), // + .RXDDIEN (GT_RXDDIEN), // + + .RXPHALIGNDONE (GT_RXPHALIGNDONE), // + .RXPHMONITOR (), // + .RXPHSLIPMONITOR (), // + .RXDLYSRESETDONE (GT_RXDLYSRESETDONE), // + + .RXSYNCMODE (GT_RXSYNCMODE), // + .RXSYNCIN (GT_RXSYNCIN), // + .RXSYNCALLIN (GT_RXSYNCALLIN), // + + .RXSYNCDONE (GT_RXSYNCDONE), // + .RXSYNCOUT (GT_RXSYNCOUT), // + + //---------- Comma Alignment ------------------------------------------- + .RXCOMMADETEN (1'd1), // + .RXMCOMMAALIGNEN (1'd1), // No Gen3 support in GTP + .RXPCOMMAALIGNEN (1'd1), // No Gen3 support in GTP + .RXSLIDE (GT_RXSLIDE), // + .RXCOMMADET (GT_RXCOMMADET), // + .RXCHARISCOMMA (rxchariscomma[3:0]), // + .RXBYTEISALIGNED (GT_RXBYTEISALIGNED), // + .RXBYTEREALIGN (GT_RXBYTEREALIGN), // + + //---------- Channel Bonding ------------------------------------------- + .RXCHBONDEN (GT_RXCHBONDEN), // + .RXCHBONDI (GT_RXCHBONDI[3:0]), // + .RXCHBONDLEVEL (GT_RXCHBONDLEVEL), // + .RXCHBONDMASTER (GT_RXCHBONDMASTER), // + .RXCHBONDSLAVE (GT_RXCHBONDSLAVE), // + + .RXCHANBONDSEQ (), // + .RXCHANISALIGNED (GT_RXCHANISALIGNED), // + .RXCHANREALIGN (), // + .RXCHBONDO (GT_RXCHBONDO[3:0]), // + + //---------- Clock Correction ----------------------------------------- + .RXCLKCORCNT (), // + + //---------- 8b10b ----------------------------------------------------- + .TX8B10BBYPASS (4'd0), // + .TX8B10BEN (1'b1), // No Gen3 support in GTP + .RX8B10BEN (1'b1), // No Gen3 support in GTP + + .RXDISPERR (GT_RXDISPERR[3:0]), // + .RXNOTINTABLE (GT_RXNOTINTABLE[3:0]), // + + //---------- 64b/66b & 64b/67b ----------------------------------------- + .TXHEADER (3'd0), // + .TXSEQUENCE (7'd0), // + .TXSTARTSEQ (1'd0), // + .RXGEARBOXSLIP (1'd0), // + + .TXGEARBOXREADY (), // + .RXDATAVALID (), // + .RXHEADER (), // + .RXHEADERVALID (), // + .RXSTARTOFSEQ (), // + + //---------- PRBS/Loopback --------------------------------------------- + .TXPRBSSEL (GT_TXPRBSSEL), // + .RXPRBSSEL (GT_RXPRBSSEL), // + .TXPRBSFORCEERR (GT_TXPRBSFORCEERR), // + .RXPRBSCNTRESET (GT_RXPRBSCNTRESET), // + .LOOPBACK (GT_LOOPBACK), // + + .RXPRBSERR (GT_RXPRBSERR), // + + //---------- OOB ------------------------------------------------------- + .SIGVALIDCLK (GT_OOBCLK), // Optimized for debug + .TXCOMINIT (1'd0), // + .TXCOMSAS (1'd0), // + .TXCOMWAKE (1'd0), // + .RXOOBRESET (1'd0), // + + .TXCOMFINISH (), // + .RXCOMINITDET (), // + .RXCOMSASDET (), // + .RXCOMWAKEDET (), // + + //---------- MISC ------------------------------------------------------ + .SETERRSTATUS ( 1'd0), // + .TXDIFFPD ( 1'd0), // + .TSTIN (20'hFFFFF), // + + //---------- GTP ------------------------------------------------------- + .RXADAPTSELTEST (14'd0), // + .DMONFIFORESET ( 1'd0), // + .DMONITORCLK (dmonitorclk), // + .RXOSCALRESET ( 1'd0), // + + .RXPMARESETDONE (GT_RXPMARESETDONE), // GTP + .TXPMARESETDONE () // + + ); + + assign GT_CPLLLOCK = 1'b0; + + end + +else if (PCIE_GT_DEVICE == "GTH") + + begin : gth_channel + + //---------- GTH Channel Module -------------------------------------------- + GTHE2_CHANNEL # + ( + + //---------- Simulation Attributes ------------------------------------- + .SIM_CPLLREFCLK_SEL (3'b001), // + .SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), // + .SIM_RECEIVER_DETECT_PASS ("TRUE"), // + .SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), // + .SIM_VERSION ("2.0"), // + + //---------- Clock Attributes ------------------------------------------ + .CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), // + .CPLL_FBDIV_45 (CPLL_FBDIV_45), // + .CPLL_FBDIV (CPLL_FBDIV), // + .TXOUT_DIV (OUT_DIV), // + .RXOUT_DIV (OUT_DIV), // + .TX_CLK25_DIV (CLK25_DIV), // + .RX_CLK25_DIV (CLK25_DIV), // + .TX_CLKMUX_PD ( 1'b1), // GTH + .RX_CLKMUX_PD ( 1'b1), // GTH + .TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer + .RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer + .OUTREFCLK_SEL_INV ( 2'b11), // + .CPLL_CFG (29'h00A407CC), // Changed from 24 to 29-bits, Optimized for PCIe PLL BW + .CPLL_INIT_CFG (24'h00001E), // Optimized for IES + .CPLL_LOCK_CFG (16'h01E8), // Optimized for IES + //.USE_PCS_CLK_PHASE_SEL ( 1'd0) // GTH new + + //---------- Reset Attributes ------------------------------------------ + .TXPCSRESET_TIME (5'b00001), // + .RXPCSRESET_TIME (5'b00001), // + .TXPMARESET_TIME (5'b00011), // + .RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP + //.RXISCANRESET_TIME (5'b00001), // + //.RESET_POWERSAVE_DISABLE ( 1'd0), // GTH new + + //---------- TX Data Attributes ---------------------------------------- + .TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2 + .TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2 + + //---------- RX Data Attributes ---------------------------------------- + .RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2 + .RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2 + + //---------- Command Attributes ---------------------------------------- + .TX_RXDETECT_CFG (TX_RXDETECT_CFG), // + .TX_RXDETECT_PRECHARGE_TIME (17'h00001), // GTH new, Optimized for sim + .TX_RXDETECT_REF ( 3'b011), // + .RX_CM_SEL ( 2'b11), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable, optimized for silicon + .RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for silicon + .TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4) + .TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim + //.PD_TRANS_TIME_FROM_P2 (12'h03C), // + .PD_TRANS_TIME_NONE_P2 ( 8'h09), // Optimized for sim + //.PD_TRANS_TIME_TO_P2 ( 8'h64), // + //.TRANS_TIME_RATE ( 8'h0E), // + + //---------- Electrical Command Attributes ----------------------------- + .TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3 + .TX_DEEMPH0 ( 6'b010100), // 6.0 dB, optimized for compliance, changed from 5 to 6-bits + .TX_DEEMPH1 ( 6'b001011), // 3.5 dB, optimized for compliance, changed from 5 to 6-bits + .TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV + .TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV + .TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV + .TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV + .TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV + .TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV + .TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV + .TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV + .TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV + .TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV + .TX_MAINCURSOR_SEL ( 1'b0), // + .TX_QPI_STATUS_EN ( 1'b0), // + + //---------- Status Attributes ----------------------------------------- + .RX_SIG_VALID_DLY (4), // Optimized for sim + + //---------- DRP Attributes -------------------------------------------- + + //---------- PCS Attributes -------------------------------------------- + .PCS_PCIE_EN ("TRUE"), // PCIe + .PCS_RSVD_ATTR (48'h0000_0000_0140), // [8] : 1 = OOB power-up, [6] : 1 = DMON enable, Optimized for IES + + //---------- PMA Attributes -------------------------------------------- + .PMA_RSV (32'h00000080), // Optimized for IES + .PMA_RSV2 (32'h1C00000A), // Changed from 16 to 32-bits, Optimized for IES + //.PMA_RSV3 ( 2'h0), // + .PMA_RSV4 (15'h0008), // GTH new, Optimized for IES + //.PMA_RSV5 ( 4'h00), // GTH new + .RX_BIAS_CFG (24'h0C0010), // Changed from 12 to 24-bits, Optimized for IES + .TERM_RCAL_CFG (15'b100001000010000), // Changed from 5 to 15-bits, Optimized for IES + .TERM_RCAL_OVRD ( 3'b000), // Changed from 1 to 3-bits, Optimized for IES + + //---------- TX PI ----------------------------------------------------- + //.TXPI_CFG0 ( 2'd0), // GTH new + //.TXPI_CFG1 ( 2'd0), // GTH new + //.TXPI_CFG2 ( 2'd0), // GTH new + //.TXPI_CFG3 ( 1'd0), // GTH new + //.TXPI_CFG4 ( 1'd0), // GTH new + //.TXPI_CFG5 ( 3'b100), // GTH new + //.TXPI_GREY_SEL ( 1'd0), // GTH new + //.TXPI_INVSTROBE_SEL ( 1'd0), // GTH new + //.TXPI_PPMCLK_SEL ("TXUSRCLK2"), // GTH new + //.TXPI_PPM_CFG ( 8'd0), // GTH new + //.TXPI_SYNFREQ_PPM ( 3'd0), // GTH new + + //---------- RX PI ----------------------------------------------------- + .RXPI_CFG0 (2'b00), // GTH new + .RXPI_CFG1 (2'b11), // GTH new + .RXPI_CFG2 (2'b11), // GTH new + .RXPI_CFG3 (2'b11), // GTH new + .RXPI_CFG4 (1'b0), // GTH new + .RXPI_CFG5 (1'b0), // GTH new + .RXPI_CFG6 (3'b100), // GTH new + + //---------- CDR Attributes -------------------------------------------- + .RXCDR_CFG (RXCDR_CFG_GTH), // + //.RXCDR_CFG (83'h0_0011_07FE_4060_0104_1010), // A. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, default, converted from GTX GES VnC,(2 Gen1) + //.RXCDR_CFG (83'h0_0011_07FE_4060_2104_1010), // B. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, default, converted from GTX GES VnC,(2 Gen1) + //.RXCDR_CFG (83'h0_0011_07FE_2060_0104_1010), // C. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, converted from GTX GES recommended, (3 Gen1) + //.RXCDR_CFG (83'h0_0011_07FE_2060_2104_1010), // D. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, converted from GTX GES recommended, (3 Gen1) + //.RXCDR_CFG (83'h0_0001_07FE_1060_0110_1010), // E. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, default, (3 Gen2) + //.RXCDR_CFG (83'h0_0001_07FE_1060_2110_1010), // F. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, default, (3 Gen2) + //.RXCDR_CFG (83'h0_0011_07FE_1060_0110_1010), // G. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, converted from GTX GES recommended, (3 Gen2) + //.RXCDR_CFG (83'h0_0011_07FE_1060_2110_1010), // H. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, converted from GTX GES recommended, (2 Gen1) + .RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001) + .RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2 + .RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3 + .RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3 + //.RXCDRFREQRESET_TIME ( 5'b00001), // optimized for IES + //.RXCDRPHRESET_TIME ( 5'b00001), // optimized for IES + + //---------- LPM Attributes -------------------------------------------- + .RXLPM_HF_CFG (14'h0200), // Optimized for IES + .RXLPM_LF_CFG (18'h09000), // Changed from 14 to 18-bits, Optimized for IES + + //---------- DFE Attributes -------------------------------------------- + .RXDFELPMRESET_TIME ( 7'h0F), // Optimized for IES + .RX_DFE_AGC_CFG0 ( 2'h0), // GTH new, optimized for IES + .RX_DFE_AGC_CFG1 ( 3'h4), // GTH new, optimized for IES, DFE + .RX_DFE_AGC_CFG2 ( 4'h0), // GTH new, optimized for IES + .RX_DFE_AGC_OVRDEN ( 1'h1), // GTH new, optimized for IES + .RX_DFE_GAIN_CFG (23'h0020C0), // Optimized for IES + .RX_DFE_H2_CFG (12'h000), // Optimized for IES + .RX_DFE_H3_CFG (12'h040), // Optimized for IES + .RX_DFE_H4_CFG (11'h0E0), // Optimized for IES + .RX_DFE_H5_CFG (11'h0E0), // Optimized for IES + .RX_DFE_H6_CFG (11'h020), // GTH new, optimized for IES + .RX_DFE_H7_CFG (11'h020), // GTH new, optimized for IES + .RX_DFE_KL_CFG (33'h000000310), // Changed from 13 to 33-bits, optimized for IES + .RX_DFE_KL_LPM_KH_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE + .RX_DFE_KL_LPM_KH_CFG1 ( 3'h2), // GTH new, optimized for IES + .RX_DFE_KL_LPM_KH_CFG2 ( 4'h2), // GTH new, optimized for IES + .RX_DFE_KL_LPM_KH_OVRDEN ( 1'h1), // GTH new, optimized for IES + .RX_DFE_KL_LPM_KL_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE + .RX_DFE_KL_LPM_KL_CFG1 ( 3'h2), // GTH new, optimized for IES + .RX_DFE_KL_LPM_KL_CFG2 ( 4'h2), // GTH new, optimized for IES + .RX_DFE_KL_LPM_KL_OVRDEN ( 1'b1), // GTH new, optimized for IES + .RX_DFE_LPM_CFG (16'h0080), // Optimized for IES + .RX_DFELPM_CFG0 ( 4'h6), // GTH new, optimized for IES + .RX_DFELPM_CFG1 ( 4'h0), // GTH new, optimized for IES + .RX_DFELPM_KLKH_AGC_STUP_EN ( 1'h1), // GTH new, optimized for IES + .RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'h1), // PCIe use mode + .RX_DFE_ST_CFG (54'h00_C100_000C_003F), // GTH new, optimized for IES + .RX_DFE_UT_CFG (17'h03800), // Optimized for IES + .RX_DFE_VP_CFG (17'h03AA3), // Optimized for IES + + //---------- OS Attributes --------------------------------------------- + .RX_OS_CFG (13'h0080), // Optimized for IES + .A_RXOSCALRESET ( 1'd0), // GTH new, optimized for IES + .RXOSCALRESET_TIME ( 5'b00011), // GTH new, optimized for IES + .RXOSCALRESET_TIMEOUT ( 5'b00000), // GTH new, disable timeout, optimized for IES + + //---------- Eye Scan Attributes --------------------------------------- + //.ES_CLK_PHASE_SEL ( 1'd0), // GTH new + //.ES_CONTROL ( 6'd0), // + //.ES_ERRDET_EN ("FALSE"), // + .ES_EYE_SCAN_EN ("FALSE"), // Optimized for IES + .ES_HORZ_OFFSET (12'h000), // Optimized for IES + //.ES_PMA_CFG (10'd0), // + //.ES_PRESCALE ( 5'd0), // + //.ES_QUAL_MASK (80'd0), // + //.ES_QUALIFIER (80'd0), // + //.ES_SDATA_MASK (80'd0), // + //.ES_VERT_OFFSET ( 9'd0), // + + //---------- TX Buffer Attributes -------------------------------------- + .TXBUF_EN (PCIE_TXBUF_EN), // + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), // + + //---------- RX Buffer Attributes -------------------------------------- + .RXBUF_EN ("TRUE"), // + //.RX_BUFFER_CFG ( 6'd0), // + .RX_DEFER_RESET_BUF_EN ("TRUE"), // + .RXBUF_ADDR_MODE ("FULL"), // + .RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim + .RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), // + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), // + .RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), // + .RXBUF_THRESH_OVRD ("FALSE"), // + .RXBUF_THRESH_OVFLW (61), // + .RXBUF_THRESH_UNDFLW ( 4), // + //.RXBUFRESET_TIME ( 5'b00001), // + + //---------- TX Sync Attributes ---------------------------------------- + //.TXPH_CFG (16'h0780), // + .TXPH_MONITOR_SEL ( 5'd0), // + //.TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range + //.TXDLY_CFG (16'h001F), // + //.TXDLY_LCFG ( 9'h030), // + //.TXDLY_TAP_CFG (16'd0), // + + .TXSYNC_OVRD (TXSYNC_OVRD), // GTH new + .TXSYNC_MULTILANE (TXSYNC_MULTILANE), // GTH new + .TXSYNC_SKIP_DA (1'b0), // GTH new + + //---------- RX Sync Attributes ---------------------------------------- + //.RXPH_CFG (24'd0), // + .RXPH_MONITOR_SEL ( 5'd0), // + .RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range + //.RXDLY_CFG (16'h001F), // + //.RXDLY_LCFG ( 9'h030), // + //.RXDLY_TAP_CFG (16'd0), // + .RX_DDI_SEL ( 6'd0), // + + .RXSYNC_OVRD (RXSYNC_OVRD), // GTH new + .RXSYNC_MULTILANE (RXSYNC_MULTILANE), // GTH new + .RXSYNC_SKIP_DA (1'b0), // GTH new + + //---------- Comma Alignment Attributes -------------------------------- + .ALIGN_COMMA_DOUBLE ("FALSE"), // + .ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe + .ALIGN_COMMA_WORD ( 1), // + .ALIGN_MCOMMA_DET ("TRUE"), // + .ALIGN_MCOMMA_VALUE (10'b1010000011), // + .ALIGN_PCOMMA_DET ("TRUE"), // + .ALIGN_PCOMMA_VALUE (10'b0101111100), // + .DEC_MCOMMA_DETECT ("TRUE"), // + .DEC_PCOMMA_DETECT ("TRUE"), // + .DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe + .SHOW_REALIGN_COMMA ("FALSE"), // PCIe + .RXSLIDE_AUTO_WAIT ( 7), // + .RXSLIDE_MODE ("PMA"), // PCIe + + //---------- Channel Bonding Attributes -------------------------------- + .CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe + .CHAN_BOND_MAX_SKEW ( 7), // + .CHAN_BOND_SEQ_LEN ( 4), // PCIe + .CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), // + .CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1 + .CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1 + .CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1 + .CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM + .CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe + .CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), // + .CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2 + .CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2 + .CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2 + .CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM + .FTS_DESKEW_SEQ_ENABLE ( 4'b1111), // + .FTS_LANE_DESKEW_EN ("TRUE"), // PCIe + .FTS_LANE_DESKEW_CFG ( 4'b1111), // + + //---------- Clock Correction Attributes ------------------------------- + .CBCC_DATA_SOURCE_SEL ("DECODED"), // + .CLK_CORRECT_USE ("TRUE"), // + .CLK_COR_KEEP_IDLE ("TRUE"), // PCIe + .CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), // + .CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), // + .CLK_COR_PRECEDENCE ("TRUE"), // + .CLK_COR_REPEAT_WAIT ( 0), // + .CLK_COR_SEQ_LEN ( 1), // + .CLK_COR_SEQ_1_ENABLE ( 4'b1111), // + .CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP + .CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled + .CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled + .CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled + .CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled + .CLK_COR_SEQ_2_USE ("FALSE"), // + .CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled + .CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled + .CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled + .CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled + + //---------- 8b10b Attributes ------------------------------------------ + .RX_DISPERR_SEQ_MATCH ("TRUE"), // + + //---------- 64b/66b & 64b/67b Attributes ------------------------------ + .GEARBOX_MODE (3'd0), // + .TXGEARBOX_EN ("FALSE"), // + .RXGEARBOX_EN ("FALSE"), // + + //---------- PRBS & Loopback Attributes -------------------------------- + .LOOPBACK_CFG ( 1'd1), // GTH new, enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0] + .RXPRBS_ERR_LOOPBACK ( 1'd0), // + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), // + + //---------- OOB & SATA Attributes ------------------------------------- + .TXOOB_CFG ( 1'd1), // GTH new, filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7] + //.RXOOB_CFG ( 7'b0000110), // + .RXOOB_CLK_CFG (RXOOB_CLK_CFG), // GTH new + //.SAS_MAX_COM (64), // + //.SAS_MIN_COM (36), // + //.SATA_BURST_SEQ_LEN ( 4'b1111), // + //.SATA_BURST_VAL ( 3'b100), // + //.SATA_CPLL_CFG ("VCO_3000MHZ"), // + //.SATA_EIDLE_VAL ( 3'b100), // + //.SATA_MAX_BURST ( 8), // + //.SATA_MAX_INIT (21), // + //.SATA_MAX_WAKE ( 7), // + //.SATA_MIN_BURST ( 4), // + //.SATA_MIN_INIT (12), // + //.SATA_MIN_WAKE ( 4), // + + //---------- MISC ------------------------------------------------------ + .DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 1011 = AGC + //.DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 0000 = CDR FSM + .RX_DEBUG_CFG (14'b00000011000000), // Changed from 12 to 14-bits, optimized for IES + //.TST_RSV (32'd0), // + //.UCODEER_CLR ( 1'd0), // + + //---------- GTH ------------------------------------------------------- + //.ACJTAG_DEBUG_MODE ( 1'd0), // GTH new + //.ACJTAG_MODE ( 1'd0), // GTH new + //.ACJTAG_RESET ( 1'd0), // GTH new + .ADAPT_CFG0 (20'h00C10), // GTH new, optimized for IES + .CFOK_CFG (42'h248_0004_0E80), // GTH new, optimized for IES, [8] : 1 = Skip CFOK + .CFOK_CFG2 ( 6'b100000), // GTH new, optimized for IES + .CFOK_CFG3 ( 6'b100000) // GTH new, optimized for IES + + ) + gthe2_channel_i + ( + + //---------- Clock ----------------------------------------------------- + .GTGREFCLK (1'd0), // + .GTREFCLK0 (GT_GTREFCLK0), // + .GTREFCLK1 (1'd0), // + .GTNORTHREFCLK0 (1'd0), // + .GTNORTHREFCLK1 (1'd0), // + .GTSOUTHREFCLK0 (1'd0), // + .GTSOUTHREFCLK1 (1'd0), // + .QPLLCLK (GT_QPLLCLK), // + .QPLLREFCLK (GT_QPLLREFCLK), // + .TXUSRCLK (GT_TXUSRCLK), // + .RXUSRCLK (GT_RXUSRCLK), // + .TXUSRCLK2 (GT_TXUSRCLK2), // + .RXUSRCLK2 (GT_RXUSRCLK2), // + .TXSYSCLKSEL (GT_TXSYSCLKSEL), // + .RXSYSCLKSEL (GT_RXSYSCLKSEL), // + .TXOUTCLKSEL (txoutclksel), // + .RXOUTCLKSEL (rxoutclksel), // + .CPLLREFCLKSEL (3'd1), // + .CPLLLOCKDETCLK (1'd0), // + .CPLLLOCKEN (1'd1), // + .CLKRSVD0 (1'd0), // GTH + .CLKRSVD1 (1'd0), // GTH + + .TXOUTCLK (GT_TXOUTCLK), // + .RXOUTCLK (GT_RXOUTCLK), // + .TXOUTCLKFABRIC (), // + .RXOUTCLKFABRIC (), // + .TXOUTCLKPCS (), // + .RXOUTCLKPCS (), // + .CPLLLOCK (GT_CPLLLOCK), // + .CPLLREFCLKLOST (), // + .CPLLFBCLKLOST (), // + .RXCDRLOCK (GT_RXCDRLOCK), // + .GTREFCLKMONITOR (), // + + //---------- Reset ----------------------------------------------------- + .CPLLPD (cpllpd | GT_CPLLPD), // + .CPLLRESET (cpllrst | GT_CPLLRESET), // + .TXUSERRDY (GT_TXUSERRDY), // + .RXUSERRDY (GT_RXUSERRDY), // + .CFGRESET (1'd0), // + .GTRESETSEL (1'd0), // + .RESETOVRD (GT_RESETOVRD), // + .GTTXRESET (GT_GTTXRESET), // + .GTRXRESET (GT_GTRXRESET), // + + .TXRESETDONE (GT_TXRESETDONE), // + .RXRESETDONE (GT_RXRESETDONE), // + + //---------- TX Data --------------------------------------------------- + .TXDATA ({32'd0, GT_TXDATA}), // + .TXCHARISK ({ 4'd0, GT_TXDATAK}), // + + .GTHTXP (GT_TXP), // GTH + .GTHTXN (GT_TXN), // GTH + + //---------- RX Data --------------------------------------------------- + .GTHRXP (GT_RXP), // GTH + .GTHRXN (GT_RXN), // GTH + + .RXDATA (rxdata), // + .RXCHARISK (rxdatak), // + + //---------- Command --------------------------------------------------- + .TXDETECTRX (GT_TXDETECTRX), // + .TXPDELECIDLEMODE ( 1'd0), // + .RXELECIDLEMODE ( 2'd0), // + .TXELECIDLE (GT_TXELECIDLE), // + .TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), // + .TXCHARDISPVAL ( 8'd0), // + .TXPOLARITY ( 1'b0), // + .RXPOLARITY (GT_RXPOLARITY), // + .TXPD (GT_TXPOWERDOWN), // + .RXPD (GT_RXPOWERDOWN), // + .TXRATE (GT_TXRATE), // + .RXRATE (GT_RXRATE), // + .TXRATEMODE (1'd0), // GTH + .RXRATEMODE (1'd0), // GTH + + //---------- Electrical Command ---------------------------------------- + .TXMARGIN (GT_TXMARGIN), // + .TXSWING (GT_TXSWING), // + .TXDEEMPH (GT_TXDEEMPH), // + .TXINHIBIT (GT_TXINHIBIT), // + .TXBUFDIFFCTRL (3'b100), // + .TXDIFFCTRL (4'b1111), // Select 850mV + .TXPRECURSOR (GT_TXPRECURSOR), // + .TXPRECURSORINV (1'd0), // + .TXMAINCURSOR (GT_TXMAINCURSOR), // + .TXPOSTCURSOR (GT_TXPOSTCURSOR), // + .TXPOSTCURSORINV (1'd0), // + + //---------- Status ---------------------------------------------------- + .RXVALID (GT_RXVALID), // + .PHYSTATUS (GT_PHYSTATUS), // + .RXELECIDLE (GT_RXELECIDLE), // + .RXSTATUS (GT_RXSTATUS), // + .TXRATEDONE (GT_TXRATEDONE), // + .RXRATEDONE (GT_RXRATEDONE), // + + //---------- DRP ------------------------------------------------------- + .DRPCLK (GT_DRPCLK), // + .DRPADDR (GT_DRPADDR), // + .DRPEN (GT_DRPEN), // + .DRPDI (GT_DRPDI), // + .DRPWE (GT_DRPWE), // + + .DRPDO (GT_DRPDO), // + .DRPRDY (GT_DRPRDY), // + + //---------- PMA ------------------------------------------------------- + .TXPMARESET (GT_TXPMARESET), // + .RXPMARESET (GT_RXPMARESET), // + .RXLPMEN (rxlpmen), // *** + .RXLPMHFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence + .RXLPMHFOVRDEN ( 1'd0), // + .RXLPMLFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence + .RXLPMLFKLOVRDEN ( 1'd0), // + .TXQPIBIASEN ( 1'd0), // + .TXQPISTRONGPDOWN ( 1'd0), // + .TXQPIWEAKPUP ( 1'd0), // + .RXQPIEN ( 1'd0), // Optimized for IES + .PMARSVDIN ( 5'd0), // + .GTRSVD (16'd0), // + + .TXQPISENP (), // + .TXQPISENN (), // + .RXQPISENP (), // + .RXQPISENN (), // + .DMONITOROUT (dmonitorout), // GTH 15-bits. + + //---------- PCS ------------------------------------------------------- + .TXPCSRESET (GT_TXPCSRESET), // + .RXPCSRESET (GT_RXPCSRESET), // + .PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async + .PCSRSVDIN2 ( 5'd0), // + + .PCSRSVDOUT (), // + + //---------- CDR ------------------------------------------------------- + .RXCDRRESET (GT_RXCDRRESET), // + .RXCDRRESETRSV (1'd0), // + .RXCDRFREQRESET (GT_RXCDRFREQRESET), // + .RXCDRHOLD (1'b0), // + .RXCDROVRDEN (1'd0), // + + //---------- PI -------------------------------------------------------- + .TXPIPPMEN (1'd0), // GTH new + .TXPIPPMOVRDEN (1'd0), // GTH new + .TXPIPPMPD (1'd0), // GTH new + .TXPIPPMSEL (1'd0), // GTH new + .TXPIPPMSTEPSIZE (5'd0), // GTH new + + //---------- DFE ------------------------------------------------------- + .RXDFELPMRESET (GT_RXDFELPMRESET), // + .RXDFEAGCTRL (5'b10000), // GTH new, optimized for IES + .RXDFECM1EN (1'd0), // + .RXDFEVSEN (1'd0), // + .RXDFETAP2HOLD (1'd0), // + .RXDFETAP2OVRDEN (1'd0), // + .RXDFETAP3HOLD (1'd0), // + .RXDFETAP3OVRDEN (1'd0), // + .RXDFETAP4HOLD (1'd0), // + .RXDFETAP4OVRDEN (1'd0), // + .RXDFETAP5HOLD (1'd0), // + .RXDFETAP5OVRDEN (1'd0), // + .RXDFETAP6HOLD (1'd0), // GTH new + .RXDFETAP6OVRDEN (1'd0), // GTH new + .RXDFETAP7HOLD (1'd0), // GTH new + .RXDFETAP7OVRDEN (1'd0), // GTH new + .RXDFEAGCHOLD (GT_RX_CONVERGE), // Set to 1 after convergence + .RXDFEAGCOVRDEN (rxlpmen), // + .RXDFELFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence + .RXDFELFOVRDEN (1'd0), // + .RXDFEUTHOLD (1'd0), // + .RXDFEUTOVRDEN (1'd0), // + .RXDFEVPHOLD (1'd0), // + .RXDFEVPOVRDEN (1'd0), // + .RXDFEXYDEN (1'd1), // Optimized for IES + .RXMONITORSEL (2'd0), // + .RXDFESLIDETAP (5'd0), // GTH new + .RXDFESLIDETAPID (6'd0), // GTH new + .RXDFESLIDETAPHOLD (1'd0), // GTH new + .RXDFESLIDETAPOVRDEN (1'd0), // GTH new + .RXDFESLIDETAPADAPTEN (1'd0), // GTH new + .RXDFESLIDETAPINITOVRDEN (1'd0), // GTH new + .RXDFESLIDETAPONLYADAPTEN (1'd0), // GTH new + .RXDFESLIDETAPSTROBE (1'd0), // GTH new + + .RXMONITOROUT (), // + .RXDFESLIDETAPSTARTED (), // GTH new + .RXDFESLIDETAPSTROBEDONE (), // GTH new + .RXDFESLIDETAPSTROBESTARTED (), // GTH new + .RXDFESTADAPTDONE (), // GTH new + + //---------- OS -------------------------------------------------------- + .RXOSHOLD (1'd0), // optimized for IES + .RXOSOVRDEN (1'd0), // optimized for IES + .RXOSINTEN (1'd1), // GTH new, optimized for IES + .RXOSINTHOLD (1'd0), // GTH new, optimized for IES + .RXOSINTNTRLEN (1'd0), // GTH new, optimized for IES + .RXOSINTOVRDEN (1'd0), // GTH new, optimized for IES + .RXOSINTSTROBE (1'd0), // GTH new, optimized for IES + .RXOSINTTESTOVRDEN (1'd0), // GTH new, optimized for IES + .RXOSINTCFG (4'b0110), // GTH new, optimized for IES + .RXOSINTID0 (4'b0000), // GTH new, optimized for IES + .RXOSCALRESET ( 1'd0), // GTH, optimized for IES + + .RSOSINTDONE (), // GTH new + .RXOSINTSTARTED (), // GTH new + .RXOSINTSTROBEDONE (), // GTH new + .RXOSINTSTROBESTARTED (), // GTH new + + //---------- Eye Scan -------------------------------------------------- + .EYESCANRESET (GT_EYESCANRESET), // + .EYESCANMODE (1'd0), // + .EYESCANTRIGGER (1'b0), // + + .EYESCANDATAERROR (GT_EYESCANDATAERROR), // + + //---------- TX Buffer ------------------------------------------------- + .TXBUFSTATUS (), // + + //---------- RX Buffer ------------------------------------------------- + .RXBUFRESET (GT_RXBUFRESET), // + + .RXBUFSTATUS (GT_RXBUFSTATUS), // + + //---------- TX Sync --------------------------------------------------- + .TXPHDLYRESET (GT_TXPHDLYRESET), // + .TXPHDLYTSTCLK (1'd0), // + .TXPHALIGN (GT_TXPHALIGN), // + .TXPHALIGNEN (GT_TXPHALIGNEN), // + .TXPHDLYPD (1'd0), // + .TXPHINIT (GT_TXPHINIT), // + .TXPHOVRDEN (1'd0), // + .TXDLYBYPASS (GT_TXDLYBYPASS), // + .TXDLYSRESET (GT_TXDLYSRESET), // + .TXDLYEN (GT_TXDLYEN), // + .TXDLYOVRDEN (1'd0), // + .TXDLYHOLD (1'd0), // + .TXDLYUPDOWN (1'd0), // + + .TXPHALIGNDONE (GT_TXPHALIGNDONE), // + .TXPHINITDONE (GT_TXPHINITDONE), // + .TXDLYSRESETDONE (GT_TXDLYSRESETDONE), // + + .TXSYNCMODE (GT_TXSYNCMODE), // GTH + .TXSYNCIN (GT_TXSYNCIN), // GTH + .TXSYNCALLIN (GT_TXSYNCALLIN), // GTH + + .TXSYNCDONE (GT_TXSYNCDONE), // GTH + .TXSYNCOUT (GT_TXSYNCOUT), // GTH + + //---------- RX Sync --------------------------------------------------- + .RXPHDLYRESET (1'd0), // + .RXPHALIGN (GT_RXPHALIGN), // + .RXPHALIGNEN (GT_RXPHALIGNEN), // + .RXPHDLYPD (1'd0), // + .RXPHOVRDEN (1'd0), // + .RXDLYBYPASS (GT_RXDLYBYPASS), // + .RXDLYSRESET (GT_RXDLYSRESET), // + .RXDLYEN (GT_RXDLYEN), // + .RXDLYOVRDEN (1'd0), // + .RXDDIEN (GT_RXDDIEN), // + + .RXPHALIGNDONE (GT_RXPHALIGNDONE), // + .RXPHMONITOR (), // + .RXPHSLIPMONITOR (), // + .RXDLYSRESETDONE (GT_RXDLYSRESETDONE), // + + .RXSYNCMODE (GT_RXSYNCMODE), // GTH + .RXSYNCIN (GT_RXSYNCIN), // GTH + .RXSYNCALLIN (GT_RXSYNCALLIN), // GTH + + .RXSYNCDONE (GT_RXSYNCDONE), // GTH + .RXSYNCOUT (GT_RXSYNCOUT), // GTH + + //---------- Comma Alignment ------------------------------------------- + .RXCOMMADETEN ( 1'd1), // + .RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3 + .RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3 + .RXSLIDE ( GT_RXSLIDE), // + + .RXCOMMADET (GT_RXCOMMADET), // + .RXCHARISCOMMA (rxchariscomma), // + .RXBYTEISALIGNED (GT_RXBYTEISALIGNED), // + .RXBYTEREALIGN (GT_RXBYTEREALIGN), // + + //---------- Channel Bonding ------------------------------------------- + .RXCHBONDEN (GT_RXCHBONDEN), // + .RXCHBONDI (GT_RXCHBONDI), // + .RXCHBONDLEVEL (GT_RXCHBONDLEVEL), // + .RXCHBONDMASTER (GT_RXCHBONDMASTER), // + .RXCHBONDSLAVE (GT_RXCHBONDSLAVE), // + + .RXCHANBONDSEQ (), // + .RXCHANISALIGNED (GT_RXCHANISALIGNED), // + .RXCHANREALIGN (), // + .RXCHBONDO (GT_RXCHBONDO), // + + //---------- Clock Correction ----------------------------------------- + .RXCLKCORCNT (), // + + //---------- 8b10b ----------------------------------------------------- + .TX8B10BBYPASS (8'd0), // + .TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3 + .RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3 + + .RXDISPERR (GT_RXDISPERR), // + .RXNOTINTABLE (GT_RXNOTINTABLE), // + + //---------- 64b/66b & 64b/67b ----------------------------------------- + .TXHEADER (3'd0), // + .TXSEQUENCE (7'd0), // + .TXSTARTSEQ (1'd0), // + .RXGEARBOXSLIP (1'd0), // + + .TXGEARBOXREADY (), // + .RXDATAVALID (), // + .RXHEADER (), // + .RXHEADERVALID (), // + .RXSTARTOFSEQ (), // + + //---------- PRBS & Loopback ------------------------------------------- + .TXPRBSSEL (GT_TXPRBSSEL), // + .RXPRBSSEL (GT_RXPRBSSEL), // + .TXPRBSFORCEERR (GT_TXPRBSFORCEERR), // + .RXPRBSCNTRESET (GT_RXPRBSCNTRESET), // + .LOOPBACK (GT_LOOPBACK), // + + .RXPRBSERR (GT_RXPRBSERR), // + + //---------- OOB ------------------------------------------------------- + .SIGVALIDCLK (GT_OOBCLK), // GTH, optimized for debug + .TXCOMINIT (1'd0), // + .TXCOMSAS (1'd0), // + .TXCOMWAKE (1'd0), // + .RXOOBRESET (1'd0), // + + .TXCOMFINISH (), // + .RXCOMINITDET (), // + .RXCOMSASDET (), // + .RXCOMWAKEDET (), // + + //---------- MISC ------------------------------------------------------ + .SETERRSTATUS ( 1'd0), // + .TXDIFFPD ( 1'd0), // + .TXPISOPD ( 1'd0), // + .TSTIN (20'hFFFFF), // + + //---------- GTH ------------------------------------------------------- + .RXADAPTSELTEST (14'd0), // GTH new + .DMONFIFORESET ( 1'd0), // GTH + .DMONITORCLK (dmonitorclk), // GTH, optimized for debug + //.DMONITORCLK (GT_DRPCLK), // GTH, optimized for debug + + .RXPMARESETDONE (GT_RXPMARESETDONE), // GTH + .TXPMARESETDONE () // GTH + + ); + + end + +else + + begin : gtx_channel + + //---------- GTX Channel Module -------------------------------------------- + GTXE2_CHANNEL # + ( + + //---------- Simulation Attributes ------------------------------------- + .SIM_CPLLREFCLK_SEL (3'b001), // + .SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), // + .SIM_RECEIVER_DETECT_PASS ("TRUE"), // + .SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), // + .SIM_VERSION (PCIE_USE_MODE), // + + //---------- Clock Attributes ------------------------------------------ + .CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), // + .CPLL_FBDIV_45 (CPLL_FBDIV_45), // + .CPLL_FBDIV (CPLL_FBDIV), // + .TXOUT_DIV (OUT_DIV), // + .RXOUT_DIV (OUT_DIV), // + .TX_CLK25_DIV (CLK25_DIV), // + .RX_CLK25_DIV (CLK25_DIV), // + .TX_CLKMUX_PD (CLKMUX_PD), // GTX + .RX_CLKMUX_PD (CLKMUX_PD), // GTX + .TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer + .RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer + .OUTREFCLK_SEL_INV ( 2'b11), // + .CPLL_CFG (CPLL_CFG), // Optimized for silicon + //.CPLL_INIT_CFG (24'h00001E), // + //.CPLL_LOCK_CFG (16'h01E8), // + + //---------- Reset Attributes ------------------------------------------ + .TXPCSRESET_TIME (5'b00001), // + .RXPCSRESET_TIME (5'b00001), // + .TXPMARESET_TIME (5'b00011), // + .RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP + //.RXISCANRESET_TIME (5'b00001), // + + //---------- TX Data Attributes ---------------------------------------- + .TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2 + .TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2 + + //---------- RX Data Attributes ---------------------------------------- + .RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2 + .RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2 + + //---------- Command Attributes ---------------------------------------- + .TX_RXDETECT_CFG (TX_RXDETECT_CFG), // + .TX_RXDETECT_REF (TX_RXDETECT_REF), // + .RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable + .RX_CM_TRIM ( 3'b010), // Select 800mV + .TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4) + .TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim + //.PD_TRANS_TIME_FROM_P2 (12'h03C), // + .PD_TRANS_TIME_NONE_P2 ( 8'h09), // + //.PD_TRANS_TIME_TO_P2 ( 8'h64), // + //.TRANS_TIME_RATE ( 8'h0E), // + + //---------- Electrical Command Attributes ----------------------------- + .TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3 + .TX_DEEMPH0 ( 5'b10100), // 6.0 dB + .TX_DEEMPH1 ( 5'b01011), // 3.5 dB + .TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV + .TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV + .TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV + .TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV + .TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV + .TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV + .TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV + .TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV + .TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV + .TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV + .TX_MAINCURSOR_SEL ( 1'b0), // + .TX_PREDRIVER_MODE ( 1'b0), // GTX + .TX_QPI_STATUS_EN ( 1'b0), // + + //---------- Status Attributes ----------------------------------------- + .RX_SIG_VALID_DLY (4), // Optimized for sim + + //---------- DRP Attributes -------------------------------------------- + + //---------- PCS Attributes -------------------------------------------- + .PCS_PCIE_EN ("TRUE"), // PCIe + .PCS_RSVD_ATTR (PCS_RSVD_ATTR), // + + //---------- PMA Attributes -------------------------------------------- + .PMA_RSV (32'h00018480), // Optimized for GES Gen1/Gen2 + .PMA_RSV2 (16'h2050), // Optimized for silicon, [4] RX_CM_TRIM[4], [5] = 1 Enable Eye Scan + //.PMA_RSV3 ( 2'd0), // + //.PMA_RSV4 (32'd0), // GTX 3.0 new + .RX_BIAS_CFG (12'b000000000100), // Optimized for GES + //.TERM_RCAL_CFG ( 5'b10000), // + //.TERM_RCAL_OVRD ( 1'd0), // + + //---------- CDR Attributes -------------------------------------------- + .RXCDR_CFG (RXCDR_CFG_GTX), // + .RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001) + .RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2 + .RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3 + .RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3 + //.RXCDRFREQRESET_TIME ( 5'b00001), // + //.RXCDRPHRESET_TIME ( 5'b00001), // + + //---------- LPM Attributes -------------------------------------------- + .RXLPM_HF_CFG (14'h00F0), // Optimized for silicon + .RXLPM_LF_CFG (14'h00F0), // Optimized for silicon + + //---------- DFE Attributes -------------------------------------------- + //.RXDFELPMRESET_TIME ( 7'b0001111), // + .RX_DFE_GAIN_CFG (23'h020FEA), // Optimized for GES, IES = 23'h001F0A + .RX_DFE_H2_CFG (12'b000000000000), // Optimized for GES + .RX_DFE_H3_CFG (12'b000001000000), // Optimized for GES + .RX_DFE_H4_CFG (11'b00011110000), // Optimized for GES + .RX_DFE_H5_CFG (11'b00011100000), // Optimized for GES + .RX_DFE_KL_CFG (13'b0000011111110), // Optimized for GES + .RX_DFE_KL_CFG2 (32'h3290D86C), // Optimized for GES, GTX new, CTLE 3 3 5, default = 32'h3010D90C + .RX_DFE_LPM_CFG (16'h0954), // Optimized for GES + .RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'd1), // Optimized for PCIe + .RX_DFE_UT_CFG (17'b10001111000000000), // Optimized for GES, IES = 17'h08F00 + .RX_DFE_VP_CFG (17'b00011111100000011), // Optimized for GES + .RX_DFE_XYD_CFG (13'h0000), // Optimized for 4.0 + + //---------- OS Attributes --------------------------------------------- + .RX_OS_CFG (13'b0000010000000), // Optimized for GES + + //---------- Eye Scan Attributes --------------------------------------- + //.ES_CONTROL ( 6'd0), // + //.ES_ERRDET_EN ("FALSE"), // + .ES_EYE_SCAN_EN ("FALSE"), // + .ES_HORZ_OFFSET (12'd0), // + //.ES_PMA_CFG (10'd0), // + //.ES_PRESCALE ( 5'd0), // + //.ES_QUAL_MASK (80'd0), // + //.ES_QUALIFIER (80'd0), // + //.ES_SDATA_MASK (80'd0), // + //.ES_VERT_OFFSET ( 9'd0), // + + //---------- TX Buffer Attributes -------------------------------------- + .TXBUF_EN (PCIE_TXBUF_EN), // + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), // + + //---------- RX Buffer Attributes -------------------------------------- + .RXBUF_EN ("TRUE"), // + //.RX_BUFFER_CFG ( 6'd0), // + .RX_DEFER_RESET_BUF_EN ("TRUE"), // + .RXBUF_ADDR_MODE ("FULL"), // + .RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim + .RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), // + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), // + .RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), // + .RXBUF_THRESH_OVRD ("FALSE"), // + .RXBUF_THRESH_OVFLW (61), // + .RXBUF_THRESH_UNDFLW ( 4), // + //.RXBUFRESET_TIME ( 5'b00001), // + + //---------- TX Sync Attributes ---------------------------------------- + //.TXPH_CFG (16'h0780), // + .TXPH_MONITOR_SEL ( 5'd0), // + //.TXPHDLY_CFG (24'h084020), // + //.TXDLY_CFG (16'h001F), // + //.TXDLY_LCFG ( 9'h030), // + //.TXDLY_TAP_CFG (16'd0), // + + //---------- RX Sync Attributes ---------------------------------------- + //.RXPH_CFG (24'd0), // + .RXPH_MONITOR_SEL ( 5'd0), // + .RXPHDLY_CFG (24'h004020), // Optimized for sim + //.RXDLY_CFG (16'h001F), // + //.RXDLY_LCFG ( 9'h030), // + //.RXDLY_TAP_CFG (16'd0), // + .RX_DDI_SEL ( 6'd0), // + + //---------- Comma Alignment Attributes -------------------------------- + .ALIGN_COMMA_DOUBLE ("FALSE"), // + .ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe + .ALIGN_COMMA_WORD ( 1), // + .ALIGN_MCOMMA_DET ("TRUE"), // + .ALIGN_MCOMMA_VALUE (10'b1010000011), // + .ALIGN_PCOMMA_DET ("TRUE"), // + .ALIGN_PCOMMA_VALUE (10'b0101111100), // + .DEC_MCOMMA_DETECT ("TRUE"), // + .DEC_PCOMMA_DETECT ("TRUE"), // + .DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe + .SHOW_REALIGN_COMMA ("FALSE"), // PCIe + .RXSLIDE_AUTO_WAIT ( 7), // + .RXSLIDE_MODE ("PMA"), // PCIe + + //---------- Channel Bonding Attributes -------------------------------- + .CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe + .CHAN_BOND_MAX_SKEW ( 7), // + .CHAN_BOND_SEQ_LEN ( 4), // PCIe + .CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), // + .CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1 + .CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1 + .CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1 + .CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM + .CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe + .CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), // + .CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2 + .CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2 + .CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2 + .CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM + .FTS_DESKEW_SEQ_ENABLE ( 4'b1111), // + .FTS_LANE_DESKEW_EN ("TRUE"), // PCIe + .FTS_LANE_DESKEW_CFG ( 4'b1111), // + + //---------- Clock Correction Attributes ------------------------------- + .CBCC_DATA_SOURCE_SEL ("DECODED"), // + .CLK_CORRECT_USE ("TRUE"), // + .CLK_COR_KEEP_IDLE ("TRUE"), // PCIe + .CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), // + .CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), // + .CLK_COR_PRECEDENCE ("TRUE"), // + .CLK_COR_REPEAT_WAIT ( 0), // + .CLK_COR_SEQ_LEN ( 1), // + .CLK_COR_SEQ_1_ENABLE ( 4'b1111), // + .CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP + .CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled + .CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled + .CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled + .CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled + .CLK_COR_SEQ_2_USE ("FALSE"), // + .CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled + .CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled + .CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled + .CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled + + //---------- 8b10b Attributes ------------------------------------------ + .RX_DISPERR_SEQ_MATCH ("TRUE"), // + + //---------- 64b/66b & 64b/67b Attributes ------------------------------ + .GEARBOX_MODE (3'd0), // + .TXGEARBOX_EN ("FALSE"), // + .RXGEARBOX_EN ("FALSE"), // + + //---------- PRBS & Loopback Attributes -------------------------------- + .RXPRBS_ERR_LOOPBACK (1'd0), // + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), // + + //---------- OOB & SATA Attributes ------------------------------------- + //.RXOOB_CFG ( 7'b0000110), // + //.SAS_MAX_COM (64), // + //.SAS_MIN_COM (36), // + //.SATA_BURST_SEQ_LEN ( 4'b1111), // + //.SATA_BURST_VAL ( 3'b100), // + //.SATA_CPLL_CFG ("VCO_3000MHZ"), // + //.SATA_EIDLE_VAL ( 3'b100), // + //.SATA_MAX_BURST ( 8), // + //.SATA_MAX_INIT (21), // + //.SATA_MAX_WAKE ( 7), // + //.SATA_MIN_BURST ( 4), // + //.SATA_MIN_INIT (12), // + //.SATA_MIN_WAKE ( 4), // + + //---------- MISC ------------------------------------------------------ + .DMONITOR_CFG (24'h000B01), // Optimized for debug + .RX_DEBUG_CFG (12'd0) // Optimized for GES + //.TST_RSV (32'd0), // + //.UCODEER_CLR ( 1'd0) // + + ) + gtxe2_channel_i + ( + + //---------- Clock ----------------------------------------------------- + .GTGREFCLK (1'd0), // + .GTREFCLK0 (GT_GTREFCLK0), // + .GTREFCLK1 (1'd0), // + .GTNORTHREFCLK0 (1'd0), // + .GTNORTHREFCLK1 (1'd0), // + .GTSOUTHREFCLK0 (1'd0), // + .GTSOUTHREFCLK1 (1'd0), // + .QPLLCLK (GT_QPLLCLK), // + .QPLLREFCLK (GT_QPLLREFCLK), // + .TXUSRCLK (GT_TXUSRCLK), // + .RXUSRCLK (GT_RXUSRCLK), // + .TXUSRCLK2 (GT_TXUSRCLK2), // + .RXUSRCLK2 (GT_RXUSRCLK2), // + .TXSYSCLKSEL (GT_TXSYSCLKSEL), // + .RXSYSCLKSEL (GT_RXSYSCLKSEL), // + .TXOUTCLKSEL (txoutclksel), // + .RXOUTCLKSEL (rxoutclksel), // + .CPLLREFCLKSEL (3'd1), // + .CPLLLOCKDETCLK (1'd0), // + .CPLLLOCKEN (1'd1), // + .CLKRSVD ({2'd0, dmonitorclk, GT_OOBCLK}), // Optimized for debug + + .TXOUTCLK (GT_TXOUTCLK), // + .RXOUTCLK (GT_RXOUTCLK), // + .TXOUTCLKFABRIC (), // + .RXOUTCLKFABRIC (), // + .TXOUTCLKPCS (), // + .RXOUTCLKPCS (), // + .CPLLLOCK (GT_CPLLLOCK), // + .CPLLREFCLKLOST (), // + .CPLLFBCLKLOST (), // + .RXCDRLOCK (GT_RXCDRLOCK), // + .GTREFCLKMONITOR (), // + + //---------- Reset ----------------------------------------------------- + .CPLLPD (cpllpd | GT_CPLLPD), // + .CPLLRESET (cpllrst | GT_CPLLRESET), // + .TXUSERRDY (GT_TXUSERRDY), // + .RXUSERRDY (GT_RXUSERRDY), // + .CFGRESET (1'd0), // + .GTRESETSEL (1'd0), // + .RESETOVRD (GT_RESETOVRD), // + .GTTXRESET (GT_GTTXRESET), // + .GTRXRESET (GT_GTRXRESET), // + + .TXRESETDONE (GT_TXRESETDONE), // + .RXRESETDONE (GT_RXRESETDONE), // + + //---------- TX Data --------------------------------------------------- + .TXDATA ({32'd0, GT_TXDATA}), // + .TXCHARISK ({ 4'd0, GT_TXDATAK}), // + + .GTXTXP (GT_TXP), // GTX + .GTXTXN (GT_TXN), // GTX + + //---------- RX Data --------------------------------------------------- + .GTXRXP (GT_RXP), // GTX + .GTXRXN (GT_RXN), // GTX + + .RXDATA (rxdata), // + .RXCHARISK (rxdatak), // + + //---------- Command --------------------------------------------------- + .TXDETECTRX (GT_TXDETECTRX), // + .TXPDELECIDLEMODE ( 1'd0), // + .RXELECIDLEMODE ( 2'd0), // + .TXELECIDLE (GT_TXELECIDLE), // + .TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), // + .TXCHARDISPVAL ( 8'd0), // + .TXPOLARITY ( 1'b0), // + .RXPOLARITY (GT_RXPOLARITY), // + .TXPD (GT_TXPOWERDOWN), // + .RXPD (GT_RXPOWERDOWN), // + .TXRATE (GT_TXRATE), // + .RXRATE (GT_RXRATE), // + + //---------- Electrical Command ---------------------------------------- + .TXMARGIN (GT_TXMARGIN), // + .TXSWING (GT_TXSWING), // + .TXDEEMPH (GT_TXDEEMPH), // + .TXINHIBIT (GT_TXINHIBIT), // + .TXBUFDIFFCTRL (3'b100), // + .TXDIFFCTRL (4'b1100), // + .TXPRECURSOR (GT_TXPRECURSOR), // + .TXPRECURSORINV (1'd0), // + .TXMAINCURSOR (GT_TXMAINCURSOR), // + .TXPOSTCURSOR (GT_TXPOSTCURSOR), // + .TXPOSTCURSORINV (1'd0), // + + //---------- Status ---------------------------------------------------- + .RXVALID (GT_RXVALID), // + .PHYSTATUS (GT_PHYSTATUS), // + .RXELECIDLE (GT_RXELECIDLE), // + .RXSTATUS (GT_RXSTATUS), // + .TXRATEDONE (GT_TXRATEDONE), // + .RXRATEDONE (GT_RXRATEDONE), // + + //---------- DRP ------------------------------------------------------- + .DRPCLK (GT_DRPCLK), // + .DRPADDR (GT_DRPADDR), // + .DRPEN (GT_DRPEN), // + .DRPDI (GT_DRPDI), // + .DRPWE (GT_DRPWE), // + + .DRPDO (GT_DRPDO), // + .DRPRDY (GT_DRPRDY), // + + //---------- PMA ------------------------------------------------------- + .TXPMARESET (GT_TXPMARESET), // + .RXPMARESET (GT_RXPMARESET), // + .RXLPMEN (rxlpmen), // + .RXLPMHFHOLD ( 1'd0), // + .RXLPMHFOVRDEN ( 1'd0), // + .RXLPMLFHOLD ( 1'd0), // + .RXLPMLFKLOVRDEN ( 1'd0), // + .TXQPIBIASEN ( 1'd0), // + .TXQPISTRONGPDOWN ( 1'd0), // + .TXQPIWEAKPUP ( 1'd0), // + .RXQPIEN ( 1'd0), // + .PMARSVDIN ( 5'd0), // + .PMARSVDIN2 ( 5'd0), // GTX + .GTRSVD (16'd0), // + + .TXQPISENP (), // + .TXQPISENN (), // + .RXQPISENP (), // + .RXQPISENN (), // + .DMONITOROUT (dmonitorout[7:0]), // GTX 8-bits + + //---------- PCS ------------------------------------------------------- + .TXPCSRESET (GT_TXPCSRESET), // + .RXPCSRESET (GT_RXPCSRESET), // + .PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async + .PCSRSVDIN2 ( 5'd0), // + + .PCSRSVDOUT (), // + //---------- CDR ------------------------------------------------------- + .RXCDRRESET (GT_RXCDRRESET), // + .RXCDRRESETRSV (1'd0), // + .RXCDRFREQRESET (GT_RXCDRFREQRESET), // + .RXCDRHOLD (1'b0), // + .RXCDROVRDEN (1'd0), // + + //---------- DFE ------------------------------------------------------- + .RXDFELPMRESET (GT_RXDFELPMRESET), // + .RXDFECM1EN (1'd0), // + .RXDFEVSEN (1'd0), // + .RXDFETAP2HOLD (1'd0), // + .RXDFETAP2OVRDEN (1'd0), // + .RXDFETAP3HOLD (1'd0), // + .RXDFETAP3OVRDEN (1'd0), // + .RXDFETAP4HOLD (1'd0), // + .RXDFETAP4OVRDEN (1'd0), // + .RXDFETAP5HOLD (1'd0), // + .RXDFETAP5OVRDEN (1'd0), // + .RXDFEAGCHOLD (GT_RX_CONVERGE), // Optimized for GES, Set to 1 after convergence + .RXDFEAGCOVRDEN (1'd0), // + .RXDFELFHOLD (1'd0), // + .RXDFELFOVRDEN (1'd1), // Optimized for GES + .RXDFEUTHOLD (1'd0), // + .RXDFEUTOVRDEN (1'd0), // + .RXDFEVPHOLD (1'd0), // + .RXDFEVPOVRDEN (1'd0), // + .RXDFEXYDEN (1'd0), // + .RXDFEXYDHOLD (1'd0), // GTX + .RXDFEXYDOVRDEN (1'd0), // GTX + .RXMONITORSEL (2'd0), // + + .RXMONITOROUT (), // + + //---------- OS -------------------------------------------------------- + .RXOSHOLD (1'd0), // + .RXOSOVRDEN (1'd0), // + + //---------- Eye Scan -------------------------------------------------- + .EYESCANRESET (GT_EYESCANRESET), // + .EYESCANMODE (1'd0), // + .EYESCANTRIGGER (1'b0), // + + .EYESCANDATAERROR (GT_EYESCANDATAERROR), // + + //---------- TX Buffer ------------------------------------------------- + .TXBUFSTATUS (), // + + //---------- RX Buffer ------------------------------------------------- + .RXBUFRESET (GT_RXBUFRESET), // + + .RXBUFSTATUS (GT_RXBUFSTATUS), // + + //---------- TX Sync --------------------------------------------------- + .TXPHDLYRESET (1'd0), // + .TXPHDLYTSTCLK (1'd0), // + .TXPHALIGN (GT_TXPHALIGN), // + .TXPHALIGNEN (GT_TXPHALIGNEN), // + .TXPHDLYPD (1'd0), // + .TXPHINIT (GT_TXPHINIT), // + .TXPHOVRDEN (1'd0), // + .TXDLYBYPASS (GT_TXDLYBYPASS), // + .TXDLYSRESET (GT_TXDLYSRESET), // + .TXDLYEN (GT_TXDLYEN), // + .TXDLYOVRDEN (1'd0), // + .TXDLYHOLD (1'd0), // + .TXDLYUPDOWN (1'd0), // + + .TXPHALIGNDONE (GT_TXPHALIGNDONE), // + .TXPHINITDONE (GT_TXPHINITDONE), // + .TXDLYSRESETDONE (GT_TXDLYSRESETDONE), // + + //---------- RX Sync --------------------------------------------------- + .RXPHDLYRESET (1'd0), // + .RXPHALIGN (GT_RXPHALIGN), // + .RXPHALIGNEN (GT_RXPHALIGNEN), // + .RXPHDLYPD (1'd0), // + .RXPHOVRDEN (1'd0), // + .RXDLYBYPASS (GT_RXDLYBYPASS), // + .RXDLYSRESET (GT_RXDLYSRESET), // + .RXDLYEN (GT_RXDLYEN), // + .RXDLYOVRDEN (1'd0), // + .RXDDIEN (GT_RXDDIEN), // + + .RXPHALIGNDONE (GT_RXPHALIGNDONE), // + .RXPHMONITOR (), // + .RXPHSLIPMONITOR (), // + .RXDLYSRESETDONE (GT_RXDLYSRESETDONE), // + + //---------- Comma Alignment ------------------------------------------- + .RXCOMMADETEN ( 1'd1), // + .RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3 + .RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3 + .RXSLIDE ( GT_RXSLIDE), // + + .RXCOMMADET (GT_RXCOMMADET), // + .RXCHARISCOMMA (rxchariscomma), // + .RXBYTEISALIGNED (GT_RXBYTEISALIGNED), // + .RXBYTEREALIGN (GT_RXBYTEREALIGN), // + + //---------- Channel Bonding ------------------------------------------- + .RXCHBONDEN (GT_RXCHBONDEN), // + .RXCHBONDI (GT_RXCHBONDI), // + .RXCHBONDLEVEL (GT_RXCHBONDLEVEL), // + .RXCHBONDMASTER (GT_RXCHBONDMASTER), // + .RXCHBONDSLAVE (GT_RXCHBONDSLAVE), // + + .RXCHANBONDSEQ (), // + .RXCHANISALIGNED (GT_RXCHANISALIGNED), // + .RXCHANREALIGN (), // + .RXCHBONDO (GT_RXCHBONDO), // + + //---------- Clock Correction ----------------------------------------- + .RXCLKCORCNT (), // + + //---------- 8b10b ----------------------------------------------------- + .TX8B10BBYPASS (8'd0), // + .TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3 + .RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3 + + .RXDISPERR (GT_RXDISPERR), // + .RXNOTINTABLE (GT_RXNOTINTABLE), // + + //---------- 64b/66b & 64b/67b ----------------------------------------- + .TXHEADER (3'd0), // + .TXSEQUENCE (7'd0), // + .TXSTARTSEQ (1'd0), // + .RXGEARBOXSLIP (1'd0), // + + .TXGEARBOXREADY (), // + .RXDATAVALID (), // + .RXHEADER (), // + .RXHEADERVALID (), // + .RXSTARTOFSEQ (), // + + //---------- PRBS/Loopback --------------------------------------------- + .TXPRBSSEL (GT_TXPRBSSEL), // + .RXPRBSSEL (GT_RXPRBSSEL), // + .TXPRBSFORCEERR (GT_TXPRBSFORCEERR), // + .RXPRBSCNTRESET (GT_RXPRBSCNTRESET), // + .LOOPBACK (GT_LOOPBACK), // + + .RXPRBSERR (GT_RXPRBSERR), // + + //---------- OOB ------------------------------------------------------- + .TXCOMINIT (1'd0), // + .TXCOMSAS (1'd0), // + .TXCOMWAKE (1'd0), // + .RXOOBRESET (1'd0), // + + .TXCOMFINISH (), // + .RXCOMINITDET (), // + .RXCOMSASDET (), // + .RXCOMWAKEDET (), // + + //---------- MISC ------------------------------------------------------ + .SETERRSTATUS ( 1'd0), // + .TXDIFFPD ( 1'd0), // + .TXPISOPD ( 1'd0), // + .TSTIN (20'hFFFFF), // + + .TSTOUT () // GTX + + ); + + //---------- Default ------------------------------------------------------- + assign dmonitorout[14:8] = 7'd0; // GTH GTP + assign GT_TXSYNCOUT = 1'd0; // GTH GTP + assign GT_TXSYNCDONE = 1'd0; // GTH GTP + assign GT_RXSYNCOUT = 1'd0; // GTH GTP + assign GT_RXSYNCDONE = 1'd0; // GTH GTP + assign GT_RXPMARESETDONE = 1'd0; // GTH GTP + + end + +endgenerate + +//---------- GT Wrapper Outputs ------------------------------------------------ +assign GT_RXDATA = rxdata [31:0]; +assign GT_RXDATAK = rxdatak[ 3:0]; +assign GT_RXCHARISCOMMA = rxchariscomma[ 3:0]; +assign GT_DMONITOROUT = dmonitorout; + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtp_cpllpd_ovrd.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtp_cpllpd_ovrd.v new file mode 100644 index 0000000..7ae62bd --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtp_cpllpd_ovrd.v @@ -0,0 +1,68 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_gtp_cpllpd_ovrd.v +// Version : 3.3 +`timescale 1ns / 1ps +module pcie_7x_0_gtp_cpllpd_ovrd ( + input i_ibufds_gte2, + output o_cpllpd_ovrd, + output o_cpllreset_ovrd + ); + (* equivalent_register_removal="no" *) reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF; + (* equivalent_register_removal="no" *) reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF; + always @(posedge i_ibufds_gte2) + begin + cpllpd_wait <= {cpllpd_wait[94:0], 1'b0}; + cpllreset_wait <= {cpllreset_wait[126:0], 1'b0}; + end + assign o_cpllpd_ovrd = cpllpd_wait[95]; + assign o_cpllreset_ovrd = cpllreset_wait[127]; +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtp_pipe_drp.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtp_pipe_drp.v new file mode 100644 index 0000000..280067f --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtp_pipe_drp.v @@ -0,0 +1,370 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_gtp_pipe_drp.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : gtp_pipe_drp.v +// Description : GTP PIPE DRP Module for 7 Series Transceiver +// Version : 19.0 +//------------------------------------------------------------------------------ + + + +`timescale 1ns / 1ps + + + +//---------- GTP PIPE DRP Module ----------------------------------------------- +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_gtp_pipe_drp # +( + + parameter LOAD_CNT_MAX = 2'd1, // Load max count + parameter INDEX_MAX = 1'd0 // Index max count + +) + +( + + //---------- Input ------------------------------------- + input DRP_CLK, + input DRP_RST_N, + input DRP_X16, + input DRP_START, + input [15:0] DRP_DO, + input DRP_RDY, + + //---------- Output ------------------------------------ + output [ 8:0] DRP_ADDR, + output DRP_EN, + output [15:0] DRP_DI, + output DRP_WE, + output DRP_DONE, + output [ 2:0] DRP_FSM + +); + + //---------- Input Registers --------------------------- +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2; + + //---------- Internal Signals -------------------------- + reg [ 1:0] load_cnt = 2'd0; + reg [ 4:0] index = 5'd0; + reg [ 8:0] addr_reg = 9'd0; + reg [15:0] di_reg = 16'd0; + + //---------- Output Registers -------------------------- + reg done = 1'd0; + reg [ 2:0] fsm = 0; + + //---------- DRP Address ------------------------------- + localparam ADDR_RX_DATAWIDTH = 9'h011; + + //---------- DRP Mask ---------------------------------- + localparam MASK_RX_DATAWIDTH = 16'b1111011111111111; // Unmask bit [ 11] + + //---------- DRP Data for x16 -------------------------- + localparam X16_RX_DATAWIDTH = 16'b0000000000000000; // 2-byte (16-bit) internal data width + + //---------- DRP Data for x20 -------------------------- + localparam X20_RX_DATAWIDTH = 16'b0000100000000000; // 2-byte (20-bit) internal data width + + //---------- DRP Data ---------------------------------- + wire [15:0] data_rx_datawidth; + + //---------- FSM --------------------------------------- + localparam FSM_IDLE = 0; + localparam FSM_LOAD = 1; + localparam FSM_READ = 2; + localparam FSM_RRDY = 3; + localparam FSM_WRITE = 4; + localparam FSM_WRDY = 5; + localparam FSM_DONE = 6; + + + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge DRP_CLK) +begin + + if (!DRP_RST_N) + begin + //---------- 1st Stage FF -------------------------- + x16_reg1 <= 1'd0; + do_reg1 <= 16'd0; + rdy_reg1 <= 1'd0; + start_reg1 <= 1'd0; + //---------- 2nd Stage FF -------------------------- + x16_reg2 <= 1'd0; + do_reg2 <= 16'd0; + rdy_reg2 <= 1'd0; + start_reg2 <= 1'd0; + end + + else + begin + //---------- 1st Stage FF -------------------------- + x16_reg1 <= DRP_X16; + do_reg1 <= DRP_DO; + rdy_reg1 <= DRP_RDY; + start_reg1 <= DRP_START; + //---------- 2nd Stage FF -------------------------- + x16_reg2 <= x16_reg1; + do_reg2 <= do_reg1; + rdy_reg2 <= rdy_reg1; + start_reg2 <= start_reg1; + end + +end + + + +//---------- Select DRP Data --------------------------------------------------- +assign data_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH; + + + +//---------- Load Counter ------------------------------------------------------ +always @ (posedge DRP_CLK) +begin + + if (!DRP_RST_N) + load_cnt <= 2'd0; + else + + //---------- Increment Load Counter ---------------- + if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX)) + load_cnt <= load_cnt + 2'd1; + + //---------- Hold Load Counter --------------------- + else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX)) + load_cnt <= load_cnt; + + //---------- Reset Load Counter -------------------- + else + load_cnt <= 2'd0; + +end + + + +//---------- Update DRP Address and Data --------------------------------------- +always @ (posedge DRP_CLK) +begin + + if (!DRP_RST_N) + begin + addr_reg <= 9'd0; + di_reg <= 16'd0; + end + else + begin + + case (index) + + //-------------------------------------------------- + 1'd0 : + begin + addr_reg <= ADDR_RX_DATAWIDTH; + di_reg <= (do_reg2 & MASK_RX_DATAWIDTH) | data_rx_datawidth; + end + + //-------------------------------------------------- + default : + begin + addr_reg <= 9'd0; + di_reg <= 16'd0; + end + + endcase + + end + +end + + + +//---------- PIPE DRP FSM ------------------------------------------------------ +always @ (posedge DRP_CLK) +begin + + if (!DRP_RST_N) + begin + fsm <= FSM_IDLE; + index <= 5'd0; + done <= 1'd1; //Fix applied for GTP DRP issue + end + else + begin + + case (fsm) + + //---------- Idle State ---------------------------- + FSM_IDLE : + + begin + //---------- Reset or Rate Change -------------- + if (start_reg2) + begin + fsm <= FSM_LOAD; + index <= 5'd0; + done <= 1'd0; + end + //---------- Idle ------------------------------ + else + begin + fsm <= FSM_IDLE; + index <= 5'd0; + done <= 1'd1; + end + end + + //---------- Load DRP Address --------------------- + FSM_LOAD : + + begin + fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD; + index <= index; + + done <= 1'd0; + end + + //---------- Read DRP ------------------------------ + FSM_READ : + + begin + fsm <= FSM_RRDY; + index <= index; + done <= 1'd0; + end + + //---------- Read DRP Ready ------------------------ + FSM_RRDY : + + begin + fsm <= rdy_reg2 ? FSM_WRITE : FSM_RRDY; + index <= index; + done <= 1'd0; + end + + + //---------- Write DRP ----------------------------- + FSM_WRITE : + + begin + fsm <= FSM_WRDY; + index <= index; + done <= 1'd0; + end + + //---------- Write DRP Ready ----------------------- + FSM_WRDY : + + begin + fsm <= rdy_reg2 ? FSM_DONE : FSM_WRDY; + index <= index; + done <= 1'd0; + end + + //---------- DRP Done ------------------------------ + FSM_DONE : + + begin + if (index == INDEX_MAX) + begin + fsm <= FSM_IDLE; + index <= 5'd0; + done <= 1'd1; //Fix applied for GTP DRP issue + end + else + begin + fsm <= FSM_LOAD; + index <= index + 5'd1; + done <= 1'd0; + end + end + + //---------- Default State ------------------------- + default : + + begin + fsm <= FSM_IDLE; + index <= 5'd0; + done <= 1'd1; //Fix applied for GTP DRP issue + end + + endcase + + end + +end + + + +//---------- PIPE DRP Output --------------------------------------------------- +assign DRP_ADDR = addr_reg; +assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE); +assign DRP_DI = di_reg; +assign DRP_WE = (fsm == FSM_WRITE); +assign DRP_DONE = done; +assign DRP_FSM = fsm; + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtp_pipe_rate.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtp_pipe_rate.v new file mode 100644 index 0000000..51ae111 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtp_pipe_rate.v @@ -0,0 +1,461 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_gtp_pipe_rate.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : gtp_pipe_rate.v +// Description : PIPE Rate Module for 7 Series Transceiver +// Version : 19.0 +//------------------------------------------------------------------------------ + + + +`timescale 1ns / 1ps + + + +//---------- PIPE Rate Module -------------------------------------------------- +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_gtp_pipe_rate # +( + + parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim mode + parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max + +) + +( + + //---------- Input ------------------------------------- + input RATE_CLK, + input RATE_RST_N, + input [ 1:0] RATE_RATE_IN, + input RATE_DRP_DONE, + input RATE_RXPMARESETDONE, + input RATE_TXRATEDONE, + input RATE_RXRATEDONE, + input RATE_TXSYNC_DONE, + input RATE_PHYSTATUS, + + //---------- Output ------------------------------------ + output RATE_PCLK_SEL, + output RATE_DRP_START, + output RATE_DRP_X16, + output [ 2:0] RATE_RATE_OUT, + output RATE_TXSYNC_START, + output RATE_DONE, + output RATE_IDLE, + output [ 4:0] RATE_FSM + +); + + //---------- Input FF or Buffer ------------------------ +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2; + + //---------- Internal Signals -------------------------- + wire [ 2:0] rate; + reg [ 3:0] txdata_wait_cnt = 4'd0; + reg txratedone = 1'd0; + reg rxratedone = 1'd0; + reg phystatus = 1'd0; + reg ratedone = 1'd0; + + //---------- Output FF or Buffer ----------------------- + reg pclk_sel = 1'd0; + reg [ 2:0] rate_out = 3'd0; + reg [ 3:0] fsm = 0; + + //---------- FSM --------------------------------------- + localparam FSM_IDLE = 0; + localparam FSM_TXDATA_WAIT = 1; + localparam FSM_PCLK_SEL = 2; + localparam FSM_DRP_X16_START = 3; + localparam FSM_DRP_X16_DONE = 4; + localparam FSM_RATE_SEL = 5; + localparam FSM_RXPMARESETDONE = 6; + localparam FSM_DRP_X20_START = 7; + localparam FSM_DRP_X20_DONE = 8; + localparam FSM_RATE_DONE = 9; + localparam FSM_TXSYNC_START = 10; + localparam FSM_TXSYNC_DONE = 11; + localparam FSM_DONE = 12; // Must sync value to pipe_user.v + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge RATE_CLK) +begin + + if (!RATE_RST_N) + begin + //---------- 1st Stage FF -------------------------- + rate_in_reg1 <= 2'd0; + drp_done_reg1 <= 1'd0; + rxpmaresetdone_reg1 <= 1'd0; + txratedone_reg1 <= 1'd0; + rxratedone_reg1 <= 1'd0; + phystatus_reg1 <= 1'd0; + txsync_done_reg1 <= 1'd0; + //---------- 2nd Stage FF -------------------------- + rate_in_reg2 <= 2'd0; + drp_done_reg2 <= 1'd0; + rxpmaresetdone_reg2 <= 1'd0; + txratedone_reg2 <= 1'd0; + rxratedone_reg2 <= 1'd0; + phystatus_reg2 <= 1'd0; + txsync_done_reg2 <= 1'd0; + end + else + begin + //---------- 1st Stage FF -------------------------- + rate_in_reg1 <= RATE_RATE_IN; + drp_done_reg1 <= RATE_DRP_DONE; + rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE; + txratedone_reg1 <= RATE_TXRATEDONE; + rxratedone_reg1 <= RATE_RXRATEDONE; + phystatus_reg1 <= RATE_PHYSTATUS; + txsync_done_reg1 <= RATE_TXSYNC_DONE; + //---------- 2nd Stage FF -------------------------- + rate_in_reg2 <= rate_in_reg1; + drp_done_reg2 <= drp_done_reg1; + rxpmaresetdone_reg2 <= rxpmaresetdone_reg1; + txratedone_reg2 <= txratedone_reg1; + rxratedone_reg2 <= rxratedone_reg1; + phystatus_reg2 <= phystatus_reg1; + txsync_done_reg2 <= txsync_done_reg1; + end + +end + + + +//---------- Select Rate ------------------------------------------------------- +// Gen1 : div 2 using [TX/RX]OUT_DIV = 2 +// Gen2 : div 1 using [TX/RX]RATE = 3'd1 +//------------------------------------------------------------------------------ +assign rate = (rate_in_reg2 == 2'd1) ? 3'd1 : 3'd0; + + + +//---------- TXDATA Wait Counter ----------------------------------------------- +always @ (posedge RATE_CLK) +begin + + if (!RATE_RST_N) + txdata_wait_cnt <= 4'd0; + else + + //---------- Increment Wait Counter ---------------- + if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX)) + txdata_wait_cnt <= txdata_wait_cnt + 4'd1; + + //---------- Hold Wait Counter --------------------- + else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX)) + txdata_wait_cnt <= txdata_wait_cnt; + + //---------- Reset Wait Counter -------------------- + else + txdata_wait_cnt <= 4'd0; + +end + + + +//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS ----------------------- +always @ (posedge RATE_CLK) +begin + + if (!RATE_RST_N) + begin + txratedone <= 1'd0; + rxratedone <= 1'd0; + phystatus <= 1'd0; + ratedone <= 1'd0; + end + else + begin + + if ((fsm == FSM_RATE_DONE) || (fsm == FSM_RXPMARESETDONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE)) + + begin + + //---------- Latch TXRATEDONE ------------------ + if (txratedone_reg2) + txratedone <= 1'd1; + else + txratedone <= txratedone; + + //---------- Latch RXRATEDONE ------------------ + if (rxratedone_reg2) + rxratedone <= 1'd1; + else + rxratedone <= rxratedone; + + //---------- Latch PHYSTATUS ------------------- + if (phystatus_reg2) + phystatus <= 1'd1; + else + phystatus <= phystatus; + + //---------- Latch Rate Done ------------------- + if (rxratedone && txratedone && phystatus) + ratedone <= 1'd1; + else + ratedone <= ratedone; + + end + + else + + begin + txratedone <= 1'd0; + rxratedone <= 1'd0; + phystatus <= 1'd0; + ratedone <= 1'd0; + end + + end + +end + + + +//---------- PIPE Rate FSM ----------------------------------------------------- +always @ (posedge RATE_CLK) +begin + + if (!RATE_RST_N) + begin + fsm <= FSM_IDLE; + pclk_sel <= 1'd0; + rate_out <= 3'd0; + end + else + begin + + case (fsm) + + //---------- Idle State ---------------------------- + FSM_IDLE : + + begin + //---------- Detect Rate Change ---------------- + if (rate_in_reg2 != rate_in_reg1) + begin + fsm <= FSM_TXDATA_WAIT; + pclk_sel <= pclk_sel; + rate_out <= rate_out; + end + else + begin + fsm <= FSM_IDLE; + pclk_sel <= pclk_sel; + rate_out <= rate_out; + end + end + + //---------- Wait for TXDATA to TX[P/N] Latency ---- + FSM_TXDATA_WAIT : + + begin + fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT; + pclk_sel <= pclk_sel; + rate_out <= rate_out; + end + + //---------- Select PCLK Frequency ----------------- + // Gen1 : PCLK = 125 MHz + // Gen2 : PCLK = 250 MHz + //-------------------------------------------------- + FSM_PCLK_SEL : + + begin + fsm <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_SEL : FSM_DRP_X16_START; + pclk_sel <= (rate_in_reg2 == 2'd1); + rate_out <= rate_out; + end + + //---------- Start DRP x16 ------------------------- + FSM_DRP_X16_START : + + begin + fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START; + pclk_sel <= pclk_sel; + rate_out <= rate_out; + end + + //---------- Wait for DRP x16 Done ----------------- + FSM_DRP_X16_DONE : + + begin + fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE; + pclk_sel <= pclk_sel; + rate_out <= rate_out; + end + + //---------- Select Rate --------------------------- + FSM_RATE_SEL : + + begin + fsm <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_DONE : FSM_RXPMARESETDONE; + pclk_sel <= pclk_sel; + rate_out <= rate; // Update [TX/RX]RATE + end + + //---------- Wait for RXPMARESETDONE De-assertion -- + FSM_RXPMARESETDONE : + + begin + fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE; + pclk_sel <= pclk_sel; + rate_out <= rate_out; + end + + //---------- Start DRP x20 ------------------------- + FSM_DRP_X20_START : + + begin + fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START; + pclk_sel <= pclk_sel; + rate_out <= rate_out; + end + + //---------- Wait for DRP x20 Done ----------------- + FSM_DRP_X20_DONE : + + begin + fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE; + pclk_sel <= pclk_sel; + rate_out <= rate_out; + end + + //---------- Wait for Rate Change Done ------------- + FSM_RATE_DONE : + + begin + if (ratedone) + fsm <= FSM_TXSYNC_START; + else + fsm <= FSM_RATE_DONE; + + pclk_sel <= pclk_sel; + rate_out <= rate_out; + end + + //---------- Start TX Sync ------------------------- + FSM_TXSYNC_START: + + begin + fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START); + pclk_sel <= pclk_sel; + rate_out <= rate_out; + end + + //---------- Wait for TX Sync Done ----------------- + FSM_TXSYNC_DONE: + + begin + fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE); + pclk_sel <= pclk_sel; + rate_out <= rate_out; + end + + //---------- Rate Change Done ---------------------- + FSM_DONE : + + begin + fsm <= FSM_IDLE; + pclk_sel <= pclk_sel; + rate_out <= rate_out; + end + + //---------- Default State ------------------------- + default : + + begin + fsm <= FSM_IDLE; + pclk_sel <= 1'd0; + rate_out <= 3'd0; + end + + endcase + + end + +end + + + +//---------- PIPE Rate Output -------------------------------------------------- +assign RATE_PCLK_SEL = pclk_sel; +assign RATE_DRP_START = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START); +assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE); +assign RATE_RATE_OUT = rate_out; +assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START); +assign RATE_DONE = (fsm == FSM_DONE); +assign RATE_IDLE = (fsm == FSM_IDLE); +assign RATE_FSM = {1'd0, fsm}; + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtp_pipe_reset.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtp_pipe_reset.v new file mode 100644 index 0000000..95fbecc --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtp_pipe_reset.v @@ -0,0 +1,537 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_gtp_pipe_reset.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : gtp_pipe_reset.v +// Description : GTP PIPE Reset Module for 7 Series Transceiver +// Version : 19.0 +//------------------------------------------------------------------------------ + + + +`timescale 1ns / 1ps + + + +//---------- PIPE Reset Module ------------------------------------------------- +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_gtp_pipe_reset # +( + + //---------- Global ------------------------------------ + parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup + parameter PCIE_LANE = 1, // PCIe number of lanes + //---------- Local ------------------------------------- + parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max + parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK + +) + +( + + //---------- Input ------------------------------------- + input RST_CLK, + input RST_RXUSRCLK, + input RST_DCLK, + input RST_RST_N, + input [PCIE_LANE-1:0] RST_DRP_DONE, + input [PCIE_LANE-1:0] RST_RXPMARESETDONE, + input RST_PLLLOCK, + input [PCIE_LANE-1:0] RST_RATE_IDLE, + input [PCIE_LANE-1:0] RST_RXCDRLOCK, + input RST_MMCM_LOCK, + input [PCIE_LANE-1:0] RST_RESETDONE, + input [PCIE_LANE-1:0] RST_PHYSTATUS, + input [PCIE_LANE-1:0] RST_TXSYNC_DONE, + + //---------- Output ------------------------------------ + output RST_CPLLRESET, + output RST_CPLLPD, + output reg RST_DRP_START, + output reg RST_DRP_X16, + output RST_RXUSRCLK_RESET, + output RST_DCLK_RESET, + output RST_GTRESET, + output RST_USERRDY, + output RST_TXSYNC_START, + output RST_IDLE, + output [ 4:0] RST_FSM + +); + + //---------- Input Register ---------------------------- +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2; + + //---------- Internal Signal --------------------------- + reg [ 5:0] cfg_wait_cnt = 6'd0; + + //---------- Output Register --------------------------- + reg pllreset = 1'd0; + reg pllpd = 1'd0; + reg rxusrclk_rst_reg1 = 1'd0; + reg rxusrclk_rst_reg2 = 1'd0; + reg dclk_rst_reg1 = 1'd0; + reg dclk_rst_reg2 = 1'd0; + reg gtreset = 1'd0; + reg userrdy = 1'd0; + reg [ 4:0] fsm = 5'h1; + + //---------- FSM --------------------------------------- + localparam FSM_IDLE = 5'h0; + localparam FSM_CFG_WAIT = 5'h1; + localparam FSM_PLLRESET = 5'h2; + localparam FSM_DRP_X16_START = 5'h3; + localparam FSM_DRP_X16_DONE = 5'h4; + localparam FSM_PLLLOCK = 5'h5; + localparam FSM_GTRESET = 5'h6; + localparam FSM_RXPMARESETDONE_1 = 5'h7; + localparam FSM_RXPMARESETDONE_2 = 5'h8; + localparam FSM_DRP_X20_START = 5'h9; + localparam FSM_DRP_X20_DONE = 5'hA; + localparam FSM_MMCM_LOCK = 5'hB; + localparam FSM_RESETDONE = 5'hC; + localparam FSM_TXSYNC_START = 5'hD; + localparam FSM_TXSYNC_DONE = 5'hE; + + + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge RST_CLK) +begin + + if (!RST_RST_N) + begin + //---------- 1st Stage FF -------------------------- + drp_done_reg1 <= {PCIE_LANE{1'd0}}; + rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}}; + plllock_reg1 <= 1'd0; + rate_idle_reg1 <= {PCIE_LANE{1'd0}}; + rxcdrlock_reg1 <= {PCIE_LANE{1'd0}}; + mmcm_lock_reg1 <= 1'd0; + resetdone_reg1 <= {PCIE_LANE{1'd0}}; + phystatus_reg1 <= {PCIE_LANE{1'd0}}; + txsync_done_reg1 <= {PCIE_LANE{1'd0}}; + //---------- 2nd Stage FF -------------------------- + drp_done_reg2 <= {PCIE_LANE{1'd0}}; + rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}}; + plllock_reg2 <= 1'd0; + rate_idle_reg2 <= {PCIE_LANE{1'd0}}; + rxcdrlock_reg2 <= {PCIE_LANE{1'd0}}; + mmcm_lock_reg2 <= 1'd0; + resetdone_reg2 <= {PCIE_LANE{1'd0}}; + phystatus_reg2 <= {PCIE_LANE{1'd0}}; + txsync_done_reg2 <= {PCIE_LANE{1'd0}}; + end + else + begin + //---------- 1st Stage FF -------------------------- + drp_done_reg1 <= RST_DRP_DONE; + rxpmaresetdone_reg1 <= RST_RXPMARESETDONE; + plllock_reg1 <= RST_PLLLOCK; + rate_idle_reg1 <= RST_RATE_IDLE; + rxcdrlock_reg1 <= RST_RXCDRLOCK; + mmcm_lock_reg1 <= RST_MMCM_LOCK; + resetdone_reg1 <= RST_RESETDONE; + phystatus_reg1 <= RST_PHYSTATUS; + txsync_done_reg1 <= RST_TXSYNC_DONE; + //---------- 2nd Stage FF -------------------------- + drp_done_reg2 <= drp_done_reg1; + rxpmaresetdone_reg2 <= rxpmaresetdone_reg1; + plllock_reg2 <= plllock_reg1; + rate_idle_reg2 <= rate_idle_reg1; + rxcdrlock_reg2 <= rxcdrlock_reg1; + mmcm_lock_reg2 <= mmcm_lock_reg1; + resetdone_reg2 <= resetdone_reg1; + phystatus_reg2 <= phystatus_reg1; + txsync_done_reg2 <= txsync_done_reg1; + end + +end + + + +//---------- Configuration Reset Wait Counter ---------------------------------- +always @ (posedge RST_CLK) +begin + + if (!RST_RST_N) + cfg_wait_cnt <= 6'd0; + else + + //---------- Increment Configuration Reset Wait Counter + if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX)) + cfg_wait_cnt <= cfg_wait_cnt + 6'd1; + + //---------- Hold Configuration Reset Wait Counter - + else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX)) + cfg_wait_cnt <= cfg_wait_cnt; + + //---------- Reset Configuration Reset Wait Counter + else + cfg_wait_cnt <= 6'd0; + +end + + + +//---------- PIPE Reset FSM ---------------------------------------------------- +always @ (posedge RST_CLK) +begin + + if (!RST_RST_N) + begin + fsm <= FSM_CFG_WAIT; + pllreset <= 1'd0; + pllpd <= 1'd0; + gtreset <= 1'd0; + userrdy <= 1'd0; + end + else + begin + + case (fsm) + + //---------- Idle State ---------------------------- + FSM_IDLE : + + begin + if (!RST_RST_N) + begin + fsm <= FSM_CFG_WAIT; + pllreset <= 1'd0; + pllpd <= 1'd0; + gtreset <= 1'd0; + userrdy <= 1'd0; + end + else + begin + fsm <= FSM_IDLE; + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + end + + //---------- Wait for Configuration Reset Delay --- + FSM_CFG_WAIT : + + begin + fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_PLLRESET : FSM_CFG_WAIT); + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Hold PLL and GTP Channel in Reset ---- + FSM_PLLRESET : + + begin + fsm <= (((~plllock_reg2) && (&(~resetdone_reg2))) ? FSM_DRP_X16_START : FSM_PLLRESET); + pllreset <= 1'd1; + pllpd <= pllpd; + gtreset <= 1'd1; + userrdy <= userrdy; + end + + //---------- Start DRP x16 ------------------------- + FSM_DRP_X16_START : + + begin + fsm <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START; + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Wait for DRP x16 Done ----------------- + FSM_DRP_X16_DONE : + + begin + fsm <= (&drp_done_reg2) ? FSM_PLLLOCK : FSM_DRP_X16_DONE; + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Wait for PLL Lock -------------------- + FSM_PLLLOCK : + + begin + fsm <= (plllock_reg2 ? FSM_GTRESET : FSM_PLLLOCK); + pllreset <= 1'd0; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Release GTRESET ----------------------- + FSM_GTRESET : + + begin + fsm <= FSM_RXPMARESETDONE_1; + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= 1'b0; + userrdy <= userrdy; + end + + //---------- Wait for RXPMARESETDONE Assertion ----- + FSM_RXPMARESETDONE_1 : + + begin + fsm <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1; + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Wait for RXPMARESETDONE De-assertion -- + FSM_RXPMARESETDONE_2 : + + begin + fsm <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2; + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Start DRP x20 ------------------------- + FSM_DRP_X20_START : + + begin + fsm <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START; + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Wait for DRP x20 Done ----------------- + FSM_DRP_X20_DONE : + + begin + fsm <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE; + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Wait for MMCM and RX CDR Lock --------- + FSM_MMCM_LOCK : + + begin + if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1))) + begin + fsm <= FSM_RESETDONE; + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= 1'd1; + end + else + begin + fsm <= FSM_MMCM_LOCK; + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= 1'd0; + end + end + + //---------- Wait for [TX/RX]RESETDONE and PHYSTATUS + FSM_RESETDONE : + + begin + fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_TXSYNC_START : FSM_RESETDONE); + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Start TX Sync ------------------------- + FSM_TXSYNC_START : + + begin + fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START); + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Wait for TX Sync Done ----------------- + FSM_TXSYNC_DONE : + + begin + fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE); + pllreset <= pllreset; + pllpd <= pllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Default State ------------------------- + default : + + begin + fsm <= FSM_CFG_WAIT; + pllreset <= 1'd0; + pllpd <= 1'd0; + gtreset <= 1'd0; + userrdy <= 1'd0; + end + + endcase + + end + +end + + + +//---------- RXUSRCLK Reset Synchronizer --------------------------------------- +always @ (posedge RST_RXUSRCLK) +begin + + if (pllreset) + begin + rxusrclk_rst_reg1 <= 1'd1; + rxusrclk_rst_reg2 <= 1'd1; + end + else + begin + rxusrclk_rst_reg1 <= 1'd0; + rxusrclk_rst_reg2 <= rxusrclk_rst_reg1; + end + +end + +//---------- DCLK Reset Synchronizer ------------------------------------------- +always @ (posedge RST_DCLK) +begin + + if (fsm == FSM_CFG_WAIT) + begin + dclk_rst_reg1 <= 1'd1; + dclk_rst_reg2 <= dclk_rst_reg1; + end + else + begin + dclk_rst_reg1 <= 1'd0; + dclk_rst_reg2 <= dclk_rst_reg1; + end + +end + + + +//---------- PIPE Reset Output ------------------------------------------------- +assign RST_CPLLRESET = pllreset; +assign RST_CPLLPD = pllpd; +assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2; +assign RST_DCLK_RESET = dclk_rst_reg2; +assign RST_GTRESET = gtreset; +assign RST_USERRDY = userrdy; +assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START); +assign RST_IDLE = (fsm == FSM_IDLE); +assign RST_FSM = fsm; + + + +//-------------------------------------------------------------------------------------------------- +// Register Output +//-------------------------------------------------------------------------------------------------- +always @ (posedge RST_CLK) +begin + + if (!RST_RST_N) + begin + RST_DRP_START <= 1'd0; + RST_DRP_X16 <= 1'd0; + end + else + begin + RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START); + RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE); + end + +end + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtx_cpllpd_ovrd.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtx_cpllpd_ovrd.v new file mode 100644 index 0000000..6463ab7 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtx_cpllpd_ovrd.v @@ -0,0 +1,68 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_gtx_cpllpd_ovrd.v +// Version : 3.3 +`timescale 1ns / 1ps +module pcie_7x_0_gtx_cpllpd_ovrd ( + input i_ibufds_gte2, + output o_cpllpd_ovrd, + output o_cpllreset_ovrd + ); + (* equivalent_register_removal="no" *) reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF; + (* equivalent_register_removal="no" *) reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF; + always @(posedge i_ibufds_gte2) + begin + cpllpd_wait <= {cpllpd_wait[94:0], 1'b0}; + cpllreset_wait <= {cpllreset_wait[126:0], 1'b0}; + end + assign o_cpllpd_ovrd = cpllpd_wait[95]; + assign o_cpllreset_ovrd = cpllreset_wait[127]; +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie2_top.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie2_top.v new file mode 100644 index 0000000..95cc08f --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie2_top.v @@ -0,0 +1,1018 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pcie2_top.v +// Version : 3.3 + +//-------------------------------------------------------------------------------- + + +`timescale 1ns/1ps +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pcie2_top # ( +parameter c_component_name ="pcie_7x_v3_3_14", +parameter dev_port_type ="0000", +parameter c_dev_port_type ="0", +parameter c_header_type ="00", +parameter c_upstream_facing ="TRUE", +parameter max_lnk_wdt = "000100", +parameter max_lnk_spd = "1", +parameter c_gen1 = 1'b0, +parameter c_int_width = 64, +parameter pci_exp_int_freq = 2, +parameter c_pcie_fast_config = 0, +parameter bar_0 = "FFFFFF80", +parameter bar_1 = "00000000", +parameter bar_2 = "00000000", +parameter bar_3 = "00000000", +parameter bar_4 = "00000000", +parameter bar_5 = "00000000", +parameter xrom_bar = "00000000", +parameter cost_table = 1, +parameter ven_id = "10EE", +parameter dev_id = "7028", +parameter rev_id = "00", +parameter subsys_ven_id = "10EE", +parameter subsys_id = "0007", +parameter class_code = "058000", +parameter cardbus_cis_ptr = "00000000", +parameter cap_ver = "2", +parameter c_pcie_cap_slot_implemented = "FALSE", +parameter mps = "010", +parameter cmps = "2", +parameter ext_tag_fld_sup = "FALSE", +parameter c_dev_control_ext_tag_default = "FALSE", +parameter phantm_func_sup = "00", +parameter c_phantom_functions = "0", +parameter ep_l0s_accpt_lat = "000", +parameter c_ep_l0s_accpt_lat = "0", +parameter ep_l1_accpt_lat = "111", +parameter c_ep_l1_accpt_lat = "7", +parameter c_cpl_timeout_disable_sup = "FALSE", +parameter c_cpl_timeout_range = "0010", +parameter c_cpl_timeout_ranges_sup = "2", +parameter c_buf_opt_bma = "TRUE", +parameter c_perf_level_high = "TRUE", +parameter c_tx_last_tlp = "29", +parameter c_rx_ram_limit = "7FF", +parameter c_fc_ph = "32", +parameter c_fc_pd = "437", +parameter c_fc_nph = "12", +parameter c_fc_npd = "24", +parameter c_fc_cplh = "36", +parameter c_fc_cpld = "461", +parameter c_cpl_inf = "TRUE", +parameter c_cpl_infinite = "TRUE", +parameter c_surprise_dn_err_cap = "FALSE", +parameter c_dll_lnk_actv_cap = "FALSE", +parameter c_lnk_bndwdt_notif = "FALSE", +parameter c_external_clocking = "TRUE", +parameter c_trgt_lnk_spd = "0", +parameter c_hw_auton_spd_disable = "FALSE", +parameter c_de_emph = "FALSE", +parameter slot_clk = "TRUE", +parameter c_rcb = "0", +parameter c_root_cap_crs = "FALSE", +parameter c_slot_cap_attn_butn = "FALSE", +parameter c_slot_cap_attn_ind = "FALSE", +parameter c_slot_cap_pwr_ctrl = "FALSE", +parameter c_slot_cap_pwr_ind = "FALSE", +parameter c_slot_cap_hotplug_surprise = "FALSE", +parameter c_slot_cap_hotplug_cap = "FALSE", +parameter c_slot_cap_mrl = "FALSE", +parameter c_slot_cap_elec_interlock = "FALSE", +parameter c_slot_cap_no_cmd_comp_sup = "FALSE", +parameter c_slot_cap_pwr_limit_value = "0", +parameter c_slot_cap_pwr_limit_scale = "0", +parameter c_slot_cap_physical_slot_num = "0", +parameter intx = "TRUE", +parameter int_pin = "1", +parameter c_msi_cap_on = "TRUE", +parameter c_pm_cap_next_ptr = "48", +parameter c_msi_64b_addr = "TRUE", +parameter c_msi = "0", +parameter c_msi_mult_msg_extn = "0", +parameter c_msi_per_vctr_mask_cap = "FALSE", +parameter c_msix_cap_on = "FALSE", +parameter c_msix_next_ptr = "00", +parameter c_pcie_cap_next_ptr = "00", +parameter c_msix_table_size = "000", +parameter c_msix_table_offset = "0", +parameter c_msix_table_bir = "0", +parameter c_msix_pba_offset = "0", +parameter c_msix_pba_bir = "0", +parameter dsi = "0", +parameter c_dsi_bool = "FALSE", +parameter d1_sup = "0", +parameter c_d1_support = "FALSE", +parameter d2_sup = "0", +parameter c_d2_support = "FALSE", +parameter pme_sup = "0F", +parameter c_pme_support = "0F", +parameter no_soft_rst = "TRUE", +parameter pwr_con_d0_state = "00", +parameter con_scl_fctr_d0_state = "0", +parameter pwr_con_d1_state = "00", +parameter con_scl_fctr_d1_state = "0", +parameter pwr_con_d2_state = "00", +parameter con_scl_fctr_d2_state = "0", +parameter pwr_con_d3_state = "00", +parameter con_scl_fctr_d3_state = "0", +parameter pwr_dis_d0_state = "00", +parameter dis_scl_fctr_d0_state = "0", +parameter pwr_dis_d1_state = "00", +parameter dis_scl_fctr_d1_state = "0", +parameter pwr_dis_d2_state = "00", +parameter dis_scl_fctr_d2_state = "0", +parameter pwr_dis_d3_state = "00", +parameter dis_scl_fctr_d3_state = "0", +parameter c_dsn_cap_enabled = "TRUE", +parameter c_dsn_base_ptr = "100", +parameter c_vc_cap_enabled = "FALSE", +parameter c_vc_base_ptr = "000", +parameter c_vc_cap_reject_snoop = "FALSE", +parameter c_vsec_cap_enabled = "FALSE", +parameter c_vsec_base_ptr = "000", +parameter c_vsec_next_ptr = "000", +parameter c_dsn_next_ptr = "000", +parameter c_vc_next_ptr = "000", +parameter c_pci_cfg_space_addr = "3F", +parameter c_ext_pci_cfg_space_addr = "3FF", +parameter c_last_cfg_dw = "10C", +parameter c_enable_msg_route = "00000000000", +parameter bram_lat = "0", +parameter c_rx_raddr_lat = "0", +parameter c_rx_rdata_lat = "2", +parameter c_rx_write_lat = "0", +parameter c_tx_raddr_lat = "0", +parameter c_tx_rdata_lat = "2", +parameter c_tx_write_lat = "0", +parameter c_ll_ack_timeout_enable = "FALSE", +parameter c_ll_ack_timeout_function = "0", +parameter c_ll_ack_timeout = "0000", +parameter c_ll_replay_timeout_enable = "FALSE", +parameter c_ll_replay_timeout_func = "1", +parameter c_ll_replay_timeout = "0000", +parameter c_dis_lane_reverse = "TRUE", +parameter c_upconfig_capable = "TRUE", +parameter c_disable_scrambling = "FALSE", +parameter c_disable_tx_aspm_l0s = "0", +parameter c_rev_gt_order = "FALSE", +parameter c_pcie_dbg_ports = "FALSE", +parameter pci_exp_ref_freq = "0", +parameter c_xlnx_ref_board = "NONE", +parameter c_pcie_blk_locn = "0", +parameter c_ur_atomic = "FALSE", +parameter c_dev_cap2_atomicop32_completer_supported = "FALSE", +parameter c_dev_cap2_atomicop64_completer_supported = "FALSE", +parameter c_dev_cap2_cas128_completer_supported = "FALSE", +parameter c_dev_cap2_tph_completer_supported = "00", +parameter c_dev_cap2_ari_forwarding_supported = "FALSE", +parameter c_dev_cap2_atomicop_routing_supported = "FALSE", +parameter c_link_cap_aspm_optionality = "FALSE", +parameter c_aer_cap_on = "FALSE", +parameter c_aer_base_ptr = "000", +parameter c_aer_cap_nextptr = "000", +parameter c_aer_cap_ecrc_check_capable = "FALSE", +parameter c_aer_cap_multiheader = "FALSE", +parameter c_aer_cap_permit_rooterr_update = "FALSE", +parameter c_rbar_cap_on = "FALSE", +parameter c_rbar_base_ptr = "000", +parameter c_rbar_cap_nextptr = "000", +parameter c_rbar_num = "0", +parameter c_rbar_cap_sup0 = "00001", +parameter c_rbar_cap_index0 = "0", +parameter c_rbar_cap_control_encodedbar0 = "00", +parameter c_rbar_cap_sup1 = "00001", +parameter c_rbar_cap_index1 = "0", +parameter c_rbar_cap_control_encodedbar1 = "00", +parameter c_rbar_cap_sup2 = "00001", +parameter c_rbar_cap_index2 = "0", +parameter c_rbar_cap_control_encodedbar2 = "00", +parameter c_rbar_cap_sup3 = "00001", +parameter c_rbar_cap_index3 = "0", +parameter c_rbar_cap_control_encodedbar3 = "00", +parameter c_rbar_cap_sup4 = "00001", +parameter c_rbar_cap_index4 = "0", +parameter c_rbar_cap_control_encodedbar4 = "00", +parameter c_rbar_cap_sup5 = "00001", +parameter c_rbar_cap_index5 = "0", +parameter c_rbar_cap_control_encodedbar5 = "00", +parameter c_recrc_check = "0", +parameter c_recrc_check_trim = "FALSE", +parameter c_disable_rx_poisoned_resp = "FALSE", +parameter c_trn_np_fc = "TRUE", +parameter c_ur_inv_req = "TRUE", +parameter c_ur_prs_response = "TRUE", +parameter c_silicon_rev = "1", +parameter c_aer_cap_optional_err_support = "000000", +parameter PIPE_SIM = "FALSE", +parameter PCIE_EXT_CLK = "TRUE", +parameter PCIE_EXT_GT_COMMON = "FALSE", +parameter EXT_CH_GT_DRP = "TRUE", +parameter TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE", +parameter SHARED_LOGIC_IN_CORE = "FALSE", +parameter PL_INTERFACE = "TRUE", +parameter CFG_MGMT_IF = "TRUE", +parameter CFG_CTL_IF = "TRUE", +parameter CFG_STATUS_IF = "TRUE", +parameter RCV_MSG_IF = "TRUE", +parameter CFG_FC_IF = "TRUE" , +parameter ERR_REPORTING_IF = "TRUE", +parameter c_aer_cap_ecrc_gen_capable = "FALSE", +parameter EXT_PIPE_INTERFACE = "FALSE", +parameter EXT_STARTUP_PRIMITIVE = "FALSE", +parameter integer LINK_CAP_MAX_LINK_WIDTH = 6'h8, +parameter integer C_DATA_WIDTH = 64, +parameter integer KEEP_WIDTH = C_DATA_WIDTH / 8, +parameter PCIE_ASYNC_EN = "FALSE", +parameter ENABLE_JTAG_DBG = "FALSE", +parameter REDUCE_OOB_FREQ = "FALSE" +) +( + + //----------------------------------------------------------------------------------------------------------------// + // 1. PCI Express (pci_exp) Interface // + //----------------------------------------------------------------------------------------------------------------// + + // Tx + output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn, + output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp, + + // Rx + input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn, + input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp, + + //----------------------------------------------------------------------------------------------------------------// + // 2. Clock & GT COMMON Sharing Interface // + //----------------------------------------------------------------------------------------------------------------// + // Shared Logic Internal + output int_pclk_out_slave, + output int_pipe_rxusrclk_out, + output [(LINK_CAP_MAX_LINK_WIDTH-1):0] int_rxoutclk_out, + output int_dclk_out, + output int_userclk1_out, + output int_userclk2_out, + output int_oobclk_out, + output int_mmcm_lock_out, + output [1:0] int_qplllock_out, + output [1:0] int_qplloutclk_out, + output [1:0] int_qplloutrefclk_out, + input [(LINK_CAP_MAX_LINK_WIDTH-1):0] int_pclk_sel_slave, + + // Shared Logic External - Clocks + input pipe_pclk_in, + input pipe_rxusrclk_in, + input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_in, + input pipe_dclk_in, + input pipe_userclk1_in, + input pipe_userclk2_in, + input pipe_oobclk_in, + input pipe_mmcm_lock_in, + + output pipe_txoutclk_out, + output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_out, + output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_pclk_sel_out, + output pipe_gen3_out, + + // Shared Logic External - GT COMMON + + input [11:0] qpll_drp_crscode, + input [17:0] qpll_drp_fsm, + input [1:0] qpll_drp_done, + input [1:0] qpll_drp_reset, + input [1:0] qpll_qplllock, + input [1:0] qpll_qplloutclk, + input [1:0] qpll_qplloutrefclk, + output qpll_qplld, + output [1:0] qpll_qpllreset, + output qpll_drp_clk, + output qpll_drp_rst_n, + output qpll_drp_ovrd, + output qpll_drp_gen3, + output qpll_drp_start, + + //----------------------------------------------------------------------------------------------------------------// + // 3. AXI-S Interface // + //----------------------------------------------------------------------------------------------------------------// + + // Common + output user_clk_out, + output user_reset_out, + output user_lnk_up, + output user_app_rdy, + + // AXI TX + //----------- + output [5:0] tx_buf_av, + output tx_err_drop, + output tx_cfg_req, + input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, + input s_axis_tx_tvalid, + output s_axis_tx_tready, + input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, + input s_axis_tx_tlast, + input [3:0] s_axis_tx_tuser, + input tx_cfg_gnt, + + // AXI RX + //----------- + output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, + output m_axis_rx_tvalid, + input m_axis_rx_tready, + output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, + output m_axis_rx_tlast, + output [21:0] m_axis_rx_tuser, + input rx_np_ok, + input rx_np_req, + + // Flow Control + output [11:0] fc_cpld, + output [7:0] fc_cplh, + output [11:0] fc_npd, + output [7:0] fc_nph, + output [11:0] fc_pd, + output [7:0] fc_ph, + input [2:0] fc_sel, + + + //----------------------------------------------------------------------------------------------------------------// + // 4. Configuration (CFG) Interface // + //----------------------------------------------------------------------------------------------------------------// + + //------------------------------------------------// + // EP and RP // + //------------------------------------------------// + output [31:0] cfg_mgmt_do, + output cfg_mgmt_rd_wr_done, + + output [15:0] cfg_status, + output [15:0] cfg_command, + output [15:0] cfg_dstatus, + output [15:0] cfg_dcommand, + output [15:0] cfg_lstatus, + output [15:0] cfg_lcommand, + output [15:0] cfg_dcommand2, + output [2:0] cfg_pcie_link_state, + + output cfg_pmcsr_pme_en, + output [1:0] cfg_pmcsr_powerstate, + output cfg_pmcsr_pme_status, + output cfg_received_func_lvl_rst, + + // Management Interface + input [31:0] cfg_mgmt_di, + input [3:0] cfg_mgmt_byte_en, + input [9:0] cfg_mgmt_dwaddr, + input cfg_mgmt_wr_en, + input cfg_mgmt_rd_en, + input cfg_mgmt_wr_readonly, + + // Error Reporting Interface + input cfg_err_ecrc, + input cfg_err_ur, + input cfg_err_cpl_timeout, + input cfg_err_cpl_unexpect, + input cfg_err_cpl_abort, + input cfg_err_posted, + input cfg_err_cor, + input cfg_err_atomic_egress_blocked, + input cfg_err_internal_cor, + input cfg_err_malformed, + input cfg_err_mc_blocked, + input cfg_err_poisoned, + input cfg_err_norecovery, + input [47:0] cfg_err_tlp_cpl_header, + output cfg_err_cpl_rdy, + input cfg_err_locked, + input cfg_err_acs, + input cfg_err_internal_uncor, + + input cfg_trn_pending, + input cfg_pm_halt_aspm_l0s, + input cfg_pm_halt_aspm_l1, + input cfg_pm_force_state_en, + input [1:0] cfg_pm_force_state, + + input [63:0] cfg_dsn, + output cfg_msg_received, + output [15:0] cfg_msg_data, + + //------------------------------------------------// + // EP Only // + //------------------------------------------------// + + // Interrupt Interface Signals + input cfg_interrupt, + output cfg_interrupt_rdy, + input cfg_interrupt_assert, + input [7:0] cfg_interrupt_di, + output [7:0] cfg_interrupt_do, + output [2:0] cfg_interrupt_mmenable, + output cfg_interrupt_msienable, + output cfg_interrupt_msixenable, + output cfg_interrupt_msixfm, + input cfg_interrupt_stat, + input [4:0] cfg_pciecap_interrupt_msgnum, + + + output cfg_to_turnoff, + input cfg_turnoff_ok, + output [7:0] cfg_bus_number, + output [4:0] cfg_device_number, + output [2:0] cfg_function_number, + input cfg_pm_wake, + + output cfg_msg_received_pm_as_nak, + output cfg_msg_received_setslotpowerlimit, + + //------------------------------------------------// + // RP Only // + //------------------------------------------------// + input cfg_pm_send_pme_to, + input [7:0] cfg_ds_bus_number, + input [4:0] cfg_ds_device_number, + input [2:0] cfg_ds_function_number, + + input cfg_mgmt_wr_rw1c_as_rw, + + output cfg_bridge_serr_en, + output cfg_slot_control_electromech_il_ctl_pulse, + output cfg_root_control_syserr_corr_err_en, + output cfg_root_control_syserr_non_fatal_err_en, + output cfg_root_control_syserr_fatal_err_en, + output cfg_root_control_pme_int_en, + output cfg_aer_rooterr_corr_err_reporting_en, + output cfg_aer_rooterr_non_fatal_err_reporting_en, + output cfg_aer_rooterr_fatal_err_reporting_en, + output cfg_aer_rooterr_corr_err_received, + output cfg_aer_rooterr_non_fatal_err_received, + output cfg_aer_rooterr_fatal_err_received, + + output cfg_msg_received_err_cor, + output cfg_msg_received_err_non_fatal, + output cfg_msg_received_err_fatal, + output cfg_msg_received_pm_pme, + output cfg_msg_received_pme_to_ack, + output cfg_msg_received_assert_int_a, + output cfg_msg_received_assert_int_b, + output cfg_msg_received_assert_int_c, + output cfg_msg_received_assert_int_d, + output cfg_msg_received_deassert_int_a, + output cfg_msg_received_deassert_int_b, + output cfg_msg_received_deassert_int_c, + output cfg_msg_received_deassert_int_d, + + //----------------------------------------------------------------------------------------------------------------// + // 5. Physical Layer Control and Status (PL) Interface // + //----------------------------------------------------------------------------------------------------------------// + + //------------------------------------------------// + // EP and RP // + //------------------------------------------------// + input [1:0] pl_directed_link_change, + input [1:0] pl_directed_link_width, + input pl_directed_link_speed, + input pl_directed_link_auton, + input pl_upstream_prefer_deemph, + + output pl_sel_lnk_rate, + output [1:0] pl_sel_lnk_width, + output [5:0] pl_ltssm_state, + output [1:0] pl_lane_reversal_mode, + + output pl_phy_lnk_up, + output [2:0] pl_tx_pm_state, + output [1:0] pl_rx_pm_state, + + output pl_link_upcfg_cap, + output pl_link_gen2_cap, + output pl_link_partner_gen2_supported, + output [2:0] pl_initial_link_width, + + output pl_directed_change_done, + + //------------------------------------------------// + // EP Only // + //------------------------------------------------// + output pl_received_hot_rst, + + //------------------------------------------------// + // RP Only // + //------------------------------------------------// + input pl_transmit_hot_rst, + input pl_downstream_deemph_source, + + //----------------------------------------------------------------------------------------------------------------// + // 6. AER interface // + //----------------------------------------------------------------------------------------------------------------// + + input [127:0] cfg_err_aer_headerlog, + input [4:0] cfg_aer_interrupt_msgnum, + output cfg_err_aer_headerlog_set, + output cfg_aer_ecrc_check_en, + output cfg_aer_ecrc_gen_en, + + //----------------------------------------------------------------------------------------------------------------// + // 7. VC interface // + //----------------------------------------------------------------------------------------------------------------// + + output [6:0] cfg_vc_tcvc_map, + + //----------------------------------------------------------------------------------------------------------------// + // 8. PCIe DRP (PCIe DRP) Interface // + //----------------------------------------------------------------------------------------------------------------// + + input pcie_drp_clk, + input pcie_drp_en, + input pcie_drp_we, + input [8:0] pcie_drp_addr, + input [15:0] pcie_drp_di, + output pcie_drp_rdy, + output [15:0] pcie_drp_do, + + //----------------------------------------------------------------------------------------------------------------// + // PCIe Fast Config: STARTUP primitive Interface - only used in Tandem configurations // + //----------------------------------------------------------------------------------------------------------------// + // This input should be used when the startup block is generated exteranl to the PCI Express Core + input startup_eos_in, // 1-bit input: This signal should be driven by the EOS output of the STARTUP primitive. + // These inputs and outputs may be use when the startup block is generated internal to the PCI Express Core. + output wire startup_cfgclk, // 1-bit output: Configuration main clock output + output wire startup_cfgmclk, // 1-bit output: Configuration internal oscillator clock output + output wire startup_eos, // 1-bit output: Active high output signal indicating the End Of Startup + output wire startup_preq, // 1-bit output: PROGRAM request to fabric output + input wire startup_clk, // 1-bit input: User start-up clock input + input wire startup_gsr, // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name) + input wire startup_gts, // 1-bit input: Global 3-state input (GTS cannot be used for the port name) + input wire startup_keyclearb, // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) + input wire startup_pack, // 1-bit input: PROGRAM acknowledge input + input wire startup_usrcclko, // 1-bit input: User CCLK input + input wire startup_usrcclkts, // 1-bit input: User CCLK 3-state enable input + input wire startup_usrdoneo, // 1-bit input: User DONE pin output control + input wire startup_usrdonets, // 1-bit input: User DONE 3-state enable output + + //----------------------------------------------------------------------------------------------------------------// + // PCIe Fast Config: ICAP primitive Interface - only used in Tandem PCIe configuration // + //----------------------------------------------------------------------------------------------------------------// + input wire icap_clk, + input wire icap_csib, + input wire icap_rdwrb, + input wire [31:0] icap_i, + output wire [31:0] icap_o, + + + input [ 2:0] pipe_txprbssel, + input [ 2:0] pipe_rxprbssel, + input pipe_txprbsforceerr, + input pipe_rxprbscntreset, + input [ 2:0] pipe_loopback, + + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_rxprbserr, + input [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_txinhibit, + + output [4:0] pipe_rst_fsm, + output [11:0] pipe_qrst_fsm, + output [(LINK_CAP_MAX_LINK_WIDTH*5)-1:0] pipe_rate_fsm, + output [(LINK_CAP_MAX_LINK_WIDTH*6)-1:0] pipe_sync_fsm_tx, + output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_sync_fsm_rx, + output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_drp_fsm, + + output pipe_rst_idle, + output pipe_qrst_idle, + output pipe_rate_idle, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_eyescandataerror, + output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxstatus, + output [(LINK_CAP_MAX_LINK_WIDTH*15)-1:0] pipe_dmonitorout, + + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_cpll_lock, + output [(LINK_CAP_MAX_LINK_WIDTH-1)>>2:0] pipe_qpll_lock, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxpmaresetdone, + output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxbufstatus, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphaligndone, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphinitdone, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txdlysresetdone, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxphaligndone, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxdlysresetdone, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxsyncdone, + output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxdisperr, + output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxnotintable, + output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxcommadet, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] gt_ch_drp_rdy, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_0, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_1, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_2, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_3, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_4, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_5, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_6, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_7, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_8, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_9, + output [31:0] pipe_debug, + + //--------------Channel DRP--------------------------------- + output ext_ch_gt_drpclk, + input [(LINK_CAP_MAX_LINK_WIDTH*9)-1:0] ext_ch_gt_drpaddr, + input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpen, + input [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0] ext_ch_gt_drpdi, + input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpwe, + + output [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0] ext_ch_gt_drpdo, + output [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drprdy, + + //----------------------------------------------------------------------------------------------------------------// + // PIPE PORTS to TOP Level For PIPE SIMULATION with 3rd Party IP/BFM/Xilinx BFM + //----------------------------------------------------------------------------------------------------------------// + input wire [11:0] common_commands_in, + input wire [24:0] pipe_rx_0_sigs, + input wire [24:0] pipe_rx_1_sigs, + input wire [24:0] pipe_rx_2_sigs, + input wire [24:0] pipe_rx_3_sigs, + input wire [24:0] pipe_rx_4_sigs, + input wire [24:0] pipe_rx_5_sigs, + input wire [24:0] pipe_rx_6_sigs, + input wire [24:0] pipe_rx_7_sigs, + + output wire [11:0] common_commands_out, + output wire [24:0] pipe_tx_0_sigs, + output wire [24:0] pipe_tx_1_sigs, + output wire [24:0] pipe_tx_2_sigs, + output wire [24:0] pipe_tx_3_sigs, + output wire [24:0] pipe_tx_4_sigs, + output wire [24:0] pipe_tx_5_sigs, + output wire [24:0] pipe_tx_6_sigs, + output wire [24:0] pipe_tx_7_sigs, + //----------------------------------------------------------------------------------------------------------------// + input wire pipe_mmcm_rst_n, // Async | Async + input wire sys_clk, + input wire sys_rst_n + +); + +pcie_7x_0_core_top # ( + .LINK_CAP_MAX_LINK_WIDTH (LINK_CAP_MAX_LINK_WIDTH), + .C_DATA_WIDTH (C_DATA_WIDTH), + .KEEP_WIDTH (KEEP_WIDTH) + ) inst + ( + .pci_exp_txn(pci_exp_txn), + .pci_exp_txp(pci_exp_txp), + .pci_exp_rxn(pci_exp_rxn), + .pci_exp_rxp(pci_exp_rxp), + .int_pclk_out_slave(int_pclk_out_slave), + .int_pipe_rxusrclk_out(int_pipe_rxusrclk_out), + .int_rxoutclk_out(int_rxoutclk_out), + .int_dclk_out(int_dclk_out), + .int_userclk1_out(int_userclk1_out), + .int_mmcm_lock_out(int_mmcm_lock_out), + .int_userclk2_out(int_userclk2_out), + .int_oobclk_out(int_oobclk_out), + .int_qplllock_out(int_qplllock_out), + .int_qplloutclk_out(int_qplloutclk_out), + .int_qplloutrefclk_out(int_qplloutrefclk_out), + .int_pclk_sel_slave(int_pclk_sel_slave), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .pipe_rxoutclk_in(pipe_rxoutclk_in), + .pipe_dclk_in(pipe_dclk_in), + .pipe_userclk1_in(pipe_userclk1_in), + .pipe_userclk2_in(pipe_userclk2_in), + .pipe_oobclk_in(pipe_oobclk_in), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_txoutclk_out(pipe_txoutclk_out), + .pipe_rxoutclk_out(pipe_rxoutclk_out), + .pipe_pclk_sel_out(pipe_pclk_sel_out), + .pipe_gen3_out(pipe_gen3_out), + .user_clk_out(user_clk_out), + .user_reset_out(user_reset_out), + .user_lnk_up(user_lnk_up), + .user_app_rdy(user_app_rdy), + .tx_buf_av(tx_buf_av), + .tx_err_drop(tx_err_drop), + .tx_cfg_req(tx_cfg_req), + .s_axis_tx_tready(s_axis_tx_tready), + .s_axis_tx_tdata(s_axis_tx_tdata), + .s_axis_tx_tkeep(s_axis_tx_tkeep), + .s_axis_tx_tuser(s_axis_tx_tuser), + .s_axis_tx_tlast(s_axis_tx_tlast), + .s_axis_tx_tvalid(s_axis_tx_tvalid), + .tx_cfg_gnt(tx_cfg_gnt), + .m_axis_rx_tdata(m_axis_rx_tdata), + .m_axis_rx_tkeep(m_axis_rx_tkeep), + .m_axis_rx_tlast(m_axis_rx_tlast), + .m_axis_rx_tvalid(m_axis_rx_tvalid), + .m_axis_rx_tready(m_axis_rx_tready), + .m_axis_rx_tuser(m_axis_rx_tuser), + .rx_np_ok(rx_np_ok), + .rx_np_req(rx_np_req), + .fc_cpld(fc_cpld), + .fc_cplh(fc_cplh), + .fc_npd(fc_npd), + .fc_nph(fc_nph), + .fc_pd(fc_pd), + .fc_ph(fc_ph), + .fc_sel(fc_sel), + .cfg_status(cfg_status), + .cfg_command(cfg_command), + .cfg_dstatus(cfg_dstatus), + .cfg_dcommand(cfg_dcommand), + .cfg_lstatus(cfg_lstatus), + .cfg_lcommand(cfg_lcommand), + .cfg_dcommand2(cfg_dcommand2), + .cfg_pcie_link_state(cfg_pcie_link_state), + .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en), + .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate), + .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status), + .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst), + .cfg_mgmt_do(cfg_mgmt_do), + .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done), + .cfg_mgmt_di(cfg_mgmt_di), + .cfg_mgmt_byte_en(cfg_mgmt_byte_en), + .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr), + .cfg_mgmt_wr_en(cfg_mgmt_wr_en), + .cfg_mgmt_rd_en(cfg_mgmt_rd_en), + .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly), + .cfg_err_ecrc(cfg_err_ecrc), + .cfg_err_ur(cfg_err_ur), + .cfg_err_cpl_timeout(cfg_err_cpl_timeout), + .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect), + .cfg_err_cpl_abort(cfg_err_cpl_abort), + .cfg_err_posted(cfg_err_posted), + .cfg_err_cor(cfg_err_cor), + .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked), + .cfg_err_internal_cor(cfg_err_internal_cor), + .cfg_err_malformed(cfg_err_malformed), + .cfg_err_mc_blocked(cfg_err_mc_blocked), + .cfg_err_poisoned(cfg_err_poisoned), + .cfg_err_norecovery(cfg_err_norecovery), + .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header), + .cfg_err_cpl_rdy(cfg_err_cpl_rdy), + .cfg_err_locked(cfg_err_locked), + .cfg_err_acs(cfg_err_acs), + .cfg_err_internal_uncor(cfg_err_internal_uncor), + .cfg_trn_pending(cfg_trn_pending), + .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s), + .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1), + .cfg_pm_force_state_en(cfg_pm_force_state_en), + .cfg_pm_force_state(cfg_pm_force_state), + .cfg_dsn(cfg_dsn), + .cfg_msg_received(cfg_msg_received), + .cfg_msg_data(cfg_msg_data), + .cfg_interrupt(cfg_interrupt), + .cfg_interrupt_rdy(cfg_interrupt_rdy), + .cfg_interrupt_assert(cfg_interrupt_assert), + .cfg_interrupt_di(cfg_interrupt_di), + .cfg_interrupt_do(cfg_interrupt_do), + .cfg_interrupt_mmenable(cfg_interrupt_mmenable), + .cfg_interrupt_msienable(cfg_interrupt_msienable), + .cfg_interrupt_msixenable(cfg_interrupt_msixenable), + .cfg_interrupt_msixfm(cfg_interrupt_msixfm), + .cfg_interrupt_stat(cfg_interrupt_stat), + .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum), + .cfg_to_turnoff(cfg_to_turnoff), + .cfg_turnoff_ok(cfg_turnoff_ok), + .cfg_bus_number(cfg_bus_number), + .cfg_device_number(cfg_device_number), + .cfg_function_number(cfg_function_number), + .cfg_pm_wake(cfg_pm_wake), + .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit), + .cfg_pm_send_pme_to(cfg_pm_send_pme_to), + .cfg_ds_bus_number(cfg_ds_bus_number), + .cfg_ds_device_number(cfg_ds_device_number), + .cfg_ds_function_number(cfg_ds_function_number), + .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw), + .cfg_bridge_serr_en(cfg_bridge_serr_en), + .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse), + .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en), + .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en), + .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en), + .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en), + .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en), + .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en), + .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en), + .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received), + .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received), + .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received), + .cfg_msg_received_err_cor(cfg_msg_received_err_cor), + .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal), + .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal), + .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak), + .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme), + .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack), + .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a), + .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b), + .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c), + .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d), + .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a), + .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b), + .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c), + .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d), + .pl_directed_link_change(pl_directed_link_change), + .pl_directed_link_width(pl_directed_link_width), + .pl_directed_link_speed(pl_directed_link_speed), + .pl_directed_link_auton(pl_directed_link_auton), + .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph), + .pl_sel_lnk_rate(pl_sel_lnk_rate), + .pl_sel_lnk_width(pl_sel_lnk_width), + .pl_ltssm_state(pl_ltssm_state), + .pl_lane_reversal_mode(pl_lane_reversal_mode), + .pl_phy_lnk_up(pl_phy_lnk_up), + .pl_tx_pm_state(pl_tx_pm_state), + .pl_rx_pm_state(pl_rx_pm_state), + .pl_link_upcfg_cap(pl_link_upcfg_cap), + .pl_link_gen2_cap(pl_link_gen2_cap), + .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported), + .pl_initial_link_width(pl_initial_link_width), + .pl_directed_change_done(pl_directed_change_done), + .pl_received_hot_rst(pl_received_hot_rst), + .pl_transmit_hot_rst(pl_transmit_hot_rst), + .pl_downstream_deemph_source(pl_downstream_deemph_source), + .cfg_err_aer_headerlog(cfg_err_aer_headerlog), + .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum), + .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set), + .cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en), + .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en), + .cfg_vc_tcvc_map(cfg_vc_tcvc_map), + .pcie_drp_clk(pcie_drp_clk), + .pcie_drp_en(pcie_drp_en), + .pcie_drp_we(pcie_drp_we), + .pcie_drp_addr(pcie_drp_addr), + .pcie_drp_di(pcie_drp_di), + .pcie_drp_rdy(pcie_drp_rdy), + .pcie_drp_do(pcie_drp_do), + + // STARTUP primitive interface - Can only be used with Tandem Configurations + // This input should be used when the startup block is generated exteranl to the PCI Express Core + .startup_eos_in(startup_eos_in), // 1-bit input: This signal should be driven by the EOS output of the STARTUP primitive. + // These inputs and outputs may be use when the startup block is generated internal to the PCI Express Core. + .startup_cfgclk(startup_cfgclk), // 1-bit output: Configuration main clock output + .startup_cfgmclk(startup_cfgmclk), // 1-bit output: Configuration internal oscillator clock output + .startup_eos(startup_eos), // 1-bit output: Active high output signal indicating the End Of Startup. + .startup_preq(startup_preq), // 1-bit output: PROGRAM request to fabric output + .startup_clk(startup_clk), // 1-bit input: User start-up clock input + .startup_gsr(startup_gsr), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name) + .startup_gts(startup_gts), // 1-bit input: Global 3-state input (GTS cannot be used for the port name) + .startup_keyclearb(startup_keyclearb), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) + .startup_pack(startup_pack), // 1-bit input: PROGRAM acknowledge input + .startup_usrcclko(startup_usrcclko), // 1-bit input: User CCLK input + .startup_usrcclkts(startup_usrcclkts), // 1-bit input: User CCLK 3-state enable input + .startup_usrdoneo(startup_usrdoneo), // 1-bit input: User DONE pin output control + .startup_usrdonets(startup_usrdonets), // 1-bit input: User DONE 3-state enable output + + // ICAP primitive interface - Can only be used with Tandem PCIe Configuration + .icap_clk(icap_clk), + .icap_csib(icap_csib), + .icap_rdwrb(icap_rdwrb), + .icap_i(icap_i), + .icap_o(icap_o), + + //External GT COMMON Ports + + .qpll_drp_crscode ( qpll_drp_crscode ), + .qpll_drp_fsm ( qpll_drp_fsm ), + .qpll_drp_done ( qpll_drp_done ), + .qpll_drp_reset ( qpll_drp_reset ), + .qpll_qplllock ( qpll_qplllock ), + .qpll_qplloutclk ( qpll_qplloutclk ), + .qpll_qplloutrefclk ( qpll_qplloutrefclk ), + .qpll_qplld ( qpll_qplld ), + .qpll_qpllreset ( qpll_qpllreset ), + .qpll_drp_clk ( qpll_drp_clk ), + .qpll_drp_rst_n ( qpll_drp_rst_n ), + .qpll_drp_ovrd ( qpll_drp_ovrd ), + .qpll_drp_gen3 ( qpll_drp_gen3), + .qpll_drp_start ( qpll_drp_start ), + + //------------TRANSCEIVER DEBUG----------------------------------- + //Drive these inputs to 0s + .ext_ch_gt_drpclk (ext_ch_gt_drpclk), + .ext_ch_gt_drpaddr (ext_ch_gt_drpaddr), + .ext_ch_gt_drpen (ext_ch_gt_drpen), + .ext_ch_gt_drpdi (ext_ch_gt_drpdi), + .ext_ch_gt_drpwe (ext_ch_gt_drpwe), + .ext_ch_gt_drpdo (ext_ch_gt_drpdo), + .ext_ch_gt_drprdy (ext_ch_gt_drprdy ), + + .pipe_txprbssel (pipe_txprbssel), + .pipe_rxprbssel (pipe_rxprbssel), + .pipe_txprbsforceerr (pipe_txprbsforceerr), + .pipe_rxprbscntreset (pipe_rxprbscntreset), + .pipe_loopback (pipe_loopback ), + .pipe_rxprbserr (pipe_rxprbserr), + .pipe_txinhibit (pipe_txinhibit), + .pipe_rst_fsm (pipe_rst_fsm), + .pipe_qrst_fsm (pipe_qrst_fsm), + .pipe_rate_fsm (pipe_rate_fsm), + .pipe_sync_fsm_tx (pipe_sync_fsm_tx), + .pipe_sync_fsm_rx (pipe_sync_fsm_rx), + .pipe_drp_fsm (pipe_drp_fsm), + .pipe_rst_idle (pipe_rst_idle), + .pipe_qrst_idle (pipe_qrst_idle), + .pipe_rate_idle (pipe_rate_idle), + .pipe_eyescandataerror (pipe_eyescandataerror), + .pipe_rxstatus (pipe_rxstatus), + .pipe_dmonitorout (pipe_dmonitorout), + .pipe_cpll_lock ( pipe_cpll_lock ), + .pipe_qpll_lock ( pipe_qpll_lock ), + .pipe_rxpmaresetdone ( pipe_rxpmaresetdone ), + .pipe_rxbufstatus ( pipe_rxbufstatus ), + .pipe_txphaligndone ( pipe_txphaligndone ), + .pipe_txphinitdone ( pipe_txphinitdone ), + .pipe_txdlysresetdone ( pipe_txdlysresetdone ), + .pipe_rxphaligndone ( pipe_rxphaligndone ), + .pipe_rxdlysresetdone ( pipe_rxdlysresetdone ), + .pipe_rxsyncdone ( pipe_rxsyncdone ), + .pipe_rxdisperr ( pipe_rxdisperr ), + .pipe_rxnotintable ( pipe_rxnotintable ), + .pipe_rxcommadet ( pipe_rxcommadet ), + + //---------- CHANNEL DRP -------------------------------- + .gt_ch_drp_rdy (gt_ch_drp_rdy), + .pipe_debug_0 (pipe_debug_0), + .pipe_debug_1 (pipe_debug_1), + .pipe_debug_2 (pipe_debug_2), + .pipe_debug_3 (pipe_debug_3), + .pipe_debug_4 (pipe_debug_4), + .pipe_debug_5 (pipe_debug_5), + .pipe_debug_6 (pipe_debug_6), + .pipe_debug_7 (pipe_debug_7), + .pipe_debug_8 (pipe_debug_8), + .pipe_debug_9 (pipe_debug_9), + .pipe_debug (pipe_debug), + + .common_commands_in ( common_commands_in ), + .pipe_rx_0_sigs ( pipe_rx_0_sigs ), + .pipe_rx_1_sigs ( pipe_rx_1_sigs ), + .pipe_rx_2_sigs ( pipe_rx_2_sigs ), + .pipe_rx_3_sigs ( pipe_rx_3_sigs ), + .pipe_rx_4_sigs ( pipe_rx_4_sigs ), + .pipe_rx_5_sigs ( pipe_rx_5_sigs ), + .pipe_rx_6_sigs ( pipe_rx_6_sigs ), + .pipe_rx_7_sigs ( pipe_rx_7_sigs ), + + .common_commands_out ( common_commands_out ), + .pipe_tx_0_sigs ( pipe_tx_0_sigs ), + .pipe_tx_1_sigs ( pipe_tx_1_sigs ), + .pipe_tx_2_sigs ( pipe_tx_2_sigs ), + .pipe_tx_3_sigs ( pipe_tx_3_sigs ), + .pipe_tx_4_sigs ( pipe_tx_4_sigs ), + .pipe_tx_5_sigs ( pipe_tx_5_sigs ), + .pipe_tx_6_sigs ( pipe_tx_6_sigs ), + .pipe_tx_7_sigs ( pipe_tx_7_sigs ), + + .pipe_mmcm_rst_n (pipe_mmcm_rst_n), // Async | Async + .sys_clk (sys_clk), + .sys_rst_n (sys_rst_n) + ); + +endmodule + + + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_7x.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_7x.v new file mode 100644 index 0000000..f41b1c5 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_7x.v @@ -0,0 +1,1634 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pcie_7x.v +// Version : 3.3 +// +// Description: Solution wrapper for Virtex7 Hard Block for PCI Express +// +// +// +//-------------------------------------------------------------------------------- +`ifndef PCIE_2LM +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pcie_7x # ( + // PCIE_2_1 params + parameter [11:0] AER_BASE_PTR = 12'h140, + parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE", + parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE", + parameter [15:0] AER_CAP_ID = 16'h0001, + parameter AER_CAP_MULTIHEADER = "FALSE", + parameter [11:0] AER_CAP_NEXTPTR = 12'h178, + parameter AER_CAP_ON = "FALSE", + parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000, + parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE", + parameter [3:0] AER_CAP_VERSION = 4'h1, + parameter ALLOW_X8_GEN2 = "FALSE", + parameter [31:0] BAR0 = 32'hFFFFFF00, + parameter [31:0] BAR1 = 32'hFFFF0000, + parameter [31:0] BAR2 = 32'hFFFF000C, + parameter [31:0] BAR3 = 32'hFFFFFFFF, + parameter [31:0] BAR4 = 32'h00000000, + parameter [31:0] BAR5 = 32'h00000000, + parameter [7:0] CAPABILITIES_PTR = 8'h40, + parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000, + parameter CFG_ECRC_ERR_CPLSTAT = 0, + parameter [23:0] CLASS_CODE = 24'h000000, + parameter CMD_INTX_IMPLEMENTED = "TRUE", + parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE", + parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0, + parameter [6:0] CRM_MODULE_RSTS = 7'h00, + parameter C_DATA_WIDTH = 64, + parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, + parameter KEEP_WIDTH = C_DATA_WIDTH / 8, + parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE", + parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE", + parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE", + parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE", + parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE", + parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE", + parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE", + parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE", + parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0, + parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE", + parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0, + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE", + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE", + parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0, + parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0, + parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE", + parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE", + parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2, + parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0, + parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE", + parameter integer DEV_CAP_RSVD_14_12 = 0, + parameter integer DEV_CAP_RSVD_17_16 = 0, + parameter integer DEV_CAP_RSVD_31_29 = 0, + parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE", + parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE", + parameter DISABLE_ASPM_L1_TIMER = "FALSE", + parameter DISABLE_BAR_FILTERING = "FALSE", + parameter DISABLE_ERR_MSG = "FALSE", + parameter DISABLE_ID_CHECK = "FALSE", + parameter DISABLE_LANE_REVERSAL = "FALSE", + parameter DISABLE_LOCKED_FILTER = "FALSE", + parameter DISABLE_PPM_FILTER = "FALSE", + parameter DISABLE_RX_POISONED_RESP = "FALSE", + parameter DISABLE_RX_TC_FILTER = "FALSE", + parameter DISABLE_SCRAMBLING = "FALSE", + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00, + parameter [11:0] DSN_BASE_PTR = 12'h100, + parameter [15:0] DSN_CAP_ID = 16'h0003, + parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C, + parameter DSN_CAP_ON = "TRUE", + parameter [3:0] DSN_CAP_VERSION = 4'h1, + parameter [10:0] ENABLE_MSG_ROUTE = 11'h000, + parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE", + parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE", + parameter ENTER_RVRY_EI_L0 = "TRUE", + parameter EXIT_LOOPBACK_ON_EI = "TRUE", + parameter [31:0] EXPANSION_ROM = 32'hFFFFF001, + parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F, + parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF, + parameter [7:0] HEADER_TYPE = 8'h00, + parameter [4:0] INFER_EI = 5'h00, + parameter [7:0] INTERRUPT_PIN = 8'h01, + parameter INTERRUPT_STAT_AUTO = "TRUE", + parameter IS_SWITCH = "FALSE", + parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF, + parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE", + parameter integer LINK_CAP_ASPM_SUPPORT = 1, + parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE", + parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE", + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7, + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7, + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7, + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7, + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7, + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7, + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7, + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7, + parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE", + parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, + parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, + parameter integer LINK_CAP_RSVD_23 = 0, + parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE", + parameter integer LINK_CONTROL_RCB = 0, + parameter LINK_CTRL2_DEEMPHASIS = "FALSE", + parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE", + parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2, + parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE", + parameter [14:0] LL_ACK_TIMEOUT = 15'h0000, + parameter LL_ACK_TIMEOUT_EN = "FALSE", + parameter integer LL_ACK_TIMEOUT_FUNC = 0, + parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000, + parameter LL_REPLAY_TIMEOUT_EN = "FALSE", + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0, + parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01, + parameter MPS_FORCE = "FALSE", + parameter [7:0] MSIX_BASE_PTR = 8'h9C, + parameter [7:0] MSIX_CAP_ID = 8'h11, + parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00, + parameter MSIX_CAP_ON = "FALSE", + parameter integer MSIX_CAP_PBA_BIR = 0, + parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000, + parameter [7:0] MSI_BASE_PTR = 8'h48, + parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE", + parameter [7:0] MSI_CAP_ID = 8'h05, + parameter integer MSI_CAP_MULTIMSGCAP = 0, + parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0, + parameter [7:0] MSI_CAP_NEXTPTR = 8'h60, + parameter MSI_CAP_ON = "FALSE", + parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE", + parameter integer N_FTS_COMCLK_GEN1 = 255, + parameter integer N_FTS_COMCLK_GEN2 = 255, + parameter integer N_FTS_GEN1 = 255, + parameter integer N_FTS_GEN2 = 255, + parameter [7:0] PCIE_BASE_PTR = 8'h60, + parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10, + parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2, + parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0, + parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C, + parameter PCIE_CAP_ON = "TRUE", + parameter integer PCIE_CAP_RSVD_15_14 = 0, + parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE", + parameter integer PCIE_REVISION = 2, + parameter integer PL_AUTO_CONFIG = 0, + parameter PL_FAST_TRAIN = "FALSE", + parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000, + parameter PM_ASPML0S_TIMEOUT_EN = "FALSE", + parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0, + parameter PM_ASPM_FASTEXIT = "FALSE", + parameter [7:0] PM_BASE_PTR = 8'h40, + parameter integer PM_CAP_AUXCURRENT = 0, + parameter PM_CAP_D1SUPPORT = "TRUE", + parameter PM_CAP_D2SUPPORT = "TRUE", + parameter PM_CAP_DSI = "FALSE", + parameter [7:0] PM_CAP_ID = 8'h01, + parameter [7:0] PM_CAP_NEXTPTR = 8'h48, + parameter PM_CAP_ON = "TRUE", + parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F, + parameter PM_CAP_PME_CLOCK = "FALSE", + parameter integer PM_CAP_RSVD_04 = 0, + parameter integer PM_CAP_VERSION = 3, + parameter PM_CSR_B2B3 = "FALSE", + parameter PM_CSR_BPCCEN = "FALSE", + parameter PM_CSR_NOSOFTRST = "TRUE", + parameter [7:0] PM_DATA0 = 8'h01, + parameter [7:0] PM_DATA1 = 8'h01, + parameter [7:0] PM_DATA2 = 8'h01, + parameter [7:0] PM_DATA3 = 8'h01, + parameter [7:0] PM_DATA4 = 8'h01, + parameter [7:0] PM_DATA5 = 8'h01, + parameter [7:0] PM_DATA6 = 8'h01, + parameter [7:0] PM_DATA7 = 8'h01, + parameter [1:0] PM_DATA_SCALE0 = 2'h1, + parameter [1:0] PM_DATA_SCALE1 = 2'h1, + parameter [1:0] PM_DATA_SCALE2 = 2'h1, + parameter [1:0] PM_DATA_SCALE3 = 2'h1, + parameter [1:0] PM_DATA_SCALE4 = 2'h1, + parameter [1:0] PM_DATA_SCALE5 = 2'h1, + parameter [1:0] PM_DATA_SCALE6 = 2'h1, + parameter [1:0] PM_DATA_SCALE7 = 2'h1, + parameter PM_MF = "FALSE", + parameter [11:0] RBAR_BASE_PTR = 12'h178, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00, + parameter [15:0] RBAR_CAP_ID = 16'h0015, + parameter [2:0] RBAR_CAP_INDEX0 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX1 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX2 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX3 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX4 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX5 = 3'h0, + parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000, + parameter RBAR_CAP_ON = "FALSE", + parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000, + parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000, + parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000, + parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000, + parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000, + parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000, + parameter [3:0] RBAR_CAP_VERSION = 4'h1, + parameter [2:0] RBAR_NUM = 3'h1, + parameter integer RECRC_CHK = 0, + parameter RECRC_CHK_TRIM = "FALSE", + parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE", + parameter [1:0] RP_AUTO_SPD = 2'h1, + parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f, + parameter SELECT_DLL_IF = "FALSE", + parameter SIM_VERSION = "1.0", + parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE", + parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE", + parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE", + parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE", + parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE", + parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE", + parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE", + parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000, + parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE", + parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE", + parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0, + parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00, + parameter integer SPARE_BIT0 = 0, + parameter integer SPARE_BIT1 = 0, + parameter integer SPARE_BIT2 = 0, + parameter integer SPARE_BIT3 = 0, + parameter integer SPARE_BIT4 = 0, + parameter integer SPARE_BIT5 = 0, + parameter integer SPARE_BIT6 = 0, + parameter integer SPARE_BIT7 = 0, + parameter integer SPARE_BIT8 = 0, + parameter [7:0] SPARE_BYTE0 = 8'h00, + parameter [7:0] SPARE_BYTE1 = 8'h00, + parameter [7:0] SPARE_BYTE2 = 8'h00, + parameter [7:0] SPARE_BYTE3 = 8'h00, + parameter [31:0] SPARE_WORD0 = 32'h00000000, + parameter [31:0] SPARE_WORD1 = 32'h00000000, + parameter [31:0] SPARE_WORD2 = 32'h00000000, + parameter [31:0] SPARE_WORD3 = 32'h00000000, + parameter SSL_MESSAGE_AUTO = "FALSE", + parameter TECRC_EP_INV = "FALSE", + parameter TL_RBYPASS = "FALSE", + parameter integer TL_RX_RAM_RADDR_LATENCY = 0, + parameter integer TL_RX_RAM_RDATA_LATENCY = 2, + parameter integer TL_RX_RAM_WRITE_LATENCY = 0, + parameter TL_TFC_DISABLE = "FALSE", + parameter TL_TX_CHECKS_DISABLE = "FALSE", + parameter integer TL_TX_RAM_RADDR_LATENCY = 0, + parameter integer TL_TX_RAM_RDATA_LATENCY = 2, + parameter integer TL_TX_RAM_WRITE_LATENCY = 0, + parameter TRN_DW = "FALSE", + parameter TRN_NP_FC = "FALSE", + parameter UPCONFIG_CAPABLE = "TRUE", + parameter UPSTREAM_FACING = "TRUE", + parameter UR_ATOMIC = "TRUE", + parameter UR_CFG1 = "TRUE", + parameter UR_INV_REQ = "TRUE", + parameter UR_PRS_RESPONSE = "TRUE", + parameter USER_CLK2_DIV2 = "FALSE", + parameter integer USER_CLK_FREQ = 3, + parameter USE_RID_PINS = "FALSE", + parameter VC0_CPL_INFINITE = "TRUE", + parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF, + parameter integer VC0_TOTAL_CREDITS_CD = 127, + parameter integer VC0_TOTAL_CREDITS_CH = 31, + parameter integer VC0_TOTAL_CREDITS_NPD = 24, + parameter integer VC0_TOTAL_CREDITS_NPH = 12, + parameter integer VC0_TOTAL_CREDITS_PD = 288, + parameter integer VC0_TOTAL_CREDITS_PH = 32, + parameter integer VC0_TX_LASTPACKET = 31, + parameter [11:0] VC_BASE_PTR = 12'h10C, + parameter [15:0] VC_CAP_ID = 16'h0002, + parameter [11:0] VC_CAP_NEXTPTR = 12'h000, + parameter VC_CAP_ON = "FALSE", + parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE", + parameter [3:0] VC_CAP_VERSION = 4'h1, + parameter [11:0] VSEC_BASE_PTR = 12'h128, + parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234, + parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018, + parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1, + parameter [15:0] VSEC_CAP_ID = 16'h000B, + parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE", + parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140, + parameter VSEC_CAP_ON = "FALSE", + parameter [3:0] VSEC_CAP_VERSION = 4'h1, + parameter ENABLE_JTAG_DBG = "FALSE" +) +( + input wire [C_DATA_WIDTH-1:0] trn_td, + input wire [REM_WIDTH-1:0] trn_trem, + input wire trn_tsof, + input wire trn_teof, + input wire trn_tsrc_rdy, + input wire trn_tsrc_dsc, + input wire trn_terrfwd, + input wire trn_tecrc_gen, + input wire trn_tstr, + input wire trn_tcfg_gnt, + input wire trn_rdst_rdy, + input wire trn_rnp_req, + input wire trn_rfcp_ret, + input wire trn_rnp_ok, + input wire [2:0] trn_fc_sel, + input wire [31:0] trn_tdllp_data, + input wire trn_tdllp_src_rdy, + input wire ll2_tlp_rcv, + input wire ll2_send_enter_l1, + input wire ll2_send_enter_l23, + input wire ll2_send_as_req_l1, + input wire ll2_send_pm_ack, + input wire [4:0] pl2_directed_lstate, + input wire ll2_suspend_now, + input wire tl2_ppm_suspend_req, + input wire tl2_aspm_suspend_credit_check, + input wire [1:0] pl_directed_link_change, + input wire [1:0] pl_directed_link_width, + input wire pl_directed_link_speed, + input wire pl_directed_link_auton, + input wire pl_upstream_prefer_deemph, + input wire pl_downstream_deemph_source, + input wire pl_directed_ltssm_new_vld, + input wire [5:0] pl_directed_ltssm_new, + input wire pl_directed_ltssm_stall, + input wire [1:0] pipe_rx0_char_is_k, + input wire [1:0] pipe_rx1_char_is_k, + input wire [1:0] pipe_rx2_char_is_k, + input wire [1:0] pipe_rx3_char_is_k, + input wire [1:0] pipe_rx4_char_is_k, + input wire [1:0] pipe_rx5_char_is_k, + input wire [1:0] pipe_rx6_char_is_k, + input wire [1:0] pipe_rx7_char_is_k, + input wire pipe_rx0_valid, + input wire pipe_rx1_valid, + input wire pipe_rx2_valid, + input wire pipe_rx3_valid, + input wire pipe_rx4_valid, + input wire pipe_rx5_valid, + input wire pipe_rx6_valid, + input wire pipe_rx7_valid, + input wire [15:0] pipe_rx0_data, + input wire [15:0] pipe_rx1_data, + input wire [15:0] pipe_rx2_data, + input wire [15:0] pipe_rx3_data, + input wire [15:0] pipe_rx4_data, + input wire [15:0] pipe_rx5_data, + input wire [15:0] pipe_rx6_data, + input wire [15:0] pipe_rx7_data, + input wire pipe_rx0_chanisaligned, + input wire pipe_rx1_chanisaligned, + input wire pipe_rx2_chanisaligned, + input wire pipe_rx3_chanisaligned, + input wire pipe_rx4_chanisaligned, + input wire pipe_rx5_chanisaligned, + input wire pipe_rx6_chanisaligned, + input wire pipe_rx7_chanisaligned, + input wire [2:0] pipe_rx0_status, + input wire [2:0] pipe_rx1_status, + input wire [2:0] pipe_rx2_status, + input wire [2:0] pipe_rx3_status, + input wire [2:0] pipe_rx4_status, + input wire [2:0] pipe_rx5_status, + input wire [2:0] pipe_rx6_status, + input wire [2:0] pipe_rx7_status, + input wire pipe_rx0_phy_status, + input wire pipe_rx1_phy_status, + input wire pipe_rx2_phy_status, + input wire pipe_rx3_phy_status, + input wire pipe_rx4_phy_status, + input wire pipe_rx5_phy_status, + input wire pipe_rx6_phy_status, + input wire pipe_rx7_phy_status, + input wire pipe_rx0_elec_idle, + input wire pipe_rx1_elec_idle, + input wire pipe_rx2_elec_idle, + input wire pipe_rx3_elec_idle, + input wire pipe_rx4_elec_idle, + input wire pipe_rx5_elec_idle, + input wire pipe_rx6_elec_idle, + input wire pipe_rx7_elec_idle, + input wire pipe_clk, + input wire user_clk, + input wire user_clk2, + input wire user_clk_prebuf, + input wire user_clk_prebuf_en, +`ifdef B_TESTMODE + input wire scanmode_n, + input wire scanenable_n, + input wire edt_clk, + input wire edt_bypass, + input wire edt_update, + input wire edt_configuration, + input wire edt_single_bypass_chain, + input wire edt_channels_in1, + input wire edt_channels_in2, + input wire edt_channels_in3, + input wire edt_channels_in4, + input wire edt_channels_in5, + input wire edt_channels_in6, + input wire edt_channels_in7, + input wire edt_channels_in8, + input wire pmv_enable_n, + input wire [2:0] pmv_select, + input wire [1:0] pmv_divide, +`endif + input wire sys_rst_n, + input wire cm_rst_n, + input wire cm_sticky_rst_n, + input wire func_lvl_rst_n, + input wire tl_rst_n, + input wire dl_rst_n, + input wire pl_rst_n, + input wire pl_transmit_hot_rst, +// input wire cfg_reset, +// input wire gwe, +// input wire grestore, +// input wire ghigh, + input wire [31:0] cfg_mgmt_di, + input wire [3:0] cfg_mgmt_byte_en_n, + input wire [9:0] cfg_mgmt_dwaddr, + input wire cfg_mgmt_wr_rw1c_as_rw_n, + input wire cfg_mgmt_wr_readonly_n, + input wire cfg_mgmt_wr_en_n, + input wire cfg_mgmt_rd_en_n, + input wire cfg_err_malformed_n, + input wire cfg_err_cor_n, + input wire cfg_err_ur_n, + input wire cfg_err_ecrc_n, + input wire cfg_err_cpl_timeout_n, + input wire cfg_err_cpl_abort_n, + input wire cfg_err_cpl_unexpect_n, + input wire cfg_err_poisoned_n, + input wire cfg_err_acs_n, + input wire cfg_err_atomic_egress_blocked_n, + input wire cfg_err_mc_blocked_n, + input wire cfg_err_internal_uncor_n, + input wire cfg_err_internal_cor_n, + input wire cfg_err_posted_n, + input wire cfg_err_locked_n, + input wire cfg_err_norecovery_n, + input wire [127:0] cfg_err_aer_headerlog, + input wire [47:0] cfg_err_tlp_cpl_header, + input wire cfg_interrupt_n, + input wire [7:0] cfg_interrupt_di, + input wire cfg_interrupt_assert_n, + input wire cfg_interrupt_stat_n, + input wire [7:0] cfg_ds_bus_number, + input wire [4:0] cfg_ds_device_number, + input wire [2:0] cfg_ds_function_number, + input wire [7:0] cfg_port_number, + input wire cfg_pm_halt_aspm_l0s_n, + input wire cfg_pm_halt_aspm_l1_n, + input wire cfg_pm_force_state_en_n, + input wire [1:0] cfg_pm_force_state, + input wire cfg_pm_wake_n, + input wire cfg_pm_turnoff_ok_n, + input wire cfg_pm_send_pme_to_n, + input wire [4:0] cfg_pciecap_interrupt_msgnum, + input wire cfg_trn_pending_n, + input wire [2:0] cfg_force_mps, + input wire cfg_force_common_clock_off, + input wire cfg_force_extended_sync_on, + input wire [63:0] cfg_dsn, + input wire [4:0] cfg_aer_interrupt_msgnum, + input wire [15:0] cfg_dev_id, + input wire [15:0] cfg_vend_id, + input wire [7:0] cfg_rev_id, + input wire [15:0] cfg_subsys_id, + input wire [15:0] cfg_subsys_vend_id, + input wire drp_clk, + input wire drp_en, + input wire drp_we, + input wire [8:0] drp_addr, + input wire [15:0] drp_di, + input wire [1:0] dbg_mode, + input wire dbg_sub_mode, + input wire [2:0] pl_dbg_mode, + + output wire trn_clk, + + output wire trn_tdst_rdy, + output wire trn_terr_drop, + output wire [5:0] trn_tbuf_av, + output wire trn_tcfg_req, + + //output wire [C_DATA_WIDTH-1:0] trn_rd, + output wire [127:0] trn_rd, + + output wire [1:0] trn_rrem, + output wire trn_rsof, + output wire trn_reof, + output wire trn_rsrc_rdy, + output wire trn_rsrc_dsc, + output wire trn_recrc_err, + output wire trn_rerrfwd, + output wire [7:0] trn_rbar_hit, + output wire trn_lnk_up, + output wire [7:0] trn_fc_ph, + output wire [11:0] trn_fc_pd, + output wire [7:0] trn_fc_nph, + output wire [11:0] trn_fc_npd, + output wire [7:0] trn_fc_cplh, + output wire [11:0] trn_fc_cpld, + output wire trn_tdllp_dst_rdy, + output wire [63:0] trn_rdllp_data, + output wire [1:0] trn_rdllp_src_rdy, + output wire ll2_tfc_init1_seq, + output wire ll2_tfc_init2_seq, + output wire pl2_suspend_ok, + output wire pl2_recovery, + output wire pl2_rx_elec_idle, + output wire [1:0] pl2_rx_pm_state, + output wire pl2_l0_req, + output wire ll2_suspend_ok, + output wire ll2_tx_idle, + output wire [4:0] ll2_link_status, + output wire tl2_ppm_suspend_ok, + output wire tl2_aspm_suspend_req, + output wire tl2_aspm_suspend_credit_check_ok, + output wire pl2_link_up, + output wire pl2_receiver_err, + output wire ll2_receiver_err, + output wire ll2_protocol_err, + output wire ll2_bad_tlp_err, + output wire ll2_bad_dllp_err, + output wire ll2_replay_ro_err, + output wire ll2_replay_to_err, + output wire [63:0] tl2_err_hdr, + output wire tl2_err_malformed, + output wire tl2_err_rxoverflow, + output wire tl2_err_fcpe, + output wire pl_sel_lnk_rate, + output wire [1:0] pl_sel_lnk_width, + output wire [5:0] pl_ltssm_state, + output wire [1:0] pl_lane_reversal_mode, + output wire pl_phy_lnk_up_n, + output wire [2:0] pl_tx_pm_state, + output wire [1:0] pl_rx_pm_state, + output wire pl_link_upcfg_cap, + output wire pl_link_gen2_cap, + output wire pl_link_partner_gen2_supported, + output wire [2:0] pl_initial_link_width, + output wire pl_directed_change_done, + output wire pipe_tx_rcvr_det, + output wire pipe_tx_reset, + output wire pipe_tx_rate, + output wire pipe_tx_deemph, + output wire [2:0] pipe_tx_margin, + output wire pipe_rx0_polarity, + output wire pipe_rx1_polarity, + output wire pipe_rx2_polarity, + output wire pipe_rx3_polarity, + output wire pipe_rx4_polarity, + output wire pipe_rx5_polarity, + output wire pipe_rx6_polarity, + output wire pipe_rx7_polarity, + output wire pipe_tx0_compliance, + output wire pipe_tx1_compliance, + output wire pipe_tx2_compliance, + output wire pipe_tx3_compliance, + output wire pipe_tx4_compliance, + output wire pipe_tx5_compliance, + output wire pipe_tx6_compliance, + output wire pipe_tx7_compliance, + output wire [1:0] pipe_tx0_char_is_k, + output wire [1:0] pipe_tx1_char_is_k, + output wire [1:0] pipe_tx2_char_is_k, + output wire [1:0] pipe_tx3_char_is_k, + output wire [1:0] pipe_tx4_char_is_k, + output wire [1:0] pipe_tx5_char_is_k, + output wire [1:0] pipe_tx6_char_is_k, + output wire [1:0] pipe_tx7_char_is_k, + output wire [15:0] pipe_tx0_data, + output wire [15:0] pipe_tx1_data, + output wire [15:0] pipe_tx2_data, + output wire [15:0] pipe_tx3_data, + output wire [15:0] pipe_tx4_data, + output wire [15:0] pipe_tx5_data, + output wire [15:0] pipe_tx6_data, + output wire [15:0] pipe_tx7_data, + output wire pipe_tx0_elec_idle, + output wire pipe_tx1_elec_idle, + output wire pipe_tx2_elec_idle, + output wire pipe_tx3_elec_idle, + output wire pipe_tx4_elec_idle, + output wire pipe_tx5_elec_idle, + output wire pipe_tx6_elec_idle, + output wire pipe_tx7_elec_idle, + output wire [1:0] pipe_tx0_powerdown, + output wire [1:0] pipe_tx1_powerdown, + output wire [1:0] pipe_tx2_powerdown, + output wire [1:0] pipe_tx3_powerdown, + output wire [1:0] pipe_tx4_powerdown, + output wire [1:0] pipe_tx5_powerdown, + output wire [1:0] pipe_tx6_powerdown, + output wire [1:0] pipe_tx7_powerdown, +`ifdef B_TESTMODE + output wire pmv_out, +`endif + output wire user_rst_n, + output wire pl_received_hot_rst, + output wire received_func_lvl_rst_n, + output wire lnk_clk_en, + output wire [31:0] cfg_mgmt_do, + output wire cfg_mgmt_rd_wr_done_n, + output wire cfg_err_aer_headerlog_set_n, + output wire cfg_err_cpl_rdy_n, + output wire cfg_interrupt_rdy_n, + output wire [2:0] cfg_interrupt_mmenable, + output wire cfg_interrupt_msienable, + output wire [7:0] cfg_interrupt_do, + output wire cfg_interrupt_msixenable, + output wire cfg_interrupt_msixfm, + output wire cfg_msg_received, + output wire [15:0] cfg_msg_data, + output wire cfg_msg_received_err_cor, + output wire cfg_msg_received_err_non_fatal, + output wire cfg_msg_received_err_fatal, + output wire cfg_msg_received_assert_int_a, + output wire cfg_msg_received_deassert_int_a, + output wire cfg_msg_received_assert_int_b, + output wire cfg_msg_received_deassert_int_b, + output wire cfg_msg_received_assert_int_c, + output wire cfg_msg_received_deassert_int_c, + output wire cfg_msg_received_assert_int_d, + output wire cfg_msg_received_deassert_int_d, + output wire cfg_msg_received_pm_pme, + output wire cfg_msg_received_pme_to_ack, + output wire cfg_msg_received_pme_to, + output wire cfg_msg_received_setslotpowerlimit, + output wire cfg_msg_received_unlock, + output wire cfg_msg_received_pm_as_nak, + output wire [2:0] cfg_pcie_link_state, + output wire cfg_pm_rcv_as_req_l1_n, + output wire cfg_pm_rcv_enter_l1_n, + output wire cfg_pm_rcv_enter_l23_n, + output wire cfg_pm_rcv_req_ack_n, + output wire [1:0] cfg_pmcsr_powerstate, + output wire cfg_pmcsr_pme_en, + output wire cfg_pmcsr_pme_status, + output wire cfg_transaction, + output wire cfg_transaction_type, + output wire [6:0] cfg_transaction_addr, + output wire cfg_command_io_enable, + output wire cfg_command_mem_enable, + output wire cfg_command_bus_master_enable, + output wire cfg_command_interrupt_disable, + output wire cfg_command_serr_en, + output wire cfg_bridge_serr_en, + output wire cfg_dev_status_corr_err_detected, + output wire cfg_dev_status_non_fatal_err_detected, + output wire cfg_dev_status_fatal_err_detected, + output wire cfg_dev_status_ur_detected, + output wire cfg_dev_control_corr_err_reporting_en, + output wire cfg_dev_control_non_fatal_reporting_en, + output wire cfg_dev_control_fatal_err_reporting_en, + output wire cfg_dev_control_ur_err_reporting_en, + output wire cfg_dev_control_enable_ro, + output wire [2:0] cfg_dev_control_max_payload, + output wire cfg_dev_control_ext_tag_en, + output wire cfg_dev_control_phantom_en, + output wire cfg_dev_control_aux_power_en, + output wire cfg_dev_control_no_snoop_en, + output wire [2:0] cfg_dev_control_max_read_req, + output wire [1:0] cfg_link_status_current_speed, + output wire [3:0] cfg_link_status_negotiated_width, + output wire cfg_link_status_link_training, + output wire cfg_link_status_dll_active, + output wire cfg_link_status_bandwidth_status, + output wire cfg_link_status_auto_bandwidth_status, + output wire [1:0] cfg_link_control_aspm_control, + output wire cfg_link_control_rcb, + output wire cfg_link_control_link_disable, + output wire cfg_link_control_retrain_link, + output wire cfg_link_control_common_clock, + output wire cfg_link_control_extended_sync, + output wire cfg_link_control_clock_pm_en, + output wire cfg_link_control_hw_auto_width_dis, + output wire cfg_link_control_bandwidth_int_en, + output wire cfg_link_control_auto_bandwidth_int_en, + output wire [3:0] cfg_dev_control2_cpl_timeout_val, + output wire cfg_dev_control2_cpl_timeout_dis, + output wire cfg_dev_control2_ari_forward_en, + output wire cfg_dev_control2_atomic_requester_en, + output wire cfg_dev_control2_atomic_egress_block, + output wire cfg_dev_control2_ido_req_en, + output wire cfg_dev_control2_ido_cpl_en, + output wire cfg_dev_control2_ltr_en, + output wire cfg_dev_control2_tlp_prefix_block, + output wire cfg_slot_control_electromech_il_ctl_pulse, + output wire cfg_root_control_syserr_corr_err_en, + output wire cfg_root_control_syserr_non_fatal_err_en, + output wire cfg_root_control_syserr_fatal_err_en, + output wire cfg_root_control_pme_int_en, + output wire cfg_aer_ecrc_check_en, + output wire cfg_aer_ecrc_gen_en, + output wire cfg_aer_rooterr_corr_err_reporting_en, + output wire cfg_aer_rooterr_non_fatal_err_reporting_en, + output wire cfg_aer_rooterr_fatal_err_reporting_en, + output wire cfg_aer_rooterr_corr_err_received, + output wire cfg_aer_rooterr_non_fatal_err_received, + output wire cfg_aer_rooterr_fatal_err_received, + output wire [6:0] cfg_vc_tcvc_map, + output wire drp_rdy, + output wire [15:0] drp_do, + output wire [63:0] dbg_vec_a, + output wire [63:0] dbg_vec_b, + output wire [11:0] dbg_vec_c, + output wire dbg_sclr_a, + output wire dbg_sclr_b, + output wire dbg_sclr_c, + output wire dbg_sclr_d, + output wire dbg_sclr_e, + output wire dbg_sclr_f, + output wire dbg_sclr_g, + output wire dbg_sclr_h, + output wire dbg_sclr_i, + output wire dbg_sclr_j, + output wire dbg_sclr_k, + output wire [11:0] pl_dbg_vec +// output wire [18:0] xil_unconn_out +); + + localparam TCQ = 1; + + wire [3:0] trn_tdst_rdy_bus; + + // Assignments to outputs + assign trn_clk = user_clk2; + assign trn_tdst_rdy = trn_tdst_rdy_bus[0]; + + //----------------------------------------------------------------------// + // BRAM // + //----------------------------------------------------------------------// + + // transmit bram interface + wire mim_tx_wen; + wire [12:0] mim_tx_waddr; + wire [68:0] mim_tx_wdata; + wire mim_tx_ren; + wire mim_tx_rce; + wire [12:0] mim_tx_raddr; + wire [68:0] mim_tx_rdata; + wire [2:0] unused_mim_tx_rdata; + + // receive bram interface + wire mim_rx_wen; + wire [12:0] mim_rx_waddr; + wire [67:0] mim_rx_wdata; + wire mim_rx_ren; + wire mim_rx_rce; + wire [12:0] mim_rx_raddr; + wire [67:0] mim_rx_rdata; + wire [3:0] unused_mim_rx_rdata; + +pcie_7x_0_pcie_bram_top_7x #( + .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ), + .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), + .DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ), + .VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ), + .TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ), + .TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ), + .TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ), + .VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ), + .TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ), + .TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ), + .TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ) + ) pcie_bram_top ( + .user_clk_i ( user_clk ), + .reset_i ( 1'b0 ), + + .mim_tx_waddr ( mim_tx_waddr ), + .mim_tx_wen ( mim_tx_wen ), + .mim_tx_ren ( mim_tx_ren ), + .mim_tx_rce ( 1'b1 ), + .mim_tx_wdata ( {3'b0, mim_tx_wdata} ), + .mim_tx_raddr ( mim_tx_raddr ), + .mim_tx_rdata ( {unused_mim_tx_rdata, mim_tx_rdata} ), + + .mim_rx_waddr ( mim_rx_waddr ), + .mim_rx_wen ( mim_rx_wen ), + .mim_rx_ren ( mim_rx_ren ), + .mim_rx_rce ( 1'b1 ), + .mim_rx_wdata ( {4'b0, mim_rx_wdata} ), + .mim_rx_raddr ( mim_rx_raddr ), + .mim_rx_rdata ( {unused_mim_rx_rdata, mim_rx_rdata} ) + ); + + //------------------------------------------------------- + // Virtex7 PCI Express Block Module + //------------------------------------------------------- + + PCIE_2_1 #( // Verilog-2001 + .AER_BASE_PTR ( AER_BASE_PTR ), + .AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ), + .AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ), + .AER_CAP_ID ( AER_CAP_ID ), + .AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ), + .AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ), + .AER_CAP_ON ( AER_CAP_ON ), + .AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ), + .AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ), + .AER_CAP_VERSION ( AER_CAP_VERSION ), + .ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ), + .BAR0 ( BAR0 ), + .BAR1 ( BAR1 ), + .BAR2 ( BAR2 ), + .BAR3 ( BAR3 ), + .BAR4 ( BAR4 ), + .BAR5 ( BAR5 ), + .CAPABILITIES_PTR ( CAPABILITIES_PTR ), + .CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ), + .CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ), + .CLASS_CODE ( CLASS_CODE ), + .CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ), + .CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ), + .CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ), + .CRM_MODULE_RSTS ( CRM_MODULE_RSTS ), + .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ), + .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ), + .DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ), + .DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ), + .DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ), + .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ), + .DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ), + .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ), + .DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ), + .DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ), + .DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ), + .DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ), + .DEV_CAP2_ARI_FORWARDING_SUPPORTED ( DEV_CAP2_ARI_FORWARDING_SUPPORTED ), + .DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ( DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ), + .DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ), + .DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ), + .DEV_CAP2_CAS128_COMPLETER_SUPPORTED ( DEV_CAP2_CAS128_COMPLETER_SUPPORTED ), + .DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ( DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ), + .DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ( DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ), + .DEV_CAP2_LTR_MECHANISM_SUPPORTED ( DEV_CAP2_LTR_MECHANISM_SUPPORTED ), + .DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ( DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ), + .DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ( DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ), + .DEV_CAP2_TPH_COMPLETER_SUPPORTED ( DEV_CAP2_TPH_COMPLETER_SUPPORTED ), + .DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ), + .DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ), + .DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ), + .DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ), + .DISABLE_ERR_MSG ( DISABLE_ERR_MSG ), + .DISABLE_ID_CHECK ( DISABLE_ID_CHECK ), + .DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ), + .DISABLE_LOCKED_FILTER ( DISABLE_LOCKED_FILTER ), + .DISABLE_PPM_FILTER ( DISABLE_PPM_FILTER ), + .DISABLE_RX_POISONED_RESP ( DISABLE_RX_POISONED_RESP ), + .DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ), + .DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ), + .DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ), + .DSN_BASE_PTR ( DSN_BASE_PTR ), + .DSN_CAP_ID ( DSN_CAP_ID ), + .DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ), + .DSN_CAP_ON ( DSN_CAP_ON ), + .DSN_CAP_VERSION ( DSN_CAP_VERSION ), + .ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ), + .ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ), + .ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ( ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ), + .ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ), + .EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ), + .EXPANSION_ROM ( EXPANSION_ROM ), + .EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ), + .EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ), + .HEADER_TYPE ( HEADER_TYPE ), + .INFER_EI ( INFER_EI ), + .INTERRUPT_PIN ( INTERRUPT_PIN ), + .INTERRUPT_STAT_AUTO ( INTERRUPT_STAT_AUTO ), + .IS_SWITCH ( IS_SWITCH ), + .LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ), + .LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ), + .LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ), + .LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ), + .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ), + .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ), + .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ), + .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ), + .LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ), + .LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ), + .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ), + .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ), + .LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ), + .LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ), + .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ), + .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), + .LINK_CAP_RSVD_23 ( LINK_CAP_RSVD_23 ), + .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ), + .LINK_CONTROL_RCB ( LINK_CONTROL_RCB ), + .LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ), + .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ), + .LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ), + .LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ), + .LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ), + .LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ), + .LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ), + .LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ), + .LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ), + .LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ), + .LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ), + .MPS_FORCE ( MPS_FORCE ), + .MSI_BASE_PTR ( MSI_BASE_PTR ), + .MSI_CAP_ID ( MSI_CAP_ID ), + .MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ), + .MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ), + .MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ), + .MSI_CAP_ON ( MSI_CAP_ON ), + .MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ), + .MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ), + .MSIX_BASE_PTR ( MSIX_BASE_PTR ), + .MSIX_CAP_ID ( MSIX_CAP_ID ), + .MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ), + .MSIX_CAP_ON ( MSIX_CAP_ON ), + .MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ), + .MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ), + .MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ), + .MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ), + .MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ), + .N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ), + .N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ), + .N_FTS_GEN1 ( N_FTS_GEN1 ), + .N_FTS_GEN2 ( N_FTS_GEN2 ), + .PCIE_BASE_PTR ( PCIE_BASE_PTR ), + .PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ), + .PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ), + .PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ), + .PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ), + .PCIE_CAP_ON ( PCIE_CAP_ON ), + .PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ), + .PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ), + .PCIE_REVISION ( PCIE_REVISION ), + .PL_AUTO_CONFIG ( PL_AUTO_CONFIG ), + .PL_FAST_TRAIN ( PL_FAST_TRAIN ), + .PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ), + .PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ), + .PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ), + .PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ), + .PM_BASE_PTR ( PM_BASE_PTR ), + .PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ), + .PM_CAP_DSI ( PM_CAP_DSI ), + .PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ), + .PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ), + .PM_CAP_ID ( PM_CAP_ID ), + .PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ), + .PM_CAP_ON ( PM_CAP_ON ), + .PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ), + .PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ), + .PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ), + .PM_CAP_VERSION ( PM_CAP_VERSION ), + .PM_CSR_BPCCEN ( PM_CSR_BPCCEN ), + .PM_CSR_B2B3 ( PM_CSR_B2B3 ), + .PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ), + .PM_DATA_SCALE0 ( PM_DATA_SCALE0 ), + .PM_DATA_SCALE1 ( PM_DATA_SCALE1 ), + .PM_DATA_SCALE2 ( PM_DATA_SCALE2 ), + .PM_DATA_SCALE3 ( PM_DATA_SCALE3 ), + .PM_DATA_SCALE4 ( PM_DATA_SCALE4 ), + .PM_DATA_SCALE5 ( PM_DATA_SCALE5 ), + .PM_DATA_SCALE6 ( PM_DATA_SCALE6 ), + .PM_DATA_SCALE7 ( PM_DATA_SCALE7 ), + .PM_DATA0 ( PM_DATA0 ), + .PM_DATA1 ( PM_DATA1 ), + .PM_DATA2 ( PM_DATA2 ), + .PM_DATA3 ( PM_DATA3 ), + .PM_DATA4 ( PM_DATA4 ), + .PM_DATA5 ( PM_DATA5 ), + .PM_DATA6 ( PM_DATA6 ), + .PM_DATA7 ( PM_DATA7 ), + .PM_MF ( PM_MF ), + .RBAR_BASE_PTR ( RBAR_BASE_PTR ), + .RBAR_CAP_CONTROL_ENCODEDBAR0 ( RBAR_CAP_CONTROL_ENCODEDBAR0 ), + .RBAR_CAP_CONTROL_ENCODEDBAR1 ( RBAR_CAP_CONTROL_ENCODEDBAR1 ), + .RBAR_CAP_CONTROL_ENCODEDBAR2 ( RBAR_CAP_CONTROL_ENCODEDBAR2 ), + .RBAR_CAP_CONTROL_ENCODEDBAR3 ( RBAR_CAP_CONTROL_ENCODEDBAR3 ), + .RBAR_CAP_CONTROL_ENCODEDBAR4 ( RBAR_CAP_CONTROL_ENCODEDBAR4 ), + .RBAR_CAP_CONTROL_ENCODEDBAR5 ( RBAR_CAP_CONTROL_ENCODEDBAR5 ), + .RBAR_CAP_ID ( RBAR_CAP_ID ), + .RBAR_CAP_INDEX0 ( RBAR_CAP_INDEX0 ), + .RBAR_CAP_INDEX1 ( RBAR_CAP_INDEX1 ), + .RBAR_CAP_INDEX2 ( RBAR_CAP_INDEX2 ), + .RBAR_CAP_INDEX3 ( RBAR_CAP_INDEX3 ), + .RBAR_CAP_INDEX4 ( RBAR_CAP_INDEX4 ), + .RBAR_CAP_INDEX5 ( RBAR_CAP_INDEX5 ), + .RBAR_CAP_NEXTPTR ( RBAR_CAP_NEXTPTR ), + .RBAR_CAP_ON ( RBAR_CAP_ON ), + .RBAR_CAP_SUP0 ( RBAR_CAP_SUP0 ), + .RBAR_CAP_SUP1 ( RBAR_CAP_SUP1 ), + .RBAR_CAP_SUP2 ( RBAR_CAP_SUP2 ), + .RBAR_CAP_SUP3 ( RBAR_CAP_SUP3 ), + .RBAR_CAP_SUP4 ( RBAR_CAP_SUP4 ), + .RBAR_CAP_SUP5 ( RBAR_CAP_SUP5 ), + .RBAR_CAP_VERSION ( RBAR_CAP_VERSION ), + .RBAR_NUM ( RBAR_NUM ), + .RECRC_CHK ( RECRC_CHK ), + .RECRC_CHK_TRIM ( RECRC_CHK_TRIM ), + .ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ), + .RP_AUTO_SPD ( RP_AUTO_SPD ), + .RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ), + .SELECT_DLL_IF ( SELECT_DLL_IF ), + .SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ), + .SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ), + .SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ), + .SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ), + .SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ), + .SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ), + .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ), + .SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ), + .SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ), + .SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ), + .SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ), + .SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ), + .SPARE_BIT0 ( SPARE_BIT0 ), + .SPARE_BIT1 ( SPARE_BIT1 ), + .SPARE_BIT2 ( SPARE_BIT2 ), + .SPARE_BIT3 ( SPARE_BIT3 ), + .SPARE_BIT4 ( SPARE_BIT4 ), + .SPARE_BIT5 ( SPARE_BIT5 ), + .SPARE_BIT6 ( SPARE_BIT6 ), + .SPARE_BIT7 ( SPARE_BIT7 ), + .SPARE_BIT8 ( SPARE_BIT8 ), + .SPARE_BYTE0 ( SPARE_BYTE0 ), + .SPARE_BYTE1 ( SPARE_BYTE1 ), + .SPARE_BYTE2 ( SPARE_BYTE2 ), + .SPARE_BYTE3 ( SPARE_BYTE3 ), + .SPARE_WORD0 ( SPARE_WORD0 ), + .SPARE_WORD1 ( SPARE_WORD1 ), + .SPARE_WORD2 ( SPARE_WORD2 ), + .SPARE_WORD3 ( SPARE_WORD3 ), + .SSL_MESSAGE_AUTO ( SSL_MESSAGE_AUTO ), + .TECRC_EP_INV ( TECRC_EP_INV ), + .TL_RBYPASS ( TL_RBYPASS ), + .TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ), + .TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ), + .TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ), + .TL_TFC_DISABLE ( TL_TFC_DISABLE ), + .TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ), + .TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ), + .TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ), + .TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ), + .TRN_DW ( TRN_DW ), + .TRN_NP_FC ( TRN_NP_FC ), + .UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ), + .UPSTREAM_FACING ( UPSTREAM_FACING ), + .UR_ATOMIC ( UR_ATOMIC ), + .UR_CFG1 ( UR_CFG1 ), + .UR_INV_REQ ( UR_INV_REQ ), + .UR_PRS_RESPONSE ( UR_PRS_RESPONSE ), + .USE_RID_PINS ( USE_RID_PINS ), + .USER_CLK_FREQ ( USER_CLK_FREQ ), + .USER_CLK2_DIV2 ( USER_CLK2_DIV2 ), + .VC_BASE_PTR ( VC_BASE_PTR ), + .VC_CAP_ID ( VC_CAP_ID ), + .VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ), + .VC_CAP_ON ( VC_CAP_ON ), + .VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ), + .VC_CAP_VERSION ( VC_CAP_VERSION ), + .VC0_CPL_INFINITE ( VC0_CPL_INFINITE ), + .VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ), + .VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ), + .VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ), + .VC0_TOTAL_CREDITS_NPD ( VC0_TOTAL_CREDITS_NPD ), + .VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ), + .VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ), + .VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ), + .VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ), + .VSEC_BASE_PTR ( VSEC_BASE_PTR ), + .VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ), + .VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ), + .VSEC_CAP_ID ( VSEC_CAP_ID ), + .VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ), + .VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ), + .VSEC_CAP_ON ( VSEC_CAP_ON ), + .VSEC_CAP_VERSION ( VSEC_CAP_VERSION ) +`ifdef B_TESTMODE + , + .TEST_MODE_PIN_CHAR ( TEST_MODE_PIN_CHAR ) +`endif + + ) + pcie_block_i ( + + .TRNTD ({{(128-C_DATA_WIDTH){1'b0}},trn_td} ), + .TRNTREM ({1'b0,trn_trem} ), + + + .TRNTSOF (trn_tsof ), + .TRNTEOF (trn_teof ), + .TRNTSRCRDY (trn_tsrc_rdy ), + .TRNTSRCDSC (trn_tsrc_dsc ), + .TRNTERRFWD (trn_terrfwd ), + .TRNTECRCGEN (trn_tecrc_gen ), + .TRNTSTR (trn_tstr ), + .TRNTCFGGNT (trn_tcfg_gnt ), + .TRNRDSTRDY (trn_rdst_rdy ), + .TRNRNPREQ (trn_rnp_req ), + .TRNRFCPRET (trn_rfcp_ret ), + .TRNRNPOK (trn_rnp_ok ), + .TRNFCSEL (trn_fc_sel ), + .MIMTXRDATA (mim_tx_rdata ), + .MIMRXRDATA (mim_rx_rdata ), + .TRNTDLLPDATA (trn_tdllp_data ), + .TRNTDLLPSRCRDY (trn_tdllp_src_rdy ), + .LL2TLPRCV (ll2_tlp_rcv ), + .LL2SENDENTERL1 (ll2_send_enter_l1 ), + .LL2SENDENTERL23 (ll2_send_enter_l23 ), + .LL2SENDASREQL1 (ll2_send_as_req_l1 ), + .LL2SENDPMACK (ll2_send_pm_ack ), + .PL2DIRECTEDLSTATE (pl2_directed_lstate ), + .LL2SUSPENDNOW (ll2_suspend_now ), + .TL2PPMSUSPENDREQ (tl2_ppm_suspend_req ), + .TL2ASPMSUSPENDCREDITCHECK (tl2_aspm_suspend_credit_check ), + .PLDIRECTEDLINKCHANGE (pl_directed_link_change ), + .PLDIRECTEDLINKWIDTH (pl_directed_link_width ), + .PLDIRECTEDLINKSPEED (pl_directed_link_speed ), + .PLDIRECTEDLINKAUTON (pl_directed_link_auton ), + .PLUPSTREAMPREFERDEEMPH (pl_upstream_prefer_deemph ), + .PLDOWNSTREAMDEEMPHSOURCE (pl_downstream_deemph_source ), + .PLDIRECTEDLTSSMNEW (pl_directed_ltssm_new ), + .PLDIRECTEDLTSSMNEWVLD (pl_directed_ltssm_new_vld ), + .PLDIRECTEDLTSSMSTALL (pl_directed_ltssm_stall ), + .PIPERX0CHARISK (pipe_rx0_char_is_k ), + .PIPERX1CHARISK (pipe_rx1_char_is_k ), + .PIPERX2CHARISK (pipe_rx2_char_is_k ), + .PIPERX3CHARISK (pipe_rx3_char_is_k ), + .PIPERX4CHARISK (pipe_rx4_char_is_k ), + .PIPERX5CHARISK (pipe_rx5_char_is_k ), + .PIPERX6CHARISK (pipe_rx6_char_is_k ), + .PIPERX7CHARISK (pipe_rx7_char_is_k ), + .PIPERX0VALID (pipe_rx0_valid ), + .PIPERX1VALID (pipe_rx1_valid ), + .PIPERX2VALID (pipe_rx2_valid ), + .PIPERX3VALID (pipe_rx3_valid ), + .PIPERX4VALID (pipe_rx4_valid ), + .PIPERX5VALID (pipe_rx5_valid ), + .PIPERX6VALID (pipe_rx6_valid ), + .PIPERX7VALID (pipe_rx7_valid ), + .PIPERX0DATA (pipe_rx0_data ), + .PIPERX1DATA (pipe_rx1_data ), + .PIPERX2DATA (pipe_rx2_data ), + .PIPERX3DATA (pipe_rx3_data ), + .PIPERX4DATA (pipe_rx4_data ), + .PIPERX5DATA (pipe_rx5_data ), + .PIPERX6DATA (pipe_rx6_data ), + .PIPERX7DATA (pipe_rx7_data ), + .PIPERX0CHANISALIGNED (pipe_rx0_chanisaligned ), + .PIPERX1CHANISALIGNED (pipe_rx1_chanisaligned ), + .PIPERX2CHANISALIGNED (pipe_rx2_chanisaligned ), + .PIPERX3CHANISALIGNED (pipe_rx3_chanisaligned ), + .PIPERX4CHANISALIGNED (pipe_rx4_chanisaligned ), + .PIPERX5CHANISALIGNED (pipe_rx5_chanisaligned ), + .PIPERX6CHANISALIGNED (pipe_rx6_chanisaligned ), + .PIPERX7CHANISALIGNED (pipe_rx7_chanisaligned ), + .PIPERX0STATUS (pipe_rx0_status ), + .PIPERX1STATUS (pipe_rx1_status ), + .PIPERX2STATUS (pipe_rx2_status ), + .PIPERX3STATUS (pipe_rx3_status ), + .PIPERX4STATUS (pipe_rx4_status ), + .PIPERX5STATUS (pipe_rx5_status ), + .PIPERX6STATUS (pipe_rx6_status ), + .PIPERX7STATUS (pipe_rx7_status ), + .PIPERX0PHYSTATUS (pipe_rx0_phy_status ), + .PIPERX1PHYSTATUS (pipe_rx1_phy_status ), + .PIPERX2PHYSTATUS (pipe_rx2_phy_status ), + .PIPERX3PHYSTATUS (pipe_rx3_phy_status ), + .PIPERX4PHYSTATUS (pipe_rx4_phy_status ), + .PIPERX5PHYSTATUS (pipe_rx5_phy_status ), + .PIPERX6PHYSTATUS (pipe_rx6_phy_status ), + .PIPERX7PHYSTATUS (pipe_rx7_phy_status ), + .PIPERX0ELECIDLE (pipe_rx0_elec_idle ), + .PIPERX1ELECIDLE (pipe_rx1_elec_idle ), + .PIPERX2ELECIDLE (pipe_rx2_elec_idle ), + .PIPERX3ELECIDLE (pipe_rx3_elec_idle ), + .PIPERX4ELECIDLE (pipe_rx4_elec_idle ), + .PIPERX5ELECIDLE (pipe_rx5_elec_idle ), + .PIPERX6ELECIDLE (pipe_rx6_elec_idle ), + .PIPERX7ELECIDLE (pipe_rx7_elec_idle ), + .PIPECLK (pipe_clk ), + .USERCLK (user_clk ), + .USERCLK2 (user_clk2 ), +`ifdef VALIDATION + .USERCLKPREBUF (user_clk_prebuf ), + .USERCLKPREBUFEN (user_clk_prebuf_en ), +`endif +`ifdef B_TESTMODE + .USERCLKPREBUF (user_clk_prebuf ), + .USERCLKPREBUFEN (user_clk_prebuf_en ), + .SCANMODEN (scanmode_n ), + .SCANENABLEN (scanenable_n ), + .EDTCLK (edt_clk ), + .EDTUPDATE (edt_update ), + .EDTBYPASS (edt_bypass ), + .EDTCONFIGURATION (edt_configuration ), + .EDTSINGLEBYPASSCHAIN (edt_single_bypass_chain ), + .EDTCHANNELSIN1 (edt_channels_in1 ), + .EDTCHANNELSIN2 (edt_channels_in2 ), + .EDTCHANNELSIN3 (edt_channels_in3 ), + .EDTCHANNELSIN4 (edt_channels_in4 ), + .EDTCHANNELSIN5 (edt_channels_in5 ), + .EDTCHANNELSIN6 (edt_channels_in6 ), + .EDTCHANNELSIN7 (edt_channels_in7 ), + .EDTCHANNELSIN8 (edt_channels_in8 ), + .PMVENABLEN (pmv_enable_n ), + .PMVSELECT (pmv_select ), + .PMVDIVIDE (pmv_divide ), +`endif +//`ifdef SECUREIP +// .GSR (gsr ), +//`endif + .SYSRSTN (sys_rst_n ), + .CMRSTN (cm_rst_n ), + .CMSTICKYRSTN (cm_sticky_rst_n ), + .FUNCLVLRSTN (func_lvl_rst_n ), + .TLRSTN (tl_rst_n ), + .DLRSTN (dl_rst_n ), + .PLRSTN (pl_rst_n ), + .PLTRANSMITHOTRST (pl_transmit_hot_rst ), + // Global pins not on Holistic model + //.CFGRESET (cfg_reset ), + //.GWE (gwe ), + //.GRESTORE (grestore ), + //.GHIGHB (ghigh_b ), + .CFGMGMTDI (cfg_mgmt_di ), + .CFGMGMTBYTEENN (cfg_mgmt_byte_en_n ), + .CFGMGMTDWADDR (cfg_mgmt_dwaddr ), + .CFGMGMTWRRW1CASRWN (cfg_mgmt_wr_rw1c_as_rw_n ), + .CFGMGMTWRREADONLYN (cfg_mgmt_wr_readonly_n ), + .CFGMGMTWRENN (cfg_mgmt_wr_en_n ), + .CFGMGMTRDENN (cfg_mgmt_rd_en_n ), + .CFGERRMALFORMEDN (cfg_err_malformed_n ), + .CFGERRCORN (cfg_err_cor_n ), + .CFGERRURN (cfg_err_ur_n ), + .CFGERRECRCN (cfg_err_ecrc_n ), + .CFGERRCPLTIMEOUTN (cfg_err_cpl_timeout_n ), + .CFGERRCPLABORTN (cfg_err_cpl_abort_n ), + .CFGERRCPLUNEXPECTN (cfg_err_cpl_unexpect_n ), + .CFGERRPOISONEDN (cfg_err_poisoned_n ), + .CFGERRACSN (cfg_err_acs_n ), + .CFGERRATOMICEGRESSBLOCKEDN (cfg_err_atomic_egress_blocked_n ), + .CFGERRMCBLOCKEDN (cfg_err_mc_blocked_n ), + .CFGERRINTERNALUNCORN (cfg_err_internal_uncor_n ), + .CFGERRINTERNALCORN (cfg_err_internal_cor_n ), + .CFGERRPOSTEDN (cfg_err_posted_n ), + .CFGERRLOCKEDN (cfg_err_locked_n ), + .CFGERRNORECOVERYN (cfg_err_norecovery_n ), + .CFGERRAERHEADERLOG (cfg_err_aer_headerlog ), + .CFGERRTLPCPLHEADER (cfg_err_tlp_cpl_header ), + .CFGINTERRUPTN (cfg_interrupt_n ), + .CFGINTERRUPTDI (cfg_interrupt_di ), + .CFGINTERRUPTASSERTN (cfg_interrupt_assert_n ), + .CFGINTERRUPTSTATN (cfg_interrupt_stat_n ), + .CFGDSBUSNUMBER (cfg_ds_bus_number ), + .CFGDSDEVICENUMBER (cfg_ds_device_number ), + .CFGDSFUNCTIONNUMBER (cfg_ds_function_number ), + .CFGPORTNUMBER (cfg_port_number ), + .CFGPMHALTASPML0SN (cfg_pm_halt_aspm_l0s_n ), + .CFGPMHALTASPML1N (cfg_pm_halt_aspm_l1_n ), + .CFGPMFORCESTATEENN (cfg_pm_force_state_en_n ), + .CFGPMFORCESTATE (cfg_pm_force_state ), + .CFGPMWAKEN (cfg_pm_wake_n ), + .CFGPMTURNOFFOKN (cfg_pm_turnoff_ok_n ), + .CFGPMSENDPMETON (cfg_pm_send_pme_to_n ), + .CFGPCIECAPINTERRUPTMSGNUM (cfg_pciecap_interrupt_msgnum ), + .CFGTRNPENDINGN (cfg_trn_pending_n ), + .CFGFORCEMPS (cfg_force_mps ), + .CFGFORCECOMMONCLOCKOFF (cfg_force_common_clock_off ), + .CFGFORCEEXTENDEDSYNCON (cfg_force_extended_sync_on ), + .CFGDSN (cfg_dsn ), + .CFGDEVID (cfg_dev_id ), + .CFGVENDID (cfg_vend_id ), + .CFGREVID (cfg_rev_id ), + .CFGSUBSYSID (cfg_subsys_id ), + .CFGSUBSYSVENDID (cfg_subsys_vend_id ), + .CFGAERINTERRUPTMSGNUM (cfg_aer_interrupt_msgnum ), + .DRPCLK (drp_clk ), + .DRPEN (drp_en ), + .DRPWE (drp_we ), + .DRPADDR (drp_addr ), + .DRPDI (drp_di ), + //.DRPREADPORT0 (drp_read_port_0 ), + //.DRPREADPORT1 (drp_read_port_1 ), + //.DRPREADPORT2 (drp_read_port_2 ), + //.DRPREADPORT3 (drp_read_port_3 ), + //.DRPREADPORT4 (drp_read_port_4 ), + //.DRPREADPORT5 (drp_read_port_5 ), + //.DRPREADPORT6 (drp_read_port_6 ), + //.DRPREADPORT7 (drp_read_port_7 ), + //.DRPREADPORT8 (drp_read_port_8 ), + //.DRPREADPORT9 (drp_read_port_9 ), + //.DRPREADPORT10 (drp_read_port_10 ), + //.DRPREADPORT11 (drp_read_port_11 ), + //.DRPREADPORT12 (drp_read_port_12 ), + .DBGMODE (dbg_mode ), + .DBGSUBMODE (dbg_sub_mode ), + .PLDBGMODE (pl_dbg_mode ), + + .TRNTDSTRDY (trn_tdst_rdy_bus ), + .TRNTERRDROP (trn_terr_drop ), + .TRNTBUFAV (trn_tbuf_av ), + .TRNTCFGREQ (trn_tcfg_req ), + .TRNRD (trn_rd ), + .TRNRREM (trn_rrem ), + .TRNRSOF (trn_rsof ), + .TRNREOF (trn_reof ), + .TRNRSRCRDY (trn_rsrc_rdy ), + .TRNRSRCDSC (trn_rsrc_dsc ), + .TRNRECRCERR (trn_recrc_err ), + .TRNRERRFWD (trn_rerrfwd ), + .TRNRBARHIT (trn_rbar_hit ), + .TRNLNKUP (trn_lnk_up ), + .TRNFCPH (trn_fc_ph ), + .TRNFCPD (trn_fc_pd ), + .TRNFCNPH (trn_fc_nph ), + .TRNFCNPD (trn_fc_npd ), + .TRNFCCPLH (trn_fc_cplh ), + .TRNFCCPLD (trn_fc_cpld ), + .MIMTXWDATA (mim_tx_wdata ), + .MIMTXWADDR (mim_tx_waddr ), + .MIMTXWEN (mim_tx_wen ), + .MIMTXRADDR (mim_tx_raddr ), + .MIMTXREN (mim_tx_ren ), + .MIMRXWDATA (mim_rx_wdata ), + .MIMRXWADDR (mim_rx_waddr ), + .MIMRXWEN (mim_rx_wen ), + .MIMRXRADDR (mim_rx_raddr ), + .MIMRXREN (mim_rx_ren ), + .TRNTDLLPDSTRDY (trn_tdllp_dst_rdy ), + .TRNRDLLPDATA (trn_rdllp_data ), + .TRNRDLLPSRCRDY (trn_rdllp_src_rdy ), + .LL2TFCINIT1SEQ (ll2_tfc_init1_seq ), + .LL2TFCINIT2SEQ (ll2_tfc_init2_seq ), + .PL2SUSPENDOK (pl2_suspend_ok ), + .PL2RECOVERY (pl2_recovery ), + .PL2RXELECIDLE (pl2_rx_elec_idle ), + .PL2RXPMSTATE (pl2_rx_pm_state ), + .PL2L0REQ (pl2_l0_req ), + .LL2SUSPENDOK (ll2_suspend_ok ), + .LL2TXIDLE (ll2_tx_idle ), + .LL2LINKSTATUS (ll2_link_status ), + .TL2PPMSUSPENDOK (tl2_ppm_suspend_ok ), + .TL2ASPMSUSPENDREQ (tl2_aspm_suspend_req ), + .TL2ASPMSUSPENDCREDITCHECKOK (tl2_aspm_suspend_credit_check_ok ), + .PL2LINKUP (pl2_link_up ), + .PL2RECEIVERERR (pl2_receiver_err ), + .LL2RECEIVERERR (ll2_receiver_err ), + .LL2PROTOCOLERR (ll2_protocol_err ), + .LL2BADTLPERR (ll2_bad_tlp_err ), + .LL2BADDLLPERR (ll2_bad_dllp_err ), + .LL2REPLAYROERR (ll2_replay_ro_err ), + .LL2REPLAYTOERR (ll2_replay_to_err ), + .TL2ERRHDR (tl2_err_hdr ), + .TL2ERRMALFORMED (tl2_err_malformed ), + .TL2ERRRXOVERFLOW (tl2_err_rxoverflow ), + .TL2ERRFCPE (tl2_err_fcpe ), + .PLSELLNKRATE (pl_sel_lnk_rate ), + .PLSELLNKWIDTH (pl_sel_lnk_width ), + .PLLTSSMSTATE (pl_ltssm_state ), + .PLLANEREVERSALMODE (pl_lane_reversal_mode ), + .PLPHYLNKUPN (pl_phy_lnk_up_n ), + .PLTXPMSTATE (pl_tx_pm_state ), + .PLRXPMSTATE (pl_rx_pm_state ), + .PLLINKUPCFGCAP (pl_link_upcfg_cap ), + .PLLINKGEN2CAP (pl_link_gen2_cap ), + .PLLINKPARTNERGEN2SUPPORTED (pl_link_partner_gen2_supported ), + .PLINITIALLINKWIDTH (pl_initial_link_width ), + .PLDIRECTEDCHANGEDONE (pl_directed_change_done ), + .PIPETXRCVRDET (pipe_tx_rcvr_det ), + .PIPETXRESET (pipe_tx_reset ), + .PIPETXRATE (pipe_tx_rate ), + .PIPETXDEEMPH (pipe_tx_deemph ), + .PIPETXMARGIN (pipe_tx_margin ), + .PIPERX0POLARITY (pipe_rx0_polarity ), + .PIPERX1POLARITY (pipe_rx1_polarity ), + .PIPERX2POLARITY (pipe_rx2_polarity ), + .PIPERX3POLARITY (pipe_rx3_polarity ), + .PIPERX4POLARITY (pipe_rx4_polarity ), + .PIPERX5POLARITY (pipe_rx5_polarity ), + .PIPERX6POLARITY (pipe_rx6_polarity ), + .PIPERX7POLARITY (pipe_rx7_polarity ), + .PIPETX0COMPLIANCE (pipe_tx0_compliance ), + .PIPETX1COMPLIANCE (pipe_tx1_compliance ), + .PIPETX2COMPLIANCE (pipe_tx2_compliance ), + .PIPETX3COMPLIANCE (pipe_tx3_compliance ), + .PIPETX4COMPLIANCE (pipe_tx4_compliance ), + .PIPETX5COMPLIANCE (pipe_tx5_compliance ), + .PIPETX6COMPLIANCE (pipe_tx6_compliance ), + .PIPETX7COMPLIANCE (pipe_tx7_compliance ), + .PIPETX0CHARISK (pipe_tx0_char_is_k ), + .PIPETX1CHARISK (pipe_tx1_char_is_k ), + .PIPETX2CHARISK (pipe_tx2_char_is_k ), + .PIPETX3CHARISK (pipe_tx3_char_is_k ), + .PIPETX4CHARISK (pipe_tx4_char_is_k ), + .PIPETX5CHARISK (pipe_tx5_char_is_k ), + .PIPETX6CHARISK (pipe_tx6_char_is_k ), + .PIPETX7CHARISK (pipe_tx7_char_is_k ), + .PIPETX0DATA (pipe_tx0_data ), + .PIPETX1DATA (pipe_tx1_data ), + .PIPETX2DATA (pipe_tx2_data ), + .PIPETX3DATA (pipe_tx3_data ), + .PIPETX4DATA (pipe_tx4_data ), + .PIPETX5DATA (pipe_tx5_data ), + .PIPETX6DATA (pipe_tx6_data ), + .PIPETX7DATA (pipe_tx7_data ), + .PIPETX0ELECIDLE (pipe_tx0_elec_idle ), + .PIPETX1ELECIDLE (pipe_tx1_elec_idle ), + .PIPETX2ELECIDLE (pipe_tx2_elec_idle ), + .PIPETX3ELECIDLE (pipe_tx3_elec_idle ), + .PIPETX4ELECIDLE (pipe_tx4_elec_idle ), + .PIPETX5ELECIDLE (pipe_tx5_elec_idle ), + .PIPETX6ELECIDLE (pipe_tx6_elec_idle ), + .PIPETX7ELECIDLE (pipe_tx7_elec_idle ), + .PIPETX0POWERDOWN (pipe_tx0_powerdown ), + .PIPETX1POWERDOWN (pipe_tx1_powerdown ), + .PIPETX2POWERDOWN (pipe_tx2_powerdown ), + .PIPETX3POWERDOWN (pipe_tx3_powerdown ), + .PIPETX4POWERDOWN (pipe_tx4_powerdown ), + .PIPETX5POWERDOWN (pipe_tx5_powerdown ), + .PIPETX6POWERDOWN (pipe_tx6_powerdown ), + .PIPETX7POWERDOWN (pipe_tx7_powerdown ), +`ifdef B_TESTMODE + .PMVOUT (pmv_out ), + .SCANOUT (scanout ), +`endif + .USERRSTN (user_rst_n ), + .PLRECEIVEDHOTRST (pl_received_hot_rst ), + .RECEIVEDFUNCLVLRSTN (received_func_lvl_rst_n ), + .LNKCLKEN (lnk_clk_en ), + .CFGMGMTDO (cfg_mgmt_do ), + .CFGMGMTRDWRDONEN (cfg_mgmt_rd_wr_done_n ), + .CFGERRAERHEADERLOGSETN (cfg_err_aer_headerlog_set_n ), + .CFGERRCPLRDYN (cfg_err_cpl_rdy_n ), + .CFGINTERRUPTRDYN (cfg_interrupt_rdy_n ), + .CFGINTERRUPTMMENABLE (cfg_interrupt_mmenable ), + .CFGINTERRUPTMSIENABLE (cfg_interrupt_msienable ), + .CFGINTERRUPTDO (cfg_interrupt_do ), + .CFGINTERRUPTMSIXENABLE (cfg_interrupt_msixenable ), + .CFGINTERRUPTMSIXFM (cfg_interrupt_msixfm ), + .CFGMSGRECEIVED (cfg_msg_received ), + .CFGMSGDATA (cfg_msg_data ), + .CFGMSGRECEIVEDERRCOR (cfg_msg_received_err_cor ), + .CFGMSGRECEIVEDERRNONFATAL (cfg_msg_received_err_non_fatal ), + .CFGMSGRECEIVEDERRFATAL (cfg_msg_received_err_fatal ), + .CFGMSGRECEIVEDASSERTINTA (cfg_msg_received_assert_int_a ), + .CFGMSGRECEIVEDDEASSERTINTA (cfg_msg_received_deassert_int_a ), + .CFGMSGRECEIVEDASSERTINTB (cfg_msg_received_assert_int_b ), + .CFGMSGRECEIVEDDEASSERTINTB (cfg_msg_received_deassert_int_b ), + .CFGMSGRECEIVEDASSERTINTC (cfg_msg_received_assert_int_c ), + .CFGMSGRECEIVEDDEASSERTINTC (cfg_msg_received_deassert_int_c ), + .CFGMSGRECEIVEDASSERTINTD (cfg_msg_received_assert_int_d ), + .CFGMSGRECEIVEDDEASSERTINTD (cfg_msg_received_deassert_int_d ), + .CFGMSGRECEIVEDPMPME (cfg_msg_received_pm_pme ), + .CFGMSGRECEIVEDPMETOACK (cfg_msg_received_pme_to_ack ), + .CFGMSGRECEIVEDPMETO (cfg_msg_received_pme_to ), + .CFGMSGRECEIVEDSETSLOTPOWERLIMIT (cfg_msg_received_setslotpowerlimit ), + .CFGMSGRECEIVEDUNLOCK (cfg_msg_received_unlock ), + .CFGMSGRECEIVEDPMASNAK (cfg_msg_received_pm_as_nak ), + .CFGPCIELINKSTATE (cfg_pcie_link_state ), + .CFGPMRCVASREQL1N (cfg_pm_rcv_as_req_l1_n ), + .CFGPMRCVREQACKN (cfg_pm_rcv_req_ack_n ), + .CFGPMRCVENTERL1N (cfg_pm_rcv_enter_l1_n ), + .CFGPMRCVENTERL23N (cfg_pm_rcv_enter_l23_n ), + .CFGPMCSRPOWERSTATE (cfg_pmcsr_powerstate ), + .CFGPMCSRPMEEN (cfg_pmcsr_pme_en ), + .CFGPMCSRPMESTATUS (cfg_pmcsr_pme_status ), + .CFGTRANSACTION (cfg_transaction ), + .CFGTRANSACTIONTYPE (cfg_transaction_type ), + .CFGTRANSACTIONADDR (cfg_transaction_addr ), + .CFGCOMMANDIOENABLE (cfg_command_io_enable ), + .CFGCOMMANDMEMENABLE (cfg_command_mem_enable ), + .CFGCOMMANDBUSMASTERENABLE (cfg_command_bus_master_enable ), + .CFGCOMMANDINTERRUPTDISABLE (cfg_command_interrupt_disable ), + .CFGCOMMANDSERREN (cfg_command_serr_en ), + .CFGBRIDGESERREN (cfg_bridge_serr_en ), + .CFGDEVSTATUSCORRERRDETECTED (cfg_dev_status_corr_err_detected ), + .CFGDEVSTATUSNONFATALERRDETECTED (cfg_dev_status_non_fatal_err_detected ), + .CFGDEVSTATUSFATALERRDETECTED (cfg_dev_status_fatal_err_detected ), + .CFGDEVSTATUSURDETECTED (cfg_dev_status_ur_detected ), + .CFGDEVCONTROLCORRERRREPORTINGEN (cfg_dev_control_corr_err_reporting_en ), + .CFGDEVCONTROLNONFATALREPORTINGEN (cfg_dev_control_non_fatal_reporting_en ), + .CFGDEVCONTROLFATALERRREPORTINGEN (cfg_dev_control_fatal_err_reporting_en ), + .CFGDEVCONTROLURERRREPORTINGEN (cfg_dev_control_ur_err_reporting_en ), + .CFGDEVCONTROLENABLERO (cfg_dev_control_enable_ro ), + .CFGDEVCONTROLMAXPAYLOAD (cfg_dev_control_max_payload ), + .CFGDEVCONTROLEXTTAGEN (cfg_dev_control_ext_tag_en ), + .CFGDEVCONTROLPHANTOMEN (cfg_dev_control_phantom_en ), + .CFGDEVCONTROLAUXPOWEREN (cfg_dev_control_aux_power_en ), + .CFGDEVCONTROLNOSNOOPEN (cfg_dev_control_no_snoop_en ), + .CFGDEVCONTROLMAXREADREQ (cfg_dev_control_max_read_req ), + .CFGLINKSTATUSCURRENTSPEED (cfg_link_status_current_speed ), + .CFGLINKSTATUSNEGOTIATEDWIDTH (cfg_link_status_negotiated_width ), + .CFGLINKSTATUSLINKTRAINING (cfg_link_status_link_training ), + .CFGLINKSTATUSDLLACTIVE (cfg_link_status_dll_active ), + .CFGLINKSTATUSBANDWIDTHSTATUS (cfg_link_status_bandwidth_status ), + .CFGLINKSTATUSAUTOBANDWIDTHSTATUS (cfg_link_status_auto_bandwidth_status ), + .CFGLINKCONTROLASPMCONTROL (cfg_link_control_aspm_control ), + .CFGLINKCONTROLRCB (cfg_link_control_rcb ), + .CFGLINKCONTROLLINKDISABLE (cfg_link_control_link_disable ), + .CFGLINKCONTROLRETRAINLINK (cfg_link_control_retrain_link ), + .CFGLINKCONTROLCOMMONCLOCK (cfg_link_control_common_clock ), + .CFGLINKCONTROLEXTENDEDSYNC (cfg_link_control_extended_sync ), + .CFGLINKCONTROLCLOCKPMEN (cfg_link_control_clock_pm_en ), + .CFGLINKCONTROLHWAUTOWIDTHDIS (cfg_link_control_hw_auto_width_dis ), + .CFGLINKCONTROLBANDWIDTHINTEN (cfg_link_control_bandwidth_int_en ), + .CFGLINKCONTROLAUTOBANDWIDTHINTEN (cfg_link_control_auto_bandwidth_int_en ), + .CFGDEVCONTROL2CPLTIMEOUTVAL (cfg_dev_control2_cpl_timeout_val ), + .CFGDEVCONTROL2CPLTIMEOUTDIS (cfg_dev_control2_cpl_timeout_dis ), + .CFGDEVCONTROL2ARIFORWARDEN (cfg_dev_control2_ari_forward_en ), + .CFGDEVCONTROL2ATOMICREQUESTEREN (cfg_dev_control2_atomic_requester_en ), + .CFGDEVCONTROL2ATOMICEGRESSBLOCK (cfg_dev_control2_atomic_egress_block ), + .CFGDEVCONTROL2IDOREQEN (cfg_dev_control2_ido_req_en ), + .CFGDEVCONTROL2IDOCPLEN (cfg_dev_control2_ido_cpl_en ), + .CFGDEVCONTROL2LTREN (cfg_dev_control2_ltr_en ), + .CFGDEVCONTROL2TLPPREFIXBLOCK (cfg_dev_control2_tlp_prefix_block ), + .CFGSLOTCONTROLELECTROMECHILCTLPULSE (cfg_slot_control_electromech_il_ctl_pulse ), + .CFGROOTCONTROLSYSERRCORRERREN (cfg_root_control_syserr_corr_err_en ), + .CFGROOTCONTROLSYSERRNONFATALERREN (cfg_root_control_syserr_non_fatal_err_en ), + .CFGROOTCONTROLSYSERRFATALERREN (cfg_root_control_syserr_fatal_err_en ), + .CFGROOTCONTROLPMEINTEN (cfg_root_control_pme_int_en ), + .CFGAERECRCCHECKEN (cfg_aer_ecrc_check_en ), + .CFGAERECRCGENEN (cfg_aer_ecrc_gen_en ), + .CFGAERROOTERRCORRERRREPORTINGEN (cfg_aer_rooterr_corr_err_reporting_en ), + .CFGAERROOTERRNONFATALERRREPORTINGEN (cfg_aer_rooterr_non_fatal_err_reporting_en ), + .CFGAERROOTERRFATALERRREPORTINGEN (cfg_aer_rooterr_fatal_err_reporting_en ), + .CFGAERROOTERRCORRERRRECEIVED (cfg_aer_rooterr_corr_err_received ), + .CFGAERROOTERRNONFATALERRRECEIVED (cfg_aer_rooterr_non_fatal_err_received ), + .CFGAERROOTERRFATALERRRECEIVED (cfg_aer_rooterr_fatal_err_received ), + .CFGVCTCVCMAP (cfg_vc_tcvc_map ), + .DRPRDY (drp_rdy ), + .DRPDO (drp_do ), + //.DRPWRITEEN (drp_write_en ), + //.DRPWRITEPORT0 (drp_write_port_0 ), + //.DRPWRITEPORT1 (drp_write_port_1 ), + //.DRPWRITEPORT2 (drp_write_port_2 ), + //.DRPWRITEPORT3 (drp_write_port_3 ), + //.DRPWRITEPORT4 (drp_write_port_4 ), + //.DRPWRITEPORT5 (drp_write_port_5 ), + //.DRPWRITEPORT6 (drp_write_port_6 ), + //.DRPWRITEPORT7 (drp_write_port_7 ), + //.DRPWRITEPORT8 (drp_write_port_8 ), + //.DRPWRITEPORT9 (drp_write_port_9 ), + //.DRPWRITEPORT10 (drp_write_port_10 ), + //.DRPWRITEPORT11 (drp_write_port_11 ), + //.DRPWRITEPORT12 (drp_write_port_12 ), + //.DRPREADADDR (drp_read_addr ), + .DBGVECA (dbg_vec_a ), + .DBGVECB (dbg_vec_b ), + .DBGVECC (dbg_vec_c ), + .DBGSCLRA (dbg_sclr_a ), + .DBGSCLRB (dbg_sclr_b ), + .DBGSCLRC (dbg_sclr_c ), + .DBGSCLRD (dbg_sclr_d ), + .DBGSCLRE (dbg_sclr_e ), + .DBGSCLRF (dbg_sclr_f ), + .DBGSCLRG (dbg_sclr_g ), + .DBGSCLRH (dbg_sclr_h ), + .DBGSCLRI (dbg_sclr_i ), + .DBGSCLRJ (dbg_sclr_j ), + .DBGSCLRK (dbg_sclr_k ), + .PLDBGVEC (pl_dbg_vec ) + //.XILUNCONNOUT (xil_unconn_out ) + ); + + + + +endmodule + +`endif // PCIE_2LM diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_bram_7x.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_bram_7x.v new file mode 100644 index 0000000..5874129 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_bram_7x.v @@ -0,0 +1,212 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pcie_bram_7x.v +// Version : 3.3 +// Description : single bram wrapper for the mb pcie block +// The bram A port is the write port +// the B port is the read port +// +// +//-----------------------------------------------------------------------------// + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pcie_bram_7x + #( + parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s + parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8 + parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT + parameter DOB_REG = 0, // 1 - use the output register; + // 0 - don't use the output register + parameter WIDTH = 0 // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36 + // 72 - uses RAMB36SDP + ) + ( + input user_clk_i,// user clock + input reset_i, // bram reset + + input wen_i, // write enable + input [12:0] waddr_i, // write address + input [WIDTH - 1:0] wdata_i, // write data + + input ren_i, // read enable + input rce_i, // output register clock enable + input [12:0] raddr_i, // read address + + output [WIDTH - 1:0] rdata_o // read data + ); + + // map the address bits + localparam ADDR_MSB = ((WIDTH == 4) ? 12 : + (WIDTH == 9) ? 11 : + (WIDTH == 18) ? 10 : + (WIDTH == 36) ? 9 : + 8 + ); + + // set the width of the tied off low address bits + localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 : + (WIDTH == 9) ? 3 : + (WIDTH == 18) ? 4 : + (WIDTH == 36) ? 5 : + 0 // for WIDTH 72 use RAMB36SDP + ); + + // map the data bits + localparam D_MSB = ((WIDTH == 4) ? 3 : + (WIDTH == 9) ? 7 : + (WIDTH == 18) ? 15 : + (WIDTH == 36) ? 31 : + 63 + ); + + // map the data parity bits + localparam DP_LSB = D_MSB + 1; + + localparam DP_MSB = ((WIDTH == 4) ? 4 : + (WIDTH == 9) ? 8 : + (WIDTH == 18) ? 17 : + (WIDTH == 36) ? 35 : + 71 + ); + + localparam DPW = DP_MSB - DP_LSB + 1; + localparam WRITE_MODE = ((WIDTH == 72) && (!((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)))) ? "WRITE_FIRST" : + ((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ? "WRITE_FIRST" : "NO_CHANGE"; + + localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6"; + localparam BRAM_SIZE = "36Kb"; + + localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ? + ((WIDTH <= 9) ? 1 : + (WIDTH > 9 && WIDTH <= 18) ? 2 : + (WIDTH > 18 && WIDTH <= 36) ? 4 : + (WIDTH > 36 && WIDTH <= 72) ? 8 : + (BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8; + + //synthesis translate_off + initial begin + //$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d", + // $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB); + + case (WIDTH) + 4,9,18,36,72:; + default: + begin + $display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH); + $finish; + end + endcase // case (WIDTH) + end + //synthesis translate_on + + generate + if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp + BRAM_SDP_MACRO #( + .DEVICE (DEVICE), + .BRAM_SIZE (BRAM_SIZE), + .DO_REG (DOB_REG), + .READ_WIDTH (WIDTH), + .WRITE_WIDTH (WIDTH), + .WRITE_MODE (WRITE_MODE) + ) + ramb36sdp( + .DO (rdata_o[WIDTH-1:0]), + .DI (wdata_i[WIDTH-1:0]), + .RDADDR (raddr_i[ADDR_MSB:0]), + .RDCLK (user_clk_i), + .RDEN (ren_i), + .REGCE (rce_i), + .RST (reset_i), + .WE ({WE_WIDTH{1'b1}}), + .WRADDR (waddr_i[ADDR_MSB:0]), + .WRCLK (user_clk_i), + .WREN (wen_i) + ); + + end // block: use_sdp + else if (WIDTH <= 36) begin : use_tdp + // use RAMB36's if the width is 4, 9, 18, or 36 + BRAM_TDP_MACRO #( + .DEVICE (DEVICE), + .BRAM_SIZE (BRAM_SIZE), + .DOA_REG (0), + .DOB_REG (DOB_REG), + .READ_WIDTH_A (WIDTH), + .READ_WIDTH_B (WIDTH), + .WRITE_WIDTH_A (WIDTH), + .WRITE_WIDTH_B (WIDTH), + .WRITE_MODE_A (WRITE_MODE) + ) + ramb36( + .DOA (), + .DOB (rdata_o[WIDTH-1:0]), + .ADDRA (waddr_i[ADDR_MSB:0]), + .ADDRB (raddr_i[ADDR_MSB:0]), + .CLKA (user_clk_i), + .CLKB (user_clk_i), + .DIA (wdata_i[WIDTH-1:0]), + .DIB ({WIDTH{1'b0}}), + .ENA (wen_i), + .ENB (ren_i), + .REGCEA (1'b0), + .REGCEB (rce_i), + .RSTA (reset_i), + .RSTB (reset_i), + .WEA ({WE_WIDTH{1'b1}}), + .WEB ({WE_WIDTH{1'b0}}) + ); + end // block: use_tdp + endgenerate + +endmodule // pcie_bram_7x + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_bram_top_7x.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_bram_top_7x.v new file mode 100644 index 0000000..9d87c1e --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_bram_top_7x.v @@ -0,0 +1,184 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pcie_bram_top_7x.v +// Version : 3.3 +// Description : bram wrapper for Tx and Rx +// given the pcie block attributes calculate the number of brams +// and pipeline stages and instantiate the brams +// +// Hierarchy: +// pcie_bram_top top level +// pcie_brams pcie_bram instantiations, +// pipeline stages (if any), +// address decode logic (if any), +// datapath muxing (if any) +// pcie_bram bram library cell wrapper +// the pcie_bram module can have a paramter that +// specifies the family (V6, V5, V4) +// +//----------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pcie_bram_top_7x +#( + parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT + parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0, // MPS Supported : 0 - 128 B, 1 - 256 B, 2 - 512 B, 3 - 1024 B + parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s + parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8 + + parameter VC0_TX_LASTPACKET = 31, // Number of Packets in Transmit + parameter TLM_TX_OVERHEAD = 24, // Overhead Bytes for Packets (Transmit) + parameter TL_TX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Transmit) + parameter TL_TX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Transmit) + parameter TL_TX_RAM_WRITE_LATENCY = 1, // BRAM Write Latency (Transmit) + + parameter VC0_RX_RAM_LIMIT = 'h1FFF, // RAM Size (Receive) + parameter TL_RX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Receive) + parameter TL_RX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Receive) + parameter TL_RX_RAM_WRITE_LATENCY = 1 // BRAM Write Latency (Receive) +) +( + input user_clk_i, // Clock input + input reset_i, // Reset input + + input mim_tx_wen, // Write Enable for Transmit path BRAM + input [12:0] mim_tx_waddr, // Write Address for Transmit path BRAM + input [71:0] mim_tx_wdata, // Write Data for Transmit path BRAM + input mim_tx_ren, // Read Enable for Transmit path BRAM + input mim_tx_rce, // Read Output Register Clock Enable for Transmit path BRAM + input [12:0] mim_tx_raddr, // Read Address for Transmit path BRAM + output [71:0] mim_tx_rdata, // Read Data for Transmit path BRAM + + input mim_rx_wen, // Write Enable for Receive path BRAM + input [12:0] mim_rx_waddr, // Write Enable for Receive path BRAM + input [71:0] mim_rx_wdata, // Write Enable for Receive path BRAM + input mim_rx_ren, // Read Enable for Receive path BRAM + input mim_rx_rce, // Read Output Register Clock Enable for Receive path BRAM + input [12:0] mim_rx_raddr, // Read Address for Receive path BRAM + output [71:0] mim_rx_rdata // Read Data for Receive path BRAM +); + + // TX calculations + localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 : + (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 : + (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 : + 1024 ); + + localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD); + + localparam ROWS_TX = 1; + localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 : + (BYTES_TX <= 8192) ? 2 : + (BYTES_TX <= 16384) ? 4 : + (BYTES_TX <= 32768) ? 8 : + 18 + ); + + // RX calculations + localparam ROWS_RX = 1; + + localparam COLS_RX = ((VC0_RX_RAM_LIMIT < 'h0200) ? 1 : + (VC0_RX_RAM_LIMIT < 'h0400) ? 2 : + (VC0_RX_RAM_LIMIT < 'h0800) ? 4 : + (VC0_RX_RAM_LIMIT < 'h1000) ? 8 : + 18 + ); + + initial begin + $display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX); + $display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX); + end + +pcie_7x_0_pcie_brams_7x #( + .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), + .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ), + .IMPL_TARGET ( IMPL_TARGET ), + .NUM_BRAMS ( COLS_TX ), + .RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ), + .RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ), + .RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ) + ) + pcie_brams_tx ( + .user_clk_i ( user_clk_i ), + .reset_i ( reset_i ), + .waddr ( mim_tx_waddr ), + .wen ( mim_tx_wen ), + .ren ( mim_tx_ren ), + .rce ( mim_tx_rce ), + .wdata ( mim_tx_wdata ), + .raddr ( mim_tx_raddr ), + .rdata ( mim_tx_rdata ) + ); + +pcie_7x_0_pcie_brams_7x #( + .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), + .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ), + .IMPL_TARGET ( IMPL_TARGET ), + .NUM_BRAMS ( COLS_RX ), + .RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ), + .RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ), + .RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ) + ) pcie_brams_rx ( + .user_clk_i ( user_clk_i ), + .reset_i ( reset_i ), + .waddr ( mim_rx_waddr ), + .wen ( mim_rx_wen ), + .ren ( mim_rx_ren ), + .rce ( mim_rx_rce ), + .wdata ( mim_rx_wdata ), + .raddr ( mim_rx_raddr ), + .rdata ( mim_rx_rdata ) + ); + +endmodule // pcie_bram_top + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_brams_7x.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_brams_7x.v new file mode 100644 index 0000000..161b9b8 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_brams_7x.v @@ -0,0 +1,296 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pcie_brams_7x.v +// Version : 3.3 +// Description : pcie bram wrapper +// arrange and connect brams +// implement address decoding, datapath muxing and pipeline stages +// +// banks of brams are used for 1,2,4,8,18 brams +// brams are stacked for other values of NUM_BRAMS +// +//----------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pcie_brams_7x +#( + parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s + parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8 + parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT + + // the number of BRAMs to use + // supported values are: + // 1,2,4,8,18 + parameter NUM_BRAMS = 0, + + // BRAM read address latency + // + // value meaning + // ==================================================== + // 0 BRAM read address port sample + // 1 BRAM read address port sample and a pipeline stage on the address port + parameter RAM_RADDR_LATENCY = 1, + + // BRAM read data latency + // + // value meaning + // ==================================================== + // 1 no BRAM OREG + // 2 use BRAM OREG + // 3 use BRAM OREG and a pipeline stage on the data port + parameter RAM_RDATA_LATENCY = 1, + + // BRAM write latency + // The BRAM write port is synchronous + // + // value meaning + // ==================================================== + // 0 BRAM write port sample + // 1 BRAM write port sample plus pipeline stage + parameter RAM_WRITE_LATENCY = 1, + parameter TCQ = 1 // synthesis warning removed: parameter declaration becomes local +) +( + input user_clk_i, + input reset_i, + + input wen, + input [12:0] waddr, + input [71:0] wdata, + input ren, + input rce, + input [12:0] raddr, + output [71:0] rdata + ); + + // turn on the bram output register + localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0; + + // calculate the data width of the individual brams + localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 : + (NUM_BRAMS == 2) ? 36 : + (NUM_BRAMS == 4) ? 18 : + (NUM_BRAMS == 8) ? 9 : + 4 + ); + +// parameter TCQ = 1; + + wire wen_int; + wire [12:0] waddr_int; + wire [71:0] wdata_int; + + wire ren_int; + wire [12:0] raddr_int; + wire [71:0] rdata_int; + + //synthesis translate_off + initial + begin + $display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d", + $time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY); + + case (NUM_BRAMS) + 1,2,4,8,18:; + default: + begin + $display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS); + $finish; + end + endcase // case(NUM_BRAMS) + + case (RAM_RADDR_LATENCY) + 0,1:; + default: + begin + $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY); + $finish; + end + endcase // case (RAM_RADDR_LATENCY) + + case (RAM_RDATA_LATENCY) + 1,2,3:; + default: + begin + $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY); + $finish; + end + endcase // case (RAM_RDATA_LATENCY) + + case (RAM_WRITE_LATENCY) + 0,1:; + default: + begin + $display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY); + $finish; + end + endcase // case(RAM_WRITE_LATENCY) + + end + //synthesis translate_on + + // model the delays for ram write latency + + generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2 + reg wen_q; + reg [12:0] waddr_q; + reg [71:0] wdata_q; + + always @(posedge user_clk_i) begin + if (reset_i) + begin + wen_q <= #TCQ 1'b0; + waddr_q <= #TCQ 13'b0; + // Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB. + // wdata_q <= #TCQ 72'b0; + end + else + begin + wen_q <= #TCQ wen; + waddr_q <= #TCQ waddr; + wdata_q <= #TCQ wdata; + end + end + + assign wen_int = wen_q; + assign waddr_int = waddr_q; + assign wdata_int = wdata_q; + end // if (RAM_WRITE_LATENCY == 1) + + else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1 + assign wen_int = wen; + assign waddr_int = waddr; + assign wdata_int = wdata; + end + endgenerate + + // model the delays for ram read latency + + generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2 + reg ren_q; + reg [12:0] raddr_q; + + always @(posedge user_clk_i) begin + if (reset_i) + begin + ren_q <= #TCQ 1'b0; + raddr_q <= #TCQ 13'b0; + end + else + begin + ren_q <= #TCQ ren; + raddr_q <= #TCQ raddr; + end // else: !if(reset_i) + end + + assign ren_int = ren_q; + assign raddr_int = raddr_q; + end // block: rd_lat_addr_2 + + else begin : raddr_lat_1 + assign ren_int = ren; + assign raddr_int = raddr; + end + endgenerate + + generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3 + reg [71:0] rdata_q; + + always @(posedge user_clk_i) begin + // Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB. + //if (reset_i) + //begin + // rdata_q <= #TCQ 72'b0; + //end + //else + //begin + rdata_q <= #TCQ rdata_int; + //end // else: !if(reset_i) + end + + assign rdata = rdata_q; + + end // block: rd_lat_data_3 + + else begin : rdata_lat_1_2 + assign rdata = rdata_int; + end + endgenerate + + // instantiate the brams + generate + genvar ii; + for (ii = 0; ii < NUM_BRAMS; ii = ii + 1) begin : brams +pcie_7x_0_pcie_bram_7x #( + .LINK_CAP_MAX_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH), + .LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED), + .IMPL_TARGET (IMPL_TARGET), + .DOB_REG (DOB_REG), + .WIDTH (WIDTH) + ) + ram ( + .user_clk_i(user_clk_i), + .reset_i(reset_i), + .wen_i(wen_int), + .waddr_i(waddr_int), + .wdata_i(wdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]), + .ren_i(ren_int), + .raddr_i(raddr_int), + .rdata_o(rdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]), + .rce_i(rce) + ); + end + endgenerate + +endmodule // pcie_brams_7x + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_pipe_lane.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_pipe_lane.v new file mode 100644 index 0000000..5fb1db4 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_pipe_lane.v @@ -0,0 +1,328 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pcie_pipe_lane.v +// Version : 3.3 +// +// Description: PIPE per lane module for 7-Series PCIe Block +// +// +// +//-------------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pcie_pipe_lane # +( + parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages + parameter TCQ = 1 // synthesis warning solved : parameter declaration becomes local +) +( + output wire [ 1:0] pipe_rx_char_is_k_o , // Pipelined PIPE Rx Char Is K + output wire [15:0] pipe_rx_data_o , // Pipelined PIPE Rx Data + output wire pipe_rx_valid_o , // Pipelined PIPE Rx Data Valid + output wire pipe_rx_chanisaligned_o , // Pipelined PIPE Rx Chan Is Aligned + output wire [ 2:0] pipe_rx_status_o , // Pipelined PIPE Rx Status + output wire pipe_rx_phy_status_o , // Pipelined PIPE Rx Phy Status + output wire pipe_rx_elec_idle_o , // Pipelined PIPE Rx Electrical Idle + input wire pipe_rx_polarity_i , // PIPE Rx Polarity + input wire pipe_tx_compliance_i , // PIPE Tx Compliance + input wire [ 1:0] pipe_tx_char_is_k_i , // PIPE Tx Char Is K + input wire [15:0] pipe_tx_data_i , // PIPE Tx Data + input wire pipe_tx_elec_idle_i , // PIPE Tx Electrical Idle + input wire [ 1:0] pipe_tx_powerdown_i , // PIPE Tx Powerdown + + input wire [ 1:0] pipe_rx_char_is_k_i , // PIPE Rx Char Is K + input wire [15:0] pipe_rx_data_i , // PIPE Rx Data + input wire pipe_rx_valid_i , // PIPE Rx Data Valid + input wire pipe_rx_chanisaligned_i , // PIPE Rx Chan Is Aligned + input wire [ 2:0] pipe_rx_status_i , // PIPE Rx Status + input wire pipe_rx_phy_status_i , // PIPE Rx Phy Status + input wire pipe_rx_elec_idle_i , // PIPE Rx Electrical Idle + output wire pipe_rx_polarity_o , // Pipelined PIPE Rx Polarity + output wire pipe_tx_compliance_o , // Pipelined PIPE Tx Compliance + output wire [ 1:0] pipe_tx_char_is_k_o , // Pipelined PIPE Tx Char Is K + output wire [15:0] pipe_tx_data_o , // Pipelined PIPE Tx Data + output wire pipe_tx_elec_idle_o , // Pipelined PIPE Tx Electrical Idle + output wire [ 1:0] pipe_tx_powerdown_o , // Pipelined PIPE Tx Powerdown + + input wire pipe_clk , // PIPE Clock + input wire rst_n // Reset +); + + //******************************************************************// + // Reality check. // + //******************************************************************// + +// parameter TCQ = 1; // clock to out delay model + + generate + + if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0 + + assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i; + assign pipe_rx_data_o = pipe_rx_data_i; + assign pipe_rx_valid_o = pipe_rx_valid_i; + assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_i; + assign pipe_rx_status_o = pipe_rx_status_i; + assign pipe_rx_phy_status_o = pipe_rx_phy_status_i; + assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i; + + assign pipe_rx_polarity_o = pipe_rx_polarity_i; + assign pipe_tx_compliance_o = pipe_tx_compliance_i; + assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i; + assign pipe_tx_data_o = pipe_tx_data_i; + assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i; + assign pipe_tx_powerdown_o = pipe_tx_powerdown_i; + + end // if (PIPE_PIPELINE_STAGES == 0) + else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1 + + reg [ 1:0] pipe_rx_char_is_k_q ; + reg [15:0] pipe_rx_data_q ; + reg pipe_rx_valid_q ; + reg pipe_rx_chanisaligned_q ; + reg [ 2:0] pipe_rx_status_q ; + reg pipe_rx_phy_status_q ; + reg pipe_rx_elec_idle_q ; + + reg pipe_rx_polarity_q ; + reg pipe_tx_compliance_q ; + reg [ 1:0] pipe_tx_char_is_k_q ; + reg [15:0] pipe_tx_data_q ; + reg pipe_tx_elec_idle_q ; + reg [ 1:0] pipe_tx_powerdown_q ; + + always @(posedge pipe_clk) begin + + if (rst_n) + begin + + pipe_rx_char_is_k_q <= #TCQ 0; + pipe_rx_data_q <= #TCQ 0; + pipe_rx_valid_q <= #TCQ 0; + pipe_rx_chanisaligned_q <= #TCQ 0; + pipe_rx_status_q <= #TCQ 0; + pipe_rx_phy_status_q <= #TCQ 0; + pipe_rx_elec_idle_q <= #TCQ 0; + + pipe_rx_polarity_q <= #TCQ 0; + pipe_tx_compliance_q <= #TCQ 0; + pipe_tx_char_is_k_q <= #TCQ 0; + pipe_tx_data_q <= #TCQ 0; + pipe_tx_elec_idle_q <= #TCQ 1'b1; + pipe_tx_powerdown_q <= #TCQ 2'b10; + + end + else + begin + + pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i; + pipe_rx_data_q <= #TCQ pipe_rx_data_i; + pipe_rx_valid_q <= #TCQ pipe_rx_valid_i; + pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i; + pipe_rx_status_q <= #TCQ pipe_rx_status_i; + pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i; + pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i; + + pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i; + pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i; + pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i; + pipe_tx_data_q <= #TCQ pipe_tx_data_i; + pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i; + pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i; + + end + + end + + assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_q; + assign pipe_rx_data_o = pipe_rx_data_q; + assign pipe_rx_valid_o = pipe_rx_valid_q; + assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_q; + assign pipe_rx_status_o = pipe_rx_status_q; + assign pipe_rx_phy_status_o = pipe_rx_phy_status_q; + assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_q; + + assign pipe_rx_polarity_o = pipe_rx_polarity_q; + assign pipe_tx_compliance_o = pipe_tx_compliance_q; + assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_q; + assign pipe_tx_data_o = pipe_tx_data_q; + assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_q; + assign pipe_tx_powerdown_o = pipe_tx_powerdown_q; + + end // if (PIPE_PIPELINE_STAGES == 1) + else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2 + + reg [ 1:0] pipe_rx_char_is_k_q ; + reg [15:0] pipe_rx_data_q ; + reg pipe_rx_valid_q ; + reg pipe_rx_chanisaligned_q ; + reg [ 2:0] pipe_rx_status_q ; + reg pipe_rx_phy_status_q ; + reg pipe_rx_elec_idle_q ; + + reg pipe_rx_polarity_q ; + reg pipe_tx_compliance_q ; + reg [ 1:0] pipe_tx_char_is_k_q ; + reg [15:0] pipe_tx_data_q ; + reg pipe_tx_elec_idle_q ; + reg [ 1:0] pipe_tx_powerdown_q ; + + reg [ 1:0] pipe_rx_char_is_k_qq ; + reg [15:0] pipe_rx_data_qq ; + reg pipe_rx_valid_qq ; + reg pipe_rx_chanisaligned_qq; + reg [ 2:0] pipe_rx_status_qq ; + reg pipe_rx_phy_status_qq ; + reg pipe_rx_elec_idle_qq ; + + reg pipe_rx_polarity_qq ; + reg pipe_tx_compliance_qq ; + reg [ 1:0] pipe_tx_char_is_k_qq ; + reg [15:0] pipe_tx_data_qq ; + reg pipe_tx_elec_idle_qq ; + reg [ 1:0] pipe_tx_powerdown_qq ; + + always @(posedge pipe_clk) begin + + if (rst_n) + begin + + pipe_rx_char_is_k_q <= #TCQ 0; + pipe_rx_data_q <= #TCQ 0; + pipe_rx_valid_q <= #TCQ 0; + pipe_rx_chanisaligned_q <= #TCQ 0; + pipe_rx_status_q <= #TCQ 0; + pipe_rx_phy_status_q <= #TCQ 0; + pipe_rx_elec_idle_q <= #TCQ 0; + + pipe_rx_polarity_q <= #TCQ 0; + pipe_tx_compliance_q <= #TCQ 0; + pipe_tx_char_is_k_q <= #TCQ 0; + pipe_tx_data_q <= #TCQ 0; + pipe_tx_elec_idle_q <= #TCQ 1'b1; + pipe_tx_powerdown_q <= #TCQ 2'b10; + + pipe_rx_char_is_k_qq <= #TCQ 0; + pipe_rx_data_qq <= #TCQ 0; + pipe_rx_valid_qq <= #TCQ 0; + pipe_rx_chanisaligned_qq <= #TCQ 0; + pipe_rx_status_qq <= #TCQ 0; + pipe_rx_phy_status_qq <= #TCQ 0; + pipe_rx_elec_idle_qq <= #TCQ 0; + + pipe_rx_polarity_qq <= #TCQ 0; + pipe_tx_compliance_qq <= #TCQ 0; + pipe_tx_char_is_k_qq <= #TCQ 0; + pipe_tx_data_qq <= #TCQ 0; + pipe_tx_elec_idle_qq <= #TCQ 1'b1; + pipe_tx_powerdown_qq <= #TCQ 2'b10; + + end + else + begin + + pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i; + pipe_rx_data_q <= #TCQ pipe_rx_data_i; + pipe_rx_valid_q <= #TCQ pipe_rx_valid_i; + pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i; + pipe_rx_status_q <= #TCQ pipe_rx_status_i; + pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i; + pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i; + + pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i; + pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i; + pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i; + pipe_tx_data_q <= #TCQ pipe_tx_data_i; + pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i; + pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i; + + pipe_rx_char_is_k_qq <= #TCQ pipe_rx_char_is_k_q; + pipe_rx_data_qq <= #TCQ pipe_rx_data_q; + pipe_rx_valid_qq <= #TCQ pipe_rx_valid_q; + pipe_rx_chanisaligned_qq <= #TCQ pipe_rx_chanisaligned_q; + pipe_rx_status_qq <= #TCQ pipe_rx_status_q; + pipe_rx_phy_status_qq <= #TCQ pipe_rx_phy_status_q; + pipe_rx_elec_idle_qq <= #TCQ pipe_rx_elec_idle_q; + + pipe_rx_polarity_qq <= #TCQ pipe_rx_polarity_q; + pipe_tx_compliance_qq <= #TCQ pipe_tx_compliance_q; + pipe_tx_char_is_k_qq <= #TCQ pipe_tx_char_is_k_q; + pipe_tx_data_qq <= #TCQ pipe_tx_data_q; + pipe_tx_elec_idle_qq <= #TCQ pipe_tx_elec_idle_q; + pipe_tx_powerdown_qq <= #TCQ pipe_tx_powerdown_q; + + end + + end + + assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_qq; + assign pipe_rx_data_o = pipe_rx_data_qq; + assign pipe_rx_valid_o = pipe_rx_valid_qq; + assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_qq; + assign pipe_rx_status_o = pipe_rx_status_qq; + assign pipe_rx_phy_status_o = pipe_rx_phy_status_qq; + assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_qq; + + assign pipe_rx_polarity_o = pipe_rx_polarity_qq; + assign pipe_tx_compliance_o = pipe_tx_compliance_qq; + assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_qq; + assign pipe_tx_data_o = pipe_tx_data_qq; + assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_qq; + assign pipe_tx_powerdown_o = pipe_tx_powerdown_qq; + + end // if (PIPE_PIPELINE_STAGES == 2) + + endgenerate + +endmodule + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_pipe_misc.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_pipe_misc.v new file mode 100644 index 0000000..e48a1f0 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_pipe_misc.v @@ -0,0 +1,219 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pcie_pipe_misc.v +// Version : 3.3 +// +// Description: Misc PIPE module for 7-Series PCIe Block +// +// +// +//-------------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pcie_pipe_misc # +( + parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages + parameter TCQ = 1 // synthesis warning solved: parameter declaration becomes local +) +( + + input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect + input wire pipe_tx_reset_i , // PIPE Tx Reset + input wire pipe_tx_rate_i , // PIPE Tx Rate + input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis + input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin + input wire pipe_tx_swing_i , // PIPE Tx Swing + + output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect + output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset + output wire pipe_tx_rate_o , // Pipelined PIPE Tx Rate + output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis + output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin + output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing + + input wire pipe_clk , // PIPE Clock + input wire rst_n // Reset +); + +//******************************************************************// +// Reality check. // +//******************************************************************// + +// parameter TCQ = 1; // clock to out delay model + + generate + + if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0 + + assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i; + assign pipe_tx_reset_o = pipe_tx_reset_i; + assign pipe_tx_rate_o = pipe_tx_rate_i; + assign pipe_tx_deemph_o = pipe_tx_deemph_i; + assign pipe_tx_margin_o = pipe_tx_margin_i; + assign pipe_tx_swing_o = pipe_tx_swing_i; + + end // if (PIPE_PIPELINE_STAGES == 0) + else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1 + + reg pipe_tx_rcvr_det_q ; + reg pipe_tx_reset_q ; + reg pipe_tx_rate_q ; + reg pipe_tx_deemph_q ; + reg [2:0] pipe_tx_margin_q ; + reg pipe_tx_swing_q ; + + always @(posedge pipe_clk) begin + + if (rst_n) + begin + + pipe_tx_rcvr_det_q <= #TCQ 0; + pipe_tx_reset_q <= #TCQ 1'b1; + pipe_tx_rate_q <= #TCQ 0; + pipe_tx_deemph_q <= #TCQ 1'b1; + pipe_tx_margin_q <= #TCQ 0; + pipe_tx_swing_q <= #TCQ 0; + + end + else + begin + + pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i; + pipe_tx_reset_q <= #TCQ pipe_tx_reset_i; + pipe_tx_rate_q <= #TCQ pipe_tx_rate_i; + pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i; + pipe_tx_margin_q <= #TCQ pipe_tx_margin_i; + pipe_tx_swing_q <= #TCQ pipe_tx_swing_i; + + end + + end + + assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q; + assign pipe_tx_reset_o = pipe_tx_reset_q; + assign pipe_tx_rate_o = pipe_tx_rate_q; + assign pipe_tx_deemph_o = pipe_tx_deemph_q; + assign pipe_tx_margin_o = pipe_tx_margin_q; + assign pipe_tx_swing_o = pipe_tx_swing_q; + + end // if (PIPE_PIPELINE_STAGES == 1) + else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2 + + reg pipe_tx_rcvr_det_q ; + reg pipe_tx_reset_q ; + reg pipe_tx_rate_q ; + reg pipe_tx_deemph_q ; + reg [2:0] pipe_tx_margin_q ; + reg pipe_tx_swing_q ; + + reg pipe_tx_rcvr_det_qq ; + reg pipe_tx_reset_qq ; + reg pipe_tx_rate_qq ; + reg pipe_tx_deemph_qq ; + reg [2:0] pipe_tx_margin_qq ; + reg pipe_tx_swing_qq ; + + always @(posedge pipe_clk) begin + + if (rst_n) + begin + + pipe_tx_rcvr_det_q <= #TCQ 0; + pipe_tx_reset_q <= #TCQ 1'b1; + pipe_tx_rate_q <= #TCQ 0; + pipe_tx_deemph_q <= #TCQ 1'b1; + pipe_tx_margin_q <= #TCQ 0; + pipe_tx_swing_q <= #TCQ 0; + + pipe_tx_rcvr_det_qq <= #TCQ 0; + pipe_tx_reset_qq <= #TCQ 1'b1; + pipe_tx_rate_qq <= #TCQ 0; + pipe_tx_deemph_qq <= #TCQ 1'b1; + pipe_tx_margin_qq <= #TCQ 0; + pipe_tx_swing_qq <= #TCQ 0; + + end + else + begin + + pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i; + pipe_tx_reset_q <= #TCQ pipe_tx_reset_i; + pipe_tx_rate_q <= #TCQ pipe_tx_rate_i; + pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i; + pipe_tx_margin_q <= #TCQ pipe_tx_margin_i; + pipe_tx_swing_q <= #TCQ pipe_tx_swing_i; + + pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q; + pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q; + pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q; + pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q; + pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q; + pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q; + + end + + end + + assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq; + assign pipe_tx_reset_o = pipe_tx_reset_qq; + assign pipe_tx_rate_o = pipe_tx_rate_qq; + assign pipe_tx_deemph_o = pipe_tx_deemph_qq; + assign pipe_tx_margin_o = pipe_tx_margin_qq; + assign pipe_tx_swing_o = pipe_tx_swing_qq; + + end // if (PIPE_PIPELINE_STAGES == 2) + + endgenerate + +endmodule + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_pipe_pipeline.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_pipe_pipeline.v new file mode 100644 index 0000000..2629455 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_pipe_pipeline.v @@ -0,0 +1,798 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pcie_pipe_pipeline.v +// Version : 3.3 +// +// Description: PIPE module for Virtex7 PCIe Block +// +// +// +//-------------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pcie_pipe_pipeline # +( + parameter LINK_CAP_MAX_LINK_WIDTH = 8, + parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages +) +( + // Pipe Per-Link Signals + input wire pipe_tx_rcvr_det_i , + input wire pipe_tx_reset_i , + input wire pipe_tx_rate_i , + input wire pipe_tx_deemph_i , + input wire [2:0] pipe_tx_margin_i , + input wire pipe_tx_swing_i , + + output wire pipe_tx_rcvr_det_o , + output wire pipe_tx_reset_o , + output wire pipe_tx_rate_o , + output wire pipe_tx_deemph_o , + output wire [2:0] pipe_tx_margin_o , + output wire pipe_tx_swing_o , + + // Pipe Per-Lane Signals - Lane 0 + output wire [ 1:0] pipe_rx0_char_is_k_o , + output wire [15:0] pipe_rx0_data_o , + output wire pipe_rx0_valid_o , + output wire pipe_rx0_chanisaligned_o , + output wire [ 2:0] pipe_rx0_status_o , + output wire pipe_rx0_phy_status_o , + output wire pipe_rx0_elec_idle_o , + input wire pipe_rx0_polarity_i , + input wire pipe_tx0_compliance_i , + input wire [ 1:0] pipe_tx0_char_is_k_i , + input wire [15:0] pipe_tx0_data_i , + input wire pipe_tx0_elec_idle_i , + input wire [ 1:0] pipe_tx0_powerdown_i , + + input wire [ 1:0] pipe_rx0_char_is_k_i , + input wire [15:0] pipe_rx0_data_i , + input wire pipe_rx0_valid_i , + input wire pipe_rx0_chanisaligned_i , + input wire [ 2:0] pipe_rx0_status_i , + input wire pipe_rx0_phy_status_i , + input wire pipe_rx0_elec_idle_i , + output wire pipe_rx0_polarity_o , + output wire pipe_tx0_compliance_o , + output wire [ 1:0] pipe_tx0_char_is_k_o , + output wire [15:0] pipe_tx0_data_o , + output wire pipe_tx0_elec_idle_o , + output wire [ 1:0] pipe_tx0_powerdown_o , + + // Pipe Per-Lane Signals - Lane 1 + output wire [ 1:0] pipe_rx1_char_is_k_o , + output wire [15:0] pipe_rx1_data_o , + output wire pipe_rx1_valid_o , + output wire pipe_rx1_chanisaligned_o , + output wire [ 2:0] pipe_rx1_status_o , + output wire pipe_rx1_phy_status_o , + output wire pipe_rx1_elec_idle_o , + input wire pipe_rx1_polarity_i , + input wire pipe_tx1_compliance_i , + input wire [ 1:0] pipe_tx1_char_is_k_i , + input wire [15:0] pipe_tx1_data_i , + input wire pipe_tx1_elec_idle_i , + input wire [ 1:0] pipe_tx1_powerdown_i , + + input wire [ 1:0] pipe_rx1_char_is_k_i , + input wire [15:0] pipe_rx1_data_i , + input wire pipe_rx1_valid_i , + input wire pipe_rx1_chanisaligned_i , + input wire [ 2:0] pipe_rx1_status_i , + input wire pipe_rx1_phy_status_i , + input wire pipe_rx1_elec_idle_i , + output wire pipe_rx1_polarity_o , + output wire pipe_tx1_compliance_o , + output wire [ 1:0] pipe_tx1_char_is_k_o , + output wire [15:0] pipe_tx1_data_o , + output wire pipe_tx1_elec_idle_o , + output wire [ 1:0] pipe_tx1_powerdown_o , + + // Pipe Per-Lane Signals - Lane 2 + output wire [ 1:0] pipe_rx2_char_is_k_o , + output wire [15:0] pipe_rx2_data_o , + output wire pipe_rx2_valid_o , + output wire pipe_rx2_chanisaligned_o , + output wire [ 2:0] pipe_rx2_status_o , + output wire pipe_rx2_phy_status_o , + output wire pipe_rx2_elec_idle_o , + input wire pipe_rx2_polarity_i , + input wire pipe_tx2_compliance_i , + input wire [ 1:0] pipe_tx2_char_is_k_i , + input wire [15:0] pipe_tx2_data_i , + input wire pipe_tx2_elec_idle_i , + input wire [ 1:0] pipe_tx2_powerdown_i , + + input wire [ 1:0] pipe_rx2_char_is_k_i , + input wire [15:0] pipe_rx2_data_i , + input wire pipe_rx2_valid_i , + input wire pipe_rx2_chanisaligned_i , + input wire [ 2:0] pipe_rx2_status_i , + input wire pipe_rx2_phy_status_i , + input wire pipe_rx2_elec_idle_i , + output wire pipe_rx2_polarity_o , + output wire pipe_tx2_compliance_o , + output wire [ 1:0] pipe_tx2_char_is_k_o , + output wire [15:0] pipe_tx2_data_o , + output wire pipe_tx2_elec_idle_o , + output wire [ 1:0] pipe_tx2_powerdown_o , + + // Pipe Per-Lane Signals - Lane 3 + output wire [ 1:0] pipe_rx3_char_is_k_o , + output wire [15:0] pipe_rx3_data_o , + output wire pipe_rx3_valid_o , + output wire pipe_rx3_chanisaligned_o , + output wire [ 2:0] pipe_rx3_status_o , + output wire pipe_rx3_phy_status_o , + output wire pipe_rx3_elec_idle_o , + input wire pipe_rx3_polarity_i , + input wire pipe_tx3_compliance_i , + input wire [ 1:0] pipe_tx3_char_is_k_i , + input wire [15:0] pipe_tx3_data_i , + input wire pipe_tx3_elec_idle_i , + input wire [ 1:0] pipe_tx3_powerdown_i , + + input wire [ 1:0] pipe_rx3_char_is_k_i , + input wire [15:0] pipe_rx3_data_i , + input wire pipe_rx3_valid_i , + input wire pipe_rx3_chanisaligned_i , + input wire [ 2:0] pipe_rx3_status_i , + input wire pipe_rx3_phy_status_i , + input wire pipe_rx3_elec_idle_i , + output wire pipe_rx3_polarity_o , + output wire pipe_tx3_compliance_o , + output wire [ 1:0] pipe_tx3_char_is_k_o , + output wire [15:0] pipe_tx3_data_o , + output wire pipe_tx3_elec_idle_o , + output wire [ 1:0] pipe_tx3_powerdown_o , + + // Pipe Per-Lane Signals - Lane 4 + output wire [ 1:0] pipe_rx4_char_is_k_o , + output wire [15:0] pipe_rx4_data_o , + output wire pipe_rx4_valid_o , + output wire pipe_rx4_chanisaligned_o , + output wire [ 2:0] pipe_rx4_status_o , + output wire pipe_rx4_phy_status_o , + output wire pipe_rx4_elec_idle_o , + input wire pipe_rx4_polarity_i , + input wire pipe_tx4_compliance_i , + input wire [ 1:0] pipe_tx4_char_is_k_i , + input wire [15:0] pipe_tx4_data_i , + input wire pipe_tx4_elec_idle_i , + input wire [ 1:0] pipe_tx4_powerdown_i , + + input wire [ 1:0] pipe_rx4_char_is_k_i , + input wire [15:0] pipe_rx4_data_i , + input wire pipe_rx4_valid_i , + input wire pipe_rx4_chanisaligned_i , + input wire [ 2:0] pipe_rx4_status_i , + input wire pipe_rx4_phy_status_i , + input wire pipe_rx4_elec_idle_i , + output wire pipe_rx4_polarity_o , + output wire pipe_tx4_compliance_o , + output wire [ 1:0] pipe_tx4_char_is_k_o , + output wire [15:0] pipe_tx4_data_o , + output wire pipe_tx4_elec_idle_o , + output wire [ 1:0] pipe_tx4_powerdown_o , + + // Pipe Per-Lane Signals - Lane 5 + output wire [ 1:0] pipe_rx5_char_is_k_o , + output wire [15:0] pipe_rx5_data_o , + output wire pipe_rx5_valid_o , + output wire pipe_rx5_chanisaligned_o , + output wire [ 2:0] pipe_rx5_status_o , + output wire pipe_rx5_phy_status_o , + output wire pipe_rx5_elec_idle_o , + input wire pipe_rx5_polarity_i , + input wire pipe_tx5_compliance_i , + input wire [ 1:0] pipe_tx5_char_is_k_i , + input wire [15:0] pipe_tx5_data_i , + input wire pipe_tx5_elec_idle_i , + input wire [ 1:0] pipe_tx5_powerdown_i , + + input wire [ 1:0] pipe_rx5_char_is_k_i , + input wire [15:0] pipe_rx5_data_i , + input wire pipe_rx5_valid_i , + input wire pipe_rx5_chanisaligned_i , + input wire [ 2:0] pipe_rx5_status_i , + input wire pipe_rx5_phy_status_i , + input wire pipe_rx5_elec_idle_i , + output wire pipe_rx5_polarity_o , + output wire pipe_tx5_compliance_o , + output wire [ 1:0] pipe_tx5_char_is_k_o , + output wire [15:0] pipe_tx5_data_o , + output wire pipe_tx5_elec_idle_o , + output wire [ 1:0] pipe_tx5_powerdown_o , + + // Pipe Per-Lane Signals - Lane 6 + output wire [ 1:0] pipe_rx6_char_is_k_o , + output wire [15:0] pipe_rx6_data_o , + output wire pipe_rx6_valid_o , + output wire pipe_rx6_chanisaligned_o , + output wire [ 2:0] pipe_rx6_status_o , + output wire pipe_rx6_phy_status_o , + output wire pipe_rx6_elec_idle_o , + input wire pipe_rx6_polarity_i , + input wire pipe_tx6_compliance_i , + input wire [ 1:0] pipe_tx6_char_is_k_i , + input wire [15:0] pipe_tx6_data_i , + input wire pipe_tx6_elec_idle_i , + input wire [ 1:0] pipe_tx6_powerdown_i , + + input wire [ 1:0] pipe_rx6_char_is_k_i , + input wire [15:0] pipe_rx6_data_i , + input wire pipe_rx6_valid_i , + input wire pipe_rx6_chanisaligned_i , + input wire [ 2:0] pipe_rx6_status_i , + input wire pipe_rx6_phy_status_i , + input wire pipe_rx6_elec_idle_i , + output wire pipe_rx6_polarity_o , + output wire pipe_tx6_compliance_o , + output wire [ 1:0] pipe_tx6_char_is_k_o , + output wire [15:0] pipe_tx6_data_o , + output wire pipe_tx6_elec_idle_o , + output wire [ 1:0] pipe_tx6_powerdown_o , + + // Pipe Per-Lane Signals - Lane 7 + output wire [ 1:0] pipe_rx7_char_is_k_o , + output wire [15:0] pipe_rx7_data_o , + output wire pipe_rx7_valid_o , + output wire pipe_rx7_chanisaligned_o , + output wire [ 2:0] pipe_rx7_status_o , + output wire pipe_rx7_phy_status_o , + output wire pipe_rx7_elec_idle_o , + input wire pipe_rx7_polarity_i , + input wire pipe_tx7_compliance_i , + input wire [ 1:0] pipe_tx7_char_is_k_i , + input wire [15:0] pipe_tx7_data_i , + input wire pipe_tx7_elec_idle_i , + input wire [ 1:0] pipe_tx7_powerdown_i , + + input wire [ 1:0] pipe_rx7_char_is_k_i , + input wire [15:0] pipe_rx7_data_i , + input wire pipe_rx7_valid_i , + input wire pipe_rx7_chanisaligned_i , + input wire [ 2:0] pipe_rx7_status_i , + input wire pipe_rx7_phy_status_i , + input wire pipe_rx7_elec_idle_i , + output wire pipe_rx7_polarity_o , + output wire pipe_tx7_compliance_o , + output wire [ 1:0] pipe_tx7_char_is_k_o , + output wire [15:0] pipe_tx7_data_o , + output wire pipe_tx7_elec_idle_o , + output wire [ 1:0] pipe_tx7_powerdown_o , + + // Non PIPE signals + input wire pipe_clk , + input wire rst_n +); + + //******************************************************************// + // Reality check. // + //******************************************************************// + + //synthesis translate_off + // initial begin + // $display("[%t] %m LINK_CAP_MAX_LINK_WIDTH %0d PIPE_PIPELINE_STAGES %0d", + // $time, LINK_CAP_MAX_LINK_WIDTH, PIPE_PIPELINE_STAGES); + // end + //synthesis translate_on + + generate + +pcie_7x_0_pcie_pipe_misc # ( + + .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) + + ) + pipe_misc_i ( + + .pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i), + .pipe_tx_reset_i(pipe_tx_reset_i), + .pipe_tx_rate_i(pipe_tx_rate_i), + .pipe_tx_deemph_i(pipe_tx_deemph_i), + .pipe_tx_margin_i(pipe_tx_margin_i), + .pipe_tx_swing_i(pipe_tx_swing_i), + + .pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o), + .pipe_tx_reset_o(pipe_tx_reset_o), + .pipe_tx_rate_o(pipe_tx_rate_o), + .pipe_tx_deemph_o(pipe_tx_deemph_o), + .pipe_tx_margin_o(pipe_tx_margin_o), + .pipe_tx_swing_o(pipe_tx_swing_o) , + + .pipe_clk(pipe_clk), + .rst_n(rst_n) + ); + + +pcie_7x_0_pcie_pipe_lane # ( + + .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) + + ) + pipe_lane_0_i ( + + .pipe_rx_char_is_k_o(pipe_rx0_char_is_k_o), + .pipe_rx_data_o(pipe_rx0_data_o), + .pipe_rx_valid_o(pipe_rx0_valid_o), + .pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o), + .pipe_rx_status_o(pipe_rx0_status_o), + .pipe_rx_phy_status_o(pipe_rx0_phy_status_o), + .pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o), + .pipe_rx_polarity_i(pipe_rx0_polarity_i), + .pipe_tx_compliance_i(pipe_tx0_compliance_i), + .pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i), + .pipe_tx_data_i(pipe_tx0_data_i), + .pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i), + .pipe_tx_powerdown_i(pipe_tx0_powerdown_i), + + .pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i), + .pipe_rx_data_i(pipe_rx0_data_i), + .pipe_rx_valid_i(pipe_rx0_valid_i), + .pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i), + .pipe_rx_status_i(pipe_rx0_status_i), + .pipe_rx_phy_status_i(pipe_rx0_phy_status_i), + .pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i), + .pipe_rx_polarity_o(pipe_rx0_polarity_o), + .pipe_tx_compliance_o(pipe_tx0_compliance_o), + .pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o), + .pipe_tx_data_o(pipe_tx0_data_o), + .pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o), + .pipe_tx_powerdown_o(pipe_tx0_powerdown_o), + + .pipe_clk(pipe_clk), + .rst_n(rst_n) + + ); + + if (LINK_CAP_MAX_LINK_WIDTH >= 2) begin : pipe_2_lane + +pcie_7x_0_pcie_pipe_lane # ( + + .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) + + ) + pipe_lane_1_i ( + + .pipe_rx_char_is_k_o(pipe_rx1_char_is_k_o), + .pipe_rx_data_o(pipe_rx1_data_o), + .pipe_rx_valid_o(pipe_rx1_valid_o), + .pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o), + .pipe_rx_status_o(pipe_rx1_status_o), + .pipe_rx_phy_status_o(pipe_rx1_phy_status_o), + .pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o), + .pipe_rx_polarity_i(pipe_rx1_polarity_i), + .pipe_tx_compliance_i(pipe_tx1_compliance_i), + .pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i), + .pipe_tx_data_i(pipe_tx1_data_i), + .pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i), + .pipe_tx_powerdown_i(pipe_tx1_powerdown_i), + + .pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i), + .pipe_rx_data_i(pipe_rx1_data_i), + .pipe_rx_valid_i(pipe_rx1_valid_i), + .pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i), + .pipe_rx_status_i(pipe_rx1_status_i), + .pipe_rx_phy_status_i(pipe_rx1_phy_status_i), + .pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i), + .pipe_rx_polarity_o(pipe_rx1_polarity_o), + .pipe_tx_compliance_o(pipe_tx1_compliance_o), + .pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o), + .pipe_tx_data_o(pipe_tx1_data_o), + .pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o), + .pipe_tx_powerdown_o(pipe_tx1_powerdown_o), + + .pipe_clk(pipe_clk), + .rst_n(rst_n) + + ); + + end // if (LINK_CAP_MAX_LINK_WIDTH >= 2) + else + begin + assign pipe_rx1_char_is_k_o = 2'b00; + assign pipe_rx1_data_o = 16'h0000; + assign pipe_rx1_valid_o = 1'b0; + assign pipe_rx1_chanisaligned_o = 1'b0; + assign pipe_rx1_status_o = 3'b000; + assign pipe_rx1_phy_status_o = 1'b0; + assign pipe_rx1_elec_idle_o = 1'b1; + assign pipe_rx1_polarity_o = 1'b0; + assign pipe_tx1_compliance_o = 1'b0; + assign pipe_tx1_char_is_k_o = 2'b00; + assign pipe_tx1_data_o = 16'h0000; + assign pipe_tx1_elec_idle_o = 1'b1; + assign pipe_tx1_powerdown_o = 2'b00; + end // if !(LINK_CAP_MAX_LINK_WIDTH >= 2) + + if (LINK_CAP_MAX_LINK_WIDTH >= 4) begin : pipe_4_lane + +pcie_7x_0_pcie_pipe_lane # ( + + .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) + ) + pipe_lane_2_i ( + + .pipe_rx_char_is_k_o(pipe_rx2_char_is_k_o), + .pipe_rx_data_o(pipe_rx2_data_o), + .pipe_rx_valid_o(pipe_rx2_valid_o), + .pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o), + .pipe_rx_status_o(pipe_rx2_status_o), + .pipe_rx_phy_status_o(pipe_rx2_phy_status_o), + .pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o), + .pipe_rx_polarity_i(pipe_rx2_polarity_i), + .pipe_tx_compliance_i(pipe_tx2_compliance_i), + .pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i), + .pipe_tx_data_i(pipe_tx2_data_i), + .pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i), + .pipe_tx_powerdown_i(pipe_tx2_powerdown_i), + + .pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i), + .pipe_rx_data_i(pipe_rx2_data_i), + .pipe_rx_valid_i(pipe_rx2_valid_i), + .pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i), + .pipe_rx_status_i(pipe_rx2_status_i), + .pipe_rx_phy_status_i(pipe_rx2_phy_status_i), + .pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i), + .pipe_rx_polarity_o(pipe_rx2_polarity_o), + .pipe_tx_compliance_o(pipe_tx2_compliance_o), + .pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o), + .pipe_tx_data_o(pipe_tx2_data_o), + .pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o), + .pipe_tx_powerdown_o(pipe_tx2_powerdown_o), + + .pipe_clk(pipe_clk), + .rst_n(rst_n) + + ); + +pcie_7x_0_pcie_pipe_lane # ( + + .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) + + ) + pipe_lane_3_i ( + + .pipe_rx_char_is_k_o(pipe_rx3_char_is_k_o), + .pipe_rx_data_o(pipe_rx3_data_o), + .pipe_rx_valid_o(pipe_rx3_valid_o), + .pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o), + .pipe_rx_status_o(pipe_rx3_status_o), + .pipe_rx_phy_status_o(pipe_rx3_phy_status_o), + .pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o), + .pipe_rx_polarity_i(pipe_rx3_polarity_i), + .pipe_tx_compliance_i(pipe_tx3_compliance_i), + .pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i), + .pipe_tx_data_i(pipe_tx3_data_i), + .pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i), + .pipe_tx_powerdown_i(pipe_tx3_powerdown_i), + + .pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i), + .pipe_rx_data_i(pipe_rx3_data_i), + .pipe_rx_valid_i(pipe_rx3_valid_i), + .pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i), + .pipe_rx_status_i(pipe_rx3_status_i), + .pipe_rx_phy_status_i(pipe_rx3_phy_status_i), + .pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i), + .pipe_rx_polarity_o(pipe_rx3_polarity_o), + .pipe_tx_compliance_o(pipe_tx3_compliance_o), + .pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o), + .pipe_tx_data_o(pipe_tx3_data_o), + .pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o), + .pipe_tx_powerdown_o(pipe_tx3_powerdown_o), + + .pipe_clk(pipe_clk), + .rst_n(rst_n) + + ); + + end // if (LINK_CAP_MAX_LINK_WIDTH >= 4) + else + begin + assign pipe_rx2_char_is_k_o = 2'b00; + assign pipe_rx2_data_o = 16'h0000; + assign pipe_rx2_valid_o = 1'b0; + assign pipe_rx2_chanisaligned_o = 1'b0; + assign pipe_rx2_status_o = 3'b000; + assign pipe_rx2_phy_status_o = 1'b0; + assign pipe_rx2_elec_idle_o = 1'b1; + assign pipe_rx2_polarity_o = 1'b0; + assign pipe_tx2_compliance_o = 1'b0; + assign pipe_tx2_char_is_k_o = 2'b00; + assign pipe_tx2_data_o = 16'h0000; + assign pipe_tx2_elec_idle_o = 1'b1; + assign pipe_tx2_powerdown_o = 2'b00; + + assign pipe_rx3_char_is_k_o = 2'b00; + assign pipe_rx3_data_o = 16'h0000; + assign pipe_rx3_valid_o = 1'b0; + assign pipe_rx3_chanisaligned_o = 1'b0; + assign pipe_rx3_status_o = 3'b000; + assign pipe_rx3_phy_status_o = 1'b0; + assign pipe_rx3_elec_idle_o = 1'b1; + assign pipe_rx3_polarity_o = 1'b0; + assign pipe_tx3_compliance_o = 1'b0; + assign pipe_tx3_char_is_k_o = 2'b00; + assign pipe_tx3_data_o = 16'h0000; + assign pipe_tx3_elec_idle_o = 1'b1; + assign pipe_tx3_powerdown_o = 2'b00; + end // if !(LINK_CAP_MAX_LINK_WIDTH >= 4) + + if (LINK_CAP_MAX_LINK_WIDTH >= 8) begin : pipe_8_lane + +pcie_7x_0_pcie_pipe_lane # ( + + .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) + + ) + pipe_lane_4_i ( + + .pipe_rx_char_is_k_o(pipe_rx4_char_is_k_o), + .pipe_rx_data_o(pipe_rx4_data_o), + .pipe_rx_valid_o(pipe_rx4_valid_o), + .pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o), + .pipe_rx_status_o(pipe_rx4_status_o), + .pipe_rx_phy_status_o(pipe_rx4_phy_status_o), + .pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o), + .pipe_rx_polarity_i(pipe_rx4_polarity_i), + .pipe_tx_compliance_i(pipe_tx4_compliance_i), + .pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i), + .pipe_tx_data_i(pipe_tx4_data_i), + .pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i), + .pipe_tx_powerdown_i(pipe_tx4_powerdown_i), + + .pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i), + .pipe_rx_data_i(pipe_rx4_data_i), + .pipe_rx_valid_i(pipe_rx4_valid_i), + .pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i), + .pipe_rx_status_i(pipe_rx4_status_i), + .pipe_rx_phy_status_i(pipe_rx4_phy_status_i), + .pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i), + .pipe_rx_polarity_o(pipe_rx4_polarity_o), + .pipe_tx_compliance_o(pipe_tx4_compliance_o), + .pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o), + .pipe_tx_data_o(pipe_tx4_data_o), + .pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o), + .pipe_tx_powerdown_o(pipe_tx4_powerdown_o), + + .pipe_clk(pipe_clk), + .rst_n(rst_n) + + ); + +pcie_7x_0_pcie_pipe_lane # ( + + .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) + + ) + pipe_lane_5_i ( + + .pipe_rx_char_is_k_o(pipe_rx5_char_is_k_o), + .pipe_rx_data_o(pipe_rx5_data_o), + .pipe_rx_valid_o(pipe_rx5_valid_o), + .pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o), + .pipe_rx_status_o(pipe_rx5_status_o), + .pipe_rx_phy_status_o(pipe_rx5_phy_status_o), + .pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o), + .pipe_rx_polarity_i(pipe_rx5_polarity_i), + .pipe_tx_compliance_i(pipe_tx5_compliance_i), + .pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i), + .pipe_tx_data_i(pipe_tx5_data_i), + .pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i), + .pipe_tx_powerdown_i(pipe_tx5_powerdown_i), + + .pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i), + .pipe_rx_data_i(pipe_rx5_data_i), + .pipe_rx_valid_i(pipe_rx5_valid_i), + .pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i), + .pipe_rx_status_i(pipe_rx5_status_i), + .pipe_rx_phy_status_i(pipe_rx5_phy_status_i), + .pipe_rx_elec_idle_i(pipe_rx5_elec_idle_i), + .pipe_rx_polarity_o(pipe_rx5_polarity_o), + .pipe_tx_compliance_o(pipe_tx5_compliance_o), + .pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o), + .pipe_tx_data_o(pipe_tx5_data_o), + .pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o), + .pipe_tx_powerdown_o(pipe_tx5_powerdown_o), + + .pipe_clk(pipe_clk), + .rst_n(rst_n) + + ); + +pcie_7x_0_pcie_pipe_lane # ( + + .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) + + ) + pipe_lane_6_i ( + + .pipe_rx_char_is_k_o(pipe_rx6_char_is_k_o), + .pipe_rx_data_o(pipe_rx6_data_o), + .pipe_rx_valid_o(pipe_rx6_valid_o), + .pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o), + .pipe_rx_status_o(pipe_rx6_status_o), + .pipe_rx_phy_status_o(pipe_rx6_phy_status_o), + .pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o), + .pipe_rx_polarity_i(pipe_rx6_polarity_i), + .pipe_tx_compliance_i(pipe_tx6_compliance_i), + .pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i), + .pipe_tx_data_i(pipe_tx6_data_i), + .pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i), + .pipe_tx_powerdown_i(pipe_tx6_powerdown_i), + + .pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i), + .pipe_rx_data_i(pipe_rx6_data_i), + .pipe_rx_valid_i(pipe_rx6_valid_i), + .pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i), + .pipe_rx_status_i(pipe_rx6_status_i), + .pipe_rx_phy_status_i(pipe_rx6_phy_status_i), + .pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i), + .pipe_rx_polarity_o(pipe_rx6_polarity_o), + .pipe_tx_compliance_o(pipe_tx6_compliance_o), + .pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o), + .pipe_tx_data_o(pipe_tx6_data_o), + .pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o), + .pipe_tx_powerdown_o(pipe_tx6_powerdown_o), + + .pipe_clk(pipe_clk), + .rst_n(rst_n) + + ); + +pcie_7x_0_pcie_pipe_lane # ( + + .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) + + ) + pipe_lane_7_i ( + + .pipe_rx_char_is_k_o(pipe_rx7_char_is_k_o), + .pipe_rx_data_o(pipe_rx7_data_o), + .pipe_rx_valid_o(pipe_rx7_valid_o), + .pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o), + .pipe_rx_status_o(pipe_rx7_status_o), + .pipe_rx_phy_status_o(pipe_rx7_phy_status_o), + .pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o), + .pipe_rx_polarity_i(pipe_rx7_polarity_i), + .pipe_tx_compliance_i(pipe_tx7_compliance_i), + .pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i), + .pipe_tx_data_i(pipe_tx7_data_i), + .pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i), + .pipe_tx_powerdown_i(pipe_tx7_powerdown_i), + + .pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i), + .pipe_rx_data_i(pipe_rx7_data_i), + .pipe_rx_valid_i(pipe_rx7_valid_i), + .pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i), + .pipe_rx_status_i(pipe_rx7_status_i), + .pipe_rx_phy_status_i(pipe_rx7_phy_status_i), + .pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i), + .pipe_rx_polarity_o(pipe_rx7_polarity_o), + .pipe_tx_compliance_o(pipe_tx7_compliance_o), + .pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o), + .pipe_tx_data_o(pipe_tx7_data_o), + .pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o), + .pipe_tx_powerdown_o(pipe_tx7_powerdown_o), + + .pipe_clk(pipe_clk), + .rst_n(rst_n) + + ); + + end // if (LINK_CAP_MAX_LINK_WIDTH >= 8) + else + begin + assign pipe_rx4_char_is_k_o = 2'b00; + assign pipe_rx4_data_o = 16'h0000; + assign pipe_rx4_valid_o = 1'b0; + assign pipe_rx4_chanisaligned_o = 1'b0; + assign pipe_rx4_status_o = 3'b000; + assign pipe_rx4_phy_status_o = 1'b0; + assign pipe_rx4_elec_idle_o = 1'b1; + assign pipe_rx4_polarity_o = 1'b0; + assign pipe_tx4_compliance_o = 1'b0; + assign pipe_tx4_char_is_k_o = 2'b00; + assign pipe_tx4_data_o = 16'h0000; + assign pipe_tx4_elec_idle_o = 1'b1; + assign pipe_tx4_powerdown_o = 2'b00; + + assign pipe_rx5_char_is_k_o = 2'b00; + assign pipe_rx5_data_o = 16'h0000; + assign pipe_rx5_valid_o = 1'b0; + assign pipe_rx5_chanisaligned_o = 1'b0; + assign pipe_rx5_status_o = 3'b000; + assign pipe_rx5_phy_status_o = 1'b0; + assign pipe_rx5_elec_idle_o = 1'b1; + assign pipe_rx5_polarity_o = 1'b0; + assign pipe_tx5_compliance_o = 1'b0; + assign pipe_tx5_char_is_k_o = 2'b00; + assign pipe_tx5_data_o = 16'h0000; + assign pipe_tx5_elec_idle_o = 1'b1; + assign pipe_tx5_powerdown_o = 2'b00; + + assign pipe_rx6_char_is_k_o = 2'b00; + assign pipe_rx6_data_o = 16'h0000; + assign pipe_rx6_valid_o = 1'b0; + assign pipe_rx6_chanisaligned_o = 1'b0; + assign pipe_rx6_status_o = 3'b000; + assign pipe_rx6_phy_status_o = 1'b0; + assign pipe_rx6_elec_idle_o = 1'b1; + assign pipe_rx6_polarity_o = 1'b0; + assign pipe_tx6_compliance_o = 1'b0; + assign pipe_tx6_char_is_k_o = 2'b00; + assign pipe_tx6_data_o = 16'h0000; + assign pipe_tx6_elec_idle_o = 1'b1; + assign pipe_tx6_powerdown_o = 2'b00; + + assign pipe_rx7_char_is_k_o = 2'b00; + assign pipe_rx7_data_o = 16'h0000; + assign pipe_rx7_valid_o = 1'b0; + assign pipe_rx7_chanisaligned_o = 1'b0; + assign pipe_rx7_status_o = 3'b000; + assign pipe_rx7_phy_status_o = 1'b0; + assign pipe_rx7_elec_idle_o = 1'b1; + assign pipe_rx7_polarity_o = 1'b0; + assign pipe_tx7_compliance_o = 1'b0; + assign pipe_tx7_char_is_k_o = 2'b00; + assign pipe_tx7_data_o = 16'h0000; + assign pipe_tx7_elec_idle_o = 1'b1; + assign pipe_tx7_powerdown_o = 2'b00; + end // if !(LINK_CAP_MAX_LINK_WIDTH >= 8) + + endgenerate + +endmodule + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_top.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_top.v new file mode 100644 index 0000000..d8f264b --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_top.v @@ -0,0 +1,2080 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pcie_top.v +// Version : 3.3 +// Description: Solution wrapper for Virtex7 Hard Block for PCI Express +// +// +// +//-------------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pcie_top # ( + // PCIE_2_1 params + parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages + parameter [11:0] AER_BASE_PTR = 12'h140, + parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE", + parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE", + parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE", + parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE", + parameter [15:0] AER_CAP_ID = 16'h0001, + parameter AER_CAP_MULTIHEADER = "FALSE", + parameter [11:0] AER_CAP_NEXTPTR = 12'h178, + parameter AER_CAP_ON = "FALSE", + parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000, + parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE", + parameter [3:0] AER_CAP_VERSION = 4'h1, + parameter ALLOW_X8_GEN2 = "FALSE", + parameter [31:0] BAR0 = 32'hFFFFFF00, + parameter [31:0] BAR1 = 32'hFFFF0000, + parameter [31:0] BAR2 = 32'hFFFF000C, + parameter [31:0] BAR3 = 32'hFFFFFFFF, + parameter [31:0] BAR4 = 32'h00000000, + parameter [31:0] BAR5 = 32'h00000000, + parameter C_DATA_WIDTH = 64, + parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, + parameter KEEP_WIDTH = C_DATA_WIDTH / 8, + parameter [7:0] CAPABILITIES_PTR = 8'h40, + parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000, + parameter [23:0] CLASS_CODE = 24'h000000, + parameter CFG_ECRC_ERR_CPLSTAT = 0, + parameter CMD_INTX_IMPLEMENTED = "TRUE", + parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE", + parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0, + parameter [6:0] CRM_MODULE_RSTS = 7'h00, + parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE", + parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE", + parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE", + parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE", + parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE", + parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE", + parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE", + parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE", + parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0, + parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE", + parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0, + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE", + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE", + parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0, + parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0, + parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE", + parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE", + parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2, + parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0, + parameter integer DEV_CAP_RSVD_14_12 = 0, + parameter integer DEV_CAP_RSVD_17_16 = 0, + parameter integer DEV_CAP_RSVD_31_29 = 0, + parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE", + parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE", + parameter DISABLE_ASPM_L1_TIMER = "FALSE", + parameter DISABLE_BAR_FILTERING = "FALSE", + parameter DISABLE_ERR_MSG = "FALSE", + parameter DISABLE_ID_CHECK = "FALSE", + parameter DISABLE_LANE_REVERSAL = "FALSE", + parameter DISABLE_LOCKED_FILTER = "FALSE", + parameter DISABLE_PPM_FILTER = "FALSE", + parameter DISABLE_RX_POISONED_RESP = "FALSE", + parameter DISABLE_RX_TC_FILTER = "FALSE", + parameter DISABLE_SCRAMBLING = "FALSE", + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00, + parameter [11:0] DSN_BASE_PTR = 12'h100, + parameter [15:0] DSN_CAP_ID = 16'h0003, + parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C, + parameter DSN_CAP_ON = "TRUE", + parameter [3:0] DSN_CAP_VERSION = 4'h1, + parameter [10:0] ENABLE_MSG_ROUTE = 11'h000, + parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE", + parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE", + parameter ENTER_RVRY_EI_L0 = "TRUE", + parameter EXIT_LOOPBACK_ON_EI = "TRUE", + parameter [31:0] EXPANSION_ROM = 32'hFFFFF001, + parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F, + parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF, + parameter [7:0] HEADER_TYPE = 8'h00, + parameter [4:0] INFER_EI = 5'h00, + parameter [7:0] INTERRUPT_PIN = 8'h01, + parameter INTERRUPT_STAT_AUTO = "TRUE", + parameter IS_SWITCH = "FALSE", + parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF, + parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE", + parameter integer LINK_CAP_ASPM_SUPPORT = 1, + parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE", + parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE", + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7, + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7, + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7, + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7, + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7, + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7, + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7, + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7, + parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE", + parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, + parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, + parameter integer LINK_CAP_RSVD_23 = 0, + parameter integer LINK_CONTROL_RCB = 0, + parameter LINK_CTRL2_DEEMPHASIS = "FALSE", + parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE", + parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2, + parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE", + parameter [14:0] LL_ACK_TIMEOUT = 15'h0000, + parameter LL_ACK_TIMEOUT_EN = "FALSE", + parameter integer LL_ACK_TIMEOUT_FUNC = 0, + parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000, + parameter LL_REPLAY_TIMEOUT_EN = "FALSE", + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0, + parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01, + parameter MPS_FORCE = "FALSE", + parameter [7:0] MSIX_BASE_PTR = 8'h9C, + parameter [7:0] MSIX_CAP_ID = 8'h11, + parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00, + parameter MSIX_CAP_ON = "FALSE", + parameter integer MSIX_CAP_PBA_BIR = 0, + parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050, + parameter integer MSIX_CAP_TABLE_BIR = 0, + parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040, + parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000, + parameter [7:0] MSI_BASE_PTR = 8'h48, + parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE", + parameter [7:0] MSI_CAP_ID = 8'h05, + parameter integer MSI_CAP_MULTIMSGCAP = 0, + parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0, + parameter [7:0] MSI_CAP_NEXTPTR = 8'h60, + parameter MSI_CAP_ON = "FALSE", + parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE", + parameter integer N_FTS_COMCLK_GEN1 = 255, + parameter integer N_FTS_COMCLK_GEN2 = 255, + parameter integer N_FTS_GEN1 = 255, + parameter integer N_FTS_GEN2 = 255, + parameter [7:0] PCIE_BASE_PTR = 8'h60, + parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10, + parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2, + parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0, + parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C, + parameter PCIE_CAP_ON = "TRUE", + parameter integer PCIE_CAP_RSVD_15_14 = 0, + parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE", + parameter integer PCIE_REVISION = 2, + parameter integer PL_AUTO_CONFIG = 0, + parameter PL_FAST_TRAIN = "FALSE", + parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000, + parameter PM_ASPML0S_TIMEOUT_EN = "FALSE", + parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0, + parameter PM_ASPM_FASTEXIT = "FALSE", + parameter [7:0] PM_BASE_PTR = 8'h40, + parameter integer PM_CAP_AUXCURRENT = 0, + parameter PM_CAP_D1SUPPORT = "TRUE", + parameter PM_CAP_D2SUPPORT = "TRUE", + parameter PM_CAP_DSI = "FALSE", + parameter [7:0] PM_CAP_ID = 8'h01, + parameter [7:0] PM_CAP_NEXTPTR = 8'h48, + parameter PM_CAP_ON = "TRUE", + parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F, + parameter PM_CAP_PME_CLOCK = "FALSE", + parameter integer PM_CAP_RSVD_04 = 0, + parameter integer PM_CAP_VERSION = 3, + parameter PM_CSR_B2B3 = "FALSE", + parameter PM_CSR_BPCCEN = "FALSE", + parameter PM_CSR_NOSOFTRST = "TRUE", + parameter [7:0] PM_DATA0 = 8'h01, + parameter [7:0] PM_DATA1 = 8'h01, + parameter [7:0] PM_DATA2 = 8'h01, + parameter [7:0] PM_DATA3 = 8'h01, + parameter [7:0] PM_DATA4 = 8'h01, + parameter [7:0] PM_DATA5 = 8'h01, + parameter [7:0] PM_DATA6 = 8'h01, + parameter [7:0] PM_DATA7 = 8'h01, + parameter [1:0] PM_DATA_SCALE0 = 2'h1, + parameter [1:0] PM_DATA_SCALE1 = 2'h1, + parameter [1:0] PM_DATA_SCALE2 = 2'h1, + parameter [1:0] PM_DATA_SCALE3 = 2'h1, + parameter [1:0] PM_DATA_SCALE4 = 2'h1, + parameter [1:0] PM_DATA_SCALE5 = 2'h1, + parameter [1:0] PM_DATA_SCALE6 = 2'h1, + parameter [1:0] PM_DATA_SCALE7 = 2'h1, + parameter PM_MF = "FALSE", + parameter [11:0] RBAR_BASE_PTR = 12'h178, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00, + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00, + parameter [15:0] RBAR_CAP_ID = 16'h0015, + parameter [2:0] RBAR_CAP_INDEX0 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX1 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX2 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX3 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX4 = 3'h0, + parameter [2:0] RBAR_CAP_INDEX5 = 3'h0, + parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000, + parameter RBAR_CAP_ON = "FALSE", + parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000, + parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000, + parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000, + parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000, + parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000, + parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000, + parameter [3:0] RBAR_CAP_VERSION = 4'h1, + parameter [2:0] RBAR_NUM = 3'h1, + parameter integer RECRC_CHK = 0, + parameter RECRC_CHK_TRIM = "FALSE", + parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE", + parameter [1:0] RP_AUTO_SPD = 2'h1, + parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f, + parameter SELECT_DLL_IF = "FALSE", + parameter SIM_VERSION = "1.0", + parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE", + parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE", + parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE", + parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE", + parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE", + parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE", + parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE", + parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000, + parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE", + parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE", + parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0, + parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00, + parameter integer SPARE_BIT0 = 0, + parameter integer SPARE_BIT1 = 0, + parameter integer SPARE_BIT2 = 0, + parameter integer SPARE_BIT3 = 0, + parameter integer SPARE_BIT4 = 0, + parameter integer SPARE_BIT5 = 0, + parameter integer SPARE_BIT6 = 0, + parameter integer SPARE_BIT7 = 0, + parameter integer SPARE_BIT8 = 0, + parameter [7:0] SPARE_BYTE0 = 8'h00, + parameter [7:0] SPARE_BYTE1 = 8'h00, + parameter [7:0] SPARE_BYTE2 = 8'h00, + parameter [7:0] SPARE_BYTE3 = 8'h00, + parameter [31:0] SPARE_WORD0 = 32'h00000000, + parameter [31:0] SPARE_WORD1 = 32'h00000000, + parameter [31:0] SPARE_WORD2 = 32'h00000000, + parameter [31:0] SPARE_WORD3 = 32'h00000000, + parameter SSL_MESSAGE_AUTO = "FALSE", + parameter TECRC_EP_INV = "FALSE", + parameter TL_RBYPASS = "FALSE", + parameter integer TL_RX_RAM_RADDR_LATENCY = 0, + parameter integer TL_RX_RAM_RDATA_LATENCY = 2, + parameter integer TL_RX_RAM_WRITE_LATENCY = 0, + parameter TL_TFC_DISABLE = "FALSE", + parameter TL_TX_CHECKS_DISABLE = "FALSE", + parameter integer TL_TX_RAM_RADDR_LATENCY = 0, + parameter integer TL_TX_RAM_RDATA_LATENCY = 2, + parameter integer TL_TX_RAM_WRITE_LATENCY = 0, + parameter TRN_DW = "FALSE", + parameter TRN_NP_FC = "FALSE", + parameter UPCONFIG_CAPABLE = "TRUE", + parameter UPSTREAM_FACING = "TRUE", + parameter UR_ATOMIC = "TRUE", + parameter UR_CFG1 = "TRUE", + parameter UR_INV_REQ = "TRUE", + parameter UR_PRS_RESPONSE = "TRUE", + parameter USER_CLK2_DIV2 = "FALSE", + parameter integer USER_CLK_FREQ = 3, + parameter USE_RID_PINS = "FALSE", + parameter VC0_CPL_INFINITE = "TRUE", + parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF, + parameter integer VC0_TOTAL_CREDITS_CD = 127, + parameter integer VC0_TOTAL_CREDITS_CH = 31, + parameter integer VC0_TOTAL_CREDITS_NPD = 24, + parameter integer VC0_TOTAL_CREDITS_NPH = 12, + parameter integer VC0_TOTAL_CREDITS_PD = 288, + parameter integer VC0_TOTAL_CREDITS_PH = 32, + parameter integer VC0_TX_LASTPACKET = 31, + parameter [11:0] VC_BASE_PTR = 12'h10C, + parameter [15:0] VC_CAP_ID = 16'h0002, + parameter [11:0] VC_CAP_NEXTPTR = 12'h000, + parameter VC_CAP_ON = "FALSE", + parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE", + parameter [3:0] VC_CAP_VERSION = 4'h1, + parameter [11:0] VSEC_BASE_PTR = 12'h128, + parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234, + parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018, + parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1, + parameter [15:0] VSEC_CAP_ID = 16'h000B, + parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE", + parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140, + parameter VSEC_CAP_ON = "FALSE", + parameter [3:0] VSEC_CAP_VERSION = 4'h1, + parameter ENABLE_JTAG_DBG = "FALSE", + parameter REDUCE_OOB_FREQ = "FALSE" +) +( + + // wrapper input + // Common + output user_clk_out, + input user_reset, + input user_lnk_up, + + output trn_lnk_up, + output user_rst_n, + + // Tx + output [5:0] tx_buf_av, + output tx_err_drop, + output tx_cfg_req, + output s_axis_tx_tready, + input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, + input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, + input [3:0] s_axis_tx_tuser, + input s_axis_tx_tlast, + input s_axis_tx_tvalid, + input tx_cfg_gnt, + + // Rx + output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, + output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, + output m_axis_rx_tlast, + output m_axis_rx_tvalid, + input m_axis_rx_tready, + output [21:0] m_axis_rx_tuser, + input rx_np_ok, + input rx_np_req, + + // Flow Control + output [11:0] fc_cpld, + output [7:0] fc_cplh, + output [11:0] fc_npd, + output [7:0] fc_nph, + output [11:0] fc_pd, + output [7:0] fc_ph, + input [2:0] fc_sel, + + input wire [1:0] pl_directed_link_change, + input wire [1:0] pl_directed_link_width, + input wire pl_directed_link_speed, + input wire pl_directed_link_auton, + input wire pl_upstream_prefer_deemph, + input wire pl_downstream_deemph_source, + input wire pl_directed_ltssm_new_vld, + input wire [5:0] pl_directed_ltssm_new, + input wire pl_directed_ltssm_stall, + + input wire cm_rst_n, + input wire func_lvl_rst_n, + input wire pl_transmit_hot_rst, + input wire [31:0] cfg_mgmt_di, + input wire [3:0] cfg_mgmt_byte_en_n, + input wire [9:0] cfg_mgmt_dwaddr, + input wire cfg_mgmt_wr_rw1c_as_rw_n, + input wire cfg_mgmt_wr_readonly_n, + input wire cfg_mgmt_wr_en_n, + input wire cfg_mgmt_rd_en_n, + input wire cfg_err_malformed_n, + input wire cfg_err_cor_n, + input wire cfg_err_ur_n, + input wire cfg_err_ecrc_n, + input wire cfg_err_cpl_timeout_n, + input wire cfg_err_cpl_abort_n, + input wire cfg_err_cpl_unexpect_n, + input wire cfg_err_poisoned_n, + input wire cfg_err_acs_n, + input wire cfg_err_atomic_egress_blocked_n, + input wire cfg_err_mc_blocked_n, + input wire cfg_err_internal_uncor_n, + input wire cfg_err_internal_cor_n, + input wire cfg_err_posted_n, + input wire cfg_err_locked_n, + input wire cfg_err_norecovery_n, + input wire [127:0] cfg_err_aer_headerlog, + input wire [47:0] cfg_err_tlp_cpl_header, + input wire cfg_interrupt_n, + input wire [7:0] cfg_interrupt_di, + input wire cfg_interrupt_assert_n, + input wire cfg_interrupt_stat_n, + input wire [7:0] cfg_ds_bus_number, + input wire [4:0] cfg_ds_device_number, + input wire [2:0] cfg_ds_function_number, + input wire [7:0] cfg_port_number, + input wire cfg_pm_halt_aspm_l0s_n, + input wire cfg_pm_halt_aspm_l1_n, + input wire cfg_pm_force_state_en_n, + input wire [1:0] cfg_pm_force_state, + input wire cfg_pm_wake_n, + input wire cfg_turnoff_ok, + input wire cfg_pm_send_pme_to_n, + input wire [4:0] cfg_pciecap_interrupt_msgnum, + input wire cfg_trn_pending, + input wire [2:0] cfg_force_mps, + input wire cfg_force_common_clock_off, + input wire cfg_force_extended_sync_on, + input wire [63:0] cfg_dsn, + input wire [4:0] cfg_aer_interrupt_msgnum, + input wire [15:0] cfg_dev_id, + input wire [15:0] cfg_vend_id, + input wire [7:0] cfg_rev_id, + input wire [15:0] cfg_subsys_id, + input wire [15:0] cfg_subsys_vend_id, + input wire drp_clk, + input wire drp_en, + input wire drp_we, + input wire [8:0] drp_addr, + input wire [15:0] drp_di, + input wire [1:0] dbg_mode, + input wire dbg_sub_mode, + input wire [2:0] pl_dbg_mode , + + output wire pl_sel_lnk_rate, + output wire [1:0] pl_sel_lnk_width, + output wire [5:0] pl_ltssm_state, + output wire [1:0] pl_lane_reversal_mode, + output wire pl_phy_lnk_up, + output wire [2:0] pl_tx_pm_state, + output wire [1:0] pl_rx_pm_state, + output wire pl_link_upcfg_cap, + output wire pl_link_gen2_cap, + output wire pl_link_partner_gen2_supported, + output wire [2:0] pl_initial_link_width, + output wire pl_directed_change_done, + output wire pl_received_hot_rst, + output wire lnk_clk_en, + output wire [31:0] cfg_mgmt_do, + output wire cfg_mgmt_rd_wr_done, + output wire cfg_err_aer_headerlog_set, + output wire cfg_err_cpl_rdy, + output wire cfg_interrupt_rdy, + output wire [2:0] cfg_interrupt_mmenable, + output wire cfg_interrupt_msienable, + output wire [7:0] cfg_interrupt_do, + output wire cfg_interrupt_msixenable, + output wire cfg_interrupt_msixfm, + output wire [7:0] cfg_bus_number, + output wire [4:0] cfg_device_number, + output wire [2:0] cfg_function_number, + output wire [15:0] cfg_status, + output wire [15:0] cfg_command, + output wire [15:0] cfg_dstatus, + output wire [15:0] cfg_dcommand, + output wire [15:0] cfg_lstatus, + output wire [15:0] cfg_lcommand, + output wire [15:0] cfg_dcommand2, + output wire cfg_received_func_lvl_rst, + output wire cfg_msg_received, + output wire [15:0] cfg_msg_data, + output wire cfg_msg_received_err_cor, + output wire cfg_msg_received_err_non_fatal, + output wire cfg_msg_received_err_fatal, + output wire cfg_msg_received_assert_int_a, + output wire cfg_msg_received_deassert_int_a, + output wire cfg_msg_received_assert_int_b, + output wire cfg_msg_received_deassert_int_b, + output wire cfg_msg_received_assert_int_c, + output wire cfg_msg_received_deassert_int_c, + output wire cfg_msg_received_assert_int_d, + output wire cfg_msg_received_deassert_int_d, + output wire cfg_msg_received_pm_pme, + output wire cfg_msg_received_pme_to_ack, + output wire cfg_msg_received_pme_to, + output wire cfg_msg_received_setslotpowerlimit, + output wire cfg_msg_received_unlock, + output wire cfg_msg_received_pm_as_nak, + output wire cfg_to_turnoff, + output wire [2:0] cfg_pcie_link_state, + output wire cfg_pm_rcv_as_req_l1_n, + output wire cfg_pm_rcv_enter_l1_n, + output wire cfg_pm_rcv_enter_l23_n, + output wire cfg_pm_rcv_req_ack_n, + output wire [1:0] cfg_pmcsr_powerstate, + output wire cfg_pmcsr_pme_en, + output wire cfg_pmcsr_pme_status, + output wire cfg_transaction, + output wire cfg_transaction_type, + output wire [6:0] cfg_transaction_addr, + output wire cfg_command_io_enable, + output wire cfg_command_mem_enable, + output wire cfg_command_bus_master_enable, + output wire cfg_command_interrupt_disable, + output wire cfg_command_serr_en, + output wire cfg_bridge_serr_en, + output wire cfg_dev_status_corr_err_detected, + output wire cfg_dev_status_non_fatal_err_detected, + output wire cfg_dev_status_fatal_err_detected, + output wire cfg_dev_status_ur_detected, + output wire cfg_dev_control_corr_err_reporting_en, + output wire cfg_dev_control_non_fatal_reporting_en, + output wire cfg_dev_control_fatal_err_reporting_en, + output wire cfg_dev_control_ur_err_reporting_en, + output wire cfg_dev_control_enable_ro, + output wire [2:0] cfg_dev_control_max_payload, + output wire cfg_dev_control_ext_tag_en, + output wire cfg_dev_control_phantom_en, + output wire cfg_dev_control_aux_power_en, + output wire cfg_dev_control_no_snoop_en, + output wire [2:0] cfg_dev_control_max_read_req, + output wire [1:0] cfg_link_status_current_speed, + output wire [3:0] cfg_link_status_negotiated_width, + output wire cfg_link_status_link_training, + output wire cfg_link_status_dll_active, + output wire cfg_link_status_bandwidth_status, + output wire cfg_link_status_auto_bandwidth_status, + output wire [1:0] cfg_link_control_aspm_control, + output wire cfg_link_control_rcb, + output wire cfg_link_control_link_disable, + output wire cfg_link_control_retrain_link, + output wire cfg_link_control_common_clock, + output wire cfg_link_control_extended_sync, + output wire cfg_link_control_clock_pm_en, + output wire cfg_link_control_hw_auto_width_dis, + output wire cfg_link_control_bandwidth_int_en, + output wire cfg_link_control_auto_bandwidth_int_en, + output wire [3:0] cfg_dev_control2_cpl_timeout_val, + output wire cfg_dev_control2_cpl_timeout_dis, + output wire cfg_dev_control2_ari_forward_en, + output wire cfg_dev_control2_atomic_requester_en, + output wire cfg_dev_control2_atomic_egress_block, + output wire cfg_dev_control2_ido_req_en, + output wire cfg_dev_control2_ido_cpl_en, + output wire cfg_dev_control2_ltr_en, + output wire cfg_dev_control2_tlp_prefix_block, + output wire cfg_slot_control_electromech_il_ctl_pulse, + output wire cfg_root_control_syserr_corr_err_en, + output wire cfg_root_control_syserr_non_fatal_err_en, + output wire cfg_root_control_syserr_fatal_err_en, + output wire cfg_root_control_pme_int_en, + output wire cfg_aer_ecrc_check_en, + output wire cfg_aer_ecrc_gen_en, + output wire cfg_aer_rooterr_corr_err_reporting_en, + output wire cfg_aer_rooterr_non_fatal_err_reporting_en, + output wire cfg_aer_rooterr_fatal_err_reporting_en, + output wire cfg_aer_rooterr_corr_err_received, + output wire cfg_aer_rooterr_non_fatal_err_received, + output wire cfg_aer_rooterr_fatal_err_received, + output wire [6:0] cfg_vc_tcvc_map, + output wire drp_rdy, + output wire [15:0] drp_do, + output wire [63:0] dbg_vec_a, + output wire [63:0] dbg_vec_b, + output wire [11:0] dbg_vec_c, + output wire dbg_sclr_a, + output wire dbg_sclr_b, + output wire dbg_sclr_c, + output wire dbg_sclr_d, + output wire dbg_sclr_e, + output wire dbg_sclr_f, + output wire dbg_sclr_g, + output wire dbg_sclr_h, + output wire dbg_sclr_i, + output wire dbg_sclr_j, + output wire dbg_sclr_k, + output wire [63:0] trn_rdllp_data, + output wire [1:0] trn_rdllp_src_rdy, + output wire [11:0] pl_dbg_vec, + + input phy_rdy_n, + input pipe_clk, + input user_clk, + input user_clk2, + output wire pipe_rx0_polarity_gt, + output wire pipe_rx1_polarity_gt, + output wire pipe_rx2_polarity_gt, + output wire pipe_rx3_polarity_gt, + output wire pipe_rx4_polarity_gt, + output wire pipe_rx5_polarity_gt, + output wire pipe_rx6_polarity_gt, + output wire pipe_rx7_polarity_gt, + output wire pipe_tx_deemph_gt, + output wire [2:0] pipe_tx_margin_gt, + output wire pipe_tx_rate_gt, + output wire pipe_tx_rcvr_det_gt, + output wire [1:0] pipe_tx0_char_is_k_gt, + output wire pipe_tx0_compliance_gt, + output wire [15:0] pipe_tx0_data_gt, + output wire pipe_tx0_elec_idle_gt, + output wire [1:0] pipe_tx0_powerdown_gt, + output wire [1:0] pipe_tx1_char_is_k_gt, + output wire pipe_tx1_compliance_gt, + output wire [15:0] pipe_tx1_data_gt, + output wire pipe_tx1_elec_idle_gt, + output wire [1:0] pipe_tx1_powerdown_gt, + output wire [1:0] pipe_tx2_char_is_k_gt, + output wire pipe_tx2_compliance_gt, + output wire [15:0] pipe_tx2_data_gt, + output wire pipe_tx2_elec_idle_gt, + output wire [1:0] pipe_tx2_powerdown_gt, + output wire [1:0] pipe_tx3_char_is_k_gt, + output wire pipe_tx3_compliance_gt, + output wire [15:0] pipe_tx3_data_gt, + output wire pipe_tx3_elec_idle_gt, + output wire [1:0] pipe_tx3_powerdown_gt, + output wire [1:0] pipe_tx4_char_is_k_gt, + output wire pipe_tx4_compliance_gt, + output wire [15:0] pipe_tx4_data_gt, + output wire pipe_tx4_elec_idle_gt, + output wire [1:0] pipe_tx4_powerdown_gt, + output wire [1:0] pipe_tx5_char_is_k_gt, + output wire pipe_tx5_compliance_gt, + output wire [15:0] pipe_tx5_data_gt, + output wire pipe_tx5_elec_idle_gt, + output wire [1:0] pipe_tx5_powerdown_gt, + output wire [1:0] pipe_tx6_char_is_k_gt, + output wire pipe_tx6_compliance_gt, + output wire [15:0] pipe_tx6_data_gt, + output wire pipe_tx6_elec_idle_gt, + output wire [1:0] pipe_tx6_powerdown_gt, + output wire [1:0] pipe_tx7_char_is_k_gt, + output wire pipe_tx7_compliance_gt, + output wire [15:0] pipe_tx7_data_gt, + output wire pipe_tx7_elec_idle_gt, + output wire [1:0] pipe_tx7_powerdown_gt, + + input wire pipe_rx0_chanisaligned_gt, + input wire [1:0] pipe_rx0_char_is_k_gt, + input wire [15:0] pipe_rx0_data_gt, + input wire pipe_rx0_elec_idle_gt, + input wire pipe_rx0_phy_status_gt, + input wire [2:0] pipe_rx0_status_gt, + input wire pipe_rx0_valid_gt, + input wire pipe_rx1_chanisaligned_gt, + input wire [1:0] pipe_rx1_char_is_k_gt, + input wire [15:0] pipe_rx1_data_gt, + input wire pipe_rx1_elec_idle_gt, + input wire pipe_rx1_phy_status_gt, + input wire [2:0] pipe_rx1_status_gt, + input wire pipe_rx1_valid_gt, + input wire pipe_rx2_chanisaligned_gt, + input wire [1:0] pipe_rx2_char_is_k_gt, + input wire [15:0] pipe_rx2_data_gt, + input wire pipe_rx2_elec_idle_gt, + input wire pipe_rx2_phy_status_gt, + input wire [2:0] pipe_rx2_status_gt, + input wire pipe_rx2_valid_gt, + input wire pipe_rx3_chanisaligned_gt, + input wire [1:0] pipe_rx3_char_is_k_gt, + input wire [15:0] pipe_rx3_data_gt, + input wire pipe_rx3_elec_idle_gt, + input wire pipe_rx3_phy_status_gt, + input wire [2:0] pipe_rx3_status_gt, + input wire pipe_rx3_valid_gt, + input wire pipe_rx4_chanisaligned_gt, + input wire [1:0] pipe_rx4_char_is_k_gt, + input wire [15:0] pipe_rx4_data_gt, + input wire pipe_rx4_elec_idle_gt, + input wire pipe_rx4_phy_status_gt, + input wire [2:0] pipe_rx4_status_gt, + input wire pipe_rx4_valid_gt, + input wire pipe_rx5_chanisaligned_gt, + input wire [1:0] pipe_rx5_char_is_k_gt, + input wire [15:0] pipe_rx5_data_gt, + input wire pipe_rx5_elec_idle_gt, + input wire pipe_rx5_phy_status_gt, + input wire [2:0] pipe_rx5_status_gt, + input wire pipe_rx5_valid_gt, + input wire pipe_rx6_chanisaligned_gt, + input wire [1:0] pipe_rx6_char_is_k_gt, + input wire [15:0] pipe_rx6_data_gt, + input wire pipe_rx6_elec_idle_gt, + input wire pipe_rx6_phy_status_gt, + input wire [2:0] pipe_rx6_status_gt, + input wire pipe_rx6_valid_gt, + input wire pipe_rx7_chanisaligned_gt, + input wire [1:0] pipe_rx7_char_is_k_gt, + input wire [15:0] pipe_rx7_data_gt, + input wire pipe_rx7_elec_idle_gt, + input wire pipe_rx7_phy_status_gt, + input wire [2:0] pipe_rx7_status_gt, + input wire pipe_rx7_valid_gt +); + + //wire declaration + + // TRN Interface + wire [C_DATA_WIDTH-1:0] trn_td; + wire [REM_WIDTH-1:0] trn_trem; + wire trn_tsof; + wire trn_teof; + wire trn_tsrc_rdy; + wire trn_tdst_rdy; + wire trn_tsrc_dsc; + wire trn_terrfwd; + wire trn_tecrc_gen; + wire trn_tstr; + wire trn_tcfg_gnt; + + + wire [127:0] trn_rd; + wire [1:0] trn_rrem; + wire trn_rdst_rdy; + wire trn_rsof; + wire trn_reof; + wire trn_rsrc_rdy; + wire trn_rsrc_dsc; + wire trn_rerrfwd; + wire trn_recrc_err; + wire [7:0] trn_rbar_hit; + + wire sys_reset_n_d; + wire [1:0] pipe_rx0_char_is_k; + wire [1:0] pipe_rx1_char_is_k; + wire [1:0] pipe_rx2_char_is_k; + wire [1:0] pipe_rx3_char_is_k; + wire [1:0] pipe_rx4_char_is_k; + wire [1:0] pipe_rx5_char_is_k; + wire [1:0] pipe_rx6_char_is_k; + wire [1:0] pipe_rx7_char_is_k; + wire pipe_rx0_valid; + wire pipe_rx1_valid; + wire pipe_rx2_valid; + wire pipe_rx3_valid; + wire pipe_rx4_valid; + wire pipe_rx5_valid; + wire pipe_rx6_valid; + wire pipe_rx7_valid; + wire [15:0] pipe_rx0_data; + wire [15:0] pipe_rx1_data; + wire [15:0] pipe_rx2_data; + wire [15:0] pipe_rx3_data; + wire [15:0] pipe_rx4_data; + wire [15:0] pipe_rx5_data; + wire [15:0] pipe_rx6_data; + wire [15:0] pipe_rx7_data; + wire pipe_rx0_chanisaligned; + wire pipe_rx1_chanisaligned; + wire pipe_rx2_chanisaligned; + wire pipe_rx3_chanisaligned; + wire pipe_rx4_chanisaligned; + wire pipe_rx5_chanisaligned; + wire pipe_rx6_chanisaligned; + wire pipe_rx7_chanisaligned; + wire [2:0] pipe_rx0_status; + wire [2:0] pipe_rx1_status; + wire [2:0] pipe_rx2_status; + wire [2:0] pipe_rx3_status; + wire [2:0] pipe_rx4_status; + wire [2:0] pipe_rx5_status; + wire [2:0] pipe_rx6_status; + wire [2:0] pipe_rx7_status; + wire pipe_rx0_phy_status; + wire pipe_rx1_phy_status; + wire pipe_rx2_phy_status; + wire pipe_rx3_phy_status; + wire pipe_rx4_phy_status; + wire pipe_rx5_phy_status; + wire pipe_rx6_phy_status; + wire pipe_rx7_phy_status; + + wire pipe_rx0_elec_idle; + wire pipe_rx1_elec_idle; + wire pipe_rx2_elec_idle; + wire pipe_rx3_elec_idle; + wire pipe_rx4_elec_idle; + wire pipe_rx5_elec_idle; + wire pipe_rx6_elec_idle; + wire pipe_rx7_elec_idle; + + + wire pipe_tx_reset; + wire pipe_tx_rcvr_det; + wire pipe_tx_rate; + wire pipe_tx_deemph; + wire [2:0] pipe_tx_margin; + wire pipe_rx0_polarity; + wire pipe_rx1_polarity; + wire pipe_rx2_polarity; + wire pipe_rx3_polarity; + wire pipe_rx4_polarity; + wire pipe_rx5_polarity; + wire pipe_rx6_polarity; + wire pipe_rx7_polarity; + wire pipe_tx0_compliance; + wire pipe_tx1_compliance; + wire pipe_tx2_compliance; + wire pipe_tx3_compliance; + wire pipe_tx4_compliance; + wire pipe_tx5_compliance; + wire pipe_tx6_compliance; + wire pipe_tx7_compliance; + wire [1:0] pipe_tx0_char_is_k; + wire [1:0] pipe_tx1_char_is_k; + wire [1:0] pipe_tx2_char_is_k; + wire [1:0] pipe_tx3_char_is_k; + wire [1:0] pipe_tx4_char_is_k; + wire [1:0] pipe_tx5_char_is_k; + wire [1:0] pipe_tx6_char_is_k; + wire [1:0] pipe_tx7_char_is_k; + wire [15:0] pipe_tx0_data; + wire [15:0] pipe_tx1_data; + wire [15:0] pipe_tx2_data; + wire [15:0] pipe_tx3_data; + wire [15:0] pipe_tx4_data; + wire [15:0] pipe_tx5_data; + wire [15:0] pipe_tx6_data; + wire [15:0] pipe_tx7_data; + wire pipe_tx0_elec_idle; + wire pipe_tx1_elec_idle; + wire pipe_tx2_elec_idle; + wire pipe_tx3_elec_idle; + wire pipe_tx4_elec_idle; + wire pipe_tx5_elec_idle; + wire pipe_tx6_elec_idle; + wire pipe_tx7_elec_idle; + wire [1:0] pipe_tx0_powerdown; + wire [1:0] pipe_tx1_powerdown; + wire [1:0] pipe_tx2_powerdown; + wire [1:0] pipe_tx3_powerdown; + wire [1:0] pipe_tx4_powerdown; + wire [1:0] pipe_tx5_powerdown; + wire [1:0] pipe_tx6_powerdown; + wire [1:0] pipe_tx7_powerdown; + + wire cfg_received_func_lvl_rst_n; + wire cfg_err_cpl_rdy_n; + wire cfg_interrupt_rdy_n; + reg [7:0] cfg_bus_number_d; + reg [4:0] cfg_device_number_d; + reg [2:0] cfg_function_number_d; + wire cfg_turnoff_ok_w; + + wire cfg_mgmt_rd_wr_done_n; + wire pl_phy_lnk_up_n; + wire cfg_err_aer_headerlog_set_n; + + assign cfg_received_func_lvl_rst = ~cfg_received_func_lvl_rst_n; + + assign cfg_err_cpl_rdy = ~cfg_err_cpl_rdy_n; + + assign cfg_interrupt_rdy = ~cfg_interrupt_rdy_n; + + assign cfg_mgmt_rd_wr_done = ~cfg_mgmt_rd_wr_done_n; + + assign pl_phy_lnk_up = ~pl_phy_lnk_up_n; + + assign cfg_err_aer_headerlog_set = ~cfg_err_aer_headerlog_set_n; + + assign cfg_to_turnoff = cfg_msg_received_pme_to; + + assign cfg_status = {16'b0}; + + assign cfg_command = {5'b0, + cfg_command_interrupt_disable, + 1'b0, + cfg_command_serr_en, + 5'b0, + cfg_command_bus_master_enable, + cfg_command_mem_enable, + cfg_command_io_enable}; + + assign cfg_dstatus = {10'h0, + cfg_trn_pending, + 1'b0, + cfg_dev_status_ur_detected, + cfg_dev_status_fatal_err_detected, + cfg_dev_status_non_fatal_err_detected, + cfg_dev_status_corr_err_detected}; + + assign cfg_dcommand = {1'b0, + cfg_dev_control_max_read_req, + cfg_dev_control_no_snoop_en, + cfg_dev_control_aux_power_en, + cfg_dev_control_phantom_en, + cfg_dev_control_ext_tag_en, + cfg_dev_control_max_payload, + cfg_dev_control_enable_ro, + cfg_dev_control_ur_err_reporting_en, + cfg_dev_control_fatal_err_reporting_en, + cfg_dev_control_non_fatal_reporting_en, + cfg_dev_control_corr_err_reporting_en }; + + assign cfg_lstatus = {cfg_link_status_auto_bandwidth_status, + cfg_link_status_bandwidth_status, + cfg_link_status_dll_active, + (LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE") ? 1'b1 : 1'b0, + cfg_link_status_link_training, + 1'b0, + {2'b00, cfg_link_status_negotiated_width}, + {2'b00, cfg_link_status_current_speed} }; + + assign cfg_lcommand = {4'b0, + cfg_link_control_auto_bandwidth_int_en, + cfg_link_control_bandwidth_int_en, + cfg_link_control_hw_auto_width_dis, + cfg_link_control_clock_pm_en, + cfg_link_control_extended_sync, + cfg_link_control_common_clock, + cfg_link_control_retrain_link, + cfg_link_control_link_disable, + cfg_link_control_rcb, + 1'b0, + cfg_link_control_aspm_control}; + + assign cfg_bus_number = cfg_bus_number_d; + + assign cfg_device_number = cfg_device_number_d; + + assign cfg_function_number = cfg_function_number_d; + + assign cfg_dcommand2 = {4'b0, + cfg_dev_control2_tlp_prefix_block, + cfg_dev_control2_ltr_en, + cfg_dev_control2_ido_cpl_en, + cfg_dev_control2_ido_req_en, + cfg_dev_control2_atomic_egress_block, + cfg_dev_control2_atomic_requester_en, + cfg_dev_control2_ari_forward_en, + cfg_dev_control2_cpl_timeout_dis, + cfg_dev_control2_cpl_timeout_val}; + + // Capture Bus/Device/Function number + + always @(posedge user_clk_out) begin + if (~user_lnk_up) + begin + cfg_bus_number_d <= 8'b0; + end // if (~user_lnk_up) + else if (~cfg_msg_received) + begin + cfg_bus_number_d <= cfg_msg_data[15:8]; + end // if (~cfg_msg_received) + end + + always @(posedge user_clk_out) begin + if (~user_lnk_up) + begin + cfg_device_number_d <= 5'b0; + end // if (~user_lnk_up) + else if (~cfg_msg_received) + begin + cfg_device_number_d <= cfg_msg_data[7:3]; + end // if (~cfg_msg_received) + end + + always @(posedge user_clk_out) begin + if (~user_lnk_up) + begin + cfg_function_number_d <= 3'b0; + end // if (~user_lnk_up) + else if (~cfg_msg_received) + begin + cfg_function_number_d <= cfg_msg_data[2:0]; + end // if (~cfg_msg_received) + end + +pcie_7x_0_axi_basic_top #( + .C_DATA_WIDTH (C_DATA_WIDTH), // RX/TX interface data width + .C_FAMILY ("X7"), // Targeted FPGA family + .C_ROOT_PORT ("FALSE"), // PCIe block is in root port mode + .C_PM_PRIORITY ("FALSE") // Disable TX packet boundary thrtl + + ) axi_basic_top ( + //---------------------------------------------// + // User Design I/O // + //---------------------------------------------// + + // AXI TX + //----------- + .s_axis_tx_tdata (s_axis_tx_tdata), // input + .s_axis_tx_tvalid (s_axis_tx_tvalid), // input + .s_axis_tx_tready (s_axis_tx_tready), // output + .s_axis_tx_tkeep (s_axis_tx_tkeep), // input + .s_axis_tx_tlast (s_axis_tx_tlast), // input + .s_axis_tx_tuser (s_axis_tx_tuser), // input + + // AXI RX + //----------- + .m_axis_rx_tdata (m_axis_rx_tdata), // output + .m_axis_rx_tvalid (m_axis_rx_tvalid), // output + .m_axis_rx_tready (m_axis_rx_tready), // input + .m_axis_rx_tkeep (m_axis_rx_tkeep), // output + .m_axis_rx_tlast (m_axis_rx_tlast), // output + .m_axis_rx_tuser (m_axis_rx_tuser), // output + + // User Misc. + //----------- + .user_turnoff_ok (cfg_turnoff_ok), // input + .user_tcfg_gnt (tx_cfg_gnt), // input + + //---------------------------------------------// + // PCIe Block I/O // + //---------------------------------------------// + + // TRN TX + //----------- + .trn_td (trn_td), // output + .trn_tsof (trn_tsof), // output + .trn_teof (trn_teof), // output + .trn_tsrc_rdy (trn_tsrc_rdy), // output + .trn_tdst_rdy (trn_tdst_rdy), // input + .trn_tsrc_dsc (trn_tsrc_dsc), // output + .trn_trem (trn_trem), // output + .trn_terrfwd (trn_terrfwd), // output + .trn_tstr (trn_tstr), // output + .trn_tbuf_av (tx_buf_av), // input + .trn_tecrc_gen (trn_tecrc_gen), // output + + // TRN RX + //----------- + .trn_rd (trn_rd), // input + .trn_rsof (trn_rsof), // input + .trn_reof (trn_reof), // input + .trn_rsrc_rdy (trn_rsrc_rdy), // input + .trn_rdst_rdy (trn_rdst_rdy), // output + .trn_rsrc_dsc (trn_rsrc_dsc), // input + .trn_rrem (trn_rrem), // input + .trn_rerrfwd (trn_rerrfwd), // input + .trn_rbar_hit (trn_rbar_hit[6:0]), // input + .trn_recrc_err (trn_recrc_err), // input + + // TRN Misc. + //----------- + .trn_tcfg_req ( tx_cfg_req ), // input + .trn_tcfg_gnt ( trn_tcfg_gnt), // output + .trn_lnk_up ( user_lnk_up), // input + + // Fuji3/Virtex6 PM + //----------- + .cfg_pcie_link_state (cfg_pcie_link_state), // input + + // Virtex6 PM + //----------- + .cfg_pm_send_pme_to (1'b0), // input NOT USED FOR EP + .cfg_pmcsr_powerstate (cfg_pmcsr_powerstate), // input + .trn_rdllp_data (32'b0), // input - Not used in 7-series + .trn_rdllp_src_rdy (1'b0), // input -- Not used in 7-series + + // Power Mgmt for S6/V6 + //----------- + .cfg_to_turnoff (cfg_to_turnoff), // input + .cfg_turnoff_ok (cfg_turnoff_ok_w), // output + + // System + //----------- + .user_clk (user_clk_out), // input + .user_rst (user_reset), // input + .np_counter () // output + + ); + + + //------------------------------------------------------- + // PCI Express Pipe Wrapper + //------------------------------------------------------- +pcie_7x_0_pcie_7x # ( + .AER_BASE_PTR ( AER_BASE_PTR ), + .AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ), + .AER_CAP_ECRC_GEN_CAPABLE( AER_CAP_ECRC_GEN_CAPABLE ), + .AER_CAP_ID ( AER_CAP_ID ), + .AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ), + .AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ), + .AER_CAP_ON ( AER_CAP_ON ), + .AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ), + .AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ), + .AER_CAP_VERSION ( AER_CAP_VERSION ), + .ALLOW_X8_GEN2 (ALLOW_X8_GEN2), + .BAR0 ( BAR0 ), + .BAR1 ( BAR1 ), + .BAR2 ( BAR2 ), + .BAR3 ( BAR3 ), + .BAR4 ( BAR4 ), + .BAR5 ( BAR5 ), + .C_DATA_WIDTH ( C_DATA_WIDTH ), + .CAPABILITIES_PTR( CAPABILITIES_PTR ), + .CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ), + .CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ), + .CLASS_CODE ( CLASS_CODE ), + .CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ), + .CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ), + .CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ), + .CRM_MODULE_RSTS (CRM_MODULE_RSTS), + .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ), + .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ), + .DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ), + .DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ), + .DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ), + .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ), + .DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ), + .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ), + .DEV_CAP_ROLE_BASED_ERROR( DEV_CAP_ROLE_BASED_ERROR ), + .DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ), + .DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ), + .DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ), + .DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ), + .DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ), + .DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ), + .DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ), + .DISABLE_ID_CHECK( DISABLE_ID_CHECK ), + .DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ), + .DISABLE_RX_POISONED_RESP (DISABLE_RX_POISONED_RESP), + .DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ), + .DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ), + .DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ), + .DSN_BASE_PTR ( DSN_BASE_PTR ), + .DSN_CAP_ID ( DSN_CAP_ID ), + .DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ), + .DSN_CAP_ON ( DSN_CAP_ON ), + .DSN_CAP_VERSION ( DSN_CAP_VERSION ), + .DEV_CAP2_ARI_FORWARDING_SUPPORTED(DEV_CAP2_ARI_FORWARDING_SUPPORTED), + .DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED), + .DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED), + .DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED (DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED), + .DEV_CAP2_CAS128_COMPLETER_SUPPORTED (DEV_CAP2_CAS128_COMPLETER_SUPPORTED), + .DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED (DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED), + .DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED (DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED), + .DEV_CAP2_LTR_MECHANISM_SUPPORTED (DEV_CAP2_LTR_MECHANISM_SUPPORTED), + .DEV_CAP2_MAX_ENDEND_TLP_PREFIXES (DEV_CAP2_MAX_ENDEND_TLP_PREFIXES), + .DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING (DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING), + .DEV_CAP2_TPH_COMPLETER_SUPPORTED (DEV_CAP2_TPH_COMPLETER_SUPPORTED), + .DISABLE_ERR_MSG (DISABLE_ERR_MSG), + .DISABLE_LOCKED_FILTER (DISABLE_LOCKED_FILTER), + .DISABLE_PPM_FILTER (DISABLE_PPM_FILTER), + .ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED (ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED), + .ENABLE_MSG_ROUTE( ENABLE_MSG_ROUTE ), + .ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ), + .ENTER_RVRY_EI_L0( ENTER_RVRY_EI_L0 ), + .EXIT_LOOPBACK_ON_EI (EXIT_LOOPBACK_ON_EI), + .EXPANSION_ROM ( EXPANSION_ROM ), + .EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ), + .EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ), + .HEADER_TYPE ( HEADER_TYPE ), + .INFER_EI( INFER_EI ), + .INTERRUPT_PIN ( INTERRUPT_PIN ), + .INTERRUPT_STAT_AUTO (INTERRUPT_STAT_AUTO), + .IS_SWITCH ( IS_SWITCH ), + .LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ), + .LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ), + .LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ), + .LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ), + .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ), + .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ), + .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ), + .LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ), + .LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ), + .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ), + .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ), + .LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ), + .LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ), + .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP (LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP), + .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ), + .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), + .LINK_CAP_RSVD_23( LINK_CAP_RSVD_23 ), + .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ), + .LINK_CONTROL_RCB( LINK_CONTROL_RCB ), + .LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ), + .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ), + .LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ), + .LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ), + .LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ), + .LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ), + .LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ), + .LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ), + .LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ), + .LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ), + .LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ), + .MPS_FORCE (MPS_FORCE), + .MSI_BASE_PTR ( MSI_BASE_PTR ), + .MSI_CAP_ID ( MSI_CAP_ID ), + .MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ), + .MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ), + .MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ), + .MSI_CAP_ON ( MSI_CAP_ON ), + .MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ), + .MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ), + .MSIX_BASE_PTR ( MSIX_BASE_PTR ), + .MSIX_CAP_ID ( MSIX_CAP_ID ), + .MSIX_CAP_NEXTPTR( MSIX_CAP_NEXTPTR ), + .MSIX_CAP_ON ( MSIX_CAP_ON ), + .MSIX_CAP_PBA_BIR( MSIX_CAP_PBA_BIR ), + .MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ), + .MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ), + .MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ), + .MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ), + .N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ), + .N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ), + .N_FTS_GEN1 ( N_FTS_GEN1 ), + .N_FTS_GEN2 ( N_FTS_GEN2 ), + .PCIE_BASE_PTR ( PCIE_BASE_PTR ), + .PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ), + .PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ), + .PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ), + .PCIE_CAP_NEXTPTR( PCIE_CAP_NEXTPTR ), + .PCIE_CAP_ON ( PCIE_CAP_ON ), + .PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ), + .PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ), + .PCIE_REVISION ( PCIE_REVISION ), + .PL_AUTO_CONFIG ( PL_AUTO_CONFIG ), + .PL_FAST_TRAIN ( PL_FAST_TRAIN ), + .PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ), + .PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ), + .PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ), + .PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ), + .PM_BASE_PTR ( PM_BASE_PTR ), + .PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ), + .PM_CAP_D1SUPPORT( PM_CAP_D1SUPPORT ), + .PM_CAP_D2SUPPORT( PM_CAP_D2SUPPORT ), + .PM_CAP_DSI ( PM_CAP_DSI ), + .PM_CAP_ID ( PM_CAP_ID ), + .PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ), + .PM_CAP_ON ( PM_CAP_ON ), + .PM_CAP_PME_CLOCK( PM_CAP_PME_CLOCK ), + .PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ), + .PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ), + .PM_CAP_VERSION ( PM_CAP_VERSION ), + .PM_CSR_B2B3 ( PM_CSR_B2B3 ), + .PM_CSR_BPCCEN ( PM_CSR_BPCCEN ), + .PM_CSR_NOSOFTRST( PM_CSR_NOSOFTRST ), + .PM_DATA0( PM_DATA0 ), + .PM_DATA1( PM_DATA1 ), + .PM_DATA2( PM_DATA2 ), + .PM_DATA3( PM_DATA3 ), + .PM_DATA4( PM_DATA4 ), + .PM_DATA5( PM_DATA5 ), + .PM_DATA6( PM_DATA6 ), + .PM_DATA7( PM_DATA7 ), + .PM_DATA_SCALE0 ( PM_DATA_SCALE0 ), + .PM_DATA_SCALE1 ( PM_DATA_SCALE1 ), + .PM_DATA_SCALE2 ( PM_DATA_SCALE2 ), + .PM_DATA_SCALE3 ( PM_DATA_SCALE3 ), + .PM_DATA_SCALE4 ( PM_DATA_SCALE4 ), + .PM_DATA_SCALE5 ( PM_DATA_SCALE5 ), + .PM_DATA_SCALE6 ( PM_DATA_SCALE6 ), + .PM_DATA_SCALE7 ( PM_DATA_SCALE7 ), + .PM_MF (PM_MF), + .RBAR_BASE_PTR (RBAR_BASE_PTR), + .RBAR_CAP_CONTROL_ENCODEDBAR0 (RBAR_CAP_CONTROL_ENCODEDBAR0), + .RBAR_CAP_CONTROL_ENCODEDBAR1 (RBAR_CAP_CONTROL_ENCODEDBAR1), + .RBAR_CAP_CONTROL_ENCODEDBAR2 (RBAR_CAP_CONTROL_ENCODEDBAR2), + .RBAR_CAP_CONTROL_ENCODEDBAR3 (RBAR_CAP_CONTROL_ENCODEDBAR3), + .RBAR_CAP_CONTROL_ENCODEDBAR4 (RBAR_CAP_CONTROL_ENCODEDBAR4), + .RBAR_CAP_CONTROL_ENCODEDBAR5 (RBAR_CAP_CONTROL_ENCODEDBAR5), + .RBAR_CAP_ID (RBAR_CAP_ID), + .RBAR_CAP_INDEX0 (RBAR_CAP_INDEX0), + .RBAR_CAP_INDEX1 (RBAR_CAP_INDEX1), + .RBAR_CAP_INDEX2 (RBAR_CAP_INDEX2), + .RBAR_CAP_INDEX3 (RBAR_CAP_INDEX3), + .RBAR_CAP_INDEX4 (RBAR_CAP_INDEX4), + .RBAR_CAP_INDEX5 (RBAR_CAP_INDEX5), + .RBAR_CAP_NEXTPTR (RBAR_CAP_NEXTPTR), + .RBAR_CAP_ON (RBAR_CAP_ON), + .RBAR_CAP_SUP0 (RBAR_CAP_SUP0), + .RBAR_CAP_SUP1 (RBAR_CAP_SUP1), + .RBAR_CAP_SUP2 (RBAR_CAP_SUP2), + .RBAR_CAP_SUP3 (RBAR_CAP_SUP3), + .RBAR_CAP_SUP4 (RBAR_CAP_SUP4), + .RBAR_CAP_SUP5 (RBAR_CAP_SUP5), + .RBAR_CAP_VERSION (RBAR_CAP_VERSION), + .RBAR_NUM (RBAR_NUM), + .RECRC_CHK (RECRC_CHK), + .RECRC_CHK_TRIM (RECRC_CHK_TRIM), + .ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ), + .RP_AUTO_SPD ( RP_AUTO_SPD ), + .RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ), + .SELECT_DLL_IF ( SELECT_DLL_IF ), + .SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ), + .SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ), + .SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ), + .SLOT_CAP_HOTPLUG_CAPABLE( SLOT_CAP_HOTPLUG_CAPABLE ), + .SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ), + .SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ), + .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ), + .SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ), + .SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ), + .SLOT_CAP_POWER_INDICATOR_PRESENT( SLOT_CAP_POWER_INDICATOR_PRESENT ), + .SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ), + .SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ), + .SPARE_BIT0 ( SPARE_BIT0 ), + .SPARE_BIT1 ( SPARE_BIT1 ), + .SPARE_BIT2 ( SPARE_BIT2 ), + .SPARE_BIT3 ( SPARE_BIT3 ), + .SPARE_BIT4 ( SPARE_BIT4 ), + .SPARE_BIT5 ( SPARE_BIT5 ), + .SPARE_BIT6 ( SPARE_BIT6 ), + .SPARE_BIT7 ( SPARE_BIT7 ), + .SPARE_BIT8 ( SPARE_BIT8 ), + .SPARE_BYTE0 ( SPARE_BYTE0 ), + .SPARE_BYTE1 ( SPARE_BYTE1 ), + .SPARE_BYTE2 ( SPARE_BYTE2 ), + .SPARE_BYTE3 ( SPARE_BYTE3 ), + .SPARE_WORD0 ( SPARE_WORD0 ), + .SPARE_WORD1 ( SPARE_WORD1 ), + .SPARE_WORD2 ( SPARE_WORD2 ), + .SPARE_WORD3 ( SPARE_WORD3 ), + .SSL_MESSAGE_AUTO (SSL_MESSAGE_AUTO), + .TECRC_EP_INV ( TECRC_EP_INV ), + .TL_RBYPASS(TL_RBYPASS), + .TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ), + .TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ), + .TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ), + .TL_TFC_DISABLE ( TL_TFC_DISABLE ), + .TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ), + .TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ), + .TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ), + .TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ), + .TRN_DW (TRN_DW), + .TRN_NP_FC (TRN_NP_FC), + .UPCONFIG_CAPABLE( UPCONFIG_CAPABLE ), + .UPSTREAM_FACING ( UPSTREAM_FACING ), + .UR_ATOMIC (UR_ATOMIC), + .UR_CFG1 (UR_CFG1), + .UR_INV_REQ(UR_INV_REQ), + .UR_PRS_RESPONSE (UR_PRS_RESPONSE), + .USER_CLK2_DIV2 (USER_CLK2_DIV2), + .USER_CLK_FREQ ( USER_CLK_FREQ ), + .USE_RID_PINS (USE_RID_PINS), + .VC0_CPL_INFINITE( VC0_CPL_INFINITE ), + .VC0_RX_RAM_LIMIT( VC0_RX_RAM_LIMIT ), + .VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ), + .VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ), + .VC0_TOTAL_CREDITS_NPD (VC0_TOTAL_CREDITS_NPD), + .VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ), + .VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ), + .VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ), + .VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ), + .VC_BASE_PTR ( VC_BASE_PTR ), + .VC_CAP_ID ( VC_CAP_ID ), + .VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ), + .VC_CAP_ON ( VC_CAP_ON ), + .VC_CAP_REJECT_SNOOP_TRANSACTIONS( VC_CAP_REJECT_SNOOP_TRANSACTIONS ), + .VC_CAP_VERSION ( VC_CAP_VERSION ), + .VSEC_BASE_PTR ( VSEC_BASE_PTR ), + .VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ), + .VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ), + .VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ), + .VSEC_CAP_ID ( VSEC_CAP_ID ), + .VSEC_CAP_IS_LINK_VISIBLE( VSEC_CAP_IS_LINK_VISIBLE ), + .VSEC_CAP_NEXTPTR( VSEC_CAP_NEXTPTR ), + .VSEC_CAP_ON ( VSEC_CAP_ON ), + .VSEC_CAP_VERSION( VSEC_CAP_VERSION ), + .ENABLE_JTAG_DBG ( ENABLE_JTAG_DBG ) + ) pcie_7x_i ( + .trn_lnk_up ( trn_lnk_up ), + .trn_clk ( user_clk_out ), + .lnk_clk_en ( lnk_clk_en), + .user_rst_n ( user_rst_n ), + .received_func_lvl_rst_n ( cfg_received_func_lvl_rst_n ), + .sys_rst_n (~phy_rdy_n), + .pl_rst_n ( 1'b1 ), + .dl_rst_n ( 1'b1 ), + .tl_rst_n ( 1'b1 ), + .cm_sticky_rst_n ( 1'b1 ), + + .func_lvl_rst_n ( func_lvl_rst_n ), + .cm_rst_n ( cm_rst_n ), + .trn_rbar_hit ( trn_rbar_hit ), + .trn_rd ( trn_rd ), + .trn_recrc_err ( trn_recrc_err ), + .trn_reof ( trn_reof ), + .trn_rerrfwd ( trn_rerrfwd ), + .trn_rrem ( trn_rrem ), + .trn_rsof ( trn_rsof ), + .trn_rsrc_dsc ( trn_rsrc_dsc ), + .trn_rsrc_rdy ( trn_rsrc_rdy ), + .trn_rdst_rdy ( trn_rdst_rdy ), + .trn_rnp_ok ( rx_np_ok ), + .trn_rnp_req ( rx_np_req ), + .trn_rfcp_ret ( 1'b1 ), + .trn_tbuf_av ( tx_buf_av ), + .trn_tcfg_req ( tx_cfg_req ), + .trn_tdllp_dst_rdy ( ), + .trn_tdst_rdy ( trn_tdst_rdy ), + .trn_terr_drop ( tx_err_drop ), + .trn_tcfg_gnt ( trn_tcfg_gnt ), + .trn_td ( trn_td ), + .trn_tdllp_data ( 32'b0 ), + .trn_tdllp_src_rdy ( 1'b0 ), + .trn_tecrc_gen ( trn_tecrc_gen ), + .trn_teof ( trn_teof ), + .trn_terrfwd ( trn_terrfwd ), + .trn_trem ( trn_trem), + .trn_tsof ( trn_tsof ), + .trn_tsrc_dsc ( trn_tsrc_dsc ), + .trn_tsrc_rdy ( trn_tsrc_rdy ), + .trn_tstr ( trn_tstr ), + + .trn_fc_cpld ( fc_cpld ), + .trn_fc_cplh ( fc_cplh ), + .trn_fc_npd ( fc_npd ), + .trn_fc_nph ( fc_nph ), + .trn_fc_pd ( fc_pd ), + .trn_fc_ph ( fc_ph ), + .trn_fc_sel ( fc_sel ), + + .cfg_dev_id (cfg_dev_id), + .cfg_vend_id (cfg_vend_id), + .cfg_rev_id (cfg_rev_id), + .cfg_subsys_id (cfg_subsys_id), + .cfg_subsys_vend_id (cfg_subsys_vend_id), + .cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum), + + .cfg_bridge_serr_en (cfg_bridge_serr_en), + + .cfg_command_bus_master_enable ( cfg_command_bus_master_enable ), + .cfg_command_interrupt_disable ( cfg_command_interrupt_disable ), + .cfg_command_io_enable ( cfg_command_io_enable ), + .cfg_command_mem_enable ( cfg_command_mem_enable ), + .cfg_command_serr_en ( cfg_command_serr_en ), + .cfg_dev_control_aux_power_en ( cfg_dev_control_aux_power_en ), + .cfg_dev_control_corr_err_reporting_en ( cfg_dev_control_corr_err_reporting_en ), + .cfg_dev_control_enable_ro ( cfg_dev_control_enable_ro ), + .cfg_dev_control_ext_tag_en ( cfg_dev_control_ext_tag_en ), + .cfg_dev_control_fatal_err_reporting_en ( cfg_dev_control_fatal_err_reporting_en ), + .cfg_dev_control_max_payload ( cfg_dev_control_max_payload ), + .cfg_dev_control_max_read_req ( cfg_dev_control_max_read_req ), + .cfg_dev_control_non_fatal_reporting_en ( cfg_dev_control_non_fatal_reporting_en ), + .cfg_dev_control_no_snoop_en ( cfg_dev_control_no_snoop_en ), + .cfg_dev_control_phantom_en ( cfg_dev_control_phantom_en ), + .cfg_dev_control_ur_err_reporting_en ( cfg_dev_control_ur_err_reporting_en ), + .cfg_dev_control2_cpl_timeout_dis ( cfg_dev_control2_cpl_timeout_dis ), + .cfg_dev_control2_cpl_timeout_val ( cfg_dev_control2_cpl_timeout_val ), + .cfg_dev_control2_ari_forward_en ( cfg_dev_control2_ari_forward_en), + .cfg_dev_control2_atomic_requester_en ( cfg_dev_control2_atomic_requester_en), + .cfg_dev_control2_atomic_egress_block ( cfg_dev_control2_atomic_egress_block), + .cfg_dev_control2_ido_req_en ( cfg_dev_control2_ido_req_en), + .cfg_dev_control2_ido_cpl_en ( cfg_dev_control2_ido_cpl_en), + .cfg_dev_control2_ltr_en ( cfg_dev_control2_ltr_en), + .cfg_dev_control2_tlp_prefix_block ( cfg_dev_control2_tlp_prefix_block), + .cfg_dev_status_corr_err_detected ( cfg_dev_status_corr_err_detected ), + .cfg_dev_status_fatal_err_detected ( cfg_dev_status_fatal_err_detected ), + .cfg_dev_status_non_fatal_err_detected ( cfg_dev_status_non_fatal_err_detected ), + .cfg_dev_status_ur_detected ( cfg_dev_status_ur_detected ), + + .cfg_mgmt_do ( cfg_mgmt_do ), + .cfg_err_aer_headerlog_set_n ( cfg_err_aer_headerlog_set_n), + .cfg_err_aer_headerlog ( cfg_err_aer_headerlog), + .cfg_err_cpl_rdy_n ( cfg_err_cpl_rdy_n ), + .cfg_interrupt_do ( cfg_interrupt_do ), + .cfg_interrupt_mmenable ( cfg_interrupt_mmenable ), + .cfg_interrupt_msienable ( cfg_interrupt_msienable ), + .cfg_interrupt_msixenable ( cfg_interrupt_msixenable ), + .cfg_interrupt_msixfm ( cfg_interrupt_msixfm ), + .cfg_interrupt_rdy_n ( cfg_interrupt_rdy_n ), + .cfg_link_control_rcb ( cfg_link_control_rcb ), + .cfg_link_control_aspm_control ( cfg_link_control_aspm_control ), + .cfg_link_control_auto_bandwidth_int_en ( cfg_link_control_auto_bandwidth_int_en ), + .cfg_link_control_bandwidth_int_en ( cfg_link_control_bandwidth_int_en ), + .cfg_link_control_clock_pm_en ( cfg_link_control_clock_pm_en ), + .cfg_link_control_common_clock ( cfg_link_control_common_clock ), + .cfg_link_control_extended_sync ( cfg_link_control_extended_sync ), + .cfg_link_control_hw_auto_width_dis ( cfg_link_control_hw_auto_width_dis ), + .cfg_link_control_link_disable ( cfg_link_control_link_disable ), + .cfg_link_control_retrain_link ( cfg_link_control_retrain_link ), + .cfg_link_status_auto_bandwidth_status ( cfg_link_status_auto_bandwidth_status ), + .cfg_link_status_bandwidth_status ( cfg_link_status_bandwidth_status ), + .cfg_link_status_current_speed ( cfg_link_status_current_speed ), + .cfg_link_status_dll_active ( cfg_link_status_dll_active ), + .cfg_link_status_link_training ( cfg_link_status_link_training ), + .cfg_link_status_negotiated_width ( cfg_link_status_negotiated_width), + .cfg_msg_data ( cfg_msg_data ), + .cfg_msg_received ( cfg_msg_received ), + .cfg_msg_received_assert_int_a ( cfg_msg_received_assert_int_a), + .cfg_msg_received_assert_int_b ( cfg_msg_received_assert_int_b), + .cfg_msg_received_assert_int_c ( cfg_msg_received_assert_int_c), + .cfg_msg_received_assert_int_d ( cfg_msg_received_assert_int_d), + .cfg_msg_received_deassert_int_a ( cfg_msg_received_deassert_int_a), + .cfg_msg_received_deassert_int_b ( cfg_msg_received_deassert_int_b), + .cfg_msg_received_deassert_int_c ( cfg_msg_received_deassert_int_c), + .cfg_msg_received_deassert_int_d ( cfg_msg_received_deassert_int_d), + .cfg_msg_received_err_cor ( cfg_msg_received_err_cor), + .cfg_msg_received_err_fatal ( cfg_msg_received_err_fatal), + .cfg_msg_received_err_non_fatal ( cfg_msg_received_err_non_fatal), + .cfg_msg_received_pm_as_nak ( cfg_msg_received_pm_as_nak), + .cfg_msg_received_pme_to ( cfg_msg_received_pme_to ), + .cfg_msg_received_pme_to_ack ( cfg_msg_received_pme_to_ack), + .cfg_msg_received_pm_pme ( cfg_msg_received_pm_pme), + .cfg_msg_received_setslotpowerlimit ( cfg_msg_received_setslotpowerlimit), + .cfg_msg_received_unlock ( cfg_msg_received_unlock), + .cfg_pcie_link_state ( cfg_pcie_link_state ), + .cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en), + .cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate), + .cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status), + .cfg_pm_rcv_as_req_l1_n ( cfg_pm_rcv_as_req_l1_n), + .cfg_pm_rcv_enter_l1_n ( cfg_pm_rcv_enter_l1_n), + .cfg_pm_rcv_enter_l23_n ( cfg_pm_rcv_enter_l23_n), + + .cfg_pm_rcv_req_ack_n ( cfg_pm_rcv_req_ack_n), + .cfg_mgmt_rd_wr_done_n ( cfg_mgmt_rd_wr_done_n ), + .cfg_slot_control_electromech_il_ctl_pulse (cfg_slot_control_electromech_il_ctl_pulse), + .cfg_root_control_syserr_corr_err_en ( cfg_root_control_syserr_corr_err_en), + .cfg_root_control_syserr_non_fatal_err_en ( cfg_root_control_syserr_non_fatal_err_en), + .cfg_root_control_syserr_fatal_err_en ( cfg_root_control_syserr_fatal_err_en), + .cfg_root_control_pme_int_en ( cfg_root_control_pme_int_en ), + .cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ), + .cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ), + .cfg_aer_rooterr_corr_err_reporting_en ( cfg_aer_rooterr_corr_err_reporting_en), + .cfg_aer_rooterr_non_fatal_err_reporting_en( cfg_aer_rooterr_non_fatal_err_reporting_en), + .cfg_aer_rooterr_fatal_err_reporting_en ( cfg_aer_rooterr_fatal_err_reporting_en), + .cfg_aer_rooterr_corr_err_received ( cfg_aer_rooterr_corr_err_received), + .cfg_aer_rooterr_non_fatal_err_received ( cfg_aer_rooterr_non_fatal_err_received), + .cfg_aer_rooterr_fatal_err_received ( cfg_aer_rooterr_fatal_err_received), + .cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ), + .cfg_transaction ( cfg_transaction), + .cfg_transaction_addr ( cfg_transaction_addr), + .cfg_transaction_type ( cfg_transaction_type), + .cfg_vc_tcvc_map ( cfg_vc_tcvc_map), + .cfg_mgmt_byte_en_n ( cfg_mgmt_byte_en_n ), + .cfg_mgmt_di ( cfg_mgmt_di ), + .cfg_ds_bus_number ( cfg_ds_bus_number ), + .cfg_ds_device_number ( cfg_ds_device_number ), + .cfg_ds_function_number ( cfg_ds_function_number ), + .cfg_dsn ( cfg_dsn ), + .cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ), + .cfg_err_acs_n ( 1'b1 ), + .cfg_err_cor_n ( cfg_err_cor_n ), + .cfg_err_cpl_abort_n ( cfg_err_cpl_abort_n ), + .cfg_err_cpl_timeout_n ( cfg_err_cpl_timeout_n ), + .cfg_err_cpl_unexpect_n ( cfg_err_cpl_unexpect_n ), + .cfg_err_ecrc_n ( cfg_err_ecrc_n ), + .cfg_err_locked_n ( cfg_err_locked_n ), + .cfg_err_posted_n ( cfg_err_posted_n ), + .cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ), + .cfg_err_ur_n ( cfg_err_ur_n ), + .cfg_err_malformed_n ( cfg_err_malformed_n ), + .cfg_err_poisoned_n ( cfg_err_poisoned_n), + .cfg_err_atomic_egress_blocked_n ( cfg_err_atomic_egress_blocked_n ), + .cfg_err_mc_blocked_n ( cfg_err_mc_blocked_n ), + .cfg_err_internal_uncor_n ( cfg_err_internal_uncor_n ), + .cfg_err_internal_cor_n ( cfg_err_internal_cor_n ), + .cfg_err_norecovery_n ( cfg_err_norecovery_n ), + + .cfg_interrupt_assert_n ( cfg_interrupt_assert_n ), + .cfg_interrupt_di ( cfg_interrupt_di ), + .cfg_interrupt_n ( cfg_interrupt_n ), + .cfg_interrupt_stat_n ( cfg_interrupt_stat_n), + .cfg_pm_send_pme_to_n ( cfg_pm_send_pme_to_n ), + .cfg_pm_turnoff_ok_n ( cfg_turnoff_ok_w ), + .cfg_pm_wake_n ( cfg_pm_wake_n ), + .cfg_pm_halt_aspm_l0s_n ( cfg_pm_halt_aspm_l0s_n ), + .cfg_pm_halt_aspm_l1_n ( cfg_pm_halt_aspm_l1_n ), + .cfg_pm_force_state_en_n ( cfg_pm_force_state_en_n ), + .cfg_pm_force_state ( cfg_pm_force_state ), + .cfg_force_mps ( cfg_force_mps ), + .cfg_force_common_clock_off ( cfg_force_common_clock_off ), + .cfg_force_extended_sync_on ( cfg_force_extended_sync_on ), + .cfg_port_number ( cfg_port_number ), + .cfg_mgmt_rd_en_n ( cfg_mgmt_rd_en_n ), + .cfg_trn_pending_n ( ~cfg_trn_pending ), + .cfg_mgmt_wr_en_n ( cfg_mgmt_wr_en_n ), + .cfg_mgmt_wr_readonly_n ( cfg_mgmt_wr_readonly_n ), + .cfg_mgmt_wr_rw1c_as_rw_n ( cfg_mgmt_wr_rw1c_as_rw_n ), + + .pl_initial_link_width ( pl_initial_link_width ), + .pl_lane_reversal_mode ( pl_lane_reversal_mode ), + .pl_link_gen2_cap ( pl_link_gen2_cap ), + .pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ), + .pl_link_upcfg_cap ( pl_link_upcfg_cap ), + .pl_ltssm_state ( pl_ltssm_state ), + .pl_phy_lnk_up_n ( pl_phy_lnk_up_n ), + .pl_received_hot_rst ( pl_received_hot_rst ), + .pl_rx_pm_state ( pl_rx_pm_state ), + .pl_sel_lnk_rate ( pl_sel_lnk_rate), + .pl_sel_lnk_width ( pl_sel_lnk_width ), + .pl_tx_pm_state ( pl_tx_pm_state ), + .pl_directed_link_auton ( pl_directed_link_auton ), + .pl_directed_link_change ( pl_directed_link_change ), + .pl_directed_link_speed ( pl_directed_link_speed ), + .pl_directed_link_width ( pl_directed_link_width ), + .pl_downstream_deemph_source ( pl_downstream_deemph_source ), + .pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ), + .pl_transmit_hot_rst ( pl_transmit_hot_rst ), + .pl_directed_ltssm_new_vld ( pl_directed_ltssm_new_vld ), + .pl_directed_ltssm_new ( pl_directed_ltssm_new ), + .pl_directed_ltssm_stall ( pl_directed_ltssm_stall ), + .pl_directed_change_done ( pl_directed_change_done ), + + .dbg_sclr_a ( dbg_sclr_a ), + .dbg_sclr_b ( dbg_sclr_b ), + .dbg_sclr_c ( dbg_sclr_c ), + .dbg_sclr_d ( dbg_sclr_d ), + .dbg_sclr_e ( dbg_sclr_e ), + .dbg_sclr_f ( dbg_sclr_f ), + .dbg_sclr_g ( dbg_sclr_g ), + .dbg_sclr_h ( dbg_sclr_h ), + .dbg_sclr_i ( dbg_sclr_i ), + .dbg_sclr_j ( dbg_sclr_j ), + .dbg_sclr_k ( dbg_sclr_k ), + + .dbg_vec_a ( dbg_vec_a ), + .dbg_vec_b ( dbg_vec_b ), + .dbg_vec_c ( dbg_vec_c ), + .pl_dbg_vec ( pl_dbg_vec ), + .dbg_mode ( dbg_mode ), + .dbg_sub_mode ( dbg_sub_mode ), + .pl_dbg_mode ( pl_dbg_mode ), + + .drp_do ( drp_do ), + .drp_rdy ( drp_rdy ), + .drp_clk ( drp_clk ), + .drp_addr ( drp_addr ), + .drp_en ( drp_en ), + .drp_di ( drp_di ), + .drp_we ( drp_we ), + + .ll2_tlp_rcv ( 1'b0 ), + .ll2_send_enter_l1 ( 1'b0 ), + .ll2_send_enter_l23 ( 1'b0 ), + .ll2_send_as_req_l1 ( 1'b0 ), + .ll2_send_pm_ack ( 1'b0 ), + .ll2_suspend_now ( 1'b0 ), + .ll2_tfc_init1_seq ( ), + .ll2_tfc_init2_seq ( ), + .ll2_suspend_ok ( ), + .ll2_tx_idle ( ), + .ll2_link_status ( ), + .ll2_receiver_err ( ), + .ll2_protocol_err ( ), + .ll2_bad_tlp_err ( ), + .ll2_bad_dllp_err ( ), + .ll2_replay_ro_err ( ), + .ll2_replay_to_err ( ), + .tl2_ppm_suspend_req ( 1'b0 ), + .tl2_aspm_suspend_credit_check ( 1'b0 ), + .tl2_ppm_suspend_ok ( ), + .tl2_aspm_suspend_req ( ), + .tl2_aspm_suspend_credit_check_ok ( ), + .tl2_err_hdr ( ), + .tl2_err_malformed ( ), + .tl2_err_rxoverflow ( ), + .tl2_err_fcpe ( ), + .pl2_directed_lstate ( 5'b0 ), + .pl2_suspend_ok ( ), + .pl2_recovery ( ), + .pl2_rx_elec_idle ( ), + .pl2_rx_pm_state ( ), + .pl2_l0_req ( ), + .pl2_link_up ( ), + .pl2_receiver_err ( ), + + .trn_rdllp_data (trn_rdllp_data ), + .trn_rdllp_src_rdy (trn_rdllp_src_rdy ), + + .pipe_clk ( pipe_clk ), + .user_clk2 ( user_clk2 ), + .user_clk ( user_clk ), + .user_clk_prebuf ( 1'b0 ), + .user_clk_prebuf_en ( 1'b0 ), + + .pipe_rx0_polarity ( pipe_rx0_polarity ), + .pipe_rx1_polarity ( pipe_rx1_polarity ), + .pipe_rx2_polarity ( pipe_rx2_polarity ), + .pipe_rx3_polarity ( pipe_rx3_polarity ), + .pipe_rx4_polarity ( pipe_rx4_polarity ), + .pipe_rx5_polarity ( pipe_rx5_polarity ), + .pipe_rx6_polarity ( pipe_rx6_polarity ), + .pipe_rx7_polarity ( pipe_rx7_polarity ), + .pipe_tx0_compliance ( pipe_tx0_compliance ), + .pipe_tx1_compliance ( pipe_tx1_compliance ), + .pipe_tx2_compliance ( pipe_tx2_compliance ), + .pipe_tx3_compliance ( pipe_tx3_compliance ), + .pipe_tx4_compliance ( pipe_tx4_compliance ), + .pipe_tx5_compliance ( pipe_tx5_compliance ), + .pipe_tx6_compliance ( pipe_tx6_compliance ), + .pipe_tx7_compliance ( pipe_tx7_compliance ), + .pipe_tx0_char_is_k ( pipe_tx0_char_is_k ), + .pipe_tx1_char_is_k ( pipe_tx1_char_is_k ), + .pipe_tx2_char_is_k ( pipe_tx2_char_is_k ), + .pipe_tx3_char_is_k ( pipe_tx3_char_is_k ), + .pipe_tx4_char_is_k ( pipe_tx4_char_is_k ), + .pipe_tx5_char_is_k ( pipe_tx5_char_is_k ), + .pipe_tx6_char_is_k ( pipe_tx6_char_is_k ), + .pipe_tx7_char_is_k ( pipe_tx7_char_is_k ), + .pipe_tx0_data ( pipe_tx0_data ), + .pipe_tx1_data ( pipe_tx1_data ), + .pipe_tx2_data ( pipe_tx2_data ), + .pipe_tx3_data ( pipe_tx3_data ), + .pipe_tx4_data ( pipe_tx4_data ), + .pipe_tx5_data ( pipe_tx5_data ), + .pipe_tx6_data ( pipe_tx6_data ), + .pipe_tx7_data ( pipe_tx7_data ), + .pipe_tx0_elec_idle ( pipe_tx0_elec_idle ), + .pipe_tx1_elec_idle ( pipe_tx1_elec_idle ), + .pipe_tx2_elec_idle ( pipe_tx2_elec_idle ), + .pipe_tx3_elec_idle ( pipe_tx3_elec_idle ), + .pipe_tx4_elec_idle ( pipe_tx4_elec_idle ), + .pipe_tx5_elec_idle ( pipe_tx5_elec_idle ), + .pipe_tx6_elec_idle ( pipe_tx6_elec_idle ), + .pipe_tx7_elec_idle ( pipe_tx7_elec_idle ), + .pipe_tx0_powerdown ( pipe_tx0_powerdown ), + .pipe_tx1_powerdown ( pipe_tx1_powerdown ), + .pipe_tx2_powerdown ( pipe_tx2_powerdown ), + .pipe_tx3_powerdown ( pipe_tx3_powerdown ), + .pipe_tx4_powerdown ( pipe_tx4_powerdown ), + .pipe_tx5_powerdown ( pipe_tx5_powerdown ), + .pipe_tx6_powerdown ( pipe_tx6_powerdown ), + .pipe_tx7_powerdown ( pipe_tx7_powerdown ), + + .pipe_rx0_char_is_k ( pipe_rx0_char_is_k ), + .pipe_rx1_char_is_k ( pipe_rx1_char_is_k ), + .pipe_rx2_char_is_k ( pipe_rx2_char_is_k ), + .pipe_rx3_char_is_k ( pipe_rx3_char_is_k ), + .pipe_rx4_char_is_k ( pipe_rx4_char_is_k ), + .pipe_rx5_char_is_k ( pipe_rx5_char_is_k ), + .pipe_rx6_char_is_k ( pipe_rx6_char_is_k ), + .pipe_rx7_char_is_k ( pipe_rx7_char_is_k ), + .pipe_rx0_valid ( pipe_rx0_valid ), + .pipe_rx1_valid ( pipe_rx1_valid ), + .pipe_rx2_valid ( pipe_rx2_valid ), + .pipe_rx3_valid ( pipe_rx3_valid ), + .pipe_rx4_valid ( pipe_rx4_valid ), + .pipe_rx5_valid ( pipe_rx5_valid ), + .pipe_rx6_valid ( pipe_rx6_valid ), + .pipe_rx7_valid ( pipe_rx7_valid ), + .pipe_rx0_data ( pipe_rx0_data ), + .pipe_rx1_data ( pipe_rx1_data ), + .pipe_rx2_data ( pipe_rx2_data ), + .pipe_rx3_data ( pipe_rx3_data ), + .pipe_rx4_data ( pipe_rx4_data ), + .pipe_rx5_data ( pipe_rx5_data ), + .pipe_rx6_data ( pipe_rx6_data ), + .pipe_rx7_data ( pipe_rx7_data ), + .pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned ), + .pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned ), + .pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned ), + .pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned ), + .pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned ), + .pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned ), + .pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned ), + .pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned ), + .pipe_rx0_status ( pipe_rx0_status ), + .pipe_rx1_status ( pipe_rx1_status ), + .pipe_rx2_status ( pipe_rx2_status ), + .pipe_rx3_status ( pipe_rx3_status ), + .pipe_rx4_status ( pipe_rx4_status ), + .pipe_rx5_status ( pipe_rx5_status ), + .pipe_rx6_status ( pipe_rx6_status ), + .pipe_rx7_status ( pipe_rx7_status ), + .pipe_rx0_phy_status ( pipe_rx0_phy_status ), + .pipe_rx1_phy_status ( pipe_rx1_phy_status ), + .pipe_rx2_phy_status ( pipe_rx2_phy_status ), + .pipe_rx3_phy_status ( pipe_rx3_phy_status ), + .pipe_rx4_phy_status ( pipe_rx4_phy_status ), + .pipe_rx5_phy_status ( pipe_rx5_phy_status ), + .pipe_rx6_phy_status ( pipe_rx6_phy_status ), + .pipe_rx7_phy_status ( pipe_rx7_phy_status ), + .pipe_tx_deemph ( pipe_tx_deemph ), + .pipe_tx_margin ( pipe_tx_margin ), + .pipe_tx_reset ( pipe_tx_reset ), + .pipe_tx_rcvr_det ( pipe_tx_rcvr_det ), + .pipe_tx_rate ( pipe_tx_rate ), + + .pipe_rx0_elec_idle ( pipe_rx0_elec_idle ), + .pipe_rx1_elec_idle ( pipe_rx1_elec_idle ), + .pipe_rx2_elec_idle ( pipe_rx2_elec_idle ), + .pipe_rx3_elec_idle ( pipe_rx3_elec_idle ), + .pipe_rx4_elec_idle ( pipe_rx4_elec_idle ), + .pipe_rx5_elec_idle ( pipe_rx5_elec_idle ), + .pipe_rx6_elec_idle ( pipe_rx6_elec_idle ), + .pipe_rx7_elec_idle ( pipe_rx7_elec_idle ) + ); + + //------------------------------------------------------------------------------------------------------------------// + // PIPE Interface PIPELINE Module // + //------------------------------------------------------------------------------------------------------------------// +pcie_7x_0_pcie_pipe_pipeline # ( + + .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), + .PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ) + + ) + pcie_pipe_pipeline_i ( + + // Pipe Per-Link Signals + .pipe_tx_rcvr_det_i (pipe_tx_rcvr_det), + .pipe_tx_reset_i (1'b0), //MV? + .pipe_tx_rate_i (pipe_tx_rate), + .pipe_tx_deemph_i (pipe_tx_deemph), + .pipe_tx_margin_i (pipe_tx_margin), + .pipe_tx_swing_i (1'b0), + + .pipe_tx_rcvr_det_o (pipe_tx_rcvr_det_gt), + .pipe_tx_reset_o ( ), + .pipe_tx_rate_o (pipe_tx_rate_gt), + .pipe_tx_deemph_o (pipe_tx_deemph_gt), + .pipe_tx_margin_o (pipe_tx_margin_gt), + .pipe_tx_swing_o ( ), + + // Pipe Per-Lane Signals - Lane 0 + + .pipe_rx0_char_is_k_o (pipe_rx0_char_is_k ), + .pipe_rx0_data_o (pipe_rx0_data ), + .pipe_rx0_valid_o (pipe_rx0_valid ), + .pipe_rx0_chanisaligned_o (pipe_rx0_chanisaligned ), + .pipe_rx0_status_o (pipe_rx0_status ), + .pipe_rx0_phy_status_o (pipe_rx0_phy_status ), + .pipe_rx0_elec_idle_i (pipe_rx0_elec_idle_gt ), + .pipe_rx0_polarity_i (pipe_rx0_polarity ), + .pipe_tx0_compliance_i (pipe_tx0_compliance ), + .pipe_tx0_char_is_k_i (pipe_tx0_char_is_k ), + .pipe_tx0_data_i (pipe_tx0_data ), + .pipe_tx0_elec_idle_i (pipe_tx0_elec_idle ), + .pipe_tx0_powerdown_i (pipe_tx0_powerdown ), + + .pipe_rx0_char_is_k_i (pipe_rx0_char_is_k_gt ), + .pipe_rx0_data_i (pipe_rx0_data_gt ), + .pipe_rx0_valid_i (pipe_rx0_valid_gt ), + .pipe_rx0_chanisaligned_i (pipe_rx0_chanisaligned_gt), + .pipe_rx0_status_i (pipe_rx0_status_gt ), + .pipe_rx0_phy_status_i (pipe_rx0_phy_status_gt ), + .pipe_rx0_elec_idle_o (pipe_rx0_elec_idle ), + .pipe_rx0_polarity_o (pipe_rx0_polarity_gt ), + .pipe_tx0_compliance_o (pipe_tx0_compliance_gt ), + .pipe_tx0_char_is_k_o (pipe_tx0_char_is_k_gt ), + .pipe_tx0_data_o (pipe_tx0_data_gt ), + .pipe_tx0_elec_idle_o (pipe_tx0_elec_idle_gt ), + .pipe_tx0_powerdown_o (pipe_tx0_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 1 + + .pipe_rx1_char_is_k_o (pipe_rx1_char_is_k ), + .pipe_rx1_data_o (pipe_rx1_data ), + .pipe_rx1_valid_o (pipe_rx1_valid ), + .pipe_rx1_chanisaligned_o (pipe_rx1_chanisaligned ), + .pipe_rx1_status_o (pipe_rx1_status ), + .pipe_rx1_phy_status_o (pipe_rx1_phy_status ), + .pipe_rx1_elec_idle_i (pipe_rx1_elec_idle_gt ), + .pipe_rx1_polarity_i (pipe_rx1_polarity ), + .pipe_tx1_compliance_i (pipe_tx1_compliance ), + .pipe_tx1_char_is_k_i (pipe_tx1_char_is_k ), + .pipe_tx1_data_i (pipe_tx1_data ), + .pipe_tx1_elec_idle_i (pipe_tx1_elec_idle ), + .pipe_tx1_powerdown_i (pipe_tx1_powerdown ), + + .pipe_rx1_char_is_k_i (pipe_rx1_char_is_k_gt ), + .pipe_rx1_data_i (pipe_rx1_data_gt ), + .pipe_rx1_valid_i (pipe_rx1_valid_gt ), + .pipe_rx1_chanisaligned_i (pipe_rx1_chanisaligned_gt), + .pipe_rx1_status_i (pipe_rx1_status_gt ), + .pipe_rx1_phy_status_i (pipe_rx1_phy_status_gt ), + .pipe_rx1_elec_idle_o (pipe_rx1_elec_idle ), + .pipe_rx1_polarity_o (pipe_rx1_polarity_gt ), + .pipe_tx1_compliance_o (pipe_tx1_compliance_gt ), + .pipe_tx1_char_is_k_o (pipe_tx1_char_is_k_gt ), + .pipe_tx1_data_o (pipe_tx1_data_gt ), + .pipe_tx1_elec_idle_o (pipe_tx1_elec_idle_gt ), + .pipe_tx1_powerdown_o (pipe_tx1_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 2 + + .pipe_rx2_char_is_k_o (pipe_rx2_char_is_k ), + .pipe_rx2_data_o (pipe_rx2_data ), + .pipe_rx2_valid_o (pipe_rx2_valid ), + .pipe_rx2_chanisaligned_o (pipe_rx2_chanisaligned ), + .pipe_rx2_status_o (pipe_rx2_status ), + .pipe_rx2_phy_status_o (pipe_rx2_phy_status ), + .pipe_rx2_elec_idle_i (pipe_rx2_elec_idle_gt ), + .pipe_rx2_polarity_i (pipe_rx2_polarity ), + .pipe_tx2_compliance_i (pipe_tx2_compliance ), + .pipe_tx2_char_is_k_i (pipe_tx2_char_is_k ), + .pipe_tx2_data_i (pipe_tx2_data ), + .pipe_tx2_elec_idle_i (pipe_tx2_elec_idle ), + .pipe_tx2_powerdown_i (pipe_tx2_powerdown ), + + .pipe_rx2_char_is_k_i (pipe_rx2_char_is_k_gt ), + .pipe_rx2_data_i (pipe_rx2_data_gt ), + .pipe_rx2_valid_i (pipe_rx2_valid_gt ), + .pipe_rx2_chanisaligned_i (pipe_rx2_chanisaligned_gt), + .pipe_rx2_status_i (pipe_rx2_status_gt ), + .pipe_rx2_phy_status_i (pipe_rx2_phy_status_gt ), + .pipe_rx2_elec_idle_o (pipe_rx2_elec_idle ), + .pipe_rx2_polarity_o (pipe_rx2_polarity_gt ), + .pipe_tx2_compliance_o (pipe_tx2_compliance_gt ), + .pipe_tx2_char_is_k_o (pipe_tx2_char_is_k_gt ), + .pipe_tx2_data_o (pipe_tx2_data_gt ), + .pipe_tx2_elec_idle_o (pipe_tx2_elec_idle_gt ), + .pipe_tx2_powerdown_o (pipe_tx2_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 3 + + .pipe_rx3_char_is_k_o (pipe_rx3_char_is_k ), + .pipe_rx3_data_o (pipe_rx3_data ), + .pipe_rx3_valid_o (pipe_rx3_valid ), + .pipe_rx3_chanisaligned_o (pipe_rx3_chanisaligned ), + .pipe_rx3_status_o (pipe_rx3_status ), + .pipe_rx3_phy_status_o (pipe_rx3_phy_status ), + .pipe_rx3_elec_idle_i (pipe_rx3_elec_idle_gt ), + .pipe_rx3_polarity_i (pipe_rx3_polarity ), + .pipe_tx3_compliance_i (pipe_tx3_compliance ), + .pipe_tx3_char_is_k_i (pipe_tx3_char_is_k ), + .pipe_tx3_data_i (pipe_tx3_data ), + .pipe_tx3_elec_idle_i (pipe_tx3_elec_idle ), + .pipe_tx3_powerdown_i (pipe_tx3_powerdown ), + + .pipe_rx3_char_is_k_i (pipe_rx3_char_is_k_gt ), + .pipe_rx3_data_i (pipe_rx3_data_gt ), + .pipe_rx3_valid_i (pipe_rx3_valid_gt ), + .pipe_rx3_chanisaligned_i (pipe_rx3_chanisaligned_gt), + .pipe_rx3_status_i (pipe_rx3_status_gt ), + .pipe_rx3_phy_status_i (pipe_rx3_phy_status_gt ), + .pipe_rx3_elec_idle_o (pipe_rx3_elec_idle ), + .pipe_rx3_polarity_o (pipe_rx3_polarity_gt ), + .pipe_tx3_compliance_o (pipe_tx3_compliance_gt ), + .pipe_tx3_char_is_k_o (pipe_tx3_char_is_k_gt ), + .pipe_tx3_data_o (pipe_tx3_data_gt ), + .pipe_tx3_elec_idle_o (pipe_tx3_elec_idle_gt ), + .pipe_tx3_powerdown_o (pipe_tx3_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 4 + + .pipe_rx4_char_is_k_o (pipe_rx4_char_is_k ), + .pipe_rx4_data_o (pipe_rx4_data ), + .pipe_rx4_valid_o (pipe_rx4_valid ), + .pipe_rx4_chanisaligned_o (pipe_rx4_chanisaligned ), + .pipe_rx4_status_o (pipe_rx4_status ), + .pipe_rx4_phy_status_o (pipe_rx4_phy_status ), + .pipe_rx4_elec_idle_i (pipe_rx4_elec_idle_gt ), + .pipe_rx4_polarity_i (pipe_rx4_polarity ), + .pipe_tx4_compliance_i (pipe_tx4_compliance ), + .pipe_tx4_char_is_k_i (pipe_tx4_char_is_k ), + .pipe_tx4_data_i (pipe_tx4_data ), + .pipe_tx4_elec_idle_i (pipe_tx4_elec_idle ), + .pipe_tx4_powerdown_i (pipe_tx4_powerdown ), + .pipe_rx4_char_is_k_i (pipe_rx4_char_is_k_gt ), + .pipe_rx4_data_i (pipe_rx4_data_gt ), + .pipe_rx4_valid_i (pipe_rx4_valid_gt ), + .pipe_rx4_chanisaligned_i (pipe_rx4_chanisaligned_gt), + .pipe_rx4_status_i (pipe_rx4_status_gt ), + .pipe_rx4_phy_status_i (pipe_rx4_phy_status_gt ), + .pipe_rx4_elec_idle_o (pipe_rx4_elec_idle ), + .pipe_rx4_polarity_o (pipe_rx4_polarity_gt ), + .pipe_tx4_compliance_o (pipe_tx4_compliance_gt ), + .pipe_tx4_char_is_k_o (pipe_tx4_char_is_k_gt ), + .pipe_tx4_data_o (pipe_tx4_data_gt ), + .pipe_tx4_elec_idle_o (pipe_tx4_elec_idle_gt ), + .pipe_tx4_powerdown_o (pipe_tx4_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 5 + + .pipe_rx5_char_is_k_o (pipe_rx5_char_is_k ), + .pipe_rx5_data_o (pipe_rx5_data ), + .pipe_rx5_valid_o (pipe_rx5_valid ), + .pipe_rx5_chanisaligned_o (pipe_rx5_chanisaligned ), + .pipe_rx5_status_o (pipe_rx5_status ), + .pipe_rx5_phy_status_o (pipe_rx5_phy_status ), + .pipe_rx5_elec_idle_i (pipe_rx5_elec_idle_gt ), + .pipe_rx5_polarity_i (pipe_rx5_polarity ), + .pipe_tx5_compliance_i (pipe_tx5_compliance ), + .pipe_tx5_char_is_k_i (pipe_tx5_char_is_k ), + .pipe_tx5_data_i (pipe_tx5_data ), + .pipe_tx5_elec_idle_i (pipe_tx5_elec_idle ), + .pipe_tx5_powerdown_i (pipe_tx5_powerdown ), + .pipe_rx5_char_is_k_i (pipe_rx5_char_is_k_gt ), + .pipe_rx5_data_i (pipe_rx5_data_gt ), + .pipe_rx5_valid_i (pipe_rx5_valid_gt ), + .pipe_rx5_chanisaligned_i (pipe_rx5_chanisaligned_gt), + .pipe_rx5_status_i (pipe_rx5_status_gt ), + .pipe_rx5_phy_status_i (pipe_rx5_phy_status_gt ), + .pipe_rx5_elec_idle_o (pipe_rx5_elec_idle ), + .pipe_rx5_polarity_o (pipe_rx5_polarity_gt ), + .pipe_tx5_compliance_o (pipe_tx5_compliance_gt ), + .pipe_tx5_char_is_k_o (pipe_tx5_char_is_k_gt ), + .pipe_tx5_data_o (pipe_tx5_data_gt ), + .pipe_tx5_elec_idle_o (pipe_tx5_elec_idle_gt ), + .pipe_tx5_powerdown_o (pipe_tx5_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 6 + + .pipe_rx6_char_is_k_o (pipe_rx6_char_is_k ), + .pipe_rx6_data_o (pipe_rx6_data ), + .pipe_rx6_valid_o (pipe_rx6_valid ), + .pipe_rx6_chanisaligned_o (pipe_rx6_chanisaligned ), + .pipe_rx6_status_o (pipe_rx6_status ), + .pipe_rx6_phy_status_o (pipe_rx6_phy_status ), + .pipe_rx6_elec_idle_i (pipe_rx6_elec_idle_gt ), + .pipe_rx6_polarity_i (pipe_rx6_polarity ), + .pipe_tx6_compliance_i (pipe_tx6_compliance ), + .pipe_tx6_char_is_k_i (pipe_tx6_char_is_k ), + .pipe_tx6_data_i (pipe_tx6_data ), + .pipe_tx6_elec_idle_i (pipe_tx6_elec_idle ), + .pipe_tx6_powerdown_i (pipe_tx6_powerdown ), + .pipe_rx6_char_is_k_i (pipe_rx6_char_is_k_gt ), + .pipe_rx6_data_i (pipe_rx6_data_gt ), + .pipe_rx6_valid_i (pipe_rx6_valid_gt ), + .pipe_rx6_chanisaligned_i (pipe_rx6_chanisaligned_gt), + .pipe_rx6_status_i (pipe_rx6_status_gt ), + .pipe_rx6_phy_status_i (pipe_rx6_phy_status_gt ), + .pipe_rx6_elec_idle_o (pipe_rx6_elec_idle ), + .pipe_rx6_polarity_o (pipe_rx6_polarity_gt ), + .pipe_tx6_compliance_o (pipe_tx6_compliance_gt ), + .pipe_tx6_char_is_k_o (pipe_tx6_char_is_k_gt ), + .pipe_tx6_data_o (pipe_tx6_data_gt ), + .pipe_tx6_elec_idle_o (pipe_tx6_elec_idle_gt ), + .pipe_tx6_powerdown_o (pipe_tx6_powerdown_gt ), + + // Pipe Per-Lane Signals - Lane 7 + + .pipe_rx7_char_is_k_o (pipe_rx7_char_is_k ), + .pipe_rx7_data_o (pipe_rx7_data ), + .pipe_rx7_valid_o (pipe_rx7_valid ), + .pipe_rx7_chanisaligned_o (pipe_rx7_chanisaligned ), + .pipe_rx7_status_o (pipe_rx7_status ), + .pipe_rx7_phy_status_o (pipe_rx7_phy_status ), + .pipe_rx7_elec_idle_i (pipe_rx7_elec_idle_gt ), + .pipe_rx7_polarity_i (pipe_rx7_polarity ), + .pipe_tx7_compliance_i (pipe_tx7_compliance ), + .pipe_tx7_char_is_k_i (pipe_tx7_char_is_k ), + .pipe_tx7_data_i (pipe_tx7_data ), + .pipe_tx7_elec_idle_i (pipe_tx7_elec_idle ), + .pipe_tx7_powerdown_i (pipe_tx7_powerdown ), + .pipe_rx7_char_is_k_i (pipe_rx7_char_is_k_gt ), + .pipe_rx7_data_i (pipe_rx7_data_gt ), + .pipe_rx7_valid_i (pipe_rx7_valid_gt ), + .pipe_rx7_chanisaligned_i (pipe_rx7_chanisaligned_gt), + .pipe_rx7_status_i (pipe_rx7_status_gt ), + .pipe_rx7_phy_status_i (pipe_rx7_phy_status_gt ), + .pipe_rx7_elec_idle_o (pipe_rx7_elec_idle ), + .pipe_rx7_polarity_o (pipe_rx7_polarity_gt ), + .pipe_tx7_compliance_o (pipe_tx7_compliance_gt ), + .pipe_tx7_char_is_k_o (pipe_tx7_char_is_k_gt ), + .pipe_tx7_data_o (pipe_tx7_data_gt ), + .pipe_tx7_elec_idle_o (pipe_tx7_elec_idle_gt ), + .pipe_tx7_powerdown_o (pipe_tx7_powerdown_gt ), + + // Non PIPE signals + .pipe_clk (pipe_clk ), + .rst_n (phy_rdy_n ) + ); + + + +endmodule + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_drp.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_drp.v new file mode 100644 index 0000000..d81e272 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_drp.v @@ -0,0 +1,782 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pipe_drp.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : pipe_drp.v +// Description : PIPE DRP Module for 7 Series Transceiver +// Version : 20.0 +//------------------------------------------------------------------------------ + + + +`timescale 1ns / 1ps + + + +//---------- PIPE DRP Module --------------------------------------------------- +module pcie_7x_0_pipe_drp # +( + + parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device + parameter PCIE_USE_MODE = "3.0", // PCIe use mode + parameter PCIE_ASYNC_EN = "FALSE", // PCIe async mode + parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only + parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR Gen3 enable + parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only + parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only + parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode + parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode + parameter LOAD_CNT_MAX = 2'd1, // Load max count + parameter INDEX_MAX = 5'd21 // Index max count + +) + +( + + //---------- Input ------------------------------------- + input DRP_CLK, + input DRP_RST_N, + input DRP_GTXRESET, + input [ 1:0] DRP_RATE, + input DRP_X16X20_MODE, + input DRP_X16, + input DRP_START, + input [15:0] DRP_DO, + input DRP_RDY, + + //---------- Output ------------------------------------ + output [ 8:0] DRP_ADDR, + output DRP_EN, + output [15:0] DRP_DI, + output DRP_WE, + output DRP_DONE, + output [ 2:0] DRP_FSM + +); + + //---------- Input Registers --------------------------- +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2; + + //---------- Internal Signals -------------------------- + reg [ 1:0] load_cnt = 2'd0; + reg [ 4:0] index = 5'd0; + reg mode = 1'd0; + reg [ 8:0] addr_reg = 9'd0; + reg [15:0] di_reg = 16'd0; + + //---------- Output Registers -------------------------- + reg done = 1'd0; + reg [ 2:0] fsm = 0; + + //---------- DRP Address ------------------------------- + // DRP access for *RXCDR_EIDLE includes + // - [11] RXCDR_HOLD_DURING_EIDLE + // - [12] RXCDR_FR_RESET_ON_EIDLE + // - [13] RXCDR_PH_RESET_ON_EIDLE + //------------------------------------------------------ + localparam ADDR_PCS_RSVD_ATTR = 9'h06F; + localparam ADDR_TXOUT_DIV = 9'h088; + localparam ADDR_RXOUT_DIV = 9'h088; + localparam ADDR_TX_DATA_WIDTH = 9'h06B; + localparam ADDR_TX_INT_DATAWIDTH = 9'h06B; + localparam ADDR_RX_DATA_WIDTH = 9'h011; + localparam ADDR_RX_INT_DATAWIDTH = 9'h011; + localparam ADDR_TXBUF_EN = 9'h01C; + localparam ADDR_RXBUF_EN = 9'h09D; + localparam ADDR_TX_XCLK_SEL = 9'h059; + localparam ADDR_RX_XCLK_SEL = 9'h059; + localparam ADDR_CLK_CORRECT_USE = 9'h044; + localparam ADDR_TX_DRIVE_MODE = 9'h019; + localparam ADDR_RXCDR_EIDLE = 9'h0A7; + localparam ADDR_RX_DFE_LPM_EIDLE = 9'h01E; + localparam ADDR_PMA_RSV_A = 9'h099; + localparam ADDR_PMA_RSV_B = 9'h09A; + localparam ADDR_RXCDR_CFG_A = 9'h0A8; + localparam ADDR_RXCDR_CFG_B = 9'h0A9; + localparam ADDR_RXCDR_CFG_C = 9'h0AA; + localparam ADDR_RXCDR_CFG_D = 9'h0AB; + localparam ADDR_RXCDR_CFG_E = 9'h0AC; + localparam ADDR_RXCDR_CFG_F = 9'h0AD; // GTH only + + //---------- DRP Mask ---------------------------------- + localparam MASK_PCS_RSVD_ATTR = 16'b1111111111111001; // Unmask bit [ 2: 1] + localparam MASK_TXOUT_DIV = 16'b1111111110001111; // Unmask bit [ 6: 4] + localparam MASK_RXOUT_DIV = 16'b1111111111111000; // Unmask bit [ 2: 0] + localparam MASK_TX_DATA_WIDTH = 16'b1111111111111000; // Unmask bit [ 2: 0] + localparam MASK_TX_INT_DATAWIDTH = 16'b1111111111101111; // Unmask bit [ 4] + localparam MASK_RX_DATA_WIDTH = 16'b1100011111111111; // Unmask bit [13:11] + localparam MASK_X16X20_RX_DATA_WIDTH = 16'b1111011111111111; // Unmask bit [ 11] // for x16 or x20 mode only + localparam MASK_RX_INT_DATAWIDTH = 16'b1011111111111111; // Unmask bit [ 14] + localparam MASK_TXBUF_EN = 16'b1011111111111111; // Unmask bit [ 14] + localparam MASK_RXBUF_EN = 16'b1111111111111101; // Unmask bit [ 1] + localparam MASK_TX_XCLK_SEL = 16'b1111111101111111; // Unmask bit [ 7] + localparam MASK_RX_XCLK_SEL = 16'b1111111110111111; // Unmask bit [ 6] + localparam MASK_CLK_CORRECT_USE = 16'b1011111111111111; // Unmask bit [ 14] + localparam MASK_TX_DRIVE_MODE = 16'b1111111111100000; // Unmask bit [ 4:0] + localparam MASK_RXCDR_EIDLE = 16'b1111011111111111; // Unmask bit [ 11] + localparam MASK_RX_DFE_LPM_EIDLE = 16'b1011111111111111; // Unmask bit [ 14] + localparam MASK_PMA_RSV_A = 16'b0000000000000000; // Unmask bit [15: 0] + localparam MASK_PMA_RSV_B = 16'b0000000000000000; // Unmask bit [15: 0] + localparam MASK_RXCDR_CFG_A = 16'b0000000000000000; // Unmask bit [15: 0] + localparam MASK_RXCDR_CFG_B = 16'b0000000000000000; // Unmask bit [15: 0] + localparam MASK_RXCDR_CFG_C = 16'b0000000000000000; // Unmask bit [15: 0] + localparam MASK_RXCDR_CFG_D = 16'b0000000000000000; // Unmask bit [15: 0] + localparam MASK_RXCDR_CFG_E_GTX = 16'b1111111100000000; // Unmask bit [ 7: 0] + localparam MASK_RXCDR_CFG_E_GTH = 16'b0000000000000000; // Unmask bit [15: 0] + localparam MASK_RXCDR_CFG_F_GTX = 16'b1111111111111111; // Unmask bit [ ] + localparam MASK_RXCDR_CFG_F_GTH = 16'b1111111111111000; // Unmask bit [ 2: 0] + + //---------- DRP Data for PCIe Gen1 and Gen2 ----------- + localparam GEN12_TXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000100000 : 16'b0000000000010000; // Divide by 4 or 2 + localparam GEN12_RXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000010 : 16'b0000000000000001; // Divide by 4 or 2 + localparam GEN12_TX_DATA_WIDTH = 16'b0000000000000011; // 2-byte (16-bit) external data width + localparam GEN12_TX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width + localparam GEN12_RX_DATA_WIDTH = 16'b0001100000000000; // 2-byte (16-bit) external data width + localparam GEN12_RX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width + localparam GEN12_TXBUF_EN = 16'b0100000000000000; // Use TX buffer if PCIE_TXBUF_EN == "TRUE" + localparam GEN12_RXBUF_EN = 16'b0000000000000010; // Use RX buffer + localparam GEN12_TX_XCLK_SEL = 16'b0000000000000000; // Use TXOUT if PCIE_TXBUF_EN == "TRUE" + localparam GEN12_RX_XCLK_SEL = 16'b0000000000000000; // Use RXREC + localparam GEN12_CLK_CORRECT_USE = 16'b0100000000000000; // Use clock correction + localparam GEN12_TX_DRIVE_MODE = 16'b0000000000000001; // Use PIPE Gen1 and Gen2 mode + localparam GEN12_RXCDR_EIDLE = 16'b0000100000000000; // Hold RXCDR during electrical idle + localparam GEN12_RX_DFE_LPM_EIDLE = 16'b0100000000000000; // Hold RX DFE or LPM during electrical idle + localparam GEN12_PMA_RSV_A_GTX = 16'b1000010010000000; // 16'h8480 + localparam GEN12_PMA_RSV_B_GTX = 16'b0000000000000001; // 16'h0001 + localparam GEN12_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008 + localparam GEN12_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000 + //---------- + localparam GEN12_RXCDR_CFG_A_GTX = 16'h0020; // 16'h0020 + localparam GEN12_RXCDR_CFG_B_GTX = 16'h1020; // 16'h1020 + localparam GEN12_RXCDR_CFG_C_GTX = 16'h23FF; // 16'h23FF + localparam GEN12_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync + localparam GEN12_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async + localparam GEN12_RXCDR_CFG_E_GTX = 16'h0003; // 16'h0003 + localparam GEN12_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000 + //---------- + localparam GEN12_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync + localparam GEN12_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async + localparam GEN12_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC208 + localparam GEN12_RXCDR_CFG_C_GTH = 16'h2000; // 16'h2000 + localparam GEN12_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE + localparam GEN12_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0020 + localparam GEN12_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 + + //---------- DRP Data for PCIe Gen3 -------------------- + localparam GEN3_TXOUT_DIV = 16'b0000000000000000; // Divide by 1 + localparam GEN3_RXOUT_DIV = 16'b0000000000000000; // Divide by 1 + localparam GEN3_TX_DATA_WIDTH = 16'b0000000000000100; // 4-byte (32-bit) external data width + localparam GEN3_TX_INT_DATAWIDTH = 16'b0000000000010000; // 4-byte (32-bit) internal data width + localparam GEN3_RX_DATA_WIDTH = 16'b0010000000000000; // 4-byte (32-bit) external data width + localparam GEN3_RX_INT_DATAWIDTH = 16'b0100000000000000; // 4-byte (32-bit) internal data width + localparam GEN3_TXBUF_EN = 16'b0000000000000000; // Bypass TX buffer + localparam GEN3_RXBUF_EN = 16'b0000000000000000; // Bypass RX buffer + localparam GEN3_TX_XCLK_SEL = 16'b0000000010000000; // Use TXUSR + localparam GEN3_RX_XCLK_SEL = 16'b0000000001000000; // Use RXUSR + localparam GEN3_CLK_CORRECT_USE = 16'b0000000000000000; // Bypass clock correction + localparam GEN3_TX_DRIVE_MODE = 16'b0000000000000010; // Use PIPE Gen3 mode + localparam GEN3_RXCDR_EIDLE = 16'b0000000000000000; // Disable Hold RXCDR during electrical idle + localparam GEN3_RX_DFE_LPM_EIDLE = 16'b0000000000000000; // Disable RX DFE or LPM during electrical idle + localparam GEN3_PMA_RSV_A_GTX = 16'b0111000010000000; // 16'h7080 + localparam GEN3_PMA_RSV_B_GTX = 16'b0000000000011110; // 16'h001E + localparam GEN3_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008 + localparam GEN3_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000 + //---------- + localparam GEN3_RXCDR_CFG_A_GTX = 16'h0080; // 16'h0080 + localparam GEN3_RXCDR_CFG_B_GTX = 16'h1010; // 16'h1010 + localparam GEN3_RXCDR_CFG_C_GTX = 16'h0BFF; // 16'h0BFF + localparam GEN3_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync + localparam GEN3_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async + localparam GEN3_RXCDR_CFG_E_GTX = 16'h000B; // 16'h000B + localparam GEN3_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000 + //---------- + //localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync + //localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async + //localparam GEN3_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC848 + //localparam GEN3_RXCDR_CFG_C_GTH = 16'h2000; // 16'h1000 + //localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon + //localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration + //localparam GEN3_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0010 + //localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon + //localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable + //---------- + localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync + localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async + localparam GEN3_RXCDR_CFG_B_GTH = 16'hC848; // 16'hC848 + localparam GEN3_RXCDR_CFG_C_GTH = 16'h1000; // 16'h1000 + localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon + localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration + localparam GEN3_RXCDR_CFG_E_GTH = 16'h0010; // 16'h0010 + localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon + localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable + + //---------- DRP Data for PCIe Gen1, Gen2 and Gen3 ----- + localparam GEN123_PCS_RSVD_ATTR_A = 16'b0000000000000000; // Auto TX and RX sync mode + localparam GEN123_PCS_RSVD_ATTR_M_TX = 16'b0000000000000010; // Manual TX sync mode + localparam GEN123_PCS_RSVD_ATTR_M_RX = 16'b0000000000000100; // Manual RX sync mode + + //---------- DRP Data for x16 -------------------------- + localparam X16_RX_DATAWIDTH = 16'b0000000000000000; // 2-byte (16-bit) internal data width + + //---------- DRP Data for x20 -------------------------- + localparam X20_RX_DATAWIDTH = 16'b0000100000000000; // 2-byte (20-bit) internal data width + + //---------- DRP Data ---------------------------------- + wire [15:0] data_txout_div; + wire [15:0] data_rxout_div; + wire [15:0] data_tx_data_width; + wire [15:0] data_tx_int_datawidth; + wire [15:0] data_rx_data_width; + wire [15:0] data_rx_int_datawidth; + wire [15:0] data_txbuf_en; + wire [15:0] data_rxbuf_en; + wire [15:0] data_tx_xclk_sel; + wire [15:0] data_rx_xclk_sel; + wire [15:0] data_clk_correction_use; + wire [15:0] data_tx_drive_mode; + wire [15:0] data_rxcdr_eidle; + wire [15:0] data_rx_dfe_lpm_eidle; + wire [15:0] data_pma_rsv_a; + wire [15:0] data_pma_rsv_b; + + wire [15:0] data_rxcdr_cfg_a; + wire [15:0] data_rxcdr_cfg_b; + wire [15:0] data_rxcdr_cfg_c; + wire [15:0] data_rxcdr_cfg_d; + wire [15:0] data_rxcdr_cfg_e; + wire [15:0] data_rxcdr_cfg_f; + + wire [15:0] data_pcs_rsvd_attr_a; + wire [15:0] data_pcs_rsvd_attr_m_tx; + wire [15:0] data_pcs_rsvd_attr_m_rx; + wire [15:0] data_pcs_rsvd_attr_m; + + wire [15:0] data_x16x20_rx_datawidth; + + //---------- FSM --------------------------------------- + localparam FSM_IDLE = 0; + localparam FSM_LOAD = 1; + localparam FSM_READ = 2; + localparam FSM_RRDY = 3; + localparam FSM_WRITE = 4; + localparam FSM_WRDY = 5; + localparam FSM_DONE = 6; + + + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge DRP_CLK) +begin + + if (!DRP_RST_N) + begin + //---------- 1st Stage FF -------------------------- + gtxreset_reg1 <= 1'd0; + rate_reg1 <= 2'd0; + x16x20_mode_reg1 <= 1'd0; + x16_reg1 <= 1'd0; + do_reg1 <= 16'd0; + rdy_reg1 <= 1'd0; + start_reg1 <= 1'd0; + //---------- 2nd Stage FF -------------------------- + gtxreset_reg2 <= 1'd0; + rate_reg2 <= 2'd0; + x16x20_mode_reg2 <= 1'd0; + x16_reg2 <= 1'd0; + do_reg2 <= 16'd0; + rdy_reg2 <= 1'd0; + start_reg2 <= 1'd0; + end + + else + begin + //---------- 1st Stage FF -------------------------- + gtxreset_reg1 <= DRP_GTXRESET; + rate_reg1 <= DRP_RATE; + x16x20_mode_reg1 <= DRP_X16X20_MODE; + x16_reg1 <= DRP_X16; + do_reg1 <= DRP_DO; + rdy_reg1 <= DRP_RDY; + start_reg1 <= DRP_START; + //---------- 2nd Stage FF -------------------------- + gtxreset_reg2 <= gtxreset_reg1; + rate_reg2 <= rate_reg1; + x16x20_mode_reg2 <= x16x20_mode_reg1; + x16_reg2 <= x16_reg1; + do_reg2 <= do_reg1; + rdy_reg2 <= rdy_reg1; + start_reg2 <= start_reg1; + end + +end + + + +//---------- Select DRP Data --------------------------------------------------- +assign data_txout_div = (rate_reg2 == 2'd2) ? GEN3_TXOUT_DIV : GEN12_TXOUT_DIV; +assign data_rxout_div = (rate_reg2 == 2'd2) ? GEN3_RXOUT_DIV : GEN12_RXOUT_DIV; +assign data_tx_data_width = (rate_reg2 == 2'd2) ? GEN3_TX_DATA_WIDTH : GEN12_TX_DATA_WIDTH; +assign data_tx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_TX_INT_DATAWIDTH : GEN12_TX_INT_DATAWIDTH; +assign data_rx_data_width = (rate_reg2 == 2'd2) ? GEN3_RX_DATA_WIDTH : GEN12_RX_DATA_WIDTH; + +assign data_rx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_RX_INT_DATAWIDTH : GEN12_RX_INT_DATAWIDTH; + +assign data_txbuf_en = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TXBUF_EN : GEN12_TXBUF_EN; +assign data_rxbuf_en = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RXBUF_EN : GEN12_RXBUF_EN; +assign data_tx_xclk_sel = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TX_XCLK_SEL : GEN12_TX_XCLK_SEL; +assign data_rx_xclk_sel = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RX_XCLK_SEL : GEN12_RX_XCLK_SEL; +assign data_clk_correction_use = (rate_reg2 == 2'd2) ? GEN3_CLK_CORRECT_USE : GEN12_CLK_CORRECT_USE; +assign data_tx_drive_mode = (rate_reg2 == 2'd2) ? GEN3_TX_DRIVE_MODE : GEN12_TX_DRIVE_MODE; +assign data_rxcdr_eidle = (rate_reg2 == 2'd2) ? GEN3_RXCDR_EIDLE : GEN12_RXCDR_EIDLE; +assign data_rx_dfe_lpm_eidle = (rate_reg2 == 2'd2) ? GEN3_RX_DFE_LPM_EIDLE : GEN12_RX_DFE_LPM_EIDLE; +assign data_pma_rsv_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_A_GTH : GEN3_PMA_RSV_A_GTX) : + ((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_A_GTH : GEN12_PMA_RSV_A_GTX); +assign data_pma_rsv_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_B_GTH : GEN3_PMA_RSV_B_GTX) : + ((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_B_GTH : GEN12_PMA_RSV_B_GTX); + +assign data_rxcdr_cfg_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_A_GTH_A : GEN3_RXCDR_CFG_A_GTH_S) : GEN3_RXCDR_CFG_A_GTX) : + ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN12_RXCDR_CFG_A_GTH_A : GEN12_RXCDR_CFG_A_GTH_S) : GEN12_RXCDR_CFG_A_GTX); + +assign data_rxcdr_cfg_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_B_GTH : GEN3_RXCDR_CFG_B_GTX) : + ((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_B_GTH : GEN12_RXCDR_CFG_B_GTX); + +assign data_rxcdr_cfg_c = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_C_GTH : GEN3_RXCDR_CFG_C_GTX) : + ((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_C_GTH : GEN12_RXCDR_CFG_C_GTX); + +assign data_rxcdr_cfg_d = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTH_AUX : GEN3_RXCDR_CFG_D_GTH) : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S)) : + ((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_D_GTH : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S)); + +assign data_rxcdr_cfg_e = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_E_GTH : GEN3_RXCDR_CFG_E_GTX) : + ((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_E_GTH : GEN12_RXCDR_CFG_E_GTX); + +assign data_rxcdr_cfg_f = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_F_GTH_AUX : GEN3_RXCDR_CFG_F_GTH) : GEN3_RXCDR_CFG_F_GTX) : + ((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_F_GTH : GEN12_RXCDR_CFG_F_GTX); + +assign data_pcs_rsvd_attr_a = GEN123_PCS_RSVD_ATTR_A; +assign data_pcs_rsvd_attr_m_tx = PCIE_TXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_TX; +assign data_pcs_rsvd_attr_m_rx = PCIE_RXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_RX; +assign data_pcs_rsvd_attr_m = data_pcs_rsvd_attr_m_tx | data_pcs_rsvd_attr_m_rx; + +assign data_x16x20_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH; + + +//---------- Load Counter ------------------------------------------------------ +always @ (posedge DRP_CLK) +begin + + if (!DRP_RST_N) + load_cnt <= 2'd0; + else + + //---------- Increment Load Counter ---------------- + if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX)) + load_cnt <= load_cnt + 2'd1; + + //---------- Hold Load Counter --------------------- + else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX)) + load_cnt <= load_cnt; + + //---------- Reset Load Counter -------------------- + else + load_cnt <= 2'd0; + +end + + + +//---------- Update DRP Address and Data --------------------------------------- +always @ (posedge DRP_CLK) +begin + + if (!DRP_RST_N) + begin + addr_reg <= 9'd0; + di_reg <= 16'd0; + end + else + begin + + case (index) + + //-------------------------------------------------- + 5'd0: + begin + addr_reg <= mode ? ADDR_PCS_RSVD_ATTR : + x16x20_mode_reg2 ? ADDR_RX_DATA_WIDTH : ADDR_TXOUT_DIV; + di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_a) : + x16x20_mode_reg2 ? ((do_reg2 & MASK_X16X20_RX_DATA_WIDTH) | data_x16x20_rx_datawidth) : + ((do_reg2 & MASK_TXOUT_DIV) | data_txout_div); + end + + //-------------------------------------------------- + 5'd1: + begin + addr_reg <= mode ? ADDR_PCS_RSVD_ATTR : ADDR_RXOUT_DIV; + di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_m) : + ((do_reg2 & MASK_RXOUT_DIV) | data_rxout_div); + end + + //-------------------------------------------------- + 5'd2 : + begin + addr_reg <= ADDR_TX_DATA_WIDTH; + di_reg <= (do_reg2 & MASK_TX_DATA_WIDTH) | data_tx_data_width; + end + + //-------------------------------------------------- + 5'd3 : + begin + addr_reg <= ADDR_TX_INT_DATAWIDTH; + di_reg <= (do_reg2 & MASK_TX_INT_DATAWIDTH) | data_tx_int_datawidth; + end + + //-------------------------------------------------- + 5'd4 : + begin + addr_reg <= ADDR_RX_DATA_WIDTH; + di_reg <= (do_reg2 & MASK_RX_DATA_WIDTH) | data_rx_data_width; + end + + //-------------------------------------------------- + 5'd5 : + begin + addr_reg <= ADDR_RX_INT_DATAWIDTH; + di_reg <= (do_reg2 & MASK_RX_INT_DATAWIDTH) | data_rx_int_datawidth; + end + + //-------------------------------------------------- + 5'd6 : + begin + addr_reg <= ADDR_TXBUF_EN; + di_reg <= (do_reg2 & MASK_TXBUF_EN) | data_txbuf_en; + end + + //-------------------------------------------------- + 5'd7 : + begin + addr_reg <= ADDR_RXBUF_EN; + di_reg <= (do_reg2 & MASK_RXBUF_EN) | data_rxbuf_en; + end + + //-------------------------------------------------- + 5'd8 : + begin + addr_reg <= ADDR_TX_XCLK_SEL; + di_reg <= (do_reg2 & MASK_TX_XCLK_SEL) | data_tx_xclk_sel; + end + + //-------------------------------------------------- + 5'd9 : + begin + addr_reg <= ADDR_RX_XCLK_SEL; + di_reg <= (do_reg2 & MASK_RX_XCLK_SEL) | data_rx_xclk_sel; + end + + //-------------------------------------------------- + 5'd10 : + begin + addr_reg <= ADDR_CLK_CORRECT_USE; + di_reg <= (do_reg2 & MASK_CLK_CORRECT_USE) | data_clk_correction_use; + end + + //-------------------------------------------------- + 5'd11 : + begin + addr_reg <= ADDR_TX_DRIVE_MODE; + di_reg <= (do_reg2 & MASK_TX_DRIVE_MODE) | data_tx_drive_mode; + end + + //-------------------------------------------------- + 5'd12 : + begin + addr_reg <= ADDR_RXCDR_EIDLE; + di_reg <= (do_reg2 & MASK_RXCDR_EIDLE) | data_rxcdr_eidle; + end + + //-------------------------------------------------- + 5'd13 : + begin + addr_reg <= ADDR_RX_DFE_LPM_EIDLE; + di_reg <= (do_reg2 & MASK_RX_DFE_LPM_EIDLE) | data_rx_dfe_lpm_eidle; + end + + //-------------------------------------------------- + 5'd14 : + begin + addr_reg <= ADDR_PMA_RSV_A; + di_reg <= (do_reg2 & MASK_PMA_RSV_A) | data_pma_rsv_a; + end + + //-------------------------------------------------- + 5'd15 : + begin + addr_reg <= ADDR_PMA_RSV_B; + di_reg <= (do_reg2 & MASK_PMA_RSV_B) | data_pma_rsv_b; + end + + //-------------------------------------------------- + 5'd16 : + begin + addr_reg <= ADDR_RXCDR_CFG_A; + di_reg <= (do_reg2 & MASK_RXCDR_CFG_A) | data_rxcdr_cfg_a; + end + + //-------------------------------------------------- + 5'd17 : + begin + addr_reg <= ADDR_RXCDR_CFG_B; + di_reg <= (do_reg2 & MASK_RXCDR_CFG_B) | data_rxcdr_cfg_b; + end + + //-------------------------------------------------- + 5'd18 : + begin + addr_reg <= ADDR_RXCDR_CFG_C; + di_reg <= (do_reg2 & MASK_RXCDR_CFG_C) | data_rxcdr_cfg_c; + end + + //-------------------------------------------------- + 5'd19 : + begin + addr_reg <= ADDR_RXCDR_CFG_D; + di_reg <= (do_reg2 & MASK_RXCDR_CFG_D) | data_rxcdr_cfg_d; + end + + //-------------------------------------------------- + 5'd20 : + begin + addr_reg <= ADDR_RXCDR_CFG_E; + di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_E_GTH : MASK_RXCDR_CFG_E_GTX)) | data_rxcdr_cfg_e; + end + + //-------------------------------------------------- + 5'd21 : + begin + addr_reg <= ADDR_RXCDR_CFG_F; + di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_F_GTH : MASK_RXCDR_CFG_F_GTX)) | data_rxcdr_cfg_f; + end + + //-------------------------------------------------- + default : + begin + addr_reg <= 9'd0; + di_reg <= 16'd0; + end + + endcase + + end + +end + + + +//---------- PIPE DRP FSM ------------------------------------------------------ +always @ (posedge DRP_CLK) +begin + + if (!DRP_RST_N) + begin + fsm <= FSM_IDLE; + index <= 5'd0; + mode <= 1'd0; + done <= 1'd0; + end + else + begin + + case (fsm) + + //---------- Idle State ---------------------------- + FSM_IDLE : + + begin + //---------- Reset or Rate Change -------------- + if (start_reg2) + begin + fsm <= FSM_LOAD; + index <= 5'd0; + mode <= 1'd0; + done <= 1'd0; + end + //---------- GTXRESET -------------------------- + else if ((gtxreset_reg2 && !gtxreset_reg1) && ((PCIE_TXSYNC_MODE == 0) || (PCIE_RXSYNC_MODE == 0)) && (PCIE_USE_MODE == "1.0")) + begin + fsm <= FSM_LOAD; + index <= 5'd0; + mode <= 1'd1; + done <= 1'd0; + end + //---------- Idle ------------------------------ + else + begin + fsm <= FSM_IDLE; + index <= 5'd0; + mode <= 1'd0; + done <= 1'd1; + end + end + + //---------- Load DRP Address --------------------- + FSM_LOAD : + + begin + fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD; + index <= index; + mode <= mode; + done <= 1'd0; + end + + //---------- Read DRP ------------------------------ + FSM_READ : + + begin + fsm <= FSM_RRDY; + index <= index; + mode <= mode; + done <= 1'd0; + end + + //---------- Read DRP Ready ------------------------ + FSM_RRDY : + + begin + fsm <= rdy_reg2 ? FSM_WRITE : FSM_RRDY; + index <= index; + mode <= mode; + done <= 1'd0; + end + + + //---------- Write DRP ----------------------------- + FSM_WRITE : + + begin + fsm <= FSM_WRDY; + index <= index; + mode <= mode; + done <= 1'd0; + end + + //---------- Write DRP Ready ----------------------- + FSM_WRDY : + + begin + fsm <= rdy_reg2 ? FSM_DONE : FSM_WRDY; + index <= index; + mode <= mode; + done <= 1'd0; + end + + //---------- DRP Done ------------------------------ + FSM_DONE : + + begin + if ((index == INDEX_MAX) || (mode && (index == 5'd1)) || (x16x20_mode_reg2 && (index == 5'd0))) + begin + fsm <= FSM_IDLE; + index <= 5'd0; + mode <= 1'd0; + done <= 1'd0; + end + else + begin + fsm <= FSM_LOAD; + index <= index + 5'd1; + mode <= mode; + done <= 1'd0; + end + end + + //---------- Default State ------------------------- + default : + + begin + fsm <= FSM_IDLE; + index <= 5'd0; + mode <= 1'd0; + done <= 1'd0; + end + + endcase + + end + +end + + + +//---------- PIPE DRP Output --------------------------------------------------- +assign DRP_ADDR = addr_reg; +assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE); +assign DRP_DI = di_reg; +assign DRP_WE = (fsm == FSM_WRITE); +assign DRP_DONE = done; +assign DRP_FSM = fsm; + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_eq.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_eq.v new file mode 100644 index 0000000..aa8b996 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_eq.v @@ -0,0 +1,830 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pipe_eq.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : pipe_eq.v +// Description : PIPE Equalization Module for 7 Series Transceiver +// Version : 20.1 +//------------------------------------------------------------------------------ + + + +`timescale 1ns / 1ps + + + +//---------- PIPE Equalization Module ------------------------------------------ +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pipe_eq # +( + parameter PCIE_SIM_MODE = "FALSE", + parameter PCIE_GT_DEVICE = "GTX", + parameter PCIE_RXEQ_MODE_GEN3 = 1 +) + +( + + //---------- Input ------------------------------------- + input EQ_CLK, + input EQ_RST_N, + input EQ_GEN3, + + input [ 1:0] EQ_TXEQ_CONTROL, + input [ 3:0] EQ_TXEQ_PRESET, + input [ 3:0] EQ_TXEQ_PRESET_DEFAULT, + input [ 5:0] EQ_TXEQ_DEEMPH_IN, + + input [ 1:0] EQ_RXEQ_CONTROL, + input [ 2:0] EQ_RXEQ_PRESET, + input [ 5:0] EQ_RXEQ_LFFS, + input [ 3:0] EQ_RXEQ_TXPRESET, + input EQ_RXEQ_USER_EN, + input [17:0] EQ_RXEQ_USER_TXCOEFF, + input EQ_RXEQ_USER_MODE, + + + //---------- Output ------------------------------------ + output EQ_TXEQ_DEEMPH, + output [ 4:0] EQ_TXEQ_PRECURSOR, + output [ 6:0] EQ_TXEQ_MAINCURSOR, + output [ 4:0] EQ_TXEQ_POSTCURSOR, + output [17:0] EQ_TXEQ_DEEMPH_OUT, + output EQ_TXEQ_DONE, + output [ 5:0] EQ_TXEQ_FSM, + + output [17:0] EQ_RXEQ_NEW_TXCOEFF, + output EQ_RXEQ_LFFS_SEL, + output EQ_RXEQ_ADAPT_DONE, + output EQ_RXEQ_DONE, + output [ 5:0] EQ_RXEQ_FSM + +); + + //---------- Input Registers --------------------------- +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg2; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg2; + + //---------- Internal Signals -------------------------- + reg [18:0] txeq_preset = 19'd0; + reg txeq_preset_done = 1'd0; + reg [ 1:0] txeq_txcoeff_cnt = 2'd0; + + reg [ 2:0] rxeq_preset = 3'd0; + reg rxeq_preset_valid = 1'd0; + reg [ 3:0] rxeq_txpreset = 4'd0; + reg [17:0] rxeq_txcoeff = 18'd0; + reg [ 2:0] rxeq_cnt = 3'd0; + reg [ 5:0] rxeq_fs = 6'd0; + reg [ 5:0] rxeq_lf = 6'd0; + reg rxeq_new_txcoeff_req = 1'd0; + + //---------- Output Registers -------------------------- + reg [18:0] txeq_txcoeff = 19'd0; + reg txeq_done = 1'd0; + reg [ 5:0] fsm_tx = 6'd0; + + reg [17:0] rxeq_new_txcoeff = 18'd0; + reg rxeq_lffs_sel = 1'd0; + reg rxeq_adapt_done_reg = 1'd0; + reg rxeq_adapt_done = 1'd0; + reg rxeq_done = 1'd0; + reg [ 5:0] fsm_rx = 6'd0; + + //---------- RXEQ Eye Scan Module Output --------------- + wire rxeqscan_lffs_sel; + wire rxeqscan_preset_done; + wire [17:0] rxeqscan_new_txcoeff; + wire rxeqscan_new_txcoeff_done; + wire rxeqscan_adapt_done; + + //---------- FSM --------------------------------------- + localparam FSM_TXEQ_IDLE = 6'b000001; + localparam FSM_TXEQ_PRESET = 6'b000010; + localparam FSM_TXEQ_TXCOEFF = 6'b000100; + localparam FSM_TXEQ_REMAP = 6'b001000; + localparam FSM_TXEQ_QUERY = 6'b010000; + localparam FSM_TXEQ_DONE = 6'b100000; + + localparam FSM_RXEQ_IDLE = 6'b000001; + localparam FSM_RXEQ_PRESET = 6'b000010; + localparam FSM_RXEQ_TXCOEFF = 6'b000100; + localparam FSM_RXEQ_LF = 6'b001000; + localparam FSM_RXEQ_NEW_TXCOEFF_REQ = 6'b010000; + localparam FSM_RXEQ_DONE = 6'b100000; + + //---------- TXEQ Presets Look-up Table ---------------- + // TXPRECURSOR = Coefficient range between 0 and 20 units + // TXMAINCURSOR = Coefficient range between 29 and 80 units + // TXPOSTCURSOR = Coefficient range between 0 and 31 units + //------------------------------------------------------ + // Actual Full Swing (FS) = 80 + // Actual Low Frequency (LF) = 29 + // Advertise Full Swing (FS) = 40 + // Advertise Low Frequency (LF) = 15 + //------------------------------------------------------ + // Pre-emphasis = 20 log [80 - (2 * TXPRECURSOR)] / 80], assuming no de-emphasis + // Main-emphasis = 80 - (TXPRECURSOR + TXPOSTCURSOR) + // De-emphasis = 20 log [80 - (2 * TXPOSTCURSOR)] / 80], assuming no pre-emphasis + //------------------------------------------------------ + // Note: TXMAINCURSOR calculated internally in GT + //------------------------------------------------------ + localparam TXPRECURSOR_00 = 6'd0; // 0.0 dB + localparam TXMAINCURSOR_00 = 7'd60; + localparam TXPOSTCURSOR_00 = 6'd20; // -6.0 +/- 1 dB + + localparam TXPRECURSOR_01 = 6'd0; // 0.0 dB + localparam TXMAINCURSOR_01 = 7'd68; // added 1 to compensate decimal + localparam TXPOSTCURSOR_01 = 6'd13; // -3.5 +/- 1 dB + + localparam TXPRECURSOR_02 = 6'd0; // 0.0 dB + localparam TXMAINCURSOR_02 = 7'd64; + localparam TXPOSTCURSOR_02 = 6'd16; // -4.4 +/- 1.5 dB + + localparam TXPRECURSOR_03 = 6'd0; // 0.0 dB + localparam TXMAINCURSOR_03 = 7'd70; + localparam TXPOSTCURSOR_03 = 6'd10; // -2.5 +/- 1 dB + + localparam TXPRECURSOR_04 = 6'd0; // 0.0 dB + localparam TXMAINCURSOR_04 = 7'd80; + localparam TXPOSTCURSOR_04 = 6'd0; // 0.0 dB + + localparam TXPRECURSOR_05 = 6'd8; // -1.9 +/- 1 dB + localparam TXMAINCURSOR_05 = 7'd72; + localparam TXPOSTCURSOR_05 = 6'd0; // 0.0 dB + + localparam TXPRECURSOR_06 = 6'd10; // -2.5 +/- 1 dB + localparam TXMAINCURSOR_06 = 7'd70; + localparam TXPOSTCURSOR_06 = 6'd0; // 0.0 dB + + localparam TXPRECURSOR_07 = 6'd8; // -3.5 +/- 1 dB + localparam TXMAINCURSOR_07 = 7'd56; + localparam TXPOSTCURSOR_07 = 6'd16; // -6.0 +/- 1 dB + + localparam TXPRECURSOR_08 = 6'd10; // -3.5 +/- 1 dB + localparam TXMAINCURSOR_08 = 7'd60; + localparam TXPOSTCURSOR_08 = 6'd10; // -3.5 +/- 1 dB + + localparam TXPRECURSOR_09 = 6'd13; // -3.5 +/- 1 dB + localparam TXMAINCURSOR_09 = 7'd68; // added 1 to compensate decimal + localparam TXPOSTCURSOR_09 = 6'd0; // 0.0 dB + + localparam TXPRECURSOR_10 = 6'd0; // 0.0 dB + localparam TXMAINCURSOR_10 = 7'd56; // added 1 to compensate decimal + localparam TXPOSTCURSOR_10 = 6'd25; // 9.5 +/- 1 dB, updated for coefficient rules + + + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge EQ_CLK) +begin + + if (!EQ_RST_N) + begin + //---------- 1st Stage FF -------------------------- + gen3_reg1 <= 1'd0; + + txeq_control_reg1 <= 2'd0; + txeq_preset_reg1 <= 4'd0; + txeq_deemph_reg1 <= 6'd1; + + rxeq_control_reg1 <= 2'd0; + rxeq_preset_reg1 <= 3'd0; + rxeq_lffs_reg1 <= 6'd0; + rxeq_txpreset_reg1 <= 4'd0; + rxeq_user_en_reg1 <= 1'd0; + rxeq_user_txcoeff_reg1 <= 18'd0; + rxeq_user_mode_reg1 <= 1'd0; + //---------- 2nd Stage FF -------------------------- + gen3_reg2 <= 1'd0; + + txeq_control_reg2 <= 2'd0; + txeq_preset_reg2 <= 4'd0; + txeq_deemph_reg2 <= 6'd1; + + rxeq_control_reg2 <= 2'd0; + rxeq_preset_reg2 <= 3'd0; + rxeq_lffs_reg2 <= 6'd0; + rxeq_txpreset_reg2 <= 4'd0; + rxeq_user_en_reg2 <= 1'd0; + rxeq_user_txcoeff_reg2 <= 18'd0; + rxeq_user_mode_reg2 <= 1'd0; + end + else + begin + //---------- 1st Stage FF -------------------------- + gen3_reg1 <= EQ_GEN3; + + txeq_control_reg1 <= EQ_TXEQ_CONTROL; + txeq_preset_reg1 <= EQ_TXEQ_PRESET; + txeq_deemph_reg1 <= EQ_TXEQ_DEEMPH_IN; + + rxeq_control_reg1 <= EQ_RXEQ_CONTROL; + rxeq_preset_reg1 <= EQ_RXEQ_PRESET; + rxeq_lffs_reg1 <= EQ_RXEQ_LFFS; + rxeq_txpreset_reg1 <= EQ_RXEQ_TXPRESET; + rxeq_user_en_reg1 <= EQ_RXEQ_USER_EN; + rxeq_user_txcoeff_reg1 <= EQ_RXEQ_USER_TXCOEFF; + rxeq_user_mode_reg1 <= EQ_RXEQ_USER_MODE; + //---------- 2nd Stage FF -------------------------- + gen3_reg2 <= gen3_reg1; + + txeq_control_reg2 <= txeq_control_reg1; + txeq_preset_reg2 <= txeq_preset_reg1; + txeq_deemph_reg2 <= txeq_deemph_reg1; + + rxeq_control_reg2 <= rxeq_control_reg1; + rxeq_preset_reg2 <= rxeq_preset_reg1; + rxeq_lffs_reg2 <= rxeq_lffs_reg1; + rxeq_txpreset_reg2 <= rxeq_txpreset_reg1; + rxeq_user_en_reg2 <= rxeq_user_en_reg1; + rxeq_user_txcoeff_reg2 <= rxeq_user_txcoeff_reg1; + rxeq_user_mode_reg2 <= rxeq_user_mode_reg1; + end + +end + + + +//---------- TXEQ Preset ------------------------------------------------------- +always @ (posedge EQ_CLK) +begin + + if (!EQ_RST_N) + begin + + //---------- Select TXEQ Preset ---------------- + case (EQ_TXEQ_PRESET_DEFAULT) + 4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00}; + 4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01}; + 4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02}; + 4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03}; + 4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04}; + 4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05}; + 4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06}; + 4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07}; + 4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08}; + 4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09}; + 4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10}; + default : txeq_preset <= 19'd4; + endcase + + txeq_preset_done <= 1'd0; + end + else + begin + if (fsm_tx == FSM_TXEQ_PRESET) + begin + + //---------- Select TXEQ Preset ---------------- + case (txeq_preset_reg2) + 4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00}; + 4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01}; + 4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02}; + 4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03}; + 4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04}; + 4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05}; + 4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06}; + 4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07}; + 4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08}; + 4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09}; + 4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10}; + default : txeq_preset <= 19'd4; + endcase + + txeq_preset_done <= 1'd1; + end + else + begin + txeq_preset <= txeq_preset; + txeq_preset_done <= 1'd0; + end + end + +end + + + +//---------- TXEQ FSM ---------------------------------------------------------- +always @ (posedge EQ_CLK) +begin + + if (!EQ_RST_N) + begin + fsm_tx <= FSM_TXEQ_IDLE; + txeq_txcoeff <= 19'd0; + txeq_txcoeff_cnt <= 2'd0; + txeq_done <= 1'd0; + end + else + begin + + case (fsm_tx) + + //---------- Idle State ---------------------------- + FSM_TXEQ_IDLE : + + begin + + case (txeq_control_reg2) + + //---------- Idle ------------------------------ + 2'd0 : + begin + fsm_tx <= FSM_TXEQ_IDLE; + txeq_txcoeff <= txeq_txcoeff; + txeq_txcoeff_cnt <= 2'd0; + txeq_done <= 1'd0; + end + + //---------- Process TXEQ Preset --------------- + 2'd1 : + begin + fsm_tx <= FSM_TXEQ_PRESET; + txeq_txcoeff <= txeq_txcoeff; + txeq_txcoeff_cnt <= 2'd0; + txeq_done <= 1'd0; + end + + //---------- Coefficient ----------------------- + 2'd2 : + begin + fsm_tx <= FSM_TXEQ_TXCOEFF; + txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]}; + txeq_txcoeff_cnt <= 2'd1; + txeq_done <= 1'd0; + end + + //---------- Query ----------------------------- + 2'd3 : + begin + fsm_tx <= FSM_TXEQ_QUERY; + txeq_txcoeff <= txeq_txcoeff; + txeq_txcoeff_cnt <= 2'd0; + txeq_done <= 1'd0; + end + + //---------- Default --------------------------- + default : + begin + fsm_tx <= FSM_TXEQ_IDLE; + txeq_txcoeff <= txeq_txcoeff; + txeq_txcoeff_cnt <= 2'd0; + txeq_done <= 1'd0; + end + + endcase + + end + + //---------- Process TXEQ Preset ------------------- + FSM_TXEQ_PRESET : + + begin + fsm_tx <= (txeq_preset_done ? FSM_TXEQ_DONE : FSM_TXEQ_PRESET); + txeq_txcoeff <= txeq_preset; + txeq_txcoeff_cnt <= 2'd0; + txeq_done <= 1'd0; + end + + //---------- Latch Link Partner TX Coefficient ----- + FSM_TXEQ_TXCOEFF : + + begin + fsm_tx <= ((txeq_txcoeff_cnt == 2'd2) ? FSM_TXEQ_REMAP : FSM_TXEQ_TXCOEFF); + + //---------- Shift in extra bit for TXMAINCURSOR + if (txeq_txcoeff_cnt == 2'd1) + txeq_txcoeff <= {1'd0, txeq_deemph_reg2, txeq_txcoeff[18:7]}; + else + txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]}; + + txeq_txcoeff_cnt <= txeq_txcoeff_cnt + 2'd1; + txeq_done <= 1'd0; + end + + //---------- Remap to GT TX Coefficient ------------ + FSM_TXEQ_REMAP : + + begin + fsm_tx <= FSM_TXEQ_DONE; + txeq_txcoeff <= txeq_txcoeff << 1; // Multiply by 2x + txeq_txcoeff_cnt <= 2'd0; + txeq_done <= 1'd0; + end + + //---------- Query TXEQ Coefficient ---------------- + FSM_TXEQ_QUERY: + + begin + fsm_tx <= FSM_TXEQ_DONE; + txeq_txcoeff <= txeq_txcoeff; + txeq_txcoeff_cnt <= 2'd0; + txeq_done <= 1'd0; + end + + //---------- Done ---------------------------------- + FSM_TXEQ_DONE : + + begin + fsm_tx <= ((txeq_control_reg2 == 2'd0) ? FSM_TXEQ_IDLE : FSM_TXEQ_DONE); + txeq_txcoeff <= txeq_txcoeff; + txeq_txcoeff_cnt <= 2'd0; + txeq_done <= 1'd1; + end + + //---------- Default State ------------------------- + default : + begin + fsm_tx <= FSM_TXEQ_IDLE; + txeq_txcoeff <= 19'd0; + txeq_txcoeff_cnt <= 2'd0; + txeq_done <= 1'd0; + end + + endcase + + end + +end + + + +//---------- RXEQ FSM ---------------------------------------------------------- +always @ (posedge EQ_CLK) +begin + + if (!EQ_RST_N) + begin + fsm_rx <= FSM_RXEQ_IDLE; + rxeq_preset <= 3'd0; + rxeq_preset_valid <= 1'd0; + rxeq_txpreset <= 4'd0; + rxeq_txcoeff <= 18'd0; + rxeq_cnt <= 3'd0; + rxeq_fs <= 6'd0; + rxeq_lf <= 6'd0; + rxeq_new_txcoeff_req <= 1'd0; + rxeq_new_txcoeff <= 18'd0; + rxeq_lffs_sel <= 1'd0; + rxeq_adapt_done_reg <= 1'd0; + rxeq_adapt_done <= 1'd0; + rxeq_done <= 1'd0; + end + else + begin + + case (fsm_rx) + + //---------- Idle State ---------------------------- + FSM_RXEQ_IDLE : + + begin + + case (rxeq_control_reg2) + + //---------- Process RXEQ Preset --------------- + 2'd1 : + begin + fsm_rx <= FSM_RXEQ_PRESET; + rxeq_preset <= rxeq_preset_reg2; + rxeq_preset_valid <= 1'd0; + rxeq_txpreset <= rxeq_txpreset; + rxeq_txcoeff <= rxeq_txcoeff; + rxeq_cnt <= 3'd0; + rxeq_fs <= rxeq_fs; + rxeq_lf <= rxeq_lf; + rxeq_new_txcoeff_req <= 1'd0; + rxeq_new_txcoeff <= rxeq_new_txcoeff; + rxeq_lffs_sel <= 1'd0; + rxeq_adapt_done_reg <= 1'd0; + rxeq_adapt_done <= 1'd0; + rxeq_done <= 1'd0; + end + + //---------- Request New TX Coefficient -------- + 2'd2 : + begin + fsm_rx <= FSM_RXEQ_TXCOEFF; + rxeq_preset <= rxeq_preset; + rxeq_preset_valid <= 1'd0; + rxeq_txpreset <= rxeq_txpreset_reg2; + rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]}; + rxeq_cnt <= 3'd1; + rxeq_fs <= rxeq_lffs_reg2; + rxeq_lf <= rxeq_lf; + rxeq_new_txcoeff_req <= 1'd0; + rxeq_new_txcoeff <= rxeq_new_txcoeff; + rxeq_lffs_sel <= 1'd0; + rxeq_adapt_done_reg <= rxeq_adapt_done_reg; + rxeq_adapt_done <= 1'd0; + rxeq_done <= 1'd0; + end + + //---------- Phase2/3 Bypass (reuse logic from rxeq_control = 2 ---- + 2'd3 : + begin + fsm_rx <= FSM_RXEQ_TXCOEFF; + rxeq_preset <= rxeq_preset; + rxeq_preset_valid <= 1'd0; + rxeq_txpreset <= rxeq_txpreset_reg2; + rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]}; + rxeq_cnt <= 3'd1; + rxeq_fs <= rxeq_lffs_reg2; + rxeq_lf <= rxeq_lf; + rxeq_new_txcoeff_req <= 1'd0; + rxeq_new_txcoeff <= rxeq_new_txcoeff; + rxeq_lffs_sel <= 1'd0; + rxeq_adapt_done_reg <= rxeq_adapt_done_reg; + rxeq_adapt_done <= 1'd0; + rxeq_done <= 1'd0; + end + + //---------- Default --------------------------- + default : + begin + fsm_rx <= FSM_RXEQ_IDLE; + rxeq_preset <= rxeq_preset; + rxeq_preset_valid <= 1'd0; + rxeq_txpreset <= rxeq_txpreset; + rxeq_txcoeff <= rxeq_txcoeff; + rxeq_cnt <= 3'd0; + rxeq_fs <= rxeq_fs; + rxeq_lf <= rxeq_lf; + rxeq_new_txcoeff_req <= 1'd0; + rxeq_new_txcoeff <= rxeq_new_txcoeff; + rxeq_lffs_sel <= 1'd0; + rxeq_adapt_done_reg <= rxeq_adapt_done_reg; + rxeq_adapt_done <= 1'd0; + rxeq_done <= 1'd0; + end + + endcase + + end + + //---------- Process RXEQ Preset ------------------- + FSM_RXEQ_PRESET : + + begin + fsm_rx <= (rxeqscan_preset_done ? FSM_RXEQ_DONE : FSM_RXEQ_PRESET); + rxeq_preset <= rxeq_preset_reg2; + rxeq_preset_valid <= 1'd1; + rxeq_txpreset <= rxeq_txpreset; + rxeq_txcoeff <= rxeq_txcoeff; + rxeq_cnt <= 3'd0; + rxeq_fs <= rxeq_fs; + rxeq_lf <= rxeq_lf; + rxeq_new_txcoeff_req <= 1'd0; + rxeq_new_txcoeff <= rxeq_new_txcoeff; + rxeq_lffs_sel <= 1'd0; + rxeq_adapt_done_reg <= rxeq_adapt_done_reg; + rxeq_adapt_done <= 1'd0; + rxeq_done <= 1'd0; + end + + //---------- Shift-in Link Partner TX Coefficient and Preset + FSM_RXEQ_TXCOEFF : + + begin + fsm_rx <= ((rxeq_cnt == 3'd2) ? FSM_RXEQ_LF : FSM_RXEQ_TXCOEFF); + rxeq_preset <= rxeq_preset; + rxeq_preset_valid <= 1'd0; + rxeq_txpreset <= rxeq_txpreset_reg2; + rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]}; + rxeq_cnt <= rxeq_cnt + 2'd1; + rxeq_fs <= rxeq_fs; + rxeq_lf <= rxeq_lf; + rxeq_new_txcoeff_req <= 1'd0; + rxeq_new_txcoeff <= rxeq_new_txcoeff; + rxeq_lffs_sel <= 1'd1; + rxeq_adapt_done_reg <= rxeq_adapt_done_reg; + rxeq_adapt_done <= 1'd0; + rxeq_done <= 1'd0; + end + + //---------- Read Low Frequency (LF) Value --------- + FSM_RXEQ_LF : + begin + fsm_rx <= ((rxeq_cnt == 3'd7) ? FSM_RXEQ_NEW_TXCOEFF_REQ : FSM_RXEQ_LF); + rxeq_preset <= rxeq_preset; + rxeq_preset_valid <= 1'd0; + rxeq_txpreset <= rxeq_txpreset; + rxeq_txcoeff <= rxeq_txcoeff; + rxeq_cnt <= rxeq_cnt + 2'd1; + rxeq_fs <= rxeq_fs; + rxeq_lf <= ((rxeq_cnt == 3'd7) ? rxeq_lffs_reg2 : rxeq_lf); + rxeq_new_txcoeff_req <= 1'd0; + rxeq_new_txcoeff <= rxeq_new_txcoeff; + rxeq_lffs_sel <= 1'd1; + rxeq_adapt_done_reg <= rxeq_adapt_done_reg; + rxeq_adapt_done <= 1'd0; + rxeq_done <= 1'd0; + end + + //---------- Request New TX Coefficient ------------ + FSM_RXEQ_NEW_TXCOEFF_REQ : + + begin + rxeq_preset <= rxeq_preset; + rxeq_preset_valid <= 1'd0; + rxeq_txpreset <= rxeq_txpreset; + rxeq_txcoeff <= rxeq_txcoeff; + rxeq_cnt <= 3'd0; + rxeq_fs <= rxeq_fs; + rxeq_lf <= rxeq_lf; + + if (rxeqscan_new_txcoeff_done) + begin + fsm_rx <= FSM_RXEQ_DONE; + rxeq_new_txcoeff_req <= 1'd0; + rxeq_new_txcoeff <= rxeqscan_lffs_sel ? {14'd0, rxeqscan_new_txcoeff[3:0]} : rxeqscan_new_txcoeff; + rxeq_lffs_sel <= rxeqscan_lffs_sel; + rxeq_adapt_done_reg <= rxeqscan_adapt_done || rxeq_adapt_done_reg; + rxeq_adapt_done <= rxeqscan_adapt_done || rxeq_adapt_done_reg; + rxeq_done <= 1'd1; + end + else + begin + fsm_rx <= FSM_RXEQ_NEW_TXCOEFF_REQ; + rxeq_new_txcoeff_req <= 1'd1; + rxeq_new_txcoeff <= rxeq_new_txcoeff; + rxeq_lffs_sel <= 1'd0; + rxeq_adapt_done_reg <= rxeq_adapt_done_reg; + rxeq_adapt_done <= 1'd0; + rxeq_done <= 1'd0; + end + + end + + //---------- RXEQ Done ----------------------------- + FSM_RXEQ_DONE : + + begin + fsm_rx <= ((rxeq_control_reg2 == 2'd0) ? FSM_RXEQ_IDLE : FSM_RXEQ_DONE); + rxeq_preset <= rxeq_preset; + rxeq_preset_valid <= 1'd0; + rxeq_txpreset <= rxeq_txpreset; + rxeq_txcoeff <= rxeq_txcoeff; + rxeq_cnt <= 3'd0; + rxeq_fs <= rxeq_fs; + rxeq_lf <= rxeq_lf; + rxeq_new_txcoeff_req <= 1'd0; + rxeq_new_txcoeff <= rxeq_new_txcoeff; + rxeq_lffs_sel <= rxeq_lffs_sel; + rxeq_adapt_done_reg <= rxeq_adapt_done_reg; + rxeq_adapt_done <= rxeq_adapt_done; + rxeq_done <= 1'd1; + end + + //---------- Default State ------------------------- + default : + begin + fsm_rx <= FSM_RXEQ_IDLE; + rxeq_preset <= 3'd0; + rxeq_preset_valid <= 1'd0; + rxeq_txpreset <= 4'd0; + rxeq_txcoeff <= 18'd0; + rxeq_cnt <= 3'd0; + rxeq_fs <= 6'd0; + rxeq_lf <= 6'd0; + rxeq_new_txcoeff_req <= 1'd0; + rxeq_new_txcoeff <= 18'd0; + rxeq_lffs_sel <= 1'd0; + rxeq_adapt_done_reg <= 1'd0; + rxeq_adapt_done <= 1'd0; + rxeq_done <= 1'd0; + end + + endcase + + end + +end + + + +//---------- RXEQ Eye Scan Module ---------------------------------------------- +pcie_7x_0_rxeq_scan # +( + .PCIE_SIM_MODE (PCIE_SIM_MODE), + .PCIE_GT_DEVICE (PCIE_GT_DEVICE), + .PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3) +) + +rxeq_scan_i +( + + //---------- Input ------------------------------------- + .RXEQSCAN_CLK (EQ_CLK), + .RXEQSCAN_RST_N (EQ_RST_N), + .RXEQSCAN_CONTROL (rxeq_control_reg2), + .RXEQSCAN_FS (rxeq_fs), + .RXEQSCAN_LF (rxeq_lf), + .RXEQSCAN_PRESET (rxeq_preset), + .RXEQSCAN_PRESET_VALID (rxeq_preset_valid), + .RXEQSCAN_TXPRESET (rxeq_txpreset), + .RXEQSCAN_TXCOEFF (rxeq_txcoeff), + .RXEQSCAN_NEW_TXCOEFF_REQ (rxeq_new_txcoeff_req), + + //---------- Output ------------------------------------ + .RXEQSCAN_PRESET_DONE (rxeqscan_preset_done), + .RXEQSCAN_NEW_TXCOEFF (rxeqscan_new_txcoeff), + .RXEQSCAN_NEW_TXCOEFF_DONE (rxeqscan_new_txcoeff_done), + .RXEQSCAN_LFFS_SEL (rxeqscan_lffs_sel), + .RXEQSCAN_ADAPT_DONE (rxeqscan_adapt_done) + +); + + + +//---------- PIPE EQ Output ---------------------------------------------------- +assign EQ_TXEQ_DEEMPH = txeq_txcoeff[0]; +assign EQ_TXEQ_PRECURSOR = gen3_reg2 ? txeq_txcoeff[ 4: 0] : 5'h00; +assign EQ_TXEQ_MAINCURSOR = gen3_reg2 ? txeq_txcoeff[12: 6] : 7'h00; +assign EQ_TXEQ_POSTCURSOR = gen3_reg2 ? txeq_txcoeff[17:13] : 5'h00; +assign EQ_TXEQ_DEEMPH_OUT = {1'd0, txeq_txcoeff[18:14], txeq_txcoeff[12:7], 1'd0, txeq_txcoeff[5:1]}; // Divide by 2x +assign EQ_TXEQ_DONE = txeq_done; +assign EQ_TXEQ_FSM = fsm_tx; + +assign EQ_RXEQ_NEW_TXCOEFF = rxeq_user_en_reg2 ? rxeq_user_txcoeff_reg2 : rxeq_new_txcoeff; +assign EQ_RXEQ_LFFS_SEL = rxeq_user_en_reg2 ? rxeq_user_mode_reg2 : rxeq_lffs_sel; +assign EQ_RXEQ_ADAPT_DONE = rxeq_adapt_done; +assign EQ_RXEQ_DONE = rxeq_done; +assign EQ_RXEQ_FSM = fsm_rx; + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_rate.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_rate.v new file mode 100644 index 0000000..8c27418 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_rate.v @@ -0,0 +1,1185 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pipe_rate.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : pipe_rate.v +// Description : PIPE Rate Module for 7 Series Transceiver +// Version : 20.1 +//------------------------------------------------------------------------------ + + + +`timescale 1ns / 1ps + + + +//---------- PIPE Rate Module -------------------------------------------------- +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pipe_rate # +( + + parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup + parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device + parameter PCIE_USE_MODE = "3.0", // PCIe use mode + parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only + parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving + parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable + parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only + parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only + parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max + +) + +( + + //---------- Input ------------------------------------- + input RATE_CLK, + input RATE_RST_N, + input RATE_RST_IDLE, + input RATE_ACTIVE_LANE, + input [ 1:0] RATE_RATE_IN, + input RATE_CPLLLOCK, + input RATE_QPLLLOCK, + input RATE_MMCM_LOCK, + input RATE_DRP_DONE, + input RATE_RXPMARESETDONE, + input RATE_TXRESETDONE, + input RATE_RXRESETDONE, + input RATE_TXRATEDONE, + input RATE_RXRATEDONE, + input RATE_PHYSTATUS, + input RATE_RESETOVRD_DONE, + input RATE_TXSYNC_DONE, + input RATE_RXSYNC_DONE, + + //---------- Output ------------------------------------ + output RATE_CPLLPD, + output RATE_QPLLPD, + output RATE_CPLLRESET, + output RATE_QPLLRESET, + output RATE_TXPMARESET, + output RATE_RXPMARESET, + output RATE_DRP_START, + output [ 1:0] RATE_SYSCLKSEL, + output RATE_PCLK_SEL, + output RATE_GEN3, + output RATE_DRP_X16X20_MODE, + output RATE_DRP_X16, + output [ 2:0] RATE_RATE_OUT, + output RATE_RESETOVRD_START, + output RATE_TXSYNC_START, + output RATE_DONE, + output RATE_RXSYNC_START, + output RATE_RXSYNC, + output RATE_IDLE, + output [ 4:0] RATE_FSM + +); + + //---------- Input FF or Buffer ------------------------ +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg2; + + //---------- Internal Signals -------------------------- + wire pll_lock; + wire [ 2:0] rate; + reg [ 3:0] txdata_wait_cnt = 4'd0; + reg txratedone = 1'd0; + reg rxratedone = 1'd0; + reg phystatus = 1'd0; + reg ratedone = 1'd0; + reg gen3_exit = 1'd0; + + //---------- Output FF or Buffer ----------------------- + reg cpllpd = 1'd0; + reg qpllpd = 1'd0; + reg cpllreset = 1'd0; + reg qpllreset = 1'd0; + reg txpmareset = 1'd0; + reg rxpmareset = 1'd0; + reg [ 1:0] sysclksel = (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0; + reg gen3 = 1'd0; + reg pclk_sel = 1'd0; + reg [ 2:0] rate_out = 3'd0; + reg drp_start = 1'd0; + reg drp_x16x20_mode = 1'd0; + reg drp_x16 = 1'd0; + reg [4:0] fsm = 0; + + //---------- FSM --------------------------------------- + localparam FSM_IDLE = 0; + localparam FSM_PLL_PU = 1; // Gen 3 only + localparam FSM_PLL_PURESET = 2; // Gen 3 only + localparam FSM_PLL_LOCK = 3; // Gen 3 or reset only + localparam FSM_DRP_X16_GEN3_START = 4; + localparam FSM_DRP_X16_GEN3_DONE = 5; + localparam FSM_PMARESET_HOLD = 6; // Gen 3 or reset only + localparam FSM_PLL_SEL = 7; // Gen 3 or reset only + localparam FSM_MMCM_LOCK = 8; // Gen 3 or reset only + localparam FSM_DRP_START = 9; // Gen 3 or reset only + localparam FSM_DRP_DONE = 10; // Gen 3 or reset only + localparam FSM_PMARESET_RELEASE = 11; // Gen 3 only + localparam FSM_PMARESET_DONE = 12; // Gen 3 only + localparam FSM_TXDATA_WAIT = 13; + localparam FSM_PCLK_SEL = 14; + localparam FSM_DRP_X16_START = 15; + localparam FSM_DRP_X16_DONE = 16; + localparam FSM_RATE_SEL = 17; + localparam FSM_RXPMARESETDONE = 18; + localparam FSM_DRP_X20_START = 19; + localparam FSM_DRP_X20_DONE = 20; + localparam FSM_RATE_DONE = 21; + localparam FSM_RESETOVRD_START = 22; // PCIe use mode 1.0 only + localparam FSM_RESETOVRD_DONE = 23; // PCIe use mode 1.0 only + localparam FSM_PLL_PDRESET = 24; + localparam FSM_PLL_PD = 25; + localparam FSM_TXSYNC_START = 26; + localparam FSM_TXSYNC_DONE = 27; + localparam FSM_DONE = 28; // Must sync value to pipe_user.v + localparam FSM_RXSYNC_START = 29; // Gen 3 only + localparam FSM_RXSYNC_DONE = 30; // Gen 3 only + + + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge RATE_CLK) +begin + + if (!RATE_RST_N) + begin + //---------- 1st Stage FF -------------------------- + rst_idle_reg1 <= 1'd0; + rate_in_reg1 <= 2'd0; + cplllock_reg1 <= 1'd0; + qplllock_reg1 <= 1'd0; + mmcm_lock_reg1 <= 1'd0; + drp_done_reg1 <= 1'd0; + rxpmaresetdone_reg1 <= 1'd0; + txresetdone_reg1 <= 1'd0; + rxresetdone_reg1 <= 1'd0; + txratedone_reg1 <= 1'd0; + rxratedone_reg1 <= 1'd0; + phystatus_reg1 <= 1'd0; + resetovrd_done_reg1 <= 1'd0; + txsync_done_reg1 <= 1'd0; + rxsync_done_reg1 <= 1'd0; + //---------- 2nd Stage FF -------------------------- + rst_idle_reg2 <= 1'd0; + rate_in_reg2 <= 2'd0; + cplllock_reg2 <= 1'd0; + qplllock_reg2 <= 1'd0; + mmcm_lock_reg2 <= 1'd0; + drp_done_reg2 <= 1'd0; + rxpmaresetdone_reg2 <= 1'd0; + txresetdone_reg2 <= 1'd0; + rxresetdone_reg2 <= 1'd0; + txratedone_reg2 <= 1'd0; + rxratedone_reg2 <= 1'd0; + phystatus_reg2 <= 1'd0; + resetovrd_done_reg2 <= 1'd0; + txsync_done_reg2 <= 1'd0; + rxsync_done_reg2 <= 1'd0; + end + else + begin + //---------- 1st Stage FF -------------------------- + rst_idle_reg1 <= RATE_RST_IDLE; + rate_in_reg1 <= RATE_RATE_IN; + cplllock_reg1 <= RATE_CPLLLOCK; + qplllock_reg1 <= RATE_QPLLLOCK; + mmcm_lock_reg1 <= RATE_MMCM_LOCK; + drp_done_reg1 <= RATE_DRP_DONE; + rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE; + txresetdone_reg1 <= RATE_TXRESETDONE; + rxresetdone_reg1 <= RATE_RXRESETDONE; + txratedone_reg1 <= RATE_TXRATEDONE; + rxratedone_reg1 <= RATE_RXRATEDONE; + phystatus_reg1 <= RATE_PHYSTATUS; + resetovrd_done_reg1 <= RATE_RESETOVRD_DONE; + txsync_done_reg1 <= RATE_TXSYNC_DONE; + rxsync_done_reg1 <= RATE_RXSYNC_DONE; + //---------- 2nd Stage FF -------------------------- + rst_idle_reg2 <= rst_idle_reg1; + rate_in_reg2 <= rate_in_reg1; + cplllock_reg2 <= cplllock_reg1; + qplllock_reg2 <= qplllock_reg1; + mmcm_lock_reg2 <= mmcm_lock_reg1; + drp_done_reg2 <= drp_done_reg1; + rxpmaresetdone_reg2 <= rxpmaresetdone_reg1; + txresetdone_reg2 <= txresetdone_reg1; + rxresetdone_reg2 <= rxresetdone_reg1; + txratedone_reg2 <= txratedone_reg1; + rxratedone_reg2 <= rxratedone_reg1; + phystatus_reg2 <= phystatus_reg1; + resetovrd_done_reg2 <= resetovrd_done_reg1; + txsync_done_reg2 <= txsync_done_reg1; + rxsync_done_reg2 <= rxsync_done_reg1; + end + +end + + + +//---------- Select CPLL or QPLL Lock ------------------------------------------ +// Gen1 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock +// Gen2 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock +// Gen3 : Wait for QPLL lock +//------------------------------------------------------------------------------ +assign pll_lock = (rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL") ? qplllock_reg2 : cplllock_reg2; + + + +//---------- Select Rate ------------------------------------------------------- +// Gen1 : Div 4 using [TX/RX]OUT_DIV = 4 if QPLL is used for Gen1/Gen2, else div 2 using [TX/RX]OUT_DIV = 2 +// Gen2 : Div 2 using [TX/RX]RATE = 3'd2 if QPLL is used for Gen1/Gen2, else div 1 using [TX/RX]RATE = 3'd1 +// Gen3 : Div 1 using [TX/RX]OUT_DIV = 1 +//------------------------------------------------------------------------------ +assign rate = (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "QPLL") ? 3'd2 : + (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "CPLL") ? 3'd1 : 3'd0; + + + +//---------- TXDATA Wait Counter ----------------------------------------------- +always @ (posedge RATE_CLK) +begin + + if (!RATE_RST_N) + txdata_wait_cnt <= 4'd0; + else + + //---------- Increment Wait Counter ---------------- + if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX)) + txdata_wait_cnt <= txdata_wait_cnt + 4'd1; + + //---------- Hold Wait Counter --------------------- + else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX)) + txdata_wait_cnt <= txdata_wait_cnt; + + //---------- Reset Wait Counter -------------------- + else + txdata_wait_cnt <= 4'd0; + +end + + + +//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS ----------------------- +always @ (posedge RATE_CLK) +begin + + if (!RATE_RST_N) + begin + txratedone <= 1'd0; + rxratedone <= 1'd0; + phystatus <= 1'd0; + ratedone <= 1'd0; + end + else + begin + + if (fsm == FSM_RATE_DONE) + + begin + + //---------- Latch TXRATEDONE ------------------ + if (txratedone_reg2) + txratedone <= 1'd1; + else + txratedone <= txratedone; + + //---------- Latch RXRATEDONE ------------------ + if (rxratedone_reg2) + rxratedone <= 1'd1; + else + rxratedone <= rxratedone; + + //---------- Latch PHYSTATUS ------------------- + if (phystatus_reg2) + phystatus <= 1'd1; + else + phystatus <= phystatus; + + //---------- Latch Rate Done ------------------- + if (rxratedone && txratedone && phystatus) + ratedone <= 1'd1; + else + ratedone <= ratedone; + + end + + else + + begin + txratedone <= 1'd0; + rxratedone <= 1'd0; + phystatus <= 1'd0; + ratedone <= 1'd0; + end + + end + +end + + + +//---------- PIPE Rate FSM ----------------------------------------------------- +always @ (posedge RATE_CLK) +begin + + if (!RATE_RST_N) + begin + fsm <= FSM_PLL_LOCK; + gen3_exit <= 1'd0; + cpllpd <= 1'd0; + qpllpd <= 1'd0; + cpllreset <= 1'd0; + qpllreset <= 1'd0; + txpmareset <= 1'd0; + rxpmareset <= 1'd0; + sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0; + pclk_sel <= 1'd0; + gen3 <= 1'd0; + rate_out <= 3'd0; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + else + begin + + case (fsm) + + //---------- Idle State ---------------------------- + FSM_IDLE : + + begin + //---------- Detect Rate Change ---------------- + if (rate_in_reg2 != rate_in_reg1) + begin + fsm <= ((rate_in_reg2 == 2'd2) || (rate_in_reg1 == 2'd2)) ? FSM_PLL_PU : FSM_TXDATA_WAIT; + gen3_exit <= (rate_in_reg2 == 2'd2); + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + else + begin + fsm <= FSM_IDLE; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + end + + //---------- Power-up PLL -------------------------- + FSM_PLL_PU : + + begin + fsm <= FSM_PLL_PURESET; + gen3_exit <= gen3_exit; + cpllpd <= (PCIE_PLL_SEL == "QPLL"); + qpllpd <= 1'd0; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Release PLL Resets -------------------- + FSM_PLL_PURESET : + + begin + fsm <= FSM_PLL_LOCK; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= (PCIE_PLL_SEL == "QPLL"); + qpllreset <= 1'd0; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Wait for PLL Lock --------------------- + FSM_PLL_LOCK : + + begin + fsm <= (pll_lock ? ((!rst_idle_reg2 || (rate_in_reg2 == 2'd1)) ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_START) : FSM_PLL_LOCK); + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Start DRP x16 ------------------------- + FSM_DRP_X16_GEN3_START : + + begin + fsm <= (!drp_done_reg2) ? FSM_DRP_X16_GEN3_DONE : FSM_DRP_X16_GEN3_START; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd1; + drp_x16x20_mode <= 1'd1; + drp_x16 <= 1'd1; + end + + //---------- Wait for DRP x16 Done ----------------- + FSM_DRP_X16_GEN3_DONE : + + begin + fsm <= drp_done_reg2 ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_DONE; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd1; + drp_x16 <= 1'd1; + end + + //---------- Hold both PMA in Reset ---------------- + // Gen1 : Release PMA Reset + // Gen2 : Release PMA Reset + // Gen3 : Hold PMA Reset + //-------------------------------------------------- + FSM_PMARESET_HOLD : + + begin + fsm <= FSM_PLL_SEL; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit); + rxpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit); + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Select PLL ---------------------------- + // Gen1 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL + // Gen2 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL + // Gen3 : QPLL + //-------------------------------------------------- + FSM_PLL_SEL : + + begin + fsm <= FSM_MMCM_LOCK; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= ((rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL")) ? 2'd1 : 2'd0; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Check for MMCM Lock ------------------- + FSM_MMCM_LOCK : + + begin + fsm <= (mmcm_lock_reg2 && !rxpmaresetdone_reg2 ? FSM_DRP_START : FSM_MMCM_LOCK); + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Start DRP ----------------------------- + FSM_DRP_START: + + begin + fsm <= (!drp_done_reg2 ? FSM_DRP_DONE : FSM_DRP_START); + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2)); + gen3 <= (rate_in_reg2 == 2'd2); + rate_out <= (((rate_in_reg2 == 2'd2) || gen3_exit) ? rate : rate_out); + drp_start <= 1'd1; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Wait for DRP Done --------------------- + FSM_DRP_DONE : + + begin + fsm <= ((drp_done_reg2 && pll_lock) ? (rst_idle_reg2 ? FSM_PMARESET_RELEASE : FSM_IDLE): FSM_DRP_DONE); + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Release PMA Resets -------------------- + FSM_PMARESET_RELEASE : + + begin + fsm <= FSM_PMARESET_DONE; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= 1'd0; + rxpmareset <= 1'd0; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Wait for both TX/RX PMA Reset Dones and PHYSTATUS Deassertion + FSM_PMARESET_DONE : + + begin + fsm <= (((rxresetdone_reg2 && txresetdone_reg2 && !phystatus_reg2) || !RATE_ACTIVE_LANE) ? FSM_TXDATA_WAIT : FSM_PMARESET_DONE); + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Wait for TXDATA to TX[P/N] Latency ---- + FSM_TXDATA_WAIT : + + begin + fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Select PCLK Frequency ----------------- + // Gen1 : PCLK = 125 MHz + // Gen2 : PCLK = 250 MHz + // Gen3 : PCLK = 250 MHz + //-------------------------------------------------- + FSM_PCLK_SEL : + + begin + fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_DRP_X16_START : FSM_RATE_SEL; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2)); + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Start DRP x16 ------------------------- + FSM_DRP_X16_START : + + begin + fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd1; + drp_x16x20_mode <= 1'd1; + drp_x16 <= 1'd1; + end + + //---------- Wait for DRP x16 Done ----------------- + FSM_DRP_X16_DONE : + + begin + fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd1; + drp_x16 <= 1'd1; + end + + //---------- Select Rate --------------------------- + FSM_RATE_SEL : + + begin + fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_RXPMARESETDONE : FSM_RATE_DONE; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate; // Update [TX/RX]RATE + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Wait for RXPMARESETDONE De-assertion -- + FSM_RXPMARESETDONE : + + begin + fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Start DRP x20 ------------------------- + FSM_DRP_X20_START : + + begin + fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd1; + drp_x16x20_mode <= 1'd1; + drp_x16 <= 1'd0; + end + + //---------- Wait for DRP x20 Done ----------------- + FSM_DRP_X20_DONE : + + begin + fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd1; + drp_x16 <= 1'd0; + end + + //---------- Wait for Rate Change Done ------------- + FSM_RATE_DONE : + + begin + if (ratedone || (rate_in_reg2 == 2'd2) || (gen3_exit) || !RATE_ACTIVE_LANE) + if ((PCIE_USE_MODE == "1.0") && (rate_in_reg2 != 2'd2) && (!gen3_exit)) + fsm <= FSM_RESETOVRD_START; + else + fsm <= FSM_PLL_PDRESET; + else + fsm <= FSM_RATE_DONE; + + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Reset Override Start ------------------ + FSM_RESETOVRD_START: + + begin + fsm <= (!resetovrd_done_reg2 ? FSM_RESETOVRD_DONE : FSM_RESETOVRD_START); + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Reset Override Done ------------------- + FSM_RESETOVRD_DONE : + + begin + fsm <= (resetovrd_done_reg2 ? FSM_PLL_PDRESET : FSM_RESETOVRD_DONE); + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Hold PLL Not Used in Reset ------------ + FSM_PLL_PDRESET : + + begin + fsm <= FSM_PLL_PD; + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2); + qpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2); + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Power-Down PLL Not Used --------------- + FSM_PLL_PD : + + begin + fsm <= (((rate_in_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? FSM_TXSYNC_START : FSM_DONE); + gen3_exit <= gen3_exit; + cpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2); + qpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2); + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Start TX Sync ------------------------- + FSM_TXSYNC_START: + + begin + fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START); + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Wait for TX Sync Done ----------------- + FSM_TXSYNC_DONE: + + begin + fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE); + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Rate Change Done ---------------------- + FSM_DONE : + + begin + fsm <= (((rate_in_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE") && (PCIE_ASYNC_EN == "TRUE")) ? FSM_RXSYNC_START : FSM_IDLE); + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Start RX Sync ------------------------- + FSM_RXSYNC_START: + + begin + fsm <= (!rxsync_done_reg2 ? FSM_RXSYNC_DONE : FSM_RXSYNC_START); + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Wait for RX Sync Done ----------------- + FSM_RXSYNC_DONE: + + begin + fsm <= (rxsync_done_reg2 ? FSM_IDLE : FSM_RXSYNC_DONE); + gen3_exit <= gen3_exit; + cpllpd <= cpllpd; + qpllpd <= qpllpd; + cpllreset <= cpllreset; + qpllreset <= qpllreset; + txpmareset <= txpmareset; + rxpmareset <= rxpmareset; + sysclksel <= sysclksel; + pclk_sel <= pclk_sel; + gen3 <= gen3; + rate_out <= rate_out; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + //---------- Default State ------------------------- + default : + + begin + fsm <= FSM_IDLE; + gen3_exit <= 1'd0; + cpllpd <= 1'd0; + qpllpd <= 1'd0; + cpllreset <= 1'd0; + qpllreset <= 1'd0; + txpmareset <= 1'd0; + rxpmareset <= 1'd0; + sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0; + pclk_sel <= 1'd0; + gen3 <= 1'd0; + rate_out <= 3'd0; + drp_start <= 1'd0; + drp_x16x20_mode <= 1'd0; + drp_x16 <= 1'd0; + end + + endcase + + end + +end + + + +//---------- PIPE Rate Output -------------------------------------------------- +assign RATE_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd); +assign RATE_QPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd); +assign RATE_CPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllreset); +assign RATE_QPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllreset); +assign RATE_TXPMARESET = txpmareset; +assign RATE_RXPMARESET = rxpmareset; +assign RATE_SYSCLKSEL = sysclksel; + +//assign RATE_DRP_START = (fsm == FSM_DRP_START) || (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START); + assign RATE_DRP_START = drp_start; + +//assign RATE_DRP_X16X20_MODE = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) || +// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) || +// (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE); + assign RATE_DRP_X16X20_MODE = drp_x16x20_mode; + +//assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) || +// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE); + assign RATE_DRP_X16 = drp_x16; + +assign RATE_PCLK_SEL = pclk_sel; +assign RATE_GEN3 = gen3; +assign RATE_RATE_OUT = rate_out; +assign RATE_RESETOVRD_START = (fsm == FSM_RESETOVRD_START); +assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START); +assign RATE_DONE = (fsm == FSM_DONE); +assign RATE_RXSYNC_START = (fsm == FSM_RXSYNC_START); +assign RATE_RXSYNC = ((fsm == FSM_RXSYNC_START) || (fsm == FSM_RXSYNC_DONE)); +assign RATE_IDLE = (fsm == FSM_IDLE); +assign RATE_FSM = fsm; + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_reset.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_reset.v new file mode 100644 index 0000000..4373c33 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_reset.v @@ -0,0 +1,576 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pipe_reset.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : pipe_reset.v +// Description : PIPE Reset Module for 7 Series Transceiver +// Version : 20.2 +//------------------------------------------------------------------------------ + + + +`timescale 1ns / 1ps + + + +//---------- PIPE Reset Module ------------------------------------------------- +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pipe_reset # +( + + //---------- Global ------------------------------------ + parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup + parameter PCIE_GT_DEVICE = "GTX", + parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only + parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving + parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable + parameter PCIE_LANE = 1, // PCIe number of lanes + //---------- Local ------------------------------------- + parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max + parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK + +) + +( + + //---------- Input ------------------------------------- + input RST_CLK, + input RST_RXUSRCLK, + input RST_DCLK, + input RST_RST_N, + input [PCIE_LANE-1:0] RST_DRP_DONE, + input [PCIE_LANE-1:0] RST_RXPMARESETDONE, + input [PCIE_LANE-1:0] RST_CPLLLOCK, + input RST_QPLL_IDLE, + input [PCIE_LANE-1:0] RST_RATE_IDLE, + input [PCIE_LANE-1:0] RST_RXCDRLOCK, + input RST_MMCM_LOCK, + input [PCIE_LANE-1:0] RST_RESETDONE, + input [PCIE_LANE-1:0] RST_PHYSTATUS, + input [PCIE_LANE-1:0] RST_TXSYNC_DONE, + + //---------- Output ------------------------------------ + output RST_CPLLRESET, + output RST_CPLLPD, + output reg RST_DRP_START, + output reg RST_DRP_X16X20_MODE, + output reg RST_DRP_X16, + output RST_RXUSRCLK_RESET, + output RST_DCLK_RESET, + output RST_GTRESET, + output RST_USERRDY, + output RST_TXSYNC_START, + output RST_IDLE, + output [4:0] RST_FSM + +); + + //---------- Input Register ---------------------------- +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2; + + //---------- Internal Signal --------------------------- + reg [ 5:0] cfg_wait_cnt = 6'd0; + + //---------- Output Register --------------------------- + reg cpllreset = 1'd0; + reg cpllpd = 1'd0; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg1 = 1'd0; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg2 = 1'd0; + reg dclk_rst = 1'd0; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg1 = 1'd0; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg2 = 1'd0; + reg gtreset = 1'd0; + reg userrdy = 1'd0; + reg [4:0] fsm = 5'h2; + + //---------- FSM --------------------------------------- + localparam FSM_IDLE = 5'h0; + localparam FSM_CFG_WAIT = 5'h1; + localparam FSM_CPLLRESET = 5'h2; + localparam FSM_DRP_X16_START = 5'h3; + localparam FSM_DRP_X16_DONE = 5'h4; + localparam FSM_CPLLLOCK = 5'h5; + localparam FSM_DRP = 5'h6; + localparam FSM_GTRESET = 5'h7; + localparam FSM_RXPMARESETDONE_1 = 5'h8; + localparam FSM_RXPMARESETDONE_2 = 5'h9; + localparam FSM_DRP_X20_START = 5'hA; + localparam FSM_DRP_X20_DONE = 5'hB; + localparam FSM_MMCM_LOCK = 5'hC; + localparam FSM_RESETDONE = 5'hD; + localparam FSM_CPLL_PD = 5'hE; + localparam FSM_TXSYNC_START = 5'hF; + localparam FSM_TXSYNC_DONE = 5'h10; + + + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge RST_CLK) +begin + + if (!RST_RST_N) + begin + //---------- 1st Stage FF -------------------------- + drp_done_reg1 <= {PCIE_LANE{1'd0}}; + rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}}; + cplllock_reg1 <= {PCIE_LANE{1'd0}}; + qpll_idle_reg1 <= 1'd0; + rate_idle_reg1 <= {PCIE_LANE{1'd0}}; + rxcdrlock_reg1 <= {PCIE_LANE{1'd0}}; + mmcm_lock_reg1 <= 1'd0; + resetdone_reg1 <= {PCIE_LANE{1'd0}}; + phystatus_reg1 <= {PCIE_LANE{1'd0}}; + txsync_done_reg1 <= {PCIE_LANE{1'd0}}; + //---------- 2nd Stage FF -------------------------- + drp_done_reg2 <= {PCIE_LANE{1'd0}}; + rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}}; + cplllock_reg2 <= {PCIE_LANE{1'd0}}; + qpll_idle_reg2 <= 1'd0; + rate_idle_reg2 <= {PCIE_LANE{1'd0}}; + rxcdrlock_reg2 <= {PCIE_LANE{1'd0}}; + mmcm_lock_reg2 <= 1'd0; + resetdone_reg2 <= {PCIE_LANE{1'd0}}; + phystatus_reg2 <= {PCIE_LANE{1'd0}}; + txsync_done_reg2 <= {PCIE_LANE{1'd0}}; + end + else + begin + //---------- 1st Stage FF -------------------------- + drp_done_reg1 <= RST_DRP_DONE; + rxpmaresetdone_reg1 <= RST_RXPMARESETDONE; + cplllock_reg1 <= RST_CPLLLOCK; + qpll_idle_reg1 <= RST_QPLL_IDLE; + rate_idle_reg1 <= RST_RATE_IDLE; + rxcdrlock_reg1 <= RST_RXCDRLOCK; + mmcm_lock_reg1 <= RST_MMCM_LOCK; + resetdone_reg1 <= RST_RESETDONE; + phystatus_reg1 <= RST_PHYSTATUS; + txsync_done_reg1 <= RST_TXSYNC_DONE; + //---------- 2nd Stage FF -------------------------- + drp_done_reg2 <= drp_done_reg1; + rxpmaresetdone_reg2 <= rxpmaresetdone_reg1; + cplllock_reg2 <= cplllock_reg1; + qpll_idle_reg2 <= qpll_idle_reg1; + rate_idle_reg2 <= rate_idle_reg1; + rxcdrlock_reg2 <= rxcdrlock_reg1; + mmcm_lock_reg2 <= mmcm_lock_reg1; + resetdone_reg2 <= resetdone_reg1; + phystatus_reg2 <= phystatus_reg1; + txsync_done_reg2 <= txsync_done_reg1; + end + +end + + + +//---------- Configuration Reset Wait Counter ---------------------------------- +always @ (posedge RST_CLK) +begin + + if (!RST_RST_N) + cfg_wait_cnt <= 6'd0; + else + + //---------- Increment Configuration Reset Wait Counter + if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX)) + cfg_wait_cnt <= cfg_wait_cnt + 6'd1; + + //---------- Hold Configuration Reset Wait Counter - + else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX)) + cfg_wait_cnt <= cfg_wait_cnt; + + //---------- Reset Configuration Reset Wait Counter + else + cfg_wait_cnt <= 6'd0; + +end + + + +//---------- PIPE Reset FSM ---------------------------------------------------- +always @ (posedge RST_CLK) +begin + + if (!RST_RST_N) + begin + fsm <= FSM_CFG_WAIT; + cpllreset <= 1'd0; + cpllpd <= 1'd0; + gtreset <= 1'd0; + userrdy <= 1'd0; + end + else + begin + + case (fsm) + + //---------- Idle State ---------------------------- + FSM_IDLE : + + begin + if (!RST_RST_N) + begin + fsm <= FSM_CFG_WAIT; + cpllreset <= 1'd0; + cpllpd <= 1'd0; + gtreset <= 1'd0; + userrdy <= 1'd0; + end + else + begin + fsm <= FSM_IDLE; + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + end + + //---------- Wait for Configuration Reset Delay --- + FSM_CFG_WAIT : + + begin + fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_CPLLRESET : FSM_CFG_WAIT); + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Hold CPLL and GTX Channel in Reset ---- + FSM_CPLLRESET : + + begin + fsm <= ((&(~cplllock_reg2) && (&(~resetdone_reg2))) ? FSM_CPLLLOCK : FSM_CPLLRESET); + cpllreset <= 1'd1; + cpllpd <= cpllpd; + gtreset <= 1'd1; + userrdy <= userrdy; + end + + //---------- Wait for CPLL Lock -------------------- + FSM_CPLLLOCK : + + begin + fsm <= (&cplllock_reg2 ? FSM_DRP : FSM_CPLLLOCK); + cpllreset <= 1'd0; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Wait for DRP Done to Setup Gen1 ------- + FSM_DRP : + + begin + fsm <= (&rate_idle_reg2 ? ((PCIE_GT_DEVICE == "GTX") ? FSM_GTRESET : FSM_DRP_X16_START) : FSM_DRP); + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Start DRP x16 ------------------------- + FSM_DRP_X16_START : + + begin + fsm <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START; + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Wait for DRP x16 Done ----------------- + FSM_DRP_X16_DONE : + + begin + fsm <= (&drp_done_reg2) ? FSM_GTRESET : FSM_DRP_X16_DONE; + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Release GTX Channel Reset ------------- + FSM_GTRESET : + + begin + fsm <= (PCIE_GT_DEVICE == "GTX") ? FSM_MMCM_LOCK : FSM_RXPMARESETDONE_1; + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= 1'b0; + userrdy <= userrdy; + end + + //---------- Wait for RXPMARESETDONE Assertion ----- + FSM_RXPMARESETDONE_1 : + + begin + fsm <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1; + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Wait for RXPMARESETDONE De-assertion -- + FSM_RXPMARESETDONE_2 : + + begin + fsm <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2; + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Start DRP x20 ------------------------- + FSM_DRP_X20_START : + + begin + fsm <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START; + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Wait for DRP x20 Done ----------------- + FSM_DRP_X20_DONE : + + begin + fsm <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE; + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Wait for MMCM and RX CDR Lock --------- + FSM_MMCM_LOCK : + + begin + if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)) && (qpll_idle_reg2 || (PCIE_PLL_SEL == "CPLL"))) + begin + fsm <= FSM_RESETDONE; + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= 1'd1; + end + else + begin + fsm <= FSM_MMCM_LOCK; + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= 1'd0; + end + end + + //---------- Wait for [TX/RX]RESETDONE and PHYSTATUS + FSM_RESETDONE : + + begin + fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_CPLL_PD : FSM_RESETDONE); + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Power-Down CPLL if QPLL is Used for Gen1/Gen2 + FSM_CPLL_PD : + + begin + fsm <= ((PCIE_TXBUF_EN == "TRUE") ? FSM_IDLE : FSM_TXSYNC_START); + cpllreset <= cpllreset; + cpllpd <= (PCIE_PLL_SEL == "QPLL"); + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Start TX Sync ------------------------- + FSM_TXSYNC_START : + + begin + fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START); + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Wait for TX Sync Done ----------------- + FSM_TXSYNC_DONE : + + begin + fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE); + cpllreset <= cpllreset; + cpllpd <= cpllpd; + gtreset <= gtreset; + userrdy <= userrdy; + end + + //---------- Default State ------------------------- + default : + + begin + fsm <= FSM_CFG_WAIT; + cpllreset <= 1'd0; + cpllpd <= 1'd0; + gtreset <= 1'd0; + userrdy <= 1'd0; + end + + endcase + + end + +end + + + +//---------- RXUSRCLK Reset Synchronizer --------------------------------------- +always @ (posedge RST_RXUSRCLK) +begin + + rxusrclk_rst_reg1 <= cpllreset; + rxusrclk_rst_reg2 <= rxusrclk_rst_reg1; + +end + + + +//---------- DCLK Reset Synchronizer ------------------------------------------- +always @ (posedge RST_CLK) +begin + + if (fsm == FSM_CFG_WAIT) + begin + dclk_rst <= 1'd1; + end + else + begin + dclk_rst <= 1'd0; + end +end + +always @ (posedge RST_DCLK) +begin + + dclk_rst_reg1 <= dclk_rst; + dclk_rst_reg2 <= dclk_rst_reg1; + +end + + + +//---------- PIPE Reset Output ------------------------------------------------- +assign RST_CPLLRESET = cpllreset; +assign RST_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd); +assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2; +assign RST_DCLK_RESET = dclk_rst_reg2; +assign RST_GTRESET = gtreset; +assign RST_USERRDY = userrdy; +assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START); +assign RST_IDLE = (fsm == FSM_IDLE); +assign RST_FSM = fsm; + + + + +//-------------------------------------------------------------------------------------------------- +// Register Output +//-------------------------------------------------------------------------------------------------- +always @ (posedge RST_CLK) +begin + + if (!RST_RST_N) + begin + RST_DRP_START <= 1'd0; + RST_DRP_X16X20_MODE <= 1'd0; + RST_DRP_X16 <= 1'd0; + end + else + begin + RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START); + RST_DRP_X16X20_MODE <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE); + RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE); + end + +end + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_sync.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_sync.v new file mode 100644 index 0000000..3f29364 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_sync.v @@ -0,0 +1,645 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pipe_sync.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : pipe_sync.v +// Description : PIPE Sync Module for 7 Series Transceiver +// Version : 20.1 +//------------------------------------------------------------------------------ +// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default). +// : 1 = Auto TX sync. +// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default). +// : 1 = Auto RX sync. +//------------------------------------------------------------------------------ + + + +`timescale 1ns / 1ps + + + +//---------- PIPE Sync Module -------------------------------------------------- +module pcie_7x_0_pipe_sync # +( + + parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device + parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only + parameter PCIE_RXBUF_EN = "TRUE", // PCIe TX buffer enable for Gen3 only + parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode + parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode + parameter PCIE_LANE = 1, // PCIe lane + parameter PCIE_LINK_SPEED = 3, // PCIe link speed + parameter BYPASS_TXDELAY_ALIGN = 0, // Bypass TX delay align + parameter BYPASS_RXDELAY_ALIGN = 0 // Bypass RX delay align + +) + +( + + //---------- Input ------------------------------------- + input SYNC_CLK, + input SYNC_RST_N, + input SYNC_SLAVE, + input SYNC_GEN3, + input SYNC_RATE_IDLE, + input SYNC_MMCM_LOCK, + input SYNC_RXELECIDLE, + input SYNC_RXCDRLOCK, + input SYNC_ACTIVE_LANE, + + input SYNC_TXSYNC_START, + input SYNC_TXPHINITDONE, + input SYNC_TXDLYSRESETDONE, + input SYNC_TXPHALIGNDONE, + input SYNC_TXSYNCDONE, + + input SYNC_RXSYNC_START, + input SYNC_RXDLYSRESETDONE, + input SYNC_RXPHALIGNDONE_M, + input SYNC_RXPHALIGNDONE_S, + input SYNC_RXSYNC_DONEM_IN, + input SYNC_RXSYNCDONE, + + //---------- Output ------------------------------------ + output SYNC_TXPHDLYRESET, + output SYNC_TXPHALIGN, + output SYNC_TXPHALIGNEN, + output SYNC_TXPHINIT, + output SYNC_TXDLYBYPASS, + output SYNC_TXDLYSRESET, + output SYNC_TXDLYEN, + output SYNC_TXSYNC_DONE, + output [ 5:0] SYNC_FSM_TX, + + output SYNC_RXPHALIGN, + output SYNC_RXPHALIGNEN, + output SYNC_RXDLYBYPASS, + output SYNC_RXDLYSRESET, + output SYNC_RXDLYEN, + output SYNC_RXDDIEN, + output SYNC_RXSYNC_DONEM_OUT, + output SYNC_RXSYNC_DONE, + output [ 6:0] SYNC_FSM_RX + +); + + //---------- Input Register ---------------------------- +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg2; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg3; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg3; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg3; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg3; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg3; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg2; + + //---------- Output Register --------------------------- + reg txdlyen = 1'd0; + reg txsync_done = 1'd0; + reg [ 5:0] fsm_tx = 6'd0; + + reg rxdlyen = 1'd0; + reg rxsync_done = 1'd0; + reg [ 6:0] fsm_rx = 7'd0; + + //---------- FSM --------------------------------------- + localparam FSM_TXSYNC_IDLE = 6'b000001; + localparam FSM_MMCM_LOCK = 6'b000010; + localparam FSM_TXSYNC_START = 6'b000100; + localparam FSM_TXPHINITDONE = 6'b001000; // Manual TX sync only + localparam FSM_TXSYNC_DONE1 = 6'b010000; + localparam FSM_TXSYNC_DONE2 = 6'b100000; + + localparam FSM_RXSYNC_IDLE = 7'b0000001; + localparam FSM_RXCDRLOCK = 7'b0000010; + localparam FSM_RXSYNC_START = 7'b0000100; + localparam FSM_RXSYNC_DONE1 = 7'b0001000; + localparam FSM_RXSYNC_DONE2 = 7'b0010000; + localparam FSM_RXSYNC_DONES = 7'b0100000; + localparam FSM_RXSYNC_DONEM = 7'b1000000; + + + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge SYNC_CLK) +begin + + if (!SYNC_RST_N) + begin + //---------- 1st Stage FF -------------------------- + gen3_reg1 <= 1'd0; + rate_idle_reg1 <= 1'd0; + mmcm_lock_reg1 <= 1'd0; + rxelecidle_reg1 <= 1'd0; + rxcdrlock_reg1 <= 1'd0; + + txsync_start_reg1 <= 1'd0; + txphinitdone_reg1 <= 1'd0; + txdlysresetdone_reg1 <= 1'd0; + txphaligndone_reg1 <= 1'd0; + txsyncdone_reg1 <= 1'd0; + + rxsync_start_reg1 <= 1'd0; + rxdlysresetdone_reg1 <= 1'd0; + rxphaligndone_m_reg1 <= 1'd0; + rxphaligndone_s_reg1 <= 1'd0; + rxsync_donem_reg1 <= 1'd0; + rxsyncdone_reg1 <= 1'd0; + //---------- 2nd Stage FF -------------------------- + gen3_reg2 <= 1'd0; + rate_idle_reg2 <= 1'd0; + mmcm_lock_reg2 <= 1'd0; + rxelecidle_reg2 <= 1'd0; + rxcdrlock_reg2 <= 1'd0; + + txsync_start_reg2 <= 1'd0; + txphinitdone_reg2 <= 1'd0; + txdlysresetdone_reg2 <= 1'd0; + txphaligndone_reg2 <= 1'd0; + txsyncdone_reg2 <= 1'd0; + + rxsync_start_reg2 <= 1'd0; + rxdlysresetdone_reg2 <= 1'd0; + rxphaligndone_m_reg2 <= 1'd0; + rxphaligndone_s_reg2 <= 1'd0; + rxsync_donem_reg2 <= 1'd0; + rxsyncdone_reg2 <= 1'd0; + //---------- 3rd Stage FF -------------------------- + txsync_start_reg3 <= 1'd0; + txphinitdone_reg3 <= 1'd0; + txdlysresetdone_reg3 <= 1'd0; + txphaligndone_reg3 <= 1'd0; + txsyncdone_reg3 <= 1'd0; + + end + else + begin + //---------- 1st Stage FF -------------------------- + gen3_reg1 <= SYNC_GEN3; + rate_idle_reg1 <= SYNC_RATE_IDLE; + mmcm_lock_reg1 <= SYNC_MMCM_LOCK; + rxelecidle_reg1 <= SYNC_RXELECIDLE; + rxcdrlock_reg1 <= SYNC_RXCDRLOCK; + + txsync_start_reg1 <= SYNC_TXSYNC_START; + txphinitdone_reg1 <= SYNC_TXPHINITDONE; + txdlysresetdone_reg1 <= SYNC_TXDLYSRESETDONE; + txphaligndone_reg1 <= SYNC_TXPHALIGNDONE; + txsyncdone_reg1 <= SYNC_TXSYNCDONE; + + rxsync_start_reg1 <= SYNC_RXSYNC_START; + rxdlysresetdone_reg1 <= SYNC_RXDLYSRESETDONE; + rxphaligndone_m_reg1 <= SYNC_RXPHALIGNDONE_M; + rxphaligndone_s_reg1 <= SYNC_RXPHALIGNDONE_S; + rxsync_donem_reg1 <= SYNC_RXSYNC_DONEM_IN; + rxsyncdone_reg1 <= SYNC_RXSYNCDONE; + //---------- 2nd Stage FF -------------------------- + gen3_reg2 <= gen3_reg1; + rate_idle_reg2 <= rate_idle_reg1; + mmcm_lock_reg2 <= mmcm_lock_reg1; + rxelecidle_reg2 <= rxelecidle_reg1; + rxcdrlock_reg2 <= rxcdrlock_reg1; + + txsync_start_reg2 <= txsync_start_reg1; + txphinitdone_reg2 <= txphinitdone_reg1; + txdlysresetdone_reg2 <= txdlysresetdone_reg1; + txphaligndone_reg2 <= txphaligndone_reg1; + txsyncdone_reg2 <= txsyncdone_reg1; + + rxsync_start_reg2 <= rxsync_start_reg1; + rxdlysresetdone_reg2 <= rxdlysresetdone_reg1; + rxphaligndone_m_reg2 <= rxphaligndone_m_reg1; + rxphaligndone_s_reg2 <= rxphaligndone_s_reg1; + rxsync_donem_reg2 <= rxsync_donem_reg1; + rxsyncdone_reg2 <= rxsyncdone_reg1; + //---------- 3rd Stage FF -------------------------- + txsync_start_reg3 <= txsync_start_reg2; + txphinitdone_reg3 <= txphinitdone_reg2; + txdlysresetdone_reg3 <= txdlysresetdone_reg2; + txphaligndone_reg3 <= txphaligndone_reg2; + txsyncdone_reg3 <= txsyncdone_reg2; + end + +end + + + +//---------- Generate TX Sync FSM ---------------------------------------------- +generate if ((PCIE_LINK_SPEED == 3) || (PCIE_TXBUF_EN == "FALSE")) + + begin : txsync_fsm + + //---------- PIPE TX Sync FSM ---------------------------------------------- + always @ (posedge SYNC_CLK) + begin + + if (!SYNC_RST_N) + begin + fsm_tx <= FSM_TXSYNC_IDLE; + txdlyen <= 1'd0; + txsync_done <= 1'd0; + end + else + begin + + case (fsm_tx) + + //---------- Idle State ------------------------ + FSM_TXSYNC_IDLE : + + begin + //---------- Exiting Reset or Rate Change -- + if (txsync_start_reg2) + begin + fsm_tx <= FSM_MMCM_LOCK; + txdlyen <= 1'd0; + txsync_done <= 1'd0; + end + else + begin + fsm_tx <= FSM_TXSYNC_IDLE; + txdlyen <= txdlyen; + txsync_done <= txsync_done; + end + end + + //---------- Check MMCM Lock ------------------- + FSM_MMCM_LOCK : + + begin + fsm_tx <= (mmcm_lock_reg2 ? FSM_TXSYNC_START : FSM_MMCM_LOCK); + txdlyen <= 1'd0; + txsync_done <= 1'd0; + end + + //---------- TX Delay Soft Reset --------------- + FSM_TXSYNC_START : + + begin + fsm_tx <= (((!txdlysresetdone_reg3 && txdlysresetdone_reg2) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START); + txdlyen <= 1'd0; + txsync_done <= 1'd0; + end + + //---------- Wait for TX Phase Init Done (Manual Mode Only) + FSM_TXPHINITDONE : + + begin + fsm_tx <= (((!txphinitdone_reg3 && txphinitdone_reg2) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE); + txdlyen <= 1'd0; + txsync_done <= 1'd0; + end + + //---------- Wait for TX Phase Alignment Done -- + FSM_TXSYNC_DONE1 : + + begin + if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE) + fsm_tx <= ((!txsyncdone_reg3 && txsyncdone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1); + else + fsm_tx <= ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1); + + txdlyen <= 1'd0; + txsync_done <= 1'd0; + end + + //---------- Wait for Master TX Delay Alignment Done + FSM_TXSYNC_DONE2 : + + begin + if ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1)) + begin + fsm_tx <= FSM_TXSYNC_IDLE; + txdlyen <= !SYNC_SLAVE; + txsync_done <= 1'd1; + end + else + begin + fsm_tx <= FSM_TXSYNC_DONE2; + txdlyen <= !SYNC_SLAVE; + txsync_done <= 1'd0; + end + end + + //---------- Default State --------------------- + default : + begin + fsm_tx <= FSM_TXSYNC_IDLE; + txdlyen <= 1'd0; + txsync_done <= 1'd0; + end + + endcase + + end + + end + + end + +//---------- TX Sync FSM Default------------------------------------------------ +else + + begin : txsync_fsm_disable + + //---------- Default ------------------------------------------------------- + always @ (posedge SYNC_CLK) + begin + fsm_tx <= FSM_TXSYNC_IDLE; + txdlyen <= 1'd0; + txsync_done <= 1'd0; + end + + end + +endgenerate + + + +//---------- Generate RX Sync FSM ---------------------------------------------- +generate if ((PCIE_LINK_SPEED == 3) && (PCIE_RXBUF_EN == "FALSE")) + + begin : rxsync_fsm + + //---------- PIPE RX Sync FSM ---------------------------------------------- + always @ (posedge SYNC_CLK) + begin + + if (!SYNC_RST_N) + begin + fsm_rx <= FSM_RXSYNC_IDLE; + rxdlyen <= 1'd0; + rxsync_done <= 1'd0; + end + else + begin + + case (fsm_rx) + + //---------- Idle State ------------------------ + FSM_RXSYNC_IDLE : + + begin + //---------- Exiting Rate Change ----------- + if (rxsync_start_reg2) + begin + fsm_rx <= FSM_RXCDRLOCK; + rxdlyen <= 1'd0; + rxsync_done <= 1'd0; + end + //---------- Exiting Electrical Idle without Rate Change + else if (gen3_reg2 && rate_idle_reg2 && ((rxelecidle_reg2 == 1'd1) && (rxelecidle_reg1 == 1'd0))) + begin + fsm_rx <= FSM_RXCDRLOCK; + rxdlyen <= 1'd0; + rxsync_done <= 1'd0; + end + //---------- Idle -------------------------- + else + begin + fsm_rx <= FSM_RXSYNC_IDLE; + rxdlyen <= rxelecidle_reg2 ? 1'd0 : rxdlyen; + rxsync_done <= rxelecidle_reg2 ? 1'd0 : rxsync_done; + end + end + + //---------- Wait for RX Electrical Idle Exit and RX CDR Lock + FSM_RXCDRLOCK : + + begin + fsm_rx <= ((!rxelecidle_reg2 && rxcdrlock_reg2) ? FSM_RXSYNC_START : FSM_RXCDRLOCK); + rxdlyen <= 1'd0; + rxsync_done <= 1'd0; + end + + //---------- Start RX Sync with RX Delay Soft Reset + FSM_RXSYNC_START : + + begin + fsm_rx <= ((!rxdlysresetdone_reg2 && rxdlysresetdone_reg1) ? FSM_RXSYNC_DONE1 : FSM_RXSYNC_START); + rxdlyen <= 1'd0; + rxsync_done <= 1'd0; + end + + //---------- Wait for RX Phase Alignment Done -- + FSM_RXSYNC_DONE1 : + + begin + if (SYNC_SLAVE) + begin + fsm_rx <= ((!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1); + rxdlyen <= 1'd0; + rxsync_done <= 1'd0; + end + else + begin + fsm_rx <= ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1); + rxdlyen <= 1'd0; + rxsync_done <= 1'd0; + end + end + + //---------- Wait for Master RX Delay Alignment Done + FSM_RXSYNC_DONE2 : + + begin + if (SYNC_SLAVE) + begin + fsm_rx <= FSM_RXSYNC_IDLE; + rxdlyen <= 1'd0; + rxsync_done <= 1'd1; + end + else if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1)) + begin + fsm_rx <= ((PCIE_LANE == 1) ? FSM_RXSYNC_IDLE : FSM_RXSYNC_DONES); + rxdlyen <= (PCIE_LANE == 1); + rxsync_done <= (PCIE_LANE == 1); + end + else + begin + fsm_rx <= FSM_RXSYNC_DONE2; + rxdlyen <= 1'd1; + rxsync_done <= 1'd0; + end + end + + //---------- Wait for Slave RX Phase Alignment Done + FSM_RXSYNC_DONES : + + begin + if (!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) + begin + fsm_rx <= FSM_RXSYNC_DONEM; + rxdlyen <= 1'd1; + rxsync_done <= 1'd0; + end + else + begin + fsm_rx <= FSM_RXSYNC_DONES; + rxdlyen <= 1'd0; + rxsync_done <= 1'd0; + end + end + + //---------- Wait for Master RX Delay Alignment Done + FSM_RXSYNC_DONEM : + + begin + if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1)) + begin + fsm_rx <= FSM_RXSYNC_IDLE; + rxdlyen <= 1'd1; + rxsync_done <= 1'd1; + end + else + begin + fsm_rx <= FSM_RXSYNC_DONEM; + rxdlyen <= 1'd1; + rxsync_done <= 1'd0; + end + end + + //---------- Default State --------------------- + default : + begin + fsm_rx <= FSM_RXSYNC_IDLE; + rxdlyen <= 1'd0; + rxsync_done <= 1'd0; + end + + endcase + + end + + end + + end + +//---------- RX Sync FSM Default ----------------------------------------------- +else + + begin : rxsync_fsm_disable + + //---------- Default ------------------------------------------------------- + always @ (posedge SYNC_CLK) + begin + fsm_rx <= FSM_RXSYNC_IDLE; + rxdlyen <= 1'd0; + rxsync_done <= 1'd0; + end + + end + +endgenerate + + + +//---------- PIPE Sync Output -------------------------------------------------- +assign SYNC_TXPHALIGNEN = ((PCIE_TXSYNC_MODE == 1) || (!gen3_reg2 && (PCIE_TXBUF_EN == "TRUE"))) ? 1'd0 : 1'd1; +assign SYNC_TXDLYBYPASS = 1'd0; +//assign SYNC_TXDLYSRESET = !(((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0; +assign SYNC_TXDLYSRESET = (fsm_tx == FSM_TXSYNC_START); +assign SYNC_TXPHDLYRESET = (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0; +assign SYNC_TXPHINIT = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXPHINITDONE); +assign SYNC_TXPHALIGN = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXSYNC_DONE1); +assign SYNC_TXDLYEN = PCIE_TXSYNC_MODE ? 1'd0 : txdlyen; +assign SYNC_TXSYNC_DONE = txsync_done; +assign SYNC_FSM_TX = fsm_tx; + +assign SYNC_RXPHALIGNEN = ((PCIE_RXSYNC_MODE == 1) || (!gen3_reg2) || (PCIE_RXBUF_EN == "TRUE")) ? 1'd0 : 1'd1; +assign SYNC_RXDLYBYPASS = !gen3_reg2 || (PCIE_RXBUF_EN == "TRUE"); +assign SYNC_RXDLYSRESET = (fsm_rx == FSM_RXSYNC_START); +assign SYNC_RXPHALIGN = PCIE_RXSYNC_MODE ? 1'd0 : (!SYNC_SLAVE ? (fsm_rx == FSM_RXSYNC_DONE1) : (rxsync_donem_reg2 && (fsm_rx == FSM_RXSYNC_DONE1))); +assign SYNC_RXDLYEN = PCIE_RXSYNC_MODE ? 1'd0 : rxdlyen; +assign SYNC_RXDDIEN = gen3_reg2 && (PCIE_RXBUF_EN == "FALSE"); +assign SYNC_RXSYNC_DONE = rxsync_done; +assign SYNC_RXSYNC_DONEM_OUT = (fsm_rx == FSM_RXSYNC_DONES); +assign SYNC_FSM_RX = fsm_rx; + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_user.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_user.v new file mode 100644 index 0000000..17dd2b2 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_user.v @@ -0,0 +1,605 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pipe_user.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : pipe_user.v +// Description : PIPE User Module for 7 Series Transceiver +// Version : 15.3.3 +//------------------------------------------------------------------------------ + + + +`timescale 1ns / 1ps + + + +//---------- PIPE User Module -------------------------------------------------- +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pipe_user # +( + + parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode + parameter PCIE_USE_MODE = "3.0", // PCIe sim version + parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode + parameter RXCDRLOCK_MAX = 4'd15, // RXCDRLOCK max count + parameter RXVALID_MAX = 4'd15, // RXVALID max count + parameter CONVERGE_MAX = 22'd3125000 // Convergence max count + +) + +( + + //---------- Input ------------------------------------- + input USER_TXUSRCLK, + input USER_RXUSRCLK, + input USER_OOBCLK_IN, + input USER_RST_N, + input USER_RXUSRCLK_RST_N, + input USER_PCLK_SEL, + input USER_RESETOVRD_START, + input USER_TXRESETDONE, + input USER_RXRESETDONE, + input USER_TXELECIDLE, + input USER_TXCOMPLIANCE, + input USER_RXCDRLOCK_IN, + input USER_RXVALID_IN, + input USER_RXSTATUS_IN, + input USER_PHYSTATUS_IN, + input USER_RATE_DONE, + input USER_RST_IDLE, + input USER_RATE_RXSYNC, + input USER_RATE_IDLE, + input USER_RATE_GEN3, + input USER_RXEQ_ADAPT_DONE, + + //---------- Output ------------------------------------ + output USER_OOBCLK, + output USER_RESETOVRD, + output USER_TXPMARESET, + output USER_RXPMARESET, + output USER_RXCDRRESET, + output USER_RXCDRFREQRESET, + output USER_RXDFELPMRESET, + output USER_EYESCANRESET, + output USER_TXPCSRESET, + output USER_RXPCSRESET, + output USER_RXBUFRESET, + output USER_RESETOVRD_DONE, + output USER_RESETDONE, + output USER_ACTIVE_LANE, + output USER_RXCDRLOCK_OUT, + output USER_RXVALID_OUT, + output USER_PHYSTATUS_OUT, + output USER_PHYSTATUS_RST, + output USER_GEN3_RDY, + output USER_RX_CONVERGE + +); + + //---------- Input Registers --------------------------- +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg2; + + //---------- Internal Signal --------------------------- + reg [ 7:0] reset_cnt = 8'd127; + reg [ 3:0] rxcdrlock_cnt = 4'd0; + reg [ 3:0] rxvalid_cnt = 4'd0; + reg [21:0] converge_cnt = 22'd0; + reg converge_gen3 = 1'd0; + + //---------- Output Registers -------------------------- + reg oobclk = 1'd0; + reg [ 7:0] reset = 8'h00; + reg gen3_rdy = 1'd0; + reg [ 1:0] fsm = 2'd0; + + //---------- FSM --------------------------------------- + localparam FSM_IDLE = 2'd0; + localparam FSM_RESETOVRD = 2'd1; + localparam FSM_RESET_INIT = 2'd2; + localparam FSM_RESET = 2'd3; + + //---------- Simulation Speedup ------------------------ + localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd100 : CONVERGE_MAX; + + + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge USER_TXUSRCLK) +begin + + if (!USER_RST_N) + begin + //---------- 1st Stage FF -------------------------- + pclk_sel_reg1 <= 1'd0; + resetovrd_start_reg1 <= 1'd0; + txresetdone_reg1 <= 1'd0; + rxresetdone_reg1 <= 1'd0; + txelecidle_reg1 <= 1'd0; + txcompliance_reg1 <= 1'd0; + rxcdrlock_reg1 <= 1'd0; + rxeq_adapt_done_reg1 <= 1'd0; + //---------- 2nd Stage FF -------------------------- + pclk_sel_reg2 <= 1'd0; + resetovrd_start_reg2 <= 1'd0; + txresetdone_reg2 <= 1'd0; + rxresetdone_reg2 <= 1'd0; + txelecidle_reg2 <= 1'd0; + txcompliance_reg2 <= 1'd0; + rxcdrlock_reg2 <= 1'd0; + rxeq_adapt_done_reg2 <= 1'd0; + end + else + begin + //---------- 1st Stage FF -------------------------- + pclk_sel_reg1 <= USER_PCLK_SEL; + resetovrd_start_reg1 <= USER_RESETOVRD_START; + txresetdone_reg1 <= USER_TXRESETDONE; + rxresetdone_reg1 <= USER_RXRESETDONE; + txelecidle_reg1 <= USER_TXELECIDLE; + txcompliance_reg1 <= USER_TXCOMPLIANCE; + rxcdrlock_reg1 <= USER_RXCDRLOCK_IN; + rxeq_adapt_done_reg1 <= USER_RXEQ_ADAPT_DONE; + //---------- 2nd Stage FF -------------------------- + pclk_sel_reg2 <= pclk_sel_reg1; + resetovrd_start_reg2 <= resetovrd_start_reg1; + txresetdone_reg2 <= txresetdone_reg1; + rxresetdone_reg2 <= rxresetdone_reg1; + txelecidle_reg2 <= txelecidle_reg1; + txcompliance_reg2 <= txcompliance_reg1; + rxcdrlock_reg2 <= rxcdrlock_reg1; + rxeq_adapt_done_reg2 <= rxeq_adapt_done_reg1; + end + +end + + + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge USER_RXUSRCLK) +begin + + if (!USER_RXUSRCLK_RST_N) + begin + //---------- 1st Stage FF -------------------------- + rxvalid_reg1 <= 1'd0; + rxstatus_reg1 <= 1'd0; + rst_idle_reg1 <= 1'd0; + rate_done_reg1 <= 1'd0; + rate_rxsync_reg1 <= 1'd0; + rate_idle_reg1 <= 1'd0; + rate_gen3_reg1 <= 1'd0; + //---------- 2nd Stage FF -------------------------- + rxvalid_reg2 <= 1'd0; + rxstatus_reg2 <= 1'd0; + rst_idle_reg2 <= 1'd0; + rate_done_reg2 <= 1'd0; + rate_rxsync_reg2 <= 1'd0; + rate_idle_reg2 <= 1'd0; + rate_gen3_reg2 <= 1'd0; + end + else + begin + //---------- 1st Stage FF -------------------------- + rxvalid_reg1 <= USER_RXVALID_IN; + rxstatus_reg1 <= USER_RXSTATUS_IN; + rst_idle_reg1 <= USER_RST_IDLE; + rate_done_reg1 <= USER_RATE_DONE; + rate_rxsync_reg1 <= USER_RATE_RXSYNC; + rate_idle_reg1 <= USER_RATE_IDLE; + rate_gen3_reg1 <= USER_RATE_GEN3; + //---------- 2nd Stage FF -------------------------- + rxvalid_reg2 <= rxvalid_reg1; + rxstatus_reg2 <= rxstatus_reg1; + rst_idle_reg2 <= rst_idle_reg1; + rate_done_reg2 <= rate_done_reg1; + rate_rxsync_reg2 <= rate_rxsync_reg1; + rate_idle_reg2 <= rate_idle_reg1; + rate_gen3_reg2 <= rate_gen3_reg1; + end + +end + + + +//---------- Generate Reset Override ------------------------------------------- +generate if (PCIE_USE_MODE == "1.0") + + begin : resetovrd + + //---------- Reset Counter ------------------------------------------------- + always @ (posedge USER_TXUSRCLK) + begin + + if (!USER_RST_N) + reset_cnt <= 8'd127; + else + + //---------- Decrement Counter --------------------- + if (((fsm == FSM_RESETOVRD) || (fsm == FSM_RESET)) && (reset_cnt != 8'd0)) + reset_cnt <= reset_cnt - 8'd1; + + //---------- Reset Counter ------------------------- + else + + case (reset) + 8'b00000000 : reset_cnt <= 8'd127; // Programmable PMARESET time + 8'b11111111 : reset_cnt <= 8'd127; // Programmable RXCDRRESET time + 8'b11111110 : reset_cnt <= 8'd127; // Programmable RXCDRFREQRESET time + 8'b11111100 : reset_cnt <= 8'd127; // Programmable RXDFELPMRESET time + 8'b11111000 : reset_cnt <= 8'd127; // Programmable EYESCANRESET time + 8'b11110000 : reset_cnt <= 8'd127; // Programmable PCSRESET time + 8'b11100000 : reset_cnt <= 8'd127; // Programmable RXBUFRESET time + 8'b11000000 : reset_cnt <= 8'd127; // Programmable RESETOVRD deassertion time + 8'b10000000 : reset_cnt <= 8'd127; + default : reset_cnt <= 8'd127; + endcase + + end + + + + //---------- Reset Shift Register ------------------------------------------ + always @ (posedge USER_TXUSRCLK) + begin + + if (!USER_RST_N) + reset <= 8'h00; + else + + //---------- Initialize Reset Register --------- + if (fsm == FSM_RESET_INIT) + reset <= 8'hFF; + //---------- Shift Reset Register -------------- + else if ((fsm == FSM_RESET) && (reset_cnt == 8'd0)) + reset <= {reset[6:0], 1'd0}; + //---------- Hold Reset Register --------------- + else + reset <= reset; + + end + + + + //---------- Reset Override FSM -------------------------------------------- + always @ (posedge USER_TXUSRCLK) + begin + + if (!USER_RST_N) + fsm <= FSM_IDLE; + + else + + begin + + case (fsm) + //---------- Idle State ------------------------ + FSM_IDLE : fsm <= resetovrd_start_reg2 ? FSM_RESETOVRD : FSM_IDLE; + //---------- Assert RESETOVRD ------------------ + FSM_RESETOVRD : fsm <= (reset_cnt == 8'd0) ? FSM_RESET_INIT : FSM_RESETOVRD; + //---------- Initialize Reset ------------------ + FSM_RESET_INIT : fsm <= FSM_RESET; + //---------- Shift Reset ----------------------- + FSM_RESET : fsm <= ((reset == 8'd0) && rxresetdone_reg2) ? FSM_IDLE : FSM_RESET; + //---------- Default State --------------------- + default : fsm <= FSM_IDLE; + endcase + + end + + end + + end + +//---------- Disable Reset Override -------------------------------------------- +else + + begin : resetovrd_disble + + //---------- Generate Default Signals -------------------------------------- + always @ (posedge USER_TXUSRCLK) + begin + + if (!USER_RST_N) + begin + reset_cnt <= 8'hFF; + reset <= 8'd0; + fsm <= 2'd0; + end + else + begin + reset_cnt <= 8'hFF; + reset <= 8'd0; + fsm <= 2'd0; + end + + end + + end + +endgenerate + + + +reg [ 1:0] oobclk_cnt = 2'd0; +//---------- Generate OOB Clock Divider ------------------------ +generate if (PCIE_OOBCLK_MODE == 1) + + begin : oobclk_div + + //---------- OOB Clock Divider ----------------------------- + always @ (posedge USER_OOBCLK_IN) + begin + + if (!USER_RST_N) + begin + oobclk_cnt <= 2'd0; + oobclk <= 1'd0; + end + else + begin + oobclk_cnt <= oobclk_cnt + 2'd1; + oobclk <= pclk_sel_reg2 ? oobclk_cnt[1] : oobclk_cnt[0]; + end + + end + + end + +else + + begin : oobclk_div_disable + + //---------- OOB Clock Default ------------------------- + always @ (posedge USER_OOBCLK_IN) + begin + + if (!USER_RST_N) + begin + oobclk_cnt <= 2'd0; + oobclk <= 1'd0; + end + else + begin + oobclk_cnt <= 2'd0; + oobclk <= 1'd0; + end + + end + + end + +endgenerate + +//---------- RXCDRLOCK Filter -------------------------------------------------- +always @ (posedge USER_TXUSRCLK) +begin + + if (!USER_RST_N) + rxcdrlock_cnt <= 4'd0; + else + + //---------- Increment RXCDRLOCK Counter ----------- + if (rxcdrlock_reg2 && (rxcdrlock_cnt != RXCDRLOCK_MAX)) + rxcdrlock_cnt <= rxcdrlock_cnt + 4'd1; + + //---------- Hold RXCDRLOCK Counter ---------------- + else if (rxcdrlock_reg2 && (rxcdrlock_cnt == RXCDRLOCK_MAX)) + rxcdrlock_cnt <= rxcdrlock_cnt; + + //---------- Reset RXCDRLOCK Counter --------------- + else + rxcdrlock_cnt <= 4'd0; + +end + + + +//---------- RXVALID Filter ---------------------------------------------------- +always @ (posedge USER_RXUSRCLK) +begin + + if (!USER_RXUSRCLK_RST_N) + rxvalid_cnt <= 4'd0; + else + + //---------- Increment RXVALID Counter ------------- + if (rxvalid_reg2 && (rxvalid_cnt != RXVALID_MAX) && (!rxstatus_reg2)) + rxvalid_cnt <= rxvalid_cnt + 4'd1; + + //---------- Hold RXVALID Counter ------------------ + else if (rxvalid_reg2 && (rxvalid_cnt == RXVALID_MAX)) + rxvalid_cnt <= rxvalid_cnt; + + //---------- Reset RXVALID Counter ----------------- + else + rxvalid_cnt <= 4'd0; + +end + + + +//---------- Converge Counter -------------------------------------------------- +always @ (posedge USER_TXUSRCLK) +begin + + if (!USER_RST_N) + converge_cnt <= 22'd0; + else + + //---------- Enter Gen1/Gen2 ----------------------- + if (rst_idle_reg2 && rate_idle_reg2 && !rate_gen3_reg2) + begin + + //---------- Increment Converge Counter -------- + if (converge_cnt < converge_max_cnt) + converge_cnt <= converge_cnt + 22'd1; + //---------- Hold Converge Counter ------------- + else + converge_cnt <= converge_cnt; + + end + + //---------- Reset Converge Counter ---------------- + else + converge_cnt <= 22'd0; + +end + + + +//---------- Converge ---------------------------------------------------------- +always @ (posedge USER_TXUSRCLK) +begin + + if (!USER_RST_N) + converge_gen3 <= 1'd0; + else + + //---------- Enter Gen3 ---------------------------- + if (rate_gen3_reg2) + + //---------- Wait for RX equalization adapt done + if (rxeq_adapt_done_reg2) + converge_gen3 <= 1'd1; + else + converge_gen3 <= converge_gen3; + + //-------- Exit Gen3 ------------------------------- + else + + converge_gen3 <= 1'd0; + + +end + + + +//---------- GEN3_RDY Generator ------------------------------------------------ +always @ (posedge USER_RXUSRCLK) +begin + + if (!USER_RXUSRCLK_RST_N) + gen3_rdy <= 1'd0; + else + gen3_rdy <= rate_idle_reg2 && rate_gen3_reg2; + +end + + + +//---------- PIPE User Override Reset Output ----------------------------------- +assign USER_RESETOVRD = (fsm != FSM_IDLE); +assign USER_TXPMARESET = 1'd0; +assign USER_RXPMARESET = reset[0]; +assign USER_RXCDRRESET = reset[1]; +assign USER_RXCDRFREQRESET = reset[2]; +assign USER_RXDFELPMRESET = reset[3]; +assign USER_EYESCANRESET = reset[4]; +assign USER_TXPCSRESET = 1'd0; +assign USER_RXPCSRESET = reset[5]; +assign USER_RXBUFRESET = reset[6]; +assign USER_RESETOVRD_DONE = (fsm == FSM_IDLE); + +//---------- PIPE User Output -------------------------------------------------- +assign USER_OOBCLK = oobclk; +assign USER_RESETDONE = (txresetdone_reg2 && rxresetdone_reg2); +assign USER_ACTIVE_LANE = !(txelecidle_reg2 && txcompliance_reg2); +//---------------------------------------------------------- +assign USER_RXCDRLOCK_OUT = (USER_RXCDRLOCK_IN && (rxcdrlock_cnt == RXCDRLOCK_MAX)); // Filtered RXCDRLOCK +//---------------------------------------------------------- +assign USER_RXVALID_OUT = ((USER_RXVALID_IN && (rxvalid_cnt == RXVALID_MAX)) && // Filtered RXVALID + rst_idle_reg2 && // Force RXVALID = 0 during reset + rate_idle_reg2); // Force RXVALID = 0 during rate change +//---------------------------------------------------------- +assign USER_PHYSTATUS_OUT = (!rst_idle_reg2 || // Force PHYSTATUS = 1 during reset + ((rate_idle_reg2 || rate_rxsync_reg2) && USER_PHYSTATUS_IN) || // Raw PHYSTATUS + rate_done_reg2); // Gated PHYSTATUS for rate change +//---------------------------------------------------------- +assign USER_PHYSTATUS_RST = !rst_idle_reg2; // Filtered PHYSTATUS for reset +//---------------------------------------------------------- +assign USER_GEN3_RDY = 0;//gen3_rdy; +//---------------------------------------------------------- +assign USER_RX_CONVERGE = (converge_cnt == converge_max_cnt) || converge_gen3; + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_wrapper.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_wrapper.v new file mode 100644 index 0000000..910feb1 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pipe_wrapper.v @@ -0,0 +1,1803 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_pipe_wrapper.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : pipe_wrapper.v +// Description : PIPE Wrapper for 7 Series Transceiver +// Version : 20.2 +//------------------------------------------------------------------------------ + +//---------- PIPE Wrapper Hierarchy -------------------------------------------- +// pipe_wrapper.v +// pipe_clock.v +// pipe_reset.v or gtp_pipe_reset.v +// qpll_reset.v +// * Generate GTXE2_CHANNEL for every lane. +// pipe_user.v +// pipe_rate.v or gtp_pipe_rate.v +// pipe_sync.v +// pipe_drp.v or gtp_pipe_drp.v +// pipe_eq.v +// rxeq_scan.v +// gt_wrapper.v +// GTXE2_CHANNEL or GTHE2_CHANNEL or GTPE2_CHANNEL +// GTXE2_COMMON or GTHE2_COMMON or GTPE2_CHANNEL +// * Generate GTXE2_COMMON for every quad. +// qpll_drp.v +// qpll_wrapper.v +//------------------------------------------------------------------------------ + +//---------- PIPE Wrapper Parameter Encoding ----------------------------------- +// PCIE_SIM_MODE : "FALSE" = Normal mode (default) +// : "TRUE" = Simulation only +// PCIE_SIM_TX_EIDLE_DRIVE_LEVEL : "0", "1" (default), "X" simulation TX electrical idle drive level +// PCIE_GT_DEVICE : "GTX" (default) +// : "GTH" +// : "GTP" +// PCIE_USE_MODE : "1.0" = GTX IES 325T or GTP IES/GES use mode. +// : "1.1" = GTX IES 485T use mode. +// : "2.0" = GTH IES 690T use mode for 1.0 silicon. +// : "2.1" = GTH GES 690T use mode for 1.2 and 2.0 silicon. SW model use "2.0" +// : "3.0" = GTX GES 325T or 485T use mode (default). +// PCIE_PLL_SEL : "CPLL" (default) +// : "QPLL" +// PCIE_AUX_CDR_GEN3_EN : "FALSE" Use Primary CDR for Gen3 only (GTH 2.0) +// : "TRUE" Use AUX CDR for Gen3 only (default) (GTH 2.0) +// PCIE_LPM_DFE : "DFE" for Gen1/Gen2 only (GTX, GTH) +// : "LPM" for Gen1/Gen2 only (default) (GTX, GTH) +// PCIE_LPM_DFE_GEN3 : "DFE" for Gen3 only (GTX, GTH) +// : "LPM" for Gen3 only (default) (GTX, GTH) +// PCIE_EXT_CLK : "FALSE" = Use internal clock module(default) +// : "TRUE" = Use external clock module +// PCIE_POWER_SAVING : "FALSE" = Disable PLL power saving +// : "TRUE" = Enable PLL power saving (default) +// PCIE_ASYNC_EN : "FALSE" = Synchronous mode (default) +// : "TRUE" = Asynchronous mode. +// PCIE_TXBUF_EN : "FALSE" = TX buffer bypass for Gen1/Gen2 only (default) +// : "TRUE" = TX buffer use for Gen1/Gen2 only (for debug only) +// PCIE_RXBUF_EN : "FALSE" = RX buffer bypass for Gen3 only (not supported) +// : "TRUE" = RX buffer use for Gen3 only (default) +// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default) (GTX, GTH) +// : 1 = Auto TX sync (GTH) +// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default) (GTX, GTH) +// : 1 = Auto RX sync (GTH) +// PCIE_CHAN_BOND : 0 = One-Hop (default) +// : 1 = Daisy-Chain +// : 2 = Binary-Tree +// PCIE_CHAN_BOND_EN : "FALSE" = Channel bonding disable for Gen1/Gen2 only +// : "TRUE" = Channel bonding enable for Gen1/Gen2 only +// PCIE_LANE : 1 (default), 2, 4, or 8 +// PCIE_LINK_SPEED : 1 = PCIe Gen1 Mode +// : 2 = PCIe Gen1/Gen2 Mode (default) +// : 3 = PCIe Gen1/Gen2/Gen3 Mode +// PCIE_REFCLK_FREQ : 0 = 100 MHz (default) +// : 1 = 125 MHz +// : 2 = 250 MHz +// PCIE_USERCLK[1/2]_FREQ : 0 = Disable user clock +// : 1 = 31.25 MHz +// : 2 = 62.50 MHz (default) +// : 3 = 125.00 MHz +// : 4 = 250.00 MHz +// : 5 = 500.00 MHz +// PCIE_TX_EIDLE_ASSERT_DELAY : 3'd0 to 3'd7 (default = 3'd4) +// PCIE_RXEQ_MODE_GEN3 : 0 = Return same TX coefficients +// : 1 = Return TX preset #5 +// PCIE_OOBCLK_MODE : 0 = Reference clock +// : 1 = 62.50 MHz (default) +// : 2 = 50.00 MHz (requires 1 BUFG) +// PCIE_JTAG_MODE : 0 = Normal operation (default) +// : 1 = JTAG mode (for debug only) +// PCIE_DEBUG_MODE : 0 = Normal operation (default) +// : 1 = Debug mode (for debug only) +//------------------------------------------------------------------------------ + +//---------- Notes ------------------------------------------------------------- +// Notes within the PIPE Wrapper RTL files are for internal use only. +// Data Width : This PIPE Wrapper supports a 32-bit [TX/RX]DATA interface. +// In Gen1/Gen2 modes, only 16-bits [15:0] are used. +// In Gen3 mode, all 32-bits are used. +//------------------------------------------------------------------------------ + + +`timescale 1ns / 1ps + + +//---------- PIPE Wrapper ------------------------------------------------------ +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_pipe_wrapper # +( + + parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode + parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup + parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level + parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device + parameter PCIE_USE_MODE = "3.0", // PCIe use mode + parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 (GTX/GTH) only + parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR for Gen3 (GTH 2.0) only + parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only + parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only + parameter PCIE_EXT_CLK = "TRUE", // PCIe external clock + parameter PCIE_EXT_GT_COMMON = "FALSE", // PCIe external GT COMMON + parameter EXT_CH_GT_DRP = "FALSE", // PCIe external CH DRP + + parameter TX_MARGIN_FULL_0 = 7'b1001111, // 1000 mV + parameter TX_MARGIN_FULL_1 = 7'b1001110, // 950 mV + parameter TX_MARGIN_FULL_2 = 7'b1001101, // 900 mV + parameter TX_MARGIN_FULL_3 = 7'b1001100, // 850 mV + parameter TX_MARGIN_FULL_4 = 7'b1000011, // 400 mV + parameter TX_MARGIN_LOW_0 = 7'b1000101, // 500 mV + parameter TX_MARGIN_LOW_1 = 7'b1000110 , // 450 mV + parameter TX_MARGIN_LOW_2 = 7'b1000011, // 400 mV + parameter TX_MARGIN_LOW_3 = 7'b1000010 , // 350 mV + parameter TX_MARGIN_LOW_4 = 7'b1000000 , + + parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving + parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable + parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only + parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only + parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode + parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode + parameter PCIE_CHAN_BOND = 0, // PCIe channel bonding mode + parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only + parameter PCIE_LANE = 4, // PCIe number of lanes + parameter PCIE_LINK_SPEED = 2, // PCIe link speed + parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency + parameter PCIE_USERCLK1_FREQ = 4, // PCIe user clock 1 frequency + parameter PCIE_USERCLK2_FREQ = 4, // PCIe user clock 2 frequency + parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd2, // PCIe TX electrical idle assert delay + parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode + parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode + parameter PCIE_JTAG_MODE = 0, // PCIe JTAG mode + parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode + +) + //-------------------------------------- +( // Gen1/Gen2 | Gen3 + //-------------------------------------- + //---------- PIPE Clock & Reset Ports ------------------ + input PIPE_CLK, // Reference clock that drives MMCM + input PIPE_RESET_N, // PCLK | PCLK + + output PIPE_PCLK, // Drives [TX/RX]USRCLK in Gen1/Gen2 + // Drives TXUSRCLK in Gen3 + // Drives RXUSRCLK in Gen3 async mode only + //---------- PIPE TX Data Ports ------------------------ + input [(PCIE_LANE*32)-1:0]PIPE_TXDATA, // PCLK | PCLK + input [(PCIE_LANE*4)-1:0] PIPE_TXDATAK, // PCLK | PCLK + + output [PCIE_LANE-1:0] PIPE_TXP, // Serial data + output [PCIE_LANE-1:0] PIPE_TXN, // Serial data + + //---------- PIPE RX Data Ports ------------------------ + input [PCIE_LANE-1:0] PIPE_RXP, // Serial data + input [PCIE_LANE-1:0] PIPE_RXN, // Serial data + + output [(PCIE_LANE*32)-1:0]PIPE_RXDATA, // PCLK | RXUSRCLK + output [(PCIE_LANE*4)-1:0] PIPE_RXDATAK, // PCLK | RXUSRCLK + + //---------- PIPE Command Ports ------------------------ + input PIPE_TXDETECTRX, // PCLK | PCLK + input [PCIE_LANE-1:0] PIPE_TXELECIDLE, // PCLK | PCLK + input [PCIE_LANE-1:0] PIPE_TXCOMPLIANCE, // PCLK | PCLK + input [PCIE_LANE-1:0] PIPE_RXPOLARITY, // PCLK | RXUSRCLK + input [(PCIE_LANE*2)-1:0] PIPE_POWERDOWN, // PCLK | PCLK + input [ 1:0] PIPE_RATE, // PCLK | PCLK + + //---------- PIPE Electrical Command Ports ------------- + input [ 2:0] PIPE_TXMARGIN, // Async | Async + input PIPE_TXSWING, // Async | Async + input [PCIE_LANE-1:0] PIPE_TXDEEMPH, // Async/PCLK | Async/PCLK + input [(PCIE_LANE*2)-1:0] PIPE_TXEQ_CONTROL, // PCLK | PCLK + input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET, // PCLK | PCLK + input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET_DEFAULT,// PCLK | PCLK + input [(PCIE_LANE*6)-1:0] PIPE_TXEQ_DEEMPH, // PCLK | PCLK + + input [(PCIE_LANE*2)-1:0] PIPE_RXEQ_CONTROL, // PCLK | PCLK + input [(PCIE_LANE*3)-1:0] PIPE_RXEQ_PRESET, // PCLK | PCLK + input [(PCIE_LANE*6)-1:0] PIPE_RXEQ_LFFS, // PCLK | PCLK + input [(PCIE_LANE*4)-1:0] PIPE_RXEQ_TXPRESET, // PCLK | PCLK + input [PCIE_LANE-1:0] PIPE_RXEQ_USER_EN, // PCLK | PCLK + input [(PCIE_LANE*18)-1:0]PIPE_RXEQ_USER_TXCOEFF, // PCLK | PCLK + input [PCIE_LANE-1:0] PIPE_RXEQ_USER_MODE, // PCLK | PCLK + + output [ 5:0] PIPE_TXEQ_FS, // Async | Async + output [ 5:0] PIPE_TXEQ_LF, // Async | Async + output [(PCIE_LANE*18)-1:0]PIPE_TXEQ_COEFF, // PCLK | PCLK + output [PCIE_LANE-1:0] PIPE_TXEQ_DONE, // PCLK | PCLK + + output [(PCIE_LANE*18)-1:0]PIPE_RXEQ_NEW_TXCOEFF, // PCLK | PCLK + output [PCIE_LANE-1:0] PIPE_RXEQ_LFFS_SEL, // PCLK | PCLK + output [PCIE_LANE-1:0] PIPE_RXEQ_ADAPT_DONE, // PCLK | PCLK + output [PCIE_LANE-1:0] PIPE_RXEQ_DONE, // PCLK | PCLK + + //---------- PIPE Status Ports ------------------------- + output [PCIE_LANE-1:0] PIPE_RXVALID, // PCLK | RXUSRCLK + output [PCIE_LANE-1:0] PIPE_PHYSTATUS, // PCLK | RXUSRCLK + output [PCIE_LANE-1:0] PIPE_PHYSTATUS_RST, // PCLK | RXUSRCLK + output [PCIE_LANE-1:0] PIPE_RXELECIDLE, // Async | Async + output [PCIE_LANE-1:0] PIPE_EYESCANDATAERROR, // Async | Async + output [(PCIE_LANE*3)-1:0] PIPE_RXSTATUS, // PCLK | RXUSRCLK + output [PCIE_LANE-1:0] PIPE_RXPMARESETDONE, // Async | Async + output [(PCIE_LANE*3)-1:0] PIPE_RXBUFSTATUS, // PCLK | RXUSRCLK + output [PCIE_LANE-1:0] PIPE_TXPHALIGNDONE, // Async | Async + output [PCIE_LANE-1:0] PIPE_TXPHINITDONE, // Async | Async + output [PCIE_LANE-1:0] PIPE_TXDLYSRESETDONE, // Async | Async + output [PCIE_LANE-1:0] PIPE_RXPHALIGNDONE, // Async | Async + output [PCIE_LANE-1:0] PIPE_RXDLYSRESETDONE, // Async | Async + output [PCIE_LANE-1:0] PIPE_RXSYNCDONE, // PCLK | RXUSRCLK + output [(PCIE_LANE*8)-1:0] PIPE_RXDISPERR, // PCLK | RXUSRCLK + output [(PCIE_LANE*8)-1:0] PIPE_RXNOTINTABLE, // PCLK | RXUSRCLK + output [PCIE_LANE-1:0] PIPE_RXCOMMADET, // PCLK | RXUSRCLK + + //---------- PIPE User Ports --------------------------- + input PIPE_MMCM_RST_N, // Async | Async + input [PCIE_LANE-1:0] PIPE_RXSLIDE, // PCLK | RXUSRCLK + + output [PCIE_LANE-1:0] PIPE_CPLL_LOCK, // Async | Async + output [(PCIE_LANE-1)>>2:0]PIPE_QPLL_LOCK, // Async | Async + output PIPE_PCLK_LOCK, // Async | Async + output [PCIE_LANE-1:0] PIPE_RXCDRLOCK, // Async | Async + output PIPE_USERCLK1, // Optional user clock + output PIPE_USERCLK2, // Optional user clock + output PIPE_RXUSRCLK, // RXUSRCLK + // Equivalent to PCLK in Gen1/Gen2 + // Equivalent to RXOUTCLK[0] in Gen3 + output [PCIE_LANE-1:0] PIPE_RXOUTCLK, // RX recovered clock (for debug only) + output [PCIE_LANE-1:0] PIPE_TXSYNC_DONE, // PCLK | PCLK + output [PCIE_LANE-1:0] PIPE_RXSYNC_DONE, // PCLK | PCLK + output [PCIE_LANE-1:0] PIPE_GEN3_RDY, // PCLK | RXUSRCLK + output [PCIE_LANE-1:0] PIPE_RXCHANISALIGNED, + output [PCIE_LANE-1:0] PIPE_ACTIVE_LANE, + +// Shared Logic Internal + output INT_PCLK_OUT_SLAVE, // PCLK | PCLK + output INT_RXUSRCLK_OUT, // RXUSERCLK + output [PCIE_LANE-1:0 ] INT_RXOUTCLK_OUT, // RX recovered clock + output INT_DCLK_OUT, // DCLK | DCLK + output INT_USERCLK1_OUT, // Optional user clock + output INT_USERCLK2_OUT, // Optional user clock + output INT_OOBCLK_OUT, // OOB | OOB + output INT_MMCM_LOCK_OUT, // Async | Async + output [1:0] INT_QPLLLOCK_OUT, + output [1:0] INT_QPLLOUTCLK_OUT, + output [1:0] INT_QPLLOUTREFCLK_OUT, + input [PCIE_LANE-1:0] INT_PCLK_SEL_SLAVE, + + + // Shared Logic External + + //---------- External Clock Ports ---------------------- + input PIPE_PCLK_IN, // PCLK | PCLK + input PIPE_RXUSRCLK_IN, // RXUSERCLK + // Equivalent to PCLK in Gen1/Gen2 + // Equivalent to RXOUTCLK[0] in Gen3 + input [PCIE_LANE-1:0] PIPE_RXOUTCLK_IN, // RX recovered clock + input PIPE_DCLK_IN, // DCLK | DCLK + input PIPE_USERCLK1_IN, // Optional user clock + input PIPE_USERCLK2_IN, // Optional user clock + input PIPE_OOBCLK_IN, // OOB | OOB + input PIPE_MMCM_LOCK_IN, // Async | Async + + output PIPE_TXOUTCLK_OUT, // PCLK | PCLK + output [PCIE_LANE-1:0] PIPE_RXOUTCLK_OUT, // RX recovered clock (for debug only) + output [PCIE_LANE-1:0] PIPE_PCLK_SEL_OUT, // PCLK | PCLK + output PIPE_GEN3_OUT, // PCLK | PCLK + //---------- External GT COMMON Ports ---------------------- + input [11:0] QPLL_DRP_CRSCODE, + input [17:0] QPLL_DRP_FSM, + input [1:0] QPLL_DRP_DONE, + input [1:0] QPLL_DRP_RESET, + input [1:0] QPLL_QPLLLOCK, + input [1:0] QPLL_QPLLOUTCLK, + input [1:0] QPLL_QPLLOUTREFCLK, + output QPLL_QPLLPD, + output [1:0] QPLL_QPLLRESET, + output QPLL_DRP_CLK, + output QPLL_DRP_RST_N, + output QPLL_DRP_OVRD, + output QPLL_DRP_GEN3, + output QPLL_DRP_START, + + //---------- TRANSCEIVER DEBUG ----------------------- + input [ 2:0] PIPE_TXPRBSSEL, // PCLK | PCLK + input [ 2:0] PIPE_RXPRBSSEL, // PCLK | PCLK + input PIPE_TXPRBSFORCEERR, // PCLK | PCLK + input PIPE_RXPRBSCNTRESET, // PCLK | PCLK + input [ 2:0] PIPE_LOOPBACK, // PCLK | PCLK + + output [PCIE_LANE-1:0] PIPE_RXPRBSERR, // PCLK | PCLK + input [PCIE_LANE-1:0] PIPE_TXINHIBIT, // PCLK | PCLK + + //---------- FSM Ports --------------------------------- + output [4:0] PIPE_RST_FSM, // PCLK | PCLK + output [11:0] PIPE_QRST_FSM, // PCLK | PCLK + output [(PCIE_LANE*5)-1:0] PIPE_RATE_FSM, // PCLK | PCLK + output [(PCIE_LANE*6)-1:0] PIPE_SYNC_FSM_TX, // PCLK | PCLK + output [(PCIE_LANE*7)-1:0] PIPE_SYNC_FSM_RX, // PCLK | PCLK + output [(PCIE_LANE*7)-1:0] PIPE_DRP_FSM, // DCLK | DCLK + output [(PCIE_LANE*6)-1:0] PIPE_TXEQ_FSM, // PCLK | PCLK + output [(PCIE_LANE*6)-1:0] PIPE_RXEQ_FSM, // PCLK | PCLK + output [((((PCIE_LANE-1)>>2)+1)*9)-1:0]PIPE_QDRP_FSM, // DCLK | DCLK + + output PIPE_RST_IDLE, // PCLK | PCLK + output PIPE_QRST_IDLE, // PCLK | PCLK + output PIPE_RATE_IDLE, // PCLK | PCLK + + //----------- Channel DRP---------------------------- + output EXT_CH_GT_DRPCLK, + input [(PCIE_LANE*9)-1:0] EXT_CH_GT_DRPADDR, + input [PCIE_LANE-1:0] EXT_CH_GT_DRPEN, + input [(PCIE_LANE*16)-1:0]EXT_CH_GT_DRPDI, + input [PCIE_LANE-1:0] EXT_CH_GT_DRPWE, + + output [(PCIE_LANE*16)-1:0]EXT_CH_GT_DRPDO, + output [PCIE_LANE-1:0] EXT_CH_GT_DRPRDY, + + //---------- JTAG Ports -------------------------------- + input PIPE_JTAG_EN, // DCLK | DCLK + output [PCIE_LANE-1:0] PIPE_JTAG_RDY, // DCLK | DCLK + + //---------- Debug Ports ------------------------------- + output [PCIE_LANE-1:0] PIPE_DEBUG_0, // Async | Async + output [PCIE_LANE-1:0] PIPE_DEBUG_1, // Async | Async + output [PCIE_LANE-1:0] PIPE_DEBUG_2, // Async | Async + output [PCIE_LANE-1:0] PIPE_DEBUG_3, // Async | Async + output [PCIE_LANE-1:0] PIPE_DEBUG_4, // Async | Async + output [PCIE_LANE-1:0] PIPE_DEBUG_5, // Async | Async + output [PCIE_LANE-1:0] PIPE_DEBUG_6, // Async | Async + output [PCIE_LANE-1:0] PIPE_DEBUG_7, // Async | Async + output [PCIE_LANE-1:0] PIPE_DEBUG_8, // Async | Async + output [PCIE_LANE-1:0] PIPE_DEBUG_9, // Async | Async + output [31:0] PIPE_DEBUG, // Async | Async + + output [(PCIE_LANE*15)-1:0] PIPE_DMONITOROUT // DMONITORCLK + +); + + //---------- Input Registers --------------------------- +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg2; + + //---------- PIPE Clock Module Output ------------------ + wire clk_pclk; + wire clk_rxusrclk; + wire [PCIE_LANE-1:0] clk_rxoutclk; + wire clk_dclk; + wire clk_oobclk; + wire clk_mmcm_lock; + + //---------- PIPE Reset Module Output ------------------ + wire rst_cpllreset; + wire rst_cpllpd; + wire rst_rxusrclk_reset; + wire rst_dclk_reset; + wire rst_gtreset; + wire rst_drp_start; + wire rst_drp_x16x20_mode; + wire rst_drp_x16; + wire rst_userrdy; + wire rst_txsync_start; + wire rst_idle; + wire [4:0] rst_fsm; + + //------------------------------------------------------ + wire gtp_rst_qpllreset; // GTP + wire gtp_rst_qpllpd; // GTP + + //------------------------------------------------------ + wire [(PCIE_LANE-1)>>2:0]qpllreset; + wire qpllpd; + + //---------- QPLL Reset Module Output ------------------ + wire qrst_ovrd; + wire qrst_drp_start; + wire qrst_qpllreset; + wire qrst_qpllpd; + wire qrst_idle; + wire [3:0] qrst_fsm; + + //---------- PIPE_JTAG Master Module Output ------------ + wire [(PCIE_LANE*37)-1:0] jtag_sl_iport; + wire [(PCIE_LANE*17)-1:0] jtag_sl_oport; + + //---------- PIPE User Module Output ------------------- + wire [PCIE_LANE-1:0] gt_txpmareset_i; + wire [PCIE_LANE-1:0] gt_rxpmareset_i; + + wire [PCIE_LANE-1:0] user_oobclk; + wire [PCIE_LANE-1:0] user_resetovrd; + wire [PCIE_LANE-1:0] user_txpmareset; + wire [PCIE_LANE-1:0] user_rxpmareset; + wire [PCIE_LANE-1:0] user_rxcdrreset; + wire [PCIE_LANE-1:0] user_rxcdrfreqreset; + wire [PCIE_LANE-1:0] user_rxdfelpmreset; + wire [PCIE_LANE-1:0] user_eyescanreset; + wire [PCIE_LANE-1:0] user_txpcsreset; + wire [PCIE_LANE-1:0] user_rxpcsreset; + wire [PCIE_LANE-1:0] user_rxbufreset; + wire [PCIE_LANE-1:0] user_resetovrd_done; + wire [PCIE_LANE-1:0] user_active_lane; + wire [PCIE_LANE-1:0] user_resetdone /* synthesis syn_keep=1 */; + wire [PCIE_LANE-1:0] user_rxcdrlock; + wire [PCIE_LANE-1:0] user_rx_converge; + wire [PCIE_LANE-1:0] PIPE_RXEQ_CONVERGE; + + //---------- PIPE Rate Module Output ------------------- + wire [PCIE_LANE-1:0] rate_cpllpd; + wire [PCIE_LANE-1:0] rate_qpllpd; + wire [PCIE_LANE-1:0] rate_cpllreset; + wire [PCIE_LANE-1:0] rate_qpllreset; + wire [PCIE_LANE-1:0] rate_txpmareset; + wire [PCIE_LANE-1:0] rate_rxpmareset; + wire [(PCIE_LANE*2)-1:0] rate_sysclksel; + wire [PCIE_LANE-1:0] rate_pclk_sel; + wire [PCIE_LANE-1:0] rate_drp_start; + wire [PCIE_LANE-1:0] rate_drp_x16x20_mode; + wire [PCIE_LANE-1:0] rate_drp_x16; + wire [PCIE_LANE-1:0] rate_gen3; + wire [(PCIE_LANE*3)-1:0] rate_rate; + wire [PCIE_LANE-1:0] rate_resetovrd_start; + wire [PCIE_LANE-1:0] rate_txsync_start; + wire [PCIE_LANE-1:0] rate_done; + wire [PCIE_LANE-1:0] rate_rxsync_start; + wire [PCIE_LANE-1:0] rate_rxsync; + wire [PCIE_LANE-1:0] rate_idle; + wire [(PCIE_LANE*5)-1:0] rate_fsm; + + //---------- PIPE Sync Module Output ------------------- + wire [PCIE_LANE-1:0] sync_txphdlyreset; + wire [PCIE_LANE-1:0] sync_txphalign; + wire [PCIE_LANE-1:0] sync_txphalignen; + wire [PCIE_LANE-1:0] sync_txphinit; + wire [PCIE_LANE-1:0] sync_txdlybypass; + wire [PCIE_LANE-1:0] sync_txdlysreset; + wire [PCIE_LANE-1:0] sync_txdlyen; + wire [PCIE_LANE-1:0] sync_txsync_done; + wire [(PCIE_LANE*6)-1:0] sync_fsm_tx; + + wire [PCIE_LANE-1:0] sync_rxphalign; + wire [PCIE_LANE-1:0] sync_rxphalignen; + wire [PCIE_LANE-1:0] sync_rxdlybypass; + wire [PCIE_LANE-1:0] sync_rxdlysreset; + wire [PCIE_LANE-1:0] sync_rxdlyen; + wire [PCIE_LANE-1:0] sync_rxddien; + wire [PCIE_LANE-1:0] sync_rxsync_done; + wire [PCIE_LANE-1:0] sync_rxsync_donem; + wire [(PCIE_LANE*7)-1:0] sync_fsm_rx; + + wire [PCIE_LANE-1:0] txdlysresetdone; + wire [PCIE_LANE-1:0] txphaligndone; + wire [PCIE_LANE-1:0] rxdlysresetdone; + wire [PCIE_LANE-1:0] rxphaligndone_s; + + wire txsyncallin; // GTH + wire rxsyncallin; // GTH + + //---------- PIPE DRP Module Output -------------------- + wire [(PCIE_LANE*9)-1:0] drp_addr; + wire [PCIE_LANE-1:0] drp_en; + wire [(PCIE_LANE*16)-1:0]drp_di; + wire [PCIE_LANE-1:0] drp_we; + wire [PCIE_LANE-1:0] drp_done; + wire [(PCIE_LANE*3)-1:0] drp_fsm; + + //---------- PIPE JTAG Slave Module Output-------------- + wire [(PCIE_LANE*17)-1:0]jtag_sl_addr; + wire [PCIE_LANE-1:0] jtag_sl_den; + wire [PCIE_LANE-1:0] jtag_sl_en; + wire [(PCIE_LANE*16)-1:0]jtag_sl_di; + wire [PCIE_LANE-1:0] jtag_sl_we; + + //---------- PIPE DRP MUX Output ----------------------- + wire [(PCIE_LANE*9)-1:0] drp_mux_addr; + wire [PCIE_LANE-1:0] drp_mux_en; + wire [(PCIE_LANE*16)-1:0]drp_mux_di; + wire [PCIE_LANE-1:0] drp_mux_we; + + //---------- PIPE EQ Module Output --------------------- + wire [PCIE_LANE-1:0] eq_txeq_deemph; + wire [(PCIE_LANE*5)-1:0] eq_txeq_precursor; + wire [(PCIE_LANE*7)-1:0] eq_txeq_maincursor; + wire [(PCIE_LANE*5)-1:0] eq_txeq_postcursor; + + wire [PCIE_LANE-1:0] eq_rxeq_adapt_done; + + //---------- PIPE DRP Module Output -------------------- + wire [((((PCIE_LANE-1)>>2)+1)*8)-1:0] qdrp_addr; + wire [(PCIE_LANE-1)>>2:0] qdrp_en; + wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qdrp_di; + wire [(PCIE_LANE-1)>>2:0] qdrp_we; + wire [(PCIE_LANE-1)>>2:0] qdrp_done; + wire [(PCIE_LANE-1)>>2:0] qdrp_qpllreset; + wire [((((PCIE_LANE-1)>>2)+1)*6)-1:0] qdrp_crscode; + wire [((((PCIE_LANE-1)>>2)+1)*9)-1:0] qdrp_fsm; + + //---------- QPLL Wrapper Output ----------------------- + wire [(PCIE_LANE-1)>>2:0] qpll_qplloutclk; + wire [(PCIE_LANE-1)>>2:0] qpll_qplloutrefclk; + wire [(PCIE_LANE-1)>>2:0] qpll_qplllock; + wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qpll_do; + wire [(PCIE_LANE-1)>>2:0] qpll_rdy; + + //---------- GTX Wrapper Output ------------------------ + wire [PCIE_LANE-1:0] gt_txoutclk; + wire [PCIE_LANE-1:0] gt_rxoutclk; + wire [PCIE_LANE-1:0] gt_cplllock; + wire [PCIE_LANE-1:0] gt_rxcdrlock; + wire [PCIE_LANE-1:0] gt_txresetdone; + wire [PCIE_LANE-1:0] gt_rxresetdone; + wire [PCIE_LANE-1:0] gt_eyescandataerror; + wire [PCIE_LANE-1:0] gt_rxpmaresetdone; + wire [(PCIE_LANE*8)-1:0] gt_rxdisperr; + wire [(PCIE_LANE*8)-1:0] gt_rxnotintable; + wire [PCIE_LANE-1:0] gt_rxvalid; + wire [PCIE_LANE-1:0] gt_phystatus; + wire [(PCIE_LANE*3)-1:0] gt_rxstatus; + wire [(PCIE_LANE*3)-1:0] gt_rxbufstatus; + wire [PCIE_LANE-1:0] gt_rxelecidle; + wire [PCIE_LANE-1:0] gt_txratedone; + wire [PCIE_LANE-1:0] gt_rxratedone; + wire [(PCIE_LANE*16)-1:0]gt_do; + wire [PCIE_LANE-1:0] gt_rdy; + wire [PCIE_LANE-1:0] gt_txphinitdone; + wire [PCIE_LANE-1:0] gt_txdlysresetdone; + wire [PCIE_LANE-1:0] gt_txphaligndone; + wire [PCIE_LANE-1:0] gt_rxdlysresetdone; + wire [PCIE_LANE:0] gt_rxphaligndone; // Custom width for calculation + wire [PCIE_LANE-1:0] gt_txsyncout; // GTH + wire [PCIE_LANE-1:0] gt_txsyncdone; // GTH + wire [PCIE_LANE-1:0] gt_rxsyncout; // GTH + wire [PCIE_LANE-1:0] gt_rxsyncdone; // GTH + wire [PCIE_LANE-1:0] gt_rxcommadet; + wire [(PCIE_LANE*4)-1:0] gt_rxchariscomma; + wire [PCIE_LANE-1:0] gt_rxbyteisaligned; + wire [PCIE_LANE-1:0] gt_rxbyterealign; + wire [ 4:0] gt_rxchbondi [PCIE_LANE:0]; + wire [(PCIE_LANE*3)-1:0] gt_rxchbondlevel; + wire [ 4:0] gt_rxchbondo [PCIE_LANE:0]; + + wire [PCIE_LANE-1:0] rxchbonden; + wire [PCIE_LANE-1:0] rxchbondmaster; + wire [PCIE_LANE-1:0] rxchbondslave; + wire [PCIE_LANE-1:0] oobclk; + + //---------- TX EQ ------------------------------------- + localparam TXEQ_FS = 6'd40; // TX equalization full swing + localparam TXEQ_LF = 6'd15; // TX equalization low frequency + + //---------- Select JTAG Slave Type ---------------------------------------- + localparam GC_XSDB_SLAVE_TYPE = (PCIE_GT_DEVICE == "GTP") ? 16'h0400 : (PCIE_GT_DEVICE == "GTH") ? 16'h004A : 16'h0046; + + //---------- Generate Per-Lane Signals ----------------- + genvar i; // Index for per-lane signals + + + +//---------- Assignments ------------------------------------------------------- +assign gt_rxchbondo[0] = 5'd0; // Initialize rxchbond for lane 0 +assign gt_rxphaligndone[PCIE_LANE] = 1'd1; // Mot used +assign txsyncallin = &(gt_txphaligndone | (~user_active_lane)); +assign rxsyncallin = &(gt_rxphaligndone | (~user_active_lane)); + +//---------- Reset Synchronizer ------------------------------------------------ +always @ (posedge clk_pclk or negedge PIPE_RESET_N) +begin + + if (!PIPE_RESET_N) + begin + reset_n_reg1 <= 1'd0; + reset_n_reg2 <= 1'd0; + end + else + begin + reset_n_reg1 <= 1'd1; + reset_n_reg2 <= reset_n_reg1; + end +end + + + + //---------- PIPE Clock External --------------------------------------- + assign clk_pclk = PIPE_PCLK_IN; + assign clk_rxusrclk = PIPE_RXUSRCLK_IN; + assign clk_rxoutclk = PIPE_RXOUTCLK_IN; + assign clk_dclk = PIPE_DCLK_IN; + assign PIPE_USERCLK1 = PIPE_USERCLK1_IN; + assign PIPE_USERCLK2 = PIPE_USERCLK2_IN; + assign clk_oobclk = PIPE_OOBCLK_IN; + assign clk_mmcm_lock = PIPE_MMCM_LOCK_IN; + + + assign INT_PCLK_OUT_SLAVE= 1'b0; + assign INT_RXUSRCLK_OUT = 1'b0; + assign INT_RXOUTCLK_OUT = {PCIE_LANE{1'b0}}; + assign INT_DCLK_OUT = 1'b0; + assign INT_USERCLK1_OUT = 1'b0; + assign INT_USERCLK2_OUT = 1'b0; + assign INT_OOBCLK_OUT = 1'b0; + assign INT_MMCM_LOCK_OUT = 1'b0; + + + + +//---------- PIPE Reset Module ------------------------------------------------- +generate + + if (PCIE_GT_DEVICE == "GTP") + + begin : gtp_pipe_reset + + //---------- GTP PIPE Reset Module ------------------------------------- +pcie_7x_0_gtp_pipe_reset # + ( + + .PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode + //.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP + //.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP + //.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only + .PCIE_LANE (PCIE_LANE) // PCIe number of lanes + + ) + gtp_pipe_reset_i + ( + + //---------- Input ----------------------------- + .RST_CLK (clk_pclk), + .RST_RXUSRCLK (clk_rxusrclk), + .RST_DCLK (clk_dclk), + .RST_RST_N (reset_n_reg2), + .RST_DRP_DONE (drp_done), + .RST_RXPMARESETDONE (gt_rxpmaresetdone), + .RST_PLLLOCK (&qpll_qplllock), + //.RST_QPLL_IDLE (qrst_idle), // removed for GTP + .RST_RATE_IDLE (rate_idle), + .RST_RXCDRLOCK (user_rxcdrlock), + .RST_MMCM_LOCK (clk_mmcm_lock), + .RST_RESETDONE (user_resetdone), + .RST_PHYSTATUS (gt_phystatus), + .RST_TXSYNC_DONE (sync_txsync_done), + + //---------- Output ---------------------------- + .RST_CPLLRESET (rst_cpllreset), + .RST_CPLLPD (rst_cpllpd), + .RST_RXUSRCLK_RESET (rst_rxusrclk_reset), + .RST_DCLK_RESET (rst_dclk_reset), + .RST_GTRESET (rst_gtreset), + .RST_DRP_START (rst_drp_start), + .RST_DRP_X16 (rst_drp_x16), + .RST_USERRDY (rst_userrdy), + .RST_TXSYNC_START (rst_txsync_start), + .RST_IDLE (rst_idle), + .RST_FSM (rst_fsm) + + ); + + //---------- Default --------------------------------------------------- + assign gtp_rst_qpllreset = rst_cpllreset; + assign gtp_rst_qpllpd = rst_cpllpd; + + end + + else + + begin : pipe_reset + + //---------- PIPE Reset Module ----------------------------------------- +pcie_7x_0_pipe_reset # + ( + + .PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode + .PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device + .PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only + .PCIE_POWER_SAVING (PCIE_POWER_SAVING), // PCIe power saving + .PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only + .PCIE_LANE (PCIE_LANE) // PCIe number of lanes + + ) + pipe_reset_i + ( + + //---------- Input ----------------------------- + .RST_CLK (clk_pclk), + .RST_RXUSRCLK (clk_rxusrclk), + .RST_DCLK (clk_dclk), + .RST_RST_N (reset_n_reg2), + .RST_DRP_DONE (drp_done), + .RST_RXPMARESETDONE (gt_rxpmaresetdone), + .RST_CPLLLOCK (gt_cplllock), + .RST_QPLL_IDLE (qrst_idle), + .RST_RATE_IDLE (rate_idle), + .RST_RXCDRLOCK (user_rxcdrlock), + .RST_MMCM_LOCK (clk_mmcm_lock), + .RST_RESETDONE (user_resetdone), + .RST_PHYSTATUS (gt_phystatus), + .RST_TXSYNC_DONE (sync_txsync_done), + + //---------- Output ---------------------------- + .RST_CPLLRESET (rst_cpllreset), + .RST_CPLLPD (rst_cpllpd), + .RST_RXUSRCLK_RESET (rst_rxusrclk_reset), + .RST_DCLK_RESET (rst_dclk_reset), + .RST_GTRESET (rst_gtreset), + .RST_DRP_START (rst_drp_start), + .RST_DRP_X16X20_MODE (rst_drp_x16x20_mode), + .RST_DRP_X16 (rst_drp_x16), + .RST_USERRDY (rst_userrdy), + .RST_TXSYNC_START (rst_txsync_start), + .RST_IDLE (rst_idle), + .RST_FSM (rst_fsm[4:0]) + + ); + + //---------- Default --------------------------------------------------- + assign gtp_rst_qpllreset = 1'd0; + assign gtp_rst_qpllpd = 1'd0; + + end + +endgenerate + + + +//---------- QPLL Reset Module ------------------------------------------------- +generate + + if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL")) + + begin : qpll_reset + +pcie_7x_0_qpll_reset # + ( + + .PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only + .PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving + .PCIE_LANE (PCIE_LANE) // PCIe number of lanes + + ) + qpll_reset_i + ( + + //---------- Input --------------------------------- + .QRST_CLK (clk_pclk), + .QRST_RST_N (reset_n_reg2), + .QRST_MMCM_LOCK (clk_mmcm_lock), + .QRST_CPLLLOCK (gt_cplllock), + .QRST_DRP_DONE (qdrp_done), + .QRST_QPLLLOCK (qpll_qplllock), + .QRST_RATE (PIPE_RATE), + .QRST_QPLLRESET_IN (rate_qpllreset), + .QRST_QPLLPD_IN (rate_qpllpd), + + //---------- Output -------------------------------- + .QRST_OVRD (qrst_ovrd), + .QRST_DRP_START (qrst_drp_start), + .QRST_QPLLRESET_OUT (qrst_qpllreset), + .QRST_QPLLPD_OUT (qrst_qpllpd), + .QRST_IDLE (qrst_idle), + .QRST_FSM (qrst_fsm) + + ); + + end + + else + + //---------- QPLL Reset Defaults --------------------------------------- + begin : qpll_reset_disable + assign qrst_ovrd = 1'd0; + assign qrst_drp_start = 1'd0; + assign qrst_qpllreset = 1'd0; + assign qrst_qpllpd = 1'd0; + assign qrst_idle = 1'd0; + assign qrst_fsm = 1; + end + +endgenerate + +assign jtag_sl_iport = {PCIE_LANE{37'd0}}; + +//Reference Clock for CPLLPD Fix + +wire gt_cpllpdrefclk; + +BUFG cpllpd_refclk_inst (.I (PIPE_CLK), .O (gt_cpllpdrefclk)); + +//---------- Generate PIPE Lane ------------------------------------------------ +generate for (i=0; i>2]) // removed for GTP + //.RATE_MMCM_LOCK (clk_mmcm_lock), // removed for GTP + .RATE_DRP_DONE (drp_done[i]), + .RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]), + //.RATE_TXRESETDONE (gt_txresetdone[i]), // removed for GTP + //.RATE_RXRESETDONE (gt_rxresetdone[i]), // removed for GTP + .RATE_TXRATEDONE (gt_txratedone[i]), + .RATE_RXRATEDONE (gt_rxratedone[i]), + .RATE_PHYSTATUS (gt_phystatus[i]), + //.RATE_RESETOVRD_DONE (user_resetovrd_done[i]), // removed for GTP + .RATE_TXSYNC_DONE (sync_txsync_done[i]), + //.RATE_RXSYNC_DONE (sync_rxsync_done[i]), // removed for GTP + + //---------- Output ---------------------------- + //.RATE_CPLLPD (rate_cpllpd[i]), // removed for GTP + //.RATE_QPLLPD (rate_qpllpd[i]), // removed for GTP + //.RATE_CPLLRESET (rate_cpllreset[i]), // removed for GTP + //.RATE_QPLLRESET (rate_qpllreset[i]), // removed for GTP + //.RATE_TXPMARESET (rate_txpmareset[i]), // removed for GTP + //.RATE_RXPMARESET (rate_rxpmareset[i]), // removed for GTP + //.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]), // removed for GTP + .RATE_DRP_START (rate_drp_start[i]), + .RATE_DRP_X16 (rate_drp_x16[i]), + .RATE_PCLK_SEL (rate_pclk_sel[i]), + //.RATE_GEN3 (rate_gen3[i]), // removed for GTP + .RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]), + //.RATE_RESETOVRD_START (rate_resetovrd_start[i]), // removed for GTP + .RATE_TXSYNC_START (rate_txsync_start[i]), + .RATE_DONE (rate_done[i]), + //.RATE_RXSYNC_START (rate_rxsync_start[i]), // removed for GTP + //.RATE_RXSYNC (rate_rxsync[i]), // removed for GTP + .RATE_IDLE (rate_idle[i]), + .RATE_FSM (rate_fsm[(5*i)+4:(5*i)]) + ); + + //---------- Default for GTP ----------------------- + assign rate_cpllpd[i] = 1'd0; + assign rate_qpllpd[i] = 1'd0; + assign rate_cpllreset[i] = 1'd0; + assign rate_qpllreset[i] = 1'd0; + assign rate_txpmareset[i] = 1'd0; + assign rate_rxpmareset[i] = 1'd0; + assign rate_sysclksel[(2*i)+1:(2*i)] = 2'b0; + assign rate_gen3[i] = 1'd0; + assign rate_resetovrd_start[i] = 1'd0; + assign rate_rxsync_start[i] = 1'd0; + assign rate_rxsync[i] = 1'd0; + + end + + else + + begin : pipe_rate + + //---------- PIPE Rate Module ---------------------------------------------- +pcie_7x_0_pipe_rate # + ( + + .PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup + .PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device + .PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode + .PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only + .PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving + .PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable + .PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only + .PCIE_RXBUF_EN (PCIE_RXBUF_EN) // PCIe RX buffer enable for Gen3 only + + ) + pipe_rate_i + ( + + //---------- Input --------------------------------- + .RATE_CLK (clk_pclk), + .RATE_RST_N (!rst_cpllreset), + .RATE_RST_IDLE (rst_idle), + .RATE_ACTIVE_LANE (user_active_lane[i]), + .RATE_RATE_IN (PIPE_RATE), + .RATE_CPLLLOCK (gt_cplllock[i]), + .RATE_QPLLLOCK (qpll_qplllock[i>>2]), + .RATE_MMCM_LOCK (clk_mmcm_lock), + .RATE_DRP_DONE (drp_done[i]), + .RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]), + .RATE_TXRESETDONE (gt_txresetdone[i]), + .RATE_RXRESETDONE (gt_rxresetdone[i]), + .RATE_TXRATEDONE (gt_txratedone[i]), + .RATE_RXRATEDONE (gt_rxratedone[i]), + .RATE_PHYSTATUS (gt_phystatus[i]), + .RATE_RESETOVRD_DONE (user_resetovrd_done[i]), + .RATE_TXSYNC_DONE (sync_txsync_done[i]), + .RATE_RXSYNC_DONE (sync_rxsync_done[i]), + + //---------- Output -------------------------------- + .RATE_CPLLPD (rate_cpllpd[i]), + .RATE_QPLLPD (rate_qpllpd[i]), + .RATE_CPLLRESET (rate_cpllreset[i]), + .RATE_QPLLRESET (rate_qpllreset[i]), + .RATE_TXPMARESET (rate_txpmareset[i]), + .RATE_RXPMARESET (rate_rxpmareset[i]), + .RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]), + .RATE_DRP_START (rate_drp_start[i]), + .RATE_DRP_X16X20_MODE (rate_drp_x16x20_mode[i]), + .RATE_DRP_X16 (rate_drp_x16[i]), + .RATE_PCLK_SEL (rate_pclk_sel[i]), + .RATE_GEN3 (rate_gen3[i]), + .RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]), + .RATE_RESETOVRD_START (rate_resetovrd_start[i]), + .RATE_TXSYNC_START (rate_txsync_start[i]), + .RATE_DONE (rate_done[i]), + .RATE_RXSYNC_START (rate_rxsync_start[i]), + .RATE_RXSYNC (rate_rxsync[i]), + .RATE_IDLE (rate_idle[i]), + .RATE_FSM (rate_fsm[(5*i)+4:(5*i)]) + + ); + + end + + + + //---------- PIPE Sync Module ---------------------------------------------- +pcie_7x_0_pipe_sync # + ( + + .PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device + .PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only + .PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only + .PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode + .PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode + .PCIE_LANE (PCIE_LANE), // PCIe lane + .PCIE_LINK_SPEED (PCIE_LINK_SPEED) // PCIe link speed + + ) + pipe_sync_i + ( + + //---------- Input --------------------------------- + .SYNC_CLK (clk_pclk), + .SYNC_RST_N (!rst_cpllreset), + .SYNC_SLAVE (i > 0), + .SYNC_GEN3 (rate_gen3[i]), + .SYNC_RATE_IDLE (rate_idle[i]), + .SYNC_MMCM_LOCK (clk_mmcm_lock), + .SYNC_RXELECIDLE (gt_rxelecidle[i]), + .SYNC_RXCDRLOCK (user_rxcdrlock[i]), + .SYNC_ACTIVE_LANE (user_active_lane[i]), + + .SYNC_TXSYNC_START (rate_txsync_start[i] || rst_txsync_start), + .SYNC_TXPHINITDONE (&(gt_txphinitdone | (~user_active_lane))), + .SYNC_TXDLYSRESETDONE (txdlysresetdone[i]), + .SYNC_TXPHALIGNDONE (txphaligndone[i]), + .SYNC_TXSYNCDONE (gt_txsyncdone[i]), // GTH + + .SYNC_RXSYNC_START (rate_rxsync_start[i]), + .SYNC_RXDLYSRESETDONE (rxdlysresetdone[i]), + .SYNC_RXPHALIGNDONE_M (gt_rxphaligndone[0]), + .SYNC_RXPHALIGNDONE_S (rxphaligndone_s[i]), + .SYNC_RXSYNC_DONEM_IN (sync_rxsync_donem[0]), + .SYNC_RXSYNCDONE (gt_rxsyncdone[i]), // GTH + + //---------- Output -------------------------------- + .SYNC_TXPHDLYRESET (sync_txphdlyreset[i]), + .SYNC_TXPHALIGN (sync_txphalign[i]), + .SYNC_TXPHALIGNEN (sync_txphalignen[i]), + .SYNC_TXPHINIT (sync_txphinit[i]), + .SYNC_TXDLYBYPASS (sync_txdlybypass[i]), + .SYNC_TXDLYSRESET (sync_txdlysreset[i]), + .SYNC_TXDLYEN (sync_txdlyen[i]), + .SYNC_TXSYNC_DONE (sync_txsync_done[i]), + .SYNC_FSM_TX (sync_fsm_tx[(6*i)+5:(6*i)]), + + .SYNC_RXPHALIGN (sync_rxphalign[i]), + .SYNC_RXPHALIGNEN (sync_rxphalignen[i]), + .SYNC_RXDLYBYPASS (sync_rxdlybypass[i]), + .SYNC_RXDLYSRESET (sync_rxdlysreset[i]), + .SYNC_RXDLYEN (sync_rxdlyen[i]), + .SYNC_RXDDIEN (sync_rxddien[i]), + .SYNC_RXSYNC_DONEM_OUT (sync_rxsync_donem[i]), + .SYNC_RXSYNC_DONE (sync_rxsync_done[i]), + .SYNC_FSM_RX (sync_fsm_rx[(7*i)+6:(7*i)]) + + ); + + //---------- PIPE Sync Assignments ----------------------------------------- + assign txdlysresetdone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txdlysresetdone[i] : >_txdlysresetdone; + assign txphaligndone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txphaligndone[i] : &(gt_txphaligndone | (~user_active_lane)); + assign rxdlysresetdone[i] = (PCIE_RXSYNC_MODE == 1) ? gt_rxdlysresetdone[i] : >_rxdlysresetdone; + assign rxphaligndone_s[i] = (PCIE_LANE == 1) ? 1'd0 : >_rxphaligndone[PCIE_LANE:1]; + + + //---------- GTP PIPE DRP Module ------------------------------------------- + if (PCIE_GT_DEVICE == "GTP") + + begin : gtp_pipe_drp + + //---------- GTP PIPE DRP Module --------------------------------------- +pcie_7x_0_gtp_pipe_drp + gtp_pipe_drp_i + ( + + //---------- Input --------------------------------- + .DRP_CLK (clk_dclk), + .DRP_RST_N (!rst_dclk_reset), + .DRP_X16 (rst_drp_x16 || rate_drp_x16[i]), + .DRP_START (rst_drp_start || rate_drp_start[i]), + .DRP_DO (gt_do[(16*i)+15:(16*i)]), + .DRP_RDY (gt_rdy[i]), + + //---------- Output -------------------------------- + .DRP_ADDR (drp_addr[(9*i)+8:(9*i)]), + .DRP_EN (drp_en[i]), + .DRP_DI (drp_di[(16*i)+15:(16*i)]), + .DRP_WE (drp_we[i]), + .DRP_DONE (drp_done[i]), + .DRP_FSM (drp_fsm[(3*i)+2:(3*i)]) + + ); + + end + + else + + begin : pipe_drp + + //---------- PIPE DRP Module ------------------------------------------- +pcie_7x_0_pipe_drp # + ( + + .PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device + .PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode + .PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only + .PCIE_AUX_CDR_GEN3_EN (PCIE_AUX_CDR_GEN3_EN), // PCIe AUX CDR Gen3 enable + .PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable + .PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only + .PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only + .PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode + .PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE) // PCIe RX sync mode + + ) + pipe_drp_i + ( + + //---------- Input --------------------------------- + .DRP_CLK (clk_dclk), + .DRP_RST_N (!rst_dclk_reset), + .DRP_GTXRESET (rst_gtreset), + .DRP_RATE (PIPE_RATE), + .DRP_X16X20_MODE (rst_drp_x16x20_mode || rate_drp_x16x20_mode[i]), + .DRP_X16 (rst_drp_x16 || rate_drp_x16[i]), + .DRP_START (rst_drp_start || rate_drp_start[i]), + .DRP_DO (gt_do[(16*i)+15:(16*i)]), + .DRP_RDY (gt_rdy[i]), + + //---------- Output -------------------------------- + .DRP_ADDR (drp_addr[(9*i)+8:(9*i)]), + .DRP_EN (drp_en[i]), + .DRP_DI (drp_di[(16*i)+15:(16*i)]), + .DRP_WE (drp_we[i]), + .DRP_DONE (drp_done[i]), + .DRP_FSM (drp_fsm[(3*i)+2:(3*i)]) + + ); + + end + + + assign jtag_sl_oport[((i+1)*17)-1 : (i*17)] = 17'd0; + assign jtag_sl_addr[(17*i)+16:(17*i)] = 17'd0; + assign jtag_sl_den[i] = 1'd0; + assign jtag_sl_di[(16*i)+15:(16*i)] = 16'd0; + assign jtag_sl_we[i] = 1'd0; + + //---------- Generate DRP MUX ---------------------------------------------- + assign PIPE_JTAG_RDY[i] = (drp_fsm[(3*i)+2:(3*i)] == 3'b000); + assign jtag_sl_en[i] = (jtag_sl_addr[(17*i)+16:(17*i)+9] == 8'd0) ? jtag_sl_den[i] : 1'd0; + + // Channel DRP + assign drp_mux_en[i] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPEN[i] : drp_en[i]; + assign drp_mux_di[(16*i)+15:(16*i)] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPDI[(16*i)+15:(16*i)] : drp_di[(16*i)+15:(16*i)]; + assign drp_mux_addr[(9*i)+8:(9*i)] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPADDR[(9*i)+8:(9*i)] : drp_addr[(9*i)+8:(9*i)]; + assign drp_mux_we[i] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPWE[i] : drp_we[i]; + + //---------- Generate PIPE EQ ---------------------------------------------- + if (PCIE_LINK_SPEED == 3) + + begin : pipe_eq + + //---------- PIPE EQ Module -------------------------------------------- +pcie_7x_0_pipe_eq # + ( + .PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode + .PCIE_GT_DEVICE (PCIE_GT_DEVICE), + .PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3) // PCIe RX equalization mode + ) + pipe_eq_i + ( + + //---------- Input ----------------------------- + .EQ_CLK (clk_pclk), + .EQ_RST_N (!rst_cpllreset), + .EQ_GEN3 (rate_gen3[i]), + + .EQ_TXEQ_CONTROL (PIPE_TXEQ_CONTROL[(2*i)+1:(2*i)]), + .EQ_TXEQ_PRESET (PIPE_TXEQ_PRESET[(4*i)+3:(4*i)]), + .EQ_TXEQ_PRESET_DEFAULT (PIPE_TXEQ_PRESET_DEFAULT[(4*i)+3:(4*i)]), + .EQ_TXEQ_DEEMPH_IN (PIPE_TXEQ_DEEMPH[(6*i)+5:(6*i)]), // renamed + + .EQ_RXEQ_CONTROL (PIPE_RXEQ_CONTROL[(2*i)+1:(2*i)]), + .EQ_RXEQ_PRESET (PIPE_RXEQ_PRESET[(3*i)+2:(3*i)]), + .EQ_RXEQ_LFFS (PIPE_RXEQ_LFFS[(6*i)+5:(6*i)]), + .EQ_RXEQ_TXPRESET (PIPE_RXEQ_TXPRESET[(4*i)+3:(4*i)]), + .EQ_RXEQ_USER_EN (PIPE_RXEQ_USER_EN[i]), + .EQ_RXEQ_USER_TXCOEFF (PIPE_RXEQ_USER_TXCOEFF[(18*i)+17:(18*i)]), + .EQ_RXEQ_USER_MODE (PIPE_RXEQ_USER_MODE[i]), + + //---------- Output ---------------------------- + .EQ_TXEQ_DEEMPH (eq_txeq_deemph[i]), + .EQ_TXEQ_PRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]), + .EQ_TXEQ_MAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]), + .EQ_TXEQ_POSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]), + .EQ_TXEQ_DEEMPH_OUT (PIPE_TXEQ_COEFF[(18*i)+17:(18*i)]),// renamed + .EQ_TXEQ_DONE (PIPE_TXEQ_DONE[i]), + .EQ_TXEQ_FSM (PIPE_TXEQ_FSM[(6*i)+5:(6*i)]), + + .EQ_RXEQ_NEW_TXCOEFF (PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)]), + .EQ_RXEQ_LFFS_SEL (PIPE_RXEQ_LFFS_SEL[i]), + .EQ_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]), + .EQ_RXEQ_DONE (PIPE_RXEQ_DONE[i]), + .EQ_RXEQ_FSM (PIPE_RXEQ_FSM[(6*i)+5:(6*i)]) + + ); + + end + + else + + //---------- PIPE EQ Defaults ------------------------------------------ + begin : pipe_eq_disable + assign eq_txeq_deemph[i] = 1'd0; + assign eq_txeq_precursor[(5*i)+4:(5*i)] = 5'h00; + assign eq_txeq_maincursor[(7*i)+6:(7*i)] = 7'h00; + assign eq_txeq_postcursor[(5*i)+4:(5*i)] = 5'h00; + assign eq_rxeq_adapt_done[i] = 1'd0; + assign PIPE_TXEQ_COEFF[(18*i)+17:(18*i)] = 18'd0; + assign PIPE_TXEQ_DONE[i] = 1'd0; + assign PIPE_TXEQ_FSM[(6*i)+5:(6*i)] = 6'd0; + + assign PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)] = 18'd0; + assign PIPE_RXEQ_LFFS_SEL[i] = 1'd0; + assign PIPE_RXEQ_ADAPT_DONE[i] = 1'd0; + assign PIPE_RXEQ_DONE[i] = 1'd0; + assign PIPE_RXEQ_FSM[(6*i)+5:(6*i)] = 6'd0; + end + + //---------- Generate PIPE Common Per Quad for Gen3 ------------------------ + if ((i%4)==0) + + begin : pipe_quad + + //---------- Generate QPLL Powerdown and Reset ------------------------- + assign qpllpd = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllpd : qrst_qpllpd; + assign qpllreset[i>>2] = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllreset : (qrst_qpllreset || qdrp_qpllreset[i>>2]); + + if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL") || (PCIE_GT_DEVICE == "GTP")) + + begin : gt_common_enabled + + if (PCIE_EXT_GT_COMMON == "FALSE") + + begin : gt_common_int + + //---------- GT COMMON INTERNAL Module --------------------------------------- +pcie_7x_0_gt_common # + ( + + .PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode + .PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device + .PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode + .PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only + .PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency + + ) + gt_common_i + ( + + //---------- Input ------------------------- + .CPLLPDREFCLK (gt_cpllpdrefclk), + .PIPE_CLK (PIPE_CLK), + .QPLL_QPLLPD (qpllpd), + .QPLL_QPLLRESET (qpllreset[i>>2]), + .QPLL_DRP_CLK (clk_dclk), + .QPLL_DRP_RST_N (rst_dclk_reset), + .QPLL_DRP_OVRD (qrst_ovrd), + .QPLL_DRP_GEN3 (&rate_gen3), + .QPLL_DRP_START (qrst_drp_start), + + .QPLL_DRP_CRSCODE (qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))]), + .QPLL_DRP_FSM (qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))]), + .QPLL_DRP_DONE (qdrp_done[i>>2]), + .QPLL_DRP_RESET (qdrp_qpllreset[i>>2]), + .QPLL_QPLLOUTCLK (qpll_qplloutclk[i>>2]), + .QPLL_QPLLOUTREFCLK (qpll_qplloutrefclk[i>>2]), + .QPLL_QPLLLOCK (qpll_qplllock[i>>2]) + ); + assign QPLL_QPLLPD = 1'b0; + assign QPLL_QPLLRESET[i>>2] = 1'b0; + assign QPLL_DRP_CLK = 1'b0; + assign QPLL_DRP_RST_N = 1'b0; + assign QPLL_DRP_OVRD = 1'b0; + assign QPLL_DRP_GEN3 = 1'b0; + assign QPLL_DRP_START = 1'b0; + assign INT_QPLLLOCK_OUT[i>>2] = qpll_qplllock[i>>2] ; + assign INT_QPLLOUTREFCLK_OUT[i>>2] = qpll_qplloutrefclk[i>>2]; + assign INT_QPLLOUTCLK_OUT[i>>2] = qpll_qplloutclk[i>>2]; + end + else + begin : gt_common_ext + assign qdrp_done[i>>2] = QPLL_DRP_DONE[i>>2]; + assign qdrp_qpllreset[i>>2] = QPLL_DRP_RESET[i>>2]; + assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = QPLL_DRP_CRSCODE[(6*(i>>2))+5:(6*(i>>2))]; + assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = QPLL_DRP_FSM[(9*(i>>2))+8:(9*(i>>2))]; + assign qpll_qplloutclk[i>>2] = QPLL_QPLLOUTCLK[i>>2]; + assign qpll_qplloutrefclk[i>>2] = QPLL_QPLLOUTREFCLK[i>>2]; + assign qpll_qplllock[i>>2] = QPLL_QPLLLOCK[i>>2]; + assign QPLL_QPLLPD = qpllpd; + assign QPLL_QPLLRESET[i>>2] = qpllreset[i>>2]; + assign QPLL_DRP_CLK = clk_dclk; + assign QPLL_DRP_RST_N = rst_dclk_reset; + assign QPLL_DRP_OVRD = qrst_ovrd; + assign QPLL_DRP_GEN3 = &rate_gen3; + assign QPLL_DRP_START = qrst_drp_start; + assign INT_QPLLLOCK_OUT[i>>2] = 1'b0; + assign INT_QPLLOUTCLK_OUT[i>>2] = 1'b0; + assign INT_QPLLOUTREFCLK_OUT[i>>2] = 1'b0; + end + end + else + + //---------- PIPE Common Defaults ---------------------------------- + begin : gt_common_disabled + assign qdrp_done[i>>2] = 1'd0; + assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = 6'd0; + assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = 9'd0; + assign qpll_qplloutclk[i>>2] = 1'd0; + assign qpll_qplloutrefclk[i>>2] = 1'd0; + assign qpll_qplllock[i>>2] = 1'd0; + assign QPLL_QPLLPD = 1'b0; + assign QPLL_QPLLRESET[i>>2] = 1'b0; + assign QPLL_DRP_CLK = 1'b0; + assign QPLL_DRP_RST_N = 1'b0; + assign QPLL_DRP_OVRD = 1'b0; + assign QPLL_DRP_GEN3 = 1'b0; + assign QPLL_DRP_START = 1'b0; + assign INT_QPLLLOCK_OUT[i>>2] = 1'b0; + assign INT_QPLLOUTCLK_OUT[i>>2] = 1'b0; + assign INT_QPLLOUTREFCLK_OUT[i>>2] = 1'b0; + end + end + + //---------- GT Wrapper ---------------------------------------------------- + assign gt_txpmareset_i[i] = (user_txpmareset[i] || rate_txpmareset[i]); + assign gt_rxpmareset_i[i] = (user_rxpmareset[i] || rate_rxpmareset[i]); + +pcie_7x_0_gt_wrapper # + ( + + .PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode + .PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup + .PCIE_SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), // PCIe sim TX electrical idle drive level + .PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device + .PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode + .PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only + .PCIE_LPM_DFE (PCIE_LPM_DFE), // PCIe LPM or DFE mode for Gen1/Gen2 only + .PCIE_LPM_DFE_GEN3 (PCIE_LPM_DFE_GEN3), // PCIe LPM or DFE mode for Gen3 only + .PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable + .PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only + .PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode + .PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode + .PCIE_CHAN_BOND (PCIE_CHAN_BOND), // PCIe Channel bonding mode + .PCIE_CHAN_BOND_EN (PCIE_CHAN_BOND_EN), // PCIe Channel bonding enable for Gen1/Gen2 only + .PCIE_LANE (PCIE_LANE), // PCIe number of lane + .PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency + .PCIE_TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // PCIe TX electrical idle assert delay + .PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode + .TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0), + .TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1), + .TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2), + .TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3), + .TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4), + .TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0), + .TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1), + .TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2), + .TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3), + .TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4), + + .PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode + ) + gt_wrapper_i + ( + + //---------- GT User Ports ------------------------- + .GT_MASTER (i == 0), + .GT_GEN3 (rate_gen3[i]), + .GT_RX_CONVERGE (&user_rx_converge), + + //---------- GT Clock Ports ------------------------ + .GT_GTREFCLK0 (PIPE_CLK), + .GT_QPLLCLK (qpll_qplloutclk[i>>2]), + .GT_QPLLREFCLK (qpll_qplloutrefclk[i>>2]), + .GT_TXUSRCLK (clk_pclk), + .GT_RXUSRCLK (clk_rxusrclk), + .GT_TXUSRCLK2 (clk_pclk), + .GT_RXUSRCLK2 (clk_rxusrclk), + .GT_OOBCLK (oobclk[i]), + .GT_TXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]), + .GT_RXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]), + .GT_CPLLPDREFCLK (gt_cpllpdrefclk), + + .GT_TXOUTCLK (gt_txoutclk[i]), + .GT_RXOUTCLK (gt_rxoutclk[i]), + .GT_CPLLLOCK (gt_cplllock[i]), + .GT_RXCDRLOCK (gt_rxcdrlock[i]), + + //---------- GT Reset Ports ------------------------ + .GT_CPLLPD (rst_cpllpd || rate_cpllpd[i]), + .GT_CPLLRESET (rst_cpllreset || rate_cpllreset[i]), + .GT_TXUSERRDY (rst_userrdy), + .GT_RXUSERRDY (rst_userrdy), + .GT_RESETOVRD (user_resetovrd[i]), + .GT_GTTXRESET (rst_gtreset), + .GT_GTRXRESET (rst_gtreset), + .GT_TXPMARESET (gt_txpmareset_i[i]), // (user_txpmareset[i] || rate_txpmareset[i]), + .GT_RXPMARESET (gt_rxpmareset_i[i]), // (user_rxpmareset[i] || rate_rxpmareset[i]), + .GT_RXCDRRESET (user_rxcdrreset[i]), + .GT_RXCDRFREQRESET (user_rxcdrfreqreset[i]), + .GT_RXDFELPMRESET (user_rxdfelpmreset[i]), + .GT_EYESCANRESET (user_eyescanreset[i]), + .GT_TXPCSRESET (user_txpcsreset[i]), + .GT_RXPCSRESET (user_rxpcsreset[i]), + .GT_RXBUFRESET (user_rxbufreset[i]), + + .GT_EYESCANDATAERROR (gt_eyescandataerror[i]), + .GT_TXRESETDONE (gt_txresetdone[i]), + .GT_RXRESETDONE (gt_rxresetdone[i]), + .GT_RXPMARESETDONE (gt_rxpmaresetdone[i]), + + //---------- GT TX Data Ports ---------------------- + .GT_TXDATA (PIPE_TXDATA[(32*i)+31:(32*i)]), + .GT_TXDATAK (PIPE_TXDATAK[(4*i)+3:(4*i)]), + + .GT_TXP (PIPE_TXP[i]), + .GT_TXN (PIPE_TXN[i]), + + //---------- GT RX Data Ports ---------------------- + .GT_RXP (PIPE_RXP[i]), + .GT_RXN (PIPE_RXN[i]), + + .GT_RXDATA (PIPE_RXDATA[(32*i)+31:(32*i)]), + .GT_RXDATAK (PIPE_RXDATAK[(4*i)+3:(4*i)]), + + //---------- GT Command Ports ---------------------- + .GT_TXDETECTRX (PIPE_TXDETECTRX), + .GT_TXELECIDLE (PIPE_TXELECIDLE[i]), + .GT_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]), + .GT_RXPOLARITY (PIPE_RXPOLARITY[i]), + .GT_TXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]), + .GT_RXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]), + .GT_TXRATE (rate_rate[(3*i)+2:(3*i)]), + .GT_RXRATE (rate_rate[(3*i)+2:(3*i)]), + + //---------- GT Electrical Command Ports ----------- + .GT_TXMARGIN (PIPE_TXMARGIN), + .GT_TXSWING (PIPE_TXSWING), + .GT_TXDEEMPH (PIPE_TXDEEMPH[i]), + .GT_TXINHIBIT (PIPE_TXINHIBIT[i]), + .GT_TXPRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]), + .GT_TXMAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]), + .GT_TXPOSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]), + + //---------- GT Status Ports ----------------------- + .GT_RXVALID (gt_rxvalid[i]), + .GT_PHYSTATUS (gt_phystatus[i]), + .GT_RXELECIDLE (gt_rxelecidle[i]), + .GT_RXSTATUS (gt_rxstatus[(3*i)+2:(3*i)]), + .GT_RXBUFSTATUS (gt_rxbufstatus[(3*i)+2:(3*i)]), + .GT_TXRATEDONE (gt_txratedone[i]), + .GT_RXRATEDONE (gt_rxratedone[i]), + .GT_RXDISPERR (gt_rxdisperr[(8*i)+7:(8*i)]), + .GT_RXNOTINTABLE (gt_rxnotintable[(8*i)+7:(8*i)]), + + //---------- GT DRP Ports -------------------------- + .GT_DRPCLK (clk_dclk), + .GT_DRPADDR (drp_mux_addr[(9*i)+8:(9*i)]), + .GT_DRPEN (drp_mux_en[i]), + .GT_DRPDI (drp_mux_di[(16*i)+15:(16*i)]), + .GT_DRPWE (drp_mux_we[i]), + + .GT_DRPDO (gt_do[(16*i)+15:(16*i)]), + .GT_DRPRDY (gt_rdy[i]), + + //---------- GT TX Sync Ports ---------------------- + .GT_TXPHALIGN (sync_txphalign[i]), + .GT_TXPHALIGNEN (sync_txphalignen[i]), + .GT_TXPHINIT (sync_txphinit[i]), + .GT_TXDLYBYPASS (sync_txdlybypass[i]), + .GT_TXDLYSRESET (sync_txdlysreset[i]), + .GT_TXDLYEN (sync_txdlyen[i]), + + .GT_TXDLYSRESETDONE (gt_txdlysresetdone[i]), + .GT_TXPHINITDONE (gt_txphinitdone[i]), + .GT_TXPHALIGNDONE (gt_txphaligndone[i]), + + .GT_TXPHDLYRESET (sync_txphdlyreset[i]), + .GT_TXSYNCMODE (i == 0), // GTH, GTP + .GT_TXSYNCIN (gt_txsyncout[0]), // GTH, GTP + .GT_TXSYNCALLIN (txsyncallin), // GTH, GTP + + .GT_TXSYNCOUT (gt_txsyncout[i]), // GTH, GTP + .GT_TXSYNCDONE (gt_txsyncdone[i]), // GTH, GTP + + //---------- GT RX Sync Ports ---------------------- + .GT_RXPHALIGN (sync_rxphalign[i]), + .GT_RXPHALIGNEN (sync_rxphalignen[i]), + .GT_RXDLYBYPASS (sync_rxdlybypass[i]), + .GT_RXDLYSRESET (sync_rxdlysreset[i]), + .GT_RXDLYEN (sync_rxdlyen[i]), + .GT_RXDDIEN (sync_rxddien[i]), + + .GT_RXDLYSRESETDONE (gt_rxdlysresetdone[i]), + .GT_RXPHALIGNDONE (gt_rxphaligndone[i]), + + .GT_RXSYNCMODE (i == 0), // GTH + .GT_RXSYNCIN (gt_rxsyncout[0]), // GTH + .GT_RXSYNCALLIN (rxsyncallin), // GTH + + .GT_RXSYNCOUT (gt_rxsyncout[i]), // GTH + .GT_RXSYNCDONE (gt_rxsyncdone[i]), // GTH + + //---------- GT Comma Alignment Ports -------------- + .GT_RXSLIDE (PIPE_RXSLIDE[i]), + + .GT_RXCOMMADET (gt_rxcommadet[i]), + .GT_RXCHARISCOMMA (gt_rxchariscomma[(4*i)+3:(4*i)]), + .GT_RXBYTEISALIGNED (gt_rxbyteisaligned[i]), + .GT_RXBYTEREALIGN (gt_rxbyterealign[i]), + + //---------- GT Channel Bonding Ports -------------- + .GT_RXCHANISALIGNED (PIPE_RXCHANISALIGNED[i]), + .GT_RXCHBONDEN (rxchbonden[i]), + .GT_RXCHBONDI (gt_rxchbondi[i]), + .GT_RXCHBONDLEVEL (gt_rxchbondlevel[(3*i)+2:(3*i)]), + .GT_RXCHBONDMASTER (rxchbondmaster[i]), + .GT_RXCHBONDSLAVE (rxchbondslave[i]), + .GT_RXCHBONDO (gt_rxchbondo[i+1]), + + //---------- GT PRBS/Loopback Ports ---------------- + .GT_TXPRBSSEL (PIPE_TXPRBSSEL), + .GT_RXPRBSSEL (PIPE_RXPRBSSEL), + .GT_TXPRBSFORCEERR (PIPE_TXPRBSFORCEERR), + .GT_RXPRBSCNTRESET (PIPE_RXPRBSCNTRESET), + .GT_LOOPBACK (PIPE_LOOPBACK), + + .GT_RXPRBSERR (PIPE_RXPRBSERR[i]), + + //---------- GT Debug Port ------------------------- + .GT_DMONITOROUT (PIPE_DMONITOROUT[(15*i)+14:(15*i)]) + ); + + + + //---------- GT Wrapper Assignments ---------------------------------------- + assign oobclk[i] = (PCIE_OOBCLK_MODE == 1) ? user_oobclk[i] : clk_oobclk; + + //---------- Channel Bonding Master Slave Enable --------------------------- + if (PCIE_CHAN_BOND_EN == "FALSE") + begin : channel_bonding_ms_disable + assign rxchbonden[i] = 1'd0; + assign rxchbondmaster[i] = 1'd0; + assign rxchbondslave[i] = 1'd0; + end + else + begin : channel_bonding_ms_enable + assign rxchbonden[i] = (PCIE_LANE > 1) && (PCIE_CHAN_BOND_EN == "TRUE") ? !rate_gen3[i] : 1'd0; + assign rxchbondmaster[i] = rate_gen3[i] ? 1'd0 : (i == 0); + assign rxchbondslave[i] = rate_gen3[i] ? 1'd0 : (i > 0); + end + + //---------- Channel Bonding Input Connection ------------------------------ + if (PCIE_CHAN_BOND_EN == "FALSE") + begin : channel_bonding_in_disable + assign gt_rxchbondi[i] = 5'd0; + assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0; + end + else + begin : channel_bonding_in_enable + + //---------- Channel Bonding (2: Binary-Tree) -------------------------- + if (PCIE_CHAN_BOND == 2) + + begin : channel_bonding_a + + case (i) + + //---------- Lane 0 -------------------------------- + 0 : + begin + assign gt_rxchbondi[0] = gt_rxchbondo[0]; + assign gt_rxchbondlevel[2:0] = (PCIE_LANE == 4'd8) ? 3'd4 : + (PCIE_LANE > 4'd5) ? 3'd3 : + (PCIE_LANE > 4'd3) ? 3'd2 : + (PCIE_LANE > 4'd1) ? 3'd1 : 3'd0; + end + //---------- Lane 1 -------------------------------- + 1 : + begin + assign gt_rxchbondi[1] = gt_rxchbondo[1]; + assign gt_rxchbondlevel[5:3] = (PCIE_LANE == 4'd8) ? 3'd3 : + (PCIE_LANE > 4'd5) ? 3'd2 : + (PCIE_LANE > 4'd3) ? 3'd1 : 3'd0; + end + //---------- Lane 2 -------------------------------- + 2 : + begin + assign gt_rxchbondi[2] = gt_rxchbondo[1]; + assign gt_rxchbondlevel[8:6] = (PCIE_LANE == 4'd8) ? 3'd3 : + (PCIE_LANE > 4'd5) ? 3'd2 : + (PCIE_LANE > 4'd3) ? 3'd1 : 3'd0; + end + //---------- Lane 3 -------------------------------- + 3 : + begin + assign gt_rxchbondi[3] = gt_rxchbondo[3]; + assign gt_rxchbondlevel[11:9] = (PCIE_LANE == 4'd8) ? 3'd2 : + (PCIE_LANE > 4'd5) ? 3'd1 : 3'd0; + end + //---------- Lane 4 -------------------------------- + 4 : + begin + assign gt_rxchbondi[4] = gt_rxchbondo[3]; + assign gt_rxchbondlevel[14:12] = (PCIE_LANE == 4'd8) ? 3'd2 : + (PCIE_LANE > 4'd5) ? 3'd1 : 3'd0; + end + //---------- Lane 5 -------------------------------- + 5 : + begin + assign gt_rxchbondi[5] = gt_rxchbondo[5]; + assign gt_rxchbondlevel[17:15] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0; + end + //---------- Lane 6 -------------------------------- + 6 : + begin + assign gt_rxchbondi[6] = gt_rxchbondo[5]; + assign gt_rxchbondlevel[20:18] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0; + end + //---------- Lane 7 -------------------------------- + 7 : + begin + assign gt_rxchbondi[7] = gt_rxchbondo[7]; + assign gt_rxchbondlevel[23:21] = 3'd0; + end + //---------- Default ------------------------------- + default : + begin + assign gt_rxchbondi[i] = gt_rxchbondo[7]; + assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0; + end + + endcase + + end + + //---------- Channel Bonding (0: One-Hop, 1: Daisy Chain) -------------- + else + + begin : channel_bonding_b + assign gt_rxchbondi[i] = (PCIE_CHAN_BOND == 1) ? gt_rxchbondo[i] : ((i == 0) ? gt_rxchbondo[0] : gt_rxchbondo[1]); + assign gt_rxchbondlevel[(3*i)+2:(3*i)] = (PCIE_CHAN_BOND == 1) ? (PCIE_LANE-1)-i : ((PCIE_LANE > 1) && (i == 0)); + end + + end + + end + +endgenerate + + + +//---------- PIPE Wrapper Output ----------------------------------------------- +assign PIPE_TXEQ_FS = 0;//TXEQ_FS; +assign PIPE_TXEQ_LF = 0;//TXEQ_LF; +assign PIPE_RXELECIDLE = gt_rxelecidle; +assign PIPE_RXSTATUS = gt_rxstatus; + +assign PIPE_RXDISPERR = gt_rxdisperr; +assign PIPE_RXNOTINTABLE = gt_rxnotintable; +assign PIPE_RXPMARESETDONE = gt_rxpmaresetdone; +assign PIPE_RXBUFSTATUS = gt_rxbufstatus; +assign PIPE_TXPHALIGNDONE = gt_txphaligndone; +assign PIPE_TXPHINITDONE = gt_txphinitdone; +assign PIPE_TXDLYSRESETDONE = gt_txdlysresetdone; +assign PIPE_RXPHALIGNDONE = gt_rxphaligndone; +assign PIPE_RXDLYSRESETDONE = gt_rxdlysresetdone; +assign PIPE_RXSYNCDONE = gt_rxsyncdone; +assign PIPE_RXCOMMADET = gt_rxcommadet; +assign PIPE_QPLL_LOCK = qpll_qplllock; +assign PIPE_CPLL_LOCK = gt_cplllock; + +assign PIPE_PCLK = clk_pclk; +assign PIPE_PCLK_LOCK = clk_mmcm_lock; +assign PIPE_RXCDRLOCK = 0;//user_rxcdrlock; +assign PIPE_RXUSRCLK = 0;//clk_rxusrclk; +assign PIPE_RXOUTCLK = 0;//clk_rxoutclk; +assign PIPE_TXSYNC_DONE = 0;//sync_txsync_done; +assign PIPE_RXSYNC_DONE = 0;//sync_rxsync_done; +assign PIPE_ACTIVE_LANE = 0;//user_active_lane; + +assign PIPE_TXOUTCLK_OUT = gt_txoutclk[0]; +assign PIPE_RXOUTCLK_OUT = gt_rxoutclk; +assign PIPE_PCLK_SEL_OUT = rate_pclk_sel; +assign PIPE_GEN3_OUT = rate_gen3[0]; + +assign PIPE_RXEQ_CONVERGE = user_rx_converge; +assign PIPE_RXEQ_ADAPT_DONE = (PCIE_GT_DEVICE == "GTP") ? {PCIE_LANE{1'd0}} : eq_rxeq_adapt_done; + +assign PIPE_EYESCANDATAERROR = gt_eyescandataerror; +assign PIPE_RST_FSM = rst_fsm; +assign PIPE_QRST_FSM = qrst_fsm; +assign PIPE_RATE_FSM = rate_fsm; +assign PIPE_SYNC_FSM_TX = sync_fsm_tx; +assign PIPE_SYNC_FSM_RX = sync_fsm_rx; +assign PIPE_DRP_FSM = drp_fsm; +assign PIPE_QDRP_FSM = 0;//qdrp_fsm; + +assign PIPE_RST_IDLE = &rst_idle; +assign PIPE_QRST_IDLE = &qrst_idle; +assign PIPE_RATE_IDLE = &rate_idle; + +assign EXT_CH_GT_DRPDO = gt_do[(PCIE_LANE*16)-1:0]; +assign EXT_CH_GT_DRPRDY = gt_rdy[(PCIE_LANE-1):0]; +assign EXT_CH_GT_DRPCLK = clk_dclk; + +assign PIPE_DEBUG_0 = (PCIE_DEBUG_MODE == 1) ? gt_txresetdone : {PCIE_LANE{1'b0}}; +assign PIPE_DEBUG_1 = (PCIE_DEBUG_MODE == 1) ? gt_rxresetdone : {PCIE_LANE{1'b0}}; +assign PIPE_DEBUG_2 = (PCIE_DEBUG_MODE == 1) ? gt_phystatus : {PCIE_LANE{1'b0}}; +assign PIPE_DEBUG_3 = (PCIE_DEBUG_MODE == 1) ? gt_rxvalid : {PCIE_LANE{1'b0}}; +assign PIPE_DEBUG_4 = (PCIE_DEBUG_MODE == 1) ? clk_dclk : {PCIE_LANE{1'b0}}; +assign PIPE_DEBUG_5 = (PCIE_DEBUG_MODE == 1) ? drp_mux_en : {PCIE_LANE{1'b0}}; +assign PIPE_DEBUG_6 = (PCIE_DEBUG_MODE == 1) ? drp_mux_we : {PCIE_LANE{1'b0}}; +assign PIPE_DEBUG_7 = (PCIE_DEBUG_MODE == 1) ? gt_rdy : {PCIE_LANE{1'b0}}; +assign PIPE_DEBUG_8 = (PCIE_DEBUG_MODE == 1) ? user_rx_converge : {PCIE_LANE{1'b0}}; +assign PIPE_DEBUG_9 = (PCIE_DEBUG_MODE == 1) ? PIPE_TXELECIDLE : {PCIE_LANE{1'b0}}; + +assign PIPE_DEBUG[ 1:0] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_CONTROL[1:0] : 2'd0; +assign PIPE_DEBUG[ 5:2] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_PRESET[3:0] : 4'd0; +assign PIPE_DEBUG[31:6] = 26'd0; + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_qpll_drp.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_qpll_drp.v new file mode 100644 index 0000000..c5bc9c9 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_qpll_drp.v @@ -0,0 +1,550 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_qpll_drp.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : qpll_drp.v +// Description : QPLL DRP Module for 7 Series Transceiver +// Version : 18.2 +//------------------------------------------------------------------------------ + + + +`timescale 1ns / 1ps + + + +//---------- QPLL DRP Module --------------------------------------------------- +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_qpll_drp # +( + + parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device + parameter PCIE_USE_MODE = "3.0", // PCIe use mode + parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only + parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency + parameter LOAD_CNT_MAX = 2'd3, // Load max count + parameter INDEX_MAX = 3'd6 // Index max count + +) + +( + + //---------- Input ------------------------------------- + input DRP_CLK, + input DRP_RST_N, + input DRP_OVRD, + input DRP_GEN3, + input DRP_QPLLLOCK, + input DRP_START, + input [15:0] DRP_DO, + input DRP_RDY, + + //---------- Output ------------------------------------ + output [ 7:0] DRP_ADDR, + output DRP_EN, + output [15:0] DRP_DI, + output DRP_WE, + output DRP_DONE, + output DRP_QPLLRESET, + output [ 5:0] DRP_CRSCODE, + output [ 8:0] DRP_FSM + +); + + //---------- Input Registers --------------------------- +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2; + + //---------- Internal Signals -------------------------- + reg [ 1:0] load_cnt = 2'd0; + reg [ 2:0] index = 3'd0; + reg mode = 1'd0; + reg [ 5:0] crscode = 6'd0; + + //---------- Output Registers -------------------------- + reg [ 7:0] addr = 8'd0; + reg [15:0] di = 16'd0; + reg done = 1'd0; + reg [ 8:0] fsm = 7'd1; + + //---------- DRP Address ------------------------------- + localparam ADDR_QPLL_FBDIV = 8'h36; + localparam ADDR_QPLL_CFG = 8'h32; + localparam ADDR_QPLL_LPF = 8'h31; + localparam ADDR_CRSCODE = 8'h88; + localparam ADDR_QPLL_COARSE_FREQ_OVRD = 8'h35; + localparam ADDR_QPLL_COARSE_FREQ_OVRD_EN = 8'h36; + localparam ADDR_QPLL_LOCK_CFG = 8'h34; + + //---------- DRP Mask ---------------------------------- + localparam MASK_QPLL_FBDIV = 16'b1111110000000000; // Unmask bit [ 9: 0] + localparam MASK_QPLL_CFG = 16'b1111111110111111; // Unmask bit [ 6] + localparam MASK_QPLL_LPF = 16'b1000011111111111; // Unmask bit [14:11] + localparam MASK_QPLL_COARSE_FREQ_OVRD = 16'b0000001111111111; // Unmask bit [15:10] + localparam MASK_QPLL_COARSE_FREQ_OVRD_EN = 16'b1111011111111111; // Unmask bit [ 11] + localparam MASK_QPLL_LOCK_CFG = 16'b1110011111111111; // Unmask bit [12:11] + + //---------- DRP Data for Normal QPLLLOCK Mode --------- + localparam NORM_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value + localparam NORM_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000000000000000; // Normal QPLL lock + localparam NORM_QPLL_LOCK_CFG = 16'b0000000000000000; // Normal QPLL lock config + + //---------- DRP Data for Optimize QPLLLOCK Mode ------- + localparam OVRD_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value + localparam OVRD_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000100000000000; // Override QPLL lock + localparam OVRD_QPLL_LOCK_CFG = 16'b0000000000000000; // Override QPLL lock config + + //---------- Select QPLL Feedback Divider -------------- + // N = 100 for 100 MHz ref clk and 10Gb/s line rate + // N = 80 for 125 MHz ref clk and 10Gb/s line rate + // N = 40 for 250 MHz ref clk and 10Gb/s line rate + //------------------------------------------------------ + // N = 80 for 100 MHz ref clk and 8Gb/s line rate + // N = 64 for 125 MHz ref clk and 8Gb/s line rate + // N = 32 for 250 MHz ref clk and 8Gb/s line rate + //------------------------------------------------------ + localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000010000000 : + (PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000100100000 : + (PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000101110000 : + (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000001100000 : + (PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000011100000 : 16'b0000000100100000; + + localparam GEN12_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000010000000 : + (PCIE_REFCLK_FREQ == 1) ? 16'b0000000100100000 : 16'b0000000101110000; + + localparam GEN3_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000001100000 : + (PCIE_REFCLK_FREQ == 1) ? 16'b0000000011100000 : 16'b0000000100100000; + + //---------- Select QPLL Configuration --------------------------- + // QPLL_CFG[6] = 0 for upper band + // = 1 for lower band + //---------------------------------------------------------------- + localparam GEN12_QPLL_CFG = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000000 : 16'b0000000001000000; + localparam GEN3_QPLL_CFG = 16'b0000000001000000; + + //---------- Select QPLL LPF ------------------------------------- + localparam GEN12_QPLL_LPF = (PCIE_PLL_SEL == "QPLL") ? 16'b0_0100_00000000000 : 16'b0_1101_00000000000; + localparam GEN3_QPLL_LPF = 16'b0_1101_00000000000; + + + + //---------- DRP Data ---------------------------------- + wire [15:0] data_qpll_fbdiv; + wire [15:0] data_qpll_cfg; + wire [15:0] data_qpll_lpf; + wire [15:0] data_qpll_coarse_freq_ovrd; + wire [15:0] data_qpll_coarse_freq_ovrd_en; + wire [15:0] data_qpll_lock_cfg; + + //---------- FSM --------------------------------------- + localparam FSM_IDLE = 9'b000000001; + localparam FSM_LOAD = 9'b000000010; + localparam FSM_READ = 9'b000000100; + localparam FSM_RRDY = 9'b000001000; + localparam FSM_WRITE = 9'b000010000; + localparam FSM_WRDY = 9'b000100000; + localparam FSM_DONE = 9'b001000000; + localparam FSM_QPLLRESET = 9'b010000000; + localparam FSM_QPLLLOCK = 9'b100000000; + + + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge DRP_CLK) +begin + + if (!DRP_RST_N) + begin + //---------- 1st Stage FF -------------------------- + ovrd_reg1 <= 1'd0; + gen3_reg1 <= 1'd0; + qplllock_reg1 <= 1'd0; + start_reg1 <= 1'd0; + do_reg1 <= 16'd0; + rdy_reg1 <= 1'd0; + //---------- 2nd Stage FF -------------------------- + ovrd_reg2 <= 1'd0; + gen3_reg2 <= 1'd0; + qplllock_reg2 <= 1'd0; + start_reg2 <= 1'd0; + do_reg2 <= 16'd0; + rdy_reg2 <= 1'd0; + end + + else + begin + //---------- 1st Stage FF -------------------------- + ovrd_reg1 <= DRP_OVRD; + gen3_reg1 <= DRP_GEN3; + qplllock_reg1 <= DRP_QPLLLOCK; + start_reg1 <= DRP_START; + do_reg1 <= DRP_DO; + rdy_reg1 <= DRP_RDY; + //---------- 2nd Stage FF -------------------------- + ovrd_reg2 <= ovrd_reg1; + gen3_reg2 <= gen3_reg1; + qplllock_reg2 <= qplllock_reg1; + start_reg2 <= start_reg1; + do_reg2 <= do_reg1; + rdy_reg2 <= rdy_reg1; + end + +end + + + +//---------- Select DRP Data --------------------------------------------------- +assign data_qpll_fbdiv = (gen3_reg2) ? GEN3_QPLL_FBDIV : GEN12_QPLL_FBDIV; +assign data_qpll_cfg = (gen3_reg2) ? GEN3_QPLL_CFG : GEN12_QPLL_CFG; +assign data_qpll_lpf = (gen3_reg2) ? GEN3_QPLL_LPF : GEN12_QPLL_LPF; +assign data_qpll_coarse_freq_ovrd = NORM_QPLL_COARSE_FREQ_OVRD; +assign data_qpll_coarse_freq_ovrd_en = (ovrd_reg2) ? OVRD_QPLL_COARSE_FREQ_OVRD_EN : NORM_QPLL_COARSE_FREQ_OVRD_EN; +assign data_qpll_lock_cfg = (ovrd_reg2) ? OVRD_QPLL_LOCK_CFG : NORM_QPLL_LOCK_CFG; + + +//---------- Load Counter ------------------------------------------------------ +always @ (posedge DRP_CLK) +begin + + if (!DRP_RST_N) + load_cnt <= 2'd0; + else + + //---------- Increment Load Counter ---------------- + if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX)) + load_cnt <= load_cnt + 2'd1; + + //---------- Hold Load Counter --------------------- + else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX)) + load_cnt <= load_cnt; + + //---------- Reset Load Counter -------------------- + else + load_cnt <= 2'd0; + +end + + + +//---------- Update DRP Address and Data --------------------------------------- +always @ (posedge DRP_CLK) +begin + + if (!DRP_RST_N) + begin + addr <= 8'd0; + di <= 16'd0; + crscode <= 6'd0; + end + else + begin + + case (index) + + //-------------------------------------------------- + 3'd0 : + begin + addr <= ADDR_QPLL_FBDIV; + di <= (do_reg2 & MASK_QPLL_FBDIV) | (mode ? data_qpll_fbdiv : QPLL_FBDIV); + crscode <= crscode; + end + + //-------------------------------------------------- + 3'd1 : + begin + addr <= ADDR_QPLL_CFG; + if (PCIE_GT_DEVICE == "GTX") + di <= (do_reg2 & MASK_QPLL_CFG) | data_qpll_cfg; + else + di <= (do_reg2 & 16'hFFFF) | data_qpll_cfg; + crscode <= crscode; + end + + //-------------------------------------------------- + 3'd2 : + begin + addr <= ADDR_QPLL_LPF; + if (PCIE_GT_DEVICE == "GTX") + di <= (do_reg2 & MASK_QPLL_LPF) | data_qpll_lpf; + else + di <= (do_reg2 & 16'hFFFF) | data_qpll_lpf; + crscode <= crscode; + end + + //-------------------------------------------------- + 3'd3 : + begin + addr <= ADDR_CRSCODE; + di <= do_reg2; + + //---------- Latch CRS Code -------------------- + if (ovrd_reg2) + crscode <= do_reg2[6:1]; + else + crscode <= crscode; + end + + //-------------------------------------------------- + 3'd4 : + begin + addr <= ADDR_QPLL_COARSE_FREQ_OVRD; + di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD) | {(crscode - 6'd1), data_qpll_coarse_freq_ovrd[9:0]}; + crscode <= crscode; + end + + //-------------------------------------------------- + 3'd5 : + begin + addr <= ADDR_QPLL_COARSE_FREQ_OVRD_EN; + di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD_EN) | data_qpll_coarse_freq_ovrd_en; + crscode <= crscode; + end + + //-------------------------------------------------- + 3'd6 : + begin + addr <= ADDR_QPLL_LOCK_CFG; + di <= (do_reg2 & MASK_QPLL_LOCK_CFG) | data_qpll_lock_cfg; + crscode <= crscode; + end + + //-------------------------------------------------- + default : + begin + addr <= 8'd0; + di <= 16'd0; + crscode <= 6'd0; + end + + endcase + + end + +end + + + +//---------- QPLL DRP FSM ------------------------------------------------------ +always @ (posedge DRP_CLK) +begin + + if (!DRP_RST_N) + begin + fsm <= FSM_IDLE; + index <= 3'd0; + mode <= 1'd0; + done <= 1'd0; + end + else + begin + + case (fsm) + + //---------- Idle State ---------------------------- + FSM_IDLE : + + begin + if (start_reg2) + begin + fsm <= FSM_LOAD; + index <= 3'd0; + mode <= 1'd0; + done <= 1'd0; + end + else if ((gen3_reg2 != gen3_reg1) && (PCIE_PLL_SEL == "QPLL")) + begin + fsm <= FSM_LOAD; + index <= 3'd0; + mode <= 1'd1; + done <= 1'd0; + end + else + begin + fsm <= FSM_IDLE; + index <= 3'd0; + mode <= 1'd0; + done <= 1'd1; + end + end + + //---------- Load DRP Address --------------------- + FSM_LOAD : + + begin + fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD; + index <= index; + mode <= mode; + done <= 1'd0; + end + + //---------- Read DRP ------------------------------ + FSM_READ : + + begin + fsm <= FSM_RRDY; + index <= index; + mode <= mode; + done <= 1'd0; + end + + //---------- Read DRP Ready ------------------------ + FSM_RRDY : + + begin + fsm <= (rdy_reg2 ? FSM_WRITE : FSM_RRDY); + index <= index; + mode <= mode; + done <= 1'd0; + end + + //---------- Write DRP ----------------------------- + FSM_WRITE : + + begin + fsm <= FSM_WRDY; + index <= index; + mode <= mode; + done <= 1'd0; + end + + //---------- Write DRP Ready ----------------------- + FSM_WRDY : + + begin + fsm <= (rdy_reg2 ? FSM_DONE : FSM_WRDY); + index <= index; + mode <= mode; + done <= 1'd0; + end + + //---------- DRP Done ------------------------------ + FSM_DONE : + + begin + if ((index == INDEX_MAX) || (mode && (index == 3'd2))) + begin + fsm <= mode ? FSM_QPLLRESET : FSM_IDLE; + index <= 3'd0; + mode <= mode; + done <= 1'd0; + end + else + begin + fsm <= FSM_LOAD; + index <= index + 3'd1; + mode <= mode; + done <= 1'd0; + end + end + + //---------- QPLL Reset ---------------------------- + FSM_QPLLRESET : + + begin + fsm <= !qplllock_reg2 ? FSM_QPLLLOCK : FSM_QPLLRESET; + index <= 3'd0; + mode <= mode; + done <= 1'd0; + end + + //---------- QPLL Reset ---------------------------- + FSM_QPLLLOCK : + + begin + fsm <= qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK; + index <= 3'd0; + mode <= mode; + done <= 1'd0; + end + + //---------- Default State ------------------------- + default : + + begin + fsm <= FSM_IDLE; + index <= 3'd0; + mode <= 1'd0; + done <= 1'd0; + end + + endcase + + end + +end + + + +//---------- QPLL DRP Output --------------------------------------------------- +assign DRP_ADDR = addr; +assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE); +assign DRP_DI = di; +assign DRP_WE = (fsm == FSM_WRITE); // || (fsm == FSM_WRDY); +assign DRP_DONE = done; +assign DRP_QPLLRESET = (fsm == FSM_QPLLRESET); +assign DRP_CRSCODE = crscode; +assign DRP_FSM = fsm; + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_qpll_reset.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_qpll_reset.v new file mode 100644 index 0000000..329f953 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_qpll_reset.v @@ -0,0 +1,370 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_qpll_reset.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : qpll_reset.v +// Description : QPLL Reset Module for 7 Series Transceiver +// Version : 11.4 +//------------------------------------------------------------------------------ + + +`timescale 1ns / 1ps + + + +//---------- QPLL Reset Module -------------------------------------------------- +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_qpll_reset # +( + + //---------- Global ------------------------------------ + parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only + parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving + parameter PCIE_LANE = 1, // PCIe number of lanes + parameter BYPASS_COARSE_OVRD = 1 // Bypass coarse frequency override + +) + +( + + //---------- Input ------------------------------------- + input QRST_CLK, + input QRST_RST_N, + input QRST_MMCM_LOCK, + input [PCIE_LANE-1:0] QRST_CPLLLOCK, + input [(PCIE_LANE-1)>>2:0]QRST_DRP_DONE, + input [(PCIE_LANE-1)>>2:0]QRST_QPLLLOCK, + input [ 1:0] QRST_RATE, + input [PCIE_LANE-1:0] QRST_QPLLRESET_IN, + input [PCIE_LANE-1:0] QRST_QPLLPD_IN, + + //---------- Output ------------------------------------ + output QRST_OVRD, + output QRST_DRP_START, + output QRST_QPLLRESET_OUT, + output QRST_QPLLPD_OUT, + output QRST_IDLE, + output [3:0] QRST_FSM + +); + + //---------- Input Register ---------------------------- +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg2; + + //---------- Output Register -------------------------- + reg ovrd = 1'd0; + reg qpllreset = 1'd1; + reg qpllpd = 1'd0; + reg [3:0] fsm = 2; + + //---------- FSM --------------------------------------- + localparam FSM_IDLE = 1;//12'b000000000001; + localparam FSM_WAIT_LOCK = 2;//12'b000000000010; + localparam FSM_MMCM_LOCK = 3;//12'b000000000100; + localparam FSM_DRP_START_NOM = 4;//12'b000000001000; + localparam FSM_DRP_DONE_NOM = 5;//12'b000000010000; + localparam FSM_QPLLLOCK = 6;//12'b000000100000; + localparam FSM_DRP_START_OPT = 7;//12'b000001000000; + localparam FSM_DRP_DONE_OPT = 8;//12'b000010000000; + localparam FSM_QPLL_RESET = 9;//12'b000100000000; + localparam FSM_QPLLLOCK2 = 10;//12'b001000000000; + localparam FSM_QPLL_PDRESET = 11;//12'b010000000000; + localparam FSM_QPLL_PD = 12;//12'b100000000000; + + + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge QRST_CLK) +begin + + if (!QRST_RST_N) + begin + //---------- 1st Stage FF -------------------------- + mmcm_lock_reg1 <= 1'd0; + cplllock_reg1 <= {PCIE_LANE{1'd1}}; + drp_done_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}}; + qplllock_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}}; + rate_reg1 <= 2'd0; + qpllreset_in_reg1 <= {PCIE_LANE{1'd1}}; + qpllpd_in_reg1 <= {PCIE_LANE{1'd0}}; + //---------- 2nd Stage FF -------------------------- + mmcm_lock_reg2 <= 1'd0; + cplllock_reg2 <= {PCIE_LANE{1'd1}}; + drp_done_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}}; + qplllock_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}}; + rate_reg2 <= 2'd0; + qpllreset_in_reg2 <= {PCIE_LANE{1'd1}}; + qpllpd_in_reg2 <= {PCIE_LANE{1'd0}}; + end + else + begin + //---------- 1st Stage FF -------------------------- + mmcm_lock_reg1 <= QRST_MMCM_LOCK; + cplllock_reg1 <= QRST_CPLLLOCK; + drp_done_reg1 <= QRST_DRP_DONE; + qplllock_reg1 <= QRST_QPLLLOCK; + rate_reg1 <= QRST_RATE; + qpllreset_in_reg1 <= QRST_QPLLRESET_IN; + qpllpd_in_reg1 <= QRST_QPLLPD_IN; + //---------- 2nd Stage FF -------------------------- + mmcm_lock_reg2 <= mmcm_lock_reg1; + cplllock_reg2 <= cplllock_reg1; + drp_done_reg2 <= drp_done_reg1; + qplllock_reg2 <= qplllock_reg1; + rate_reg2 <= rate_reg1; + qpllreset_in_reg2 <= qpllreset_in_reg1; + qpllpd_in_reg2 <= qpllpd_in_reg1; + end + +end + + + +//---------- QPLL Reset FSM ---------------------------------------------------- +always @ (posedge QRST_CLK) +begin + + if (!QRST_RST_N) + begin + fsm <= FSM_WAIT_LOCK; + ovrd <= 1'd0; + qpllreset <= 1'd1; + qpllpd <= 1'd0; + end + else + begin + + case (fsm) + + //---------- Idle State ---------------------------- + FSM_IDLE : + + begin + if (!QRST_RST_N) + begin + fsm <= FSM_WAIT_LOCK; + ovrd <= 1'd0; + qpllreset <= 1'd1; + qpllpd <= 1'd0; + end + else + begin + fsm <= FSM_IDLE; + ovrd <= ovrd; + qpllreset <= &qpllreset_in_reg2; + qpllpd <= &qpllpd_in_reg2; + end + end + + //---------- Wait for CPLL and QPLL to Lose Lock --- + FSM_WAIT_LOCK : + + begin + fsm <= ((&(~cplllock_reg2)) && (&(~qplllock_reg2)) ? FSM_MMCM_LOCK : FSM_WAIT_LOCK); + ovrd <= ovrd; + qpllreset <= qpllreset; + qpllpd <= qpllpd; + end + + //---------- Wait for MMCM and CPLL Lock ----------- + FSM_MMCM_LOCK : + + begin + fsm <= ((mmcm_lock_reg2 && (&cplllock_reg2)) ? FSM_DRP_START_NOM : FSM_MMCM_LOCK); + ovrd <= ovrd; + qpllreset <= qpllreset; + qpllpd <= qpllpd; + end + + //---------- Start QPLL DRP for Normal QPLL Lock Mode + FSM_DRP_START_NOM: + + begin + fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_NOM : FSM_DRP_START_NOM); + ovrd <= ovrd; + qpllreset <= qpllreset; + qpllpd <= qpllpd; + end + + //---------- Wait for QPLL DRP Done ---------------- + FSM_DRP_DONE_NOM : + + begin + fsm <= (&drp_done_reg2 ? FSM_QPLLLOCK : FSM_DRP_DONE_NOM); + ovrd <= ovrd; + qpllreset <= qpllreset; + qpllpd <= qpllpd; + end + + //---------- Wait for QPLL Lock -------------------- + FSM_QPLLLOCK : + + begin + fsm <= (&qplllock_reg2 ? ((BYPASS_COARSE_OVRD == 1) ? FSM_QPLL_PDRESET : FSM_DRP_START_OPT) : FSM_QPLLLOCK); + ovrd <= ovrd; + qpllreset <= 1'd0; + qpllpd <= qpllpd; + end + + //---------- Start QPLL DRP for Optimized QPLL Lock Mode + FSM_DRP_START_OPT: + + begin + fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_OPT : FSM_DRP_START_OPT); + ovrd <= 1'd1; + qpllreset <= qpllreset; + qpllpd <= qpllpd; + end + + //---------- Wait for QPLL DRP Done ---------------- + FSM_DRP_DONE_OPT : + + begin + if (&drp_done_reg2) + begin + fsm <= ((PCIE_PLL_SEL == "QPLL") ? FSM_QPLL_RESET : FSM_QPLL_PDRESET); + ovrd <= ovrd; + qpllreset <= (PCIE_PLL_SEL == "QPLL"); + qpllpd <= qpllpd; + end + else + begin + fsm <= FSM_DRP_DONE_OPT; + ovrd <= ovrd; + qpllreset <= qpllreset; + qpllpd <= qpllpd; + end + end + + //---------- Reset QPLL ---------------------------- + FSM_QPLL_RESET : + + begin + fsm <= (&(~qplllock_reg2) ? FSM_QPLLLOCK2 : FSM_QPLL_RESET); + ovrd <= ovrd; + qpllreset <= 1'd1; + qpllpd <= 1'd0; + end + + //---------- Wait for QPLL Lock -------------------- + FSM_QPLLLOCK2 : + + begin + fsm <= (&qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK2); + ovrd <= ovrd; + qpllreset <= 1'd0; + qpllpd <= 1'd0; + end + + //---------- Hold QPLL in Reset -------------------- + FSM_QPLL_PDRESET : + + begin + fsm <= FSM_QPLL_PD; + ovrd <= ovrd; + qpllreset <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0; + qpllpd <= qpllpd; + end + + //---------- Power-down QPLL ----------------------- + FSM_QPLL_PD : + + begin + fsm <= FSM_IDLE; + ovrd <= ovrd; + qpllreset <= qpllreset; + qpllpd <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0; + end + + //---------- Default State ------------------------- + default : + + begin + fsm <= FSM_WAIT_LOCK; + ovrd <= 1'd0; + qpllreset <= 1'd0; + qpllpd <= 1'd0; + end + + endcase + + end + +end + + + +//---------- QPLL Lock Output -------------------------------------------------- +assign QRST_OVRD = ovrd; +assign QRST_DRP_START = (fsm == FSM_DRP_START_NOM) || (fsm == FSM_DRP_START_OPT); +assign QRST_QPLLRESET_OUT = qpllreset; +assign QRST_QPLLPD_OUT = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd); +assign QRST_IDLE = (fsm == FSM_IDLE); +assign QRST_FSM = fsm; + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_qpll_wrapper.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_qpll_wrapper.v new file mode 100644 index 0000000..ef5649d --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_qpll_wrapper.v @@ -0,0 +1,439 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_qpll_wrapper.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : qpll_wrapper.v +// Description : QPLL Wrapper Module for 7 Series Transceiver +// Version : 18.1 +//------------------------------------------------------------------------------ + + + +`timescale 1ns / 1ps + + + +//---------- QPLL Wrapper ---------------------------------------------------- +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_qpll_wrapper # +( + + parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode + parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device + parameter PCIE_USE_MODE = "3.0", // PCIe use mode + parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only + parameter PCIE_REFCLK_FREQ = 0 // PCIe reference clock frequency + +) + +( + + //---------- QPLL Clock Ports -------------------------- + input QPLL_CPLLPDREFCLK, + input QPLL_GTGREFCLK, + input QPLL_QPLLLOCKDETCLK, + + output QPLL_QPLLOUTCLK, + output QPLL_QPLLOUTREFCLK, + output QPLL_QPLLLOCK, + + //---------- QPLL Reset Ports -------------------------- + input QPLL_QPLLPD, + input QPLL_QPLLRESET, + + //---------- QPLL DRP Ports ---------------------------- + input QPLL_DRPCLK, + input [ 7:0] QPLL_DRPADDR, + input QPLL_DRPEN, + input [15:0] QPLL_DRPDI, + input QPLL_DRPWE, + + output [15:0] QPLL_DRPDO, + output QPLL_DRPRDY + +); + + + + //---------- Select QPLL Feedback Divider -------------- + // N = 100 for 100 MHz ref clk and 10Gb/s line rate + // N = 80 for 125 MHz ref clk and 10Gb/s line rate + // N = 40 for 250 MHz ref clk and 10Gb/s line rate + //------------------------------------------------------ + // N = 80 for 100 MHz ref clk and 8Gb/s line rate + // N = 64 for 125 MHz ref clk and 8Gb/s line rate + // N = 32 for 250 MHz ref clk and 8Gb/s line rate + //------------------------------------------------------ + localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 10'b0010000000 : + (PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 10'b0100100000 : + (PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 10'b0101110000 : + (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 10'b0001100000 : + (PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 10'b0011100000 : 10'b0100100000; + + //---------- Select GTP QPLL Feedback Divider ---------- + localparam GTP_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 3'd2 : + (PCIE_REFCLK_FREQ == 1) ? 3'd4 : 3'd5; + + //---------- Select BIAS_CFG --------------------------- + localparam BIAS_CFG = ((PCIE_USE_MODE == "1.0") && (PCIE_PLL_SEL == "CPLL")) ? 64'h0000042000001000 : 64'h0000040000001000; + + + wire cpllpd; + wire cpllrst; + +//---------- Select GTX or GTH or GTP ------------------------------------------ +// Notes : Attributes that are commented out uses the GT default settings +//------------------------------------------------------------------------------ +generate if (PCIE_GT_DEVICE == "GTP") + + //---------- GTP Common ---------------------------------------------------- + begin : gtp_common + + //---------- GTP Common Module --------------------------------------------- + GTPE2_COMMON # + ( + + //---------- Simulation Attributes ------------------------------------- + .SIM_PLL0REFCLK_SEL (3'b001), // + .SIM_PLL1REFCLK_SEL (3'b001), // + .SIM_RESET_SPEEDUP (PCIE_SIM_MODE), // + .SIM_VERSION (PCIE_USE_MODE), // + + //---------- Clock Attributes ------------------------------------------ + .PLL0_CFG (27'h01F024C), // Optimized for IES + .PLL1_CFG (27'h01F024C), // Optimized for IES + .PLL_CLKOUT_CFG (8'd0), // Optimized for IES + .PLL0_DMON_CFG (1'b0), // Optimized for IES + .PLL1_DMON_CFG (1'b0), // Optimized for IES + .PLL0_FBDIV (GTP_QPLL_FBDIV), // Optimized for IES + .PLL1_FBDIV (GTP_QPLL_FBDIV), // Optimized for IES + .PLL0_FBDIV_45 (5), // Optimized for IES + .PLL1_FBDIV_45 (5), // Optimized for IES + .PLL0_INIT_CFG (24'h00001E), // Optimized for IES + .PLL1_INIT_CFG (24'h00001E), // Optimized for IES + .PLL0_LOCK_CFG ( 9'h1E8), // Optimized for IES + .PLL1_LOCK_CFG ( 9'h1E8), // Optimized for IES + .PLL0_REFCLK_DIV (1), // Optimized for IES + .PLL1_REFCLK_DIV (1), // Optimized for IES + + //---------- MISC ------------------------------------------------------ + .BIAS_CFG (64'h0000000000050001), // Optimized for GES + //.COMMON_CFG (32'd0), // + .RSVD_ATTR0 (16'd0), // + .RSVD_ATTR1 (16'd0) // + + ) + gtpe2_common_i + ( + + //---------- Clock ----------------------------------------------------- + .GTGREFCLK0 ( 1'd0), // + .GTGREFCLK1 ( 1'd0), // + .GTREFCLK0 (QPLL_GTGREFCLK), // + .GTREFCLK1 ( 1'd0), // + .GTEASTREFCLK0 ( 1'd0), // + .GTEASTREFCLK1 ( 1'd0), // + .GTWESTREFCLK0 ( 1'd0), // + .GTWESTREFCLK1 ( 1'd0), // + .PLL0LOCKDETCLK (QPLL_QPLLLOCKDETCLK), // + .PLL1LOCKDETCLK (QPLL_QPLLLOCKDETCLK), // + .PLL0LOCKEN ( 1'd1), // + .PLL1LOCKEN ( 1'd1), // + .PLL0REFCLKSEL ( 3'd1), // Optimized for IES + .PLL1REFCLKSEL ( 3'd1), // Optimized for IES + .PLLRSVD1 (16'd0), // Optimized for IES + .PLLRSVD2 ( 5'd0), // Optimized for IES + + .PLL0OUTCLK (QPLL_QPLLOUTCLK), // + .PLL1OUTCLK (), // + .PLL0OUTREFCLK (QPLL_QPLLOUTREFCLK), // + .PLL1OUTREFCLK (), // + .PLL0LOCK (QPLL_QPLLLOCK), // + .PLL1LOCK (), // + .PLL0FBCLKLOST (), // + .PLL1FBCLKLOST (), // + .PLL0REFCLKLOST (), // + .PLL1REFCLKLOST (), // + .DMONITOROUT (), // + + //---------- Reset ----------------------------------------------------- + .PLL0PD (cpllpd | QPLL_QPLLPD), // + .PLL1PD ( 1'd1), // + .PLL0RESET (cpllrst | QPLL_QPLLRESET), // + .PLL1RESET ( 1'd1), // + + //---------- DRP ------------------------------------------------------- + .DRPCLK (QPLL_DRPCLK), // + .DRPADDR (QPLL_DRPADDR), // + .DRPEN (QPLL_DRPEN), // + .DRPDI (QPLL_DRPDI), // + .DRPWE (QPLL_DRPWE), // + + .DRPDO (QPLL_DRPDO), // + .DRPRDY (QPLL_DRPRDY), // + + //---------- Band Gap -------------------------------------------------- + .BGBYPASSB ( 1'd1), // Optimized for IES + .BGMONITORENB ( 1'd1), // Optimized for IES + .BGPDB ( 1'd1), // Optimized for IES + .BGRCALOVRD ( 5'd31), // Optimized for IES + .BGRCALOVRDENB ( 1'd1), // Optimized for IES + + //---------- MISC ------------------------------------------------------ + .PMARSVD ( 8'd0), // + .RCALENB ( 1'd1), // Optimized for IES + + .REFCLKOUTMONITOR0 (), // + .REFCLKOUTMONITOR1 (), // + .PMARSVDOUT () // + + ); + + end + +else if (PCIE_GT_DEVICE == "GTH") + + //---------- GTH Common ---------------------------------------------------- + begin : gth_common + + //---------- GTX Common Module --------------------------------------------- + GTHE2_COMMON # + ( + + //---------- Simulation Attributes ------------------------------------- + .SIM_QPLLREFCLK_SEL (3'b001), // + .SIM_RESET_SPEEDUP (PCIE_SIM_MODE), // + .SIM_VERSION ("2.0"), // + + //---------- Clock Attributes ------------------------------------------ + .QPLL_CFG (27'h04801C7), // QPLL for Gen3, optimized for GES + .QPLL_CLKOUT_CFG ( 4'b1111), // Optimized for GES + .QPLL_COARSE_FREQ_OVRD ( 6'b010000), // + .QPLL_COARSE_FREQ_OVRD_EN ( 1'd0), // + .QPLL_CP (10'h0FF), // * Optimized for IES and PCIe PLL BW + .QPLL_CP_MONITOR_EN ( 1'd0), // + .QPLL_DMONITOR_SEL ( 1'd0), // + .QPLL_FBDIV (QPLL_FBDIV), // + .QPLL_FBDIV_MONITOR_EN ( 1'd0), // + .QPLL_FBDIV_RATIO ( 1'd1), // Optimized + .QPLL_INIT_CFG (24'h000006), // + .QPLL_LOCK_CFG (16'h05E8), // Optimized for IES + .QPLL_LPF ( 4'hD), // Optimized for IES, [1:0] = 2'b00 (13.3 KOhm), [1:0] = 2'b01 (57.0 KOhm) + .QPLL_REFCLK_DIV ( 1), // + .QPLL_RP_COMP ( 1'd0), // GTH new + .QPLL_VTRL_RESET ( 2'd0), // GTH new + + //---------- MISC ------------------------------------------------------ + .BIAS_CFG (64'h0000040000001050), // Optimized for GES + .COMMON_CFG (32'd0), // + .RCAL_CFG ( 2'b00), // GTH new + .RSVD_ATTR0 (16'd0), // GTH + .RSVD_ATTR1 (16'd0) // GTH + ) + gthe2_common_i + ( + + //---------- Clock ----------------------------------------------------- + .GTGREFCLK ( 1'd0), // + .GTREFCLK0 (QPLL_GTGREFCLK), // + .GTREFCLK1 ( 1'd0), // + .GTNORTHREFCLK0 ( 1'd0), // + .GTNORTHREFCLK1 ( 1'd0), // + .GTSOUTHREFCLK0 ( 1'd0), // + .GTSOUTHREFCLK1 ( 1'd0), // + .QPLLLOCKDETCLK (QPLL_QPLLLOCKDETCLK), // + .QPLLLOCKEN ( 1'd1), // + .QPLLREFCLKSEL ( 3'd1), // + .QPLLRSVD1 (16'd0), // + .QPLLRSVD2 ( 5'b11111), // + + .QPLLOUTCLK (QPLL_QPLLOUTCLK), // + .QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), // + .QPLLLOCK (QPLL_QPLLLOCK), // + .QPLLFBCLKLOST (), // + .QPLLREFCLKLOST (), // + .QPLLDMONITOR (), // + + //---------- Reset ----------------------------------------------------- + .QPLLPD (QPLL_QPLLPD), // + .QPLLRESET (QPLL_QPLLRESET), // + .QPLLOUTRESET ( 1'd0), // + + //---------- DRP ------------------------------------------------------- + .DRPCLK (QPLL_DRPCLK), // + .DRPADDR (QPLL_DRPADDR), // + .DRPEN (QPLL_DRPEN), // + .DRPDI (QPLL_DRPDI), // + .DRPWE (QPLL_DRPWE), // + + .DRPDO (QPLL_DRPDO), // + .DRPRDY (QPLL_DRPRDY), // + + //---------- Band Gap -------------------------------------------------- + .BGBYPASSB ( 1'd1), // Optimized for IES + .BGMONITORENB ( 1'd1), // Optimized for IES + .BGPDB ( 1'd1), // Optimized for IES + .BGRCALOVRD ( 5'd31), // Optimized for IES + .BGRCALOVRDENB ( 1'd1), // GTH, Optimized for IES + + //---------- MISC ------------------------------------------------------ + .PMARSVD ( 8'd0), // + .RCALENB ( 1'd1), // Optimized for IES + + .REFCLKOUTMONITOR (), // + .PMARSVDOUT () // GTH + + ); + + end + +else + + //---------- GTX Common ---------------------------------------------------- + begin : gtx_common + + //---------- GTX Common Module --------------------------------------------- + GTXE2_COMMON # + ( + + //---------- Simulation Attributes ------------------------------------- + .SIM_QPLLREFCLK_SEL ( 3'b001), // + .SIM_RESET_SPEEDUP (PCIE_SIM_MODE), // + .SIM_VERSION (PCIE_USE_MODE), // + + //---------- Clock Attributes ------------------------------------------ + .QPLL_CFG (27'h06801C1), // QPLL for Gen3, Optimized for silicon, + //.QPLL_CLKOUT_CFG ( 4'd0), // + .QPLL_COARSE_FREQ_OVRD ( 6'b010000), // + .QPLL_COARSE_FREQ_OVRD_EN ( 1'd0), // + .QPLL_CP (10'h01F), // Optimized for Gen3 compliance (Gen1/Gen2 = 10'h1FF) + .QPLL_CP_MONITOR_EN ( 1'd0), // + .QPLL_DMONITOR_SEL ( 1'd0), // + .QPLL_FBDIV (QPLL_FBDIV), // + .QPLL_FBDIV_MONITOR_EN ( 1'd0), // + .QPLL_FBDIV_RATIO ( 1'd1), // Optimized for silicon + //.QPLL_INIT_CFG (24'h000006), // + .QPLL_LOCK_CFG (16'h21E8), // Optimized for silicon, IES = 16'h01D0, GES 16'h21D0 + .QPLL_LPF ( 4'hD), // Optimized for silicon, [1:0] = 2'b00 (13.3 KOhm), [1:0] = 2'b01 (57.0 KOhm) + .QPLL_REFCLK_DIV (1), // + + //---------- MISC ------------------------------------------------------ + .BIAS_CFG (BIAS_CFG) // Optimized for silicon + //.COMMON_CFG (32'd0) // + + ) + gtxe2_common_i + ( + + //---------- Clock ----------------------------------------------------- + .GTGREFCLK ( 1'd0), // + .GTREFCLK0 (QPLL_GTGREFCLK), // + .GTREFCLK1 ( 1'd0), // + .GTNORTHREFCLK0 ( 1'd0), // + .GTNORTHREFCLK1 ( 1'd0), // + .GTSOUTHREFCLK0 ( 1'd0), // + .GTSOUTHREFCLK1 ( 1'd0), // + .QPLLLOCKDETCLK (QPLL_QPLLLOCKDETCLK), // + .QPLLLOCKEN ( 1'd1), // + .QPLLREFCLKSEL ( 3'd1), // + .QPLLRSVD1 (16'd0), // + .QPLLRSVD2 ( 5'b11111), // + + .QPLLOUTCLK (QPLL_QPLLOUTCLK), // + .QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), // + .QPLLLOCK (QPLL_QPLLLOCK), // + .QPLLFBCLKLOST (), // + .QPLLREFCLKLOST (), // + .QPLLDMONITOR (), // + + //---------- Reset ----------------------------------------------------- + .QPLLPD (QPLL_QPLLPD), // + .QPLLRESET (QPLL_QPLLRESET), // + .QPLLOUTRESET ( 1'd0), // + + //---------- DRP ------------------------------------------------------- + .DRPCLK (QPLL_DRPCLK), // + .DRPADDR (QPLL_DRPADDR), // + .DRPEN (QPLL_DRPEN), // + .DRPDI (QPLL_DRPDI), // + .DRPWE (QPLL_DRPWE), // + + .DRPDO (QPLL_DRPDO), // + .DRPRDY (QPLL_DRPRDY), // + + //---------- Band Gap -------------------------------------------------- + .BGBYPASSB ( 1'd1), // + .BGMONITORENB ( 1'd1), // + .BGPDB ( 1'd1), // + .BGRCALOVRD ( 5'd31), // + + //---------- MISC ------------------------------------------------------ + .PMARSVD ( 8'd0), // + .RCALENB ( 1'd1), // Optimized for GES + + .REFCLKOUTMONITOR () // + + ); + + end + +endgenerate + +pcie_7x_0_gtp_cpllpd_ovrd cpllPDInst ( + .i_ibufds_gte2(QPLL_CPLLPDREFCLK), + .o_cpllpd_ovrd(cpllpd), + .o_cpllreset_ovrd(cpllrst)); + + +endmodule + + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_rxeq_scan.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_rxeq_scan.v new file mode 100644 index 0000000..bb355a4 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_rxeq_scan.v @@ -0,0 +1,366 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : pcie_7x_0_rxeq_scan.v +// Version : 3.3 +//------------------------------------------------------------------------------ +// Filename : rxeq_scan.v +// Description : PIPE RX Equalization Eye Scan Module for 7 Series Transceiver +// Version : 18.0 +//------------------------------------------------------------------------------ + + +`timescale 1ns / 1ps + + + +//---------- RXEQ Eye Scan Module ---------------------------------------------- +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0_rxeq_scan # +( + + parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode + parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device + parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode + parameter CONVERGE_MAX = 22'd3125000, // Convergence max count (12ms) + parameter CONVERGE_MAX_BYPASS = 22'd2083333 // Convergence max count for phase2/3 bypass mode (8ms) +) + +( + + //---------- Input ------------------------------------- + input RXEQSCAN_CLK, + input RXEQSCAN_RST_N, + + input [ 1:0] RXEQSCAN_CONTROL, + input [ 2:0] RXEQSCAN_PRESET, + input RXEQSCAN_PRESET_VALID, + input [ 3:0] RXEQSCAN_TXPRESET, + input [17:0] RXEQSCAN_TXCOEFF, + input RXEQSCAN_NEW_TXCOEFF_REQ, + input [ 5:0] RXEQSCAN_FS, + input [ 5:0] RXEQSCAN_LF, + + + //---------- Output ------------------------------------ + output RXEQSCAN_PRESET_DONE, + output [17:0] RXEQSCAN_NEW_TXCOEFF, + output RXEQSCAN_NEW_TXCOEFF_DONE, + output RXEQSCAN_LFFS_SEL, + output RXEQSCAN_ADAPT_DONE + +); + + //---------- Input Register ---------------------------- +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg1; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg1; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg2; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg2; + + //---------- Internal Signals -------------------------- + reg adapt_done_cnt = 1'd0; + + //---------- Output Register --------------------------- + reg preset_done = 1'd0; + reg [21:0] converge_cnt = 22'd0; + reg [17:0] new_txcoeff = 18'd0; + reg new_txcoeff_done = 1'd0; + reg lffs_sel = 1'd0; + reg adapt_done = 1'd0; + reg [ 3:0] fsm = 4'd0; + + //---------- FSM --------------------------------------- + localparam FSM_IDLE = 4'b0001; + localparam FSM_PRESET = 4'b0010; + localparam FSM_CONVERGE = 4'b0100; + localparam FSM_NEW_TXCOEFF_REQ = 4'b1000; + + //---------- Simulation Speedup ------------------------ + // Gen3: 32 bits / PCLK : 1 million bits / X PCLK + // X = + //------------------------------------------------------ + localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX; + localparam converge_max_bypass_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX_BYPASS; + + + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge RXEQSCAN_CLK) +begin + + if (!RXEQSCAN_RST_N) + begin + //---------- 1st Stage FF -------------------------- + preset_reg1 <= 3'd0; + preset_valid_reg1 <= 1'd0; + txpreset_reg1 <= 4'd0; + txcoeff_reg1 <= 18'd0; + new_txcoeff_req_reg1 <= 1'd0; + fs_reg1 <= 6'd0; + lf_reg1 <= 6'd0; + //---------- 2nd Stage FF -------------------------- + preset_reg2 <= 3'd0; + preset_valid_reg2 <= 1'd0; + txpreset_reg2 <= 4'd0; + txcoeff_reg2 <= 18'd0; + new_txcoeff_req_reg2 <= 1'd0; + fs_reg2 <= 6'd0; + lf_reg2 <= 6'd0; + end + else + begin + //---------- 1st Stage FF -------------------------- + preset_reg1 <= RXEQSCAN_PRESET; + preset_valid_reg1 <= RXEQSCAN_PRESET_VALID; + txpreset_reg1 <= RXEQSCAN_TXPRESET; + txcoeff_reg1 <= RXEQSCAN_TXCOEFF; + new_txcoeff_req_reg1 <= RXEQSCAN_NEW_TXCOEFF_REQ; + fs_reg1 <= RXEQSCAN_FS; + lf_reg1 <= RXEQSCAN_LF; + //---------- 2nd Stage FF -------------------------- + preset_reg2 <= preset_reg1; + preset_valid_reg2 <= preset_valid_reg1; + txpreset_reg2 <= txpreset_reg1; + txcoeff_reg2 <= txcoeff_reg1; + new_txcoeff_req_reg2 <= new_txcoeff_req_reg1; + fs_reg2 <= fs_reg1; + lf_reg2 <= lf_reg1; + end + +end + + + +//---------- Eye Scan ---------------------------------------------------------- +always @ (posedge RXEQSCAN_CLK) +begin + + if (!RXEQSCAN_RST_N) + begin + fsm <= FSM_IDLE; + preset_done <= 1'd0; + converge_cnt <= 22'd0; + new_txcoeff <= 18'd0; + new_txcoeff_done <= 1'd0; + lffs_sel <= 1'd0; + adapt_done <= 1'd0; + adapt_done_cnt <= 1'd0; + end + else + + begin + + case (fsm) + + //---------- Idle State ---------------------------- + FSM_IDLE : + + begin + + //---------- Process RXEQ Preset --------------- + if (preset_valid_reg2) + begin + fsm <= FSM_PRESET; + preset_done <= 1'd1; + converge_cnt <= 22'd0; + new_txcoeff <= new_txcoeff; + new_txcoeff_done <= 1'd0; + lffs_sel <= 1'd0; + adapt_done <= 1'd0; + adapt_done_cnt <= adapt_done_cnt; + end + //---------- Request New TX Coefficient -------- + else if (new_txcoeff_req_reg2) + begin + fsm <= FSM_CONVERGE; + preset_done <= 1'd0; + converge_cnt <= 22'd0; + //new_txcoeff <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : 18'd4; // Default + new_txcoeff <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : (PCIE_GT_DEVICE == "GTX") ? 18'd5 : 18'd4; // Optimized for Gen3 RX JTOL + new_txcoeff_done <= 1'd0; + lffs_sel <= (PCIE_RXEQ_MODE_GEN3 == 0) ? 1'd0 : 1'd1; + adapt_done <= 1'd0; + adapt_done_cnt <= adapt_done_cnt; + end + //---------- Default --------------------------- + else + begin + fsm <= FSM_IDLE; + preset_done <= 1'd0; + converge_cnt <= 22'd0; + new_txcoeff <= new_txcoeff; + new_txcoeff_done <= 1'd0; + lffs_sel <= 1'd0; + adapt_done <= 1'd0; + adapt_done_cnt <= adapt_done_cnt; + end + + end + + //---------- Process RXEQ Preset ------------------- + FSM_PRESET : + + begin + fsm <= (!preset_valid_reg2) ? FSM_IDLE : FSM_PRESET; + preset_done <= 1'd1; + converge_cnt <= 22'd0; + new_txcoeff <= new_txcoeff; + new_txcoeff_done <= 1'd0; + lffs_sel <= 1'd0; + adapt_done <= 1'd0; + adapt_done_cnt <= adapt_done_cnt; + end + + //---------- Wait for Convergence ------------------ + FSM_CONVERGE : + + begin + if ((adapt_done_cnt == 1'd0) && (RXEQSCAN_CONTROL == 2'd2)) + begin + fsm <= FSM_NEW_TXCOEFF_REQ; + preset_done <= 1'd0; + converge_cnt <= 22'd0; + new_txcoeff <= new_txcoeff; + new_txcoeff_done <= 1'd0; + lffs_sel <= lffs_sel; + adapt_done <= 1'd0; + adapt_done_cnt <= adapt_done_cnt; + end + else + begin + + //---------- Phase2/3 ---------------------- + if (RXEQSCAN_CONTROL == 2'd2) + fsm <= (converge_cnt == converge_max_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE; + //---------- Phase2/3 Bypass --------------- + else + fsm <= (converge_cnt == converge_max_bypass_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE; + + preset_done <= 1'd0; + converge_cnt <= converge_cnt + 1'd1; + new_txcoeff <= new_txcoeff; + new_txcoeff_done <= 1'd0; + lffs_sel <= lffs_sel; + adapt_done <= 1'd0; + adapt_done_cnt <= adapt_done_cnt; + end + end + + //---------- Request New TX Coefficient ------------ + FSM_NEW_TXCOEFF_REQ : + + begin + if (!new_txcoeff_req_reg2) + begin + fsm <= FSM_IDLE; + preset_done <= 1'd0; + converge_cnt <= 22'd0; + new_txcoeff <= new_txcoeff; + new_txcoeff_done <= 1'd0; + lffs_sel <= lffs_sel; + adapt_done <= 1'd0; + adapt_done_cnt <= (RXEQSCAN_CONTROL == 2'd3) ? 1'd0 : adapt_done_cnt + 1'd1; + end + else + begin + fsm <= FSM_NEW_TXCOEFF_REQ; + preset_done <= 1'd0; + converge_cnt <= 22'd0; + new_txcoeff <= new_txcoeff; + new_txcoeff_done <= 1'd1; + lffs_sel <= lffs_sel; + adapt_done <= (adapt_done_cnt == 1'd1) || (RXEQSCAN_CONTROL == 2'd3); + adapt_done_cnt <= adapt_done_cnt; + end + end + + //---------- Default State ------------------------- + default : + + begin + fsm <= FSM_IDLE; + preset_done <= 1'd0; + converge_cnt <= 22'd0; + new_txcoeff <= 18'd0; + new_txcoeff_done <= 1'd0; + lffs_sel <= 1'd0; + adapt_done <= 1'd0; + adapt_done_cnt <= 1'd0; + end + + endcase + + end + +end + + + +//---------- RXEQ Eye Scan Output ---------------------------------------------- +assign RXEQSCAN_PRESET_DONE = preset_done; +assign RXEQSCAN_NEW_TXCOEFF = new_txcoeff; +assign RXEQSCAN_NEW_TXCOEFF_DONE = new_txcoeff_done; +assign RXEQSCAN_LFFS_SEL = lffs_sel; +assign RXEQSCAN_ADAPT_DONE = adapt_done; + + + +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/synth/pcie_7x_0.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/synth/pcie_7x_0.v new file mode 100644 index 0000000..7f24f08 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/synth/pcie_7x_0.v @@ -0,0 +1,1106 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:pcie_7x:3.3 +// IP Revision: 14 + +(* X_CORE_INFO = "pcie_7x_0_pcie2_top,Vivado 2020.2" *) +(* CHECK_LICENSE_TYPE = "pcie_7x_0,pcie_7x_0_pcie2_top,{}" *) +(* CORE_GENERATION_INFO = "pcie_7x_0,pcie_7x_0_pcie2_top,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=pcie_7x,x_ipVersion=3.3,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,c_component_name=pcie_7x_0,dev_port_type=0000,c_dev_port_type=0,c_header_type=00,c_upstream_facing=TRUE,max_lnk_wdt=000100,max_lnk_spd=2,c_gen1=true,pci_exp_int_freq=3,c_pcie_fast_config=0,bar_0=FFFF0000,bar_1=00000000,bar_2=00000000,bar_3=00000000,bar_4=00000000,bar_5=00000000,xrom_bar=00000000,cost_table=1,\ +ven_id=10EE,dev_id=7024,rev_id=00,subsys_ven_id=10EE,subsys_id=0007,class_code=050000,cardbus_cis_ptr=00000000,cap_ver=2,c_pcie_cap_slot_implemented=FALSE,mps=011,cmps=3,ext_tag_fld_sup=FALSE,c_dev_control_ext_tag_default=FALSE,phantm_func_sup=00,c_phantom_functions=0,ep_l0s_accpt_lat=000,c_ep_l0s_accpt_lat=0,ep_l1_accpt_lat=111,c_ep_l1_accpt_lat=7,c_cpl_timeout_disable_sup=FALSE,c_cpl_timeout_range=0010,c_cpl_timeout_ranges_sup=2,c_buf_opt_bma=TRUE,c_perf_level_high=TRUE,c_tx_last_tlp=30,c_rx_r\ +am_limit=FFF,c_fc_ph=32,c_fc_pd=949,c_fc_nph=12,c_fc_npd=24,c_fc_cplh=36,c_fc_cpld=973,c_cpl_inf=TRUE,c_cpl_infinite=TRUE,c_dll_lnk_actv_cap=FALSE,c_trgt_lnk_spd=2,c_hw_auton_spd_disable=FALSE,c_de_emph=FALSE,slot_clk=TRUE,c_rcb=0,c_root_cap_crs=FALSE,c_slot_cap_attn_butn=FALSE,c_slot_cap_attn_ind=FALSE,c_slot_cap_pwr_ctrl=FALSE,c_slot_cap_pwr_ind=FALSE,c_slot_cap_hotplug_surprise=FALSE,c_slot_cap_hotplug_cap=FALSE,c_slot_cap_mrl=FALSE,c_slot_cap_elec_interlock=FALSE,c_slot_cap_no_cmd_comp_sup=F\ +ALSE,c_slot_cap_pwr_limit_value=0,c_slot_cap_pwr_limit_scale=0,c_slot_cap_physical_slot_num=0,intx=TRUE,int_pin=1,c_msi_cap_on=FALSE,c_pm_cap_next_ptr=60,c_msi_64b_addr=TRUE,c_msi=0,c_msi_mult_msg_extn=0,c_msi_per_vctr_mask_cap=FALSE,c_msix_cap_on=FALSE,c_msix_next_ptr=00,c_pcie_cap_next_ptr=00,c_msix_table_size=000,c_msix_table_offset=0,c_msix_table_bir=0,c_msix_pba_offset=0,c_msix_pba_bir=0,dsi=0,c_dsi_bool=FALSE,d1_sup=0,c_d1_support=FALSE,d2_sup=0,c_d2_support=FALSE,pme_sup=0F,c_pme_support=\ +0F,no_soft_rst=TRUE,pwr_con_d0_state=00,con_scl_fctr_d0_state=0,pwr_con_d1_state=00,con_scl_fctr_d1_state=0,pwr_con_d2_state=00,con_scl_fctr_d2_state=0,pwr_con_d3_state=00,con_scl_fctr_d3_state=0,pwr_dis_d0_state=00,dis_scl_fctr_d0_state=0,pwr_dis_d1_state=00,dis_scl_fctr_d1_state=0,pwr_dis_d2_state=00,dis_scl_fctr_d2_state=0,pwr_dis_d3_state=00,dis_scl_fctr_d3_state=0,c_dsn_cap_enabled=TRUE,c_dsn_base_ptr=100,c_vc_cap_enabled=FALSE,c_vc_base_ptr=000,c_vc_cap_reject_snoop=FALSE,c_vsec_cap_enable\ +d=FALSE,c_vsec_base_ptr=000,c_vsec_next_ptr=000,c_dsn_next_ptr=000,c_vc_next_ptr=000,c_pci_cfg_space_addr=3F,c_ext_pci_cfg_space_addr=3FF,c_last_cfg_dw=10C,c_enable_msg_route=00000000000,bram_lat=0,c_rx_raddr_lat=0,c_rx_rdata_lat=2,c_rx_write_lat=0,c_tx_raddr_lat=0,c_tx_rdata_lat=2,c_tx_write_lat=0,c_ll_ack_timeout_enable=FALSE,c_ll_ack_timeout_function=0,c_ll_ack_timeout=0000,c_ll_replay_timeout_enable=FALSE,c_ll_replay_timeout_func=1,c_ll_replay_timeout=0000,c_dis_lane_reverse=TRUE,c_upconfig_\ +capable=TRUE,c_disable_scrambling=FALSE,c_disable_tx_aspm_l0s=FALSE,c_pcie_dbg_ports=TRUE,pci_exp_ref_freq=0,c_xlnx_ref_board=ZC706,c_pcie_blk_locn=0,c_ur_atomic=FALSE,c_dev_cap2_atomicop32_completer_supported=FALSE,c_dev_cap2_atomicop64_completer_supported=FALSE,c_dev_cap2_cas128_completer_supported=FALSE,c_dev_cap2_tph_completer_supported=00,c_dev_cap2_ari_forwarding_supported=FALSE,c_dev_cap2_atomicop_routing_supported=FALSE,c_link_cap_aspm_optionality=FALSE,c_aer_cap_on=FALSE,c_aer_base_ptr=\ +000,c_aer_cap_nextptr=000,c_aer_cap_ecrc_check_capable=FALSE,c_aer_cap_ecrc_gen_capable=FALSE,c_aer_cap_multiheader=FALSE,c_aer_cap_permit_rooterr_update=FALSE,c_rbar_cap_on=FALSE,c_rbar_base_ptr=000,c_rbar_cap_nextptr=000,c_rbar_num=0,c_rbar_cap_sup0=00001,c_rbar_cap_index0=0,c_rbar_cap_control_encodedbar0=00,c_rbar_cap_sup1=00001,c_rbar_cap_index1=0,c_rbar_cap_control_encodedbar1=00,c_rbar_cap_sup2=00001,c_rbar_cap_index2=0,c_rbar_cap_control_encodedbar2=00,c_rbar_cap_sup3=00001,c_rbar_cap_ind\ +ex3=0,c_rbar_cap_control_encodedbar3=00,c_rbar_cap_sup4=00001,c_rbar_cap_index4=0,c_rbar_cap_control_encodedbar4=00,c_rbar_cap_sup5=00001,c_rbar_cap_index5=0,c_rbar_cap_control_encodedbar5=00,c_recrc_check=0,c_recrc_check_trim=FALSE,c_disable_rx_poisoned_resp=FALSE,c_trn_np_fc=TRUE,c_ur_inv_req=TRUE,c_ur_prs_response=TRUE,c_silicon_rev=2,c_aer_cap_optional_err_support=000000,LINK_CAP_MAX_LINK_WIDTH=4,C_DATA_WIDTH=64,PIPE_SIM=FALSE,PCIE_EXT_CLK=TRUE,PCIE_EXT_GT_COMMON=FALSE,EXT_CH_GT_DRP=FALSE,TR\ +ANSCEIVER_CTRL_STATUS_PORTS=FALSE,SHARED_LOGIC_IN_CORE=FALSE,ERR_REPORTING_IF=TRUE,PL_INTERFACE=TRUE,CFG_MGMT_IF=TRUE,CFG_CTL_IF=TRUE,CFG_STATUS_IF=TRUE,RCV_MSG_IF=TRUE,CFG_FC_IF=TRUE,EXT_PIPE_INTERFACE=FALSE,EXT_STARTUP_PRIMITIVE=FALSE,KEEP_WIDTH=8,PCIE_ASYNC_EN=FALSE,ENABLE_JTAG_DBG=FALSE,REDUCE_OOB_FREQ=FALSE}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_7x_0 ( + pci_exp_txp, + pci_exp_txn, + pci_exp_rxp, + pci_exp_rxn, + pipe_pclk_in, + pipe_rxusrclk_in, + pipe_rxoutclk_in, + pipe_dclk_in, + pipe_userclk1_in, + pipe_userclk2_in, + pipe_oobclk_in, + pipe_mmcm_lock_in, + pipe_txoutclk_out, + pipe_rxoutclk_out, + pipe_pclk_sel_out, + pipe_gen3_out, + user_clk_out, + user_reset_out, + user_lnk_up, + user_app_rdy, + tx_buf_av, + tx_cfg_req, + tx_err_drop, + s_axis_tx_tready, + s_axis_tx_tdata, + s_axis_tx_tkeep, + s_axis_tx_tlast, + s_axis_tx_tvalid, + s_axis_tx_tuser, + tx_cfg_gnt, + m_axis_rx_tdata, + m_axis_rx_tkeep, + m_axis_rx_tlast, + m_axis_rx_tvalid, + m_axis_rx_tready, + m_axis_rx_tuser, + rx_np_ok, + rx_np_req, + fc_cpld, + fc_cplh, + fc_npd, + fc_nph, + fc_pd, + fc_ph, + fc_sel, + cfg_mgmt_do, + cfg_mgmt_rd_wr_done, + cfg_status, + cfg_command, + cfg_dstatus, + cfg_dcommand, + cfg_lstatus, + cfg_lcommand, + cfg_dcommand2, + cfg_pcie_link_state, + cfg_pmcsr_pme_en, + cfg_pmcsr_powerstate, + cfg_pmcsr_pme_status, + cfg_received_func_lvl_rst, + cfg_mgmt_di, + cfg_mgmt_byte_en, + cfg_mgmt_dwaddr, + cfg_mgmt_wr_en, + cfg_mgmt_rd_en, + cfg_mgmt_wr_readonly, + cfg_err_ecrc, + cfg_err_ur, + cfg_err_cpl_timeout, + cfg_err_cpl_unexpect, + cfg_err_cpl_abort, + cfg_err_posted, + cfg_err_cor, + cfg_err_atomic_egress_blocked, + cfg_err_internal_cor, + cfg_err_malformed, + cfg_err_mc_blocked, + cfg_err_poisoned, + cfg_err_norecovery, + cfg_err_tlp_cpl_header, + cfg_err_cpl_rdy, + cfg_err_locked, + cfg_err_acs, + cfg_err_internal_uncor, + cfg_trn_pending, + cfg_pm_halt_aspm_l0s, + cfg_pm_halt_aspm_l1, + cfg_pm_force_state_en, + cfg_pm_force_state, + cfg_dsn, + cfg_interrupt, + cfg_interrupt_rdy, + cfg_interrupt_assert, + cfg_interrupt_di, + cfg_interrupt_do, + cfg_interrupt_mmenable, + cfg_interrupt_msienable, + cfg_interrupt_msixenable, + cfg_interrupt_msixfm, + cfg_interrupt_stat, + cfg_pciecap_interrupt_msgnum, + cfg_to_turnoff, + cfg_turnoff_ok, + cfg_bus_number, + cfg_device_number, + cfg_function_number, + cfg_pm_wake, + cfg_pm_send_pme_to, + cfg_ds_bus_number, + cfg_ds_device_number, + cfg_ds_function_number, + cfg_mgmt_wr_rw1c_as_rw, + cfg_msg_received, + cfg_msg_data, + cfg_bridge_serr_en, + cfg_slot_control_electromech_il_ctl_pulse, + cfg_root_control_syserr_corr_err_en, + cfg_root_control_syserr_non_fatal_err_en, + cfg_root_control_syserr_fatal_err_en, + cfg_root_control_pme_int_en, + cfg_aer_rooterr_corr_err_reporting_en, + cfg_aer_rooterr_non_fatal_err_reporting_en, + cfg_aer_rooterr_fatal_err_reporting_en, + cfg_aer_rooterr_corr_err_received, + cfg_aer_rooterr_non_fatal_err_received, + cfg_aer_rooterr_fatal_err_received, + cfg_msg_received_err_cor, + cfg_msg_received_err_non_fatal, + cfg_msg_received_err_fatal, + cfg_msg_received_pm_as_nak, + cfg_msg_received_pm_pme, + cfg_msg_received_pme_to_ack, + cfg_msg_received_assert_int_a, + cfg_msg_received_assert_int_b, + cfg_msg_received_assert_int_c, + cfg_msg_received_assert_int_d, + cfg_msg_received_deassert_int_a, + cfg_msg_received_deassert_int_b, + cfg_msg_received_deassert_int_c, + cfg_msg_received_deassert_int_d, + cfg_msg_received_setslotpowerlimit, + pl_directed_link_change, + pl_directed_link_width, + pl_directed_link_speed, + pl_directed_link_auton, + pl_upstream_prefer_deemph, + pl_sel_lnk_rate, + pl_sel_lnk_width, + pl_ltssm_state, + pl_lane_reversal_mode, + pl_phy_lnk_up, + pl_tx_pm_state, + pl_rx_pm_state, + pl_link_upcfg_cap, + pl_link_gen2_cap, + pl_link_partner_gen2_supported, + pl_initial_link_width, + pl_directed_change_done, + pl_received_hot_rst, + pl_transmit_hot_rst, + pl_downstream_deemph_source, + cfg_err_aer_headerlog, + cfg_aer_interrupt_msgnum, + cfg_err_aer_headerlog_set, + cfg_aer_ecrc_check_en, + cfg_aer_ecrc_gen_en, + cfg_vc_tcvc_map, + sys_clk, + sys_rst_n, + pipe_mmcm_rst_n, + pcie_drp_clk, + pcie_drp_en, + pcie_drp_we, + pcie_drp_addr, + pcie_drp_di, + pcie_drp_do, + pcie_drp_rdy +); + +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txp" *) +output wire [3 : 0] pci_exp_txp; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txn" *) +output wire [3 : 0] pci_exp_txn; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxp" *) +input wire [3 : 0] pci_exp_rxp; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxn" *) +input wire [3 : 0] pci_exp_rxn; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock pclk_in" *) +input wire pipe_pclk_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxusrclk_in" *) +input wire pipe_rxusrclk_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxoutclk_in" *) +input wire [3 : 0] pipe_rxoutclk_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock dclk_in" *) +input wire pipe_dclk_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock userclk1_in" *) +input wire pipe_userclk1_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock userclk2_in" *) +input wire pipe_userclk2_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock oobclk_in" *) +input wire pipe_oobclk_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock mmcm_lock_in" *) +input wire pipe_mmcm_lock_in; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock txoutclk_out" *) +output wire pipe_txoutclk_out; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxoutclk_out" *) +output wire [3 : 0] pipe_rxoutclk_out; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock pclk_sel_out" *) +output wire [3 : 0] pipe_pclk_sel_out; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock gen3_out" *) +output wire pipe_gen3_out; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.user_clk_out, ASSOCIATED_BUSIF m_axis_rx:s_axis_tx, FREQ_HZ 125000000, ASSOCIATED_RESET user_reset_out, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.user_clk_out CLK" *) +output wire user_clk_out; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.user_reset_out, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.user_reset_out RST" *) +output wire user_reset_out; +output wire user_lnk_up; +output wire user_app_rdy; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_buf_av" *) +output wire [5 : 0] tx_buf_av; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_cfg_req" *) +output wire tx_cfg_req; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_err_drop" *) +output wire tx_err_drop; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TREADY" *) +output wire s_axis_tx_tready; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TDATA" *) +input wire [63 : 0] s_axis_tx_tdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TKEEP" *) +input wire [7 : 0] s_axis_tx_tkeep; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TLAST" *) +input wire s_axis_tx_tlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TVALID" *) +input wire s_axis_tx_tvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axis_tx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TUSER" *) +input wire [3 : 0] s_axis_tx_tuser; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control tx_cfg_gnt" *) +input wire tx_cfg_gnt; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TDATA" *) +output wire [63 : 0] m_axis_rx_tdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TKEEP" *) +output wire [7 : 0] m_axis_rx_tkeep; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TLAST" *) +output wire m_axis_rx_tlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TVALID" *) +output wire m_axis_rx_tvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TREADY" *) +input wire m_axis_rx_tready; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis_rx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TUSER" *) +output wire [21 : 0] m_axis_rx_tuser; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_ok" *) +input wire rx_np_ok; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_req" *) +input wire rx_np_req; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLD" *) +output wire [11 : 0] fc_cpld; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLH" *) +output wire [7 : 0] fc_cplh; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPD" *) +output wire [11 : 0] fc_npd; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPH" *) +output wire [7 : 0] fc_nph; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PD" *) +output wire [11 : 0] fc_pd; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PH" *) +output wire [7 : 0] fc_ph; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc SEL" *) +input wire [2 : 0] fc_sel; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_DATA" *) +output wire [31 : 0] cfg_mgmt_do; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_WRITE_DONE" *) +output wire cfg_mgmt_rd_wr_done; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status status" *) +output wire [15 : 0] cfg_status; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status command" *) +output wire [15 : 0] cfg_command; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dstatus" *) +output wire [15 : 0] cfg_dstatus; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand" *) +output wire [15 : 0] cfg_dcommand; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lstatus" *) +output wire [15 : 0] cfg_lstatus; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lcommand" *) +output wire [15 : 0] cfg_lcommand; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand2" *) +output wire [15 : 0] cfg_dcommand2; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pcie_link_state" *) +output wire [2 : 0] cfg_pcie_link_state; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_en" *) +output wire cfg_pmcsr_pme_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_powerstate" *) +output wire [1 : 0] cfg_pmcsr_powerstate; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_status" *) +output wire cfg_pmcsr_pme_status; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status received_func_lvl_rst" *) +output wire cfg_received_func_lvl_rst; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_DATA" *) +input wire [31 : 0] cfg_mgmt_di; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt BYTE_EN" *) +input wire [3 : 0] cfg_mgmt_byte_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt ADDR" *) +input wire [9 : 0] cfg_mgmt_dwaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_EN" *) +input wire cfg_mgmt_wr_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_EN" *) +input wire cfg_mgmt_rd_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READONLY" *) +input wire cfg_mgmt_wr_readonly; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ecrc" *) +input wire cfg_err_ecrc; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ur" *) +input wire cfg_err_ur; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_timeout" *) +input wire cfg_err_cpl_timeout; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_unexpect" *) +input wire cfg_err_cpl_unexpect; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_abort" *) +input wire cfg_err_cpl_abort; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err posted" *) +input wire cfg_err_posted; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cor" *) +input wire cfg_err_cor; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err atomic_egress_blocked" *) +input wire cfg_err_atomic_egress_blocked; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_cor" *) +input wire cfg_err_internal_cor; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err malformed" *) +input wire cfg_err_malformed; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err mc_blocked" *) +input wire cfg_err_mc_blocked; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err poisoned" *) +input wire cfg_err_poisoned; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err norecovery" *) +input wire cfg_err_norecovery; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err tlp_cpl_header" *) +input wire [47 : 0] cfg_err_tlp_cpl_header; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_rdy" *) +output wire cfg_err_cpl_rdy; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err locked" *) +input wire cfg_err_locked; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err acs" *) +input wire cfg_err_acs; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_uncor" *) +input wire cfg_err_internal_uncor; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control trn_pending" *) +input wire cfg_trn_pending; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l0s" *) +input wire cfg_pm_halt_aspm_l0s; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l1" *) +input wire cfg_pm_halt_aspm_l1; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state_en" *) +input wire cfg_pm_force_state_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state" *) +input wire [1 : 0] cfg_pm_force_state; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control dsn" *) +input wire [63 : 0] cfg_dsn; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt interrupt" *) +input wire cfg_interrupt; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt rdy" *) +output wire cfg_interrupt_rdy; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt assert" *) +input wire cfg_interrupt_assert; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt write_data" *) +input wire [7 : 0] cfg_interrupt_di; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt read_data" *) +output wire [7 : 0] cfg_interrupt_do; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt mmenable" *) +output wire [2 : 0] cfg_interrupt_mmenable; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msienable" *) +output wire cfg_interrupt_msienable; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixenable" *) +output wire cfg_interrupt_msixenable; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixfm" *) +output wire cfg_interrupt_msixfm; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt stat" *) +input wire cfg_interrupt_stat; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt pciecap_interrupt_msgnum" *) +input wire [4 : 0] cfg_pciecap_interrupt_msgnum; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status turnoff" *) +output wire cfg_to_turnoff; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control turnoff_ok" *) +input wire cfg_turnoff_ok; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bus_number" *) +output wire [7 : 0] cfg_bus_number; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status device_number" *) +output wire [4 : 0] cfg_device_number; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status function_number" *) +output wire [2 : 0] cfg_function_number; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_wake" *) +input wire cfg_pm_wake; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_send_pme_to" *) +input wire cfg_pm_send_pme_to; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_bus_number" *) +input wire [7 : 0] cfg_ds_bus_number; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_device_number" *) +input wire [4 : 0] cfg_ds_device_number; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_function_number" *) +input wire [2 : 0] cfg_ds_function_number; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt TYPE1_CFG_REG_ACCESS" *) +input wire cfg_mgmt_wr_rw1c_as_rw; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received" *) +output wire cfg_msg_received; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd data" *) +output wire [15 : 0] cfg_msg_data; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bridge_serr_en" *) +output wire cfg_bridge_serr_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status slot_control_electromech_il_ctl_pulse" *) +output wire cfg_slot_control_electromech_il_ctl_pulse; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_corr_err_en" *) +output wire cfg_root_control_syserr_corr_err_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_non_fatal_err_en" *) +output wire cfg_root_control_syserr_non_fatal_err_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_fatal_err_en" *) +output wire cfg_root_control_syserr_fatal_err_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_pme_int_en" *) +output wire cfg_root_control_pme_int_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_reporting_en" *) +output wire cfg_aer_rooterr_corr_err_reporting_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_reporting_en" *) +output wire cfg_aer_rooterr_non_fatal_err_reporting_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_reporting_en" *) +output wire cfg_aer_rooterr_fatal_err_reporting_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_received" *) +output wire cfg_aer_rooterr_corr_err_received; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_received" *) +output wire cfg_aer_rooterr_non_fatal_err_received; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_received" *) +output wire cfg_aer_rooterr_fatal_err_received; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_cor" *) +output wire cfg_msg_received_err_cor; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_non_fatal" *) +output wire cfg_msg_received_err_non_fatal; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_fatal" *) +output wire cfg_msg_received_err_fatal; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_pm_as_nak" *) +output wire cfg_msg_received_pm_as_nak; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pm_pme" *) +output wire cfg_msg_received_pm_pme; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pme_to_ack" *) +output wire cfg_msg_received_pme_to_ack; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_a" *) +output wire cfg_msg_received_assert_int_a; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_b" *) +output wire cfg_msg_received_assert_int_b; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_c" *) +output wire cfg_msg_received_assert_int_c; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_d" *) +output wire cfg_msg_received_assert_int_d; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_a" *) +output wire cfg_msg_received_deassert_int_a; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_b" *) +output wire cfg_msg_received_deassert_int_b; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_c" *) +output wire cfg_msg_received_deassert_int_c; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_d" *) +output wire cfg_msg_received_deassert_int_d; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_setslotpowerlimit" *) +output wire cfg_msg_received_setslotpowerlimit; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_change" *) +input wire [1 : 0] pl_directed_link_change; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_width" *) +input wire [1 : 0] pl_directed_link_width; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_speed" *) +input wire pl_directed_link_speed; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_auton" *) +input wire pl_directed_link_auton; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl upstream_prefer_deemph" *) +input wire pl_upstream_prefer_deemph; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_rate" *) +output wire pl_sel_lnk_rate; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_width" *) +output wire [1 : 0] pl_sel_lnk_width; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl ltssm_state" *) +output wire [5 : 0] pl_ltssm_state; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl lane_reversal_mode" *) +output wire [1 : 0] pl_lane_reversal_mode; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl phy_lnk_up" *) +output wire pl_phy_lnk_up; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl tx_pm_state" *) +output wire [2 : 0] pl_tx_pm_state; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl rx_pm_state" *) +output wire [1 : 0] pl_rx_pm_state; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_upcfg_cap" *) +output wire pl_link_upcfg_cap; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_gen2_cap" *) +output wire pl_link_gen2_cap; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_partner_gen2_supported" *) +output wire pl_link_partner_gen2_supported; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl initial_link_width" *) +output wire [2 : 0] pl_initial_link_width; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_change_done" *) +output wire pl_directed_change_done; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl received_hot_rst" *) +output wire pl_received_hot_rst; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl transmit_hot_rst" *) +input wire pl_transmit_hot_rst; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl downstream_deemph_source" *) +input wire pl_downstream_deemph_source; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog" *) +input wire [127 : 0] cfg_err_aer_headerlog; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_interrupt_msgnum" *) +input wire [4 : 0] cfg_aer_interrupt_msgnum; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog_set" *) +output wire cfg_err_aer_headerlog_set; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_check_en" *) +output wire cfg_aer_ecrc_check_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_gen_en" *) +output wire cfg_aer_ecrc_gen_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status vc_tcvc_map" *) +output wire [6 : 0] cfg_vc_tcvc_map; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.sys_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.sys_clk CLK" *) +input wire sys_clk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.sys_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.sys_rst_n RST" *) +input wire sys_rst_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock mmcm_rst_n" *) +input wire pipe_mmcm_rst_n; +input wire pcie_drp_clk; +(* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DEN" *) +input wire pcie_drp_en; +(* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DWE" *) +input wire pcie_drp_we; +(* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DADDR" *) +input wire [8 : 0] pcie_drp_addr; +(* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DI" *) +input wire [15 : 0] pcie_drp_di; +(* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DO" *) +output wire [15 : 0] pcie_drp_do; +(* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DRDY" *) +output wire pcie_drp_rdy; + + pcie_7x_0_pcie2_top #( + .c_component_name("pcie_7x_0"), + .dev_port_type("0000"), + .c_dev_port_type("0"), + .c_header_type("00"), + .c_upstream_facing("TRUE"), + .max_lnk_wdt("000100"), + .max_lnk_spd("2"), + .c_gen1(1'B1), + .pci_exp_int_freq(3), + .c_pcie_fast_config(0), + .bar_0("FFFF0000"), + .bar_1("00000000"), + .bar_2("00000000"), + .bar_3("00000000"), + .bar_4("00000000"), + .bar_5("00000000"), + .xrom_bar("00000000"), + .cost_table(1), + .ven_id("10EE"), + .dev_id("7024"), + .rev_id("00"), + .subsys_ven_id("10EE"), + .subsys_id("0007"), + .class_code("050000"), + .cardbus_cis_ptr("00000000"), + .cap_ver("2"), + .c_pcie_cap_slot_implemented("FALSE"), + .mps("011"), + .cmps("3"), + .ext_tag_fld_sup("FALSE"), + .c_dev_control_ext_tag_default("FALSE"), + .phantm_func_sup("00"), + .c_phantom_functions("0"), + .ep_l0s_accpt_lat("000"), + .c_ep_l0s_accpt_lat("0"), + .ep_l1_accpt_lat("111"), + .c_ep_l1_accpt_lat("7"), + .c_cpl_timeout_disable_sup("FALSE"), + .c_cpl_timeout_range("0010"), + .c_cpl_timeout_ranges_sup("2"), + .c_buf_opt_bma("TRUE"), + .c_perf_level_high("TRUE"), + .c_tx_last_tlp("30"), + .c_rx_ram_limit("FFF"), + .c_fc_ph("32"), + .c_fc_pd("949"), + .c_fc_nph("12"), + .c_fc_npd("24"), + .c_fc_cplh("36"), + .c_fc_cpld("973"), + .c_cpl_inf("TRUE"), + .c_cpl_infinite("TRUE"), + .c_dll_lnk_actv_cap("FALSE"), + .c_trgt_lnk_spd("2"), + .c_hw_auton_spd_disable("FALSE"), + .c_de_emph("FALSE"), + .slot_clk("TRUE"), + .c_rcb("0"), + .c_root_cap_crs("FALSE"), + .c_slot_cap_attn_butn("FALSE"), + .c_slot_cap_attn_ind("FALSE"), + .c_slot_cap_pwr_ctrl("FALSE"), + .c_slot_cap_pwr_ind("FALSE"), + .c_slot_cap_hotplug_surprise("FALSE"), + .c_slot_cap_hotplug_cap("FALSE"), + .c_slot_cap_mrl("FALSE"), + .c_slot_cap_elec_interlock("FALSE"), + .c_slot_cap_no_cmd_comp_sup("FALSE"), + .c_slot_cap_pwr_limit_value("0"), + .c_slot_cap_pwr_limit_scale("0"), + .c_slot_cap_physical_slot_num("0"), + .intx("TRUE"), + .int_pin("1"), + .c_msi_cap_on("FALSE"), + .c_pm_cap_next_ptr("60"), + .c_msi_64b_addr("TRUE"), + .c_msi("0"), + .c_msi_mult_msg_extn("0"), + .c_msi_per_vctr_mask_cap("FALSE"), + .c_msix_cap_on("FALSE"), + .c_msix_next_ptr("00"), + .c_pcie_cap_next_ptr("00"), + .c_msix_table_size("000"), + .c_msix_table_offset("0"), + .c_msix_table_bir("0"), + .c_msix_pba_offset("0"), + .c_msix_pba_bir("0"), + .dsi("0"), + .c_dsi_bool("FALSE"), + .d1_sup("0"), + .c_d1_support("FALSE"), + .d2_sup("0"), + .c_d2_support("FALSE"), + .pme_sup("0F"), + .c_pme_support("0F"), + .no_soft_rst("TRUE"), + .pwr_con_d0_state("00"), + .con_scl_fctr_d0_state("0"), + .pwr_con_d1_state("00"), + .con_scl_fctr_d1_state("0"), + .pwr_con_d2_state("00"), + .con_scl_fctr_d2_state("0"), + .pwr_con_d3_state("00"), + .con_scl_fctr_d3_state("0"), + .pwr_dis_d0_state("00"), + .dis_scl_fctr_d0_state("0"), + .pwr_dis_d1_state("00"), + .dis_scl_fctr_d1_state("0"), + .pwr_dis_d2_state("00"), + .dis_scl_fctr_d2_state("0"), + .pwr_dis_d3_state("00"), + .dis_scl_fctr_d3_state("0"), + .c_dsn_cap_enabled("TRUE"), + .c_dsn_base_ptr("100"), + .c_vc_cap_enabled("FALSE"), + .c_vc_base_ptr("000"), + .c_vc_cap_reject_snoop("FALSE"), + .c_vsec_cap_enabled("FALSE"), + .c_vsec_base_ptr("000"), + .c_vsec_next_ptr("000"), + .c_dsn_next_ptr("000"), + .c_vc_next_ptr("000"), + .c_pci_cfg_space_addr("3F"), + .c_ext_pci_cfg_space_addr("3FF"), + .c_last_cfg_dw("10C"), + .c_enable_msg_route("00000000000"), + .bram_lat("0"), + .c_rx_raddr_lat("0"), + .c_rx_rdata_lat("2"), + .c_rx_write_lat("0"), + .c_tx_raddr_lat("0"), + .c_tx_rdata_lat("2"), + .c_tx_write_lat("0"), + .c_ll_ack_timeout_enable("FALSE"), + .c_ll_ack_timeout_function("0"), + .c_ll_ack_timeout("0000"), + .c_ll_replay_timeout_enable("FALSE"), + .c_ll_replay_timeout_func("1"), + .c_ll_replay_timeout("0000"), + .c_dis_lane_reverse("TRUE"), + .c_upconfig_capable("TRUE"), + .c_disable_scrambling("FALSE"), + .c_disable_tx_aspm_l0s("FALSE"), + .c_pcie_dbg_ports("TRUE"), + .pci_exp_ref_freq("0"), + .c_xlnx_ref_board("ZC706"), + .c_pcie_blk_locn("0"), + .c_ur_atomic("FALSE"), + .c_dev_cap2_atomicop32_completer_supported("FALSE"), + .c_dev_cap2_atomicop64_completer_supported("FALSE"), + .c_dev_cap2_cas128_completer_supported("FALSE"), + .c_dev_cap2_tph_completer_supported("00"), + .c_dev_cap2_ari_forwarding_supported("FALSE"), + .c_dev_cap2_atomicop_routing_supported("FALSE"), + .c_link_cap_aspm_optionality("FALSE"), + .c_aer_cap_on("FALSE"), + .c_aer_base_ptr("000"), + .c_aer_cap_nextptr("000"), + .c_aer_cap_ecrc_check_capable("FALSE"), + .c_aer_cap_ecrc_gen_capable("FALSE"), + .c_aer_cap_multiheader("FALSE"), + .c_aer_cap_permit_rooterr_update("FALSE"), + .c_rbar_cap_on("FALSE"), + .c_rbar_base_ptr("000"), + .c_rbar_cap_nextptr("000"), + .c_rbar_num("0"), + .c_rbar_cap_sup0("00001"), + .c_rbar_cap_index0("0"), + .c_rbar_cap_control_encodedbar0("00"), + .c_rbar_cap_sup1("00001"), + .c_rbar_cap_index1("0"), + .c_rbar_cap_control_encodedbar1("00"), + .c_rbar_cap_sup2("00001"), + .c_rbar_cap_index2("0"), + .c_rbar_cap_control_encodedbar2("00"), + .c_rbar_cap_sup3("00001"), + .c_rbar_cap_index3("0"), + .c_rbar_cap_control_encodedbar3("00"), + .c_rbar_cap_sup4("00001"), + .c_rbar_cap_index4("0"), + .c_rbar_cap_control_encodedbar4("00"), + .c_rbar_cap_sup5("00001"), + .c_rbar_cap_index5("0"), + .c_rbar_cap_control_encodedbar5("00"), + .c_recrc_check("0"), + .c_recrc_check_trim("FALSE"), + .c_disable_rx_poisoned_resp("FALSE"), + .c_trn_np_fc("TRUE"), + .c_ur_inv_req("TRUE"), + .c_ur_prs_response("TRUE"), + .c_silicon_rev("2"), + .c_aer_cap_optional_err_support("000000"), + .LINK_CAP_MAX_LINK_WIDTH(4), + .C_DATA_WIDTH(64), + .PIPE_SIM("FALSE"), + .PCIE_EXT_CLK("TRUE"), + .PCIE_EXT_GT_COMMON("FALSE"), + .EXT_CH_GT_DRP("FALSE"), + .TRANSCEIVER_CTRL_STATUS_PORTS("FALSE"), + .SHARED_LOGIC_IN_CORE("FALSE"), + .ERR_REPORTING_IF("TRUE"), + .PL_INTERFACE("TRUE"), + .CFG_MGMT_IF("TRUE"), + .CFG_CTL_IF("TRUE"), + .CFG_STATUS_IF("TRUE"), + .RCV_MSG_IF("TRUE"), + .CFG_FC_IF("TRUE"), + .EXT_PIPE_INTERFACE("FALSE"), + .EXT_STARTUP_PRIMITIVE("FALSE"), + .KEEP_WIDTH(8), + .PCIE_ASYNC_EN("FALSE"), + .ENABLE_JTAG_DBG("FALSE"), + .REDUCE_OOB_FREQ("FALSE") + ) inst ( + .pci_exp_txp(pci_exp_txp), + .pci_exp_txn(pci_exp_txn), + .pci_exp_rxp(pci_exp_rxp), + .pci_exp_rxn(pci_exp_rxn), + .int_pclk_out_slave(), + .int_pipe_rxusrclk_out(), + .int_rxoutclk_out(), + .int_dclk_out(), + .int_mmcm_lock_out(), + .int_userclk1_out(), + .int_userclk2_out(), + .int_oobclk_out(), + .int_qplllock_out(), + .int_qplloutclk_out(), + .int_qplloutrefclk_out(), + .int_pclk_sel_slave(4'B0), + .pipe_pclk_in(pipe_pclk_in), + .pipe_rxusrclk_in(pipe_rxusrclk_in), + .pipe_rxoutclk_in(pipe_rxoutclk_in), + .pipe_dclk_in(pipe_dclk_in), + .pipe_userclk1_in(pipe_userclk1_in), + .pipe_userclk2_in(pipe_userclk2_in), + .pipe_oobclk_in(pipe_oobclk_in), + .pipe_mmcm_lock_in(pipe_mmcm_lock_in), + .pipe_txoutclk_out(pipe_txoutclk_out), + .pipe_rxoutclk_out(pipe_rxoutclk_out), + .pipe_pclk_sel_out(pipe_pclk_sel_out), + .pipe_gen3_out(pipe_gen3_out), + .user_clk_out(user_clk_out), + .user_reset_out(user_reset_out), + .user_lnk_up(user_lnk_up), + .user_app_rdy(user_app_rdy), + .tx_buf_av(tx_buf_av), + .tx_cfg_req(tx_cfg_req), + .tx_err_drop(tx_err_drop), + .s_axis_tx_tready(s_axis_tx_tready), + .s_axis_tx_tdata(s_axis_tx_tdata), + .s_axis_tx_tkeep(s_axis_tx_tkeep), + .s_axis_tx_tlast(s_axis_tx_tlast), + .s_axis_tx_tvalid(s_axis_tx_tvalid), + .s_axis_tx_tuser(s_axis_tx_tuser), + .tx_cfg_gnt(tx_cfg_gnt), + .m_axis_rx_tdata(m_axis_rx_tdata), + .m_axis_rx_tkeep(m_axis_rx_tkeep), + .m_axis_rx_tlast(m_axis_rx_tlast), + .m_axis_rx_tvalid(m_axis_rx_tvalid), + .m_axis_rx_tready(m_axis_rx_tready), + .m_axis_rx_tuser(m_axis_rx_tuser), + .rx_np_ok(rx_np_ok), + .rx_np_req(rx_np_req), + .fc_cpld(fc_cpld), + .fc_cplh(fc_cplh), + .fc_npd(fc_npd), + .fc_nph(fc_nph), + .fc_pd(fc_pd), + .fc_ph(fc_ph), + .fc_sel(fc_sel), + .cfg_mgmt_do(cfg_mgmt_do), + .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done), + .cfg_status(cfg_status), + .cfg_command(cfg_command), + .cfg_dstatus(cfg_dstatus), + .cfg_dcommand(cfg_dcommand), + .cfg_lstatus(cfg_lstatus), + .cfg_lcommand(cfg_lcommand), + .cfg_dcommand2(cfg_dcommand2), + .cfg_pcie_link_state(cfg_pcie_link_state), + .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en), + .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate), + .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status), + .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst), + .cfg_mgmt_di(cfg_mgmt_di), + .cfg_mgmt_byte_en(cfg_mgmt_byte_en), + .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr), + .cfg_mgmt_wr_en(cfg_mgmt_wr_en), + .cfg_mgmt_rd_en(cfg_mgmt_rd_en), + .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly), + .cfg_err_ecrc(cfg_err_ecrc), + .cfg_err_ur(cfg_err_ur), + .cfg_err_cpl_timeout(cfg_err_cpl_timeout), + .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect), + .cfg_err_cpl_abort(cfg_err_cpl_abort), + .cfg_err_posted(cfg_err_posted), + .cfg_err_cor(cfg_err_cor), + .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked), + .cfg_err_internal_cor(cfg_err_internal_cor), + .cfg_err_malformed(cfg_err_malformed), + .cfg_err_mc_blocked(cfg_err_mc_blocked), + .cfg_err_poisoned(cfg_err_poisoned), + .cfg_err_norecovery(cfg_err_norecovery), + .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header), + .cfg_err_cpl_rdy(cfg_err_cpl_rdy), + .cfg_err_locked(cfg_err_locked), + .cfg_err_acs(cfg_err_acs), + .cfg_err_internal_uncor(cfg_err_internal_uncor), + .cfg_trn_pending(cfg_trn_pending), + .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s), + .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1), + .cfg_pm_force_state_en(cfg_pm_force_state_en), + .cfg_pm_force_state(cfg_pm_force_state), + .cfg_dsn(cfg_dsn), + .cfg_interrupt(cfg_interrupt), + .cfg_interrupt_rdy(cfg_interrupt_rdy), + .cfg_interrupt_assert(cfg_interrupt_assert), + .cfg_interrupt_di(cfg_interrupt_di), + .cfg_interrupt_do(cfg_interrupt_do), + .cfg_interrupt_mmenable(cfg_interrupt_mmenable), + .cfg_interrupt_msienable(cfg_interrupt_msienable), + .cfg_interrupt_msixenable(cfg_interrupt_msixenable), + .cfg_interrupt_msixfm(cfg_interrupt_msixfm), + .cfg_interrupt_stat(cfg_interrupt_stat), + .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum), + .cfg_to_turnoff(cfg_to_turnoff), + .cfg_turnoff_ok(cfg_turnoff_ok), + .cfg_bus_number(cfg_bus_number), + .cfg_device_number(cfg_device_number), + .cfg_function_number(cfg_function_number), + .cfg_pm_wake(cfg_pm_wake), + .cfg_pm_send_pme_to(cfg_pm_send_pme_to), + .cfg_ds_bus_number(cfg_ds_bus_number), + .cfg_ds_device_number(cfg_ds_device_number), + .cfg_ds_function_number(cfg_ds_function_number), + .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw), + .cfg_msg_received(cfg_msg_received), + .cfg_msg_data(cfg_msg_data), + .cfg_bridge_serr_en(cfg_bridge_serr_en), + .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse), + .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en), + .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en), + .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en), + .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en), + .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en), + .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en), + .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en), + .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received), + .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received), + .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received), + .cfg_msg_received_err_cor(cfg_msg_received_err_cor), + .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal), + .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal), + .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak), + .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme), + .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack), + .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a), + .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b), + .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c), + .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d), + .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a), + .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b), + .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c), + .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d), + .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit), + .pl_directed_link_change(pl_directed_link_change), + .pl_directed_link_width(pl_directed_link_width), + .pl_directed_link_speed(pl_directed_link_speed), + .pl_directed_link_auton(pl_directed_link_auton), + .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph), + .pl_sel_lnk_rate(pl_sel_lnk_rate), + .pl_sel_lnk_width(pl_sel_lnk_width), + .pl_ltssm_state(pl_ltssm_state), + .pl_lane_reversal_mode(pl_lane_reversal_mode), + .pl_phy_lnk_up(pl_phy_lnk_up), + .pl_tx_pm_state(pl_tx_pm_state), + .pl_rx_pm_state(pl_rx_pm_state), + .pl_link_upcfg_cap(pl_link_upcfg_cap), + .pl_link_gen2_cap(pl_link_gen2_cap), + .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported), + .pl_initial_link_width(pl_initial_link_width), + .pl_directed_change_done(pl_directed_change_done), + .pl_received_hot_rst(pl_received_hot_rst), + .pl_transmit_hot_rst(pl_transmit_hot_rst), + .pl_downstream_deemph_source(pl_downstream_deemph_source), + .cfg_err_aer_headerlog(cfg_err_aer_headerlog), + .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum), + .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set), + .cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en), + .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en), + .cfg_vc_tcvc_map(cfg_vc_tcvc_map), + .sys_clk(sys_clk), + .sys_rst_n(sys_rst_n), + .pipe_mmcm_rst_n(pipe_mmcm_rst_n), + .startup_eos_in(1'B0), + .startup_cfgclk(), + .startup_cfgmclk(), + .startup_eos(), + .startup_preq(), + .startup_clk(1'B0), + .startup_gsr(1'B0), + .startup_gts(1'B0), + .startup_keyclearb(1'B1), + .startup_pack(1'B0), + .startup_usrcclko(1'B1), + .startup_usrcclkts(1'B0), + .startup_usrdoneo(1'B0), + .startup_usrdonets(1'B1), + .icap_clk(1'B0), + .icap_csib(1'B0), + .icap_rdwrb(1'B0), + .icap_i(32'B0), + .icap_o(), + .qpll_drp_crscode(12'B0), + .qpll_drp_fsm(18'B0), + .qpll_drp_done(2'B0), + .qpll_drp_reset(2'B0), + .qpll_qplllock(2'B0), + .qpll_qplloutclk(2'B0), + .qpll_qplloutrefclk(2'B0), + .qpll_qplld(), + .qpll_qpllreset(), + .qpll_drp_clk(), + .qpll_drp_rst_n(), + .qpll_drp_ovrd(), + .qpll_drp_gen3(), + .qpll_drp_start(), + .pipe_txprbssel(3'B0), + .pipe_rxprbssel(3'B0), + .pipe_txprbsforceerr(1'B0), + .pipe_rxprbscntreset(1'B0), + .pipe_loopback(3'B0), + .pipe_rxprbserr(), + .pipe_txinhibit(4'B0), + .pipe_rst_fsm(), + .pipe_qrst_fsm(), + .pipe_rate_fsm(), + .pipe_sync_fsm_tx(), + .pipe_sync_fsm_rx(), + .pipe_drp_fsm(), + .pipe_rst_idle(), + .pipe_qrst_idle(), + .pipe_rate_idle(), + .pipe_eyescandataerror(), + .pipe_rxstatus(), + .pipe_dmonitorout(), + .pipe_cpll_lock(), + .pipe_qpll_lock(), + .pipe_rxpmaresetdone(), + .pipe_rxbufstatus(), + .pipe_txphaligndone(), + .pipe_txphinitdone(), + .pipe_txdlysresetdone(), + .pipe_rxphaligndone(), + .pipe_rxdlysresetdone(), + .pipe_rxsyncdone(), + .pipe_rxdisperr(), + .pipe_rxnotintable(), + .pipe_rxcommadet(), + .gt_ch_drp_rdy(), + .pipe_debug_1(), + .pipe_debug_2(), + .pipe_debug_3(), + .pipe_debug_4(), + .pipe_debug_5(), + .pipe_debug_6(), + .pipe_debug_7(), + .pipe_debug_8(), + .pipe_debug_9(), + .pipe_debug(), + .ext_ch_gt_drpclk(), + .ext_ch_gt_drpaddr(36'B0), + .ext_ch_gt_drpen(4'B0), + .ext_ch_gt_drpdi(64'B0), + .ext_ch_gt_drpwe(4'B0), + .ext_ch_gt_drpdo(), + .ext_ch_gt_drprdy(), + .pcie_drp_clk(pcie_drp_clk), + .pcie_drp_en(pcie_drp_en), + .pcie_drp_we(pcie_drp_we), + .pcie_drp_addr(pcie_drp_addr), + .pcie_drp_di(pcie_drp_di), + .pcie_drp_do(pcie_drp_do), + .pcie_drp_rdy(pcie_drp_rdy), + .common_commands_in(12'B0), + .pipe_rx_0_sigs(25'B0), + .pipe_rx_1_sigs(25'B0), + .pipe_rx_2_sigs(25'B0), + .pipe_rx_3_sigs(25'B0), + .pipe_rx_4_sigs(25'B0), + .pipe_rx_5_sigs(25'B0), + .pipe_rx_6_sigs(25'B0), + .pipe_rx_7_sigs(25'B0), + .common_commands_out(), + .pipe_tx_0_sigs(), + .pipe_tx_1_sigs(), + .pipe_tx_2_sigs(), + .pipe_tx_3_sigs(), + .pipe_tx_4_sigs(), + .pipe_tx_5_sigs(), + .pipe_tx_6_sigs(), + .pipe_tx_7_sigs() + ); +endmodule diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/synth/pcie_7x_0_ooc.xdc b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/synth/pcie_7x_0_ooc.xdc new file mode 100644 index 0000000..a8b7737 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/synth/pcie_7x_0_ooc.xdc @@ -0,0 +1,76 @@ +##----------------------------------------------------------------------------- +## +## (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. +## +##----------------------------------------------------------------------------- +## Project : Series-7 Integrated Block for PCI Express +## File : pcie_7x_0_ooc.xdc +## Version : 3.3 +# +# This constraints file contains default clock frequencies to be used during out-of-context flows such as +# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified +# to match the target frequencies. +# This constraints file is not used in normal top-down synthesis (the default flow of Vivado) + +# +create_clock -name pcie_7x_0_sys_clk -period 10 [get_ports sys_clk] +# 100/125/250 MHz + +create_clock -name pcie_7x_0_pclk -period 4 [get_ports pipe_pclk_in] +# 125/250 MHz + +create_clock -name pcie_7x_0_rxusrclk -period 4 [get_ports pipe_rxusrclk_in] +# 125/250 MHz + +create_clock -name pcie_7x_0_dclk -period 8 [get_ports pipe_dclk_in] +# 125 MHz + +create_clock -name pcie_7x_0_usrclk1 -period 4 [get_ports pipe_userclk1_in] +create_clock -name pcie_7x_0_usrclk2 -period 4 [get_ports pipe_userclk2_in] + +create_clock -name pcie_7x_0_oobclk -period 4 [get_ports pipe_oobclk_in] +# 50 MHz , 125/250 MHz diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/sys_clk_gen_ps_v.txt b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/sys_clk_gen_ps_v.txt new file mode 100644 index 0000000..98b9d08 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/sys_clk_gen_ps_v.txt @@ -0,0 +1 @@ +//-------------------------------------------------------------------------------- diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci new file mode 100644 index 0000000..f5010b4 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci @@ -0,0 +1,318 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pr_read_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.000 + 0 + 4 + 4 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 6.700549 mW + zynq + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + pr_read_mem.mem + pr_read_mem.mif + 0 + 1 + 0 + 0 + 1 + 16 + 16 + 1 + 1 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 16 + 16 + WRITE_FIRST + WRITE_FIRST + 64 + 64 + zynq + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../coe/pr_read.coe + ALL + pr_read_mem + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + true + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 16 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + zynq + xilinx.com:zc706:part0:1.4 + + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + ../../../../ZC706.gen/sources_1/ip/pr_read_mem + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci new file mode 100644 index 0000000..dc67ed9 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pr_ref_mem/pr_ref_mem.xci @@ -0,0 +1,319 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pr_ref_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.000 + 0 + 6 + 6 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 6.700549 mW + zynq + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + pr_ref_mem.mem + pr_ref_mem.mif + 0 + 1 + 0 + 0 + 1 + 64 + 64 + 1 + 1 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 64 + 64 + WRITE_FIRST + WRITE_FIRST + 64 + 64 + zynq + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../coe/pr_ref.coe + ALL + pr_ref_mem + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + true + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 64 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + zynq + xilinx.com:zc706:part0:1.4 + + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + ../../../../ZC706.gen/sources_1/ip/pr_ref_mem + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xci new file mode 100644 index 0000000..3bb41a3 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/rdback_fifo/rdback_fifo.xci @@ -0,0 +1,585 @@ + + + xilinx.com + xci + unknown + 1.0 + + + rdback_fifo + + + + + + 100000000 + 0 + 0 + 0.000 + + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 1 + 0 + 11 + BlankString + 512 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 256 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 0 + 1 + 1kx36 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 895 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 894 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 12 + 2048 + 1 + 11 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + rdback_fifo + 64 + false + 11 + false + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + 0 + 895 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 894 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 512 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 256 + 2048 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + Single_Programmable_Empty_Threshold_Constant + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + Single_Programmable_Full_Threshold_Constant + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 12 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Synchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + true + false + true + true + Active_High + 0 + false + Active_High + 1 + false + 11 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + xilinx.com:zc706:part0:1.4 + + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + ../../../../ZC706.gen/sources_1/ip/rdback_fifo + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/scratchpad/scratchpad.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/scratchpad/scratchpad.xci new file mode 100644 index 0000000..368811c --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/scratchpad/scratchpad.xci @@ -0,0 +1,316 @@ + + + xilinx.com + xci + unknown + 1.0 + + + scratchpad + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.000 + 0 + 10 + 10 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 2.95215 mW + zynq + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + scratchpad.mem + no_coe_file_loaded + 0 + 0 + 0 + 0 + 1 + 1024 + 1024 + 1 + 1 + 32 + 32 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1024 + 1024 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + zynq + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + no_coe_file_loaded + ALL + scratchpad + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 1024 + 32 + 32 + No_ECC + false + false + false + Stand_Alone + zynq + xilinx.com:zc706:part0:1.4 + + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + ../../../../ZC706.gen/sources_1/ip/scratchpad + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci new file mode 100644 index 0000000..c5bcca5 --- /dev/null +++ b/projects/ZC706/ZC706.srcs/sources_1/ip/zq_calib_mem/zq_calib_mem.xci @@ -0,0 +1,319 @@ + + + xilinx.com + xci + unknown + 1.0 + + + zq_calib_mem + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.000 + 0 + 6 + 6 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 6.700549 mW + zynq + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zq_calib_mem.mem + zq_calib_mem.mif + 0 + 1 + 0 + 0 + 1 + 64 + 64 + 1 + 1 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 64 + 64 + WRITE_FIRST + WRITE_FIRST + 64 + 64 + zynq + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../coe/pr_zq.coe + ALL + zq_calib_mem + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + true + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 64 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + zynq + xilinx.com:zc706:part0:1.4 + + xc7z045 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + ../../../../ZC706.gen/sources_1/ip/zq_calib_mem + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/ZC706/ZC706.xpr b/projects/ZC706/ZC706.xpr new file mode 100644 index 0000000..2ea1269 --- /dev/null +++ b/projects/ZC706/ZC706.xpr @@ -0,0 +1,1194 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/projects/ZC706/coe/pr_zq.coe new file mode 100644 index 0000000..16d563c --- /dev/null +++ b/projects/ZC706/coe/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, 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+0000000000000001000000000000000000000000011000000000000000010110, +0100000000000000000000000000000000000000000000000001110010000110, +0000000000000001000000000000000000000000011100000000000000010111, +0100000000000000000000000000000000000000000000000001101110110111, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +0000000000000110000000000000000000000000110100000000000011110000, +0000000000000110000000000000000000000000111000000000000000000000, +0000000000000110000000000000000000000000111100000000000000000000, +0000000000000000000000000000000000000000000000000000000000000001, +1111000000000000111100000000000011110000000000001010100000001101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000011101101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001000000011111101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000011111101, +0000000000000111000000000000000000000000000000000000000000000000, +0000000000000111000000000000000000000000000100000000000000000001, +0000000000000111000000000000000000000000001000000000000000000010, +0000000000000111000000000000000000000000001100000000000000000011, +0000000000000111000000000000000000000000010000000000000000000100, +0000000000000111000000000000000000000000010100000000000000000101, +0000000000000111000000000000000000000000011000000000000000000110, +0000000000000111000000000000000000000000011100000000000000000111, +0000000000000111000000000000000000000000100000000000000000001000, +0000000000000111000000000000000000000000100100000000000000001001, +0000000000000111000000000000000000000000101000000000000000001010, +0000000000000111000000000000000000000000101100000000000000001011, +0000000000000111000000000000000000000000110000000000000000001100, +0000000000000111000000000000000000000000110100000000000000001101, +0000000000000111000000000000000000000000111000000000000000001110, +0000000000000111000000000000000000000000111100000000000000001111, +0000000000000000000000000000000000000000000000000000000000000001, +1111000000000000111100000000000011110000000000001000000011111101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000011111101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001010100000001101, +0000000000000000000000000000000000000000000000000000000000000000; \ No newline at end of file diff --git a/projects/ZC706/constraints/SODIMM.xdc b/projects/ZC706/constraints/SODIMM.xdc new file mode 100644 index 0000000..d9137ec --- /dev/null +++ b/projects/ZC706/constraints/SODIMM.xdc @@ -0,0 +1,819 @@ +create_clock -period 5.000 [get_ports c0_sys_clk_p] +set_clock_groups -asynchronous -group [get_clocks c0_sys_clk_p -include_generated_clocks] + +# Set DCI_CASCADE +set_property DCI_CASCADE {34} [get_iobanks 33] +############## NET - IOSTANDARD ################## +# Bank: 34 - PL_CPU_RESET +set_property VCCAUX_IO DONTCARE [get_ports sys_rst] +set_property IOSTANDARD LVCMOS15 [get_ports sys_rst] +set_property PACKAGE_PIN A8 [get_ports sys_rst] + +# Bank: 11 - GPIO_LED_RIGHT +#set_property DRIVE 12 [get_ports init_calib_complete] +#set_property SLEW SLOW [get_ports init_calib_complete] +#set_property IOSTANDARD LVCMOS25 [get_ports init_calib_complete] +#set_property PACKAGE_PIN W21 [get_ports init_calib_complete] + +# PadFunction: IO_L2P_T0_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[0]}] +set_property SLEW FAST [get_ports {ddr3_dq[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}] +set_property PACKAGE_PIN L1 [get_ports {ddr3_dq[0]}] + +# PadFunction: IO_L4N_T0_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[1]}] +set_property SLEW FAST [get_ports {ddr3_dq[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}] +set_property PACKAGE_PIN L2 [get_ports {ddr3_dq[1]}] + +# PadFunction: IO_L5P_T0_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[2]}] +set_property SLEW FAST [get_ports {ddr3_dq[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}] +set_property PACKAGE_PIN K5 [get_ports {ddr3_dq[2]}] + +# PadFunction: IO_L1P_T0_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[3]}] +set_property SLEW FAST [get_ports {ddr3_dq[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}] +set_property PACKAGE_PIN J4 [get_ports {ddr3_dq[3]}] + +# PadFunction: IO_L2N_T0_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[4]}] +set_property SLEW FAST [get_ports {ddr3_dq[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}] +set_property PACKAGE_PIN K1 [get_ports {ddr3_dq[4]}] + +# PadFunction: IO_L4P_T0_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[5]}] +set_property SLEW FAST [get_ports {ddr3_dq[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}] +set_property PACKAGE_PIN L3 [get_ports {ddr3_dq[5]}] + +# PadFunction: IO_L5N_T0_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[6]}] +set_property SLEW FAST [get_ports {ddr3_dq[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}] +set_property PACKAGE_PIN J5 [get_ports {ddr3_dq[6]}] + +# PadFunction: IO_L6P_T0_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[7]}] +set_property SLEW FAST [get_ports {ddr3_dq[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}] +set_property PACKAGE_PIN K6 [get_ports {ddr3_dq[7]}] + +# PadFunction: IO_L8N_T1_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[8]}] +set_property SLEW FAST [get_ports {ddr3_dq[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}] +set_property PACKAGE_PIN G6 [get_ports {ddr3_dq[8]}] + +# PadFunction: IO_L11P_T1_SRCC_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[9]}] +set_property SLEW FAST [get_ports {ddr3_dq[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}] +set_property PACKAGE_PIN H4 [get_ports {ddr3_dq[9]}] + +# PadFunction: IO_L8P_T1_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[10]}] +set_property SLEW FAST [get_ports {ddr3_dq[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}] +set_property PACKAGE_PIN H6 [get_ports {ddr3_dq[10]}] + +# PadFunction: IO_L11N_T1_SRCC_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[11]}] +set_property SLEW FAST [get_ports {ddr3_dq[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}] +set_property PACKAGE_PIN H3 [get_ports {ddr3_dq[11]}] + +# PadFunction: IO_L10N_T1_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[12]}] +set_property SLEW FAST [get_ports {ddr3_dq[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}] +set_property PACKAGE_PIN G1 [get_ports {ddr3_dq[12]}] + +# PadFunction: IO_L10P_T1_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[13]}] +set_property SLEW FAST [get_ports {ddr3_dq[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}] +set_property PACKAGE_PIN H2 [get_ports {ddr3_dq[13]}] + +# PadFunction: IO_L12P_T1_MRCC_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[14]}] +set_property SLEW FAST [get_ports {ddr3_dq[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}] +set_property PACKAGE_PIN G5 [get_ports {ddr3_dq[14]}] + +# PadFunction: IO_L12N_T1_MRCC_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[15]}] +set_property SLEW FAST [get_ports {ddr3_dq[15]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}] +set_property PACKAGE_PIN G4 [get_ports {ddr3_dq[15]}] + +# PadFunction: IO_L17N_T2_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[16]}] +set_property SLEW FAST [get_ports {ddr3_dq[16]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[16]}] +set_property PACKAGE_PIN E2 [get_ports {ddr3_dq[16]}] + +# PadFunction: IO_L17P_T2_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[17]}] +set_property SLEW FAST [get_ports {ddr3_dq[17]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[17]}] +set_property PACKAGE_PIN E3 [get_ports {ddr3_dq[17]}] + +# PadFunction: IO_L16P_T2_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[18]}] +set_property SLEW FAST [get_ports {ddr3_dq[18]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[18]}] +set_property PACKAGE_PIN D4 [get_ports {ddr3_dq[18]}] + +# PadFunction: IO_L13N_T2_MRCC_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[19]}] +set_property SLEW FAST [get_ports {ddr3_dq[19]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[19]}] +set_property PACKAGE_PIN E5 [get_ports {ddr3_dq[19]}] + +# PadFunction: IO_L14P_T2_SRCC_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[20]}] +set_property SLEW FAST [get_ports {ddr3_dq[20]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[20]}] +set_property PACKAGE_PIN F4 [get_ports {ddr3_dq[20]}] + +# PadFunction: IO_L14N_T2_SRCC_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[21]}] +set_property SLEW FAST [get_ports {ddr3_dq[21]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[21]}] +set_property PACKAGE_PIN F3 [get_ports {ddr3_dq[21]}] + +# PadFunction: IO_L18N_T2_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[22]}] +set_property SLEW FAST [get_ports {ddr3_dq[22]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[22]}] +set_property PACKAGE_PIN D1 [get_ports {ddr3_dq[22]}] + +# PadFunction: IO_L16N_T2_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[23]}] +set_property SLEW FAST [get_ports {ddr3_dq[23]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[23]}] +set_property PACKAGE_PIN D3 [get_ports {ddr3_dq[23]}] + +# PadFunction: IO_L24N_T3_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[24]}] +set_property SLEW FAST [get_ports {ddr3_dq[24]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[24]}] +set_property PACKAGE_PIN A2 [get_ports {ddr3_dq[24]}] + +# PadFunction: IO_L23P_T3_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[25]}] +set_property SLEW FAST [get_ports {ddr3_dq[25]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[25]}] +set_property PACKAGE_PIN B2 [get_ports {ddr3_dq[25]}] + +# PadFunction: IO_L20N_T3_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[26]}] +set_property SLEW FAST [get_ports {ddr3_dq[26]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[26]}] +set_property PACKAGE_PIN B4 [get_ports {ddr3_dq[26]}] + +# PadFunction: IO_L20P_T3_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[27]}] +set_property SLEW FAST [get_ports {ddr3_dq[27]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[27]}] +set_property PACKAGE_PIN B5 [get_ports {ddr3_dq[27]}] + +# PadFunction: IO_L24P_T3_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[28]}] +set_property SLEW FAST [get_ports {ddr3_dq[28]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[28]}] +set_property PACKAGE_PIN A3 [get_ports {ddr3_dq[28]}] + +# PadFunction: IO_L23N_T3_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[29]}] +set_property SLEW FAST [get_ports {ddr3_dq[29]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[29]}] +set_property PACKAGE_PIN B1 [get_ports {ddr3_dq[29]}] + +# PadFunction: IO_L22N_T3_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[30]}] +set_property SLEW FAST [get_ports {ddr3_dq[30]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[30]}] +set_property PACKAGE_PIN C1 [get_ports {ddr3_dq[30]}] + +# PadFunction: IO_L19P_T3_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[31]}] +set_property SLEW FAST [get_ports {ddr3_dq[31]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[31]}] +set_property PACKAGE_PIN C4 [get_ports {ddr3_dq[31]}] + +# PadFunction: IO_L22N_T3_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[32]}] +set_property SLEW FAST [get_ports {ddr3_dq[32]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[32]}] +set_property PACKAGE_PIN K10 [get_ports {ddr3_dq[32]}] + +# PadFunction: IO_L23N_T3_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[33]}] +set_property SLEW FAST [get_ports {ddr3_dq[33]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[33]}] +set_property PACKAGE_PIN L9 [get_ports {ddr3_dq[33]}] + +# PadFunction: IO_L24N_T3_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[34]}] +set_property SLEW FAST [get_ports {ddr3_dq[34]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[34]}] +set_property PACKAGE_PIN K12 [get_ports {ddr3_dq[34]}] + +# PadFunction: IO_L20N_T3_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[35]}] +set_property SLEW FAST [get_ports {ddr3_dq[35]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[35]}] +set_property PACKAGE_PIN J9 [get_ports {ddr3_dq[35]}] + +# PadFunction: IO_L22P_T3_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[36]}] +set_property SLEW FAST [get_ports {ddr3_dq[36]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[36]}] +set_property PACKAGE_PIN K11 [get_ports {ddr3_dq[36]}] + +# PadFunction: IO_L23P_T3_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[37]}] +set_property SLEW FAST [get_ports {ddr3_dq[37]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[37]}] +set_property PACKAGE_PIN L10 [get_ports {ddr3_dq[37]}] + +# PadFunction: IO_L20P_T3_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[38]}] +set_property SLEW FAST [get_ports {ddr3_dq[38]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[38]}] +set_property PACKAGE_PIN J10 [get_ports {ddr3_dq[38]}] + +# PadFunction: IO_L19P_T3_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[39]}] +set_property SLEW FAST [get_ports {ddr3_dq[39]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[39]}] +set_property PACKAGE_PIN L7 [get_ports {ddr3_dq[39]}] + +# PadFunction: IO_L12N_T1_MRCC_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[40]}] +set_property SLEW FAST [get_ports {ddr3_dq[40]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[40]}] +set_property PACKAGE_PIN F14 [get_ports {ddr3_dq[40]}] + +# PadFunction: IO_L12P_T1_MRCC_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[41]}] +set_property SLEW FAST [get_ports {ddr3_dq[41]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[41]}] +set_property PACKAGE_PIN F15 [get_ports {ddr3_dq[41]}] + +# PadFunction: IO_L10P_T1_AD11P_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[42]}] +set_property SLEW FAST [get_ports {ddr3_dq[42]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[42]}] +set_property PACKAGE_PIN F13 [get_ports {ddr3_dq[42]}] + +# PadFunction: IO_L7N_T1_AD2N_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[43]}] +set_property SLEW FAST [get_ports {ddr3_dq[43]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[43]}] +set_property PACKAGE_PIN G16 [get_ports {ddr3_dq[43]}] + +# PadFunction: IO_L8P_T1_AD10P_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[44]}] +set_property SLEW FAST [get_ports {ddr3_dq[44]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[44]}] +set_property PACKAGE_PIN G15 [get_ports {ddr3_dq[44]}] + +# PadFunction: IO_L10N_T1_AD11N_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[45]}] +set_property SLEW FAST [get_ports {ddr3_dq[45]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[45]}] +set_property PACKAGE_PIN E12 [get_ports {ddr3_dq[45]}] + +# PadFunction: IO_L11N_T1_SRCC_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[46]}] +set_property SLEW FAST [get_ports {ddr3_dq[46]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[46]}] +set_property PACKAGE_PIN D13 [get_ports {ddr3_dq[46]}] + +# PadFunction: IO_L11P_T1_SRCC_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[47]}] +set_property SLEW FAST [get_ports {ddr3_dq[47]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[47]}] +set_property PACKAGE_PIN E13 [get_ports {ddr3_dq[47]}] + +# PadFunction: IO_L14P_T2_AD4P_SRCC_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[48]}] +set_property SLEW FAST [get_ports {ddr3_dq[48]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[48]}] +set_property PACKAGE_PIN D15 [get_ports {ddr3_dq[48]}] + +# PadFunction: IO_L13N_T2_MRCC_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[49]}] +set_property SLEW FAST [get_ports {ddr3_dq[49]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[49]}] +set_property PACKAGE_PIN E15 [get_ports {ddr3_dq[49]}] + +# PadFunction: IO_L16P_T2_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[50]}] +set_property SLEW FAST [get_ports {ddr3_dq[50]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[50]}] +set_property PACKAGE_PIN D16 [get_ports {ddr3_dq[50]}] + +# PadFunction: IO_L13P_T2_MRCC_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[51]}] +set_property SLEW FAST [get_ports {ddr3_dq[51]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[51]}] +set_property PACKAGE_PIN E16 [get_ports {ddr3_dq[51]}] + +# PadFunction: IO_L17P_T2_AD5P_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[52]}] +set_property SLEW FAST [get_ports {ddr3_dq[52]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[52]}] +set_property PACKAGE_PIN C17 [get_ports {ddr3_dq[52]}] + +# PadFunction: IO_L17N_T2_AD5N_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[53]}] +set_property SLEW FAST [get_ports {ddr3_dq[53]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[53]}] +set_property PACKAGE_PIN B16 [get_ports {ddr3_dq[53]}] + +# PadFunction: IO_L14N_T2_AD4N_SRCC_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[54]}] +set_property SLEW FAST [get_ports {ddr3_dq[54]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[54]}] +set_property PACKAGE_PIN D14 [get_ports {ddr3_dq[54]}] + +# PadFunction: IO_L18P_T2_AD13P_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[55]}] +set_property SLEW FAST [get_ports {ddr3_dq[55]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[55]}] +set_property PACKAGE_PIN B17 [get_ports {ddr3_dq[55]}] + +# PadFunction: IO_L20N_T3_AD6N_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[56]}] +set_property SLEW FAST [get_ports {ddr3_dq[56]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[56]}] +set_property PACKAGE_PIN B12 [get_ports {ddr3_dq[56]}] + +# PadFunction: IO_L20P_T3_AD6P_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[57]}] +set_property SLEW FAST [get_ports {ddr3_dq[57]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[57]}] +set_property PACKAGE_PIN C12 [get_ports {ddr3_dq[57]}] + +# PadFunction: IO_L24N_T3_AD15N_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[58]}] +set_property SLEW FAST [get_ports {ddr3_dq[58]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[58]}] +set_property PACKAGE_PIN A12 [get_ports {ddr3_dq[58]}] + +# PadFunction: IO_L23N_T3_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[59]}] +set_property SLEW FAST [get_ports {ddr3_dq[59]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[59]}] +set_property PACKAGE_PIN A14 [get_ports {ddr3_dq[59]}] + +# PadFunction: IO_L24P_T3_AD15P_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[60]}] +set_property SLEW FAST [get_ports {ddr3_dq[60]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[60]}] +set_property PACKAGE_PIN A13 [get_ports {ddr3_dq[60]}] + +# PadFunction: IO_L22N_T3_AD7N_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[61]}] +set_property SLEW FAST [get_ports {ddr3_dq[61]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[61]}] +set_property PACKAGE_PIN B11 [get_ports {ddr3_dq[61]}] + +# PadFunction: IO_L19P_T3_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[62]}] +set_property SLEW FAST [get_ports {ddr3_dq[62]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[62]}] +set_property PACKAGE_PIN C14 [get_ports {ddr3_dq[62]}] + +# PadFunction: IO_L23P_T3_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[63]}] +set_property SLEW FAST [get_ports {ddr3_dq[63]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[63]}] +set_property PACKAGE_PIN B14 [get_ports {ddr3_dq[63]}] + +# PadFunction: IO_L1N_T0_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[13]}] +set_property SLEW FAST [get_ports {ddr3_addr[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}] +set_property PACKAGE_PIN A10 [get_ports {ddr3_addr[13]}] + +# PadFunction: IO_L9P_T1_DQS_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[12]}] +set_property SLEW FAST [get_ports {ddr3_addr[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}] +set_property PACKAGE_PIN H12 [get_ports {ddr3_addr[12]}] + +# PadFunction: IO_L4N_T0_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[11]}] +set_property SLEW FAST [get_ports {ddr3_addr[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}] +set_property PACKAGE_PIN B7 [get_ports {ddr3_addr[11]}] + +# PadFunction: IO_L17N_T2_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[10]}] +set_property SLEW FAST [get_ports {ddr3_addr[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}] +set_property PACKAGE_PIN D6 [get_ports {ddr3_addr[10]}] + +# PadFunction: IO_L15P_T2_DQS_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[9]}] +set_property SLEW FAST [get_ports {ddr3_addr[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}] +set_property PACKAGE_PIN J8 [get_ports {ddr3_addr[9]}] + +# PadFunction: IO_L1P_T0_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[8]}] +set_property SLEW FAST [get_ports {ddr3_addr[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}] +set_property PACKAGE_PIN B10 [get_ports {ddr3_addr[8]}] + +# PadFunction: IO_L14N_T2_SRCC_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[7]}] +set_property SLEW FAST [get_ports {ddr3_addr[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}] +set_property PACKAGE_PIN E8 [get_ports {ddr3_addr[7]}] + +# PadFunction: IO_L14P_T2_SRCC_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[6]}] +set_property SLEW FAST [get_ports {ddr3_addr[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}] +set_property PACKAGE_PIN F9 [get_ports {ddr3_addr[6]}] + +# PadFunction: IO_L5N_T0_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[5]}] +set_property SLEW FAST [get_ports {ddr3_addr[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}] +set_property PACKAGE_PIN B6 [get_ports {ddr3_addr[5]}] + +# PadFunction: IO_L8N_T1_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[4]}] +set_property SLEW FAST [get_ports {ddr3_addr[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}] +set_property PACKAGE_PIN D11 [get_ports {ddr3_addr[4]}] + +# PadFunction: IO_L2N_T0_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[3]}] +set_property SLEW FAST [get_ports {ddr3_addr[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}] +set_property PACKAGE_PIN A9 [get_ports {ddr3_addr[3]}] + +# PadFunction: IO_L8P_T1_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[2]}] +set_property SLEW FAST [get_ports {ddr3_addr[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}] +set_property PACKAGE_PIN E11 [get_ports {ddr3_addr[2]}] + +# PadFunction: IO_L2P_T0_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[1]}] +set_property SLEW FAST [get_ports {ddr3_addr[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}] +set_property PACKAGE_PIN B9 [get_ports {ddr3_addr[1]}] + +# PadFunction: IO_L10P_T1_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[0]}] +set_property SLEW FAST [get_ports {ddr3_addr[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}] +set_property PACKAGE_PIN E10 [get_ports {ddr3_addr[0]}] + +# PadFunction: IO_L3N_T0_DQS_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[2]}] +set_property SLEW FAST [get_ports {ddr3_ba[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}] +set_property PACKAGE_PIN A7 [get_ports {ddr3_ba[2]}] + +# PadFunction: IO_L18P_T2_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[1]}] +set_property SLEW FAST [get_ports {ddr3_ba[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}] +set_property PACKAGE_PIN H7 [get_ports {ddr3_ba[1]}] + +# PadFunction: IO_L16P_T2_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[0]}] +set_property SLEW FAST [get_ports {ddr3_ba[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}] +set_property PACKAGE_PIN F8 [get_ports {ddr3_ba[0]}] + +# PadFunction: IO_L7N_T1_34 +set_property VCCAUX_IO HIGH [get_ports ddr3_ras_n] +set_property SLEW FAST [get_ports ddr3_ras_n] +set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n] +set_property PACKAGE_PIN H11 [get_ports ddr3_ras_n] + +# PadFunction: IO_L17P_T2_34 +set_property VCCAUX_IO HIGH [get_ports ddr3_cas_n] +set_property SLEW FAST [get_ports ddr3_cas_n] +set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n] +set_property PACKAGE_PIN E7 [get_ports ddr3_cas_n] + +# PadFunction: IO_L16N_T2_34 +set_property VCCAUX_IO HIGH [get_ports ddr3_we_n] +set_property SLEW FAST [get_ports ddr3_we_n] +set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n] +set_property PACKAGE_PIN F7 [get_ports ddr3_we_n] + +# PadFunction: IO_L7P_T1_AD2P_35 +set_property VCCAUX_IO HIGH [get_ports ddr3_reset_n] +set_property SLEW FAST [get_ports ddr3_reset_n] +set_property IOSTANDARD LVCMOS15 [get_ports ddr3_reset_n] +set_property PACKAGE_PIN G17 [get_ports ddr3_reset_n] + +# PadFunction: IO_L10N_T1_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_cke[0]}] +set_property SLEW FAST [get_ports {ddr3_cke[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}] +set_property PACKAGE_PIN D10 [get_ports {ddr3_cke[0]}] + +# PadFunction: IO_L18N_T2_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_odt[0]}] +set_property SLEW FAST [get_ports {ddr3_odt[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}] +set_property PACKAGE_PIN G7 [get_ports {ddr3_odt[0]}] + +# PadFunction: IO_L7P_T1_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_cs_n[0]}] +set_property SLEW FAST [get_ports {ddr3_cs_n[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}] +set_property PACKAGE_PIN J11 [get_ports {ddr3_cs_n[0]}] + +# PadFunction: IO_L1N_T0_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[0]}] +set_property SLEW FAST [get_ports {ddr3_dm[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}] +set_property PACKAGE_PIN J3 [get_ports {ddr3_dm[0]}] + +# PadFunction: IO_L7N_T1_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[1]}] +set_property SLEW FAST [get_ports {ddr3_dm[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}] +set_property PACKAGE_PIN F2 [get_ports {ddr3_dm[1]}] + +# PadFunction: IO_L18P_T2_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[2]}] +set_property SLEW FAST [get_ports {ddr3_dm[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}] +set_property PACKAGE_PIN E1 [get_ports {ddr3_dm[2]}] + +# PadFunction: IO_L22P_T3_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[3]}] +set_property SLEW FAST [get_ports {ddr3_dm[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}] +set_property PACKAGE_PIN C2 [get_ports {ddr3_dm[3]}] + +# PadFunction: IO_L24P_T3_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[4]}] +set_property SLEW FAST [get_ports {ddr3_dm[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[4]}] +set_property PACKAGE_PIN L12 [get_ports {ddr3_dm[4]}] + +# PadFunction: IO_L8N_T1_AD10N_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[5]}] +set_property SLEW FAST [get_ports {ddr3_dm[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[5]}] +set_property PACKAGE_PIN G14 [get_ports {ddr3_dm[5]}] + +# PadFunction: IO_L16N_T2_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[6]}] +set_property SLEW FAST [get_ports {ddr3_dm[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[6]}] +set_property PACKAGE_PIN C16 [get_ports {ddr3_dm[6]}] + +# PadFunction: IO_L22P_T3_AD7P_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[7]}] +set_property SLEW FAST [get_ports {ddr3_dm[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[7]}] +set_property PACKAGE_PIN C11 [get_ports {ddr3_dm[7]}] + +set_property VCCAUX_IO DONTCARE [get_ports c0_sys_clk_p] +set_property IOSTANDARD DIFF_SSTL15 [get_ports c0_sys_clk_p] +set_property PACKAGE_PIN H9 [get_ports c0_sys_clk_p] + +set_property IOSTANDARD DIFF_SSTL15 [get_ports c0_sys_clk_n] +set_property PACKAGE_PIN G9 [get_ports c0_sys_clk_n] + +# set_property SLEW SLOW [get_ports clk_200mhz] +# set_property IOSTANDARD LVCMOS15 [get_ports clk_200mhz] +# set_property PACKAGE_PIN AJ21 [get_ports clk_200mhz] + +# PadFunction: IO_L3P_T0_DQS_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[0]}] +set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}] + +# PadFunction: IO_L3N_T0_DQS_33 +set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}] +set_property PACKAGE_PIN K3 [get_ports {ddr3_dqs_p[0]}] +set_property PACKAGE_PIN K2 [get_ports {ddr3_dqs_n[0]}] + +# PadFunction: IO_L9P_T1_DQS_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[1]}] +set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}] + +# PadFunction: IO_L9N_T1_DQS_33 +set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}] +set_property PACKAGE_PIN J1 [get_ports {ddr3_dqs_p[1]}] +set_property PACKAGE_PIN H1 [get_ports {ddr3_dqs_n[1]}] + +# PadFunction: IO_L15P_T2_DQS_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[2]}] +set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[2]}] + +# PadFunction: IO_L15N_T2_DQS_33 +set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[2]}] +set_property PACKAGE_PIN E6 [get_ports {ddr3_dqs_p[2]}] +set_property PACKAGE_PIN D5 [get_ports {ddr3_dqs_n[2]}] + +# PadFunction: IO_L21P_T3_DQS_33 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[3]}] +set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[3]}] + +# PadFunction: IO_L21N_T3_DQS_33 +set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[3]}] +set_property PACKAGE_PIN A5 [get_ports {ddr3_dqs_p[3]}] +set_property PACKAGE_PIN A4 [get_ports {ddr3_dqs_n[3]}] + +# PadFunction: IO_L21P_T3_DQS_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[4]}] +set_property SLEW FAST [get_ports {ddr3_dqs_p[4]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[4]}] + +# PadFunction: IO_L21N_T3_DQS_34 +set_property SLEW FAST [get_ports {ddr3_dqs_n[4]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[4]}] +set_property PACKAGE_PIN L8 [get_ports {ddr3_dqs_p[4]}] +set_property PACKAGE_PIN K8 [get_ports {ddr3_dqs_n[4]}] + +# PadFunction: IO_L9P_T1_DQS_AD3P_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[5]}] +set_property SLEW FAST [get_ports {ddr3_dqs_p[5]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[5]}] + +# PadFunction: IO_L9N_T1_DQS_AD3N_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[5]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[5]}] +set_property PACKAGE_PIN G12 [get_ports {ddr3_dqs_p[5]}] +set_property PACKAGE_PIN F12 [get_ports {ddr3_dqs_n[5]}] + +# PadFunction: IO_L15P_T2_DQS_AD12P_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[6]}] +set_property SLEW FAST [get_ports {ddr3_dqs_p[6]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[6]}] + +# PadFunction: IO_L15N_T2_DQS_AD12N_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[6]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[6]}] +set_property PACKAGE_PIN F17 [get_ports {ddr3_dqs_p[6]}] +set_property PACKAGE_PIN E17 [get_ports {ddr3_dqs_n[6]}] + +# PadFunction: IO_L21P_T3_DQS_AD14P_35 +set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[7]}] +set_property SLEW FAST [get_ports {ddr3_dqs_p[7]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[7]}] + +# PadFunction: IO_L21N_T3_DQS_AD14N_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[7]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[7]}] +set_property PACKAGE_PIN B15 [get_ports {ddr3_dqs_p[7]}] +set_property PACKAGE_PIN A15 [get_ports {ddr3_dqs_n[7]}] + +# PadFunction: IO_L11P_T1_SRCC_34 +set_property VCCAUX_IO HIGH [get_ports {ddr3_ck_p[0]}] +set_property SLEW FAST [get_ports {ddr3_ck_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}] + +# PadFunction: IO_L11N_T1_SRCC_34 +set_property SLEW FAST [get_ports {ddr3_ck_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}] +set_property PACKAGE_PIN G10 [get_ports {ddr3_ck_p[0]}] +set_property PACKAGE_PIN F10 [get_ports {ddr3_ck_n[0]}] + +set_property IODELAY_GROUP MEMCTL_IODELAY_MIG0 [get_cells -hier -filter {NAME =~ *.idelaye2}] + +set_property LOC PHASER_OUT_PHY_X1Y19 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y18 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y17 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y16 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y23 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y22 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y21 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y20 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y26 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y25 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y24 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] + +set_property LOC PHASER_IN_PHY_X1Y19 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y18 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y17 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y16 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y20 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y26 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y25 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y24 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] + +set_property LOC OUT_FIFO_X1Y19 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] +set_property LOC OUT_FIFO_X1Y18 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] +set_property LOC OUT_FIFO_X1Y17 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] +set_property LOC OUT_FIFO_X1Y16 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] +set_property LOC OUT_FIFO_X1Y23 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] +set_property LOC OUT_FIFO_X1Y22 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] +set_property LOC OUT_FIFO_X1Y21 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] +set_property LOC OUT_FIFO_X1Y20 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] +set_property LOC OUT_FIFO_X1Y26 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] +set_property LOC OUT_FIFO_X1Y25 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] +set_property LOC OUT_FIFO_X1Y24 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] + +set_property LOC IN_FIFO_X1Y19 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y18 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y17 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y16 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y20 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y26 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y25 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y24 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}] + +set_property LOC PHY_CONTROL_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/phy_control_i}] +set_property LOC PHY_CONTROL_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}] +set_property LOC PHY_CONTROL_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}] + +set_property LOC PHASER_REF_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_ref_i}] +set_property LOC PHASER_REF_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i}] +set_property LOC PHASER_REF_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}] + +set_property LOC OLOGIC_X1Y243 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y231 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y219 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y207 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y257 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y331 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y319 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y307 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}] + +set_property LOC PLLE2_ADV_X1Y5 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}] +set_property LOC MMCME2_ADV_X1Y5 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}] + +set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]] + +set_multicycle_path -setup -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 2 +set_multicycle_path -hold -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 1 + +set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20.000 +set_max_delay -datapath_only -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] 5.000 + +set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20.000 + +# PCIE +set_property LOC GTXE2_CHANNEL_X0Y15 [get_cells {zc706_pcie/zc706_pcie_x4_gen2_support_i/zc706_pcie_x4_gen2_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] +set_property PACKAGE_PIN P5 [get_ports {pci_exp_rxn[0]}] +set_property PACKAGE_PIN P6 [get_ports {pci_exp_rxp[0]}] +set_property PACKAGE_PIN N3 [get_ports {pci_exp_txn[0]}] +set_property PACKAGE_PIN N4 [get_ports {pci_exp_txp[0]}] + +set_property LOC GTXE2_CHANNEL_X0Y14 [get_cells {zc706_pcie/zc706_pcie_x4_gen2_support_i/zc706_pcie_x4_gen2_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] +set_property PACKAGE_PIN T5 [get_ports {pci_exp_rxn[1]}] +set_property PACKAGE_PIN T6 [get_ports {pci_exp_rxp[1]}] +set_property PACKAGE_PIN P1 [get_ports {pci_exp_txn[1]}] +set_property PACKAGE_PIN P2 [get_ports {pci_exp_txp[1]}] + +set_property LOC GTXE2_CHANNEL_X0Y13 [get_cells {zc706_pcie/zc706_pcie_x4_gen2_support_i/zc706_pcie_x4_gen2_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] +set_property PACKAGE_PIN U3 [get_ports {pci_exp_rxn[2]}] +set_property PACKAGE_PIN U4 [get_ports {pci_exp_rxp[2]}] +set_property PACKAGE_PIN R3 [get_ports {pci_exp_txn[2]}] +set_property PACKAGE_PIN R4 [get_ports {pci_exp_txp[2]}] + +set_property LOC GTXE2_CHANNEL_X0Y12 [get_cells {zc706_pcie/zc706_pcie_x4_gen2_support_i/zc706_pcie_x4_gen2_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] +set_property PACKAGE_PIN V5 [get_ports {pci_exp_rxn[3]}] +set_property PACKAGE_PIN V6 [get_ports {pci_exp_rxp[3]}] +set_property PACKAGE_PIN T1 [get_ports {pci_exp_txn[3]}] +set_property PACKAGE_PIN T2 [get_ports {pci_exp_txp[3]}] + +set_property IOSTANDARD LVCMOS15 [get_ports pcie_rst_n] +set_property PULLUP true [get_ports pcie_rst_n] +set_property PACKAGE_PIN AK23 [get_ports pcie_rst_n] + +create_clock -period 10.000 -name sys_clk -waveform {0.000 5.000} [get_ports clk_ref_p] +set_clock_groups -asynchronous -group [get_clocks sys_clk -include_generated_clocks] +set_false_path -to [get_pins zc706_pcie/zc706_pcie_x4_gen2_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S0] +set_false_path -to [get_pins zc706_pcie/zc706_pcie_x4_gen2_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S1] +create_generated_clock -name clk_125mhz_x0y0 [get_pins zc706_pcie/zc706_pcie_x4_gen2_support_i/pipe_clock_i/mmcm_i/CLKOUT0] +create_generated_clock -name clk_250mhz_x0y0 [get_pins zc706_pcie/zc706_pcie_x4_gen2_support_i/pipe_clock_i/mmcm_i/CLKOUT1] +create_generated_clock -name clk_125mhz_mux_x0y0 -source [get_pins zc706_pcie/zc706_pcie_x4_gen2_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/I0] -divide_by 1 [get_pins zc706_pcie/zc706_pcie_x4_gen2_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/O] +create_generated_clock -name clk_250mhz_mux_x0y0 -source [get_pins zc706_pcie/zc706_pcie_x4_gen2_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/I1] -divide_by 1 -add -master_clock [get_clocks -of [get_pins zc706_pcie/zc706_pcie_x4_gen2_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/I1]] [get_pins zc706_pcie/zc706_pcie_x4_gen2_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/O] +set_clock_groups -name pcieclkmux -physically_exclusive -group clk_125mhz_mux_x0y0 -group clk_250mhz_mux_x0y0 + +set_property LOC IBUFDS_GTE2_X0Y6 [get_cells zc706_pcie/refclk_ibuf] + +set_false_path -from [get_ports pcie_rst_n] diff --git a/projects/ZC706/verilog/ddr3_adapter.v b/projects/ZC706/verilog/ddr3_adapter.v new file mode 100644 index 0000000..d3305f1 --- /dev/null +++ b/projects/ZC706/verilog/ddr3_adapter.v @@ -0,0 +1,161 @@ +`timescale 1ns / 1ps +`include "parameters.vh" +`include "project.vh" + +module ddr3_adapter + ( + input clk, + input rst, + + input init_calib_complete, + + // ddr_pipeline <-> outer module if + input [3:0] ddr_write, + input [3:0] ddr_read, + input [3:0] ddr_pre, + input [3:0] ddr_act, + input [3:0] ddr_ref, + input [3:0] ddr_zq, + input [3:0] ddr_nop, + input [3:0] ddr_ap, + input [3:0] ddr_half_bl, + input [3:0] ddr_pall, + input [4*`BG_WIDTH-1:0] ddr_bg, + input [4*`BANK_WIDTH-1:0] ddr_bank, + input [4*`COL_WIDTH-1:0] ddr_col, + input [4*`ROW_WIDTH-1:0] ddr_row, + input [511:0] ddr_wdata, + + // periodic maintenance signals + input ddr_maint_read, // next read will be a maintenance read + + // Adapter <-> PHY Interface + output [3:0] mc_ras_n, // DDR Row access strobe + output [3:0] mc_cas_n, // DDR Column access strobe + output [3:0] mc_we_n, // DDR Write enable + output [4*14-1:0] mc_address, // row address for activates / column address for read&writes + output [11:0] mc_bank, // bank address + output [3:0] mc_cs_n, // chip select, probably used to deselect in NOP cycles + output mc_reset_n, // Have no idea, probably need to keep HIGH + output reg [1:0] mc_odt, // Need some logic to drive this + output [3:0] mc_cke, // This should be HIGH all the time + // AUX - For ODT and CKE assertion during reads and writes + output [3:0] mc_aux_out0, + output [3:0] mc_aux_out1, + output mc_cmd_wren, // Enqueue new command + output mc_ctl_wren, // Enqueue new control singal + output [2:0] mc_cmd, // The command to enqueue + output [1:0] mc_cas_slot, // Which CAS slot we issued this command from 0-2 + output reg [5:0] mc_data_offset, + output reg [5:0] mc_data_offset_1, + output reg [5:0] mc_data_offset_2, + output [1:0] mc_rank_cnt, + // Write + output mc_wrdata_en, // Asserted for DDR-WRITEs + output [511:0] mc_wrdata, + output [63:0] mc_wrdata_mask, + output idle, + input phy_mc_ctl_full, // CTL interface is full + input phy_mc_cmd_full, // CMD interface is full + input phy_mc_data_full, // ????????? + input [5:0] calib_rd_data_offset_0, + input [5:0] calib_rd_data_offset_1, + input [5:0] calib_rd_data_offset_2, + // Misc + output wd_fifo_rden + ); + + // TODO: Fix WRDATA - drive wrdata and mask at wrdata_stage 2 + // TODO2: is mask enabled when it is set to one or zero? + + localparam CWL = 5; + + reg [511:0] wrdata_s1, wrdata_s2; + reg mc_wrdata_en_ns; + reg wrdata_en_s1, wrdata_en_s2; + // Pipe these signals + reg [1:0] mc_odt_r, mc_odt_ns; // Needs to be HI for two consecutive cycles after each WRITE + reg [2:0] mc_cmd_int; + assign mc_cmd = mc_cmd_int; + assign mc_wrdata_mask = {64{1'b1}}; + + assign mc_wrdata = wrdata_s2; + + always @(posedge clk) begin + wrdata_en_s1 <= mc_wrdata_en_ns; + wrdata_s1 <= ddr_wdata; + wrdata_en_s2 <= wrdata_en_s1; + wrdata_s2 <= wrdata_s1; + mc_odt_r <= mc_odt_ns; + end + + // TODO: can only issue CAS commands from odd slots for now + wire [1:0] cas_offset = ddr_read[1] | ddr_write[1] ? 2'b01 : 2'b11; + + assign wd_fifo_rden = wrdata_en_s1; + assign mc_wrdata_en = wrdata_en_s2; + assign mc_reset_n = 1'b1; + assign mc_cke = {4{1'b1}}; + assign mc_aux_out0 = 3'b0; + assign mc_aux_out1 = 3'b0; + assign idle = 1'b0; + assign mc_cmd_wren = init_calib_complete; + assign mc_ctl_wren = init_calib_complete; + assign mc_cas_slot = cas_offset; + assign mc_rank_cnt = 2'b0; + + genvar cmd_off; + generate + for(cmd_off = 0 ; cmd_off < 4 ; cmd_off = cmd_off + 1) begin: for_conv + assign mc_cs_n[cmd_off] = ddr_nop[cmd_off]; // NOP + assign mc_ras_n[cmd_off] = ddr_read[cmd_off] | // READ + ddr_write[cmd_off] | // WRITE + ddr_zq[cmd_off]; // ZQS + assign mc_cas_n[cmd_off] = ddr_act[cmd_off] | // ACT + ddr_pre[cmd_off] | // PRE + ddr_pall[cmd_off] | // PRE-ALL + ddr_zq[cmd_off]; // ZQS + assign mc_we_n[cmd_off] = ddr_act[cmd_off] | // ACT + ddr_read[cmd_off] | // READ + ddr_ref[cmd_off]; // REF + assign mc_bank = ddr_bank; // TODO is this correct?? + assign mc_address[cmd_off*14 +: 14] = + (ddr_read[cmd_off] | // READ or WRITE + ddr_write[cmd_off]) ? + ddr_col[cmd_off*`COL_WIDTH+:`COL_WIDTH]: // column address if read&write + ddr_act[cmd_off] ? + ddr_row[cmd_off*`ROW_WIDTH+:`ROW_WIDTH] :// row address + ddr_pall[cmd_off] ? + 14'b00_0100_0000_0000 : 14'b0; // all zeros if PRE - 10th bit will precharge all banks + end + endgenerate + + always @* begin + mc_odt = mc_odt_r; + mc_odt_ns = 2'b0; + mc_wrdata_en_ns = 1'b0; + mc_cmd_int = 0; + if(|ddr_write) begin// WRITE + mc_cmd_int = 3'b001; + mc_data_offset = CWL + 2'b10 + 1'b1; + mc_data_offset_1 = CWL + 2'b10 + 1'b1; + mc_data_offset_2 = CWL + 2'b10 + 1'b1; + mc_odt_ns = 2'b01; + mc_odt = 2'b01; + mc_wrdata_en_ns = 1'b1; + end + else if(|ddr_read) begin// READ + mc_cmd_int = 3'b011; + mc_data_offset = calib_rd_data_offset_0[5:0]; + mc_data_offset_1 = calib_rd_data_offset_1[5:0]; + mc_data_offset_2 = calib_rd_data_offset_2[5:0]; + end + else begin + mc_cmd_int = 3'b100; + mc_data_offset = 6'b0; + mc_data_offset_1 = 6'b0; + mc_data_offset_2 = 6'b0; + end + end + +endmodule \ No newline at end of file diff --git a/projects/ZC706/verilog/instruction_buffer.v b/projects/ZC706/verilog/instruction_buffer.v new file mode 100644 index 0000000..07a81f7 --- /dev/null +++ b/projects/ZC706/verilog/instruction_buffer.v @@ -0,0 +1,164 @@ +`timescale 1ns / 1ps + +module instruction_buffer #( + parameter C_DATA_WIDTH = 64, + parameter FIFO_WIDTH = 256, + localparam KEEP_WIDTH = C_DATA_WIDTH/8 +)( + input clk, + input reset, + + input [C_DATA_WIDTH-1:0] s_axis_tdata, + input s_axis_tvalid, + input [KEEP_WIDTH-1:0] s_axis_tkeep, + output s_axis_tready, + input s_axis_tlast, + + output [FIFO_WIDTH-1:0] m_axis_tdata, + output m_axis_tvalid, + input m_axis_tready, + output m_axis_tlast +); + +localparam FIFO_SCALE = FIFO_WIDTH / C_DATA_WIDTH; +localparam FIFO_BYTES = FIFO_WIDTH / 8; +localparam DATA_BYTES = C_DATA_WIDTH / 8; + +wire wr_rst_busy; +wire rd_rst_busy; + +reg [FIFO_WIDTH-1:0] fifo_tdata_r; +reg fifo_tvalid_r; +reg fifo_tlast_r; +reg [$clog2(FIFO_BYTES):0] byte_counter_r; +reg [(C_DATA_WIDTH/2)-1:0] overflow_buffer_r; +reg overflow_flag_r; +reg s_axis_tready_r; + +reg [FIFO_WIDTH-1:0] fifo_tdata_ns; +reg fifo_tvalid_ns; +reg fifo_tlast_ns; +reg [$clog2(FIFO_BYTES):0] byte_counter_ns; +reg [(C_DATA_WIDTH/2)-1:0] overflow_buffer_ns; +reg overflow_flag_ns; +reg s_axis_tready_ns; + +wire fifo_tready; + +initial begin + fifo_tdata_r <= 0; + fifo_tvalid_r <= 0; + fifo_tlast_r <= 0; + byte_counter_r <= 0; + s_axis_tready_r <= 0; + overflow_buffer_r <= 0; + overflow_flag_r <= 0; +end + +integer i; +always @(*) begin + fifo_tdata_ns = fifo_tdata_r; + fifo_tvalid_ns = fifo_tvalid_r; + byte_counter_ns = byte_counter_r; + fifo_tlast_ns = fifo_tlast_r || s_axis_tlast; + s_axis_tready_ns = !(fifo_tvalid_r && !fifo_tready); + overflow_buffer_ns = overflow_buffer_r; + overflow_flag_ns = overflow_flag_r; + if (fifo_tvalid_r && fifo_tready) begin + fifo_tvalid_ns = 0; + fifo_tlast_ns = 0; + end + if (s_axis_tvalid && s_axis_tready_r && !(fifo_tvalid_r && !fifo_tready)) begin + if (overflow_flag_r) begin + fifo_tdata_ns[(FIFO_BYTES - 4) * 8 +: 32] = overflow_buffer_r; + overflow_flag_ns = 0; + end + case(s_axis_tkeep) + 'h0F: begin + fifo_tdata_ns[(FIFO_BYTES - byte_counter_r - 4) * 8 +: 32] = s_axis_tdata[31:0]; + byte_counter_ns = byte_counter_r + 'd4; + if (byte_counter_r == FIFO_BYTES - 'd4) begin + fifo_tvalid_ns = 1; + byte_counter_ns = 0; + s_axis_tready_ns = fifo_tready; + end + end + 'hF0: begin + fifo_tdata_ns[(FIFO_BYTES - byte_counter_r - 4) * 8 +: 32] = s_axis_tdata[63:32]; + byte_counter_ns = byte_counter_r + 'd4; + if (byte_counter_r == FIFO_BYTES - 'd4) begin + fifo_tvalid_ns = 1; + byte_counter_ns = 0; + s_axis_tready_ns = fifo_tready; + end + end + 'hFF: begin + if (byte_counter_r == FIFO_BYTES - 'd4) begin + fifo_tdata_ns[(FIFO_BYTES - byte_counter_r - 4) * 8 +: 32] = s_axis_tdata[63:32]; + overflow_buffer_ns = s_axis_tdata[31:0]; + fifo_tvalid_ns = 1; + overflow_flag_ns = 1; + byte_counter_ns = 'd4; + s_axis_tready_ns = fifo_tready; + end + else if (byte_counter_r == FIFO_BYTES - 'd8) begin + fifo_tdata_ns[(FIFO_BYTES - byte_counter_r - 8) * 8 +: 64] = s_axis_tdata; + fifo_tvalid_ns = 1; + byte_counter_ns = 'd0; + s_axis_tready_ns = fifo_tready; + end + else begin + fifo_tdata_ns[(FIFO_BYTES - byte_counter_r - 8) * 8 +: 64] = s_axis_tdata; + byte_counter_ns = byte_counter_r + 'd8; + fifo_tvalid_ns = 0; + end + end + default: begin + fifo_tdata_ns = fifo_tdata_r; + byte_counter_ns = byte_counter_r; + end + endcase + end +end + +always @(posedge clk) begin + if (reset) begin + fifo_tdata_r <= 0; + fifo_tvalid_r <= 0; + fifo_tlast_r <= 0; + byte_counter_r <= 0; + overflow_buffer_r <= 0; + overflow_flag_r <= 0; + s_axis_tready_r <= 0; + end + else begin + fifo_tdata_r <= fifo_tdata_ns; + fifo_tvalid_r <= fifo_tvalid_ns; + fifo_tlast_r <= fifo_tlast_ns; + byte_counter_r <= byte_counter_ns; + overflow_buffer_r <= overflow_buffer_ns; + overflow_flag_r <= overflow_flag_ns; + s_axis_tready_r <= s_axis_tready_ns; + end +end + +instr_fifo instr_fifo_i ( + .s_aclk(clk), // input wire s_aclk + .s_aresetn(~reset), // input wire s_aresetn + .wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy + .rd_rst_busy(rd_rst_busy), // output wire rd_rst_busy + .s_axis_tvalid(fifo_tvalid_r), // input wire s_axis_tvalid + .s_axis_tready(fifo_tready), // output wire s_axis_tready + .s_axis_tdata(fifo_tdata_r), // input wire [255 : 0] s_axis_tdata + .s_axis_tlast(fifo_tlast_r), // input wire s_axis_tlast + .m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid + .m_axis_tready(m_axis_tready), // input wire m_axis_tready + .m_axis_tdata(m_axis_tdata), // output wire [255 : 0] m_axis_tdata + .m_axis_tlast(m_axis_tlast) // output wire m_axis_tlast +); + +assign s_axis_tready = s_axis_tready_r; + +wire unused = wr_rst_busy & rd_rst_busy; + +endmodule \ No newline at end of file diff --git a/projects/ZC706/verilog/pcie_app_7x.v b/projects/ZC706/verilog/pcie_app_7x.v new file mode 100644 index 0000000..33c2b24 --- /dev/null +++ b/projects/ZC706/verilog/pcie_app_7x.v @@ -0,0 +1,207 @@ +`timescale 1ps / 1ps + +`include "project.vh" +`define PCI_EXP_EP_OUI 24'h000A35 +`define PCI_EXP_EP_DSN_1 {{8'h1},`PCI_EXP_EP_OUI} +`define PCI_EXP_EP_DSN_2 32'h00000001 + +module pcie_app_7x #( + parameter C_DATA_WIDTH = 64, // RX/TX interface data width + parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // TSTRB width +)( + input user_clk, + input user_reset, + input user_lnk_up, + + // softmc <- host + output [`SOFTMC_STREAM_WIDTH-1:0] softmc_h2c_tdata, + output [`SOFTMC_STREAM_KEEP-1:0] softmc_h2c_tkeep, + output softmc_h2c_tvalid, + input softmc_h2c_tready, + output softmc_h2c_tlast, + + // softmc -> host + input [`SOFTMC_STREAM_WIDTH-1:0] softmc_c2h_tdata, + input [`SOFTMC_STREAM_KEEP-1:0] softmc_c2h_tkeep, + input softmc_c2h_tvalid, + output softmc_c2h_tready, + input softmc_c2h_tlast, + + // Tx + input s_axis_tx_tready, + output [C_DATA_WIDTH-1:0] s_axis_tx_tdata, + output [KEEP_WIDTH-1:0] s_axis_tx_tkeep, + output [3:0] s_axis_tx_tuser, + output s_axis_tx_tlast, + output s_axis_tx_tvalid, + + // Rx + input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, + input [KEEP_WIDTH-1:0] m_axis_rx_tkeep, + input m_axis_rx_tlast, + input m_axis_rx_tvalid, + output m_axis_rx_tready, + input [21:0] m_axis_rx_tuser, + + input cfg_to_turnoff, + input [7:0] cfg_bus_number, + input [4:0] cfg_device_number, + input [2:0] cfg_function_number, + input [15:0] cfg_dcommand, + input [15:0] cfg_command, + + output tx_cfg_gnt, + output cfg_pm_halt_aspm_l0s, + output cfg_pm_halt_aspm_l1, + output cfg_pm_force_state_en, + output [1:0] cfg_pm_force_state, + output rx_np_ok, + output rx_np_req, + output cfg_turnoff_ok, + output cfg_trn_pending, + output cfg_pm_wake, + output [63:0] cfg_dsn, + // Flow Control + output [2:0] fc_sel, + // CFG + output cfg_err_cor, + output cfg_err_ur, + output cfg_err_ecrc, + output cfg_err_cpl_timeout, + output cfg_err_cpl_unexpect, + output cfg_err_cpl_abort, + output cfg_err_atomic_egress_blocked, + output cfg_err_internal_cor, + output cfg_err_malformed, + output cfg_err_mc_blocked, + output cfg_err_poisoned, + output cfg_err_norecovery, + output cfg_err_acs, + output cfg_err_internal_uncor, + output cfg_err_posted, + output cfg_err_locked, + output [47:0] cfg_err_tlp_cpl_header, + output [127:0] cfg_err_aer_headerlog, + output [4:0] cfg_aer_interrupt_msgnum, + output [1:0] pl_directed_link_change, + output [1:0] pl_directed_link_width, + output pl_directed_link_speed, + output pl_directed_link_auton, + output pl_upstream_prefer_deemph, + input cfg_mgmt_rd_wr_done, + input [31:0] cfg_mgmt_do, + output [31:0] cfg_mgmt_di, + output [3:0] cfg_mgmt_byte_en, + output [9:0] cfg_mgmt_dwaddr, + output cfg_mgmt_wr_en, + output cfg_mgmt_rd_en, + output cfg_mgmt_wr_readonly, + input cfg_interrupt_rdy, + output cfg_interrupt, + output cfg_interrupt_assert, + output [7:0] cfg_interrupt_di, + output cfg_interrupt_stat, + input cfg_interrupt_msienable, + output [4:0] cfg_pciecap_interrupt_msgnum +); + +wire [15:0] cfg_completer_id; + +assign fc_sel = 3'b0; +assign tx_cfg_gnt = 1'b1; // Always allow transmission of Config traffic within block +assign rx_np_ok = 1'b1; // Allow Reception of Non-posted Traffic +assign rx_np_req = 1'b1; // Always request Non-posted Traffic if available +assign cfg_pm_wake = 1'b0; // Never direct the core to send a PM_PME Message +assign cfg_trn_pending = 1'b0; // Never set the transaction pending bit in the Device Status Register +assign cfg_pm_halt_aspm_l0s = 1'b0; // Allow entry into L0s +assign cfg_pm_halt_aspm_l1 = 1'b0; // Allow entry into L1 +assign cfg_pm_force_state_en = 1'b0; // Do not qualify cfg_pm_force_state +assign cfg_pm_force_state = 2'b00; // Do not move force core into specific PM state +assign cfg_dsn = {`PCI_EXP_EP_DSN_2, `PCI_EXP_EP_DSN_1}; // Assign the input DSN +assign s_axis_tx_tuser[0] = 1'b0; // Unused for V6 +assign s_axis_tx_tuser[1] = 1'b0; // Error forward packet +assign s_axis_tx_tuser[2] = 1'b0; // Stream packet +assign cfg_err_cor = 1'b0; // Never report Correctable Error +assign cfg_err_ur = 1'b0; // Never report UR +assign cfg_err_ecrc = 1'b0; // Never report ECRC Error +assign cfg_err_cpl_timeout = 1'b0; // Never report Completion Timeout +assign cfg_err_cpl_abort = 1'b0; // Never report Completion Abort +assign cfg_err_cpl_unexpect = 1'b0; // Never report unexpected completion +assign cfg_err_posted = 1'b0; // Never qualify cfg_err_* inputs +assign cfg_err_locked = 1'b0; // Never qualify cfg_err_ur or cfg_err_cpl_abort +assign cfg_err_atomic_egress_blocked = 1'b0; // Never report Atomic TLP blocked +assign cfg_err_internal_cor = 1'b0; // Never report internal error occurred +assign cfg_err_malformed = 1'b0; // Never report malformed error +assign cfg_err_mc_blocked = 1'b0; // Never report multi-cast TLP blocked +assign cfg_err_poisoned = 1'b0; // Never report poisoned TLP received +assign cfg_err_norecovery = 1'b0; // Never qualify cfg_err_poisoned or cfg_err_cpl_timeout +assign cfg_err_acs = 1'b0; // Never report an ACS violation +assign cfg_err_internal_uncor = 1'b0; // Never report internal uncorrectable error +assign cfg_err_aer_headerlog = 128'h0; // Zero out the AER Header Log +assign cfg_aer_interrupt_msgnum = 5'b00000; // Zero out the AER Root Error Status Register +assign cfg_err_tlp_cpl_header = 48'h0; // Zero out the header information + +assign cfg_interrupt_stat = 1'b0; // Never set the Interrupt Status bit +assign cfg_pciecap_interrupt_msgnum = 5'b00000; // Zero out Interrupt Message Number + +assign pl_directed_link_change = 2'b00; // Never initiate link change +assign pl_directed_link_width = 2'b00; // Zero out directed link width +assign pl_directed_link_speed = 1'b0; // Zero out directed link speed +assign pl_directed_link_auton = 1'b0; // Zero out link autonomous input +assign pl_upstream_prefer_deemph = 1'b1; // Zero out preferred de-emphasis of upstream port + +assign cfg_mgmt_di = 32'h0; // Zero out CFG MGMT input data bus +assign cfg_mgmt_byte_en = 4'h0; // Zero out CFG MGMT byte enables +assign cfg_mgmt_wr_en = 1'b0; // Do not write CFG space +assign cfg_mgmt_wr_readonly = 1'b0; // Never treat RO bit as RW + +assign cfg_completer_id = {cfg_bus_number, cfg_device_number, cfg_function_number}; +assign softmc_h2c_tkeep = {`SOFTMC_STREAM_KEEP{1'b1}}; + +pcie_app_softmc #( + .C_DATA_WIDTH( C_DATA_WIDTH ), + .KEEP_WIDTH( KEEP_WIDTH ) +) softmc_app ( + .user_clk ( user_clk ), // I + .user_reset ( user_reset ), // I + .user_lnk_up ( user_lnk_up ), // I + .softmc_h2c_tdata ( softmc_h2c_tdata ), // O + .softmc_h2c_tvalid ( softmc_h2c_tvalid ), // O + .softmc_h2c_tready ( softmc_h2c_tready ), // I + .softmc_h2c_tlast ( softmc_h2c_tlast ), // O + .softmc_c2h_tdata ( softmc_c2h_tdata ), // I + .softmc_c2h_tvalid ( softmc_c2h_tvalid ), // I + .softmc_c2h_tready ( softmc_c2h_tready ), // O + .softmc_c2h_tlast ( softmc_c2h_tlast ), // I + .cfg_bus_number ( cfg_bus_number ), // I + .cfg_device_number ( cfg_device_number ), // I + .cfg_function_number ( cfg_function_number ), // I + .cfg_to_turnoff ( cfg_to_turnoff ), // I + .cfg_completer_id ( cfg_completer_id ), // I + .cfg_turnoff_ok ( cfg_turnoff_ok ), // O + .cfg_dcommand ( cfg_dcommand ), // I + .cfg_command ( cfg_command ), // I + .cfg_interrupt ( cfg_interrupt ), // O + .cfg_interrupt_assert ( cfg_interrupt_assert ), // O + .cfg_interrupt_rdy ( cfg_interrupt_rdy ), // I + .cfg_interrupt_di ( cfg_interrupt_di ), // O + .cfg_interrupt_msienable ( cfg_interrupt_msienable ), // I + .pci_cfg_dwaddr ( cfg_mgmt_dwaddr ), // O + .pci_cfg_rd_en ( cfg_mgmt_rd_en ), // O + .pci_cfg_dout ( cfg_mgmt_do ), // I + .pci_cfg_rd_wr_done ( cfg_mgmt_rd_wr_done ), // I + .s_axis_tx_tready ( s_axis_tx_tready ), // I + .s_axis_tx_tdata ( s_axis_tx_tdata ), // O + .s_axis_tx_tkeep ( s_axis_tx_tkeep ), // O + .s_axis_tx_tlast ( s_axis_tx_tlast ), // O + .s_axis_tx_tvalid ( s_axis_tx_tvalid ), // O + .tx_src_dsc ( s_axis_tx_tuser[3] ), // O + .m_axis_rx_tdata ( m_axis_rx_tdata ), // I + .m_axis_rx_tkeep ( m_axis_rx_tkeep ), // I + .m_axis_rx_tlast ( m_axis_rx_tlast ), // I + .m_axis_rx_tvalid ( m_axis_rx_tvalid ), // I + .m_axis_rx_tready ( m_axis_rx_tready ), // O + .m_axis_rx_tuser ( m_axis_rx_tuser ) // I +); + +endmodule diff --git a/projects/ZC706/verilog/pcie_softmc_app.v b/projects/ZC706/verilog/pcie_softmc_app.v new file mode 100644 index 0000000..7389078 --- /dev/null +++ b/projects/ZC706/verilog/pcie_softmc_app.v @@ -0,0 +1,957 @@ +`timescale 1ps/1ps + +`include "project.vh" + +module pcie_app_softmc #( + parameter C_DATA_WIDTH = 64, + parameter KEEP_WIDTH = C_DATA_WIDTH / 8, + + // TLP Field Constants + parameter DW_WIDTH = 32, + parameter MAX_ADDR_WIDTH = 64, + parameter DW_COUNT = 2, + parameter PKT_REQUESTER_ID_WIDTH = 16, + parameter PKT_LENGTH_WIDTH = 10, + parameter PKT_TAG_WIDTH = 8, + parameter PKT_TYPE_WIDTH = 5, + parameter PKT_FORMAT_WIDTH = 3, + parameter PKT_FIRST_WD_WIDTH = 4, + parameter PKT_LAST_WD_WIDTH = 4, + + // Internal Memory Parameters + parameter INTERNAL_MEM_DEPTH = 1024, + parameter BAR_BITS = 20 // MAX number of bits required for BAR adress space + // might seem unnecessary but saves us a subtraction + // which reduces latency (needs to be pipelined at 250+ MHz) +)( + input user_clk, + input user_reset, + input user_lnk_up, + + output [`SOFTMC_STREAM_WIDTH-1:0] softmc_h2c_tdata, + output softmc_h2c_tvalid, + input softmc_h2c_tready, + output softmc_h2c_tlast, + + input [`SOFTMC_STREAM_WIDTH-1:0] softmc_c2h_tdata, + input softmc_c2h_tvalid, + output softmc_c2h_tready, + input softmc_c2h_tlast, + + input [7:0] cfg_bus_number, + input [4:0] cfg_device_number, + input [2:0] cfg_function_number, + input [15:0] cfg_dcommand, + input [15:0] cfg_command, + output cfg_interrupt, + output cfg_interrupt_assert, + input cfg_interrupt_rdy, + output [7:0] cfg_interrupt_di, + input cfg_interrupt_msienable, + + output [9:0] pci_cfg_dwaddr, + output pci_cfg_rd_en, + input [31:0] pci_cfg_dout, + input pci_cfg_rd_wr_done, + + input s_axis_tx_tready, + output [C_DATA_WIDTH-1:0] s_axis_tx_tdata, + output [KEEP_WIDTH-1:0] s_axis_tx_tkeep, + output s_axis_tx_tlast, + output s_axis_tx_tvalid, + output tx_src_dsc, + + input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, + input [KEEP_WIDTH-1:0] m_axis_rx_tkeep, + input m_axis_rx_tlast, + input m_axis_rx_tvalid, + output m_axis_rx_tready, + input [21:0] m_axis_rx_tuser, + + input cfg_to_turnoff, + output cfg_turnoff_ok, + input [15:0] cfg_completer_id +); + +wire app_reset; + +// RX FSM Declarations +localparam RECV_IDLE = 'd0; +localparam RECV_HEAD1 = 'd1; +localparam RECV_HEAD2 = 'd2; +localparam RECV_DATA = 'd3; +localparam UNDEFINED_STATE = 'bz; + +reg [2:0] fsm_recv_state_r; +reg m_axis_rx_tready_r; +wire [7:0] rx_bar_hit; + +// TLP Declarations +localparam DW3_NODATA = 'b000; +localparam DW4_NODATA = 'b001; +localparam DW3_DATA = 'b010; +localparam DW4_DATA = 'b011; + +wire [15:0] dma_requester_id = {cfg_bus_number, cfg_device_number, cfg_function_number}; + +wire [PKT_LENGTH_WIDTH-1:0] pkt_len; +wire [PKT_REQUESTER_ID_WIDTH-1:0] pkt_requester_id; +wire [PKT_TAG_WIDTH-1:0] pkt_tag; +wire [PKT_TYPE_WIDTH-1:0] pkt_type; +wire [PKT_FORMAT_WIDTH-1:0] pkt_fmt; +wire [PKT_FIRST_WD_WIDTH-1:0] pkt_first_wd_be; +wire [PKT_LAST_WD_WIDTH-1:0] pkt_last_wd_be; +wire [3:0] pkt_valid_bytes; +wire pkt_is_MRd; +wire pkt_is_MWr; +wire pkt_is_IORd; +wire pkt_is_IOWr; + +reg [MAX_ADDR_WIDTH-1:0] pkt_local_addr; +reg pkt_bar_id; +wire [DW_WIDTH-1:0] tlp_dw[0:DW_COUNT-1]; + +reg pkt_bar_id_r; +reg [PKT_LENGTH_WIDTH-1:0] pkt_len_r; +reg [PKT_REQUESTER_ID_WIDTH-1:0] pkt_requester_id_r; +reg [PKT_TAG_WIDTH-1:0] pkt_tag_r; +reg [PKT_TYPE_WIDTH-1:0] pkt_type_r; +reg [PKT_FORMAT_WIDTH-1:0] pkt_fmt_r; +reg [PKT_FIRST_WD_WIDTH-1:0] pkt_first_wd_be_r; +reg [PKT_LAST_WD_WIDTH-1:0] pkt_last_wd_be_r; +reg [MAX_ADDR_WIDTH-1:0] pkt_addr_r; +reg [C_DATA_WIDTH-1:0] pkt_data_r; +reg [KEEP_WIDTH-1:0] pkt_data_valid_r; +reg [11:0] pkt_data_byte_ctr_r; + +// Internal Packet Data Routing Decalarations +reg [(C_DATA_WIDTH/2)-1:0] pkt_a_din; +reg [MAX_ADDR_WIDTH-1:0] pkt_a_addr; +reg pkt_a_wr_en; + +reg [(C_DATA_WIDTH/2)-1:0] pkt_b_din; +reg [MAX_ADDR_WIDTH-1:0] pkt_b_addr; +reg pkt_b_wr_en; + + +// Internal Memory Declarations +reg [(C_DATA_WIDTH/2)-1:0] mem_a_din; +reg [MAX_ADDR_WIDTH-1:0] mem_a_addr; +reg mem_a_dout; +reg mem_a_wr_en; + +reg [(C_DATA_WIDTH/2)-1:0] mem_b_din; +reg [MAX_ADDR_WIDTH-1:0] mem_b_addr; +reg mem_b_dout; +reg mem_b_wr_en; + +// TxN Buffer Declarations +wire [C_DATA_WIDTH-1:0] send_buff_tdata; +wire [C_DATA_WIDTH/2-1:0] send_buff_upper_half_data; +wire [KEEP_WIDTH-1:0] send_buff_tkeep; +wire [KEEP_WIDTH/2-1:0] send_buff_upper_half_keep; +wire send_buff_tvalid; +wire send_buff_upper_half_valid; +wire send_buff_tready; +wire send_buff_upper_half_ready; + +wire [11:0] send_buff_full_data_count; +wire [12:0] send_buff_half_data_count; +wire send_buff_programmed_stop; + +reg send_buff_tready_r; +reg send_buff_upper_half_ready_r; + + + +// Application Control Declarations +localparam COMMAND_RD = 'b01; +localparam COMMAND_WR = 'b11; +localparam COMMAND_NOP = 'b00; +localparam COMMAND_LAST_BIT = 'd3; +localparam INTR_RD_DONE = 8'd0; +localparam INTR_WR_DONE = 8'd0; + +localparam ABANDON_COUNT = 50_000_000; + +localparam SEND_IDLE = 'd0; +localparam SEND_WRITE0 = 'd1; // Starts from 0, checks buffers and timers before initiating txn. +localparam SEND_WRITE1 = 'd2; +localparam SEND_WRITE2 = 'd3; +localparam SEND_READ1 = 'd4; +localparam SEND_READ2 = 'd5; +localparam SEND_READ3 = 'd6; +localparam SEND_DATA1 = 'd7; +localparam SEND_DATA2 = 'd8; +localparam SEND_ISSUE = 'd9; +localparam SEND_INTR1 = 'd10; +localparam SEND_INTR_LEGACY1 = 'd11; +localparam SEND_INTR_LEGACY2 = 'd12; +localparam SEND_INTR_LEGACY3 = 'd13; +localparam SEND_INTR_MSI1 = 'd14; +localparam SEND_INTR_MSI2 = 'd15; +localparam SEND_STALL_READ = 'd16; +localparam SEND_TXN_REG1 = 'd17; +localparam SEND_TXN_REG2 = 'd18; +localparam SEND_TXN_REG3 = 'd19; + +reg cfg_interrupt_r; +reg [7:0] cfg_interrupt_di_r; +reg cfg_interrupt_assert_r; + +wire [10:0] cfg_max_rd_size; +wire [10:0] cfg_max_wr_size; + +reg [4:0] fsm_send_state_r; +reg [PKT_TAG_WIDTH-1:0] cmd_tag_r; +reg cmd_tag_completed_r; +reg [15:0] cmd_tag_req_len_r; +reg [15:0] tag_dw_count_r; +reg cmd_rd_is_last_r; +reg tag_tlast_r; + +reg [15:0] cmd_sent_r; +reg [15:0] cmd_remaining_r; +reg [PKT_TAG_WIDTH-1:0] cmd_remaining_tag_r; +reg [1:0] cmd_remaining_type_r; +reg [63:0] cmd_remaining_addr_r; + + +reg cmd_stat_update_r; +reg [3:0] cmd_stat_idx_r; +reg [31:0] cmd_stat_data_r; +wire cmd_bar_hit; + +wire bus_master_enabled; +wire intr_enabled; + +/* + command_controls_r: + // Temporary Regs (cleared after each command) + 0 -> command initiator + 1 -> high 32 bit address, only used for 64 bit addressing mode + 2 -> low 32 bit address + 3 -> reserved for later + // Permanent Regs (never cleared by device, must be overwritten by host) + 0 -> high 32 bit address for status writes, only used for 64 bit addressing mode + 1 -> low 32 bit address for status writes (i.e. number of bytes written, errors etc) + 2 -> 32 bit status register {16 bits->bytes written by last command, 16 bits->reserved} +*/ + +localparam NUM_TEMP_REGS = 'd4; +localparam NUM_PERM_REGS = 'd3; +localparam CMD_EXEC_REG = 'd0; +localparam CMD_HI_ADDR = 'd1; +localparam CMD_LO_ADDR = 'd2; +localparam CMD_RESERVED0 = 'd3; +localparam TXN_STATUS_HI_ADDR = NUM_TEMP_REGS + 'd0; +localparam TXN_STATUS_LO_ADDR = NUM_TEMP_REGS + 'd1; +localparam TXN_STATUS_REG = NUM_TEMP_REGS + 'd2; + +reg [31:0] command_controls_r[0:NUM_TEMP_REGS + NUM_PERM_REGS - 1]; +reg command_clear_r; + +reg [15:0] cmd_len_r; +wire [1:0] cmd_type; +wire [15:0] cmd_len; +wire cmd_tlast; +wire [15:0] cmd_wr_pkt_len; +wire [15:0] cmd_rd_pkt_len; + +reg [15:0] cmd_wr_pkt_len_r; +reg [15:0] cmd_rd_pkt_len_r; + +// Master AXIS Port Declarations +reg [C_DATA_WIDTH-1:0] s_axis_tx_tdata_r; +reg [KEEP_WIDTH-1:0] s_axis_tx_tkeep_r; +reg s_axis_tx_tlast_r; +reg s_axis_tx_tvalid_r; + +// Instruction Memory Declarations +wire [C_DATA_WIDTH-1:0] s_axis_instr_mem_tdata; +wire s_axis_instr_mem_tvalid; +wire s_axis_instr_mem_tready; +wire [KEEP_WIDTH-1:0] s_axis_instr_mem_tkeep; +wire s_axis_instr_mem_tlast; +wire [`SOFTMC_STREAM_WIDTH-1:0] m_axis_instr_mem_tdata; +wire m_axis_instr_mem_tvalid; +wire m_axis_instr_mem_tready; +wire m_axis_instr_mem_tlast; + +// Loop and Generation Declarations +integer i; +genvar j; + +// Relabelling Packet Double Words To Increase Readability +generate + for (j = 0; j < DW_COUNT; j = j + 1) begin : tlp_dw_assg + assign tlp_dw[j] = m_axis_rx_tdata[j*DW_WIDTH +: DW_WIDTH]; + end +endgenerate + +initial begin + for (i = 0; i < NUM_PERM_REGS + NUM_TEMP_REGS; i = i + 1) begin + command_controls_r[i] <= 0; + end + fsm_recv_state_r <= RECV_IDLE; + fsm_send_state_r <= SEND_IDLE; + m_axis_rx_tready_r <= 0; + pkt_data_byte_ctr_r <= 0; + pkt_a_din <= 0; + pkt_a_addr <= 0; + pkt_a_wr_en <= 0; + pkt_b_din <= 0; + pkt_b_addr <= 0; + pkt_b_wr_en <= 0; + cmd_rd_is_last_r <= 0; + command_clear_r <= 0; + s_axis_tx_tdata_r <= 0; + s_axis_tx_tkeep_r <= 0; + s_axis_tx_tlast_r <= 0; + s_axis_tx_tvalid_r <= 0; + cmd_sent_r <= 0; + cmd_remaining_r <= 0; + cmd_remaining_type_r <= 0; + cfg_interrupt_r <= 0; + cfg_interrupt_assert_r <= 0; + cfg_interrupt_di_r <= 0; + cmd_stat_update_r <= 0; + cmd_stat_idx_r <= 0; + cmd_stat_data_r <= 0; + tag_tlast_r <= 0; +end + +// Local address Conversion And Bus ID Assignment +always @(*) begin + pkt_local_addr = {64'd0, pkt_addr_r[BAR_BITS-1:0]}; + pkt_bar_id = rx_bar_hit[0] ? 'd0 : 'hFF; +end + +always @(posedge user_clk) begin + cmd_wr_pkt_len_r <= cmd_wr_pkt_len; + cmd_rd_pkt_len_r <= cmd_rd_pkt_len; +end + +// Packet Decode FSM +always @(posedge user_clk) begin + if (command_clear_r) begin + tag_dw_count_r <= 0; + end + if (app_reset) begin + fsm_recv_state_r <= RECV_IDLE; + m_axis_rx_tready_r <= 0; + pkt_data_byte_ctr_r <= 0; + tag_dw_count_r <= 0; + end + else begin + case (fsm_recv_state_r) + RECV_IDLE: begin + if (m_axis_rx_tready_r && m_axis_rx_tvalid) begin + fsm_recv_state_r <= (pkt_fmt == 'b001 || pkt_fmt == 'b011) ? RECV_HEAD1 : + (pkt_fmt == 'b000 || pkt_fmt == 'b010) ? RECV_HEAD2 : RECV_IDLE; + pkt_len_r <= pkt_len; + pkt_requester_id_r <= pkt_requester_id; + pkt_tag_r <= pkt_tag; + pkt_type_r <= pkt_type; + pkt_fmt_r <= pkt_fmt; + pkt_first_wd_be_r <= pkt_first_wd_be; + pkt_last_wd_be_r <= pkt_last_wd_be; + pkt_bar_id_r <= pkt_bar_id; + pkt_data_byte_ctr_r <= 0; + end + else begin + m_axis_rx_tready_r <= 1; + pkt_bar_id_r <= 'hFF; + end + pkt_data_valid_r <= 0; + tag_tlast_r <= 0; + end + RECV_HEAD1: begin + if (m_axis_rx_tready_r && m_axis_rx_tvalid) begin + pkt_addr_r[63:2] <= {tlp_dw[1], tlp_dw[0][31:2]}; + pkt_addr_r[1:0] <= pkt_first_wd_be_r[0] ? 'b00 : + pkt_first_wd_be_r[1] ? 'b01 : + pkt_first_wd_be_r[2] ? 'b10 : + pkt_first_wd_be_r[3] ? 'b11 : 'b00; + fsm_recv_state_r <= (pkt_fmt_r == 'b010 || pkt_fmt_r == 'b011) && (pkt_len_r != 'b1) ? RECV_DATA : RECV_IDLE; + end + else begin + m_axis_rx_tready_r <= 1; + end + pkt_data_valid_r <= 0; + end + RECV_HEAD2: begin + if (m_axis_rx_tready_r && m_axis_rx_tvalid) begin + if (pkt_type_r == 5'h0a) begin // Read Completion, update tag + pkt_tag_r <= tlp_dw[0][15:8]; + tag_tlast_r <= cmd_rd_is_last_r && (pkt_tag_r == cmd_tag_r) && (tag_dw_count_r == (cmd_tag_req_len_r - (pkt_valid_bytes / 4))); + tag_dw_count_r <= m_axis_rx_tkeep[7:4] == 'hF ? tag_dw_count_r + 1 : tag_dw_count_r; + end + pkt_addr_r[63:2] <= {32'd0, tlp_dw[0][31:2]}; + pkt_addr_r[1:0] <= pkt_first_wd_be_r[0] ? 'b00 : + pkt_first_wd_be_r[1] ? 'b01 : + pkt_first_wd_be_r[2] ? 'b10 : + pkt_first_wd_be_r[3] ? 'b11 : 'b00; + pkt_data_r[63:32] <= 32'd0; + pkt_data_r[31:0] <= tlp_dw[1]; + pkt_data_valid_r <= {4'b0, m_axis_rx_tkeep[7:4]}; + pkt_data_byte_ctr_r <= m_axis_rx_tkeep[7:4] == 'hF ? pkt_data_byte_ctr_r + 'd4 : pkt_data_byte_ctr_r; + fsm_recv_state_r <= (pkt_fmt_r == 'b010 || pkt_fmt_r == 'b011) && (pkt_len_r != 'b1) ? RECV_DATA : RECV_IDLE; + end + else begin + m_axis_rx_tready_r <= 1; + pkt_data_valid_r <= 0; + end + end + RECV_DATA: begin + if (m_axis_rx_tready_r && m_axis_rx_tvalid) begin + pkt_data_r[63:32] <= tlp_dw[1]; + pkt_data_r[31:0] <= tlp_dw[0]; + pkt_data_valid_r <= m_axis_rx_tkeep; + tag_tlast_r <= cmd_rd_is_last_r && (pkt_tag_r == cmd_tag_r) && (tag_dw_count_r == (cmd_tag_req_len_r - (pkt_valid_bytes / 4))); + tag_dw_count_r <= pkt_tag_r == cmd_tag_r ? tag_dw_count_r + (pkt_valid_bytes / 4) : tag_dw_count_r; + pkt_data_byte_ctr_r <= pkt_data_byte_ctr_r + pkt_valid_bytes; + fsm_recv_state_r <= m_axis_rx_tlast || + pkt_data_byte_ctr_r + pkt_valid_bytes >= pkt_len_r << 2 || + pkt_data_byte_ctr_r == 'd4096 ? RECV_IDLE : RECV_DATA; + end + else begin + m_axis_rx_tready_r <= 1; + pkt_data_valid_r <= 0; + tag_tlast_r <= 0; + end + end + endcase + end +end + +// Write Request Routing +// Left Port B Empty So Read Requests can be paralellized in the future +always @(*) begin + pkt_a_din = 0; + pkt_a_addr = 0; + pkt_a_wr_en = 0; + pkt_b_din = 0; + pkt_b_addr = 0; + pkt_b_wr_en = 0; + case (pkt_data_valid_r) + 'h0F: begin + pkt_a_addr = pkt_local_addr / 4; + pkt_a_din = pkt_data_r[31:0]; + pkt_a_wr_en = 1; + end + 'hF0: begin + pkt_a_addr = pkt_local_addr / 4; + pkt_a_din = pkt_data_r[63:32]; + pkt_a_wr_en = 1; + end + 'hFF: begin + pkt_a_addr = pkt_local_addr / 4; + pkt_a_din = pkt_data_r[31:0]; + pkt_a_wr_en = 1; + pkt_b_addr = pkt_local_addr / 4 + 1; + pkt_b_din = pkt_data_r[63:32]; + pkt_b_wr_en = 1; + end + default: begin + pkt_a_addr = pkt_local_addr / 4; + pkt_a_wr_en = 0; + pkt_b_addr = pkt_local_addr / 4 + 1; + pkt_b_wr_en = 0; + end + endcase +end + +// Handling Writes to command registers +always @(posedge user_clk) begin + if (app_reset) begin + for (i = 0; i < NUM_TEMP_REGS + NUM_PERM_REGS; i = i + 1) begin + command_controls_r[i] <= 0; + end + end + else begin + if (command_clear_r) begin + for (i = 0; i < NUM_TEMP_REGS; i = i + 1) begin + command_controls_r[i] <= 0; + end + end + if (cmd_bar_hit && !(command_clear_r && pkt_a_addr < NUM_TEMP_REGS)) begin + if (pkt_a_wr_en) begin + command_controls_r[pkt_a_addr] <= {<<8{pkt_a_din}}; // Big Endian -> Little Endian + end + if (pkt_b_wr_en) begin + command_controls_r[pkt_b_addr] <= {<<8{pkt_b_din}}; // Big Endian -> Little Endian + end + end + if (cmd_stat_update_r) begin + command_controls_r[cmd_stat_idx_r] <= cmd_stat_data_r; + end + end +end + +reg [14:0] available_bytes_r; +reg [14:0] available_bytes_ns; + +reg [31:0] abandon_ctr_r; +reg [31:0] abandon_ctr_ns; + +// Implement these if your module should be able to flush buffers +// One implementation could be to connect timers and apply these +// Flush just sends a single packet early, abandon drops remaining requests as well +// MUST be held high until fsm_send_state_r : SEND_WRITE0 -> SEND_WRITE1 happens +reg flush_early_r; +reg flush_early_ns; +reg abandon_cmd_r; +reg abandon_cmd_ns; + +always @(posedge user_clk) begin + if (app_reset) begin + available_bytes_r <= 0; + flush_early_r <= 0; + abandon_cmd_r <= 0; + abandon_ctr_r <= 0; + end + else begin + available_bytes_r <= available_bytes_ns; + flush_early_r <= flush_early_ns; + abandon_cmd_r <= abandon_cmd_ns; + abandon_ctr_r <= abandon_ctr_ns; + end +end + +// Combinational Application Control +always @(*) begin + flush_early_ns = fsm_send_state_r == SEND_WRITE0 ? 0 : flush_early_r; + abandon_cmd_ns = fsm_send_state_r == SEND_WRITE0 ? 0 : abandon_cmd_r; + abandon_ctr_ns = (softmc_c2h_tvalid || fsm_send_state_r != SEND_WRITE0) ? 0 : abandon_ctr_r + 1; + available_bytes_ns = send_buff_full_data_count * C_DATA_WIDTH / 8; + if (app_reset) begin + send_buff_tready_r = 0; + send_buff_upper_half_ready_r = 0; + end + else begin + if (abandon_ctr_r == ABANDON_COUNT) begin + flush_early_ns = 1; + abandon_cmd_ns = 1; + abandon_ctr_ns = 1; + end + send_buff_tready_r = 0; + send_buff_upper_half_ready_r = 0; + case (fsm_send_state_r) + SEND_WRITE2: begin + send_buff_upper_half_ready_r = s_axis_tx_tvalid_r && s_axis_tx_tready; + end + SEND_DATA1: begin + send_buff_upper_half_ready_r = s_axis_tx_tvalid_r && s_axis_tx_tready && cmd_len_r == 1; + send_buff_tready_r = s_axis_tx_tvalid_r && s_axis_tx_tready && cmd_len_r != 1; + end + endcase + end +end + +// Sequential Application Control +always @(posedge user_clk) begin + if (app_reset) begin + fsm_send_state_r <= SEND_IDLE; + command_clear_r <= 0; + cmd_sent_r <= 0; + cmd_remaining_r <= 0; + cmd_remaining_type_r <= COMMAND_NOP; + cmd_tag_r <= 0; + cmd_tag_completed_r <= 1; + end + else begin + case (fsm_send_state_r) + SEND_IDLE: begin + if (cmd_type == COMMAND_WR) begin + fsm_send_state_r <= SEND_ISSUE; + cmd_sent_r <= 0; + cmd_remaining_r <= cmd_len; + cmd_remaining_type_r <= COMMAND_WR; + cmd_rd_is_last_r <= 0; + cmd_remaining_addr_r <= {command_controls_r[CMD_HI_ADDR][31:0], command_controls_r[CMD_LO_ADDR][31:2], 2'b00}; + command_clear_r <= 1; + end + else if (cmd_type == COMMAND_RD) begin + fsm_send_state_r <= SEND_ISSUE; + cmd_tag_req_len_r <= cmd_len; + cmd_remaining_r <= cmd_len; + cmd_remaining_tag_r <= cmd_tag_r + 1; + cmd_remaining_type_r <= COMMAND_RD; + cmd_rd_is_last_r <= cmd_tlast; + cmd_remaining_addr_r <= {command_controls_r[CMD_HI_ADDR][31:0], command_controls_r[CMD_LO_ADDR][31:2], 2'b00}; + command_clear_r <= 1; + end + else begin + cmd_remaining_type_r <= COMMAND_NOP; + command_clear_r <= 0; + cmd_rd_is_last_r <= 0; + end + s_axis_tx_tvalid_r <= 0; + s_axis_tx_tlast_r <= 0; + cfg_interrupt_r <= 0; + cmd_stat_update_r <= 0; + end + SEND_ISSUE: begin + if (!bus_master_enabled) begin + cmd_remaining_type_r <= COMMAND_NOP; + fsm_send_state_r <= SEND_ISSUE; + end + else if (cmd_remaining_type_r == COMMAND_WR) begin + fsm_send_state_r <= SEND_WRITE0; + end + else if (cmd_remaining_type_r == COMMAND_RD) begin + if (cmd_tag_r == cmd_remaining_tag_r) begin + fsm_send_state_r <= SEND_READ1; + cmd_len_r <= cmd_rd_pkt_len_r; + cmd_remaining_r <= cmd_remaining_r - cmd_rd_pkt_len_r; + cmd_tag_completed_r <= 0; + end + if (cmd_tag_completed_r) begin + cmd_tag_r <= cmd_remaining_tag_r; + end + end + else begin + cmd_remaining_type_r <= COMMAND_NOP; + fsm_send_state_r <= SEND_IDLE; + end + s_axis_tx_tvalid_r <= 0; + s_axis_tx_tlast_r <= 0; + end + SEND_INTR1: begin + if (intr_enabled) begin + fsm_send_state_r <= cfg_interrupt_msienable ? SEND_INTR_MSI1 : SEND_INTR_LEGACY1; + end + else begin + fsm_send_state_r <= SEND_INTR1; + end + end + SEND_INTR_MSI1: begin + if (cfg_interrupt_r && cfg_interrupt_rdy) begin + fsm_send_state_r <= SEND_IDLE; + cmd_remaining_type_r <= COMMAND_NOP; + cfg_interrupt_r <= 0; + end + else begin + cfg_interrupt_r <= 1; + cfg_interrupt_assert_r <= 1; + cfg_interrupt_di_r <= cmd_remaining_r == COMMAND_WR ? INTR_WR_DONE : + cmd_remaining_r == COMMAND_RD ? INTR_RD_DONE : 0; + end + end + SEND_INTR_LEGACY1: begin + if (cfg_interrupt_r && cfg_interrupt_rdy) begin + fsm_send_state_r <= SEND_INTR_LEGACY2; + cfg_interrupt_r <= 0; + cfg_interrupt_assert_r <= 1; + end + else begin + cfg_interrupt_r <= 1; + cfg_interrupt_assert_r <= 1; + end + end + SEND_INTR_LEGACY2: begin + if (!intr_enabled) begin + fsm_send_state_r <= SEND_INTR_LEGACY3; + cfg_interrupt_r <= 1; + cfg_interrupt_assert_r <= 0; + end + else begin + cfg_interrupt_r <= 0; + cfg_interrupt_assert_r <= 1; + end + end + SEND_INTR_LEGACY3: begin + if (cfg_interrupt_r && cfg_interrupt_rdy) begin + fsm_send_state_r <= SEND_IDLE; + cmd_remaining_type_r <= COMMAND_NOP; + cfg_interrupt_r <= 0; + cfg_interrupt_assert_r <= 0; + end + else begin + cfg_interrupt_r <= 1; + cfg_interrupt_assert_r <= 0; + end + end + SEND_READ1: begin + fsm_send_state_r <= SEND_READ2; + s_axis_tx_tdata_r[9:0] <= cmd_len_r; + s_axis_tx_tdata_r[23:10] <= 'd0; + s_axis_tx_tdata_r[28:24] <= 'b0_0000; + s_axis_tx_tdata_r[31:29] <= DW3_NODATA; + s_axis_tx_tdata_r[35:32] <= 'hF; + s_axis_tx_tdata_r[39:36] <= cmd_len_r == 1 ? 'h0 : 'hF; + s_axis_tx_tdata_r[47:40] <= cmd_remaining_tag_r; + s_axis_tx_tdata_r[63:48] <= dma_requester_id; + s_axis_tx_tkeep_r <= 'hFF; + s_axis_tx_tvalid_r <= 1; + command_clear_r <= 0; + cmd_stat_update_r <= 0; + end + SEND_READ2: begin + if (s_axis_tx_tvalid_r && s_axis_tx_tready) begin + fsm_send_state_r <= SEND_READ3; + s_axis_tx_tdata_r[1:0] <= 'd0; + s_axis_tx_tdata_r[63:2] <= cmd_remaining_addr_r[63:2]; + cmd_remaining_addr_r <= cmd_remaining_addr_r + (cmd_len_r * 4); + s_axis_tx_tkeep_r <= 'h0F; + s_axis_tx_tlast_r <= 1; + end + s_axis_tx_tvalid_r <= 1; + command_clear_r <= 0; + cmd_stat_update_r <= 0; + end + SEND_READ3: begin + if (s_axis_tx_tvalid_r && s_axis_tx_tready) begin + fsm_send_state_r <= cmd_remaining_r == 0 ? SEND_STALL_READ : SEND_ISSUE; + s_axis_tx_tvalid_r <= 0; + s_axis_tx_tlast_r <= 0; + end + else begin + s_axis_tx_tvalid_r <= 1; + end + command_clear_r <= 0; + cmd_stat_update_r <= 0; + end + SEND_STALL_READ: begin + if (tag_dw_count_r == cmd_tag_req_len_r) begin + fsm_send_state_r <= SEND_INTR1; + cmd_tag_completed_r <= 1; + end + end + SEND_WRITE0: begin + if ((available_bytes_r / 4) >= cmd_wr_pkt_len_r) begin + fsm_send_state_r <= SEND_WRITE1; + cmd_len_r <= cmd_wr_pkt_len_r; + cmd_sent_r <= cmd_sent_r + cmd_wr_pkt_len_r * 4; + cmd_remaining_r <= cmd_remaining_r - cmd_wr_pkt_len_r; + end + else if (send_buff_programmed_stop) begin + fsm_send_state_r <= SEND_WRITE1; + cmd_len_r <= available_bytes_r >= 4 ? available_bytes_r / 4 : 1; + cmd_sent_r <= cmd_sent_r + available_bytes_r; + cmd_remaining_r <= 0; + end + else if (flush_early_r) begin + fsm_send_state_r <= SEND_WRITE1; + cmd_len_r <= available_bytes_r > 4 ? available_bytes_r / 4 : 1; + cmd_sent_r <= cmd_sent_r + available_bytes_r; + cmd_remaining_r <= abandon_cmd_r ? 0 : cmd_remaining_r - (available_bytes_r / 4); + end + else begin + fsm_send_state_r <= SEND_WRITE0; + end + end + SEND_WRITE1: begin + fsm_send_state_r <= SEND_WRITE2; + s_axis_tx_tdata_r[9:0] <= cmd_len_r; + s_axis_tx_tdata_r[23:10] <= 'd0; + s_axis_tx_tdata_r[28:24] <= 'b0_0000; + s_axis_tx_tdata_r[31:29] <= DW3_DATA; + s_axis_tx_tdata_r[35:32] <= 'hF; + s_axis_tx_tdata_r[39:36] <= cmd_len_r == 1 ? 'h0 : 'hF; + s_axis_tx_tdata_r[47:40] <= 'd0; + s_axis_tx_tdata_r[63:48] <= dma_requester_id; + s_axis_tx_tkeep_r <= 'hFF; + s_axis_tx_tvalid_r <= 1; + command_clear_r <= 0; + cmd_stat_update_r <= 0; + end + SEND_WRITE2: begin + if (s_axis_tx_tvalid_r && s_axis_tx_tready) begin + fsm_send_state_r <= cmd_len_r == 1 ? SEND_DATA2 : SEND_DATA1; + s_axis_tx_tdata_r[1:0] <= 'd0; + s_axis_tx_tdata_r[31:2] <= cmd_remaining_addr_r[31:2]; + cmd_remaining_addr_r <= cmd_remaining_addr_r + (cmd_len_r * 4); + s_axis_tx_tdata_r[63:32] <= send_buff_upper_half_data; + s_axis_tx_tkeep_r <= 'hFF; + s_axis_tx_tlast_r <= cmd_len_r == 1 ? 1 : 0; + cmd_len_r <= cmd_len_r - 1; + end + s_axis_tx_tvalid_r <= 1; + command_clear_r <= 0; + cmd_stat_update_r <= 0; + end + SEND_DATA1: begin + if (s_axis_tx_tvalid_r && s_axis_tx_tready) begin + fsm_send_state_r <= (cmd_len_r != 2 && cmd_len_r != 1) ? SEND_DATA1 : + (cmd_remaining_r == 0) ? SEND_DATA2 : SEND_ISSUE; + s_axis_tx_tdata_r[31:0] <= cmd_len_r != 1 ? send_buff_tdata[63:32] : send_buff_upper_half_data; + s_axis_tx_tdata_r[63:32] <= send_buff_tdata[31:0]; + s_axis_tx_tkeep_r <= cmd_len_r != 1 ? 'hFF : 'h0F; + s_axis_tx_tlast_r <= (cmd_len_r != 2 && cmd_len_r != 1) ? 0 : 1; + cmd_len_r <= cmd_len_r - 2; + end + s_axis_tx_tvalid_r <= 1; + command_clear_r <= 0; + cmd_stat_update_r <= 0; + end + SEND_DATA2: begin + if (s_axis_tx_tvalid_r && s_axis_tx_tready) begin + fsm_send_state_r <= SEND_TXN_REG1; + s_axis_tx_tvalid_r <= 0; + s_axis_tx_tlast_r <= 0; + cmd_stat_update_r <= 1; + cmd_stat_idx_r <= TXN_STATUS_REG; + cmd_stat_data_r <= {<<8{16'b0, cmd_sent_r}}; + end + command_clear_r <= 0; + end + SEND_TXN_REG1: begin + fsm_send_state_r <= SEND_TXN_REG2; + s_axis_tx_tdata_r[9:0] <= 'd1; + s_axis_tx_tdata_r[23:10] <= 'd0; + s_axis_tx_tdata_r[28:24] <= 'b0_0000; + s_axis_tx_tdata_r[31:29] <= DW3_DATA; + s_axis_tx_tdata_r[35:32] <= 'hF; + s_axis_tx_tdata_r[39:36] <= 'h0; + s_axis_tx_tdata_r[47:40] <= 'd0; + s_axis_tx_tdata_r[63:48] <= dma_requester_id; + s_axis_tx_tkeep_r <= 'hFF; + s_axis_tx_tvalid_r <= 1; + command_clear_r <= 0; + cmd_stat_update_r <= 0; + end + SEND_TXN_REG2: begin + if (s_axis_tx_tvalid_r && s_axis_tx_tready) begin + fsm_send_state_r <= SEND_TXN_REG3; + s_axis_tx_tdata_r[1:0] <= 'd0; + s_axis_tx_tdata_r[31:2] <= command_controls_r[TXN_STATUS_LO_ADDR][31:2]; + s_axis_tx_tdata_r[63:32] <= command_controls_r[TXN_STATUS_REG]; + s_axis_tx_tkeep_r <= 'hFF; + s_axis_tx_tlast_r <= 'd1; + end + s_axis_tx_tvalid_r <= 1; + command_clear_r <= 0; + cmd_stat_update_r <= 0; + end + SEND_TXN_REG3: begin + if (s_axis_tx_tvalid_r && s_axis_tx_tready) begin + fsm_send_state_r <= SEND_INTR1; + s_axis_tx_tvalid_r <= 0; + s_axis_tx_tlast_r <= 0; + end + end + endcase + end +end + +assign app_reset = user_reset || !user_lnk_up; +assign m_axis_rx_tready = m_axis_rx_tready_r; +assign pkt_len = tlp_dw[0][9:0]; +assign pkt_type = tlp_dw[0][28:24]; +assign pkt_fmt = tlp_dw[0][31:29]; +assign pkt_requester_id = tlp_dw[1][31:16]; +assign pkt_tag = tlp_dw[1][15:8]; +assign pkt_first_wd_be = tlp_dw[1][3:0]; +assign pkt_last_wd_be = tlp_dw[1][7:4]; +assign pkt_is_MRd = (pkt_fmt == DW3_NODATA || pkt_fmt == DW3_NODATA) && pkt_type == 'b0_0000; +assign pkt_is_MWr = (pkt_fmt == DW3_DATA || pkt_fmt == DW3_DATA) && pkt_type == 'b0_0000; +assign pkt_is_IORd = pkt_fmt == DW3_NODATA && pkt_type == 'b0_0010; +assign pkt_is_IOWr = pkt_fmt == DW4_NODATA && pkt_type == 'b0_0010; +assign pkt_valid_bytes = m_axis_rx_tkeep == 'hF0 ? 'd4 : + m_axis_rx_tkeep == 'h0F ? 'd4 : + m_axis_rx_tkeep == 'hFF ? 'd8 : 'd0; +assign cmd_tlast = command_controls_r[CMD_EXEC_REG][COMMAND_LAST_BIT]; +assign cmd_type = command_controls_r[CMD_EXEC_REG][1:0]; +assign cmd_len = command_controls_r[CMD_EXEC_REG][31:16] / 4; +assign cmd_bar_hit = pkt_bar_id_r == 'd0; +assign s_axis_tx_tdata = s_axis_tx_tdata_r; +assign s_axis_tx_tkeep = s_axis_tx_tkeep_r; +assign s_axis_tx_tlast = s_axis_tx_tlast_r; +assign s_axis_tx_tvalid = s_axis_tx_tvalid_r; +assign tx_src_dsc = 'b0; +assign cfg_turnoff_ok = 'b1; +assign rx_bar_hit = m_axis_rx_tuser[9:2]; +assign cfg_max_rd_size = (1 << (cfg_dcommand[14:12] + 'd5)); +assign cfg_max_wr_size = (1 << (cfg_dcommand[7:5] + 'd5)); +assign cfg_interrupt = cfg_interrupt_r; +assign cfg_interrupt_assert = cfg_interrupt_assert_r; +assign cfg_interrupt_di = cfg_interrupt_di_r; +assign s_axis_instr_mem_tdata = {pkt_a_din, pkt_b_din}; +assign s_axis_instr_mem_tvalid = (pkt_a_wr_en || pkt_b_wr_en) && (!cmd_bar_hit); +assign s_axis_instr_mem_tkeep = {{4{pkt_a_wr_en}}, {4{pkt_b_wr_en}}}; +assign s_axis_instr_mem_tlast = tag_tlast_r; +assign softmc_h2c_tdata = m_axis_instr_mem_tdata; +assign softmc_h2c_tvalid = m_axis_instr_mem_tvalid; +assign softmc_h2c_tlast = m_axis_instr_mem_tlast; +assign m_axis_instr_mem_tready = softmc_h2c_tready; +assign cmd_wr_pkt_len = cmd_remaining_r > cfg_max_wr_size ? cfg_max_wr_size : cmd_remaining_r; +assign cmd_rd_pkt_len = cmd_remaining_r > cfg_max_rd_size ? cfg_max_rd_size : cmd_remaining_r; +assign send_buff_full_data_count = send_buff_half_data_count / 2; +assign send_buff_tready = send_buff_tready_r; +assign send_buff_upper_half_ready = send_buff_upper_half_ready_r; +assign bus_master_enabled = cfg_command[2]; +assign intr_enabled = ~cfg_command[10]; +assign pci_cfg_dwaddr = 0; +assign pci_cfg_rd_en = 0; + +pcie_txn_buffer #( + .C_IN_DATA_WIDTH(`SOFTMC_STREAM_WIDTH), + .C_OUT_DATA_WIDTH(C_DATA_WIDTH) +) send_buff ( + .clk(user_clk), + .reset(app_reset), + .s_axis_tdata(softmc_c2h_tdata), + .s_axis_tkeep('hFFFFFFFFFFFFFFFF), + .s_axis_tvalid(softmc_c2h_tvalid), + .s_axis_tready(softmc_c2h_tready), + .s_axis_tlast(softmc_c2h_tlast), + .m_axis_tdata(send_buff_tdata), + .m_axis_tkeep(send_buff_tkeep), + .m_axis_tvalid(send_buff_tvalid), + .m_axis_tready(send_buff_tready), + .m_axis_upper_half_data(send_buff_upper_half_data), + .m_axis_upper_half_keep(send_buff_upper_half_keep), + .m_axis_upper_half_valid(send_buff_upper_half_valid), + .m_axis_upper_half_ready(send_buff_upper_half_ready), + .data_count(send_buff_half_data_count), + .programmed_stop(send_buff_programmed_stop) +); + +instruction_buffer #( + .C_DATA_WIDTH(C_DATA_WIDTH), + .FIFO_WIDTH(`SOFTMC_STREAM_WIDTH) +) instr_buff ( + .clk(user_clk), + .reset(app_reset), + .s_axis_tdata(s_axis_instr_mem_tdata), + .s_axis_tvalid(s_axis_instr_mem_tvalid), + .s_axis_tready(s_axis_instr_mem_tready), + .s_axis_tkeep(s_axis_instr_mem_tkeep), + .s_axis_tlast(s_axis_instr_mem_tlast), + .m_axis_tdata(m_axis_instr_mem_tdata), + .m_axis_tvalid(m_axis_instr_mem_tvalid), + .m_axis_tready(m_axis_instr_mem_tready), + .m_axis_tlast(m_axis_instr_mem_tlast) +); + +// ila_app debug_app ( +// .clk(user_clk), +// .probe0(cmd_rd_is_last_r), +// .probe1(app_reset), +// .probe2(cfg_interrupt_rdy), +// .probe3(intr_enabled), +// .probe4(fsm_recv_state_r), +// .probe5(fsm_send_state_r), +// .probe6(command_controls_r[CMD_EXEC_REG]), +// .probe7(tag_tlast_r), +// .probe8(cmd_sent_r), +// .probe9(command_controls_r[TXN_STATUS_REG]), +// .probe10(available_bytes_r) +// ); + +// ila_instr_fifo debug_instr_fifo ( +// .clk(user_clk), // input wire clk +// .probe0(s_axis_instr_mem_tlast), // input wire [0:0] probe0 +// .probe1(s_axis_instr_mem_tdata), // input wire [63:0] probe1 +// .probe2(s_axis_instr_mem_tvalid), // input wire [0:0] probe2 +// .probe3(s_axis_instr_mem_tready), // input wire [0:0] probe3 +// .probe4(s_axis_instr_mem_tkeep), // input wire [7:0] probe4 +// .probe5(m_axis_instr_mem_tdata), // input wire [255:0] probe5 +// .probe6(m_axis_instr_mem_tvalid), // input wire [0:0] probe6 +// .probe7(m_axis_instr_mem_tready), // input wire [0:0] probe7 +// .probe8(m_axis_instr_mem_tlast) // input wire [0:0] probe8 +// ); + +endmodule \ No newline at end of file diff --git a/projects/ZC706/verilog/pcie_top.v b/projects/ZC706/verilog/pcie_top.v new file mode 100644 index 0000000..2e5d55a --- /dev/null +++ b/projects/ZC706/verilog/pcie_top.v @@ -0,0 +1,706 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : xilinx_pcie_2_1_ep_7x.v +// Version : 3.2 +//-- +//-- Description: PCI Express Endpoint example FPGA design +//-- +//------------------------------------------------------------------------------ + +`include "project.vh" +// `define DEBUG + +`timescale 1ns / 1ps +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_top # ( + parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup + parameter EXT_PIPE_SIM = "FALSE", // This Parameter has effect on selecting Enable External PIPE Interface in GUI. + parameter PCIE_EXT_CLK = "TRUE", // Use External Clocking Module + parameter PCIE_EXT_GT_COMMON = "FALSE", + parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz + parameter C_DATA_WIDTH = 64, // RX/TX interface data width + parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // TSTRB width +) ( + output [3:0] pci_exp_txp, + output [3:0] pci_exp_txn, + input [3:0] pci_exp_rxp, + input [3:0] pci_exp_rxn, + + output led_0, + output led_2, + output led_3, + +`ifndef DEBUG + output [`SOFTMC_STREAM_WIDTH-1:0] softmc_h2c_tdata, + output [`SOFTMC_STREAM_KEEP-1:0] softmc_h2c_tkeep, + output softmc_h2c_tvalid, + input softmc_h2c_tready, + output softmc_h2c_tlast, + + input [`SOFTMC_STREAM_WIDTH-1:0] softmc_c2h_tdata, + input [`SOFTMC_STREAM_KEEP-1:0] softmc_c2h_tkeep, + input softmc_c2h_tvalid, + output softmc_c2h_tready, + input softmc_c2h_tlast, + + output user_clk_o, + output user_reset_o, +`endif + + input sys_clk_p, + input sys_clk_n, + input sys_rst_n +); + +// Wire Declarations + wire pipe_mmcm_rst_n; + + wire user_clk; + wire user_reset; + wire user_lnk_up; + + assign user_clk_o = user_clk; + assign user_reset_o = user_reset; + + // Tx + wire s_axis_tx_tready; + wire [3:0] s_axis_tx_tuser; + wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata; + wire [KEEP_WIDTH-1:0] s_axis_tx_tkeep; + wire s_axis_tx_tlast; + wire s_axis_tx_tvalid; + + // Rx + wire [C_DATA_WIDTH-1:0] m_axis_rx_tdata; + wire [KEEP_WIDTH-1:0] m_axis_rx_tkeep; + wire m_axis_rx_tlast; + wire m_axis_rx_tvalid; + wire m_axis_rx_tready; + wire [21:0] m_axis_rx_tuser; + + wire tx_cfg_gnt; + wire rx_np_ok; + wire rx_np_req; + wire cfg_turnoff_ok; + wire cfg_trn_pending; + wire cfg_pm_halt_aspm_l0s; + wire cfg_pm_halt_aspm_l1; + wire cfg_pm_force_state_en; + wire [1:0] cfg_pm_force_state; + wire cfg_pm_wake; + wire [63:0] cfg_dsn; + + // Flow Control + wire [2:0] fc_sel; + + //------------------------------------------------------- + // Configuration (CFG) Interface + //------------------------------------------------------- + wire cfg_err_ecrc; + wire cfg_err_cor; + wire cfg_err_ur; + wire cfg_err_cpl_timeout; + wire cfg_err_cpl_abort; + wire cfg_err_cpl_unexpect; + wire cfg_err_posted; + wire cfg_err_locked; + wire [47:0] cfg_err_tlp_cpl_header; + wire [127:0] cfg_err_aer_headerlog; + wire [4:0] cfg_aer_interrupt_msgnum; + + wire cfg_interrupt; + wire cfg_interrupt_rdy; + wire cfg_interrupt_assert; + wire [7:0] cfg_interrupt_di; + wire cfg_interrupt_stat; + wire [4:0] cfg_pciecap_interrupt_msgnum; + wire cfg_interrupt_msienable; + + wire cfg_to_turnoff; + wire [7:0] cfg_bus_number; + wire [4:0] cfg_device_number; + wire [2:0] cfg_function_number; + + wire [31:0] cfg_mgmt_di; + wire [31:0] cfg_mgmt_do; + wire [3:0] cfg_mgmt_byte_en; + wire [9:0] cfg_mgmt_dwaddr; + wire cfg_mgmt_wr_en; + wire cfg_mgmt_rd_en; + wire cfg_mgmt_rd_wr_done; + wire cfg_mgmt_wr_readonly; + + wire [15:0] cfg_dcommand; + wire [15:0] cfg_command; + + //------------------------------------------------------- + // Physical Layer Control and Status (PL) Interface + //------------------------------------------------------- + wire pl_directed_link_auton; + wire [1:0] pl_directed_link_change; + wire pl_directed_link_speed; + wire [1:0] pl_directed_link_width; + wire pl_upstream_prefer_deemph; + + wire sys_rst_n_c; + + +// Register Declaration + reg user_reset_q; + reg user_lnk_up_q; + reg [25:0] user_clk_heartbeat = 'h0; + +// Local Parameters + localparam TCQ = 1; + localparam USER_CLK_FREQ = 3; + localparam USER_CLK2_DIV2 = "FALSE"; + localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "TRUE") ? (USER_CLK_FREQ == 4) ? 3 : (USER_CLK_FREQ == 3) ? 2 : USER_CLK_FREQ: USER_CLK_FREQ; + + + //-----------------------------I/O BUFFERS------------------------// + + IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_rst_n)); + + IBUFDS_GTE2 refclk_ibuf (.O(sys_clk), .ODIV2(), .I(sys_clk_p), .CEB(1'b0), .IB(sys_clk_n)); + + OBUF led_0_obuf (.O(led_0), .I(!user_reset)); + OBUF led_2_obuf (.O(led_2), .I(user_lnk_up)); + OBUF led_3_obuf (.O(led_3), .I(user_clk_heartbeat[25])); + + always @(posedge user_clk) begin + user_reset_q <= user_reset; + user_lnk_up_q <= user_lnk_up; + end + + // Create a Clock Heartbeat on LED #3 + always @(posedge user_clk) begin + user_clk_heartbeat <= #TCQ user_clk_heartbeat + 1'b1; + end + + assign pipe_mmcm_rst_n = 1'b1; + +`ifdef DEBUG + localparam DATA_LIMIT = 'd1024; + wire [`SOFTMC_STREAM_WIDTH-1:0] softmc_h2c_tdata; + wire [`SOFTMC_STREAM_KEEP-1:0] softmc_h2c_tkeep; + wire softmc_h2c_tvalid; + reg softmc_h2c_tready; + wire softmc_h2c_tlast; + + reg [`SOFTMC_STREAM_WIDTH-1:0] softmc_c2h_tdata; + reg [`SOFTMC_STREAM_KEEP-1:0] softmc_c2h_tkeep; + reg softmc_c2h_tvalid; + wire softmc_c2h_tready; + reg softmc_c2h_tlast; + + reg [15:0] data_count; + reg [7:0] data_base; + + integer data_loop_i; + always @(posedge user_clk) begin + if (user_reset_q) begin + softmc_c2h_tdata <= 0; + softmc_c2h_tkeep <= 0; + softmc_c2h_tvalid <= 0; + softmc_c2h_tlast <= 0; + softmc_h2c_tready <= 0; + data_count <= 0; + data_base <= 0; + end + else begin + softmc_c2h_tkeep <= {`SOFTMC_STREAM_KEEP{1'b1}}; + softmc_c2h_tlast <= data_count == (DATA_LIMIT - 1); + softmc_h2c_tready <= 1; + if (softmc_c2h_tready && softmc_c2h_tvalid) begin + for (data_loop_i = 0; data_loop_i < `SOFTMC_STREAM_KEEP; data_loop_i = data_loop_i + 1) begin + softmc_c2h_tdata[(`SOFTMC_STREAM_KEEP - data_loop_i - 1) * 8 +: 8] <= (data_base + `SOFTMC_STREAM_KEEP) + data_loop_i; + end + softmc_c2h_tvalid <= data_count < (DATA_LIMIT - 1); + data_count <= data_count + (`SOFTMC_STREAM_WIDTH / 32); // each data is 32 bits long + data_base <= data_base + `SOFTMC_STREAM_KEEP; + end + else begin + for (data_loop_i = 0; data_loop_i < `SOFTMC_STREAM_KEEP; data_loop_i = data_loop_i + 1) begin + softmc_c2h_tdata[(`SOFTMC_STREAM_KEEP - data_loop_i - 1) * 8 +: 8] <= data_base + data_loop_i; + end + softmc_c2h_tvalid <= data_count < DATA_LIMIT; + end + end + end +`endif + +zc706_pcie_x4_gen2_support # + ( + .LINK_CAP_MAX_LINK_WIDTH ( 4 ), // PCIe Lane Width + .C_DATA_WIDTH ( C_DATA_WIDTH ), // RX/TX interface data width + .KEEP_WIDTH ( KEEP_WIDTH ), // TSTRB width + .PCIE_REFCLK_FREQ ( REF_CLK_FREQ ), // PCIe reference clock frequency + .PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ), // PCIe user clock 1 frequency + .PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 ), // PCIe user clock 2 frequency + .PCIE_USE_MODE ("3.0"), // PCIe use mode + .PCIE_GT_DEVICE ("GTX") // PCIe GT device + ) +zc706_pcie_x4_gen2_support_i + ( + + //----------------------------------------------------------------------------------------------------------------// + // PCI Express (pci_exp) Interface // + //----------------------------------------------------------------------------------------------------------------// + // Tx + .pci_exp_txn ( pci_exp_txn ), + .pci_exp_txp ( pci_exp_txp ), + + // Rx + .pci_exp_rxn ( pci_exp_rxn ), + .pci_exp_rxp ( pci_exp_rxp ), + + //----------------------------------------------------------------------------------------------------------------// + // Clocking Sharing Interface // + //----------------------------------------------------------------------------------------------------------------// + .pipe_pclk_out_slave ( ), + .pipe_rxusrclk_out ( ), + .pipe_rxoutclk_out ( ), + .pipe_dclk_out ( ), + .pipe_userclk1_out ( ), + .pipe_oobclk_out ( ), + .pipe_userclk2_out ( ), + .pipe_mmcm_lock_out ( ), + .pipe_pclk_sel_slave ( 4'b0), + .pipe_mmcm_rst_n ( pipe_mmcm_rst_n ), // Async | Async + + + //----------------------------------------------------------------------------------------------------------------// + // AXI-S Interface // + //----------------------------------------------------------------------------------------------------------------// + + // Common + .user_clk_out ( user_clk ), + .user_reset_out ( user_reset ), + .user_lnk_up ( user_lnk_up ), + .user_app_rdy ( ), + + // TX + .s_axis_tx_tready ( s_axis_tx_tready ), + .s_axis_tx_tdata ( s_axis_tx_tdata ), + .s_axis_tx_tkeep ( s_axis_tx_tkeep ), + .s_axis_tx_tuser ( s_axis_tx_tuser ), + .s_axis_tx_tlast ( s_axis_tx_tlast ), + .s_axis_tx_tvalid ( s_axis_tx_tvalid ), + + // Rx + .m_axis_rx_tdata ( m_axis_rx_tdata ), + .m_axis_rx_tkeep ( m_axis_rx_tkeep ), + .m_axis_rx_tlast ( m_axis_rx_tlast ), + .m_axis_rx_tvalid ( m_axis_rx_tvalid ), + .m_axis_rx_tready ( m_axis_rx_tready ), + .m_axis_rx_tuser ( m_axis_rx_tuser ), + + // Flow Control + .fc_cpld ( ), + .fc_cplh ( ), + .fc_npd ( ), + .fc_nph ( ), + .fc_pd ( ), + .fc_ph ( ), + .fc_sel ( fc_sel ), + + // Management Interface + .cfg_mgmt_di ( cfg_mgmt_di ), + .cfg_mgmt_byte_en ( cfg_mgmt_byte_en ), + .cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ), + .cfg_mgmt_wr_en ( cfg_mgmt_wr_en ), + .cfg_mgmt_rd_en ( cfg_mgmt_rd_en ), + .cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ), + + //------------------------------------------------// + // EP and RP // + //------------------------------------------------// + .cfg_mgmt_do ( cfg_mgmt_do ), + .cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ), + .cfg_mgmt_wr_rw1c_as_rw ( 1'b0 ), + + // Error Reporting Interface + .cfg_err_ecrc ( cfg_err_ecrc ), + .cfg_err_ur ( cfg_err_ur ), + .cfg_err_cpl_timeout ( cfg_err_cpl_timeout ), + .cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ), + .cfg_err_cpl_abort ( cfg_err_cpl_abort ), + .cfg_err_posted ( cfg_err_posted ), + .cfg_err_cor ( cfg_err_cor ), + .cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ), + .cfg_err_internal_cor ( cfg_err_internal_cor ), + .cfg_err_malformed ( cfg_err_malformed ), + .cfg_err_mc_blocked ( cfg_err_mc_blocked ), + .cfg_err_poisoned ( cfg_err_poisoned ), + .cfg_err_norecovery ( cfg_err_norecovery ), + .cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ), + .cfg_err_cpl_rdy ( ), + .cfg_err_locked ( cfg_err_locked ), + .cfg_err_acs ( cfg_err_acs ), + .cfg_err_internal_uncor ( cfg_err_internal_uncor ), + + //----------------------------------------------------------------------------------------------------------------// + // AER Interface // + //----------------------------------------------------------------------------------------------------------------// + .cfg_err_aer_headerlog ( cfg_err_aer_headerlog ), + .cfg_err_aer_headerlog_set ( ), + .cfg_aer_ecrc_check_en ( ), + .cfg_aer_ecrc_gen_en ( ), + .cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ), + + .tx_cfg_gnt ( tx_cfg_gnt ), + .rx_np_ok ( rx_np_ok ), + .rx_np_req ( rx_np_req ), + .cfg_trn_pending ( cfg_trn_pending ), + .cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ), + .cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ), + .cfg_pm_force_state_en ( cfg_pm_force_state_en ), + .cfg_pm_force_state ( cfg_pm_force_state ), + .cfg_dsn ( cfg_dsn ), + .cfg_turnoff_ok ( cfg_turnoff_ok ), + .cfg_pm_wake ( cfg_pm_wake ), + //------------------------------------------------// + // RP Only // + //------------------------------------------------// + .cfg_pm_send_pme_to ( 1'b0 ), + .cfg_ds_bus_number ( 8'b0 ), + .cfg_ds_device_number ( 5'b0 ), + .cfg_ds_function_number ( 3'b0 ), + + //------------------------------------------------// + // EP Only // + //------------------------------------------------// + .cfg_interrupt ( cfg_interrupt ), + .cfg_interrupt_rdy ( cfg_interrupt_rdy ), + .cfg_interrupt_assert ( cfg_interrupt_assert ), + .cfg_interrupt_di ( cfg_interrupt_di ), + .cfg_interrupt_do ( ), + .cfg_interrupt_mmenable ( ), + .cfg_interrupt_msienable ( cfg_interrupt_msienable ), + .cfg_interrupt_msixenable ( ), + .cfg_interrupt_msixfm ( ), + .cfg_interrupt_stat ( cfg_interrupt_stat ), + .cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ), + + //----------------------------------------------------------------------------------------------------------------// + // Configuration (CFG) Interface // + //----------------------------------------------------------------------------------------------------------------// + .cfg_status ( ), + .cfg_command ( cfg_command ), + .cfg_dstatus ( ), + .cfg_lstatus ( ), + .cfg_pcie_link_state ( ), + .cfg_dcommand ( cfg_dcommand ), + .cfg_lcommand ( ), + .cfg_dcommand2 ( ), + + .cfg_pmcsr_pme_en ( ), + .cfg_pmcsr_powerstate ( ), + .cfg_pmcsr_pme_status ( ), + .cfg_received_func_lvl_rst ( ), + .tx_buf_av ( ), + .tx_err_drop ( ), + .tx_cfg_req ( ), + .cfg_to_turnoff ( cfg_to_turnoff ), + .cfg_bus_number ( cfg_bus_number ), + .cfg_device_number ( cfg_device_number ), + .cfg_function_number ( cfg_function_number ), + .cfg_bridge_serr_en ( ), + .cfg_slot_control_electromech_il_ctl_pulse ( ), + .cfg_root_control_syserr_corr_err_en ( ), + .cfg_root_control_syserr_non_fatal_err_en ( ), + .cfg_root_control_syserr_fatal_err_en ( ), + .cfg_root_control_pme_int_en ( ), + .cfg_aer_rooterr_corr_err_reporting_en ( ), + .cfg_aer_rooterr_non_fatal_err_reporting_en( ), + .cfg_aer_rooterr_fatal_err_reporting_en ( ), + .cfg_aer_rooterr_corr_err_received ( ), + .cfg_aer_rooterr_non_fatal_err_received ( ), + .cfg_aer_rooterr_fatal_err_received ( ), + //----------------------------------------------------------------------------------------------------------------// + // VC interface // + //---------------------------------------------------------------------------------------------------------------// + .cfg_vc_tcvc_map ( ), + + .cfg_msg_received ( ), + .cfg_msg_data ( ), + .cfg_msg_received_err_cor ( ), + .cfg_msg_received_err_non_fatal ( ), + .cfg_msg_received_err_fatal ( ), + .cfg_msg_received_pm_as_nak ( ), + .cfg_msg_received_pme_to_ack ( ), + .cfg_msg_received_assert_int_a ( ), + .cfg_msg_received_assert_int_b ( ), + .cfg_msg_received_assert_int_c ( ), + .cfg_msg_received_assert_int_d ( ), + .cfg_msg_received_deassert_int_a ( ), + .cfg_msg_received_deassert_int_b ( ), + .cfg_msg_received_deassert_int_c ( ), + .cfg_msg_received_deassert_int_d ( ), + .cfg_msg_received_pm_pme ( ), + .cfg_msg_received_setslotpowerlimit ( ), + + //----------------------------------------------------------------------------------------------------------------// + // Physical Layer Control and Status (PL) Interface // + //----------------------------------------------------------------------------------------------------------------// + .pl_directed_link_change ( pl_directed_link_change ), + .pl_directed_link_width ( pl_directed_link_width ), + .pl_directed_link_speed ( pl_directed_link_speed ), + .pl_directed_link_auton ( pl_directed_link_auton ), + .pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ), + + .pl_sel_lnk_rate ( ), + .pl_sel_lnk_width ( ), + .pl_ltssm_state ( ), + .pl_lane_reversal_mode ( ), + + .pl_phy_lnk_up ( ), + .pl_tx_pm_state ( ), + .pl_rx_pm_state ( ), + + .pl_link_upcfg_cap ( ), + .pl_link_gen2_cap ( ), + .pl_link_partner_gen2_supported ( ), + .pl_initial_link_width ( ), + + .pl_directed_change_done ( ), + + //------------------------------------------------// + // EP Only // + //------------------------------------------------// + .pl_received_hot_rst ( ), + + //------------------------------------------------// + // RP Only // + //------------------------------------------------// + .pl_transmit_hot_rst ( 1'b0 ), + .pl_downstream_deemph_source ( 1'b0 ), + + //----------------------------------------------------------------------------------------------------------------// + // PCIe DRP (PCIe DRP) Interface // + //----------------------------------------------------------------------------------------------------------------// + .pcie_drp_clk ( 1'b1 ), + .pcie_drp_en ( 1'b0 ), + .pcie_drp_we ( 1'b0 ), + .pcie_drp_addr ( 9'h0 ), + .pcie_drp_di ( 16'h0 ), + .pcie_drp_rdy ( ), + .pcie_drp_do ( ), + + + + //----------------------------------------------------------------------------------------------------------------// + // System (SYS) Interface // + //----------------------------------------------------------------------------------------------------------------// + .sys_clk ( sys_clk ), + .sys_rst_n ( sys_rst_n_c ) + +); + +pcie_app_7x #( + .C_DATA_WIDTH( C_DATA_WIDTH ) +) app ( + + //----------------------------------------------------------------------------------------------------------------// + // AXI-S Interface // + //----------------------------------------------------------------------------------------------------------------// + + // Common + .user_clk ( user_clk ), + .user_reset ( user_reset_q ), + .user_lnk_up ( user_lnk_up_q ), + + // Tx + .s_axis_tx_tready ( s_axis_tx_tready ), + .s_axis_tx_tdata ( s_axis_tx_tdata ), + .s_axis_tx_tkeep ( s_axis_tx_tkeep ), + .s_axis_tx_tuser ( s_axis_tx_tuser ), + .s_axis_tx_tlast ( s_axis_tx_tlast ), + .s_axis_tx_tvalid ( s_axis_tx_tvalid ), + + // Rx + .m_axis_rx_tdata ( m_axis_rx_tdata ), + .m_axis_rx_tkeep ( m_axis_rx_tkeep ), + .m_axis_rx_tlast ( m_axis_rx_tlast ), + .m_axis_rx_tvalid ( m_axis_rx_tvalid ), + .m_axis_rx_tready ( m_axis_rx_tready ), + .m_axis_rx_tuser ( m_axis_rx_tuser ), + + .tx_cfg_gnt ( tx_cfg_gnt ), + .rx_np_ok ( rx_np_ok ), + .rx_np_req ( rx_np_req ), + .cfg_turnoff_ok ( cfg_turnoff_ok ), + .cfg_trn_pending ( cfg_trn_pending ), + .cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ), + .cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ), + .cfg_pm_force_state_en ( cfg_pm_force_state_en ), + .cfg_pm_force_state ( cfg_pm_force_state ), + .cfg_pm_wake ( cfg_pm_wake ), + .cfg_dsn ( cfg_dsn ), + .cfg_dcommand ( cfg_dcommand ), + .cfg_command ( cfg_command ), + + // Flow Control + .fc_sel ( fc_sel ), + + //----------------------------------------------------------------------------------------------------------------// + // Configuration (CFG) Interface // + //----------------------------------------------------------------------------------------------------------------// + .cfg_err_cor ( cfg_err_cor ), + .cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ), + .cfg_err_internal_cor ( cfg_err_internal_cor ), + .cfg_err_malformed ( cfg_err_malformed ), + .cfg_err_mc_blocked ( cfg_err_mc_blocked ), + .cfg_err_poisoned ( cfg_err_poisoned ), + .cfg_err_norecovery ( cfg_err_norecovery ), + .cfg_err_ur ( cfg_err_ur ), + .cfg_err_ecrc ( cfg_err_ecrc ), + .cfg_err_cpl_timeout ( cfg_err_cpl_timeout ), + .cfg_err_cpl_abort ( cfg_err_cpl_abort ), + .cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ), + .cfg_err_posted ( cfg_err_posted ), + .cfg_err_locked ( cfg_err_locked ), + .cfg_err_acs ( cfg_err_acs ), //1'b0 ), + .cfg_err_internal_uncor ( cfg_err_internal_uncor ), //1'b0 ), + .cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ), + //----------------------------------------------------------------------------------------------------------------// + // Advanced Error Reporting (AER) Interface // + //----------------------------------------------------------------------------------------------------------------// + .cfg_err_aer_headerlog ( cfg_err_aer_headerlog ), + .cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ), + + .cfg_to_turnoff ( cfg_to_turnoff ), + .cfg_bus_number ( cfg_bus_number ), + .cfg_device_number ( cfg_device_number ), + .cfg_function_number ( cfg_function_number ), + + //----------------------------------------------------------------------------------------------------------------// + // Management (MGMT) Interface // + //----------------------------------------------------------------------------------------------------------------// + .cfg_mgmt_di ( cfg_mgmt_di ), + .cfg_mgmt_do ( cfg_mgmt_do ), + .cfg_mgmt_byte_en ( cfg_mgmt_byte_en ), + .cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ), + .cfg_mgmt_wr_en ( cfg_mgmt_wr_en ), + .cfg_mgmt_rd_en ( cfg_mgmt_rd_en ), + .cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ), + .cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ), + + //----------------------------------------------------------------------------------------------------------------// + // Physical Layer Control and Status (PL) Interface // + //----------------------------------------------------------------------------------------------------------------// + .pl_directed_link_auton ( pl_directed_link_auton ), + .pl_directed_link_change ( pl_directed_link_change ), + .pl_directed_link_speed ( pl_directed_link_speed ), + .pl_directed_link_width ( pl_directed_link_width ), + .pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ), + + .cfg_interrupt ( cfg_interrupt ), + .cfg_interrupt_rdy ( cfg_interrupt_rdy ), + .cfg_interrupt_assert ( cfg_interrupt_assert ), + .cfg_interrupt_di ( cfg_interrupt_di ), + .cfg_interrupt_stat ( cfg_interrupt_stat ), + .cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ), + .cfg_interrupt_msienable ( cfg_interrupt_msienable ), + + //--------------------------------------------------------------------------------------------------------------// + // Streaming Data Transfer Interface // + //--------------------------------------------------------------------------------------------------------------// + .softmc_h2c_tdata ( softmc_h2c_tdata ), + .softmc_h2c_tkeep ( softmc_h2c_tkeep ), + .softmc_h2c_tvalid ( softmc_h2c_tvalid ), + .softmc_h2c_tready ( softmc_h2c_tready ), + .softmc_h2c_tlast ( softmc_h2c_tlast ), + + .softmc_c2h_tdata ( softmc_c2h_tdata ), + .softmc_c2h_tkeep ( softmc_c2h_tkeep ), + .softmc_c2h_tvalid ( softmc_c2h_tvalid ), + .softmc_c2h_tready ( softmc_c2h_tready ), + .softmc_c2h_tlast ( softmc_c2h_tlast ) +); + +// ila_ms debug_maxis ( +// .clk ( user_clk ), +// .probe0 ( m_axis_rx_tdata ), +// .probe1 ( m_axis_rx_tkeep ), +// .probe2 ( m_axis_rx_tvalid ), +// .probe3 ( m_axis_rx_tready ), +// .probe4 ( m_axis_rx_tlast ) +// ); + +// ila_ms debug_saxis ( +// .clk ( user_clk ), +// .probe0 ( s_axis_tx_tdata ), +// .probe1 ( s_axis_tx_tkeep ), +// .probe2 ( s_axis_tx_tvalid ), +// .probe3 ( s_axis_tx_tready ), +// .probe4 ( s_axis_tx_tlast ) +// ); + +// ila_hc debug_c2h ( +// .clk ( user_clk ), +// .probe0 ( softmc_c2h_tdata ), +// .probe1 ( softmc_c2h_tkeep ), +// .probe2 ( softmc_c2h_tvalid ), +// .probe3 ( softmc_c2h_tready ), +// .probe4 ( softmc_c2h_tlast ) +// ); + +// ila_hc debug_h2c ( +// .clk ( user_clk ), +// .probe0 ( softmc_h2c_tdata ), +// .probe1 ( softmc_h2c_tkeep ), +// .probe2 ( softmc_h2c_tvalid ), +// .probe3 ( softmc_h2c_tready ), +// .probe4 ( softmc_h2c_tlast ) +// ); + +endmodule \ No newline at end of file diff --git a/projects/ZC706/verilog/pcie_txn_buffer.v b/projects/ZC706/verilog/pcie_txn_buffer.v new file mode 100644 index 0000000..ad9ebb0 --- /dev/null +++ b/projects/ZC706/verilog/pcie_txn_buffer.v @@ -0,0 +1,249 @@ +`timescale 1ns / 1ps + +module pcie_txn_buffer #( + parameter C_IN_DATA_WIDTH = 256, + parameter C_OUT_DATA_WIDTH = 64, + + localparam C_IN_KEEP = C_IN_DATA_WIDTH / 8, + localparam C_OUT_KEEP = C_OUT_DATA_WIDTH / 8, + localparam FIFO_DEPTH = 1024, + localparam C_IO_WIDTH_RATIO = C_IN_DATA_WIDTH / C_OUT_DATA_WIDTH, + localparam DATA_COUNT_WIDTH = $clog2(FIFO_DEPTH * C_IO_WIDTH_RATIO) + 1, + localparam C_RATIO_WIDTH = C_IO_WIDTH_RATIO, + localparam C_HALF_RATIO_WIDTH = 2 * C_IO_WIDTH_RATIO +)( + input clk, + input reset, + + input [C_IN_DATA_WIDTH-1:0] s_axis_tdata, + input [C_IN_KEEP-1:0] s_axis_tkeep, + input s_axis_tvalid, + output s_axis_tready, + input s_axis_tlast, + + output [C_OUT_DATA_WIDTH-1:0] m_axis_tdata, + output [C_OUT_DATA_WIDTH/2-1:0] m_axis_upper_half_data, + output [C_OUT_KEEP-1:0] m_axis_tkeep, + output [C_OUT_KEEP/2-1:0] m_axis_upper_half_keep, + output m_axis_tvalid, + output m_axis_upper_half_valid, + input m_axis_tready, + input m_axis_upper_half_ready, + + output [DATA_COUNT_WIDTH-1:0] data_count, + output programmed_stop +); + +// Combinational Outputs +reg [C_OUT_DATA_WIDTH-1:0] m_axis_tdata_r; +reg [C_OUT_KEEP-1:0] m_axis_tkeep_r; +reg m_axis_tvalid_r; +reg m_axis_upper_half_valid_r; + +reg user_stop_flag_r; +reg user_stop_flag_ns; + +// Fall Through Registers +reg [C_IN_DATA_WIDTH-1:0] ft_data_r; +reg [C_IN_KEEP-1:0] ft_keep_r; +reg [C_HALF_RATIO_WIDTH-1:0] ft_valid_r; +reg [DATA_COUNT_WIDTH-1:0] ft_half_data_count_r; + +reg [C_IN_DATA_WIDTH-1:0] ft_data_ns; +reg [C_IN_KEEP-1:0] ft_keep_ns; +reg [C_HALF_RATIO_WIDTH-1:0] ft_valid_ns; +reg [DATA_COUNT_WIDTH-1:0] ft_half_data_count_ns; + +wire [C_IN_DATA_WIDTH-1:0] fifo_tdata; +wire [C_IN_KEEP-1:0] fifo_tkeep; +wire fifo_tvalid; +reg fifo_tready_r; +wire [9:0] fifo_data_count; + +generate + if (C_IN_DATA_WIDTH == C_OUT_DATA_WIDTH) begin + always @(*) begin + ft_half_data_count_ns = ft_half_data_count_r; + fifo_tready_r = 0; + user_stop_flag_ns = (user_stop_flag_r || s_axis_tlast) && !s_axis_tvalid; + ft_data_ns = ft_data_r; + ft_keep_ns = ft_keep_r; + ft_valid_ns = ft_valid_r; + m_axis_tdata_r = ft_data_r[C_IN_DATA_WIDTH-1 -: C_OUT_DATA_WIDTH]; + m_axis_tkeep_r = ft_keep_r[C_IN_KEEP-1 -: C_OUT_KEEP]; + m_axis_tvalid_r = (ft_valid_r[C_HALF_RATIO_WIDTH-2] || fifo_tvalid) && ft_valid_r[C_HALF_RATIO_WIDTH-1]; + m_axis_upper_half_valid_r = ft_valid_r[C_HALF_RATIO_WIDTH-1]; + if (!ft_valid_r[C_HALF_RATIO_WIDTH-1] && fifo_tvalid) begin + fifo_tready_r = 1; + m_axis_tdata_r = fifo_tdata; + m_axis_tkeep_r = fifo_tkeep; + m_axis_tvalid_r = 1; + m_axis_upper_half_valid_r = 1; + if (m_axis_tready) begin + ft_data_ns = fifo_tdata << C_OUT_DATA_WIDTH; + ft_keep_ns = fifo_tkeep << C_OUT_KEEP; + ft_valid_ns = {C_HALF_RATIO_WIDTH{1'b1}} << 2; + ft_half_data_count_ns = C_HALF_RATIO_WIDTH - 2; + end + else if (m_axis_upper_half_ready) begin + ft_data_ns = fifo_tdata << (C_OUT_DATA_WIDTH / 2); + ft_keep_ns = fifo_tkeep << (C_OUT_KEEP / 2); + ft_valid_ns = {C_HALF_RATIO_WIDTH{1'b1}} << 1; + ft_half_data_count_ns = C_HALF_RATIO_WIDTH - 1; + end + else begin + ft_data_ns = fifo_tdata; + ft_keep_ns = fifo_tkeep; + ft_valid_ns = {C_HALF_RATIO_WIDTH{1'b1}}; + ft_half_data_count_ns = C_HALF_RATIO_WIDTH; + end + end + else if (!ft_valid_r[C_HALF_RATIO_WIDTH-2] && fifo_tvalid) begin + m_axis_tdata_r = {ft_data_r[C_IN_DATA_WIDTH-1 -: C_OUT_DATA_WIDTH/2], fifo_tdata[C_IN_DATA_WIDTH-1 -: C_OUT_DATA_WIDTH/2]}; + m_axis_tkeep_r = {ft_keep_r[C_IN_KEEP-1 -: C_OUT_KEEP/2], fifo_tkeep[C_IN_KEEP-1 -: C_OUT_KEEP/2]}; + if (m_axis_tready) begin + fifo_tready_r = 1; + ft_data_ns = fifo_tdata << (C_OUT_DATA_WIDTH / 2); + ft_keep_ns = fifo_tkeep << (C_OUT_KEEP / 2); + ft_valid_ns = {C_HALF_RATIO_WIDTH{1'b1}} << 1; + ft_half_data_count_ns = C_HALF_RATIO_WIDTH - 1; + end + else if (m_axis_upper_half_ready) begin + fifo_tready_r = 1; + ft_data_ns = fifo_tdata; + ft_keep_ns = fifo_tkeep; + ft_valid_ns = {C_HALF_RATIO_WIDTH{1'b1}}; + ft_half_data_count_ns = C_HALF_RATIO_WIDTH; + end + end + else if (m_axis_tready) begin + fifo_tready_r = 1; + ft_data_ns = fifo_tdata; + ft_keep_ns = fifo_tkeep; + ft_valid_ns = {C_HALF_RATIO_WIDTH{1'b1}}; + ft_half_data_count_ns = C_HALF_RATIO_WIDTH; + end + else if (m_axis_upper_half_ready) begin + ft_data_ns = ft_data_r << (C_OUT_DATA_WIDTH / 2); + ft_keep_ns = ft_keep_r << (C_OUT_KEEP / 2); + ft_valid_ns = ft_valid_r << 1; + ft_half_data_count_ns = C_HALF_RATIO_WIDTH - 1; + end + end + end + else begin + always @(*) begin + ft_half_data_count_ns = ft_half_data_count_r; + fifo_tready_r = 0; + user_stop_flag_ns = (user_stop_flag_r || s_axis_tlast) && !s_axis_tvalid; + ft_data_ns = ft_data_r; + ft_keep_ns = ft_keep_r; + ft_valid_ns = ft_valid_r; + m_axis_tdata_r = ft_data_r[C_IN_DATA_WIDTH-1 -: C_OUT_DATA_WIDTH]; + m_axis_tkeep_r = ft_keep_r[C_IN_KEEP-1 -: C_OUT_KEEP]; + m_axis_tvalid_r = (ft_valid_r[C_HALF_RATIO_WIDTH-2] || fifo_tvalid) && ft_valid_r[C_HALF_RATIO_WIDTH-1]; + m_axis_upper_half_valid_r = ft_valid_r[C_HALF_RATIO_WIDTH-1]; + if (!ft_valid_r[C_HALF_RATIO_WIDTH-1] && fifo_tvalid) begin + fifo_tready_r = 1; + m_axis_tdata_r = fifo_tdata; + m_axis_tkeep_r = fifo_tkeep; + m_axis_tvalid_r = 1; + m_axis_upper_half_valid_r = 1; + if (m_axis_tready) begin + ft_data_ns = fifo_tdata << C_OUT_DATA_WIDTH; + ft_keep_ns = fifo_tkeep << C_OUT_KEEP; + ft_valid_ns = {C_HALF_RATIO_WIDTH{1'b1}} << 2; + ft_half_data_count_ns = C_HALF_RATIO_WIDTH - 2; + end + else if (m_axis_upper_half_ready) begin + ft_data_ns = fifo_tdata << (C_OUT_DATA_WIDTH / 2); + ft_keep_ns = fifo_tkeep << (C_OUT_KEEP / 2); + ft_valid_ns = {C_HALF_RATIO_WIDTH{1'b1}} << 1; + ft_half_data_count_ns = C_HALF_RATIO_WIDTH - 1; + end + else begin + ft_data_ns = fifo_tdata; + ft_keep_ns = fifo_tkeep; + ft_valid_ns = {C_HALF_RATIO_WIDTH{1'b1}}; + ft_half_data_count_ns = C_HALF_RATIO_WIDTH; + end + end + else if (!ft_valid_r[C_HALF_RATIO_WIDTH-2] && fifo_tvalid) begin + m_axis_tdata_r = {ft_data_r[C_IN_DATA_WIDTH-1 -: C_OUT_DATA_WIDTH/2], fifo_tdata[C_IN_DATA_WIDTH-1 -: C_OUT_DATA_WIDTH/2]}; + m_axis_tkeep_r = {ft_keep_r[C_IN_KEEP-1 -: C_OUT_KEEP/2], fifo_tkeep[C_IN_KEEP-1 -: C_OUT_KEEP/2]}; + if (m_axis_tready) begin + fifo_tready_r = 1; + ft_data_ns = fifo_tdata << (C_OUT_DATA_WIDTH / 2); + ft_keep_ns = fifo_tkeep << (C_OUT_KEEP / 2); + ft_valid_ns = {C_HALF_RATIO_WIDTH{1'b1}} << 1; + ft_half_data_count_ns = C_HALF_RATIO_WIDTH - 1; + end + else if (m_axis_upper_half_ready) begin + fifo_tready_r = 1; + ft_data_ns = fifo_tdata; + ft_keep_ns = fifo_tkeep; + ft_valid_ns = {C_HALF_RATIO_WIDTH{1'b1}}; + ft_half_data_count_ns = C_HALF_RATIO_WIDTH; + end + end + else if (m_axis_tready && m_axis_tvalid_r) begin + ft_data_ns = ft_data_r << C_OUT_DATA_WIDTH; + ft_keep_ns = ft_keep_r << C_OUT_KEEP; + ft_valid_ns = ft_valid_r << 2; + ft_half_data_count_ns = ft_half_data_count_r - 2; + end + else if (m_axis_upper_half_ready && m_axis_upper_half_valid_r) begin + ft_data_ns = ft_data_r << (C_OUT_DATA_WIDTH / 2); + ft_keep_ns = ft_keep_r << (C_OUT_KEEP / 2); + ft_valid_ns = ft_valid_r << 1; + ft_half_data_count_ns = ft_half_data_count_r - 1; + end + end + end +endgenerate + +always @(posedge clk) begin + if (reset) begin + ft_data_r <= 0; + ft_keep_r <= 0; + ft_valid_r <= 0; + user_stop_flag_r <= 0; + ft_half_data_count_r <= 0; + end + else begin + ft_data_r <= ft_data_ns; + ft_keep_r <= ft_keep_ns; + ft_valid_r <= ft_valid_ns; + user_stop_flag_r <= user_stop_flag_ns; + ft_half_data_count_r <= ft_half_data_count_ns; + end +end + +assign data_count = (fifo_data_count > 0 ? fifo_data_count * C_IO_WIDTH_RATIO * 2 : + fifo_tvalid ? FIFO_DEPTH * C_IO_WIDTH_RATIO * 2 : 0) + ft_half_data_count_r; + +assign programmed_stop = user_stop_flag_r && fifo_data_count == 0; +assign m_axis_tdata = m_axis_tdata_r; +assign m_axis_tkeep = m_axis_tkeep_r; +assign m_axis_tvalid = m_axis_tvalid_r; +assign m_axis_upper_half_data = m_axis_tdata_r[C_OUT_DATA_WIDTH/2 +: C_OUT_DATA_WIDTH/2]; +assign m_axis_upper_half_keep = m_axis_tkeep_r[C_OUT_KEEP/2 +: C_OUT_KEEP/2]; +assign m_axis_upper_half_valid = m_axis_upper_half_valid_r; + +data_fifo pcie_buffer ( + .wr_rst_busy( ), // output wire wr_rst_busy + .rd_rst_busy( ), // output wire rd_rst_busy + .s_aclk(clk), // input wire s_aclk + .s_aresetn(~reset), // input wire s_aresetn + .s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid + .s_axis_tready(s_axis_tready), // output wire s_axis_tready + .s_axis_tdata(s_axis_tdata), // input wire [127 : 0] s_axis_tdata + .s_axis_tkeep(s_axis_tkeep), // input wire [15 : 0] s_axis_tkeep + .m_axis_tvalid(fifo_tvalid), // output wire m_axis_tvalid + .m_axis_tready(fifo_tready_r), // input wire m_axis_tready + .m_axis_tdata(fifo_tdata), // output wire [127 : 0] m_axis_tdata + .m_axis_tkeep(fifo_tkeep), // output wire [15 : 0] m_axis_tkeep + .axis_data_count(fifo_data_count) +); + +endmodule \ No newline at end of file diff --git a/projects/ZC706/verilog/phy/memctl_mig.v b/projects/ZC706/verilog/phy/memctl_mig.v new file mode 100644 index 0000000..7c199a3 --- /dev/null +++ b/projects/ZC706/verilog/phy/memctl_mig.v @@ -0,0 +1,1015 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 4.0 +// \ \ Application : MIG +// / / Filename : memctl_mig.v +// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ +// \ \ / \ Date Created : Tue Sept 21 2010 +// \___\/\___\ +// +// Device : 7 Series +// Design Name : DDR3 SDRAM +// Purpose : +// Top-level module. This module can be instantiated in the +// system and interconnect as shown in user design wrapper file (user top module). +// In addition to the memory controller, the module instantiates: +// 1. Clock generation/distribution, reset logic +// 2. IDELAY control block +// 3. Debug logic +// Reference : +// Revision History : +//***************************************************************************** + +//`define SKIP_CALIB +`timescale 1ps/1ps + +module memctl_mig # + ( + + //*************************************************************************** + // The following parameters refer to width of various ports + //*************************************************************************** + parameter BANK_WIDTH = 3, + // # of memory Bank Address bits. + parameter CK_WIDTH = 1, + // # of CK/CK# outputs to memory. + parameter COL_WIDTH = 10, + // # of memory Column Address bits. + parameter CS_WIDTH = 1, + // # of unique CS outputs to memory. + parameter nCS_PER_RANK = 1, + // # of unique CS outputs per rank for phy + parameter CKE_WIDTH = 1, + // # of CKE outputs to memory. + parameter DATA_BUF_ADDR_WIDTH = 5, + parameter DQ_CNT_WIDTH = 6, + // = ceil(log2(DQ_WIDTH)) + parameter DQ_PER_DM = 8, + parameter DM_WIDTH = 8, + // # of DM (data mask) + parameter DQ_WIDTH = 64, + // # of DQ (data) + parameter DQS_WIDTH = 8, + parameter DQS_CNT_WIDTH = 3, + // = ceil(log2(DQS_WIDTH)) + parameter DRAM_WIDTH = 8, + // # of DQ per DQS + parameter ECC = "OFF", + parameter DATA_WIDTH = 64, + parameter ECC_TEST = "OFF", + parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH, + parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN", + //Possible Parameters + //1.BANK_ROW_COLUMN : Address mapping is + // in form of Bank Row Column. + //2.ROW_BANK_COLUMN : Address mapping is + // in the form of Row Bank Column. + //3.TG_TEST : Scrambles Address bits + // for distributed Addressing. + + parameter nBANK_MACHS = 4, + parameter RANKS = 1, + // # of Ranks. + parameter ODT_WIDTH = 1, + // # of ODT outputs to memory. + parameter ROW_WIDTH = 14, + // # of memory Row Address bits. + parameter ADDR_WIDTH = 28, + // # = RANK_WIDTH + BANK_WIDTH + // + ROW_WIDTH + COL_WIDTH; + // Chip Select is always tied to low for + // single rank devices + parameter USE_CS_PORT = 1, + // # = 1, When Chip Select (CS#) output is enabled + // = 0, When Chip Select (CS#) output is disabled + // If CS_N disabled, user must connect + // DRAM CS_N input(s) to ground + parameter USE_DM_PORT = 1, + // # = 1, When Data Mask option is enabled + // = 0, When Data Mask option is disbaled + // When Data Mask option is disabled in + // MIG Controller Options page, the logic + // related to Data Mask should not get + // synthesized + parameter USE_ODT_PORT = 1, + // # = 1, When ODT output is enabled + // = 0, When ODT output is disabled + // Parameter configuration for Dynamic ODT support: + // USE_ODT_PORT = 0, RTT_NOM = "DISABLED", RTT_WR = "60/120". + // This configuration allows to save ODT pin mapping from FPGA. + // The user can tie the ODT input of DRAM to HIGH. + parameter IS_CLK_SHARED = "FALSE", + // # = "true" when clock is shared + // = "false" when clock is not shared + + parameter PHY_CONTROL_MASTER_BANK = 1, + // The bank index where master PHY_CONTROL resides, + // equal to the PLL residing bank + parameter MEM_DENSITY = "1Gb", + // Indicates the density of the Memory part + // Added for the sake of Vivado simulations + parameter MEM_SPEEDGRADE = "125", + // Indicates the Speed grade of Memory Part + // Added for the sake of Vivado simulations + parameter MEM_DEVICE_WIDTH = 8, + // Indicates the device width of the Memory Part + // Added for the sake of Vivado simulations + + //*************************************************************************** + // The following parameters are mode register settings + //*************************************************************************** + parameter AL = "0", + // DDR3 SDRAM: + // Additive Latency (Mode Register 1). + // # = "0", "CL-1", "CL-2". + // DDR2 SDRAM: + // Additive Latency (Extended Mode Register). + parameter nAL = 0, + // # Additive Latency in number of clock + // cycles. + parameter BURST_MODE = "8", + // DDR3 SDRAM: + // Burst Length (Mode Register 0). + // # = "8", "4", "OTF". + // DDR2 SDRAM: + // Burst Length (Mode Register). + // # = "8", "4". + parameter BURST_TYPE = "SEQ", + // DDR3 SDRAM: Burst Type (Mode Register 0). + // DDR2 SDRAM: Burst Type (Mode Register). + // # = "SEQ" - (Sequential), + // = "INT" - (Interleaved). + parameter CL = 6, + // in number of clock cycles + // DDR3 SDRAM: CAS Latency (Mode Register 0). + // DDR2 SDRAM: CAS Latency (Mode Register). + parameter CWL = 5, + // in number of clock cycles + // DDR3 SDRAM: CAS Write Latency (Mode Register 2). + // DDR2 SDRAM: Can be ignored + parameter OUTPUT_DRV = "HIGH", + // Output Driver Impedance Control (Mode Register 1). + // # = "HIGH" - RZQ/7, + // = "LOW" - RZQ/6. + parameter RTT_NOM = "60", + // RTT_NOM (ODT) (Mode Register 1). + // = "120" - RZQ/2, + // = "60" - RZQ/4, + // = "40" - RZQ/6. + parameter RTT_WR = "OFF", + // RTT_WR (ODT) (Mode Register 2). + // # = "OFF" - Dynamic ODT off, + // = "120" - RZQ/2, + // = "60" - RZQ/4, + parameter ADDR_CMD_MODE = "1T" , + // # = "1T", "2T". + parameter REG_CTRL = "OFF", + // # = "ON" - RDIMMs, + // = "OFF" - Components, SODIMMs, UDIMMs. + parameter CA_MIRROR = "OFF", + // C/A mirror opt for DDR3 dual rank + + parameter VDD_OP_VOLT = "150", + // # = "150" - 1.5V Vdd Memory part + // = "135" - 1.35V Vdd Memory part + + + //*************************************************************************** + // The following parameters are multiplier and divisor factors for PLLE2. + // Based on the selected design frequency these parameters vary. + //*************************************************************************** + parameter CLKIN_PERIOD = 5000, + // Input Clock Period + parameter CLKFBOUT_MULT = 4, + // write PLL VCO multiplier + parameter DIVCLK_DIVIDE = 1, + // write PLL VCO divisor + parameter CLKOUT0_PHASE = 337.5, + // Phase for PLL output clock (CLKOUT0) + parameter CLKOUT0_DIVIDE = 2, + // VCO output divisor for PLL output clock (CLKOUT0) + parameter CLKOUT1_DIVIDE = 2, + // VCO output divisor for PLL output clock (CLKOUT1) + parameter CLKOUT2_DIVIDE = 32, + // VCO output divisor for PLL output clock (CLKOUT2) + parameter CLKOUT3_DIVIDE = 8, + // VCO output divisor for PLL output clock (CLKOUT3) + parameter MMCM_VCO = 800, + // Max Freq (MHz) of MMCM VCO + parameter MMCM_MULT_F = 8, + // write MMCM VCO multiplier + parameter MMCM_DIVCLK_DIVIDE = 1, + // write MMCM VCO divisor + + //*************************************************************************** + // Memory Timing Parameters. These parameters varies based on the selected + // memory part. + //*************************************************************************** + parameter tCKE = 5000, + // memory tCKE paramter in pS + parameter tFAW = 30000, + // memory tRAW paramter in pS. + parameter tPRDI = 1_000_000, + // memory tPRDI paramter in pS. + parameter tRAS = 35000, + // memory tRAS paramter in pS. + parameter tRCD = 13750, + // memory tRCD paramter in pS. + parameter tREFI = 7800000, + // memory tREFI paramter in pS. + parameter tRFC = 110000, + // memory tRFC paramter in pS. + parameter tRP = 13750, + // memory tRP paramter in pS. + parameter tRRD = 6000, + // memory tRRD paramter in pS. + parameter tRTP = 7500, + // memory tRTP paramter in pS. + parameter tWTR = 7500, + // memory tWTR paramter in pS. + parameter tZQI = 128_000_000, + // memory tZQI paramter in nS. + parameter tZQCS = 64,//64, + // memory tZQCS paramter in clock cycles. + + //*************************************************************************** + // Simulation parameters + //*************************************************************************** + parameter SIM_BYPASS_INIT_CAL = "OFF", + // # = "OFF" - Complete memory init & + // calibration sequence + // # = "SKIP" - Not supported + // # = "FAST" - Complete memory init & use + // abbreviated calib sequence + + parameter SIMULATION = "FALSE", + // Should be TRUE during design simulations and + // FALSE during implementations + + //*************************************************************************** + // The following parameters varies based on the pin out entered in MIG GUI. + // Do not change any of these parameters directly by editing the RTL. + // Any changes required should be done through GUI and the design regenerated. + //*************************************************************************** + parameter BYTE_LANES_B0 = 4'b0111, + // Byte lanes used in an IO column. + parameter BYTE_LANES_B1 = 4'b1111, + // Byte lanes used in an IO column. + parameter BYTE_LANES_B2 = 4'b1111, + // Byte lanes used in an IO column. + parameter BYTE_LANES_B3 = 4'b0000, + // Byte lanes used in an IO column. + parameter BYTE_LANES_B4 = 4'b0000, + // Byte lanes used in an IO column. + parameter DATA_CTL_B0 = 4'b0111, + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + parameter DATA_CTL_B1 = 4'b0001, + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + parameter DATA_CTL_B2 = 4'b1111, + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + parameter DATA_CTL_B3 = 4'b0000, + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + parameter DATA_CTL_B4 = 4'b0000, + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + parameter PHY_0_BITLANES = 48'h000_1FF_3FE_2FF, + parameter PHY_1_BITLANES = 48'h7D4_BF0_8FF_2FF, + parameter PHY_2_BITLANES = 48'h3FE_1FF_1FF_2FF, + + // control/address/data pin mapping parameters + parameter CK_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_12, + parameter ADDR_MAP + = 192'h000_000_138_12B_134_112_11B_139_116_117_132_126_136_127_137_125, + parameter BANK_MAP = 36'h13A_111_115, + parameter CAS_MAP = 12'h113, + parameter CKE_ODT_BYTE_MAP = 8'h00, + parameter CKE_MAP = 96'h000_000_000_000_000_000_000_124, + parameter ODT_MAP = 96'h000_000_000_000_000_000_000_110, + parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_129, + parameter PARITY_MAP = 12'h000, + parameter RAS_MAP = 12'h128, + parameter WE_MAP = 12'h114, + parameter DQS_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_01_02_10_20_21_22_23, + parameter DATA0_MAP = 96'h231_232_235_236_239_233_234_237, + parameter DATA1_MAP = 96'h220_221_225_224_222_227_223_226, + parameter DATA2_MAP = 96'h214_210_216_217_218_215_213_212, + parameter DATA3_MAP = 96'h209_204_202_201_207_206_203_200, + parameter DATA4_MAP = 96'h109_107_103_105_106_100_102_104, + parameter DATA5_MAP = 96'h023_022_024_027_028_025_021_020, + parameter DATA6_MAP = 96'h011_016_012_013_019_015_018_017, + parameter DATA7_MAP = 96'h003_009_004_001_002_000_007_006, + parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, + parameter MASK0_MAP = 108'h000_005_014_026_101_205_211_228_238, + parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, + + parameter SLOT_0_CONFIG = 8'b0000_0001, + // Mapping of Ranks. + parameter SLOT_1_CONFIG = 8'b0000_0000, + // Mapping of Ranks. + + //*************************************************************************** + // IODELAY and PHY related parameters + //*************************************************************************** + parameter IBUF_LPWR_MODE = "OFF", + // to phy_top + parameter DATA_IO_IDLE_PWRDWN = "ON", + // # = "ON", "OFF" + parameter BANK_TYPE = "HP_IO", + // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" + parameter DATA_IO_PRIM_TYPE = "HP_LP", + // # = "HP_LP", "HR_LP", "DEFAULT" + parameter CKE_ODT_AUX = "FALSE", + parameter USER_REFRESH = "OFF", + parameter WRLVL = "ON", + // # = "ON" - DDR3 SDRAM + // = "OFF" - DDR2 SDRAM. + parameter ORDERING = "NORM", + // # = "NORM", "STRICT", "RELAXED". + parameter CALIB_ROW_ADD = 16'h0000, + // Calibration row address will be used for + // calibration read and write operations + parameter CALIB_COL_ADD = 12'h000, + // Calibration column address will be used for + // calibration read and write operations + parameter CALIB_BA_ADD = 3'h0, + // Calibration bank address will be used for + // calibration read and write operations + parameter TCQ = 100, + parameter IDELAY_ADJ = "OFF", + parameter FINE_PER_BIT = "OFF", + parameter CENTER_COMP_MODE = "OFF", + parameter PI_VAL_ADJ = "OFF", + parameter IODELAY_GRP0 = "MEMCTL_IODELAY_MIG0", + // It is associated to a set of IODELAYs with + // an IDELAYCTRL that have same IODELAY CONTROLLER + // clock frequency (200MHz). + parameter IODELAY_GRP1 = "MEMCTL_IODELAY_MIG1", + // It is associated to a set of IODELAYs with + // an IDELAYCTRL that have same IODELAY CONTROLLER + // clock frequency (300MHz/400MHz). + parameter SYSCLK_TYPE = "DIFFERENTIAL", + // System clock type DIFFERENTIAL, SINGLE_ENDED, + // NO_BUFFER + parameter REFCLK_TYPE = "USE_SYSTEM_CLOCK", + // Reference clock type DIFFERENTIAL, SINGLE_ENDED, + // NO_BUFFER, USE_SYSTEM_CLOCK + parameter SYS_RST_PORT = "TRUE", + // "TRUE" - if pin is selected for sys_rst + // and IBUF will be instantiated. + // "FALSE" - if pin is not selected for sys_rst + parameter FPGA_SPEED_GRADE = 2, + // FPGA speed grade + + parameter CMD_PIPE_PLUS1 = "ON", + // add pipeline stage between MC and PHY + parameter DRAM_TYPE = "DDR3", + parameter CAL_WIDTH = "HALF", + parameter STARVE_LIMIT = 2, + // # = 2,3,4. + parameter REF_CLK_MMCM_IODELAY_CTRL = "FALSE", + + + //*************************************************************************** + // Referece clock frequency parameters + //*************************************************************************** + parameter REFCLK_FREQ = 200.0, + // IODELAYCTRL reference clock frequency + parameter DIFF_TERM_REFCLK = "TRUE", + // Differential Termination for idelay + // reference clock input pins + //*************************************************************************** + // System clock frequency parameters + //*************************************************************************** + parameter tCK = 2500, + // memory tCK paramter. + // # = Clock Period in pS. + parameter nCK_PER_CLK = 4, + // # of memory CKs per fabric CLK + + parameter DIFF_TERM_SYSCLK = "FALSE", + // Differential Termination for System + // clock input pins + + + + + //*************************************************************************** + // Debug parameters + //*************************************************************************** + parameter DEBUG_PORT = "OFF", + // # = "ON" Enable debug signals/controls. + // = "OFF" Disable debug signals/controls. + + //*************************************************************************** + // Temparature monitor parameter + //*************************************************************************** + parameter TEMP_MON_CONTROL = "INTERNAL", + // # = "INTERNAL", "EXTERNAL" + //*************************************************************************** + // FPGA Voltage Type parameter + //*************************************************************************** + parameter FPGA_VOLT_TYPE = "N", + // # = "L", "N". When FPGA VccINT is 0.9v, + // the value is "L", else it is "N" + + parameter RST_ACT_LOW = 0 + // =1 for active low reset, + // =0 for active high. + ) + ( + // DDR Interface + inout [DQ_WIDTH-1:0] ddr3_dq, + inout [DQS_WIDTH-1:0] ddr3_dqs_n, + inout [DQS_WIDTH-1:0] ddr3_dqs_p, + output [ROW_WIDTH-1:0] ddr3_addr, + output [BANK_WIDTH-1:0] ddr3_ba, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + output ddr3_reset_n, + output [CK_WIDTH-1:0] ddr3_ck_p, + output [CK_WIDTH-1:0] ddr3_ck_n, + output [CKE_WIDTH-1:0] ddr3_cke, + output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n, + output [DM_WIDTH-1:0] ddr3_dm, + output [ODT_WIDTH-1:0] ddr3_odt, + + // MC <-> PHY Interface + input [nCK_PER_CLK-1:0] mc_ras_n, + input [nCK_PER_CLK-1:0] mc_cas_n, + input [nCK_PER_CLK-1:0] mc_we_n, + input [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, + input [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, + input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, + input mc_reset_n, + input [1:0] mc_odt, + input [nCK_PER_CLK-1:0] mc_cke, + // AUX - For ODT and CKE assertion during reads and writes + input [3:0] mc_aux_out0, + input [3:0] mc_aux_out1, + input mc_cmd_wren, + input mc_ctl_wren, + input [2:0] mc_cmd, + input [1:0] mc_cas_slot, + input [5:0] mc_data_offset, + input [5:0] mc_data_offset_1, + input [5:0] mc_data_offset_2, + input [1:0] mc_rank_cnt, + // Write + input mc_wrdata_en, + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata, + input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mc_wrdata_mask, + input idle, + output phy_mc_ctl_full, + output phy_mc_cmd_full, + output phy_mc_data_full, + output [6*RANKS-1:0] calib_rd_data_offset_0, + output [6*RANKS-1:0] calib_rd_data_offset_1, + output [6*RANKS-1:0] calib_rd_data_offset_2, + output phy_rddata_valid, + output [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data, + + // Differential system clocks + input sys_clk_p, + input sys_clk_n, + + output ui_clk, + output ui_clk_sync_rst, + + output init_calib_complete, + + // System reset - Default polarity of sys_rst pin is Active Low. + // System reset polarity will change based on the option + // selected in GUI. + input sys_rst + ); + + function integer clogb2 (input integer size); + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + + localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS); + localparam RANK_WIDTH = clogb2(RANKS); + + localparam ECC_WIDTH = (ECC == "OFF")? + 0 : (DATA_WIDTH <= 4)? + 4 : (DATA_WIDTH <= 10)? + 5 : (DATA_WIDTH <= 26)? + 6 : (DATA_WIDTH <= 57)? + 7 : (DATA_WIDTH <= 120)? + 8 : (DATA_WIDTH <= 247)? + 9 : 10; + localparam DATA_BUF_OFFSET_WIDTH = 1; + localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH) + + BANK_WIDTH + ROW_WIDTH + COL_WIDTH + + DATA_BUF_OFFSET_WIDTH; + + localparam TEMP_MON_EN = (SIMULATION == "FALSE") ? "ON" : "OFF"; + // Enable or disable the temp monitor module + localparam tTEMPSAMPLE = 10000000; // sample every 10 us + localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock + `ifdef SKIP_CALIB + localparam SKIP_CALIB = "TRUE"; + `else + localparam SKIP_CALIB = "FALSE"; + `endif + + + localparam TAPSPERKCLK = (56*MMCM_MULT_F)/nCK_PER_CLK; + + + // Wire declarations + + wire [BM_CNT_WIDTH-1:0] bank_mach_next; + wire clk; + wire [1:0] clk_ref; + wire [1:0] iodelay_ctrl_rdy; + wire clk_ref_in; + wire sys_rst_o; + wire clk_div2; + wire rst_div2; + wire freq_refclk ; + wire mem_refclk ; + wire pll_lock ; + wire sync_pulse; + wire mmcm_ps_clk; + wire poc_sample_pd; + wire psen; + wire psincdec; + wire psdone; + wire iddr_rst; + wire ref_dll_lock; + wire rst_phaser_ref; + wire pll_locked; + + wire rst; + + wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err; + wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err; + wire ddr3_parity; + + + wire sys_clk_i; + wire mmcm_clk; + wire clk_ref_p; + wire clk_ref_n; + wire clk_ref_i; + wire [11:0] device_temp_i; + wire [11:0] device_temp; + + + +//*************************************************************************** + + assign ui_clk = clk; + assign ui_clk_sync_rst = rst; + + assign sys_clk_i = 1'b0; + assign clk_ref_i = 1'b0; + + + generate + if (REFCLK_TYPE == "USE_SYSTEM_CLOCK") + assign clk_ref_in = mmcm_clk; + else + assign clk_ref_in = clk_ref_i; + endgenerate + + mig_7series_v4_0_iodelay_ctrl # + ( + .TCQ (TCQ), + .IODELAY_GRP0 (IODELAY_GRP0), + .IODELAY_GRP1 (IODELAY_GRP1), + .REFCLK_TYPE (REFCLK_TYPE), + .SYSCLK_TYPE (SYSCLK_TYPE), + .SYS_RST_PORT (SYS_RST_PORT), + .RST_ACT_LOW (RST_ACT_LOW), + .DIFF_TERM_REFCLK (DIFF_TERM_REFCLK), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .REF_CLK_MMCM_IODELAY_CTRL (REF_CLK_MMCM_IODELAY_CTRL) + ) + u_iodelay_ctrl + ( + // Outputs + .iodelay_ctrl_rdy (iodelay_ctrl_rdy), + .sys_rst_o (sys_rst_o), + .clk_ref (clk_ref), + // Inputs + .clk_ref_p (clk_ref_p), + .clk_ref_n (clk_ref_n), + .clk_ref_i (clk_ref_in), + .sys_rst (sys_rst) + ); + mig_7series_v4_0_clk_ibuf # + ( + .SYSCLK_TYPE (SYSCLK_TYPE), + .DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK) + ) + u_ddr3_clk_ibuf + ( + .sys_clk_p (sys_clk_p), + .sys_clk_n (sys_clk_n), + .sys_clk_i (sys_clk_i), + .mmcm_clk (mmcm_clk) + ); + // Temperature monitoring logic + + generate + if (TEMP_MON_EN == "ON") begin: temp_mon_enabled + + mig_7series_v4_0_tempmon # + ( + .TCQ (TCQ), + .TEMP_MON_CONTROL (TEMP_MON_CONTROL), + .XADC_CLK_PERIOD (XADC_CLK_PERIOD), + .tTEMPSAMPLE (tTEMPSAMPLE) + ) + u_tempmon + ( + .clk (clk), + .xadc_clk (clk_ref[0]), + .rst (rst), + .device_temp_i (device_temp_i), + .device_temp (device_temp) + ); + end else begin: temp_mon_disabled + + assign device_temp = 'b0; + + end + endgenerate + + mig_7series_v4_0_infrastructure # + ( + //.SIMULATION (SIMULATION), + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .CLKIN_PERIOD (CLKIN_PERIOD), + .SYSCLK_TYPE (SYSCLK_TYPE), + .CLKFBOUT_MULT (CLKFBOUT_MULT), + .DIVCLK_DIVIDE (DIVCLK_DIVIDE), + .CLKOUT0_PHASE (CLKOUT0_PHASE), + .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), + .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), + .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), + .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), + .MMCM_VCO (MMCM_VCO), + .MMCM_MULT_F (MMCM_MULT_F), + .MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), + .RST_ACT_LOW (RST_ACT_LOW), + .tCK (tCK), + .MEM_TYPE (DRAM_TYPE) + ) + u_ddr3_infrastructure + ( + // Outputs + .rstdiv0 (rst), + .clk (clk), + .clk_div2 (clk_div2), + .rst_div2 (rst_div2), + .mem_refclk (mem_refclk), + .freq_refclk (freq_refclk), + .sync_pulse (sync_pulse), + .mmcm_ps_clk (mmcm_ps_clk), + .poc_sample_pd (poc_sample_pd), + .psdone (psdone), + .iddr_rst (iddr_rst), +// .auxout_clk (), + .ui_addn_clk_0 (), + .ui_addn_clk_1 (), + .ui_addn_clk_2 (), + .ui_addn_clk_3 (), + .ui_addn_clk_4 (), + .pll_locked (pll_locked), + .mmcm_locked (), + .rst_phaser_ref (rst_phaser_ref), + // Inputs + .psen (psen), + .psincdec (psincdec), + .mmcm_clk (mmcm_clk), + .sys_rst (sys_rst_o), + .iodelay_ctrl_rdy (iodelay_ctrl_rdy), + .ref_dll_lock (ref_dll_lock) + ); + + + //=================== INIT PHY WITH WRAPPER CODE ======================= + localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0); + localparam SLOT_0_CONFIG_MC = (nSLOTS == 2)? 8'b0000_0101 : 8'b0000_1111; + localparam SLOT_1_CONFIG_MC = (nSLOTS == 2)? 8'b0000_1010 : 8'b0000_0000; + + // 8*tREFI in ps is divided by fabric clock period also in ps. 270 is the number + // of fabric clock cycles that accounts for the Writes, read, and PRECHARGE time + localparam REFRESH_TIMER = (8*tREFI/(tCK*nCK_PER_CLK)) - 270; + + reg [7:0] slot_0_present_mc; + reg [7:0] slot_1_present_mc; + + reg user_periodic_rd_req = 1'b0; + reg user_ref_req = 1'b0; + reg user_zq_req = 1'b0; + + // MC/PHY interface + wire mc_ref_zq_wip; + wire tempmon_sample_en; + + wire init_calib_complete_w; + wire init_wrcal_complete_w; + wire mux_calib_complete; + wire reset = rst; + // assigning CWL = CL -1 for DDR2. DDR2 customers will not know anything + // about CWL. There is also nCWL parameter. Need to clean it up. + localparam CWL_T = (DRAM_TYPE == "DDR3") ? CWL : CL-1; + localparam PRE_REV3ES = "OFF"; + localparam DDR2_DQSN_ENABLE = "YES"; + localparam PHYCTL_CMD_FIFO = "FALSE"; + localparam IODELAY_GRP = "IODELAY_MIG"; + localparam MASTER_PHY_CTL = 0; + // following calculations should be moved inside PHY + // odt bus should be added to PHY. + localparam CLK_PERIOD = tCK * nCK_PER_CLK; + localparam nCL = CL; + localparam nCWL = CWL_T; + + assign init_wrcal_complete = init_wrcal_complete_w; + assign mux_calib_complete = (PRE_REV3ES == "OFF") ? init_calib_complete_w : + (init_calib_complete_w | init_wrcal_complete_w); + + assign init_calib_complete = mux_calib_complete; + + // Enable / disable temperature monitoring + assign tempmon_sample_en = TEMP_MON_EN == "OFF" ? 1'b0 : mc_ref_zq_wip; + + mig_7series_v4_0_ddr_phy_top # + ( + .TCQ (TCQ), + .DDR3_VDD_OP_VOLT (VDD_OP_VOLT), + .REFCLK_FREQ (REFCLK_FREQ), + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .PHY_0_BITLANES (PHY_0_BITLANES), + .PHY_1_BITLANES (PHY_1_BITLANES), + .PHY_2_BITLANES (PHY_2_BITLANES), + .CA_MIRROR (CA_MIRROR), + .CK_BYTE_MAP (CK_BYTE_MAP), + .ADDR_MAP (ADDR_MAP), + .BANK_MAP (BANK_MAP), + .CAS_MAP (CAS_MAP), + .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), + .CKE_MAP (CKE_MAP), + .ODT_MAP (ODT_MAP), + .CKE_ODT_AUX (CKE_ODT_AUX), + .CS_MAP (CS_MAP), + .PARITY_MAP (PARITY_MAP), + .RAS_MAP (RAS_MAP), + .WE_MAP (WE_MAP), + .DQS_BYTE_MAP (DQS_BYTE_MAP), + .DATA0_MAP (DATA0_MAP), + .DATA1_MAP (DATA1_MAP), + .DATA2_MAP (DATA2_MAP), + .DATA3_MAP (DATA3_MAP), + .DATA4_MAP (DATA4_MAP), + .DATA5_MAP (DATA5_MAP), + .DATA6_MAP (DATA6_MAP), + .DATA7_MAP (DATA7_MAP), + .DATA8_MAP (DATA8_MAP), + .DATA9_MAP (DATA9_MAP), + .DATA10_MAP (DATA10_MAP), + .DATA11_MAP (DATA11_MAP), + .DATA12_MAP (DATA12_MAP), + .DATA13_MAP (DATA13_MAP), + .DATA14_MAP (DATA14_MAP), + .DATA15_MAP (DATA15_MAP), + .DATA16_MAP (DATA16_MAP), + .DATA17_MAP (DATA17_MAP), + .MASK0_MAP (MASK0_MAP), + .MASK1_MAP (MASK1_MAP), + .CALIB_ROW_ADD (CALIB_ROW_ADD), + .CALIB_COL_ADD (CALIB_COL_ADD), + .CALIB_BA_ADD (CALIB_BA_ADD), + .nCS_PER_RANK (nCS_PER_RANK), + .CS_WIDTH (CS_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK), + .PRE_REV3ES (PRE_REV3ES), + .CKE_WIDTH (CKE_WIDTH), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4), + .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), + .DRAM_TYPE (DRAM_TYPE), + .BANK_WIDTH (BANK_WIDTH), + .CK_WIDTH (CK_WIDTH), + .COL_WIDTH (COL_WIDTH), + .DM_WIDTH (DM_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO), + .ROW_WIDTH (ROW_WIDTH), + .AL (AL), + .ADDR_CMD_MODE (ADDR_CMD_MODE), + .BURST_MODE (BURST_MODE), + .BURST_TYPE (BURST_TYPE), + .CL (nCL), + .CWL (nCWL), + .tRFC (tRFC), + .tREFI (tREFI), + .tCK (tCK), + .OUTPUT_DRV (OUTPUT_DRV), + .RANKS (RANKS), + .ODT_WIDTH (ODT_WIDTH), + .REG_CTRL (REG_CTRL), + .RTT_NOM (RTT_NOM), + .RTT_WR (RTT_WR), + .SLOT_1_CONFIG (SLOT_1_CONFIG), + .WRLVL (WRLVL), + .BANK_TYPE (BANK_TYPE), + .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), + .DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + // Prevent the following simulation-related parameters from + // being overridden for synthesis - for synthesis only the + // default values of these parameters should be used + // synthesis translate_off + .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL), + // synthesis translate_on + .USE_CS_PORT (USE_CS_PORT), + .USE_DM_PORT (USE_DM_PORT), + .USE_ODT_PORT (USE_ODT_PORT), + .MASTER_PHY_CTL (MASTER_PHY_CTL), + .DEBUG_PORT (DEBUG_PORT), + .IDELAY_ADJ (IDELAY_ADJ), + .FINE_PER_BIT (FINE_PER_BIT), + .CENTER_COMP_MODE (CENTER_COMP_MODE), + .PI_VAL_ADJ (PI_VAL_ADJ), + .TAPSPERKCLK (TAPSPERKCLK), + .SKIP_CALIB (SKIP_CALIB), + .FPGA_VOLT_TYPE (FPGA_VOLT_TYPE) + ) + ddr_phy_top0 + ( + // Outputs + .calib_rd_data_offset_0 (calib_rd_data_offset_0), + .calib_rd_data_offset_1 (calib_rd_data_offset_1), + .calib_rd_data_offset_2 (calib_rd_data_offset_2), + .ddr_ck (ddr3_ck_p), + .ddr_ck_n (ddr3_ck_n), + .ddr_addr (ddr3_addr), + .ddr_ba (ddr3_ba), + .ddr_ras_n (ddr3_ras_n), + .ddr_cas_n (ddr3_cas_n), + .ddr_we_n (ddr3_we_n), + .ddr_cs_n (ddr3_cs_n), + .ddr_cke (ddr3_cke), + .ddr_odt (ddr3_odt), + .ddr_reset_n (ddr3_reset_n), + .ddr_parity (ddr3_parity), + .ddr_dm (ddr3_dm), + .init_calib_complete (init_calib_complete_w), + .init_wrcal_complete (init_wrcal_complete_w), + .mc_address (mc_address), + .mc_aux_out0 (mc_aux_out0), + .mc_aux_out1 (mc_aux_out1), + .mc_bank (mc_bank), + .mc_cke (mc_cke), + .mc_odt (mc_odt), + .mc_cas_n (mc_cas_n), + .mc_cmd (mc_cmd), + .mc_cmd_wren (mc_cmd_wren), + .mc_cas_slot (mc_cas_slot), + .mc_cs_n (mc_cs_n), + .mc_ctl_wren (mc_ctl_wren), + .mc_data_offset (mc_data_offset), + .mc_data_offset_1 (mc_data_offset_1), + .mc_data_offset_2 (mc_data_offset_2), + .mc_rank_cnt (mc_rank_cnt), + .mc_ras_n (mc_ras_n), + .mc_reset_n (mc_reset_n), + .mc_we_n (mc_we_n), + .mc_wrdata (mc_wrdata), + .mc_wrdata_en (mc_wrdata_en), + .mc_wrdata_mask (mc_wrdata_mask), + .idle (idle), + .mem_refclk (mem_refclk), + .phy_mc_ctl_full (phy_mc_ctl_full), + .phy_mc_cmd_full (phy_mc_cmd_full), + .phy_mc_data_full (phy_mc_data_full), + .phy_rd_data (phy_rd_data), + .phy_rddata_valid (phy_rddata_valid), + .pll_lock (pll_locked), + .sync_pulse (sync_pulse), + // Inouts + .ddr_dqs (ddr3_dqs_p), + .ddr_dqs_n (ddr3_dqs_n), + .ddr_dq (ddr3_dq), + // Inputs + .clk_ref (tCK <= 1500 ? clk_ref[1] : clk_ref[0]), + .freq_refclk (freq_refclk), + .clk (clk), + .clk_div2 (clk_div2), + .rst_div2 (rst_div2), + .mmcm_ps_clk (mmcm_ps_clk), + .poc_sample_pd (poc_sample_pd), + .rst (rst), + + .slot_0_present (SLOT_0_CONFIG), + .slot_1_present (SLOT_1_CONFIG) + + ,.device_temp (device_temp) + ,.tempmon_sample_en (tempmon_sample_en) + ,.psen (psen) + ,.psincdec (psincdec) + ,.psdone (psdone) + + ,.ref_dll_lock (ref_dll_lock) + ,.rst_phaser_ref (rst_phaser_ref) + ,.iddr_rst (iddr_rst) + ); + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_clk_ibuf.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_clk_ibuf.v new file mode 100644 index 0000000..4a27897 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_clk_ibuf.v @@ -0,0 +1,130 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: clk_ibuf.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ +// \ \ / \ Date Created:Mon Aug 3 2009 +// \___\/\___\ +// +//Device: Virtex-6 +//Design Name: DDR3 SDRAM +//Purpose: +// Clock generation/distribution and reset synchronization +//Reference: +//Revision History: +//***************************************************************************** +`timescale 1ns/1ps + +module mig_7series_v4_0_clk_ibuf # + ( + parameter SYSCLK_TYPE = "DIFFERENTIAL", + // input clock type + parameter DIFF_TERM_SYSCLK = "TRUE" + // Differential Termination + ) + ( + // Clock inputs + input sys_clk_p, // System clock diff input + input sys_clk_n, + input sys_clk_i, + output mmcm_clk + ); + + (* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */; + + generate + if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk + + //*********************************************************************** + // Differential input clock input buffers + //*********************************************************************** + + IBUFGDS # + ( + .DIFF_TERM (DIFF_TERM_SYSCLK), + .IBUF_LOW_PWR ("FALSE") + ) + u_ibufg_sys_clk + ( + .I (sys_clk_p), + .IB (sys_clk_n), + .O (sys_clk_ibufg) + ); + + end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk + + //*********************************************************************** + // SINGLE_ENDED input clock input buffers + //*********************************************************************** + + IBUFG # + ( + .IBUF_LOW_PWR ("FALSE") + ) + u_ibufg_sys_clk + ( + .I (sys_clk_i), + .O (sys_clk_ibufg) + ); + end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk + + //*********************************************************************** + // System clock is driven from FPGA internal clock (clock from fabric) + //*********************************************************************** + assign sys_clk_ibufg = sys_clk_i; + end + endgenerate + + assign mmcm_clk = sys_clk_ibufg; + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_byte_group_io.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_byte_group_io.v new file mode 100644 index 0000000..595fb98 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_byte_group_io.v @@ -0,0 +1,534 @@ +/***************************************************************** +-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). A Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +// +// +// Owner: Gary Martin +// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_group_io.v#4 $ +// $Author: $ +// $DateTime: $ +// $Change: $ +// Description: +// This verilog file is a paramertizable I/O termination for +// the single byte lane. +// to create a N byte-lane wide phy. +// +// History: +// Date Engineer Description +// 04/01/2010 G. Martin Initial Checkin. +// +////////////////////////////////////////////////////////////////// +*****************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_byte_group_io #( +// bit lane existance + parameter BITLANES = 12'b1111_1111_1111, + parameter BITLANES_OUTONLY = 12'b0000_0000_0000, + parameter PO_DATA_CTL = "FALSE", + parameter OSERDES_DATA_RATE = "DDR", + parameter OSERDES_DATA_WIDTH = 4, + parameter IDELAYE2_IDELAY_TYPE = "VARIABLE", + parameter IDELAYE2_IDELAY_VALUE = 00, + parameter IODELAY_GRP = "IODELAY_MIG", + parameter FPGA_SPEED_GRADE = 1, + parameter real TCK = 2500.0, +// local usage only, don't pass down + parameter BUS_WIDTH = 12, + parameter SYNTHESIS = "FALSE" + ) + ( + input [9:0] mem_dq_in, + output [BUS_WIDTH-1:0] mem_dq_out, + output [BUS_WIDTH-1:0] mem_dq_ts, + input mem_dqs_in, + output mem_dqs_out, + output mem_dqs_ts, + output [(4*10)-1:0] iserdes_dout, // 2 extra 12-bit lanes not used + output dqs_to_phaser, + input iserdes_clk, + input iserdes_clkb, + input iserdes_clkdiv, + input phy_clk, + input rst, + input oserdes_rst, + input iserdes_rst, + input [1:0] oserdes_dqs, + input [1:0] oserdes_dqsts, + input [(4*BUS_WIDTH)-1:0] oserdes_dq, + input [1:0] oserdes_dqts, + input oserdes_clk, + input oserdes_clk_delayed, + input oserdes_clkdiv, + input idelay_inc, + input idelay_ce, + input idelay_ld, + input idelayctrl_refclk, + input [29:0] fine_delay , + input fine_delay_sel + ); + + + +/// INSTANCES + + +localparam ISERDES_DQ_DATA_RATE = "DDR"; +localparam ISERDES_DQ_DATA_WIDTH = 4; +localparam ISERDES_DQ_DYN_CLKDIV_INV_EN = "FALSE"; +localparam ISERDES_DQ_DYN_CLK_INV_EN = "FALSE"; +localparam ISERDES_DQ_INIT_Q1 = 1'b0; +localparam ISERDES_DQ_INIT_Q2 = 1'b0; +localparam ISERDES_DQ_INIT_Q3 = 1'b0; +localparam ISERDES_DQ_INIT_Q4 = 1'b0; +localparam ISERDES_DQ_INTERFACE_TYPE = "MEMORY_DDR3"; +localparam ISERDES_NUM_CE = 2; +localparam ISERDES_DQ_IOBDELAY = "IFD"; +localparam ISERDES_DQ_OFB_USED = "FALSE"; +localparam ISERDES_DQ_SERDES_MODE = "MASTER"; +localparam ISERDES_DQ_SRVAL_Q1 = 1'b0; +localparam ISERDES_DQ_SRVAL_Q2 = 1'b0; +localparam ISERDES_DQ_SRVAL_Q3 = 1'b0; +localparam ISERDES_DQ_SRVAL_Q4 = 1'b0; + +localparam IDELAY_FINEDELAY_USE = (TCK > 1500) ? "FALSE" : "TRUE"; + +wire [BUS_WIDTH-1:0] data_in_dly; +wire [BUS_WIDTH-1:0] oserdes_dq_buf; +wire [BUS_WIDTH-1:0] oserdes_dqts_buf; +wire oserdes_dqs_buf; +wire oserdes_dqsts_buf; +wire [9:0] data_in; +wire tbyte_out; +reg [29:0] fine_delay_r; + +assign mem_dq_out = oserdes_dq_buf; +assign mem_dq_ts = oserdes_dqts_buf; +assign data_in = mem_dq_in; + +assign mem_dqs_out = oserdes_dqs_buf; +assign mem_dqs_ts = oserdes_dqsts_buf; +assign dqs_to_phaser = mem_dqs_in; + +reg iserdes_clk_d; + +always @(*) + iserdes_clk_d = iserdes_clk; + +reg idelay_ld_rst; +reg rst_r1; +reg rst_r2; +reg rst_r3; +reg rst_r4; + +always @(posedge phy_clk) begin + rst_r1 <= #1 rst; + rst_r2 <= #1 rst_r1; + rst_r3 <= #1 rst_r2; + rst_r4 <= #1 rst_r3; +end + +always @(posedge phy_clk) begin + if (rst) + idelay_ld_rst <= #1 1'b1; + else if (rst_r4) + idelay_ld_rst <= #1 1'b0; +end + +always @ (posedge phy_clk) begin + if(rst) + fine_delay_r <= #1 1'b0; + else if(fine_delay_sel) + fine_delay_r <= #1 fine_delay; +end + + +genvar i; + +generate + +for ( i = 0; i != 10 && PO_DATA_CTL == "TRUE" ; i=i+1) begin : input_ + if ( BITLANES[i] && !BITLANES_OUTONLY[i]) begin : iserdes_dq_ + + ISERDESE2 #( + .DATA_RATE ( ISERDES_DQ_DATA_RATE), + .DATA_WIDTH ( ISERDES_DQ_DATA_WIDTH), + .DYN_CLKDIV_INV_EN ( ISERDES_DQ_DYN_CLKDIV_INV_EN), + .DYN_CLK_INV_EN ( ISERDES_DQ_DYN_CLK_INV_EN), + .INIT_Q1 ( ISERDES_DQ_INIT_Q1), + .INIT_Q2 ( ISERDES_DQ_INIT_Q2), + .INIT_Q3 ( ISERDES_DQ_INIT_Q3), + .INIT_Q4 ( ISERDES_DQ_INIT_Q4), + .INTERFACE_TYPE ( ISERDES_DQ_INTERFACE_TYPE), + .NUM_CE ( ISERDES_NUM_CE), + .IOBDELAY ( ISERDES_DQ_IOBDELAY), + .OFB_USED ( ISERDES_DQ_OFB_USED), + .SERDES_MODE ( ISERDES_DQ_SERDES_MODE), + .SRVAL_Q1 ( ISERDES_DQ_SRVAL_Q1), + .SRVAL_Q2 ( ISERDES_DQ_SRVAL_Q2), + .SRVAL_Q3 ( ISERDES_DQ_SRVAL_Q3), + .SRVAL_Q4 ( ISERDES_DQ_SRVAL_Q4) + ) + iserdesdq + ( + .O (), + .Q1 (iserdes_dout[4*i + 3]), + .Q2 (iserdes_dout[4*i + 2]), + .Q3 (iserdes_dout[4*i + 1]), + .Q4 (iserdes_dout[4*i + 0]), + .Q5 (), + .Q6 (), + .Q7 (), + .Q8 (), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + + .BITSLIP (1'b0), + .CE1 (1'b1), + .CE2 (1'b1), + .CLK (iserdes_clk_d), + .CLKB (!iserdes_clk_d), + .CLKDIVP (iserdes_clkdiv), + .CLKDIV (), + .DDLY (data_in_dly[i]), + .D (data_in[i]), // dedicated route to iob for debugging + // or as needed, select with IOBDELAY + .DYNCLKDIVSEL (1'b0), + .DYNCLKSEL (1'b0), +// NOTE: OCLK is not used in this design, but is required to meet +// a design rule check in map and bitgen. Do not disconnect it. + .OCLK (oserdes_clk), + .OCLKB (), + .OFB (), + .RST (1'b0), +// .RST (iserdes_rst), + .SHIFTIN1 (1'b0), + .SHIFTIN2 (1'b0) + ); + +localparam IDELAYE2_CINVCTRL_SEL = "FALSE"; +localparam IDELAYE2_DELAY_SRC = "IDATAIN"; +localparam IDELAYE2_HIGH_PERFORMANCE_MODE = "TRUE"; +localparam IDELAYE2_PIPE_SEL = "FALSE"; +localparam IDELAYE2_ODELAY_TYPE = "FIXED"; +localparam IDELAYE2_REFCLK_FREQUENCY = ((FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) && TCK <= 1500) ? 400.0 : + (FPGA_SPEED_GRADE == 1 && TCK <= 1500) ? 300.0 : 200.0; +localparam IDELAYE2_SIGNAL_PATTERN = "DATA"; +localparam IDELAYE2_FINEDELAY_IN = "ADD_DLY"; + + if(IDELAY_FINEDELAY_USE == "TRUE") begin: idelay_finedelay_dq + (* IODELAY_GROUP = IODELAY_GRP *) + IDELAYE2_FINEDELAY #( + .CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL), + .DELAY_SRC ( IDELAYE2_DELAY_SRC), + .HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE), + .IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE), + .IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE), + .PIPE_SEL ( IDELAYE2_PIPE_SEL), + .FINEDELAY ( IDELAYE2_FINEDELAY_IN), + .REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ), + .SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN) + ) + idelaye2 + ( + .CNTVALUEOUT (), + .DATAOUT (data_in_dly[i]), + .C (phy_clk), // automatically wired by ISE + .CE (idelay_ce), + .CINVCTRL (), + .CNTVALUEIN (5'b00000), + .DATAIN (1'b0), + .IDATAIN (data_in[i]), + .IFDLY (fine_delay_r[i*3+:3]), + .INC (idelay_inc), + .LD (idelay_ld | idelay_ld_rst), + .LDPIPEEN (1'b0), + .REGRST (rst) + ); + end else begin : idelay_dq + (* IODELAY_GROUP = IODELAY_GRP *) + IDELAYE2 #( + .CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL), + .DELAY_SRC ( IDELAYE2_DELAY_SRC), + .HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE), + .IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE), + .IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE), + .PIPE_SEL ( IDELAYE2_PIPE_SEL), + .REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ), + .SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN) + ) + idelaye2 + ( + .CNTVALUEOUT (), + .DATAOUT (data_in_dly[i]), + .C (phy_clk), // automatically wired by ISE + .CE (idelay_ce), + .CINVCTRL (), + .CNTVALUEIN (5'b00000), + .DATAIN (1'b0), + .IDATAIN (data_in[i]), + .INC (idelay_inc), + .LD (idelay_ld | idelay_ld_rst), + .LDPIPEEN (1'b0), + .REGRST (rst) + ); + + end + end // iserdes_dq + else begin + assign iserdes_dout[4*i + 3] = 0; + assign iserdes_dout[4*i + 2] = 0; + assign iserdes_dout[4*i + 1] = 0; + assign iserdes_dout[4*i + 0] = 0; + end +end // input_ +endgenerate // iserdes_dq_ + +localparam OSERDES_DQ_DATA_RATE_OQ = OSERDES_DATA_RATE; +localparam OSERDES_DQ_DATA_RATE_TQ = OSERDES_DQ_DATA_RATE_OQ; +localparam OSERDES_DQ_DATA_WIDTH = OSERDES_DATA_WIDTH; +localparam OSERDES_DQ_INIT_OQ = 1'b1; +localparam OSERDES_DQ_INIT_TQ = 1'b1; +localparam OSERDES_DQ_INTERFACE_TYPE = "DEFAULT"; +localparam OSERDES_DQ_ODELAY_USED = 0; +localparam OSERDES_DQ_SERDES_MODE = "MASTER"; +localparam OSERDES_DQ_SRVAL_OQ = 1'b1; +localparam OSERDES_DQ_SRVAL_TQ = 1'b1; +// note: obuf used in control path case, no ts input so width irrelevant +localparam OSERDES_DQ_TRISTATE_WIDTH = (OSERDES_DQ_DATA_RATE_OQ == "DDR") ? 4 : 1; + +localparam OSERDES_DQS_DATA_RATE_OQ = "DDR"; +localparam OSERDES_DQS_DATA_RATE_TQ = "DDR"; +localparam OSERDES_DQS_TRISTATE_WIDTH = 4; // this is always ddr +localparam OSERDES_DQS_DATA_WIDTH = 4; +localparam ODDR_CLK_EDGE = "SAME_EDGE"; +localparam OSERDES_TBYTE_CTL = "TRUE"; + + +generate + +localparam NUM_BITLANES = PO_DATA_CTL == "TRUE" ? 10 : BUS_WIDTH; + + if ( PO_DATA_CTL == "TRUE" ) begin : slave_ts + OSERDESE2 #( + .DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ), + .DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ), + .DATA_WIDTH (OSERDES_DQ_DATA_WIDTH), + .INIT_OQ (OSERDES_DQ_INIT_OQ), + .INIT_TQ (OSERDES_DQ_INIT_TQ), + .SERDES_MODE (OSERDES_DQ_SERDES_MODE), + .SRVAL_OQ (OSERDES_DQ_SRVAL_OQ), + .SRVAL_TQ (OSERDES_DQ_SRVAL_TQ), + .TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH), + .TBYTE_CTL ("TRUE"), + .TBYTE_SRC ("TRUE") + ) + oserdes_slave_ts + ( + .OFB (), + .OQ (), + .SHIFTOUT1 (), // not extended + .SHIFTOUT2 (), // not extended + .TFB (), + .TQ (), + .CLK (oserdes_clk), + .CLKDIV (oserdes_clkdiv), + .D1 (), + .D2 (), + .D3 (), + .D4 (), + .D5 (), + .D6 (), + .D7 (), + .D8 (), + .OCE (1'b1), + .RST (oserdes_rst), + .SHIFTIN1 (), // not extended + .SHIFTIN2 (), // not extended + .T1 (oserdes_dqts[0]), + .T2 (oserdes_dqts[0]), + .T3 (oserdes_dqts[1]), + .T4 (oserdes_dqts[1]), + .TCE (1'b1), + .TBYTEOUT (tbyte_out), + .TBYTEIN (tbyte_out) + ); + end // slave_ts + + for (i = 0; i != NUM_BITLANES; i=i+1) begin : output_ + if ( BITLANES[i]) begin : oserdes_dq_ + + if ( PO_DATA_CTL == "TRUE" ) begin : ddr + + OSERDESE2 #( + .DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ), + .DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ), + .DATA_WIDTH (OSERDES_DQ_DATA_WIDTH), + .INIT_OQ (OSERDES_DQ_INIT_OQ), + .INIT_TQ (OSERDES_DQ_INIT_TQ), + .SERDES_MODE (OSERDES_DQ_SERDES_MODE), + .SRVAL_OQ (OSERDES_DQ_SRVAL_OQ), + .SRVAL_TQ (OSERDES_DQ_SRVAL_TQ), + .TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH), + .TBYTE_CTL (OSERDES_TBYTE_CTL), + .TBYTE_SRC ("FALSE") + ) + oserdes_dq_i + ( + .OFB (), + .OQ (oserdes_dq_buf[i]), + .SHIFTOUT1 (), // not extended + .SHIFTOUT2 (), // not extended + .TBYTEOUT (), + .TFB (), + .TQ (oserdes_dqts_buf[i]), + .CLK (oserdes_clk), + .CLKDIV (oserdes_clkdiv), + .D1 (oserdes_dq[4 * i + 0]), + .D2 (oserdes_dq[4 * i + 1]), + .D3 (oserdes_dq[4 * i + 2]), + .D4 (oserdes_dq[4 * i + 3]), + .D5 (), + .D6 (), + .D7 (), + .D8 (), + .OCE (1'b1), + .RST (oserdes_rst), + .SHIFTIN1 (), // not extended + .SHIFTIN2 (), // not extended + .T1 (/*oserdes_dqts[0]*/), + .T2 (/*oserdes_dqts[0]*/), + .T3 (/*oserdes_dqts[1]*/), + .T4 (/*oserdes_dqts[1]*/), + .TCE (1'b1), + .TBYTEIN (tbyte_out) + ); + end + else begin : sdr + OSERDESE2 #( + .DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ), + .DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ), + .DATA_WIDTH (OSERDES_DQ_DATA_WIDTH), + .INIT_OQ (1'b0 /*OSERDES_DQ_INIT_OQ*/), + .INIT_TQ (OSERDES_DQ_INIT_TQ), + .SERDES_MODE (OSERDES_DQ_SERDES_MODE), + .SRVAL_OQ (1'b0 /*OSERDES_DQ_SRVAL_OQ*/), + .SRVAL_TQ (OSERDES_DQ_SRVAL_TQ), + .TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH) + ) + oserdes_dq_i + ( + .OFB (), + .OQ (oserdes_dq_buf[i]), + .SHIFTOUT1 (), // not extended + .SHIFTOUT2 (), // not extended + .TBYTEOUT (), + .TFB (), + .TQ (), + .CLK (oserdes_clk), + .CLKDIV (oserdes_clkdiv), + .D1 (oserdes_dq[4 * i + 0]), + .D2 (oserdes_dq[4 * i + 1]), + .D3 (oserdes_dq[4 * i + 2]), + .D4 (oserdes_dq[4 * i + 3]), + .D5 (), + .D6 (), + .D7 (), + .D8 (), + .OCE (1'b1), + .RST (oserdes_rst), + .SHIFTIN1 (), // not extended + .SHIFTIN2 (), // not extended + .T1 (), + .T2 (), + .T3 (), + .T4 (), + .TCE (1'b1), + .TBYTEIN () + ); + end // ddr + end // oserdes_dq_ + end // output_ + +endgenerate + +generate + + if ( PO_DATA_CTL == "TRUE" ) begin : dqs_gen + + ODDR + #(.DDR_CLK_EDGE (ODDR_CLK_EDGE)) + oddr_dqs + ( + .Q (oserdes_dqs_buf), + .D1 (oserdes_dqs[0]), + .D2 (oserdes_dqs[1]), + .C (oserdes_clk_delayed), + .R (1'b0), + .S (), + .CE (1'b1) + ); + + ODDR + #(.DDR_CLK_EDGE (ODDR_CLK_EDGE)) + oddr_dqsts + ( .Q (oserdes_dqsts_buf), + .D1 (oserdes_dqsts[0]), + .D2 (oserdes_dqsts[0]), + .C (oserdes_clk_delayed), + .R (), + .S (1'b0), + .CE (1'b1) + ); + + end // sdr rate + else begin:null_dqs + end +endgenerate + +endmodule // byte_group_io diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_byte_lane.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_byte_lane.v new file mode 100644 index 0000000..4891a93 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_byte_lane.v @@ -0,0 +1,800 @@ +/*********************************************************** +-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). A Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +// +// +// Owner: Gary Martin +// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_lane.v#4 $ +// $Author: gary $ +// $DateTime: 2010/05/11 18:05:17 $ +// $Change: 490882 $ +// Description: +// This verilog file is a parameterizable single 10 or 12 bit byte lane. +// +// History: +// Date Engineer Description +// 04/01/2010 G. Martin Initial Checkin. +// +//////////////////////////////////////////////////////////// +***********************************************************/ + + +`timescale 1ps/1ps + +//`include "phy.vh" + +module mig_7series_v4_0_ddr_byte_lane #( +// these are used to scale the index into phaser,calib,scan,mc vectors +// to access fields used in this instance + parameter ABCD = "A", // A,B,C, or D + parameter PO_DATA_CTL = "FALSE", + parameter BITLANES = 12'b1111_1111_1111, + parameter BITLANES_OUTONLY = 12'b1111_1111_1111, + parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010, + parameter RCLK_SELECT_LANE = "B", + parameter PC_CLK_RATIO = 4, + parameter USE_PRE_POST_FIFO = "FALSE", +//OUT_FIFO + parameter OF_ALMOST_EMPTY_VALUE = 1, + parameter OF_ALMOST_FULL_VALUE = 1, + parameter OF_ARRAY_MODE = "UNDECLARED", + parameter OF_OUTPUT_DISABLE = "FALSE", + parameter OF_SYNCHRONOUS_MODE = "TRUE", +//IN_FIFO + parameter IF_ALMOST_EMPTY_VALUE = 1, + parameter IF_ALMOST_FULL_VALUE = 1, + parameter IF_ARRAY_MODE = "UNDECLARED", + parameter IF_SYNCHRONOUS_MODE = "TRUE", +//PHASER_IN + parameter PI_BURST_MODE = "TRUE", + parameter PI_CLKOUT_DIV = 2, + parameter PI_FREQ_REF_DIV = "NONE", + parameter PI_FINE_DELAY = 1, + parameter PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF", + parameter PI_SEL_CLK_OFFSET = 0, + + parameter PI_SYNC_IN_DIV_RST = "FALSE", +//PHASER_OUT + parameter PO_CLKOUT_DIV = (PO_DATA_CTL == "FALSE") ? 4 : 2, + parameter PO_FINE_DELAY = 0, + parameter PO_COARSE_BYPASS = "FALSE", + parameter PO_COARSE_DELAY = 0, + parameter PO_OCLK_DELAY = 0, + parameter PO_OCLKDELAY_INV = "TRUE", + parameter PO_OUTPUT_CLK_SRC = "DELAYED_REF", + parameter PO_SYNC_IN_DIV_RST = "FALSE", +// OSERDES + parameter OSERDES_DATA_RATE = "DDR", + parameter OSERDES_DATA_WIDTH = 4, + +//IDELAY + parameter IDELAYE2_IDELAY_TYPE = "VARIABLE", + parameter IDELAYE2_IDELAY_VALUE = 00, + parameter IODELAY_GRP = "IODELAY_MIG", + parameter FPGA_SPEED_GRADE = 1, + parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" + parameter real TCK = 0.00, + parameter SYNTHESIS = "FALSE", + +// local constants, do not pass in from above + parameter BUS_WIDTH = 12, + parameter MSB_BURST_PEND_PO = 3, + parameter MSB_BURST_PEND_PI = 7, + parameter MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8, + parameter PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1 + ,parameter CKE_ODT_AUX = "FALSE" + ,parameter PI_DIV2_INCDEC = "FALSE" + )( + input rst, + input phy_clk, + input rst_pi_div2, + input clk_div2, + input freq_refclk, + input mem_refclk, + input idelayctrl_refclk, + input sync_pulse, + output [BUS_WIDTH-1:0] mem_dq_out, + output [BUS_WIDTH-1:0] mem_dq_ts, + input [9:0] mem_dq_in, + output mem_dqs_out, + output mem_dqs_ts, + input mem_dqs_in, + output [11:0] ddr_ck_out, + output rclk, + input if_empty_def, + output if_a_empty, + output if_empty, + output if_a_full, + output if_full, + output of_a_empty, + output of_empty, + output of_a_full, + output of_full, + output pre_fifo_a_full, + output [79:0] phy_din, + input [79:0] phy_dout, + input phy_cmd_wr_en, + input phy_data_wr_en, + input phy_rd_en, + input [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus, + input idelay_inc, + input idelay_ce, + input idelay_ld, + input if_rst, + input [2:0] byte_rd_en_oth_lanes, + input [1:0] byte_rd_en_oth_banks, + output byte_rd_en, + + output po_coarse_overflow, + output po_fine_overflow, + output [8:0] po_counter_read_val, + input po_fine_enable, + input po_coarse_enable, + input [1:0] po_en_calib, + input po_fine_inc, + input po_coarse_inc, + input po_counter_load_en, + input po_counter_read_en, + input po_sel_fine_oclk_delay, + input [8:0] po_counter_load_val, + + input [1:0] pi_en_calib, + input pi_rst_dqs_find, + input pi_fine_enable, + input pi_fine_inc, + input pi_counter_load_en, + input pi_counter_read_en, + input [5:0] pi_counter_load_val, + + output wire pi_iserdes_rst, + output pi_phase_locked, + output pi_fine_overflow, + output [5:0] pi_counter_read_val, + output wire pi_dqs_found, + output dqs_out_of_range, + input [29:0] fine_delay, + input fine_delay_sel +); + +localparam PHASER_INDEX = + (ABCD=="B" ? 1 : (ABCD == "C") ? 2 : (ABCD == "D" ? 3 : 0)); +localparam L_OF_ARRAY_MODE = + (OF_ARRAY_MODE != "UNDECLARED") ? OF_ARRAY_MODE : + (PO_DATA_CTL == "FALSE" || PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_8_X_4"; +localparam L_IF_ARRAY_MODE = (IF_ARRAY_MODE != "UNDECLARED") ? IF_ARRAY_MODE : + (PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_4_X_8"; + +localparam L_OSERDES_DATA_RATE = (OSERDES_DATA_RATE != "UNDECLARED") ? OSERDES_DATA_RATE : ((PO_DATA_CTL == "FALSE" && PC_CLK_RATIO == 4) ? "SDR" : "DDR") ; +localparam L_OSERDES_DATA_WIDTH = (OSERDES_DATA_WIDTH != "UNDECLARED") ? OSERDES_DATA_WIDTH : 4; +localparam real L_FREQ_REF_PERIOD_NS = TCK > 2500.0 ? (TCK/(PI_FREQ_REF_DIV == "DIV2" ? 2 : 1)/1000.0) : TCK/1000.0; +localparam real L_MEM_REF_PERIOD_NS = TCK/1000.0; +localparam real L_PHASE_REF_PERIOD_NS = TCK/1000.0; +localparam ODDR_CLK_EDGE = "SAME_EDGE"; +localparam PO_DCD_CORRECTION = "ON"; +localparam [2:0] PO_DCD_SETTING = (PO_DCD_CORRECTION == "ON") ? 3'b111 : 3'b000; + +localparam DQS_AUTO_RECAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? 1 : 0; +localparam DQS_FIND_PATTERN = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? "001" : "000"; + +wire [1:0] oserdes_dqs; +wire [1:0] oserdes_dqs_ts; +wire [1:0] oserdes_dq_ts; + +wire [3:0] of_q9; +wire [3:0] of_q8; +wire [3:0] of_q7; +wire [7:0] of_q6; +wire [7:0] of_q5; +wire [3:0] of_q4; +wire [3:0] of_q3; +wire [3:0] of_q2; +wire [3:0] of_q1; +wire [3:0] of_q0; +wire [7:0] of_d9; +wire [7:0] of_d8; +wire [7:0] of_d7; +wire [7:0] of_d6; +wire [7:0] of_d5; +wire [7:0] of_d4; +wire [7:0] of_d3; +wire [7:0] of_d2; +wire [7:0] of_d1; +wire [7:0] of_d0; + +wire [7:0] if_q9; +wire [7:0] if_q8; +wire [7:0] if_q7; +wire [7:0] if_q6; +wire [7:0] if_q5; +wire [7:0] if_q4; +wire [7:0] if_q3; +wire [7:0] if_q2; +wire [7:0] if_q1; +wire [7:0] if_q0; +wire [3:0] if_d9; +wire [3:0] if_d8; +wire [3:0] if_d7; +wire [3:0] if_d6; +wire [3:0] if_d5; +wire [3:0] if_d4; +wire [3:0] if_d3; +wire [3:0] if_d2; +wire [3:0] if_d1; +wire [3:0] if_d0; + +wire [3:0] dummy_i5; +wire [3:0] dummy_i6; + +wire [48-1:0] of_dqbus; +wire [10*4-1:0] iserdes_dout; + +wire iserdes_clk; +wire iserdes_clkdiv; +wire ififo_wr_enable; +wire phy_rd_en_; + + +wire dqs_to_phaser; +wire phy_wr_en = ( PO_DATA_CTL == "FALSE" ) ? phy_cmd_wr_en : phy_data_wr_en; +wire if_empty_; +wire if_a_empty_; +wire if_full_; +wire if_a_full_; +wire po_oserdes_rst; +wire empty_post_fifo; +reg [3:0] if_empty_r /* synthesis syn_maxfan = 3 */; +wire [79:0] rd_data; +reg [79:0] rd_data_r; + +reg ififo_rst = 1'b1; +reg ofifo_rst = 1'b1; + +wire of_wren_pre; +wire [79:0] pre_fifo_dout; +wire pre_fifo_full; +wire pre_fifo_rden; +wire [5:0] ddr_ck_out_q; +wire ififo_rd_en_in /* synthesis syn_maxfan = 10 */; +wire oserdes_clkdiv; +wire oserdes_clk_delayed; +wire po_rd_enable; + +always @(posedge phy_clk) begin + ififo_rst <= #1 pi_rst_dqs_find | if_rst ; +// reset only data o-fifos on reset of dqs_found + ofifo_rst <= #1 (pi_rst_dqs_find & PO_DATA_CTL == "TRUE") | rst; +end + +// IN_FIFO EMPTY->RDEN TIMING FIX: +// Always read from IN_FIFO - it doesn't hurt to read from an empty FIFO +// since the IN_FIFO read pointers are not incr'ed when the FIFO is empty +assign #(25) phy_rd_en_ = 1'b1; +//assign #(25) phy_rd_en_ = phy_rd_en; + +generate +if ( PO_DATA_CTL == "FALSE" ) begin : if_empty_null + assign if_empty = 0; + assign if_a_empty = 0; + assign if_full = 0; + assign if_a_full = 0; +end +else begin : if_empty_gen + assign if_empty = empty_post_fifo; + assign if_a_empty = if_a_empty_; + assign if_full = if_full_; + assign if_a_full = if_a_full_; +end +endgenerate + +generate +if ( PO_DATA_CTL == "FALSE" ) begin : dq_gen_48 + assign of_dqbus[48-1:0] = {of_q6[7:4], of_q5[7:4], of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0}; + assign phy_din = 80'h0; + assign byte_rd_en = 1'b1; +end +else begin : dq_gen_40 + + assign of_dqbus[40-1:0] = {of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0}; + assign ififo_rd_en_in = !if_empty_def ? ((&byte_rd_en_oth_banks) && (&byte_rd_en_oth_lanes) && byte_rd_en) : + ((|byte_rd_en_oth_banks) || (|byte_rd_en_oth_lanes) || byte_rd_en); + + if (USE_PRE_POST_FIFO == "TRUE") begin : if_post_fifo_gen + + // IN_FIFO EMPTY->RDEN TIMING FIX: + assign rd_data = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0}; + + always @(posedge phy_clk) begin + rd_data_r <= #(025) rd_data; + if_empty_r[0] <= #(025) if_empty_; + if_empty_r[1] <= #(025) if_empty_; + if_empty_r[2] <= #(025) if_empty_; + if_empty_r[3] <= #(025) if_empty_; + end + + + mig_7series_v4_0_ddr_if_post_fifo # + ( + .TCQ (25), // simulation CK->Q delay + .DEPTH (4), //2 // depth - account for up to 2 cycles of skew + .WIDTH (80) // width + ) + u_ddr_if_post_fifo + ( + .clk (phy_clk), + .rst (ififo_rst), + .empty_in (if_empty_r), + .rd_en_in (ififo_rd_en_in), + .d_in (rd_data_r), + .empty_out (empty_post_fifo), + .byte_rd_en (byte_rd_en), + .d_out (phy_din) + ); + + end + else begin : phy_din_gen + assign phy_din = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0}; + assign empty_post_fifo = if_empty_; + end + +end +endgenerate + + +assign { if_d9, if_d8, if_d7, if_d6, if_d5, if_d4, if_d3, if_d2, if_d1, if_d0} = iserdes_dout; + + +wire [1:0] rank_sel_i = ((phaser_ctl_bus[MSB_RANK_SEL_I :MSB_RANK_SEL_I -7] >> (PHASER_INDEX << 1)) & 2'b11); + + + + +generate + +if ( USE_PRE_POST_FIFO == "TRUE" ) begin : of_pre_fifo_gen + assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = pre_fifo_dout; + mig_7series_v4_0_ddr_of_pre_fifo # + ( + .TCQ (25), // simulation CK->Q delay + .DEPTH (9), // depth - set to 9 to accommodate flow control + .WIDTH (80) // width + ) + u_ddr_of_pre_fifo + ( + .clk (phy_clk), + .rst (ofifo_rst), + .full_in (of_full), + .wr_en_in (phy_wr_en), + .d_in (phy_dout), + .wr_en_out (of_wren_pre), + .d_out (pre_fifo_dout), + .afull (pre_fifo_a_full) + ); +end +else begin +// wire direct to ofifo + assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = phy_dout; + assign of_wren_pre = phy_wr_en; +end + + +endgenerate + +/////////////////////////////////////////////////////////////////////////////// +// Synchronize pi_phase_locked to phy_clk domain +/////////////////////////////////////////////////////////////////////////////// +wire pi_phase_locked_w; +wire pi_dqs_found_w; +wire [5:0] pi_counter_read_val_w; +generate + if (PI_DIV2_INCDEC == "TRUE") begin: phaser_in_div2_clk + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_r1; + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_r2; + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_r3; + reg pi_phase_locked_r4; + + (* ASYNC_REG = "TRUE" *) reg pi_dqs_found_r1; + (* ASYNC_REG = "TRUE" *) reg pi_dqs_found_r2; + (* ASYNC_REG = "TRUE" *) reg pi_dqs_found_r3; + reg pi_dqs_found_r4; + + (* ASYNC_REG = "TRUE" *) reg [5:0] pi_counter_read_val_r1; + (* ASYNC_REG = "TRUE" *) reg [5:0] pi_counter_read_val_r2; + (* ASYNC_REG = "TRUE" *) reg [5:0] pi_counter_read_val_r3; + reg [5:0] pi_counter_read_val_r4; + + always @ (posedge phy_clk) begin + pi_phase_locked_r1 <= pi_phase_locked_w; + pi_phase_locked_r2 <= pi_phase_locked_r1; + pi_phase_locked_r3 <= pi_phase_locked_r2; + pi_dqs_found_r1 <= pi_dqs_found_w; + pi_dqs_found_r2 <= pi_dqs_found_r1; + pi_dqs_found_r3 <= pi_dqs_found_r2; + pi_counter_read_val_r1 <= pi_counter_read_val_w; + pi_counter_read_val_r2 <= pi_counter_read_val_r1; + pi_counter_read_val_r3 <= pi_counter_read_val_r2; + end + + always @ (posedge phy_clk) begin + if (rst) + pi_phase_locked_r4 <= 1'b0; + else if (pi_phase_locked_r2 == pi_phase_locked_r3) + pi_phase_locked_r4 <= pi_phase_locked_r3; + end + + always @ (posedge phy_clk) begin + if (rst) + pi_dqs_found_r4 <= 1'b0; + else if (pi_dqs_found_r2 == pi_dqs_found_r3) + pi_dqs_found_r4 <= pi_dqs_found_r3; + end + + always @ (posedge phy_clk) begin + if (rst) + pi_counter_read_val_r4 <= 1'b0; + else if (pi_counter_read_val_r2 == pi_counter_read_val_r3) + pi_counter_read_val_r4 <= pi_counter_read_val_r3; + end + + assign pi_phase_locked = pi_phase_locked_r4; + assign pi_dqs_found = pi_dqs_found_r4; + assign pi_counter_read_val = pi_counter_read_val_r4; + + end else begin: pahser_in_div4_clk + assign pi_phase_locked = pi_phase_locked_w; + assign pi_dqs_found = pi_dqs_found_w; + assign pi_counter_read_val = pi_counter_read_val_w; + end +endgenerate + + +generate + +if ( PO_DATA_CTL == "TRUE" || ((RCLK_SELECT_LANE==ABCD) && (CKE_ODT_AUX =="TRUE"))) begin : phaser_in_gen + +//if (PI_DIV2_INCDEC == "TRUE") begin: phaser_in_div2_sys_clk +if (PI_DIV2_INCDEC == "TRUE") begin + +PHASER_IN_PHY #( + .BURST_MODE ( PI_BURST_MODE), + .CLKOUT_DIV ( PI_CLKOUT_DIV), + .DQS_AUTO_RECAL ( DQS_AUTO_RECAL), + .DQS_FIND_PATTERN ( DQS_FIND_PATTERN), + .SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET), + .FINE_DELAY ( PI_FINE_DELAY), + .FREQ_REF_DIV ( PI_FREQ_REF_DIV), + .OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC), + .SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST), + .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS), + .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS), + .PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS) +) phaser_in ( + .DQSFOUND (pi_dqs_found_w), + .DQSOUTOFRANGE (dqs_out_of_range), + .FINEOVERFLOW (pi_fine_overflow), + .PHASELOCKED (pi_phase_locked_w), + .ISERDESRST (pi_iserdes_rst), + .ICLKDIV (iserdes_clkdiv), + .ICLK (iserdes_clk), + .COUNTERREADVAL (pi_counter_read_val_w), + .RCLK (rclk), + .WRENABLE (ififo_wr_enable), + .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]), + .ENCALIBPHY (pi_en_calib), + .FINEENABLE (pi_fine_enable), + .FREQREFCLK (freq_refclk), + .MEMREFCLK (mem_refclk), + .RANKSELPHY (rank_sel_i), + .PHASEREFCLK (dqs_to_phaser), + .RSTDQSFIND (pi_rst_dqs_find), + .RST (rst_pi_div2), + .FINEINC (pi_fine_inc), + .COUNTERLOADEN (pi_counter_load_en), + .COUNTERREADEN (pi_counter_read_en), + .COUNTERLOADVAL (pi_counter_load_val), + .SYNCIN (sync_pulse), + .SYSCLK (clk_div2) +); +end + +else begin + +PHASER_IN_PHY #( + .BURST_MODE ( PI_BURST_MODE), + .CLKOUT_DIV ( PI_CLKOUT_DIV), + .DQS_AUTO_RECAL ( DQS_AUTO_RECAL), + .DQS_FIND_PATTERN ( DQS_FIND_PATTERN), + .SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET), + .FINE_DELAY ( PI_FINE_DELAY), + .FREQ_REF_DIV ( PI_FREQ_REF_DIV), + .OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC), + .SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST), + .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS), + .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS), + .PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS) +) phaser_in ( + .DQSFOUND (pi_dqs_found_w), + .DQSOUTOFRANGE (dqs_out_of_range), + .FINEOVERFLOW (pi_fine_overflow), + .PHASELOCKED (pi_phase_locked_w), + .ISERDESRST (pi_iserdes_rst), + .ICLKDIV (iserdes_clkdiv), + .ICLK (iserdes_clk), + .COUNTERREADVAL (pi_counter_read_val_w), + .RCLK (rclk), + .WRENABLE (ififo_wr_enable), + .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]), + .ENCALIBPHY (pi_en_calib), + .FINEENABLE (pi_fine_enable), + .FREQREFCLK (freq_refclk), + .MEMREFCLK (mem_refclk), + .RANKSELPHY (rank_sel_i), + .PHASEREFCLK (dqs_to_phaser), + .RSTDQSFIND (pi_rst_dqs_find), + .RST (rst), + .FINEINC (pi_fine_inc), + .COUNTERLOADEN (pi_counter_load_en), + .COUNTERREADEN (pi_counter_read_en), + .COUNTERLOADVAL (pi_counter_load_val), + .SYNCIN (sync_pulse), + .SYSCLK (phy_clk) +); + +end +end +else begin + assign pi_dqs_found_w = 1'b1; +// assign pi_dqs_out_of_range = 1'b0; + assign pi_phase_locked_w = 1'b1; +end + +endgenerate + +wire #0 phase_ref = freq_refclk; + +wire oserdes_clk; + + +PHASER_OUT_PHY #( + .CLKOUT_DIV ( PO_CLKOUT_DIV), + .DATA_CTL_N ( PO_DATA_CTL ), + .FINE_DELAY ( PO_FINE_DELAY), + .COARSE_BYPASS ( PO_COARSE_BYPASS ), + .COARSE_DELAY ( PO_COARSE_DELAY), + .OCLK_DELAY ( PO_OCLK_DELAY), + .OCLKDELAY_INV ( PO_OCLKDELAY_INV), + .OUTPUT_CLK_SRC ( PO_OUTPUT_CLK_SRC), + .SYNC_IN_DIV_RST ( PO_SYNC_IN_DIV_RST), + .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS), + .PHASEREFCLK_PERIOD ( 1), // dummy, not used + .PO ( PO_DCD_SETTING ), + .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS) +) phaser_out ( + .COARSEOVERFLOW (po_coarse_overflow), + .CTSBUS (oserdes_dqs_ts), + .DQSBUS (oserdes_dqs), + .DTSBUS (oserdes_dq_ts), + .FINEOVERFLOW (po_fine_overflow), + .OCLKDIV (oserdes_clkdiv), + .OCLK (oserdes_clk), + .OCLKDELAYED (oserdes_clk_delayed), + .COUNTERREADVAL (po_counter_read_val), + .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PO -3 + PHASER_INDEX]), + .ENCALIBPHY (po_en_calib), + .RDENABLE (po_rd_enable), + .FREQREFCLK (freq_refclk), + .MEMREFCLK (mem_refclk), + .PHASEREFCLK (/*phase_ref*/), + .RST (rst), + .OSERDESRST (po_oserdes_rst), + .COARSEENABLE (po_coarse_enable), + .FINEENABLE (po_fine_enable), + .COARSEINC (po_coarse_inc), + .FINEINC (po_fine_inc), + .SELFINEOCLKDELAY (po_sel_fine_oclk_delay), + .COUNTERLOADEN (po_counter_load_en), + .COUNTERREADEN (po_counter_read_en), + .COUNTERLOADVAL (po_counter_load_val), + .SYNCIN (sync_pulse), + .SYSCLK (phy_clk) +); + + +generate + +if (PO_DATA_CTL == "TRUE") begin : in_fifo_gen + +IN_FIFO #( + .ALMOST_EMPTY_VALUE ( IF_ALMOST_EMPTY_VALUE ), + .ALMOST_FULL_VALUE ( IF_ALMOST_FULL_VALUE ), + .ARRAY_MODE ( L_IF_ARRAY_MODE), + .SYNCHRONOUS_MODE ( IF_SYNCHRONOUS_MODE) +) in_fifo ( + .ALMOSTEMPTY (if_a_empty_), + .ALMOSTFULL (if_a_full_), + .EMPTY (if_empty_), + .FULL (if_full_), + .Q0 (if_q0), + .Q1 (if_q1), + .Q2 (if_q2), + .Q3 (if_q3), + .Q4 (if_q4), + .Q5 (if_q5), + .Q6 (if_q6), + .Q7 (if_q7), + .Q8 (if_q8), + .Q9 (if_q9), +//=== + .D0 (if_d0), + .D1 (if_d1), + .D2 (if_d2), + .D3 (if_d3), + .D4 (if_d4), + .D5 ({dummy_i5,if_d5}), + .D6 ({dummy_i6,if_d6}), + .D7 (if_d7), + .D8 (if_d8), + .D9 (if_d9), + .RDCLK (phy_clk), + .RDEN (phy_rd_en_), + .RESET (ififo_rst), + .WRCLK (iserdes_clkdiv), + .WREN (ififo_wr_enable) +); +end + +endgenerate + + + +OUT_FIFO #( + .ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), + .ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), + .ARRAY_MODE (L_OF_ARRAY_MODE), + .OUTPUT_DISABLE (OF_OUTPUT_DISABLE), + .SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE) +) out_fifo ( + .ALMOSTEMPTY (of_a_empty), + .ALMOSTFULL (of_a_full), + .EMPTY (of_empty), + .FULL (of_full), + .Q0 (of_q0), + .Q1 (of_q1), + .Q2 (of_q2), + .Q3 (of_q3), + .Q4 (of_q4), + .Q5 (of_q5), + .Q6 (of_q6), + .Q7 (of_q7), + .Q8 (of_q8), + .Q9 (of_q9), + .D0 (of_d0), + .D1 (of_d1), + .D2 (of_d2), + .D3 (of_d3), + .D4 (of_d4), + .D5 (of_d5), + .D6 (of_d6), + .D7 (of_d7), + .D8 (of_d8), + .D9 (of_d9), + .RDCLK (oserdes_clkdiv), + .RDEN (po_rd_enable), + .RESET (ofifo_rst), + .WRCLK (phy_clk), + .WREN (of_wren_pre) +); + + +mig_7series_v4_0_ddr_byte_group_io # + ( + .PO_DATA_CTL (PO_DATA_CTL), + .BITLANES (BITLANES), + .BITLANES_OUTONLY (BITLANES_OUTONLY), + .OSERDES_DATA_RATE (L_OSERDES_DATA_RATE), + .OSERDES_DATA_WIDTH (L_OSERDES_DATA_WIDTH), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .IDELAYE2_IDELAY_TYPE (IDELAYE2_IDELAY_TYPE), + .IDELAYE2_IDELAY_VALUE (IDELAYE2_IDELAY_VALUE), + .TCK (TCK), + .SYNTHESIS (SYNTHESIS) + ) + ddr_byte_group_io + ( + .mem_dq_out (mem_dq_out), + .mem_dq_ts (mem_dq_ts), + .mem_dq_in (mem_dq_in), + .mem_dqs_in (mem_dqs_in), + .mem_dqs_out (mem_dqs_out), + .mem_dqs_ts (mem_dqs_ts), + .rst (rst), + .oserdes_rst (po_oserdes_rst), + .iserdes_rst (pi_iserdes_rst ), + .iserdes_dout (iserdes_dout), + .dqs_to_phaser (dqs_to_phaser), + .phy_clk (phy_clk), + .iserdes_clk (iserdes_clk), + .iserdes_clkb (!iserdes_clk), + .iserdes_clkdiv (iserdes_clkdiv), + .idelay_inc (idelay_inc), + .idelay_ce (idelay_ce), + .idelay_ld (idelay_ld), + .idelayctrl_refclk (idelayctrl_refclk), + .oserdes_clk (oserdes_clk), + .oserdes_clk_delayed (oserdes_clk_delayed), + .oserdes_clkdiv (oserdes_clkdiv), + .oserdes_dqs ({oserdes_dqs[1], oserdes_dqs[0]}), + .oserdes_dqsts ({oserdes_dqs_ts[1], oserdes_dqs_ts[0]}), + .oserdes_dq (of_dqbus), + .oserdes_dqts ({oserdes_dq_ts[1], oserdes_dq_ts[0]}), + .fine_delay (fine_delay), + .fine_delay_sel (fine_delay_sel) + ); + +genvar i; +generate + for (i = 0; i <= 5; i = i+1) begin : ddr_ck_gen_loop + if (PO_DATA_CTL== "FALSE" && (BYTELANES_DDR_CK[i*4+PHASER_INDEX])) begin : ddr_ck_gen + ODDR #(.DDR_CLK_EDGE (ODDR_CLK_EDGE)) + ddr_ck ( + .C (oserdes_clk), + .R (1'b0), + .S (), + .D1 (1'b0), + .D2 (1'b1), + .CE (1'b1), + .Q (ddr_ck_out_q[i]) + ); + OBUFDS ddr_ck_obuf (.I(ddr_ck_out_q[i]), .O(ddr_ck_out[i*2]), .OB(ddr_ck_out[i*2+1])); + end // ddr_ck_gen + else begin : ddr_ck_null + assign ddr_ck_out[i*2+1:i*2] = 2'b0; + end + end // ddr_ck_gen_loop +endgenerate + +endmodule // byte_lane diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_calib_top.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_calib_top.v new file mode 100644 index 0000000..8ce8845 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_calib_top.v @@ -0,0 +1,2291 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_calib_top.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:06 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +//Purpose: +// Top-level for memory physical layer (PHY) interface +// NOTES: +// 1. Need to support multiple copies of CS outputs +// 2. DFI_DRAM_CKE_DISABLE not supported +// +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $ +**$Date: 2011/06/02 08:35:06 $ +**$Author: mishra $ +**$Revision: 1.1 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_calib_top # + ( + parameter TCQ = 100, + parameter nCK_PER_CLK = 2, // # of memory clocks per CLK + parameter tCK = 2500, // DDR3 SDRAM clock period + parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3 + parameter CLK_PERIOD = 3333, // Internal clock period (in ps) + parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY + parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" + parameter PRBS_WIDTH = 8, // The PRBS sequence is 2^PRBS_WIDTH + parameter HIGHEST_LANE = 4, + parameter HIGHEST_BANK = 3, + parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" + // five fields, one per possible I/O bank, 4 bits in each field, + // 1 per lane data=1/ctl=0 + parameter DATA_CTL_B0 = 4'hc, + parameter DATA_CTL_B1 = 4'hf, + parameter DATA_CTL_B2 = 4'hf, + parameter DATA_CTL_B3 = 4'hf, + parameter DATA_CTL_B4 = 4'hf, + // defines the byte lanes in I/O banks being used in the interface + // 1- Used, 0- Unused + parameter BYTE_LANES_B0 = 4'b1111, + parameter BYTE_LANES_B1 = 4'b0000, + parameter BYTE_LANES_B2 = 4'b0000, + parameter BYTE_LANES_B3 = 4'b0000, + parameter BYTE_LANES_B4 = 4'b0000, + parameter DQS_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, + parameter CTL_BYTE_LANE = 8'hE4, // Control byte lane map + parameter CTL_BANK = 3'b000, // Bank used for control byte lanes + // Slot Conifg parameters + parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000, + // DRAM bus widths + parameter BANK_WIDTH = 2, // # of bank bits + parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank + parameter COL_WIDTH = 10, // column address width + parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank + parameter DQ_WIDTH = 64, // # of DQ (data) + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter ROW_WIDTH = 14, // DRAM address bus width + parameter RANKS = 1, // # of memory ranks in the interface + parameter CS_WIDTH = 1, // # of CS# signals in the interface + parameter CKE_WIDTH = 1, // # of cke outputs + parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 + parameter PER_BIT_DESKEW = "ON", + // calibration Address. The address given below will be used for calibration + // read and write operations. + parameter NUM_DQSFOUND_CAL = 1020, // # of iteration of DQSFOUND calib + parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address + parameter CALIB_COL_ADD = 12'h000, // Calibration column address + parameter CALIB_BA_ADD = 3'h0, // Calibration bank address + // DRAM mode settings + parameter AL = "0", // Additive Latency option + parameter TEST_AL = "0", // Additive Latency for internal use + parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T" + parameter BURST_MODE = "8", // Burst length + parameter BURST_TYPE = "SEQ", // Burst type + parameter nCL = 5, // Read CAS latency (in clk cyc) + parameter nCWL = 5, // Write CAS latency (in clk cyc) + parameter tRFC = 110000, // Refresh-to-command delay + parameter tREFI = 7800000, // pS Refresh-to-Refresh delay + parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option + parameter REG_CTRL = "ON", // "ON" for registered DIMM + parameter RTT_NOM = "60", // ODT Nominal termination value + parameter RTT_WR = "60", // ODT Write termination value + parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA + // 1 - ODT output from FPGA + parameter WRLVL = "OFF", // Enable write leveling + parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly + parameter POC_USE_METASTABLE_SAMP = "FALSE", + + // Simulation /debug options + parameter SIM_INIT_OPTION = "NONE", // Performs all initialization steps + parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps + parameter CKE_ODT_AUX = "FALSE", + parameter IDELAY_ADJ = "ON", + parameter FINE_PER_BIT = "ON", + parameter CENTER_COMP_MODE = "ON", + parameter PI_VAL_ADJ = "ON", + parameter TAPSPERKCLK = 56, + parameter DEBUG_PORT = "OFF", // Enable debug port + parameter SKIP_CALIB = "FALSE", + parameter PI_DIV2_INCDEC = "TRUE" + ) + ( + input clk, // Internal (logic) clock + input rst, // Reset sync'ed to CLK + // Slot present inputs + input [7:0] slot_0_present, + input [7:0] slot_1_present, + // Hard PHY signals + // From PHY Ctrl Block + input phy_ctl_ready, + input phy_ctl_full, + input phy_cmd_full, + input phy_data_full, + // To PHY Ctrl Block + output write_calib, + output read_calib, + output calib_ctl_wren, + output calib_cmd_wren, + output [1:0] calib_seq, + output [3:0] calib_aux_out, + output [nCK_PER_CLK -1:0] calib_cke, + output [1:0] calib_odt, + output [2:0] calib_cmd, + output calib_wrdata_en, + output [1:0] calib_rank_cnt, + output [1:0] calib_cas_slot, + output [5:0] calib_data_offset_0, + output [5:0] calib_data_offset_1, + output [5:0] calib_data_offset_2, + output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address, + output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank, + output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n, + output [nCK_PER_CLK-1:0] phy_ras_n, + output [nCK_PER_CLK-1:0] phy_cas_n, + output [nCK_PER_CLK-1:0] phy_we_n, + output phy_reset_n, + // To hard PHY wrapper + output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 */, + output reg calib_in_common/* synthesis syn_maxfan = 10 */, + output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 */, + output reg [HIGHEST_BANK-1:0] calib_zero_ctrl, + output phy_if_empty_def, + output reg phy_if_reset, +// output reg ck_addr_ctl_delay_done, + // From DQS Phaser_In + input pi_phaselocked, + input pi_phase_locked_all, + input pi_found_dqs, + input pi_dqs_found_all, + input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, + input [5:0] pi_counter_read_val, + // To DQS Phaser_In + output [HIGHEST_BANK-1:0] pi_rst_stg1_cal, + output pi_en_stg2_f, + output pi_stg2_f_incdec, + output pi_stg2_load, + output [5:0] pi_stg2_reg_l, + // To DQ IDELAY + output idelay_ce, + output idelay_inc, + output idelay_ld, + // To DQS Phaser_Out + output [2:0] po_sel_stg2stg3 /* synthesis syn_maxfan = 3 */, + output [2:0] po_stg2_c_incdec /* synthesis syn_maxfan = 3 */, + output [2:0] po_en_stg2_c /* synthesis syn_maxfan = 3 */, + output [2:0] po_stg2_f_incdec /* synthesis syn_maxfan = 3 */, + output [2:0] po_en_stg2_f /* synthesis syn_maxfan = 3 */, + output po_counter_load_en, + input [8:0] po_counter_read_val, + // To command Phaser_Out + input phy_if_empty, + input [4:0] idelaye2_init_val, + input [5:0] oclkdelay_init_val, + + input tg_err, + output rst_tg_mc, + // Write data to OUT_FIFO + output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata, + // To CNTVALUEIN input of DQ IDELAYs for perbit de-skew + output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq, + // IN_FIFO read enable during write leveling, write calibration, + // and read leveling + // Read data from hard PHY fans out to mc and calib logic + input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata, + // To MC + output [6*RANKS-1:0] calib_rd_data_offset_0, + output [6*RANKS-1:0] calib_rd_data_offset_1, + output [6*RANKS-1:0] calib_rd_data_offset_2, + output phy_rddata_valid, + output calib_writes, + (* max_fanout = 50 *) output reg init_calib_complete/* synthesis syn_maxfan = 10 */, + output init_wrcal_complete, + output pi_phase_locked_err, + output pi_dqsfound_err, + output wrcal_err, + input pd_out, + // input mmcm_ps_clk, //phase shift clock + // input oclkdelay_fb_clk, //Write DQS feedback clk + //phase shift clock control + output psen, + output psincdec, + input psdone, + input poc_sample_pd, + + // Ports to be used when SKIP_CALIB="TRUE" + output reg calib_tap_req, + input [6:0] calib_tap_addr, + input calib_tap_load, + input [7:0] calib_tap_val, + input calib_tap_load_done, + + // Debug Port + output dbg_pi_phaselock_start, + output dbg_pi_dqsfound_start, + output dbg_pi_dqsfound_done, + output dbg_wrcal_start, + output dbg_wrcal_done, + output dbg_wrlvl_start, + output dbg_wrlvl_done, + output dbg_wrlvl_err, + output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, + output [255:0] dbg_phy_wrlvl, + output [5:0] dbg_tap_cnt_during_wrlvl, + output dbg_wl_edge_detect_valid, + output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect, + + // Write Calibration Logic + output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, + output [99:0] dbg_phy_wrcal, + + // Read leveling logic + output [1:0] dbg_rdlvl_start, + output [1:0] dbg_rdlvl_done, + output [1:0] dbg_rdlvl_err, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, + output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, + + // Delay control + input [11:0] device_temp, + input tempmon_sample_en, + input dbg_sel_pi_incdec, + input dbg_sel_po_incdec, + input [DQS_CNT_WIDTH:0] dbg_byte_sel, + input dbg_pi_f_inc, + input dbg_pi_f_dec, + input dbg_po_f_inc, + input dbg_po_f_stg23_sel, + input dbg_po_f_dec, + input dbg_idel_up_all, + input dbg_idel_down_all, + input dbg_idel_up_cpt, + input dbg_idel_down_cpt, + input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, + input dbg_sel_all_idel_cpt, + output [255:0] dbg_phy_rdlvl, // Read leveling calibration + output [255:0] dbg_calib_top, // General PHY debug + output dbg_oclkdelay_calib_start, + output dbg_oclkdelay_calib_done, + output [255:0] dbg_phy_oclkdelay_cal, + output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data, + output [255:0] dbg_phy_init, + output [255:0] dbg_prbs_rdlvl, + output [255:0] dbg_dqs_found_cal, + output [1023:0] dbg_poc, + + output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r, + output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, + output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps, + output reg [DQS_CNT_WIDTH:0] byte_sel_cnt, + output [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit + output fine_delay_sel + ); + + function integer clogb2 (input integer size); + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction + +// Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center +// align DQ and DQS on writes. Round (up or down) value to nearest integer +// localparam integer SHIFT_TBY4_TAP +// = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) / +// (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4); + +// Calculate number of slots in the system + localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0); + + localparam OCAL_EN = ((SIM_CAL_OPTION == "FAST_CAL") || (tCK > 2500) || (SKIP_CALIB == "TRUE")) ? "OFF" : "ON"; + + // Different CTL_LANES value for DDR2. In DDR2 during DQS found all + // the add,ctl & data phaser out fine delays will be adjusted. + // In DDR3 only the add/ctrl lane delays will be adjusted + localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == "DDR3") ? N_CTL_LANES : 1; + + localparam DQSFOUND_CAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && tCK > 2500)) ? "LEFT" : "RIGHT"; // IO Bank used for Memory I/F: "LEFT", "RIGHT" + + localparam FIXED_VICTIM = (SIM_CAL_OPTION == "NONE") ? "FALSE" : "TRUE"; + localparam VCCO_PAT_EN = 1; // Enable VCCO pattern during calibration + localparam VCCAUX_PAT_EN = 1; // Enable VCCAUX pattern during calibration + localparam ISI_PAT_EN = 1; // Enable VCCO pattern during calibration + + //Per-bit deskew for higher freqency (>800Mhz) + //localparam FINE_DELAY = (tCK < 1250) ? "ON" : "OFF"; + + //BYPASS + localparam BYPASS_COMPLEX_RDLVL = ((tCK > 2500) || (SKIP_CALIB == "TRUE")) ? "TRUE": "FALSE"; //"TRUE"; + localparam BYPASS_COMPLEX_OCAL = "TRUE"; + //localparam BYPASS_COMPLEX_OCAL = ((DRAM_TYPE == "DDR2") || (nCK_PER_CLK == 2) || (OCAL_EN == "OFF")) ? "TRUE" : "FALSE"; + + // 8*tREFI in ps is divided by the fabric clock period in ps + // 270 fabric clock cycles is subtracted to account for PRECHARGE, WR, RD times + localparam REFRESH_TIMER = (8*tREFI/(tCK*nCK_PER_CLK)) - 270; + + localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER); + + wire [2*8*nCK_PER_CLK-1:0] prbs_seed; + //wire [2*8*nCK_PER_CLK-1:0] prbs_out; + wire [8*DQ_WIDTH-1:0] prbs_out; + wire [7:0] prbs_rise0; + wire [7:0] prbs_fall0; + wire [7:0] prbs_rise1; + wire [7:0] prbs_fall1; + wire [7:0] prbs_rise2; + wire [7:0] prbs_fall2; + wire [7:0] prbs_rise3; + wire [7:0] prbs_fall3; + //wire [2*8*nCK_PER_CLK-1:0] prbs_o; + wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; + wire dqsfound_retry; + wire dqsfound_retry_done; + wire phy_rddata_en; + wire prech_done; + wire rdlvl_stg1_done; + reg rdlvl_stg1_done_r1; + wire pi_dqs_found_done; + wire rdlvl_stg1_err; + wire pi_dqs_found_err; + wire wrcal_pat_resume; + wire wrcal_resume_w; + wire rdlvl_prech_req; + wire rdlvl_last_byte_done; + wire rdlvl_stg1_start; + wire rdlvl_stg1_rank_done; + wire rdlvl_assrt_common; + wire pi_dqs_found_start; + wire pi_dqs_found_rank_done; + wire wl_sm_start; + wire wrcal_start; + wire wrcal_rd_wait; + wire wrcal_prech_req; + wire wrcal_pat_err; + wire wrcal_done; + wire wrlvl_done; + wire wrlvl_err; + wire wrlvl_start; + wire ck_addr_cmd_delay_done; + wire po_ck_addr_cmd_delay_done; + wire pi_calib_done; + wire detect_pi_found_dqs; + wire [5:0] rd_data_offset_0; + wire [5:0] rd_data_offset_1; + wire [5:0] rd_data_offset_2; + wire [6*RANKS-1:0] rd_data_offset_ranks_0; + wire [6*RANKS-1:0] rd_data_offset_ranks_1; + wire [6*RANKS-1:0] rd_data_offset_ranks_2; + wire [6*RANKS-1:0] rd_data_offset_ranks_mc_0; + wire [6*RANKS-1:0] rd_data_offset_ranks_mc_1; + wire [6*RANKS-1:0] rd_data_offset_ranks_mc_2; + wire cmd_po_stg2_f_incdec; + wire cmd_po_stg2_incdec_ddr2_c; + wire cmd_po_en_stg2_f; + wire cmd_po_en_stg2_ddr2_c; + wire cmd_po_stg2_c_incdec; + wire cmd_po_en_stg2_c; + wire po_stg2_ddr2_incdec; + wire po_en_stg2_ddr2; + wire dqs_po_stg2_f_incdec; + wire dqs_po_en_stg2_f; + wire dqs_wl_po_stg2_c_incdec; + wire wrcal_po_stg2_c_incdec; + wire dqs_wl_po_en_stg2_c; + wire wrcal_po_en_stg2_c; + wire [N_CTL_LANES-1:0] ctl_lane_cnt; + reg [N_CTL_LANES-1:0] ctl_lane_sel; + wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt; + wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt; + wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt; + wire [8:0] dqs_wl_po_stg2_reg_l; + wire dqs_wl_po_stg2_load; + wire [8:0] dqs_po_stg2_reg_l; + wire dqs_po_stg2_load; + wire dqs_po_dec_done; + wire pi_fine_dly_dec_done; + wire rdlvl_pi_stg2_f_incdec; + wire rdlvl_pi_stg2_f_en; + wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt; + //reg [DQS_CNT_WIDTH:0] byte_sel_cnt; + wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt; + wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt; + wire phase_locked_err; + wire phy_ctl_rdy_dly; + wire idelay_ce_int; + wire idelay_inc_int; + reg idelay_ce_r1; + reg idelay_ce_r2; + reg idelay_inc_r1; + reg idelay_inc_r2 /* synthesis syn_maxfan = 30 */; + reg po_dly_req_r; + wire wrcal_read_req; + wire wrcal_act_req; + wire temp_wrcal_done; + wire tg_timer_done; + wire no_rst_tg_mc; + wire calib_complete; + reg reset_if_r1; + reg reset_if_r2; + reg reset_if_r3; + reg reset_if_r4; + reg reset_if_r5; + reg reset_if_r6; + reg reset_if_r7; + reg reset_if_r8; + reg reset_if_r9; + reg reset_if; + wire phy_if_reset_w; + wire pi_phaselock_start; + + reg dbg_pi_f_inc_r; + reg dbg_pi_f_en_r; + reg dbg_sel_pi_incdec_r; + + reg dbg_po_f_inc_r; + reg dbg_po_f_stg23_sel_r; + reg dbg_po_f_en_r; + reg dbg_sel_po_incdec_r; + + reg tempmon_pi_f_inc_r; + reg tempmon_pi_f_en_r; + reg tempmon_sel_pi_incdec_r; + + reg ck_addr_cmd_delay_done_r1; + reg ck_addr_cmd_delay_done_r2; + reg ck_addr_cmd_delay_done_r3; + reg ck_addr_cmd_delay_done_r4; + reg ck_addr_cmd_delay_done_r5; + reg ck_addr_cmd_delay_done_r6; +// wire oclk_init_delay_start; + wire oclk_prech_req; + wire oclk_calib_resume; + wire [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + wire [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt; + wire oclkdelay_calib_start; + wire oclkdelay_calib_done; + wire complex_oclk_prech_req; + wire complex_oclk_calib_resume; + wire complex_oclkdelay_calib_start; + wire complex_oclkdelay_calib_done; + wire complex_ocal_num_samples_inc; + wire complex_ocal_num_samples_done_r; + wire [2:0] complex_ocal_rd_victim_sel; + wire complex_ocal_ref_req; + wire complex_ocal_ref_done; + wire [6*DQS_WIDTH-1:0] oclkdelay_left_edge_val; + wire [6*DQS_WIDTH-1:0] oclkdelay_right_edge_val; + + wire wrlvl_final; + wire complex_wrlvl_final; + reg wrlvl_final_mux; + wire wrlvl_final_if_rst; + wire wrlvl_byte_redo; + wire wrlvl_byte_done; + wire early1_data; + wire early2_data; + wire po_stg23_sel; + wire po_stg23_incdec; + wire po_en_stg23; + wire complex_po_stg23_sel; + wire complex_po_stg23_incdec; + wire complex_po_en_stg23; + wire mpr_rdlvl_done; + wire mpr_rdlvl_start; + wire mpr_last_byte_done; + wire mpr_rnk_done; + wire mpr_end_if_reset; + wire mpr_rdlvl_err; + wire rdlvl_err; + wire prbs_rdlvl_start; + wire prbs_rdlvl_done; + wire prbs_rdlvl_done_complex; + reg prbs_rdlvl_done_r1; + wire prbs_last_byte_done; + wire prbs_rdlvl_prech_req; + wire prbs_pi_stg2_f_incdec; + wire prbs_pi_stg2_f_en; + wire complex_sample_cnt_inc; + wire complex_sample_cnt_inc_ocal; + wire [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt; + wire prbs_gen_clk_en; + wire prbs_gen_oclk_clk_en; + wire rd_data_offset_cal_done; + wire fine_adjust_done; + wire [N_CTL_LANES-1:0] fine_adjust_lane_cnt; + wire ck_po_stg2_f_indec; + wire ck_po_stg2_f_en; + wire dqs_found_prech_req; + wire tempmon_pi_f_inc; + wire tempmon_pi_f_dec; + wire tempmon_sel_pi_incdec; + wire wrcal_sanity_chk; + wire wrcal_sanity_chk_done; + wire wrlvl_done_w; + wire wrlvl_rank_done; + wire done_dqs_tap_inc; + wire [2:0] rd_victim_sel; + wire [2:0] victim_sel; + wire [DQS_CNT_WIDTH:0] victim_byte_cnt; + wire complex_wr_done; + wire complex_victim_inc; + + wire reset_rd_addr; + wire complex_ocal_reset_rd_addr; + + wire oclkdelay_center_calib_start; + wire poc_error; + + wire prbs_ignore_first_byte; + wire prbs_ignore_last_bytes; + + //stg3 tap values + // wire [6*DQS_WIDTH-1:0] oclkdelay_center_val; + + //byte selection + // wire [DQS_CNT_WIDTH:0] oclkdelay_center_cnt; + + //INC/DEC for stg3 taps + // wire ocal_ctr_po_stg23_sel; + // wire ocal_ctr_po_stg23_incdec; + // wire ocal_ctr_po_en_stg23; + + //Write resume for DQS toggling + wire oclk_center_write_resume; + wire oclkdelay_center_calib_done; + + //Write request to toggle DQS for limit module + wire lim2init_write_request; + wire lim_done; + + // Bypass complex ocal + wire complex_oclkdelay_calib_start_w; + wire complex_oclkdelay_calib_done_w; + wire [2:0] complex_ocal_rd_victim_sel_w; + wire complex_wrlvl_final_w; + + wire [255:0] dbg_ocd_lim; + + //with MMCM phase detect logic + //wire mmcm_edge_detect_rdy; // ready for MMCM detect + //wire ktap_at_rightedge; // stg3 tap at right edge + //wire ktap_at_leftedge; // stg3 tap at left edge + //wire mmcm_tap_at_center; // indicate stg3 tap at center + //wire mmcm_ps_clkphase_ok; // ps clkphase is OK + //wire mmcm_edge_detect_done; // mmcm edge detect is done + //wire mmcm_lbclk_edges_aligned; // mmcm edge detect is done + //wire reset_mmcm; //mmcm detect logic reset per byte + + // wire [255:0] dbg_phy_oclkdelay_center_cal; + + //PI inc/dec prevention during READ + wire rdlvl_pi_incdec; + wire complex_act_start; + wire complex_pi_incdec_done; + wire num_samples_done_r; + wire complex_init_pi_dec_done; + + wire calib_tap_inc_start; + wire calib_tap_inc_done; + wire calib_tap_end_if_reset; + wire [5:0] calib_tap_inc_byte_cnt; + wire calib_po_f_en; + wire calib_po_f_incdec; + wire calib_po_sel_stg2stg3; + wire calib_po_c_en; + wire calib_po_c_inc; + wire calib_pi_f_en; + wire calib_pi_f_incdec; + wire calib_idelay_ce; + wire calib_idelay_inc; + wire coarse_dec_err; + reg skip_cal_tempmon_samp_en; + wire tempmon_done_skip; + + wire skip_cal_po_pi_dec_done; + reg [6*DQS_WIDTH-1:0] calib_po_stage2_tap_cnt; + reg [6*DQS_WIDTH-1:0] calib_po_stage3_tap_cnt; + reg [3*DQS_WIDTH-1:0] calib_po_coarse_tap_cnt; + reg [6*DQS_WIDTH-1:0] calib_pi_stage2_tap_cnt; + reg [5*DQS_WIDTH-1:0] calib_idelay_tap_cnt; + reg [11:0] calib_device_temp; + wire [127:0] dbg_skip_cal; + + //***************************************************************************** + // Assertions to check correctness of parameter values + //***************************************************************************** + // synthesis translate_off + initial + begin + if (RANKS == 0) begin + $display ("Error: Invalid RANKS parameter. Must be 1 or greater"); + $finish; + end + if (phy_ctl_full == 1'b1) begin + $display ("Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode"); + $finish; + end + end + // synthesis translate_on + + //*************************************************************************** + // Debug + //*************************************************************************** + reg if_empty_reg; + reg pi_stg2_en_reg; + + assign prbs_rdlvl_done = (SIM_CAL_OPTION == "FAST_CAL")? rdlvl_stg1_done : prbs_rdlvl_done_complex; + + assign dbg_pi_phaselock_start = pi_phaselock_start; + assign dbg_pi_dqsfound_start = pi_dqs_found_start; + assign dbg_pi_dqsfound_done = pi_dqs_found_done; + assign dbg_wrcal_start = wrcal_start; + assign dbg_wrcal_done = wrcal_done; + + // Unused for now - use these as needed to bring up lower level signals + //assign dbg_calib_top = dbg_ocd_lim; + assign dbg_calib_top[0] = pi_stg2_en_reg ; + assign dbg_calib_top[1] = if_empty_reg ; + assign dbg_calib_top[3] = coarse_dec_err; + assign dbg_calib_top[4] = calib_tap_inc_start; + assign dbg_calib_top[5] = calib_tap_inc_done; + assign dbg_calib_top[6+:63] = dbg_skip_cal; + + always @ (posedge clk) begin + if_empty_reg <= #TCQ phy_if_empty; + pi_stg2_en_reg <= #TCQ pi_en_stg2_f; + end + + // Write Level and write calibration debug observation ports + assign dbg_wrlvl_start = wrlvl_start; + assign dbg_wrlvl_done = wrlvl_done; + assign dbg_wrlvl_err = wrlvl_err; + + // Read Level debug observation ports + assign dbg_rdlvl_start = {mpr_rdlvl_start, rdlvl_stg1_start}; + assign dbg_rdlvl_done = {mpr_rdlvl_done, rdlvl_stg1_done}; + assign dbg_rdlvl_err = {mpr_rdlvl_err, rdlvl_err}; + + assign dbg_oclkdelay_calib_done = oclkdelay_calib_done; + assign dbg_oclkdelay_calib_start = oclkdelay_calib_start; + + //*************************************************************************** + // Write leveling dependent signals + //*************************************************************************** + + assign wrcal_resume_w = (WRLVL == "ON") ? wrcal_pat_resume : 1'b0; + assign wrlvl_done_w = (WRLVL == "ON") ? wrlvl_done : 1'b1; + assign ck_addr_cmd_delay_done = (WRLVL == "ON") ? po_ck_addr_cmd_delay_done : + (po_ck_addr_cmd_delay_done + && pi_fine_dly_dec_done) ; + +generate + if((WRLVL == "ON") && (BYPASS_COMPLEX_OCAL=="FALSE")) begin: complex_oclk_calib + assign complex_oclkdelay_calib_start_w = complex_oclkdelay_calib_start; + assign complex_oclkdelay_calib_done_w = complex_oclkdelay_calib_done; + assign complex_ocal_rd_victim_sel_w = complex_ocal_rd_victim_sel; + assign complex_wrlvl_final_w = complex_wrlvl_final; + end else begin: bypass_complex_ocal + assign complex_oclkdelay_calib_start_w = 1'b0; + assign complex_oclkdelay_calib_done_w = prbs_rdlvl_done; + assign complex_ocal_rd_victim_sel_w = 'd0; + assign complex_wrlvl_final_w = 1'b0; + end +endgenerate + + + generate + genvar i; + for (i = 0; i <= 2; i = i+1) begin : bankwise_signal + + assign po_sel_stg2stg3[i] = ((ck_addr_cmd_delay_done && ~oclkdelay_calib_done && mpr_rdlvl_done) ? po_stg23_sel : + (complex_oclkdelay_calib_start_w&&~complex_oclkdelay_calib_done_w? po_stg23_sel : 1'b0 ) + // (~oclkdelay_center_calib_done? ocal_ctr_po_stg23_sel:1'b0)) + ) || calib_po_sel_stg2stg3 || dbg_po_f_stg23_sel_r; + + assign po_stg2_c_incdec[i] = cmd_po_stg2_c_incdec || + cmd_po_stg2_incdec_ddr2_c || + calib_po_c_inc || + dqs_wl_po_stg2_c_incdec; + + assign po_en_stg2_c[i] = cmd_po_en_stg2_c || + cmd_po_en_stg2_ddr2_c || + calib_po_c_en || + dqs_wl_po_en_stg2_c; + + assign po_stg2_f_incdec[i] = dqs_po_stg2_f_incdec || + cmd_po_stg2_f_incdec || + ck_po_stg2_f_indec || + po_stg23_incdec || + calib_po_f_incdec || + // complex_po_stg23_incdec || + // ocal_ctr_po_stg23_incdec || + dbg_po_f_inc_r; + + assign po_en_stg2_f[i] = dqs_po_en_stg2_f || + cmd_po_en_stg2_f || + ck_po_stg2_f_en || + po_en_stg23 || + calib_po_f_en || + // complex_po_en_stg23 || + // ocal_ctr_po_en_stg23 || + dbg_po_f_en_r; + + end + endgenerate + + assign pi_stg2_f_incdec = (calib_pi_f_incdec | dbg_pi_f_inc_r | rdlvl_pi_stg2_f_incdec | prbs_pi_stg2_f_incdec | tempmon_pi_f_inc_r); + assign pi_en_stg2_f = (calib_pi_f_en | dbg_pi_f_en_r | rdlvl_pi_stg2_f_en | prbs_pi_stg2_f_en | tempmon_pi_f_en_r); + + assign idelay_ce = (idelay_ce_r2 | calib_idelay_ce); + assign idelay_inc = (idelay_inc_r2 | calib_idelay_inc); + + assign po_counter_load_en = 1'b0; + + assign complex_oclkdelay_calib_cnt = oclkdelay_calib_cnt; + assign complex_oclk_calib_resume = oclk_calib_resume; + assign complex_ocal_ref_req = oclk_prech_req; + + +// Added single stage flop to meet timing + always @(posedge clk) begin + if (SKIP_CALIB == "FALSE") + init_calib_complete <= calib_complete; + else + init_calib_complete <= tempmon_done_skip; + end + + assign calib_rd_data_offset_0 = rd_data_offset_ranks_mc_0; + assign calib_rd_data_offset_1 = rd_data_offset_ranks_mc_1; + assign calib_rd_data_offset_2 = rd_data_offset_ranks_mc_2; + + //*************************************************************************** + // Hard PHY signals + //*************************************************************************** + + assign pi_phase_locked_err = phase_locked_err; + assign pi_dqsfound_err = pi_dqs_found_err; + assign wrcal_err = wrcal_pat_err; + assign rst_tg_mc = 1'b0; + +//Restart WRLVL after oclkdealy cal + always @ (posedge clk) + wrlvl_final_mux <= #TCQ complex_oclkdelay_calib_start_w? complex_wrlvl_final_w: wrlvl_final; + + + always @(posedge clk) + phy_if_reset <= #TCQ (phy_if_reset_w | mpr_end_if_reset | + reset_if | wrlvl_final_if_rst | calib_tap_end_if_reset); + + //*************************************************************************** + // Phaser_IN inc dec control for debug + //*************************************************************************** + + always @(posedge clk) begin + if (rst) begin + dbg_pi_f_inc_r <= #TCQ 1'b0; + dbg_pi_f_en_r <= #TCQ 1'b0; + dbg_sel_pi_incdec_r <= #TCQ 1'b0; + end else begin + dbg_pi_f_inc_r <= #TCQ dbg_pi_f_inc; + dbg_pi_f_en_r <= #TCQ (dbg_pi_f_inc | dbg_pi_f_dec); + dbg_sel_pi_incdec_r <= #TCQ dbg_sel_pi_incdec; + end + end + + //*************************************************************************** + // Phaser_OUT inc dec control for debug + //*************************************************************************** + + always @(posedge clk) begin + if (rst) begin + dbg_po_f_inc_r <= #TCQ 1'b0; + dbg_po_f_stg23_sel_r<= #TCQ 1'b0; + dbg_po_f_en_r <= #TCQ 1'b0; + dbg_sel_po_incdec_r <= #TCQ 1'b0; + end else begin + dbg_po_f_inc_r <= #TCQ dbg_po_f_inc; + dbg_po_f_stg23_sel_r<= #TCQ dbg_po_f_stg23_sel; + dbg_po_f_en_r <= #TCQ (dbg_po_f_inc | dbg_po_f_dec); + dbg_sel_po_incdec_r <= #TCQ dbg_sel_po_incdec; + end + end + + //*************************************************************************** + // Phaser_IN inc dec control for temperature tracking + //*************************************************************************** + + always @(posedge clk) begin + if (rst) begin + tempmon_pi_f_inc_r <= #TCQ 1'b0; + tempmon_pi_f_en_r <= #TCQ 1'b0; + tempmon_sel_pi_incdec_r <= #TCQ 1'b0; + end else begin + tempmon_pi_f_inc_r <= #TCQ tempmon_pi_f_inc; + tempmon_pi_f_en_r <= #TCQ (tempmon_pi_f_inc | tempmon_pi_f_dec); + tempmon_sel_pi_incdec_r <= #TCQ tempmon_sel_pi_incdec; + end + end + + //*************************************************************************** + // OCLKDELAY calibration signals + //*************************************************************************** + + // Minimum of 5 'clk' cycles required between assertion of po_sel_stg2stg3 + // and increment/decrement of Phaser_Out stage 3 delay + always @(posedge clk) begin + ck_addr_cmd_delay_done_r1 <= #TCQ ck_addr_cmd_delay_done; + ck_addr_cmd_delay_done_r2 <= #TCQ ck_addr_cmd_delay_done_r1; + ck_addr_cmd_delay_done_r3 <= #TCQ ck_addr_cmd_delay_done_r2; + ck_addr_cmd_delay_done_r4 <= #TCQ ck_addr_cmd_delay_done_r3; + ck_addr_cmd_delay_done_r5 <= #TCQ ck_addr_cmd_delay_done_r4; + ck_addr_cmd_delay_done_r6 <= #TCQ ck_addr_cmd_delay_done_r5; + end + + + + + //*************************************************************************** + // MUX select logic to select current byte undergoing calibration + // Use DQS_CAL_MAP to determine the correlation between the physical + // byte numbering, and the byte numbering within the hard PHY + //*************************************************************************** +generate + if (SKIP_CALIB == "TRUE") begin: gen_byte_sel_skip_calib + always @(posedge clk) begin + if (rst) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b0; + end else if (~skip_cal_po_pi_dec_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~ck_addr_cmd_delay_done) begin + ctl_lane_sel <= #TCQ ctl_lane_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~fine_adjust_done && rd_data_offset_cal_done) begin + if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ fine_adjust_lane_cnt; + calib_in_common <= #TCQ 1'b0; + end + end else if (~pi_calib_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~pi_dqs_found_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~calib_tap_inc_done) begin + byte_sel_cnt <= #TCQ calib_tap_inc_byte_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin + byte_sel_cnt <= #TCQ dbg_byte_sel; + calib_in_common <= #TCQ 1'b0; + end else if (tempmon_sel_pi_incdec) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end + end + end else if (tCK > 2500) begin: gen_byte_sel_div2 + + always @(posedge clk) begin + if (rst) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b0; + end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~ck_addr_cmd_delay_done) begin + ctl_lane_sel <= #TCQ ctl_lane_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~fine_adjust_done && rd_data_offset_cal_done) begin + if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ fine_adjust_lane_cnt; + calib_in_common <= #TCQ 1'b0; + end + end else if (~pi_calib_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~pi_dqs_found_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~wrlvl_done_w) begin + if (SIM_CAL_OPTION != "FAST_CAL") begin + byte_sel_cnt <= #TCQ po_stg2_wl_cnt; + calib_in_common <= #TCQ 1'b0; + end else begin + // Special case for FAST_CAL simulation only to ensure that + // calib_in_common isn't asserted too soon + if (!phy_ctl_rdy_dly) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b0; + end else begin + byte_sel_cnt <= #TCQ po_stg2_wl_cnt; + calib_in_common <= #TCQ 1'b1; + end + end + end else if (~mpr_rdlvl_done) begin + byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~oclkdelay_calib_done) begin + byte_sel_cnt <= #TCQ oclkdelay_calib_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~rdlvl_stg1_done && pi_calib_done) begin + if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin + byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; + calib_in_common <= #TCQ 1'b1; + end else begin + byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; + calib_in_common <= #TCQ 1'b0; + end + end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin + byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin + byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt; + calib_in_common <= #TCQ 1'b0; + end else if ((~wrcal_done) && (DRAM_TYPE == "DDR3")) begin + byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin + byte_sel_cnt <= #TCQ dbg_byte_sel; + calib_in_common <= #TCQ 1'b0; + end else if (tempmon_sel_pi_incdec) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end + end + end else begin: gen_byte_sel_div1 + + always @(posedge clk) begin + if (rst) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b0; + end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~ck_addr_cmd_delay_done) begin + ctl_lane_sel <= #TCQ ctl_lane_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~fine_adjust_done && rd_data_offset_cal_done) begin + if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ fine_adjust_lane_cnt; + calib_in_common <= #TCQ 1'b0; + end + end else if (~pi_calib_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~pi_dqs_found_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~wrlvl_done_w) begin + if (SIM_CAL_OPTION != "FAST_CAL") begin + byte_sel_cnt <= #TCQ po_stg2_wl_cnt; + calib_in_common <= #TCQ 1'b0; + end else begin + // Special case for FAST_CAL simulation only to ensure that + // calib_in_common isn't asserted too soon + if (!phy_ctl_rdy_dly) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b0; + end else begin + byte_sel_cnt <= #TCQ po_stg2_wl_cnt; + calib_in_common <= #TCQ 1'b1; + end + end + end else if (~mpr_rdlvl_done) begin + byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~oclkdelay_calib_done) begin + byte_sel_cnt <= #TCQ oclkdelay_calib_cnt; + calib_in_common <= #TCQ 1'b0; + end else if ((~wrcal_done)&& (DRAM_TYPE == "DDR3")) begin + byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~rdlvl_stg1_done && pi_calib_done) begin + if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin + byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; + calib_in_common <= #TCQ 1'b1; + end else begin + byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; + calib_in_common <= #TCQ 1'b0; + end + end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin + byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin + byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin + byte_sel_cnt <= #TCQ dbg_byte_sel; + calib_in_common <= #TCQ 1'b0; + end else if (tempmon_sel_pi_incdec) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end + end + + end +endgenerate + + // verilint STARC-2.2.3.3 off + always @(posedge clk) begin + if (rst || (calib_complete && ~ (dbg_sel_pi_incdec_r|dbg_sel_po_incdec_r|tempmon_sel_pi_incdec) )) begin + calib_sel <= #TCQ 6'b000100; + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done) || ~skip_cal_po_pi_dec_done) begin + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; + calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + if (~dqs_po_dec_done && (WRLVL != "ON")) + //if (~dqs_po_dec_done && ((SIM_CAL_OPTION == "FAST_CAL") ||(WRLVL != "ON"))) + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}}; + else + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + end else if (~ck_addr_cmd_delay_done || (~fine_adjust_done && rd_data_offset_cal_done)) begin + if(WRLVL =="ON") begin + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ CTL_BYTE_LANE[(ctl_lane_sel*2)+:2]; + calib_sel[5:3] <= #TCQ CTL_BANK; + if (|pi_rst_stg1_cal) begin + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + end else begin + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; + calib_zero_inputs[1*CTL_BANK] <= #TCQ 1'b0; + end + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + end else begin // if (WRLVL =="ON") + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; + calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + if(~ck_addr_cmd_delay_done) + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + else + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}}; + end // else: !if(WRLVL =="ON") + end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == "FAST_CAL")) begin + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; + calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + end else if (~rdlvl_stg1_done && (SIM_CAL_OPTION == "FAST_CAL") && + rdlvl_assrt_common) begin + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; + calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + end else if (tempmon_sel_pi_incdec) begin + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; + calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + end else begin + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; + calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + if (~calib_in_common) begin + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; + calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0; + end else + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + end + end + // verilint STARC-2.2.3.3 on + // Logic to reset IN_FIFO flags to account for the possibility that + // one or more PHASER_IN's have not correctly found the DQS preamble + // If this happens, we can still complete read leveling, but the # of + // words written into the IN_FIFO's may be an odd #, so that if the + // IN_FIFO is used in 2:1 mode ("8:4 mode"), there may be a "half" word + // of data left that can only be flushed out by reseting the IN_FIFO + always @(posedge clk) begin + rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done; + prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done; + reset_if_r1 <= #TCQ reset_if; + reset_if_r2 <= #TCQ reset_if_r1; + reset_if_r3 <= #TCQ reset_if_r2; + reset_if_r4 <= #TCQ reset_if_r3; + reset_if_r5 <= #TCQ reset_if_r4; + reset_if_r6 <= #TCQ reset_if_r5; + reset_if_r7 <= #TCQ reset_if_r6; + reset_if_r8 <= #TCQ reset_if_r7; + reset_if_r9 <= #TCQ reset_if_r8; + end + + always @(posedge clk) begin + if (rst || reset_if_r9) + reset_if <= #TCQ 1'b0; + else if ((rdlvl_stg1_done && ~rdlvl_stg1_done_r1) || + (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) + reset_if <= #TCQ 1'b1; + end + + assign phy_if_empty_def = 1'b0; + + // DQ IDELAY tap inc and ce signals registered to control calib_in_common + // signal during read leveling in FAST_CAL mode. The calib_in_common signal + // is only asserted for IDELAY tap increments not Phaser_IN tap increments + // in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load + // inputs are used. + always @(posedge clk) begin + if (rst) begin + idelay_ce_r1 <= #TCQ 1'b0; + idelay_ce_r2 <= #TCQ 1'b0; + idelay_inc_r1 <= #TCQ 1'b0; + idelay_inc_r2 <= #TCQ 1'b0; + end else begin + idelay_ce_r1 <= #TCQ idelay_ce_int; + idelay_ce_r2 <= #TCQ idelay_ce_r1; + idelay_inc_r1 <= #TCQ idelay_inc_int; + idelay_inc_r2 <= #TCQ idelay_inc_r1; + end + end + + //*************************************************************************** + // Delay all Outputs using Phaser_Out fine taps + //*************************************************************************** + + assign init_wrcal_complete = 1'b0; + + //*************************************************************************** + // PRBS Generator for Read Leveling Stage 1 - read window detection and + // DQS Centering + //*************************************************************************** + + // Assign initial seed (used for 1st data word in 8-burst sequence); use alternating 1/0 pat + assign prbs_seed = 64'h9966aa559966aa55; + + // A single PRBS generator + // writes 64-bits every 4to1 fabric clock cycle and + // write 32-bits every 2to1 fabric clock cycle + // used for complex read leveling and complex oclkdealy calib + mig_7series_v4_0_ddr_prbs_gen # + ( + .TCQ (TCQ), + .PRBS_WIDTH (2*8*nCK_PER_CLK), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .VCCO_PAT_EN (VCCO_PAT_EN), + .VCCAUX_PAT_EN (VCCAUX_PAT_EN), + .ISI_PAT_EN (ISI_PAT_EN), + .FIXED_VICTIM (FIXED_VICTIM) + ) + u_ddr_prbs_gen + (.prbs_ignore_first_byte (prbs_ignore_first_byte), + .prbs_ignore_last_bytes (prbs_ignore_last_bytes), + .clk_i (clk), + .clk_en_i (prbs_gen_clk_en | prbs_gen_oclk_clk_en), + .rst_i (rst), + .prbs_o (prbs_out), + .prbs_seed_i (prbs_seed), + .phy_if_empty (phy_if_empty), + .prbs_rdlvl_start (prbs_rdlvl_start), + .prbs_rdlvl_done (prbs_rdlvl_done), + .complex_wr_done (complex_wr_done), + .victim_sel (victim_sel), + .byte_cnt (victim_byte_cnt), + .dbg_prbs_gen (), + .reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr) + ); + + +// PRBS data slice that decides the Rise0, Fall0, Rise1, Fall1, +// Rise2, Fall2, Rise3, Fall3 data + generate + if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4 + assign prbs_o = prbs_out; + /*assign prbs_rise0 = prbs_out[7:0]; + assign prbs_fall0 = prbs_out[15:8]; + assign prbs_rise1 = prbs_out[23:16]; + assign prbs_fall1 = prbs_out[31:24]; + assign prbs_rise2 = prbs_out[39:32]; + assign prbs_fall2 = prbs_out[47:40]; + assign prbs_rise3 = prbs_out[55:48]; + assign prbs_fall3 = prbs_out[63:56]; + assign prbs_o = {prbs_fall3, prbs_rise3, prbs_fall2, prbs_rise2, + prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/ + end else begin :gen_ck_per_clk2 + assign prbs_o = prbs_out[4*DQ_WIDTH-1:0]; + /*assign prbs_rise0 = prbs_out[7:0]; + assign prbs_fall0 = prbs_out[15:8]; + assign prbs_rise1 = prbs_out[23:16]; + assign prbs_fall1 = prbs_out[31:24]; + assign prbs_o = {prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/ + end + endgenerate + + + //*************************************************************************** + // Initialization / Master PHY state logic (overall control during memory + // init, timing leveling) + //*************************************************************************** + + mig_7series_v4_0_ddr_phy_init # + ( + .tCK (tCK), + .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .CLK_PERIOD (CLK_PERIOD), + .DRAM_TYPE (DRAM_TYPE), + .PRBS_WIDTH (PRBS_WIDTH), + .BANK_WIDTH (BANK_WIDTH), + .CA_MIRROR (CA_MIRROR), + .COL_WIDTH (COL_WIDTH), + .nCS_PER_RANK (nCS_PER_RANK), + .DQ_WIDTH (DQ_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .ROW_WIDTH (ROW_WIDTH), + .CS_WIDTH (CS_WIDTH), + .RANKS (RANKS), + .CKE_WIDTH (CKE_WIDTH), + .CALIB_ROW_ADD (CALIB_ROW_ADD), + .CALIB_COL_ADD (CALIB_COL_ADD), + .CALIB_BA_ADD (CALIB_BA_ADD), + .AL (AL), + .BURST_MODE (BURST_MODE), + .BURST_TYPE (BURST_TYPE), + .nCL (nCL), + .nCWL (nCWL), + .tRFC (tRFC), + .REFRESH_TIMER (REFRESH_TIMER), + .REFRESH_TIMER_WIDTH (REFRESH_TIMER_WIDTH), + .OUTPUT_DRV (OUTPUT_DRV), + .REG_CTRL (REG_CTRL), + .ADDR_CMD_MODE (ADDR_CMD_MODE), + .RTT_NOM (RTT_NOM), + .RTT_WR (RTT_WR), + .WRLVL (WRLVL), + .USE_ODT_PORT (USE_ODT_PORT), + .DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE), + .nSLOTS (nSLOTS), + .SIM_INIT_OPTION (SIM_INIT_OPTION), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .CKE_ODT_AUX (CKE_ODT_AUX), + .PRE_REV3ES (PRE_REV3ES), + .TEST_AL (TEST_AL), + .FIXED_VICTIM (FIXED_VICTIM), + .BYPASS_COMPLEX_OCAL(BYPASS_COMPLEX_OCAL), + .SKIP_CALIB (SKIP_CALIB) + ) + u_ddr_phy_init + ( + .clk (clk), + .rst (rst), + .prbs_o (prbs_o), + .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), + .delay_incdec_done (ck_addr_cmd_delay_done), + .pi_phase_locked_all (pi_phase_locked_all), + .pi_phaselock_start (pi_phaselock_start), + .pi_phase_locked_err (phase_locked_err), + .pi_calib_done (pi_calib_done), + .phy_if_empty (phy_if_empty), + .phy_ctl_ready (phy_ctl_ready), + .phy_ctl_full (phy_ctl_full), + .phy_cmd_full (phy_cmd_full), + .phy_data_full (phy_data_full), + .calib_ctl_wren (calib_ctl_wren), + .calib_cmd_wren (calib_cmd_wren), + .calib_wrdata_en (calib_wrdata_en), + .calib_seq (calib_seq), + .calib_aux_out (calib_aux_out), + .calib_rank_cnt (calib_rank_cnt), + .calib_cas_slot (calib_cas_slot), + .calib_data_offset_0 (calib_data_offset_0), + .calib_data_offset_1 (calib_data_offset_1), + .calib_data_offset_2 (calib_data_offset_2), + .calib_cmd (calib_cmd), + .calib_cke (calib_cke), + .calib_odt (calib_odt), + .write_calib (write_calib), + .read_calib (read_calib), + .wrlvl_done (wrlvl_done), + .wrlvl_rank_done (wrlvl_rank_done), + .wrlvl_byte_done (wrlvl_byte_done), + .wrlvl_byte_redo (wrlvl_byte_redo), + .wrlvl_final (wrlvl_final_mux), + .wrlvl_final_if_rst (wrlvl_final_if_rst), + .oclkdelay_calib_start (oclkdelay_calib_start), + .oclkdelay_calib_done (oclkdelay_calib_done), + .oclk_prech_req (oclk_prech_req), + .oclk_calib_resume (oclk_calib_resume), + .lim_wr_req (lim2init_write_request), + .lim_done (lim_done), + .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), + .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done_w), + .complex_oclk_calib_resume (complex_oclk_calib_resume), + .complex_oclkdelay_calib_cnt (complex_oclkdelay_calib_cnt), + .complex_sample_cnt_inc_ocal (complex_sample_cnt_inc_ocal), + .complex_ocal_num_samples_inc (complex_ocal_num_samples_inc), + .complex_ocal_num_samples_done_r (complex_ocal_num_samples_done_r), + .complex_ocal_reset_rd_addr (complex_ocal_reset_rd_addr), + .complex_ocal_ref_req (complex_ocal_ref_req), + .complex_ocal_ref_done (complex_ocal_ref_done), + .done_dqs_tap_inc (done_dqs_tap_inc), + .wl_sm_start (wl_sm_start), + .wr_lvl_start (wrlvl_start), + .slot_0_present (slot_0_present), + .slot_1_present (slot_1_present), + .mpr_rdlvl_done (mpr_rdlvl_done), + .mpr_rdlvl_start (mpr_rdlvl_start), + .mpr_last_byte_done (mpr_last_byte_done), + .mpr_rnk_done (mpr_rnk_done), + .mpr_end_if_reset (mpr_end_if_reset), + .rdlvl_stg1_done (rdlvl_stg1_done), + .rdlvl_stg1_rank_done (rdlvl_stg1_rank_done), + .rdlvl_stg1_start (rdlvl_stg1_start), + .rdlvl_prech_req (rdlvl_prech_req), + .rdlvl_last_byte_done (rdlvl_last_byte_done), + .prbs_rdlvl_start (prbs_rdlvl_start), + .complex_wr_done (complex_wr_done), + .prbs_rdlvl_done (prbs_rdlvl_done), + .prbs_last_byte_done (prbs_last_byte_done), + .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req), + .complex_victim_inc (complex_victim_inc), + .rd_victim_sel (rd_victim_sel), + .complex_ocal_rd_victim_sel (complex_ocal_rd_victim_sel), + .pi_stg2_prbs_rdlvl_cnt(pi_stg2_prbs_rdlvl_cnt), + .victim_sel (victim_sel), + .victim_byte_cnt (victim_byte_cnt), + .prbs_gen_clk_en (prbs_gen_clk_en), + .prbs_gen_oclk_clk_en (prbs_gen_oclk_clk_en), + .complex_sample_cnt_inc(complex_sample_cnt_inc), + .pi_dqs_found_start (pi_dqs_found_start), + .dqsfound_retry (dqsfound_retry), + .dqs_found_prech_req (dqs_found_prech_req), + .pi_dqs_found_rank_done(pi_dqs_found_rank_done), + .pi_dqs_found_done (pi_dqs_found_done), + .detect_pi_found_dqs (detect_pi_found_dqs), + .rd_data_offset_0 (rd_data_offset_0), + .rd_data_offset_1 (rd_data_offset_1), + .rd_data_offset_2 (rd_data_offset_2), + .rd_data_offset_ranks_0(rd_data_offset_ranks_0), + .rd_data_offset_ranks_1(rd_data_offset_ranks_1), + .rd_data_offset_ranks_2(rd_data_offset_ranks_2), + .wrcal_start (wrcal_start), + .wrcal_rd_wait (wrcal_rd_wait), + .wrcal_prech_req (wrcal_prech_req), + .wrcal_resume (wrcal_resume_w), + .wrcal_read_req (wrcal_read_req), + .wrcal_act_req (wrcal_act_req), + .wrcal_sanity_chk (wrcal_sanity_chk), + .temp_wrcal_done (temp_wrcal_done), + .wrcal_sanity_chk_done (wrcal_sanity_chk_done), + .tg_timer_done (tg_timer_done), + .no_rst_tg_mc (no_rst_tg_mc), + .wrcal_done (wrcal_done), + .prech_done (prech_done), + .calib_writes (calib_writes), + .init_calib_complete (calib_complete), + .phy_address (phy_address), + .phy_bank (phy_bank), + .phy_cas_n (phy_cas_n), + .phy_cs_n (phy_cs_n), + .phy_ras_n (phy_ras_n), + .phy_reset_n (phy_reset_n), + .phy_we_n (phy_we_n), + .phy_wrdata (phy_wrdata), + .phy_rddata_en (phy_rddata_en), + .phy_rddata_valid (phy_rddata_valid), + .dbg_phy_init (dbg_phy_init), + .reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr), + .oclkdelay_center_calib_start (oclkdelay_center_calib_start), + .oclk_center_write_resume (oclk_center_write_resume), + .oclkdelay_center_calib_done (oclkdelay_center_calib_done), + .rdlvl_pi_incdec (rdlvl_pi_incdec), + .complex_act_start (complex_act_start), + .complex_pi_incdec_done (complex_pi_incdec_done), + .complex_init_pi_dec_done (complex_init_pi_dec_done), + .num_samples_done_r (num_samples_done_r), + .calib_tap_inc_start (calib_tap_inc_start), + .calib_tap_end_if_reset (calib_tap_end_if_reset), + .calib_tap_inc_done (calib_tap_inc_done) + ); + + + //***************************************************************** + // Write Calibration + //***************************************************************** + + mig_7series_v4_0_ddr_phy_wrcal # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .CLK_PERIOD (CLK_PERIOD), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .SIM_CAL_OPTION (SIM_CAL_OPTION) + ) + u_ddr_phy_wrcal + ( + .clk (clk), + .rst (rst), + .wrcal_start (wrcal_start), + .wrcal_rd_wait (wrcal_rd_wait), + .wrcal_sanity_chk (wrcal_sanity_chk), + .dqsfound_retry_done (pi_dqs_found_done), + .dqsfound_retry (dqsfound_retry), + .wrcal_read_req (wrcal_read_req), + .wrcal_act_req (wrcal_act_req), + .phy_rddata_en (phy_rddata_en), + .wrcal_done (wrcal_done), + .wrcal_pat_err (wrcal_pat_err), + .wrcal_prech_req (wrcal_prech_req), + .temp_wrcal_done (temp_wrcal_done), + .wrcal_sanity_chk_done (wrcal_sanity_chk_done), + .prech_done (prech_done), + .rd_data (phy_rddata), + .wrcal_pat_resume (wrcal_pat_resume), + .po_stg2_wrcal_cnt (po_stg2_wrcal_cnt), + .phy_if_reset (phy_if_reset_w), + .wl_po_coarse_cnt (wl_po_coarse_cnt), + .wl_po_fine_cnt (wl_po_fine_cnt), + .wrlvl_byte_redo (wrlvl_byte_redo), + .wrlvl_byte_done (wrlvl_byte_done), + .early1_data (early1_data), + .early2_data (early2_data), + .idelay_ld (idelay_ld), + .dbg_phy_wrcal (dbg_phy_wrcal), + .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), + .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt) + ); + + + + //*************************************************************************** + // Write-leveling calibration logic + //*************************************************************************** + + generate + if ((WRLVL == "ON") && (SKIP_CALIB == "FALSE")) begin: mb_wrlvl_inst + + mig_7series_v4_0_ddr_phy_wrlvl # + ( + .TCQ (TCQ), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .RANKS (1), + .CLK_PERIOD (CLK_PERIOD), + .nCK_PER_CLK (nCK_PER_CLK), + .SIM_CAL_OPTION (SIM_CAL_OPTION) + ) + u_ddr_phy_wrlvl + ( + .clk (clk), + .rst (rst), + .phy_ctl_ready (phy_ctl_ready), + .wr_level_start (wrlvl_start), + .wl_sm_start (wl_sm_start), + .wrlvl_byte_redo (wrlvl_byte_redo), + .wrcal_cnt (po_stg2_wrcal_cnt), + .early1_data (early1_data), + .early2_data (early2_data), + .wrlvl_final (wrlvl_final_mux), + .oclkdelay_calib_cnt (oclkdelay_calib_cnt), + .wrlvl_byte_done (wrlvl_byte_done), + .oclkdelay_calib_done (oclkdelay_calib_done), + .rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]), + .dqs_po_dec_done (dqs_po_dec_done), + .phy_ctl_rdy_dly (phy_ctl_rdy_dly), + .wr_level_done (wrlvl_done), + .wrlvl_rank_done (wrlvl_rank_done), + .done_dqs_tap_inc (done_dqs_tap_inc), + .dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec), + .dqs_po_en_stg2_f (dqs_po_en_stg2_f), + .dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec), + .dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c), + .po_counter_read_val (po_counter_read_val), + .po_stg2_wl_cnt (po_stg2_wl_cnt), + .wrlvl_err (wrlvl_err), + .wl_po_coarse_cnt (wl_po_coarse_cnt), + .wl_po_fine_cnt (wl_po_fine_cnt), + .dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl), + .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), + .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), + .dbg_dqs_count (), + .dbg_wl_state (), + .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), + .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), + .dbg_phy_wrlvl (dbg_phy_wrlvl) + ); + + + mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay # + ( + .TCQ (TCQ), + .tCK (tCK), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .N_CTL_LANES (N_CTL_LANES), + .SIM_CAL_OPTION(SIM_CAL_OPTION) + ) + u_ddr_phy_ck_addr_cmd_delay + ( + .clk (clk), + .rst (rst), + .cmd_delay_start (dqs_po_dec_done & pi_fine_dly_dec_done), + .ctl_lane_cnt (ctl_lane_cnt), + .po_stg2_f_incdec (cmd_po_stg2_f_incdec), + .po_en_stg2_f (cmd_po_en_stg2_f), + .po_stg2_c_incdec (cmd_po_stg2_c_incdec), + .po_en_stg2_c (cmd_po_en_stg2_c), + .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done) + ); + + assign cmd_po_stg2_incdec_ddr2_c = 1'b0; + assign cmd_po_en_stg2_ddr2_c = 1'b0; + + end else if ((WRLVL == "ON") && (SKIP_CALIB == "TRUE")) begin: wrlvl_on_skip_calib + + mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay # + ( + .TCQ (TCQ), + .tCK (tCK), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .N_CTL_LANES (N_CTL_LANES), + .SIM_CAL_OPTION(SIM_CAL_OPTION) + ) + u_ddr_phy_ck_addr_cmd_delay + ( + .clk (clk), + .rst (rst), + .cmd_delay_start (skip_cal_po_pi_dec_done), + .ctl_lane_cnt (ctl_lane_cnt), + .po_stg2_f_incdec (cmd_po_stg2_f_incdec), + .po_en_stg2_f (cmd_po_en_stg2_f), + .po_stg2_c_incdec (cmd_po_stg2_c_incdec), + .po_en_stg2_c (cmd_po_en_stg2_c), + .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done) + ); + + assign dqs_po_dec_done = 1'b1; + assign wrlvl_byte_done = 1'b1; + assign wrlvl_rank_done = 1'b1; + assign phy_ctl_rdy_dly = 1'b1; + assign done_dqs_tap_inc = 1'b1; + assign po_stg2_wl_cnt = 'h0; + assign wl_po_coarse_cnt = 'h0; + assign wl_po_fine_cnt = 'h0; + assign dbg_tap_cnt_during_wrlvl = 'h0; + assign dbg_wl_edge_detect_valid = 'h0; + assign dbg_rd_data_edge_detect = 'h0; + assign dbg_wrlvl_fine_tap_cnt = 'h0; + assign dbg_wrlvl_coarse_tap_cnt = 'h0; + assign dbg_phy_wrlvl = 'h0; + + assign wrlvl_done = 1'b1; + assign wrlvl_err = 1'b0; + assign dqs_po_stg2_f_incdec = 1'b0; + assign dqs_po_en_stg2_f = 1'b0; + assign dqs_wl_po_en_stg2_c = 1'b0; + assign dqs_wl_po_stg2_c_incdec = 1'b0; + + assign cmd_po_stg2_incdec_ddr2_c = 1'b0; + assign cmd_po_en_stg2_ddr2_c = 1'b0; + + end else begin: mb_wrlvl_off + + mig_7series_v4_0_ddr_phy_wrlvl_off_delay # + ( + .TCQ (TCQ), + .tCK (tCK), + .nCK_PER_CLK (nCK_PER_CLK), + .CLK_PERIOD (CLK_PERIOD), + .PO_INITIAL_DLY(60), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .N_CTL_LANES (N_CTL_LANES) + ) + u_phy_wrlvl_off_delay + ( + .clk (clk), + .rst (rst), + .pi_fine_dly_dec_done (pi_fine_dly_dec_done), + .cmd_delay_start (phy_ctl_ready), + .ctl_lane_cnt (ctl_lane_cnt), + .po_s2_incdec_f (cmd_po_stg2_f_incdec), + .po_en_s2_f (cmd_po_en_stg2_f), + .po_s2_incdec_c (cmd_po_stg2_incdec_ddr2_c), + .po_en_s2_c (cmd_po_en_stg2_ddr2_c), + .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done), + .po_dec_done (dqs_po_dec_done), + .phy_ctl_rdy_dly (phy_ctl_rdy_dly) + ); + + assign wrlvl_byte_done = 1'b1; + assign wrlvl_rank_done = 1'b1; + assign po_stg2_wl_cnt = 'h0; + assign wl_po_coarse_cnt = 'h0; + assign wl_po_fine_cnt = 'h0; + assign dbg_tap_cnt_during_wrlvl = 'h0; + assign dbg_wl_edge_detect_valid = 'h0; + assign dbg_rd_data_edge_detect = 'h0; + assign dbg_wrlvl_fine_tap_cnt = 'h0; + assign dbg_wrlvl_coarse_tap_cnt = 'h0; + assign dbg_phy_wrlvl = 'h0; + + assign wrlvl_done = 1'b1; + assign wrlvl_err = 1'b0; + assign dqs_po_stg2_f_incdec = 1'b0; + assign dqs_po_en_stg2_f = 1'b0; + assign dqs_wl_po_en_stg2_c = 1'b0; + assign cmd_po_stg2_c_incdec = 1'b0; + assign dqs_wl_po_stg2_c_incdec = 1'b0; + assign cmd_po_en_stg2_c = 1'b0; + + end + endgenerate + + generate + if((WRLVL == "ON") && (OCAL_EN == "ON")) begin: oclk_calib + + localparam SAMPCNTRWIDTH = 17; + localparam SAMPLES = (SIM_CAL_OPTION=="NONE") ? 512 : 4; //MG from 2048 + localparam TAPCNTRWIDTH = clogb2(TAPSPERKCLK); + localparam MMCM_SAMP_WAIT = (SIM_CAL_OPTION=="NONE") ? 256 : 10; + localparam OCAL_SIMPLE_SCAN_SAMPS = (SIM_CAL_OPTION=="NONE") ? 512 : 1; //MG from 2048 + localparam POC_PCT_SAMPS_SOLID = 80; + localparam SCAN_PCT_SAMPS_SOLID = 95; + + mig_7series_v4_0_ddr_phy_oclkdelay_cal # + (/*AUTOINSTPARAM*/ + // Parameters + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + //.DRAM_TYPE (DRAM_TYPE), + .DRAM_WIDTH (DRAM_WIDTH), + //.OCAL_EN (OCAL_EN), + .OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS), + .PCT_SAMPS_SOLID (POC_PCT_SAMPS_SOLID), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), + .SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID), + .SAMPCNTRWIDTH (SAMPCNTRWIDTH), + .SAMPLES (SAMPLES), + .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL) + //.tCK (tCK) + ) + u_ddr_phy_oclkdelay_cal + (/*AUTOINST*/ + // Outputs + .prbs_ignore_first_byte (prbs_ignore_first_byte), + .prbs_ignore_last_bytes (prbs_ignore_last_bytes), + .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done), + .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data[16*DRAM_WIDTH-1:0]), + .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal[255:0]), + .lim2init_write_request (lim2init_write_request), + .lim_done (lim_done), + .oclk_calib_resume (oclk_calib_resume), + .oclk_prech_req (oclk_prech_req), + .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), + .oclkdelay_calib_done (oclkdelay_calib_done), + .po_en_stg23 (po_en_stg23), + .po_stg23_incdec (po_stg23_incdec), + .po_stg23_sel (po_stg23_sel), + .psen (psen), + .psincdec (psincdec), + .wrlvl_final (wrlvl_final), + .rd_victim_sel (complex_ocal_rd_victim_sel), + .ocal_num_samples_done_r (complex_ocal_num_samples_done_r), + .complex_wrlvl_final (complex_wrlvl_final), + .poc_error (poc_error), + // Inputs + .clk (clk), + .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start_w), + .metaQ (pd_out), + //.oclk_init_delay_start (oclk_init_delay_start), + .po_counter_read_val (po_counter_read_val), + .oclkdelay_calib_start (oclkdelay_calib_start), + .oclkdelay_init_val (oclkdelay_init_val[5:0]), + .poc_sample_pd (poc_sample_pd), + .phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]), + .phy_rddata_en (phy_rddata_en), + .prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]), + .prech_done (prech_done), + .psdone (psdone), + .rst (rst), + .wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0]), + .ocal_num_samples_inc (complex_ocal_num_samples_inc), + .oclkdelay_center_calib_start (oclkdelay_center_calib_start), + .oclk_center_write_resume (oclk_center_write_resume), + .oclkdelay_center_calib_done (oclkdelay_center_calib_done), + .dbg_ocd_lim (dbg_ocd_lim), + .dbg_poc (dbg_poc[1023:0]) ); + + end else begin : oclk_calib_disabled + + assign wrlvl_final = 'b0; + assign psen = 'b0; + assign psincdec = 'b0; + assign po_stg23_sel = 'b0; + assign po_stg23_incdec = 'b0; + assign po_en_stg23 = 'b0; + assign oclkdelay_calib_cnt = 'b0; + assign oclk_prech_req = 'b0; + assign oclk_calib_resume = 'b0; + assign oclkdelay_calib_done = 1'b1; + assign dbg_phy_oclkdelay_cal = 'h0; + assign dbg_oclkdelay_rd_data = 'h0; + + end + endgenerate + //*************************************************************************** + // Read data-offset calibration required for Phaser_In + //*************************************************************************** + + generate + if(DQSFOUND_CAL == "RIGHT") begin: dqsfind_calib_right + mig_7series_v4_0_ddr_phy_dqs_found_cal # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .nCL (nCL), + .AL (AL), + .nCWL (nCWL), + //.RANKS (RANKS), + .RANKS (1), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .REG_CTRL (REG_CTRL), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .DRAM_TYPE (DRAM_TYPE), + .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL), + .N_CTL_LANES (DQS_FOUND_N_CTL_LANES), + .HIGHEST_LANE (HIGHEST_LANE), + .HIGHEST_BANK (HIGHEST_BANK), + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4) + ) + u_ddr_phy_dqs_found_cal + ( + .clk (clk), + .rst (rst), + .pi_dqs_found_start (pi_dqs_found_start), + .dqsfound_retry (dqsfound_retry), + .detect_pi_found_dqs (detect_pi_found_dqs), + .prech_done (prech_done), + .pi_dqs_found_lanes (pi_dqs_found_lanes), + .pi_rst_stg1_cal (pi_rst_stg1_cal), + .rd_data_offset_0 (rd_data_offset_0), + .rd_data_offset_1 (rd_data_offset_1), + .rd_data_offset_2 (rd_data_offset_2), + .pi_dqs_found_rank_done (pi_dqs_found_rank_done), + .pi_dqs_found_done (pi_dqs_found_done), + .dqsfound_retry_done (dqsfound_retry_done), + .dqs_found_prech_req (dqs_found_prech_req), + .pi_dqs_found_err (pi_dqs_found_err), + .rd_data_offset_ranks_0 (rd_data_offset_ranks_0), + .rd_data_offset_ranks_1 (rd_data_offset_ranks_1), + .rd_data_offset_ranks_2 (rd_data_offset_ranks_2), + .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0), + .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1), + .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2), + .po_counter_read_val (po_counter_read_val), + .rd_data_offset_cal_done (rd_data_offset_cal_done), + .fine_adjust_done (fine_adjust_done), + .fine_adjust_lane_cnt (fine_adjust_lane_cnt), + .ck_po_stg2_f_indec (ck_po_stg2_f_indec), + .ck_po_stg2_f_en (ck_po_stg2_f_en), + .dbg_dqs_found_cal (dbg_dqs_found_cal) + ); + end else begin: dqsfind_calib_left + mig_7series_v4_0_ddr_phy_dqs_found_cal_hr # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .nCL (nCL), + .AL (AL), + .nCWL (nCWL), + //.RANKS (RANKS), + .RANKS (1), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .REG_CTRL (REG_CTRL), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .DRAM_TYPE (DRAM_TYPE), + .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL), + .N_CTL_LANES (DQS_FOUND_N_CTL_LANES), + .HIGHEST_LANE (HIGHEST_LANE), + .HIGHEST_BANK (HIGHEST_BANK), + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4) + ) + u_ddr_phy_dqs_found_cal_hr + ( + .clk (clk), + .rst (rst), + .pi_dqs_found_start (pi_dqs_found_start), + .dqsfound_retry (dqsfound_retry), + .detect_pi_found_dqs (detect_pi_found_dqs), + .prech_done (prech_done), + .pi_dqs_found_lanes (pi_dqs_found_lanes), + .pi_rst_stg1_cal (pi_rst_stg1_cal), + .rd_data_offset_0 (rd_data_offset_0), + .rd_data_offset_1 (rd_data_offset_1), + .rd_data_offset_2 (rd_data_offset_2), + .pi_dqs_found_rank_done (pi_dqs_found_rank_done), + .pi_dqs_found_done (pi_dqs_found_done), + .dqsfound_retry_done (dqsfound_retry_done), + .dqs_found_prech_req (dqs_found_prech_req), + .pi_dqs_found_err (pi_dqs_found_err), + .rd_data_offset_ranks_0 (rd_data_offset_ranks_0), + .rd_data_offset_ranks_1 (rd_data_offset_ranks_1), + .rd_data_offset_ranks_2 (rd_data_offset_ranks_2), + .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0), + .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1), + .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2), + .po_counter_read_val (po_counter_read_val), + .rd_data_offset_cal_done (rd_data_offset_cal_done), + .fine_adjust_done (fine_adjust_done), + .fine_adjust_lane_cnt (fine_adjust_lane_cnt), + .ck_po_stg2_f_indec (ck_po_stg2_f_indec), + .ck_po_stg2_f_en (ck_po_stg2_f_en), + .dbg_dqs_found_cal (dbg_dqs_found_cal) + ); + end + endgenerate + + //*************************************************************************** + // Read-leveling calibration logic + //*************************************************************************** +generate +if (SKIP_CALIB == "FALSE") begin:ddr_phy_rdlvl_gen + mig_7series_v4_0_ddr_phy_rdlvl # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .CLK_PERIOD (CLK_PERIOD), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .RANKS (1), + .PER_BIT_DESKEW (PER_BIT_DESKEW), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .DEBUG_PORT (DEBUG_PORT), + .DRAM_TYPE (DRAM_TYPE), + .OCAL_EN (OCAL_EN), + .IDELAY_ADJ (IDELAY_ADJ), + .PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + u_ddr_phy_rdlvl + ( + .clk (clk), + .rst (rst), + .mpr_rdlvl_done (mpr_rdlvl_done), + .mpr_rdlvl_start (mpr_rdlvl_start), + .mpr_last_byte_done (mpr_last_byte_done), + .mpr_rnk_done (mpr_rnk_done), + .rdlvl_stg1_start (rdlvl_stg1_start), + .rdlvl_stg1_done (rdlvl_stg1_done), + .rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done), + .rdlvl_stg1_err (rdlvl_stg1_err), + .mpr_rdlvl_err (mpr_rdlvl_err), + .rdlvl_err (rdlvl_err), + .rdlvl_prech_req (rdlvl_prech_req), + .rdlvl_last_byte_done (rdlvl_last_byte_done), + .rdlvl_assrt_common (rdlvl_assrt_common), + .prech_done (prech_done), + .phy_if_empty (phy_if_empty), + .idelaye2_init_val (idelaye2_init_val), + .rd_data (phy_rddata), + .pi_en_stg2_f (rdlvl_pi_stg2_f_en), + .pi_stg2_f_incdec (rdlvl_pi_stg2_f_incdec), + .pi_stg2_load (pi_stg2_load), + .pi_stg2_reg_l (pi_stg2_reg_l), + .dqs_po_dec_done (dqs_po_dec_done), + .pi_counter_read_val (pi_counter_read_val), + .pi_fine_dly_dec_done (pi_fine_dly_dec_done), + .idelay_ce (idelay_ce_int), + .idelay_inc (idelay_inc_int), + .idelay_ld (idelay_ld), + .wrcal_cnt (po_stg2_wrcal_cnt), + .pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt), + .dlyval_dq (dlyval_dq), + .rdlvl_pi_incdec (rdlvl_pi_incdec), + .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), + .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), + .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), + .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), + .dbg_idel_up_all (dbg_idel_up_all), + .dbg_idel_down_all (dbg_idel_down_all), + .dbg_idel_up_cpt (dbg_idel_up_cpt), + .dbg_idel_down_cpt (dbg_idel_down_cpt), + .dbg_sel_idel_cpt (dbg_sel_idel_cpt), + .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), + .dbg_phy_rdlvl (dbg_phy_rdlvl) + ); +end else begin:ddr_phy_rdlvl_off + + assign mpr_rdlvl_done = 1'b1; + assign mpr_last_byte_done = 1'b1; + assign mpr_rnk_done = 1'b1; + assign rdlvl_stg1_done = 1'b1; + assign rdlvl_stg1_rank_done = 1'b1; + assign rdlvl_last_byte_done = 1'b1; + assign pi_fine_dly_dec_done = 1'b1; + assign rdlvl_prech_req = 1'b0; + assign rdlvl_stg1_err = 1'b0; + assign mpr_rdlvl_err = 1'b0; + assign rdlvl_err = 1'b0; + assign rdlvl_assrt_common = 1'b0; + assign rdlvl_pi_stg2_f_en = 1'b0; + assign rdlvl_pi_stg2_f_incdec = 1'b0; + assign pi_stg2_rdlvl_cnt = 'h0; + assign idelay_ce_int = 1'b0; + assign idelay_inc_int = 1'b0; + assign rdlvl_pi_incdec = 1'b0; + assign dbg_phy_rdlvl = 'h0; + assign dbg_cpt_first_edge_cnt = 'h0; + assign dbg_cpt_second_edge_cnt = 'h0; + assign dbg_cpt_tap_cnt = 'h0; + assign dbg_dq_idelay_tap_cnt = 'h0; + +end +endgenerate + +generate +if((DRAM_TYPE == "DDR3") && (nCK_PER_CLK == 4) && (BYPASS_COMPLEX_RDLVL=="FALSE")) begin:ddr_phy_prbs_rdlvl_gen + mig_7series_v4_0_ddr_phy_prbs_rdlvl # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .RANKS (1), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .PRBS_WIDTH (PRBS_WIDTH), + .FIXED_VICTIM (FIXED_VICTIM), + .FINE_PER_BIT (FINE_PER_BIT), + .CENTER_COMP_MODE (CENTER_COMP_MODE), + .PI_VAL_ADJ (PI_VAL_ADJ) + ) + u_ddr_phy_prbs_rdlvl + ( + .clk (clk), + .rst (rst), + .prbs_rdlvl_start (prbs_rdlvl_start), + .prbs_rdlvl_done (prbs_rdlvl_done_complex), + .prbs_last_byte_done (prbs_last_byte_done), + .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req), + .complex_sample_cnt_inc (complex_sample_cnt_inc), + .prech_done (prech_done), + .phy_if_empty (phy_if_empty), + .rd_data (phy_rddata), + .compare_data (prbs_o), + .pi_counter_read_val (pi_counter_read_val), + .pi_en_stg2_f (prbs_pi_stg2_f_en), + .pi_stg2_f_incdec (prbs_pi_stg2_f_incdec), + .dbg_prbs_rdlvl (dbg_prbs_rdlvl), + .pi_stg2_prbs_rdlvl_cnt (pi_stg2_prbs_rdlvl_cnt), + .prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r), + .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps), + .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps), + .rd_victim_sel (rd_victim_sel), + .complex_victim_inc (complex_victim_inc), + .reset_rd_addr (reset_rd_addr), + .fine_delay_incdec_pb (fine_delay_incdec_pb), + .fine_delay_sel (fine_delay_sel), + .complex_act_start (complex_act_start), + .num_samples_done_r (num_samples_done_r), + .complex_pi_incdec_done (complex_pi_incdec_done), + .complex_init_pi_dec_done (complex_init_pi_dec_done) + ); +end else begin:ddr_phy_prbs_rdlvl_off + + assign prbs_rdlvl_done_complex = rdlvl_stg1_done ; + //assign prbs_last_byte_done = rdlvl_stg1_rank_done ; + assign prbs_last_byte_done = rdlvl_stg1_done; + assign reset_rd_addr = 1'b0; + assign prbs_rdlvl_prech_req = 1'b0 ; + assign prbs_pi_stg2_f_en = 1'b0 ; + assign prbs_pi_stg2_f_incdec = 1'b0 ; + assign pi_stg2_prbs_rdlvl_cnt = 'b0 ; + assign dbg_prbs_rdlvl = 'h0 ; + assign prbs_final_dqs_tap_cnt_r = {(6*DQS_WIDTH*RANKS){1'b0}}; + assign dbg_prbs_first_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}}; + assign dbg_prbs_second_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}}; + assign complex_pi_incdec_done = 'b0; + assign complex_init_pi_dec_done = 'b1; + assign num_samples_done_r = 'b0; +end +endgenerate + + //*************************************************************************** + // Inc/Dec Phaser_Out, Phaser_In, and IDELAY taps to match calibration values + //*************************************************************************** + + generate + if (SKIP_CALIB == "TRUE") begin: gen_skip_calib_tap + + // Generate request to get calibration tap values per byte + always @(posedge clk) begin + if (rst) + calib_tap_req <= #TCQ 1'b0; + else if (phy_ctl_ready) + calib_tap_req <= #TCQ 1'b1; + end + + + // Store calibration values to registers + always @(posedge clk) begin + if (rst) begin + calib_po_coarse_tap_cnt <= #TCQ 'd0; + calib_po_stage3_tap_cnt <= #TCQ 'd0; + calib_po_stage2_tap_cnt <= #TCQ 'd0; + calib_pi_stage2_tap_cnt <= #TCQ 'd0; + calib_idelay_tap_cnt <= #TCQ 'd0; + calib_device_temp <= #TCQ 'd0; + end else if (calib_tap_load) begin + case (calib_tap_addr[2:0]) + 3'b000: + calib_po_coarse_tap_cnt[3*calib_tap_addr[6:3]+:3] <= #TCQ calib_tap_val[2:0]; + 3'b001: + calib_po_stage3_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0]; + 3'b010: + calib_po_stage2_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0]; + 3'b011: + calib_pi_stage2_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0]; + 3'b100: + calib_idelay_tap_cnt[5*calib_tap_addr[6:3]+:5] <= #TCQ calib_tap_val[4:0]; + 3'b110: + if (&calib_tap_addr[6:3]) + calib_device_temp[7:0] <= #TCQ calib_tap_val[7:0]; + 3'b111: + if (&calib_tap_addr[6:3]) + calib_device_temp[11:8] <= #TCQ calib_tap_val[3:0]; + default: + calib_po_coarse_tap_cnt[3*calib_tap_addr[6:3]+:3] <= #TCQ calib_tap_val[2:0]; + endcase + end + end + + + mig_7series_v4_0_ddr_skip_calib_tap # + ( + .TCQ (TCQ), + .DQS_WIDTH (DQS_WIDTH) + ) + u_ddr_skip_calib_tap + ( + .rst (rst), + .clk (clk), + .phy_ctl_ready (phy_ctl_ready), + .load_done (calib_tap_load_done), + .calib_tap_inc_start (calib_tap_inc_start), + .calib_tap_inc_done (calib_tap_inc_done), + .calib_tap_inc_byte_cnt (calib_tap_inc_byte_cnt), + .calib_po_stage2_tap_cnt (calib_po_stage2_tap_cnt), + .calib_po_stage3_tap_cnt (calib_po_stage3_tap_cnt), + .calib_po_coarse_tap_cnt (calib_po_coarse_tap_cnt), + .calib_pi_stage2_tap_cnt (calib_pi_stage2_tap_cnt), + .calib_idelay_tap_cnt (calib_idelay_tap_cnt), + .po_counter_read_val (po_counter_read_val), + .pi_counter_read_val (pi_counter_read_val), + .calib_po_f_en (calib_po_f_en), + .calib_po_f_incdec (calib_po_f_incdec), + .calib_po_sel_stg2stg3 (calib_po_sel_stg2stg3), + .calib_po_c_en (calib_po_c_en), + .calib_po_c_inc (calib_po_c_inc), + .calib_pi_f_en (calib_pi_f_en), + .calib_pi_f_incdec (calib_pi_f_incdec), + .calib_idelay_ce (calib_idelay_ce), + .calib_idelay_inc (calib_idelay_inc), + .skip_cal_po_pi_dec_done (skip_cal_po_pi_dec_done), + .coarse_dec_err (coarse_dec_err), + .dbg_skip_cal (dbg_skip_cal) + ); + + // Generate tempmon_sample_en pulses for temperature adjustment + reg [8:0] samp_en_cnt; + + always @ (posedge clk) begin + if (rst || tempmon_done_skip || (samp_en_cnt == 'd0)) + samp_en_cnt <= #TCQ 'd267; + else if (calib_complete && (samp_en_cnt > 'd0)) + samp_en_cnt <= #TCQ samp_en_cnt - 1; + end + + always @ (posedge clk) begin + if (rst || tempmon_done_skip) + skip_cal_tempmon_samp_en <= #TCQ 1'b0; + else if (samp_en_cnt == 'd260) + skip_cal_tempmon_samp_en <= #TCQ 1'b1; + else + skip_cal_tempmon_samp_en <= #TCQ 1'b0; + end + + + + end else begin: skip_calib_tap_off + assign calib_po_f_en = 1'b0; + assign calib_po_f_incdec = 1'b0; + assign calib_po_sel_stg2stg3 = 1'b0; + assign calib_po_c_en = 1'b0; + assign calib_po_c_inc = 1'b0; + assign calib_pi_f_en = 1'b0; + assign calib_pi_f_incdec = 1'b0; + assign calib_idelay_ce = 1'b0; + assign calib_idelay_inc = 1'b0; + assign calib_tap_inc_done = 1'b0; + assign calib_tap_inc_byte_cnt = 'd0; + assign skip_cal_po_pi_dec_done = 1'b1; + + always @(posedge clk) begin + calib_tap_req <= #TCQ 1'b0; + calib_device_temp <= #TCQ 'd0; + skip_cal_tempmon_samp_en <= #TCQ 1'b0; + end + +end +endgenerate + + //*************************************************************************** + // Temperature induced PI tap adjustment logic + //*************************************************************************** + + mig_7series_v4_0_ddr_phy_tempmon # + ( + .SKIP_CALIB (SKIP_CALIB), + .TCQ (TCQ) + ) + ddr_phy_tempmon_0 + ( + .rst (rst), + .clk (clk), + .calib_complete (calib_complete), + .tempmon_pi_f_inc (tempmon_pi_f_inc), + .tempmon_pi_f_dec (tempmon_pi_f_dec), + .tempmon_sel_pi_incdec (tempmon_sel_pi_incdec), + .device_temp (device_temp), + .calib_device_temp (calib_device_temp), + .tempmon_sample_en (tempmon_sample_en | skip_cal_tempmon_samp_en), + .tempmon_done_skip (tempmon_done_skip) + ); + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_if_post_fifo.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_if_post_fifo.v new file mode 100644 index 0000000..28ae0a7 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_if_post_fifo.v @@ -0,0 +1,212 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : mig_7series_v1_x_ddr_if_post_fifo.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Feb 08 2011 +// \___\/\___\ +// +//Device : 7 Series +//Design Name : DDR3 SDRAM +//Purpose : Extends the depth of a PHASER IN_FIFO up to 4 entries +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_0_ddr_if_post_fifo # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter DEPTH = 4, // # of entries + parameter WIDTH = 32 // data bus width + ) + ( + input clk, // clock + input rst, // synchronous reset + input [3:0] empty_in, + input rd_en_in, + input [WIDTH-1:0] d_in, // write data from controller + output empty_out, + output byte_rd_en, + output [WIDTH-1:0] d_out // write data to OUT_FIFO + ); + + // # of bits used to represent read/write pointers + localparam PTR_BITS + = (DEPTH == 2) ? 1 : + (((DEPTH == 3) || (DEPTH == 4)) ? 2 : 'bx); + + integer i; + + reg [WIDTH-1:0] mem[0:DEPTH-1]; + (* max_fanout = 40 *) reg [4:0] my_empty /* synthesis syn_maxfan = 3 */; + (* max_fanout = 40 *) reg [1:0] my_full /* synthesis syn_maxfan = 3 */; + reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */; + // Register duplication to reduce the fan out + (* KEEP = "TRUE" *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */; + reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */; + wire [WIDTH-1:0] mem_out; + (* max_fanout = 40 *) wire wr_en /* synthesis syn_maxfan = 10 */; + + task updt_ptrs; + input rd; + input wr; + reg [1:0] next_rd_ptr; + reg [1:0] next_wr_ptr; + begin + next_rd_ptr = (rd_ptr + 1'b1)%DEPTH; + next_wr_ptr = (wr_ptr + 1'b1)%DEPTH; + casez ({rd, wr, my_empty[1], my_full[1]}) + 4'b00zz: ; // No access, do nothing + 4'b0100: begin + // Write when neither empty, nor full; check for full + wr_ptr <= #TCQ next_wr_ptr; + my_full[0] <= #TCQ (next_wr_ptr == rd_ptr); + my_full[1] <= #TCQ (next_wr_ptr == rd_ptr); + //mem[wr_ptr] <= #TCQ d_in; + end + 4'b0110: begin + // Write when empty; no need to check for full + wr_ptr <= #TCQ next_wr_ptr; + my_empty <= #TCQ 5'b00000; + //mem[wr_ptr] <= #TCQ d_in; + end + 4'b1000: begin + // Read when neither empty, nor full; check for empty + rd_ptr <= #TCQ next_rd_ptr; + rd_ptr_timing <= #TCQ next_rd_ptr; + my_empty[0] <= #TCQ (next_rd_ptr == wr_ptr); + my_empty[1] <= #TCQ (next_rd_ptr == wr_ptr); + my_empty[2] <= #TCQ (next_rd_ptr == wr_ptr); + my_empty[3] <= #TCQ (next_rd_ptr == wr_ptr); + my_empty[4] <= #TCQ (next_rd_ptr == wr_ptr); + end + 4'b1001: begin + // Read when full; no need to check for empty + rd_ptr <= #TCQ next_rd_ptr; + rd_ptr_timing <= #TCQ next_rd_ptr; + my_full[0] <= #TCQ 1'b0; + my_full[1] <= #TCQ 1'b0; + end + 4'b1100, 4'b1101, 4'b1110: begin + // Read and write when empty, full, or neither empty/full; no need + // to check for empty or full conditions + rd_ptr <= #TCQ next_rd_ptr; + rd_ptr_timing <= #TCQ next_rd_ptr; + wr_ptr <= #TCQ next_wr_ptr; + //mem[wr_ptr] <= #TCQ d_in; + end + 4'b0101, 4'b1010: ; + // Read when empty, Write when full; Keep all pointers the same + // and don't change any of the flags (i.e. ignore the read/write). + // This might happen because a faulty DQS_FOUND calibration could + // result in excessive skew between when the various IN_FIFO's + // first become not empty. In this case, the data going to each + // post-FIFO/IN_FIFO should be read out and discarded + // synthesis translate_off + default: begin + // Covers any other cases, in particular for simulation if + // any signals are X's + $display("ERR %m @%t: Bad access: rd:%b,wr:%b,empty:%b,full:%b", + $time, rd, wr, my_empty[1], my_full[1]); + rd_ptr <= #TCQ 2'bxx; + rd_ptr_timing <= #TCQ 2'bxx; + wr_ptr <= #TCQ 2'bxx; + end + // synthesis translate_on + endcase + end + endtask + + + assign d_out = my_empty[4] ? d_in : mem_out;//mem[rd_ptr]; + // The combined IN_FIFO + post FIFO is only "empty" when both are empty + assign empty_out = empty_in[0] & my_empty[0]; + assign byte_rd_en = !empty_in[3] || !my_empty[3]; + + always @(posedge clk) + if (rst) begin + my_empty <= #TCQ 5'b11111; + my_full <= #TCQ 2'b00; + rd_ptr <= #TCQ 'b0; + rd_ptr_timing <= #TCQ 'b0; + wr_ptr <= #TCQ 'b0; + end else begin + // Special mode: If IN_FIFO has data, and controller is reading at + // the same time, then operate post-FIFO in "passthrough" mode (i.e. + // don't update any of the read/write pointers, and route IN_FIFO + // data to post-FIFO data) + if (my_empty[1] && !my_full[1] && rd_en_in && !empty_in[1]) ; + else + // Otherwise, we're writing to FIFO when IN_FIFO is not empty, + // and reading from the FIFO based on the rd_en_in signal (read + // enable from controller). The functino updt_ptrs should catch + // an illegal conditions. + updt_ptrs(rd_en_in, !empty_in[1]); + end + + + assign wr_en = (!empty_in[2] & ((!rd_en_in & !my_full[0]) | + (rd_en_in & !my_empty[2]))); + + + always @ (posedge clk) + begin + if (wr_en) + mem[wr_ptr] <= #TCQ d_in; + end + + assign mem_out = mem[rd_ptr_timing]; + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_mc_phy.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_mc_phy.v new file mode 100644 index 0000000..14b0f11 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_mc_phy.v @@ -0,0 +1,1804 @@ +/*********************************************************** +-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). A Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +// +// +// Owner: Gary Martin +// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $ +// $Author: gary $ +// $DateTime: 2010/05/11 18:05:17 $ +// $Change: 490882 $ +// Description: +// This verilog file is a parameterizable wrapper instantiating +// up to 5 memory banks of 4-lane phy primitives. There +// There are always 2 control banks leaving 18 lanes for data. +// +// History: +// Date Engineer Description +// 04/01/2010 G. Martin Initial Checkin. +// +//////////////////////////////////////////////////////////// +***********************************************************/ + + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_mc_phy + #( +// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0 + parameter BYTE_LANES_B0 = 4'b1111, + parameter BYTE_LANES_B1 = 4'b0000, + parameter BYTE_LANES_B2 = 4'b0000, + parameter BYTE_LANES_B3 = 4'b0000, + parameter BYTE_LANES_B4 = 4'b0000, + parameter DATA_CTL_B0 = 4'hc, + parameter DATA_CTL_B1 = 4'hf, + parameter DATA_CTL_B2 = 4'hf, + parameter DATA_CTL_B3 = 4'hf, + parameter DATA_CTL_B4 = 4'hf, + parameter RCLK_SELECT_BANK = 0, + parameter RCLK_SELECT_LANE = "B", + parameter RCLK_SELECT_EDGE = 4'b1111, + parameter GENERATE_DDR_CK_MAP = "0B", + parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002, + parameter USE_PRE_POST_FIFO = "TRUE", + parameter SYNTHESIS = "FALSE", + parameter PO_CTL_COARSE_BYPASS = "FALSE", + parameter PI_SEL_CLK_OFFSET = 6, + + parameter PHYCTL_CMD_FIFO = "FALSE", + parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio + +// common to all i/o banks + parameter PHY_FOUR_WINDOW_CLOCKS = 63, + parameter PHY_EVENTS_DELAY = 18, + parameter PHY_COUNT_EN = "TRUE", + parameter PHY_SYNC_MODE = "TRUE", + parameter PHY_DISABLE_SEQ_MATCH = "FALSE", + parameter MASTER_PHY_CTL = 0, +// common to instance 0 + parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff, + parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000, + parameter PHY_0_LANE_REMAP = 16'h3210, + parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE", + parameter PHY_0_IODELAY_GRP = "IODELAY_MIG", + parameter FPGA_SPEED_GRADE = 1, + parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" + parameter NUM_DDR_CK = 1, + parameter PHY_0_DATA_CTL = DATA_CTL_B0, + parameter PHY_0_CMD_OFFSET = 0, + parameter PHY_0_RD_CMD_OFFSET_0 = 0, + parameter PHY_0_RD_CMD_OFFSET_1 = 0, + parameter PHY_0_RD_CMD_OFFSET_2 = 0, + parameter PHY_0_RD_CMD_OFFSET_3 = 0, + parameter PHY_0_RD_DURATION_0 = 0, + parameter PHY_0_RD_DURATION_1 = 0, + parameter PHY_0_RD_DURATION_2 = 0, + parameter PHY_0_RD_DURATION_3 = 0, + parameter PHY_0_WR_CMD_OFFSET_0 = 0, + parameter PHY_0_WR_CMD_OFFSET_1 = 0, + parameter PHY_0_WR_CMD_OFFSET_2 = 0, + parameter PHY_0_WR_CMD_OFFSET_3 = 0, + parameter PHY_0_WR_DURATION_0 = 0, + parameter PHY_0_WR_DURATION_1 = 0, + parameter PHY_0_WR_DURATION_2 = 0, + parameter PHY_0_WR_DURATION_3 = 0, + parameter PHY_0_AO_WRLVL_EN = 0, + parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE) + parameter PHY_0_OF_ALMOST_FULL_VALUE = 1, + parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1, +// per lane parameters + parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE", + parameter PHY_0_A_PI_CLKOUT_DIV = 2, + parameter PHY_0_A_PO_CLKOUT_DIV = 2, + parameter PHY_0_A_BURST_MODE = "TRUE", + parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF", + parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF", + parameter PHY_0_A_PO_OCLK_DELAY = 25, + parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, + parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, + parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, + parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE", + parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4", + parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4", + parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED", + parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED", + parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE", + parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00, + parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, + +// common to instance 1 + parameter PHY_1_BITLANES = PHY_0_BITLANES, + parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000, + parameter PHY_1_LANE_REMAP = 16'h3210, + parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE", + parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP, + parameter PHY_1_DATA_CTL = DATA_CTL_B1, + parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET, + parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0, + parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1, + parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2, + parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3, + parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0, + parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1, + parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2, + parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3, + parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0, + parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1, + parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2, + parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3, + parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0, + parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1, + parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2, + parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3, + parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN, + parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE) + parameter PHY_1_OF_ALMOST_FULL_VALUE = 1, + parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1, +// per lane parameters + parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV, + parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV, + parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV, + parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE, + parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC, + parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC , + parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, + parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY, + parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY, + parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY, + parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV, + parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE, + parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + +// common to instance 2 + parameter PHY_2_BITLANES = PHY_0_BITLANES, + parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000, + parameter PHY_2_LANE_REMAP = 16'h3210, + parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE", + parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP, + parameter PHY_2_DATA_CTL = DATA_CTL_B2, + parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET, + parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0, + parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1, + parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2, + parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3, + parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0, + parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1, + parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2, + parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3, + parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0, + parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1, + parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2, + parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3, + parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0, + parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1, + parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2, + parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3, + parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN, + parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE) + parameter PHY_2_OF_ALMOST_FULL_VALUE = 1, + parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1, +// per lane parameters + parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV, + parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV , + parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV, + parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE , + parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC, + parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC, + parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE, + parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, + parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY, + parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY, + parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY, + parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV, + parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE", + parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"), + parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"), + parameter TCK = 2500, + +// local computational use, do not pass down + parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3]) + + (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3]) + , // must not delete comma for syntax + parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))), + parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) , + parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) , + parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) , + parameter HIGHEST_LANE_B3 = 0, + parameter HIGHEST_LANE_B4 = 0, + + parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))), + parameter LP_DDR_CK_WIDTH = 2, + parameter GENERATE_SIGNAL_SPLIT = "FALSE" + ,parameter CKE_ODT_AUX = "FALSE" + ,parameter PI_DIV2_INCDEC = "FALSE" + ) + ( + input rst, + input ddr_rst_in_n , + input phy_clk, + input clk_div2, + input freq_refclk, + input mem_refclk, + input mem_refclk_div4, + input pll_lock, + input sync_pulse, + input auxout_clk, + input idelayctrl_refclk, + input [HIGHEST_LANE*80-1:0] phy_dout, + input phy_cmd_wr_en, + input phy_data_wr_en, + input phy_rd_en, + input [31:0] phy_ctl_wd, + input [3:0] aux_in_1, + input [3:0] aux_in_2, + input [5:0] data_offset_1, + input [5:0] data_offset_2, + input phy_ctl_wr, + input if_rst, + input if_empty_def, + input cke_in, + input idelay_ce, + input idelay_ld, + input idelay_inc, + input phyGo, + input input_sink, + output if_a_empty, + output if_empty /* synthesis syn_maxfan = 3 */, + output if_empty_or, + output if_empty_and, + output of_ctl_a_full, + output of_data_a_full, + output of_ctl_full, + output of_data_full, + output pre_data_a_full, + output [HIGHEST_LANE*80-1:0] phy_din, + output phy_ctl_a_full, + output wire [3:0] phy_ctl_full, + output [HIGHEST_LANE*12-1:0] mem_dq_out, + output [HIGHEST_LANE*12-1:0] mem_dq_ts, + input [HIGHEST_LANE*10-1:0] mem_dq_in, + output [HIGHEST_LANE-1:0] mem_dqs_out, + output [HIGHEST_LANE-1:0] mem_dqs_ts, + input [HIGHEST_LANE-1:0] mem_dqs_in, + +(* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller + output phy_ctl_ready, // to fabric + output reg rst_out, // to memory + output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk, +// output rclk, + output mcGo, + output ref_dll_lock, +// calibration signals + input phy_write_calib, + input phy_read_calib, + input [5:0] calib_sel, + input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank + input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs + input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane + input calib_in_common, + input [2:0] po_fine_enable, + input [2:0] po_coarse_enable, + input [2:0] po_fine_inc, + input [2:0] po_coarse_inc, + input po_counter_load_en, + input [2:0] po_sel_fine_oclk_delay, + input [8:0] po_counter_load_val, + input po_counter_read_en, + output reg po_coarse_overflow, + output reg po_fine_overflow, + output reg [8:0] po_counter_read_val, + + + input [HIGHEST_BANK-1:0] pi_rst_dqs_find, + input pi_fine_enable, + input pi_fine_inc, + input pi_counter_load_en, + input pi_counter_read_en, + input [5:0] pi_counter_load_val, + output reg pi_fine_overflow, + output reg [5:0] pi_counter_read_val, + + output reg pi_phase_locked, + output pi_phase_locked_all, + output reg pi_dqs_found, + output pi_dqs_found_all, + output pi_dqs_found_any, + output [HIGHEST_LANE-1:0] pi_phase_locked_lanes, + output [HIGHEST_LANE-1:0] pi_dqs_found_lanes, + output reg pi_dqs_out_of_range, + input [29:0] fine_delay, + input fine_delay_sel + ); + + +wire [7:0] calib_zero_inputs_int ; +wire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ; + +//Added the temporary variable for concadination operation +wire [2:0] calib_sel_byte0 ; +wire [2:0] calib_sel_byte1 ; +wire [2:0] calib_sel_byte2 ; + +wire [4:0] po_coarse_overflow_w; +wire [4:0] po_fine_overflow_w; +wire [8:0] po_counter_read_val_w[4:0]; +wire [4:0] pi_fine_overflow_w; +wire [5:0] pi_counter_read_val_w[4:0]; +wire [4:0] pi_dqs_found_w; +wire [4:0] pi_dqs_found_all_w; +wire [4:0] pi_dqs_found_any_w; +wire [4:0] pi_dqs_out_of_range_w; +wire [4:0] pi_phase_locked_w; +wire [4:0] pi_phase_locked_all_w; +wire [4:0] rclk_w; +wire [HIGHEST_BANK-1:0] phy_ctl_ready_w; +wire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0]; +wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_; + + +wire [3:0] if_q0; +wire [3:0] if_q1; +wire [3:0] if_q2; +wire [3:0] if_q3; +wire [3:0] if_q4; +wire [7:0] if_q5; +wire [7:0] if_q6; +wire [3:0] if_q7; +wire [3:0] if_q8; +wire [3:0] if_q9; + +wire [31:0] _phy_ctl_wd; +wire [3:0] aux_in_[4:1]; +wire [3:0] rst_out_w; + +wire freq_refclk_split; +wire mem_refclk_split; +wire mem_refclk_div4_split; +wire sync_pulse_split; +wire phy_clk_split0; +wire phy_ctl_clk_split0; +wire [31:0] phy_ctl_wd_split0; +wire phy_ctl_wr_split0; +wire phy_ctl_clk_split1; +wire phy_clk_split1; +wire [31:0] phy_ctl_wd_split1; +wire phy_ctl_wr_split1; +wire [5:0] phy_data_offset_1_split1; +wire phy_ctl_clk_split2; +wire phy_clk_split2; +wire [31:0] phy_ctl_wd_split2; +wire phy_ctl_wr_split2; +wire [5:0] phy_data_offset_2_split2; +wire [HIGHEST_LANE*80-1:0] phy_dout_split0; +wire phy_cmd_wr_en_split0; +wire phy_data_wr_en_split0; +wire phy_rd_en_split0; +wire [HIGHEST_LANE*80-1:0] phy_dout_split1; +wire phy_cmd_wr_en_split1; +wire phy_data_wr_en_split1; +wire phy_rd_en_split1; +wire [HIGHEST_LANE*80-1:0] phy_dout_split2; +wire phy_cmd_wr_en_split2; +wire phy_data_wr_en_split2; +wire phy_rd_en_split2; + +wire phy_ctl_mstr_empty; +wire [HIGHEST_BANK-1:0] phy_ctl_empty; + +wire _phy_ctl_a_full_f; +wire _phy_ctl_a_empty_f; +wire _phy_ctl_full_f; +wire _phy_ctl_empty_f; +wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p; +wire [HIGHEST_BANK-1:0] _phy_ctl_full_p; +wire [HIGHEST_BANK-1:0] of_ctl_a_full_v; +wire [HIGHEST_BANK-1:0] of_ctl_full_v; +wire [HIGHEST_BANK-1:0] of_data_a_full_v; +wire [HIGHEST_BANK-1:0] of_data_full_v; +wire [HIGHEST_BANK-1:0] pre_data_a_full_v; +wire [HIGHEST_BANK-1:0] if_empty_v; +wire [HIGHEST_BANK-1:0] byte_rd_en_v; +wire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks; +wire [HIGHEST_BANK-1:0] if_empty_or_v; +wire [HIGHEST_BANK-1:0] if_empty_and_v; +wire [HIGHEST_BANK-1:0] if_a_empty_v; + +localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4"; +localparam IF_SYNCHRONOUS_MODE = "FALSE"; +localparam IF_SLOW_WR_CLK = "FALSE"; +localparam IF_SLOW_RD_CLK = "FALSE"; + +localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE"; +localparam RCLK_NEG_EDGE = 3'b000; +localparam RCLK_POS_EDGE = 3'b111; + +localparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF; +localparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF; +localparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF; + +// hi, lo positions for data offset field, MIG doesn't allow defines +localparam PC_DATA_OFFSET_RANGE_HI = 22; +localparam PC_DATA_OFFSET_RANGE_LO = 17; + +/* Phaser_In Output source coding table + "PHASE_REF" : 4'b0000; + "DELAYED_MEM_REF" : 4'b0101; + "DELAYED_PHASE_REF" : 4'b0011; + "DELAYED_REF" : 4'b0001; + "FREQ_REF" : 4'b1000; + "MEM_REF" : 4'b0010; +*/ + +localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF"; + + +localparam DDR_TCK = TCK; + +localparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1); +localparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0; +localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line +localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line +localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta + +/* +Intrinsic delay of Phaser In Stage 1 +@3300ps - 1.939ns - 58.8% +@2500ps - 1.657ns - 66.3% +@1875ps - 1.263ns - 67.4% +@1500ps - 1.021ns - 68.1% +@1250ps - 0.868ns - 69.4% +@1072ps - 0.752ns - 70.1% +@938ps - 0.667ns - 71.1% +*/ + +// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0 +// Fraction of a full DDR_TCK period +localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 : + ((DDR_TCK < 1005) ? 0.667 : + (DDR_TCK < 1160) ? 0.752 : + (DDR_TCK < 1375) ? 0.868 : + (DDR_TCK < 1685) ? 1.021 : + (DDR_TCK < 2185) ? 1.263 : + (DDR_TCK < 2900) ? 1.657 : + (DDR_TCK < 3100) ? 1.771 : 1.939)*1000; +/* +Intrinsic delay of Phaser In Stage 2 +@3300ps - 0.912ns - 27.6% - single tap - 13ps +@3000ps - 0.848ns - 28.3% - single tap - 11ps +@2500ps - 1.264ns - 50.6% - single tap - 19ps +@1875ps - 1.000ns - 53.3% - single tap - 15ps +@1500ps - 0.848ns - 56.5% - single tap - 11ps +@1250ps - 0.736ns - 58.9% - single tap - 9ps +@1072ps - 0.664ns - 61.9% - single tap - 8ps +@938ps - 0.608ns - 64.8% - single tap - 7ps +*/ +// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps) +localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor +/* +Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1 +@3300ps - 1.294ns - 39.2% +@2500ps - 1.294ns - 51.8% +@1875ps - 1.030ns - 54.9% +@1500ps - 0.878ns - 58.5% +@1250ps - 0.766ns - 61.3% +@1072ps - 0.694ns - 64.7% +@938ps - 0.638ns - 68.0% + +Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0 +@3300ps - 2.084ns - 63.2% - single tap - 20ps +@2500ps - 2.084ns - 81.9% - single tap - 19ps +@1875ps - 1.676ns - 89.4% - single tap - 15ps +@1500ps - 1.444ns - 96.3% - single tap - 11ps +@1250ps - 1.276ns - 102.1% - single tap - 9ps +@1072ps - 1.164ns - 108.6% - single tap - 8ps +@938ps - 1.076ns - 114.7% - single tap - 7ps +*/ +// Fraction of a full DDR_TCK period +localparam real PO_STG1_INTRINSIC_DELAY = 0; +localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor +localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor +localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY + + (PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY); + +// When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can +// go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this, +// a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments +// to the stage 2 delay can be made after reset is removed. + +localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line +localparam real PO_CIRC_BUF_META_ZONE = 200.0; +localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0; +localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK; +// If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold +// If it is not more than the threshold than we must push the delay after the clock period plus a guardband. + +//A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated. +localparam integer PO_CIRC_BUF_DELAY = 60; + +//localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 : +// (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE : +// (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE; + +localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line +localparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE; +localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY; +localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY; +localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE); +localparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi +// The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path +// of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the +// oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment +// is within the range of the stage 2 delay line in the Phaser_In. +localparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY); +localparam integer PO_DELAY_INT = PO_DELAY; +localparam PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK); + +// if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is +// if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge. +// note that in this case PI_OFFSET is negative so invert before subtracting. +localparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0 + ? PI_OFFSET + : ((-PI_OFFSET) < DDR_TCK/2) ? + (DDR_TCK/2 - (- PI_OFFSET)) : + (DDR_TCK - (- PI_OFFSET)) ; + +localparam real PI_STG2_DELAY = + (PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ? + PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND); +localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE; + +localparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE)); + +localparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ; +localparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ; +localparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ; + +localparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ; + +localparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ; + +localparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ; + + +localparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC; + +localparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC; + +localparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC; + +wire _phy_clk; + +wire [2:0] mcGo_w; +wire [HIGHEST_BANK-1:0] ref_dll_lock_w; +reg [15:0] mcGo_r; + + +assign ref_dll_lock = & ref_dll_lock_w; + +initial begin + if ( SYNTHESIS == "FALSE" ) begin + $display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1); + $display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1); + $display("%m : HIGHEST_BANK = %d", HIGHEST_BANK); + + $display("%m : FREQ_REF_PERIOD = %0.2f ", FREQ_REF_PERIOD); + $display("%m : DDR_TCK = %0d ", DDR_TCK); + $display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE); + $display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY); + $display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET); + $display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE); + $display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY); + $display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY); + $display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY); + $display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY); + $display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY); + $display("%m : PO_DELAY = %0.2f ", PO_DELAY); + $display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY); + $display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY); + + $display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY); + $display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY); + $display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY); + $display("%m : PI_MAX_STG2_DELAY = %0.2f ", PI_MAX_STG2_DELAY); + $display("%m : PI_OFFSET = %0.2f ", PI_OFFSET); + if ( PI_OFFSET < 0) $display("%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used."); + $display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY); + $display("%m :PI_STG2_DELAY_CAND = %0.2f ",PI_STG2_DELAY_CAND); + $display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY); + $display("%m : RCLK_SELECT_EDGE = %0b ", LP_RCLK_SELECT_EDGE); + end // SYNTHESIS + if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display("WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY); +end + + assign sync_pulse_split = sync_pulse; + assign mem_refclk_split = mem_refclk; + assign freq_refclk_split = freq_refclk; + assign mem_refclk_div4_split = mem_refclk_div4; + assign phy_ctl_clk_split0 = _phy_clk; + assign phy_ctl_wd_split0 = phy_ctl_wd; + assign phy_ctl_wr_split0 = phy_ctl_wr; + assign phy_clk_split0 = phy_clk; + assign phy_cmd_wr_en_split0 = phy_cmd_wr_en; + assign phy_data_wr_en_split0 = phy_data_wr_en; + assign phy_rd_en_split0 = phy_rd_en; + assign phy_dout_split0 = phy_dout; + assign phy_ctl_clk_split1 = phy_clk; + assign phy_ctl_wd_split1 = phy_ctl_wd; + assign phy_data_offset_1_split1 = data_offset_1; + assign phy_ctl_wr_split1 = phy_ctl_wr; + assign phy_clk_split1 = phy_clk; + assign phy_cmd_wr_en_split1 = phy_cmd_wr_en; + assign phy_data_wr_en_split1 = phy_data_wr_en; + assign phy_rd_en_split1 = phy_rd_en; + assign phy_dout_split1 = phy_dout; + assign phy_ctl_clk_split2 = phy_clk; + assign phy_ctl_wd_split2 = phy_ctl_wd; + assign phy_data_offset_2_split2 = data_offset_2; + assign phy_ctl_wr_split2 = phy_ctl_wr; + assign phy_clk_split2 = phy_clk; + assign phy_cmd_wr_en_split2 = phy_cmd_wr_en; + assign phy_data_wr_en_split2 = phy_data_wr_en; + assign phy_rd_en_split2 = phy_rd_en; + assign phy_dout_split2 = phy_dout; + +// these wires are needed to coerce correct synthesis +// the synthesizer did not always see the widths of the +// parameters as 4 bits. + +wire [3:0] blb0 = BYTE_LANES_B0; +wire [3:0] blb1 = BYTE_LANES_B1; +wire [3:0] blb2 = BYTE_LANES_B2; + +wire [3:0] dcb0 = DATA_CTL_B0; +wire [3:0] dcb1 = DATA_CTL_B1; +wire [3:0] dcb2 = DATA_CTL_B2; + +assign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0}); +assign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0}); +assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0]; +assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs}; +//Added to remove concadination in the instantiation +assign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ; +assign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ; +assign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ; + +assign calib_zero_lanes_int = calib_zero_lanes; + +assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0]; + +assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL]; + +assign of_ctl_a_full = |of_ctl_a_full_v; +assign of_ctl_full = |of_ctl_full_v; +assign of_data_a_full = |of_data_a_full_v; +assign of_data_full = |of_data_full_v; +assign pre_data_a_full= |pre_data_a_full_v; +// if if_empty_def == 1, empty is asserted only if all are empty; +// this allows the user to detect a skewed fifo depth and self-clear +// if desired. It avoids a reset to clear the flags. +assign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v; +assign if_empty_or = |if_empty_or_v; +assign if_empty_and = &if_empty_and_v; +assign if_a_empty = |if_a_empty_v; + + +generate +genvar i; +for (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen + case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff) + 16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11; + 16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11; + 16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11; + 16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11; + 16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11; + 16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11; + 16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11; + 16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11; + 16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11; + 16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11; + 16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11; + 16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11; + default : initial $display("ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) ", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff )); + endcase +end +endgenerate + +//assign rclk = rclk_w[RCLK_SELECT_BANK]; + +reg rst_auxout; +reg rst_auxout_r; +reg rst_auxout_rr; + +always @(posedge auxout_clk or posedge rst) begin + if ( rst) begin + rst_auxout_r <= #(1) 1'b1; + rst_auxout_rr <= #(1) 1'b1; + end + else begin + rst_auxout_r <= #(1) rst; + rst_auxout_rr <= #(1) rst_auxout_r; + end +end +if ( LP_RCLK_SELECT_EDGE[0]) begin + always @(posedge auxout_clk or posedge rst) begin + if ( rst) begin + rst_auxout <= #(1) 1'b1; + end + else begin + rst_auxout <= #(1) rst_auxout_rr; + end + end +end +else begin + always @(negedge auxout_clk or posedge rst) begin + if ( rst) begin + rst_auxout <= #(1) 1'b1; + end + else begin + rst_auxout <= #(1) rst_auxout_rr; + end + end +end + +localparam L_RESET_SELECT_BANK = + (BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK; + +always @(*) begin + rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n; +end + +always @(posedge phy_clk) begin + if ( rst) + mcGo_r <= #(1) 0; + else + mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w; +end + +assign mcGo = mcGo_r[15]; + + +generate + + +// this is an optional 1 clock delay to add latency to the phy_control programming path + +if (PHYCTL_CMD_FIFO == "TRUE") begin : cmd_fifo_soft + reg [31:0] phy_wd_reg = 0; + reg [3:0] aux_in1_reg = 0; + reg [3:0] aux_in2_reg = 0; + reg sfifo_ready = 0; + assign _phy_ctl_wd = phy_wd_reg; + assign aux_in_[1] = aux_in1_reg; + assign aux_in_[2] = aux_in2_reg; + assign phy_ctl_a_full = |_phy_ctl_a_full_p; + assign phy_ctl_full[0] = |_phy_ctl_full_p; + assign phy_ctl_full[1] = |_phy_ctl_full_p; + assign phy_ctl_full[2] = |_phy_ctl_full_p; + assign phy_ctl_full[3] = |_phy_ctl_full_p; + assign _phy_clk = phy_clk; + + always @(posedge phy_clk) begin + phy_wd_reg <= #1 phy_ctl_wd; + aux_in1_reg <= #1 aux_in_1; + aux_in2_reg <= #1 aux_in_2; + sfifo_ready <= #1 phy_ctl_wr; + end + +end + +else if (PHYCTL_CMD_FIFO == "FALSE") begin + assign _phy_ctl_wd = phy_ctl_wd; + assign aux_in_[1] = aux_in_1; + assign aux_in_[2] = aux_in_2; + assign phy_ctl_a_full = |_phy_ctl_a_full_p; + assign phy_ctl_full[0] = |_phy_ctl_full_p; + assign phy_ctl_full[3:1] = 3'b000; + assign _phy_clk = phy_clk; + +end +endgenerate + + +// instance of four-lane phy + +generate + +if (HIGHEST_BANK == 3) begin : banks_3 + assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]}; + assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]}; + assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]}; +end +else if (HIGHEST_BANK == 2) begin : banks_2 + assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1}; + assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1}; +end +else begin : banks_1 + assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1}; +end + +if ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0 +mig_7series_v4_0_ddr_phy_4lanes # + ( + .BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */ + .DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */ + .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS), + .PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY), + .BITLANES (PHY_0_BITLANES), + .BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY), + .BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK), + .LAST_BANK (PHY_0_IS_LAST_BANK), + .LANE_REMAP (PHY_0_LANE_REMAP), + .OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE), + .IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE), + .GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL), + .IODELAY_GRP (PHY_0_IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .NUM_DDR_CK (NUM_DDR_CK), + .TCK (TCK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .PC_CLK_RATIO (PHY_CLK_RATIO), + .PC_EVENTS_DELAY (PHY_EVENTS_DELAY), + .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS), + .PC_BURST_MODE (PHY_0_A_BURST_MODE), + .PC_SYNC_MODE (PHY_SYNC_MODE), + .PC_MULTI_REGION (PHY_MULTI_REGION), + .PC_PHY_COUNT_EN (PHY_COUNT_EN), + .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH), + .PC_CMD_OFFSET (PHY_0_CMD_OFFSET), + .PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0), + .PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1), + .PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2), + .PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3), + .PC_RD_DURATION_0 (PHY_0_RD_DURATION_0), + .PC_RD_DURATION_1 (PHY_0_RD_DURATION_1), + .PC_RD_DURATION_2 (PHY_0_RD_DURATION_2), + .PC_RD_DURATION_3 (PHY_0_RD_DURATION_3), + .PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0), + .PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1), + .PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2), + .PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3), + .PC_WR_DURATION_0 (PHY_0_WR_DURATION_0), + .PC_WR_DURATION_1 (PHY_0_WR_DURATION_1), + .PC_WR_DURATION_2 (PHY_0_WR_DURATION_2), + .PC_WR_DURATION_3 (PHY_0_WR_DURATION_3), + .PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN), + .PC_AO_TOGGLE (PHY_0_AO_TOGGLE), + + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + + .A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY), + .B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY), + .C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY), + .D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY), + + .A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV), + .A_PI_BURST_MODE (PHY_0_A_BURST_MODE), + .A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC), + .B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC), + .C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC), + .D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC), + .A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC), + .A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV), + .A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE), + .B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE), + .C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE), + .D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE), + .A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE), + .B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE), + .C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE), + .D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE), + .A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE), + .A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH), + .B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE), + .B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH), + .C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE), + .C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH), + .D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE), + .D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH), + .A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE), + .A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) +) + u_ddr_phy_4lanes +( + .rst (rst), + .phy_clk (phy_clk_split0), + .clk_div2 (clk_div2), + .phy_ctl_clk (phy_ctl_clk_split0), + .phy_ctl_wd (phy_ctl_wd_split0), + .data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]), + .phy_ctl_wr (phy_ctl_wr_split0), + .mem_refclk (mem_refclk_split), + .freq_refclk (freq_refclk_split), + .mem_refclk_div4 (mem_refclk_div4_split), + .sync_pulse (sync_pulse_split), + .phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]), + .phy_cmd_wr_en (phy_cmd_wr_en_split0), + .phy_data_wr_en (phy_data_wr_en_split0), + .phy_rd_en (phy_rd_en_split0), + .pll_lock (pll_lock), + .ddr_clk (ddr_clk_w[0]), + .rclk (), + .rst_out (rst_out_w[0]), + .mcGo (mcGo_w[0]), + .ref_dll_lock (ref_dll_lock_w[0]), + .idelayctrl_refclk (idelayctrl_refclk), + .idelay_inc (idelay_inc), + .idelay_ce (idelay_ce), + .idelay_ld (idelay_ld), + .phy_ctl_mstr_empty (phy_ctl_mstr_empty), + .if_rst (if_rst), + .if_empty_def (if_empty_def), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]), + .if_a_empty (if_a_empty_v[0]), + .if_empty (if_empty_v[0]), + .byte_rd_en (byte_rd_en_v[0]), + .if_empty_or (if_empty_or_v[0]), + .if_empty_and (if_empty_and_v[0]), + .of_ctl_a_full (of_ctl_a_full_v[0]), + .of_data_a_full (of_data_a_full_v[0]), + .of_ctl_full (of_ctl_full_v[0]), + .of_data_full (of_data_full_v[0]), + .pre_data_a_full (pre_data_a_full_v[0]), + .phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]), + .phy_ctl_a_full (_phy_ctl_a_full_p[0]), + .phy_ctl_full (_phy_ctl_full_p[0]), + .phy_ctl_empty (phy_ctl_empty[0]), + .mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]), + .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]), + .mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]), + .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]), + .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]), + .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]), + .aux_out (aux_out_[3:0]), + .phy_ctl_ready (phy_ctl_ready_w[0]), + .phy_write_calib (phy_write_calib), + .phy_read_calib (phy_read_calib), +// .scan_test_bus_A (scan_test_bus_A), +// .scan_test_bus_B (), +// .scan_test_bus_C (), +// .scan_test_bus_D (), + .phyGo (phyGo), + .input_sink (input_sink), + + .calib_sel (calib_sel_byte0), + .calib_zero_ctrl (calib_zero_ctrl[0]), + .calib_zero_lanes (calib_zero_lanes_int[3:0]), + .calib_in_common (calib_in_common), + .po_coarse_enable (po_coarse_enable[0]), + .po_fine_enable (po_fine_enable[0]), + .po_fine_inc (po_fine_inc[0]), + .po_coarse_inc (po_coarse_inc[0]), + .po_counter_load_en (po_counter_load_en), + .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]), + .po_counter_load_val (po_counter_load_val), + .po_counter_read_en (po_counter_read_en), + .po_coarse_overflow (po_coarse_overflow_w[0]), + .po_fine_overflow (po_fine_overflow_w[0]), + .po_counter_read_val (po_counter_read_val_w[0]), + + .pi_rst_dqs_find (pi_rst_dqs_find[0]), + .pi_fine_enable (pi_fine_enable), + .pi_fine_inc (pi_fine_inc), + .pi_counter_load_en (pi_counter_load_en), + .pi_counter_read_en (pi_counter_read_en), + .pi_counter_load_val (pi_counter_load_val), + .pi_fine_overflow (pi_fine_overflow_w[0]), + .pi_counter_read_val (pi_counter_read_val_w[0]), + .pi_dqs_found (pi_dqs_found_w[0]), + .pi_dqs_found_all (pi_dqs_found_all_w[0]), + .pi_dqs_found_any (pi_dqs_found_any_w[0]), + .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]), + .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]), + .pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]), + .pi_phase_locked (pi_phase_locked_w[0]), + .pi_phase_locked_all (pi_phase_locked_all_w[0]), + .fine_delay (fine_delay), + .fine_delay_sel (fine_delay_sel) +); + + always @(posedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[0] <= #100 0; + aux_out[2] <= #100 0; + end + else begin + aux_out[0] <= #100 aux_out_[0]; + aux_out[2] <= #100 aux_out_[2]; + end + end + if ( LP_RCLK_SELECT_EDGE[0]) begin + always @(posedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[1] <= #100 0; + aux_out[3] <= #100 0; + end + else begin + aux_out[1] <= #100 aux_out_[1]; + aux_out[3] <= #100 aux_out_[3]; + end + end + end + else begin + always @(negedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[1] <= #100 0; + aux_out[3] <= #100 0; + end + else begin + aux_out[1] <= #100 aux_out_[1]; + aux_out[3] <= #100 aux_out_[3]; + end + end + end +end +else begin + if ( HIGHEST_BANK > 0) begin + assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0; + assign _phy_ctl_a_full_p[0] = 0; + assign of_ctl_a_full_v[0] = 0; + assign of_ctl_full_v[0] = 0; + assign of_data_a_full_v[0] = 0; + assign of_data_full_v[0] = 0; + assign pre_data_a_full_v[0] = 0; + assign if_empty_v[0] = 0; + assign byte_rd_en_v[0] = 1; + always @(*) + aux_out[3:0] = 0; + end + assign pi_dqs_found_w[0] = 1; + assign pi_dqs_found_all_w[0] = 1; + assign pi_dqs_found_any_w[0] = 0; + assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111; + assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111; + assign pi_dqs_out_of_range_w[0] = 0; + assign pi_phase_locked_w[0] = 1; + assign po_fine_overflow_w[0] = 0; + assign po_coarse_overflow_w[0] = 0; + assign po_fine_overflow_w[0] = 0; + assign pi_fine_overflow_w[0] = 0; + assign po_counter_read_val_w[0] = 0; + assign pi_counter_read_val_w[0] = 0; + assign mcGo_w[0] = 1; + if ( RCLK_SELECT_BANK == 0) + always @(*) + aux_out[3:0] = 0; +end + +if ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1 + +mig_7series_v4_0_ddr_phy_4lanes # + ( + .BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */ + .DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */ + .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS), + .PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY), + .BITLANES (PHY_1_BITLANES), + .BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY), + .BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK), + .LAST_BANK (PHY_1_IS_LAST_BANK ), + .LANE_REMAP (PHY_1_LANE_REMAP), + .OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE), + .IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE), + .GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL), + .IODELAY_GRP (PHY_1_IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .NUM_DDR_CK (NUM_DDR_CK), + .TCK (TCK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .PC_CLK_RATIO (PHY_CLK_RATIO), + .PC_EVENTS_DELAY (PHY_EVENTS_DELAY), + .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS), + .PC_BURST_MODE (PHY_1_A_BURST_MODE), + .PC_SYNC_MODE (PHY_SYNC_MODE), + .PC_MULTI_REGION (PHY_MULTI_REGION), + .PC_PHY_COUNT_EN (PHY_COUNT_EN), + .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH), + .PC_CMD_OFFSET (PHY_1_CMD_OFFSET), + .PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0), + .PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1), + .PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2), + .PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3), + .PC_RD_DURATION_0 (PHY_1_RD_DURATION_0), + .PC_RD_DURATION_1 (PHY_1_RD_DURATION_1), + .PC_RD_DURATION_2 (PHY_1_RD_DURATION_2), + .PC_RD_DURATION_3 (PHY_1_RD_DURATION_3), + .PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0), + .PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1), + .PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2), + .PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3), + .PC_WR_DURATION_0 (PHY_1_WR_DURATION_0), + .PC_WR_DURATION_1 (PHY_1_WR_DURATION_1), + .PC_WR_DURATION_2 (PHY_1_WR_DURATION_2), + .PC_WR_DURATION_3 (PHY_1_WR_DURATION_3), + .PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN), + .PC_AO_TOGGLE (PHY_1_AO_TOGGLE), + + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + + .A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY), + .B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY), + .C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY), + .D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY), + + .A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV), + .A_PI_BURST_MODE (PHY_1_A_BURST_MODE), + .A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC), + .B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC), + .C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC), + .D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC), + .A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC), + .A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY), + .A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV), + .A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE), + .B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE), + .C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE), + .D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE), + .A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE), + .B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE), + .C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE), + .D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE), + .A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE), + .A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH), + .B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE), + .B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH), + .C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE), + .C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH), + .D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE), + .D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH), + .A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE), + .A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) +) + u_ddr_phy_4lanes +( + .rst (rst), + .phy_clk (phy_clk_split1), + .clk_div2 (clk_div2), + .phy_ctl_clk (phy_ctl_clk_split1), + .phy_ctl_wd (phy_ctl_wd_split1), + .data_offset (phy_data_offset_1_split1), + .phy_ctl_wr (phy_ctl_wr_split1), + .mem_refclk (mem_refclk_split), + .freq_refclk (freq_refclk_split), + .mem_refclk_div4 (mem_refclk_div4_split), + .sync_pulse (sync_pulse_split), + .phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]), + .phy_cmd_wr_en (phy_cmd_wr_en_split1), + .phy_data_wr_en (phy_data_wr_en_split1), + .phy_rd_en (phy_rd_en_split1), + .pll_lock (pll_lock), + .ddr_clk (ddr_clk_w[1]), + .rclk (), + .rst_out (rst_out_w[1]), + .mcGo (mcGo_w[1]), + .ref_dll_lock (ref_dll_lock_w[1]), + .idelayctrl_refclk (idelayctrl_refclk), + .idelay_inc (idelay_inc), + .idelay_ce (idelay_ce), + .idelay_ld (idelay_ld), + .phy_ctl_mstr_empty (phy_ctl_mstr_empty), + .if_rst (if_rst), + .if_empty_def (if_empty_def), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]), + .if_a_empty (if_a_empty_v[1]), + .if_empty (if_empty_v[1]), + .byte_rd_en (byte_rd_en_v[1]), + .if_empty_or (if_empty_or_v[1]), + .if_empty_and (if_empty_and_v[1]), + .of_ctl_a_full (of_ctl_a_full_v[1]), + .of_data_a_full (of_data_a_full_v[1]), + .of_ctl_full (of_ctl_full_v[1]), + .of_data_full (of_data_full_v[1]), + .pre_data_a_full (pre_data_a_full_v[1]), + .phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]), + .phy_ctl_a_full (_phy_ctl_a_full_p[1]), + .phy_ctl_full (_phy_ctl_full_p[1]), + .phy_ctl_empty (phy_ctl_empty[1]), + .mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]), + .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]), + .mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]), + .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]), + .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]), + .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]), + .aux_out (aux_out_[7:4]), + .phy_ctl_ready (phy_ctl_ready_w[1]), + .phy_write_calib (phy_write_calib), + .phy_read_calib (phy_read_calib), +// .scan_test_bus_A (scan_test_bus_A), +// .scan_test_bus_B (), +// .scan_test_bus_C (), +// .scan_test_bus_D (), + .phyGo (phyGo), + .input_sink (input_sink), + + .calib_sel (calib_sel_byte1), + .calib_zero_ctrl (calib_zero_ctrl[1]), + .calib_zero_lanes (calib_zero_lanes_int[7:4]), + .calib_in_common (calib_in_common), + .po_coarse_enable (po_coarse_enable[1]), + .po_fine_enable (po_fine_enable[1]), + .po_fine_inc (po_fine_inc[1]), + .po_coarse_inc (po_coarse_inc[1]), + .po_counter_load_en (po_counter_load_en), + .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]), + .po_counter_load_val (po_counter_load_val), + .po_counter_read_en (po_counter_read_en), + .po_coarse_overflow (po_coarse_overflow_w[1]), + .po_fine_overflow (po_fine_overflow_w[1]), + .po_counter_read_val (po_counter_read_val_w[1]), + + .pi_rst_dqs_find (pi_rst_dqs_find[1]), + .pi_fine_enable (pi_fine_enable), + .pi_fine_inc (pi_fine_inc), + .pi_counter_load_en (pi_counter_load_en), + .pi_counter_read_en (pi_counter_read_en), + .pi_counter_load_val (pi_counter_load_val), + .pi_fine_overflow (pi_fine_overflow_w[1]), + .pi_counter_read_val (pi_counter_read_val_w[1]), + .pi_dqs_found (pi_dqs_found_w[1]), + .pi_dqs_found_all (pi_dqs_found_all_w[1]), + .pi_dqs_found_any (pi_dqs_found_any_w[1]), + .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]), + .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]), + .pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]), + .pi_phase_locked (pi_phase_locked_w[1]), + .pi_phase_locked_all (pi_phase_locked_all_w[1]), + .fine_delay (fine_delay), + .fine_delay_sel (fine_delay_sel) +); + + always @(posedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[4] <= #100 0; + aux_out[6] <= #100 0; + end + else begin + aux_out[4] <= #100 aux_out_[4]; + aux_out[6] <= #100 aux_out_[6]; + end + end + if ( LP_RCLK_SELECT_EDGE[1]) begin + always @(posedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[5] <= #100 0; + aux_out[7] <= #100 0; + end + else begin + aux_out[5] <= #100 aux_out_[5]; + aux_out[7] <= #100 aux_out_[7]; + end + end + end + else begin + always @(negedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[5] <= #100 0; + aux_out[7] <= #100 0; + end + else begin + aux_out[5] <= #100 aux_out_[5]; + aux_out[7] <= #100 aux_out_[7]; + end + end + end +end +else begin + if ( HIGHEST_BANK > 1) begin + assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0; + assign _phy_ctl_a_full_p[1] = 0; + assign of_ctl_a_full_v[1] = 0; + assign of_ctl_full_v[1] = 0; + assign of_data_a_full_v[1] = 0; + assign of_data_full_v[1] = 0; + assign pre_data_a_full_v[1] = 0; + assign if_empty_v[1] = 0; + assign byte_rd_en_v[1] = 1; + assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111; + assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111; + always @(*) + aux_out[7:4] = 0; + end + assign pi_dqs_found_w[1] = 1; + assign pi_dqs_found_all_w[1] = 1; + assign pi_dqs_found_any_w[1] = 0; + assign pi_dqs_out_of_range_w[1] = 0; + assign pi_phase_locked_w[1] = 1; + assign po_coarse_overflow_w[1] = 0; + assign po_fine_overflow_w[1] = 0; + assign pi_fine_overflow_w[1] = 0; + assign po_counter_read_val_w[1] = 0; + assign pi_counter_read_val_w[1] = 0; + assign mcGo_w[1] = 1; +end + +if ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2 + +mig_7series_v4_0_ddr_phy_4lanes # + ( + .BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */ + .DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */ + .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS), + .PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY), + .BITLANES (PHY_2_BITLANES), + .BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY), + .BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK), + .LAST_BANK (PHY_2_IS_LAST_BANK ), + .LANE_REMAP (PHY_2_LANE_REMAP), + .OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE), + .IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE), + .GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL), + .IODELAY_GRP (PHY_2_IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .NUM_DDR_CK (NUM_DDR_CK), + .TCK (TCK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .PC_CLK_RATIO (PHY_CLK_RATIO), + .PC_EVENTS_DELAY (PHY_EVENTS_DELAY), + .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS), + .PC_BURST_MODE (PHY_2_A_BURST_MODE), + .PC_SYNC_MODE (PHY_SYNC_MODE), + .PC_MULTI_REGION (PHY_MULTI_REGION), + .PC_PHY_COUNT_EN (PHY_COUNT_EN), + .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH), + .PC_CMD_OFFSET (PHY_2_CMD_OFFSET), + .PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0), + .PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1), + .PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2), + .PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3), + .PC_RD_DURATION_0 (PHY_2_RD_DURATION_0), + .PC_RD_DURATION_1 (PHY_2_RD_DURATION_1), + .PC_RD_DURATION_2 (PHY_2_RD_DURATION_2), + .PC_RD_DURATION_3 (PHY_2_RD_DURATION_3), + .PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0), + .PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1), + .PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2), + .PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3), + .PC_WR_DURATION_0 (PHY_2_WR_DURATION_0), + .PC_WR_DURATION_1 (PHY_2_WR_DURATION_1), + .PC_WR_DURATION_2 (PHY_2_WR_DURATION_2), + .PC_WR_DURATION_3 (PHY_2_WR_DURATION_3), + .PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN), + .PC_AO_TOGGLE (PHY_2_AO_TOGGLE), + + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + + .A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY), + .B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY), + .C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY), + .D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY), + .A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV), + .A_PI_BURST_MODE (PHY_2_A_BURST_MODE), + .A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC), + .B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC), + .C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC), + .D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC), + .A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC), + .A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY), + .A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV), + .A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE), + .B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE), + .C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE), + .D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE), + .A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE), + .B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE), + .C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE), + .D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE), + .A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE), + .A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH), + .B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE), + .B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH), + .C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE), + .C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH), + .D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE), + .D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH), + .A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE), + .A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) +) + u_ddr_phy_4lanes +( + .rst (rst), + .phy_clk (phy_clk_split2), + .clk_div2 (clk_div2), + .phy_ctl_clk (phy_ctl_clk_split2), + .phy_ctl_wd (phy_ctl_wd_split2), + .data_offset (phy_data_offset_2_split2), + .phy_ctl_wr (phy_ctl_wr_split2), + .mem_refclk (mem_refclk_split), + .freq_refclk (freq_refclk_split), + .mem_refclk_div4 (mem_refclk_div4_split), + .sync_pulse (sync_pulse_split), + .phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]), + .phy_cmd_wr_en (phy_cmd_wr_en_split2), + .phy_data_wr_en (phy_data_wr_en_split2), + .phy_rd_en (phy_rd_en_split2), + .pll_lock (pll_lock), + .ddr_clk (ddr_clk_w[2]), + .rclk (), + .rst_out (rst_out_w[2]), + .mcGo (mcGo_w[2]), + .ref_dll_lock (ref_dll_lock_w[2]), + .idelayctrl_refclk (idelayctrl_refclk), + .idelay_inc (idelay_inc), + .idelay_ce (idelay_ce), + .idelay_ld (idelay_ld), + .phy_ctl_mstr_empty (phy_ctl_mstr_empty), + .if_rst (if_rst), + .if_empty_def (if_empty_def), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]), + .if_a_empty (if_a_empty_v[2]), + .if_empty (if_empty_v[2]), + .byte_rd_en (byte_rd_en_v[2]), + .if_empty_or (if_empty_or_v[2]), + .if_empty_and (if_empty_and_v[2]), + .of_ctl_a_full (of_ctl_a_full_v[2]), + .of_data_a_full (of_data_a_full_v[2]), + .of_ctl_full (of_ctl_full_v[2]), + .of_data_full (of_data_full_v[2]), + .pre_data_a_full (pre_data_a_full_v[2]), + .phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]), + .phy_ctl_a_full (_phy_ctl_a_full_p[2]), + .phy_ctl_full (_phy_ctl_full_p[2]), + .phy_ctl_empty (phy_ctl_empty[2]), + .mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]), + .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]), + .mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]), + .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]), + .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]), + .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]), + .aux_out (aux_out_[11:8]), + .phy_ctl_ready (phy_ctl_ready_w[2]), + .phy_write_calib (phy_write_calib), + .phy_read_calib (phy_read_calib), +// .scan_test_bus_A (scan_test_bus_A), +// .scan_test_bus_B (), +// .scan_test_bus_C (), +// .scan_test_bus_D (), + .phyGo (phyGo), + .input_sink (input_sink), + + .calib_sel (calib_sel_byte2), + .calib_zero_ctrl (calib_zero_ctrl[2]), + .calib_zero_lanes (calib_zero_lanes_int[11:8]), + .calib_in_common (calib_in_common), + .po_coarse_enable (po_coarse_enable[2]), + .po_fine_enable (po_fine_enable[2]), + .po_fine_inc (po_fine_inc[2]), + .po_coarse_inc (po_coarse_inc[2]), + .po_counter_load_en (po_counter_load_en), + .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]), + .po_counter_load_val (po_counter_load_val), + .po_counter_read_en (po_counter_read_en), + .po_coarse_overflow (po_coarse_overflow_w[2]), + .po_fine_overflow (po_fine_overflow_w[2]), + .po_counter_read_val (po_counter_read_val_w[2]), + + .pi_rst_dqs_find (pi_rst_dqs_find[2]), + .pi_fine_enable (pi_fine_enable), + .pi_fine_inc (pi_fine_inc), + .pi_counter_load_en (pi_counter_load_en), + .pi_counter_read_en (pi_counter_read_en), + .pi_counter_load_val (pi_counter_load_val), + .pi_fine_overflow (pi_fine_overflow_w[2]), + .pi_counter_read_val (pi_counter_read_val_w[2]), + .pi_dqs_found (pi_dqs_found_w[2]), + .pi_dqs_found_all (pi_dqs_found_all_w[2]), + .pi_dqs_found_any (pi_dqs_found_any_w[2]), + .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]), + .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]), + .pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]), + .pi_phase_locked (pi_phase_locked_w[2]), + .pi_phase_locked_all (pi_phase_locked_all_w[2]), + .fine_delay (fine_delay), + .fine_delay_sel (fine_delay_sel) +); + always @(posedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[8] <= #100 0; + aux_out[10] <= #100 0; + end + else begin + aux_out[8] <= #100 aux_out_[8]; + aux_out[10] <= #100 aux_out_[10]; + end + end + if ( LP_RCLK_SELECT_EDGE[1]) begin + always @(posedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[9] <= #100 0; + aux_out[11] <= #100 0; + end + else begin + aux_out[9] <= #100 aux_out_[9]; + aux_out[11] <= #100 aux_out_[11]; + end + end + end + else begin + always @(negedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[9] <= #100 0; + aux_out[11] <= #100 0; + end + else begin + aux_out[9] <= #100 aux_out_[9]; + aux_out[11] <= #100 aux_out_[11]; + end + end + end +end +else begin + if ( HIGHEST_BANK > 2) begin + assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0; + assign _phy_ctl_a_full_p[2] = 0; + assign of_ctl_a_full_v[2] = 0; + assign of_ctl_full_v[2] = 0; + assign of_data_a_full_v[2] = 0; + assign of_data_full_v[2] = 0; + assign pre_data_a_full_v[2] = 0; + assign if_empty_v[2] = 0; + assign byte_rd_en_v[2] = 1; + assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111; + assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111; + always @(*) + aux_out[11:8] = 0; + end + assign pi_dqs_found_w[2] = 1; + assign pi_dqs_found_all_w[2] = 1; + assign pi_dqs_found_any_w[2] = 0; + assign pi_dqs_out_of_range_w[2] = 0; + assign pi_phase_locked_w[2] = 1; + assign po_coarse_overflow_w[2] = 0; + assign po_fine_overflow_w[2] = 0; + assign po_counter_read_val_w[2] = 0; + assign pi_counter_read_val_w[2] = 0; + assign mcGo_w[2] = 1; +end +endgenerate + +generate + +// for single bank , emit an extra phaser_in to generate rclk +// so that auxout can be placed in another region +// if desired + +if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0) +begin : phaser_in_rclk + +localparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY; + +PHASER_IN_PHY #( + .BURST_MODE ( PHY_0_A_BURST_MODE), + .CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV), + .FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV), + .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS), + .FINE_DELAY ( L_EXTRA_PI_FINE_DELAY), + .OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC) +) phaser_in_rclk ( + .DQSFOUND (), + .DQSOUTOFRANGE (), + .FINEOVERFLOW (), + .PHASELOCKED (), + .ISERDESRST (), + .ICLKDIV (), + .ICLK (), + .COUNTERREADVAL (), + .RCLK (), + .WRENABLE (), + .BURSTPENDINGPHY (), + .ENCALIBPHY (), + .FINEENABLE (0), + .FREQREFCLK (freq_refclk), + .MEMREFCLK (mem_refclk), + .RANKSELPHY (0), + .PHASEREFCLK (), + .RSTDQSFIND (0), + .RST (rst), + .FINEINC (), + .COUNTERLOADEN (), + .COUNTERREADEN (), + .COUNTERLOADVAL (), + .SYNCIN (sync_pulse), + .SYSCLK (phy_clk) +); + +end + +endgenerate + + + +always @(*) begin + case (calib_sel[5:3]) + 3'b000: begin + po_coarse_overflow = po_coarse_overflow_w[0]; + po_fine_overflow = po_fine_overflow_w[0]; + po_counter_read_val = po_counter_read_val_w[0]; + pi_fine_overflow = pi_fine_overflow_w[0]; + pi_counter_read_val = pi_counter_read_val_w[0]; + pi_phase_locked = pi_phase_locked_w[0]; + if ( calib_in_common) + pi_dqs_found = pi_dqs_found_any; + else + pi_dqs_found = pi_dqs_found_w[0]; + pi_dqs_out_of_range = pi_dqs_out_of_range_w[0]; + end + 3'b001: begin + po_coarse_overflow = po_coarse_overflow_w[1]; + po_fine_overflow = po_fine_overflow_w[1]; + po_counter_read_val = po_counter_read_val_w[1]; + pi_fine_overflow = pi_fine_overflow_w[1]; + pi_counter_read_val = pi_counter_read_val_w[1]; + pi_phase_locked = pi_phase_locked_w[1]; + if ( calib_in_common) + pi_dqs_found = pi_dqs_found_any; + else + pi_dqs_found = pi_dqs_found_w[1]; + pi_dqs_out_of_range = pi_dqs_out_of_range_w[1]; + end + 3'b010: begin + po_coarse_overflow = po_coarse_overflow_w[2]; + po_fine_overflow = po_fine_overflow_w[2]; + po_counter_read_val = po_counter_read_val_w[2]; + pi_fine_overflow = pi_fine_overflow_w[2]; + pi_counter_read_val = pi_counter_read_val_w[2]; + pi_phase_locked = pi_phase_locked_w[2]; + if ( calib_in_common) + pi_dqs_found = pi_dqs_found_any; + else + pi_dqs_found = pi_dqs_found_w[2]; + pi_dqs_out_of_range = pi_dqs_out_of_range_w[2]; + end + default: begin + po_coarse_overflow = 0; + po_fine_overflow = 0; + po_counter_read_val = 0; + pi_fine_overflow = 0; + pi_counter_read_val = 0; + pi_phase_locked = 0; + pi_dqs_found = 0; + pi_dqs_out_of_range = 0; + end + endcase +end + +endmodule // mc_phy diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_mc_phy_wrapper.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_mc_phy_wrapper.v new file mode 100644 index 0000000..c80e0ab --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_mc_phy_wrapper.v @@ -0,0 +1,1684 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : ddr_mc_phy_wrapper.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Oct 10 2010 +// \___\/\___\ +// +//Device : 7 Series +//Design Name : DDR3 SDRAM +//Purpose : Wrapper file that encompasses the MC_PHY module +// instantiation and handles the vector remapping between +// the MC_PHY ports and the user's DDR3 ports. Vector +// remapping affects DDR3 control, address, and DQ/DQS/DM. +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_0_ddr_mc_phy_wrapper # + ( + parameter TCQ = 100, // Register delay (simulation only) + parameter tCK = 2500, // ps + parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" + parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" + parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" + parameter IODELAY_GRP = "IODELAY_MIG", + parameter FPGA_SPEED_GRADE = 1, + parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio + parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank + parameter BANK_WIDTH = 3, // # of bank address + parameter CKE_WIDTH = 1, // # of clock enable outputs + parameter CS_WIDTH = 1, // # of chip select + parameter CK_WIDTH = 1, // # of CK + parameter CWL = 5, // CAS Write latency + parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 + parameter DM_WIDTH = 8, // # of data mask + parameter DQ_WIDTH = 16, // # of data bits + parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of strobe pairs + parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3) + parameter RANKS = 4, // # of ranks + parameter ODT_WIDTH = 1, // # of ODT outputs + parameter POC_USE_METASTABLE_SAMP = "FALSE", + parameter REG_CTRL = "OFF", // "ON" for registered DIMM + parameter ROW_WIDTH = 16, // # of row/column address + parameter USE_CS_PORT = 1, // Support chip select output + parameter USE_DM_PORT = 1, // Support data mask output + parameter USE_ODT_PORT = 1, // Support ODT output + parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option + parameter LP_DDR_CK_WIDTH = 2, + + // Hard PHY parameters + parameter PHYCTL_CMD_FIFO = "FALSE", + parameter DATA_CTL_B0 = 4'hc, + parameter DATA_CTL_B1 = 4'hf, + parameter DATA_CTL_B2 = 4'hf, + parameter DATA_CTL_B3 = 4'hf, + parameter DATA_CTL_B4 = 4'hf, + parameter BYTE_LANES_B0 = 4'b1111, + parameter BYTE_LANES_B1 = 4'b0000, + parameter BYTE_LANES_B2 = 4'b0000, + parameter BYTE_LANES_B3 = 4'b0000, + parameter BYTE_LANES_B4 = 4'b0000, + parameter PHY_0_BITLANES = 48'h0000_0000_0000, + parameter PHY_1_BITLANES = 48'h0000_0000_0000, + parameter PHY_2_BITLANES = 48'h0000_0000_0000, + // Parameters calculated outside of this block + parameter HIGHEST_BANK = 3, // Highest I/O bank index + parameter HIGHEST_LANE = 12, // Highest byte lane index + // ** Pin mapping parameters + // Parameters for mapping between hard PHY and physical DDR3 signals + // There are 2 classes of parameters: + // - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of + // 8-bit elements. Each element indicates the bank and byte lane + // location of that particular signal. The bit lane in this case + // doesn't need to be specified, either because there's only one + // pin pair in each byte lane that the DQS or CK pair can be + // located at, or in the case of CKE_ODT_BYTE_MAP, only the byte + // lane needs to be specified in order to determine which byte + // lane generates the RCLK (Note that CKE, and ODT must be located + // in the same bank, thus only one element in CKE_ODT_BYTE_MAP) + // [7:4] = bank # (0-4) + // [3:0] = byte lane # (0-3) + // - All other MAP parameters: These consist of 12-bit elements. Each + // element indicates the bank, byte lane, and bit lane location of + // that particular signal: + // [11:8] = bank # (0-4) + // [7:4] = byte lane # (0-3) + // [3:0] = bit lane # (0-11) + // Note that not all elements in all parameters will be used - it + // depends on the actual widths of the DDR3 buses. The parameters are + // structured to support a maximum of: + // - DQS groups: 18 + // - data mask bits: 18 + // In addition, the default parameter size of some of the parameters will + // support a certain number of bits, however, this can be expanded at + // compile time by expanding the width of the vector passed into this + // parameter + // - chip selects: 10 + // - bank bits: 3 + // - address bits: 16 + parameter CK_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, + parameter ADDR_MAP + = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, + parameter BANK_MAP = 36'h000_000_000, + parameter CAS_MAP = 12'h000, + parameter CKE_ODT_BYTE_MAP = 8'h00, + parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000, + parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000, + parameter CKE_ODT_AUX = "FALSE", + parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, + parameter PARITY_MAP = 12'h000, + parameter RAS_MAP = 12'h000, + parameter WE_MAP = 12'h000, + parameter DQS_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, + // DATAx_MAP parameter is used for byte lane X in the design + parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, + // MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9] + parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, + parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, + // Simulation options + parameter SIM_CAL_OPTION = "NONE", + + // The PHY_CONTROL primitive in the bank where PLL exists is declared + // as the Master PHY_CONTROL. + parameter MASTER_PHY_CTL = 1, + parameter DRAM_WIDTH = 8, + parameter PI_DIV2_INCDEC = "FALSE" + ) + ( + input rst, + input iddr_rst, + input clk, + input clk_div2, + input freq_refclk, + input mem_refclk, + input pll_lock, + input sync_pulse, + input mmcm_ps_clk, + input idelayctrl_refclk, + input phy_cmd_wr_en, + input phy_data_wr_en, + input [31:0] phy_ctl_wd, + input phy_ctl_wr, + input phy_if_empty_def, + input phy_if_reset, + input [5:0] data_offset_1, + input [5:0] data_offset_2, + input [3:0] aux_in_1, + input [3:0] aux_in_2, + output [4:0] idelaye2_init_val, + output [5:0] oclkdelay_init_val, + output if_empty, + output phy_ctl_full, + output phy_cmd_full, + output phy_data_full, + output phy_pre_data_a_full, + output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk, + output phy_mc_go, + input phy_write_calib, + input phy_read_calib, + input calib_in_common, + input [5:0] calib_sel, + input [DQS_CNT_WIDTH:0] byte_sel_cnt, + input [DRAM_WIDTH-1:0] fine_delay_incdec_pb, + input fine_delay_sel, + input [HIGHEST_BANK-1:0] calib_zero_inputs, + input [HIGHEST_BANK-1:0] calib_zero_ctrl, + input [2:0] po_fine_enable, + input [2:0] po_coarse_enable, + input [2:0] po_fine_inc, + input [2:0] po_coarse_inc, + input po_counter_load_en, + input po_counter_read_en, + input [2:0] po_sel_fine_oclk_delay, + input [8:0] po_counter_load_val, + output [8:0] po_counter_read_val, + output [5:0] pi_counter_read_val, + input [HIGHEST_BANK-1:0] pi_rst_dqs_find, + input pi_fine_enable, + input pi_fine_inc, + input pi_counter_load_en, + input [5:0] pi_counter_load_val, + input idelay_ce, + input idelay_inc, + input idelay_ld, + input idle, + output pi_phase_locked, + output pi_phase_locked_all, + output pi_dqs_found, + output pi_dqs_found_all, + output pi_dqs_out_of_range, + // From/to calibration logic/soft PHY + input phy_init_data_sel, + input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address, + input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank, + input [nCK_PER_CLK-1:0] mux_cas_n, + input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n, + input [nCK_PER_CLK-1:0] mux_ras_n, + input [1:0] mux_odt, + input [nCK_PER_CLK-1:0] mux_cke, + input [nCK_PER_CLK-1:0] mux_we_n, + input [nCK_PER_CLK-1:0] parity_in, + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata, + input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask, + input mux_reset_n, + output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, + // Memory I/F + output [ROW_WIDTH-1:0] ddr_addr, + output [BANK_WIDTH-1:0] ddr_ba, + output ddr_cas_n, + output [CKE_WIDTH-1:0] ddr_cke, + output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, + output [DM_WIDTH-1:0] ddr_dm, + output [ODT_WIDTH-1:0] ddr_odt, + output ddr_parity, + output ddr_ras_n, + output ddr_we_n, + output ddr_reset_n, + inout [DQ_WIDTH-1:0] ddr_dq, + inout [DQS_WIDTH-1:0] ddr_dqs, + inout [DQS_WIDTH-1:0] ddr_dqs_n, + //output iodelay_ctrl_rdy, + output pd_out + + ,input dbg_pi_counter_read_en + ,output ref_dll_lock + ,input rst_phaser_ref + ,output [11:0] dbg_pi_phase_locked_phy4lanes + ,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes + ); + + function [71:0] generate_bytelanes_ddr_ck; + input [143:0] ck_byte_map; + integer v ; + begin + generate_bytelanes_ddr_ck = 'b0 ; + for (v = 0; v < CK_WIDTH; v = v + 1) begin + if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2) + generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; + else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1) + generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; + else + generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; + end + end + endfunction + + function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map; + input [143:0] ck_byte_map; + integer g; + begin + generate_ddr_ck_map = 'b0 ; + for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin + generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" : + (ck_byte_map[(g*8)+:4] == 4'd1) ? "B" : + (ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ; + generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" : + (ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location + end + end + endfunction + + + + // Enable low power mode for input buffer + localparam IBUF_LOW_PWR + = (IBUF_LPWR_MODE == "OFF") ? "FALSE" : + ((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL"); + + // Ratio of data to strobe + localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH; + // number of data phases per internal clock + localparam PHASE_PER_CLK = 2*nCK_PER_CLK; + // used to determine routing to OUT_FIFO for control/address for 2:1 + // vs. 4:1 memory:internal clock ratio modes + localparam PHASE_DIV = 4 / nCK_PER_CLK; + + localparam CLK_PERIOD = tCK * nCK_PER_CLK; + + // Create an aggregate parameters for data mapping to reduce # of generate + // statements required in remapping code. Need to account for the case + // when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP + // parameter will have fewer than 8 elements used + localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0], + DATA16_MAP[12*DQ_PER_DQS-1:0], + DATA15_MAP[12*DQ_PER_DQS-1:0], + DATA14_MAP[12*DQ_PER_DQS-1:0], + DATA13_MAP[12*DQ_PER_DQS-1:0], + DATA12_MAP[12*DQ_PER_DQS-1:0], + DATA11_MAP[12*DQ_PER_DQS-1:0], + DATA10_MAP[12*DQ_PER_DQS-1:0], + DATA9_MAP[12*DQ_PER_DQS-1:0], + DATA8_MAP[12*DQ_PER_DQS-1:0], + DATA7_MAP[12*DQ_PER_DQS-1:0], + DATA6_MAP[12*DQ_PER_DQS-1:0], + DATA5_MAP[12*DQ_PER_DQS-1:0], + DATA4_MAP[12*DQ_PER_DQS-1:0], + DATA3_MAP[12*DQ_PER_DQS-1:0], + DATA2_MAP[12*DQ_PER_DQS-1:0], + DATA1_MAP[12*DQ_PER_DQS-1:0], + DATA0_MAP[12*DQ_PER_DQS-1:0]}; + // Same deal, but for data mask mapping + localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP}; + localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ; + localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ; + + // Temporary parameters to determine which bank is outputting the CK/CK# + // Eventually there will be support for multiple CK/CK# output + //localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]); + //// Temporary method to force MC_PHY to generate ODDR associated with + //// CK/CK# output only for a single byte lane in the design. All banks + //// that won't be generating the CK/CK# will have "UNUSED" as their + //// PHY_GENERATE_DDR_CK parameter + //localparam TMP_PHY_0_GENERATE_DDR_CK + // = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" : + // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : + // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : + // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); + //localparam TMP_PHY_1_GENERATE_DDR_CK + // = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" : + // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : + // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : + // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); + //localparam TMP_PHY_2_GENERATE_DDR_CK + // = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" : + // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : + // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : + // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); + + // Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx + // which indicates which bit lanes in data byte lanes are + // output-only bitlanes (e.g. used specifically for data mask outputs) + function [143:0] calc_phy_bitlanes_outonly; + input [215:0] data_mask_in; + integer z; + begin + calc_phy_bitlanes_outonly = 'b0; + // Only enable BITLANES parameters for data masks if, well, if + // the data masks are actually enabled + if (USE_DM_PORT == 1) + for (z = 0; z < DM_WIDTH; z = z + 1) + calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] + + 12*data_mask_in[(12*z+4)+:2] + + data_mask_in[12*z+:4]] = 1'b1; + end + endfunction + + localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP); + localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0]; + localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48]; + localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96]; + + // Determine which bank and byte lane generates the RCLK used to clock + // out the auxilliary (ODT, CKE) outputs + localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON + = (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 : + ((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 : + ((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 : + ((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 : + ((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1)))); + localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON + = (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" : + ((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" : + ((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" : + ((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL"))); + + localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF + = (CKE_MAP[11:8] == 4'h0) ? 0 : + ((CKE_MAP[11:8] == 4'h1) ? 1 : + ((CKE_MAP[11:8] == 4'h2) ? 2 : + ((CKE_MAP[11:8] == 4'h3) ? 3 : + ((CKE_MAP[11:8] == 4'h4) ? 4 : -1)))); + localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF + = (CKE_MAP[7:4] == 4'h0) ? "A" : + ((CKE_MAP[7:4] == 4'h1) ? "B" : + ((CKE_MAP[7:4] == 4'h2) ? "C" : + ((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL"))); + + + localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ; + localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ; + + + //*************************************************************************** + // OCLKDELAYED tap setting calculation: + // Parameters for calculating amount of phase shifting output clock to + // achieve 90 degree offset between DQS and DQ on writes + //*************************************************************************** + + //90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz + // and 1.25 for Mem_RefClk > 300 MHz + localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE"; + + //DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, + //DIV4: MemRefClk < 200 MHz + localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" : + tCK > 2500 ? "DIV2": "NONE"; + + localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 : + PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1); + + // Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output + localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK; + + // Whether OCLK_DELAY output comes inverted or not + localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0); + + // Phaser-Out Stage3 Tap delay for 90 deg shift. + // Maximum tap delay is FreqRefClk period distributed over 64 taps + // localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV; + localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) - + (INT_DELAY + HALF_CYCLE_DELAY)) + * 63 * FREQ_REF_DIV; + //localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY; + + localparam integer PHY_0_A_PO_OCLK_DELAY_HW + = (tCK > 2273) ? 34 : + (tCK > 2000) ? 33 : + (tCK > 1724) ? 32 : + (tCK > 1515) ? 31 : + (tCK > 1315) ? 30 : + (tCK > 1136) ? 29 : + (tCK > 1021) ? 28 : 27; + + // Note that simulation requires a different value than in H/W because of the + // difference in the way delays are modeled + localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ? + ((tCK > 2500) ? 8 : + (DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) : + MC_OCLK_DELAY; + + // Initial DQ IDELAY value + localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 : + (tCK < 1000) ? 0 : + (tCK < 1330) ? 0 : + (tCK < 2300) ? 0 : + (tCK < 2500) ? 2 : 0; + //localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0; + + // Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3? + localparam PHY_0_RD_CMD_OFFSET_0 = 10; + localparam PHY_0_RD_CMD_OFFSET_1 = 10; + localparam PHY_0_RD_CMD_OFFSET_2 = 10; + localparam PHY_0_RD_CMD_OFFSET_3 = 10; + // 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing + localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4; + localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4; + localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4; + localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4; + // 4:1 and 2:1 have different values + localparam PHY_0_WR_DURATION_0 = 7; + localparam PHY_0_WR_DURATION_1 = 7; + localparam PHY_0_WR_DURATION_2 = 7; + localparam PHY_0_WR_DURATION_3 = 7; + // Aux_out parameters for toggle mode (CKE) + localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; + localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 : + (CWL < 7) ? + 4 + ((CWL_M % 2) ? 0 : 1) : + 5 + ((CWL_M % 2) ? 0 : 1); + + // temporary parameter to enable/disable PHY PC counters. In both 4:1 and + // 2:1 cases, this should be disabled. For now, enable for 4:1 mode to + // avoid making too many changes at once. + localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE"; + + + wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out; + wire [HIGHEST_LANE-1:0] mem_dqs_in; + wire [HIGHEST_LANE-1:0] mem_dqs_out; + wire [HIGHEST_LANE-1:0] mem_dqs_ts; + wire [HIGHEST_LANE*10-1:0] mem_dq_in; + wire [HIGHEST_LANE*12-1:0] mem_dq_out; + wire [HIGHEST_LANE*12-1:0] mem_dq_ts; + wire [DQ_WIDTH-1:0] in_dq; + wire [DQS_WIDTH-1:0] in_dqs; + wire [ROW_WIDTH-1:0] out_addr; + wire [BANK_WIDTH-1:0] out_ba; + wire out_cas_n; + wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n; + wire [DM_WIDTH-1:0] out_dm; + wire [ODT_WIDTH -1:0] out_odt; + wire [CKE_WIDTH -1 :0] out_cke ; + wire [DQ_WIDTH-1:0] out_dq; + wire [DQS_WIDTH-1:0] out_dqs; + wire out_parity; + wire out_ras_n; + wire out_we_n; + wire [HIGHEST_LANE*80-1:0] phy_din; + wire [HIGHEST_LANE*80-1:0] phy_dout; + wire phy_rd_en; + wire [DM_WIDTH-1:0] ts_dm; + wire [DQ_WIDTH-1:0] ts_dq; + wire [DQS_WIDTH-1:0] ts_dqs; + wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr; + wire [DQS_WIDTH-1:0] pd_out_pre; + //wire metaQ; + + reg [31:0] phy_ctl_wd_i1; + reg [31:0] phy_ctl_wd_i2; + reg phy_ctl_wr_i1; + reg phy_ctl_wr_i2; + reg [5:0] data_offset_1_i1; + reg [5:0] data_offset_1_i2; + reg [5:0] data_offset_2_i1; + reg [5:0] data_offset_2_i2; + wire [31:0] phy_ctl_wd_temp; + wire phy_ctl_wr_temp; + wire [5:0] data_offset_1_temp; + wire [5:0] data_offset_2_temp; + wire [5:0] data_offset_1_of; + wire [5:0] data_offset_2_of; + wire [31:0] phy_ctl_wd_of; + wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */; + wire [3:0] phy_ctl_full_temp; + + wire data_io_idle_pwrdwn; + reg [29:0] fine_delay_mod; //3 bit per DQ + reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb + + wire iddr_rst_i; + + (* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1; + + // Always read from input data FIFOs when not empty + assign phy_rd_en = !if_empty; + + // IDELAYE2 initial value + assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE; + assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY; + + // Idle powerdown when there are no pending reads in the MC + assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0; + assign iddr_rst_i = iddr_rst; + //*************************************************************************** + // Auxiliary output steering + //*************************************************************************** + + // For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be + // mapped to ddr_odt and the aux_out[7:4] from one of the data banks + // will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the + // addr/ctl bank would bank would map to both ddr_odt and ddr_cke. + generate + if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins + if (CKE_WIDTH == 1) begin : gen_cke + // Explicitly instantiate OBUF to ensure that these are present + // in the netlist. Typically this is not required since NGDBUILD + // at the top-level knows to infer an I/O/IOBUF and therefore a + // top-level LOC constraint can be attached to that pin. This does + // not work when a hierarchical flow is used and the LOC is applied + // at the individual core-level UCF + OBUF u_cke_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), + .O (ddr_cke) + ); + end else begin: gen_2rank_cke + OBUF u_cke0_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), + .O (ddr_cke[0]) + ); + OBUF u_cke1_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), + .O (ddr_cke[1]) + ); + end + end + endgenerate + + generate + if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins + if (USE_ODT_PORT == 1) begin : gen_use_odt + // Explicitly instantiate OBUF to ensure that these are present + // in the netlist. Typically this is not required since NGDBUILD + // at the top-level knows to infer an I/O/IOBUF and therefore a + // top-level LOC constraint can be attached to that pin. This does + // not work when a hierarchical flow is used and the LOC is applied + // at the individual core-level UCF + OBUF u_odt_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]), + .O (ddr_odt[0]) + ); + if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt + OBUF u_odt1_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), + .O (ddr_odt[1]) + ); + end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt + OBUF u_odt1_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), + .O (ddr_odt[1]) + ); + end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt + OBUF u_odt1_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), + .O (ddr_odt[1]) + ); + OBUF u_odt2_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), + .O (ddr_odt[2]) + ); + end + end else begin + assign ddr_odt = 'b0; + end + end + endgenerate + + //*************************************************************************** + // Read data bit steering + //*************************************************************************** + + // Transpose elements of rd_data_map to form final read data output: + // phy_din elements are grouped according to "physical bit" - e.g. + // for nCK_PER_CLK = 4, there are 8 data phases transfered per physical + // bit per clock cycle: + // = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2, + // dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0} + // whereas rd_data is are grouped according to "phase" - e.g. + // = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0, + // dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0} + // therefore rd_data is formed by transposing phy_din - e.g. + // for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY + // bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then + // the assignments for bits of rd_data corresponding to DQ[1:0] + // would be: + // {rd_data[112], rd_data[96], rd_data[80], rd_data[64], + // rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0] + // {rd_data[113], rd_data[97], rd_data[81], rd_data[65], + // rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8] + generate + genvar i, j; + for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1 + for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2 + assign rd_data[DQ_WIDTH*j + i] + = phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+ + 80*FULL_DATA_MAP[(12*i+4)+:2] + + 8*FULL_DATA_MAP[12*i+:4]) + j]; + end + end + endgenerate + + //generage idelay_inc per bits + + reg [11:0] cal_tmp; + reg [95:0] byte_sel_data_map; + + assign byte_sel_cnt_w1 = byte_sel_cnt; + + always @ (posedge clk) begin + byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96]; + end + + always @ (posedge clk) begin + fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00}; + fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00}; + fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00}; + fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00}; + fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00}; + fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00}; + fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00}; + fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00}; + fine_delay_sel_r <= #TCQ fine_delay_sel; + end + + //*************************************************************************** + // Control/address + //*************************************************************************** + + assign out_cas_n + = mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]]; + + generate + // if signal placed on bit lanes [0-9] + if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10 + // Determine routing based on clock ratio mode. If running in 4:1 + // mode, then all four bits from logic are used. If 2:1 mode, only + // 2-bits are provided by logic, and each bit is repeated 2x to form + // 4-bit input to IN_FIFO, e.g. + // 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]} + // 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]} + assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + + 8*CAS_MAP[3:0])+:4] + = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], + mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; + end else begin: gen_cas_ge10 + // If signal is placed in bit lane [10] or [11], route to upper + // nibble of phy_dout lane [5] or [6] respectively (in this case + // phy_dout lane [5, 6] are multiplexed to take input for two + // different SDR signals - this is how bits[10,11] need to be + // provided to the OUT_FIFO + assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + + 8*(CAS_MAP[3:0]-5) + 4)+:4] + = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], + mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; + end + endgenerate + + assign out_ras_n + = mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]]; + + generate + if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10 + assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + + 8*RAS_MAP[3:0])+:4] + = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], + mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; + end else begin: gen_ras_ge10 + assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + + 8*(RAS_MAP[3:0]-5) + 4)+:4] + = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], + mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; + end + endgenerate + + assign out_we_n + = mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]]; + + generate + if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10 + assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + + 8*WE_MAP[3:0])+:4] + = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], + mux_we_n[1/PHASE_DIV], mux_we_n[0]}; + end else begin: gen_we_ge10 + assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + + 8*(WE_MAP[3:0]-5) + 4)+:4] + = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], + mux_we_n[1/PHASE_DIV], mux_we_n[0]}; + end + endgenerate + + generate + if (REG_CTRL == "ON") begin: gen_parity_out + // Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs + assign out_parity + = mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] + + PARITY_MAP[3:0]]; + if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10 + assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + + 8*PARITY_MAP[3:0])+:4] + = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], + parity_in[1/PHASE_DIV], parity_in[0]}; + end else begin: gen_ge10 + assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + + 8*(PARITY_MAP[3:0]-5) + 4)+:4] + = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], + parity_in[1/PHASE_DIV], parity_in[0]}; + end + end + endgenerate + + //***************************************************************** + + generate + genvar m, n,x; + + //***************************************************************** + // Control/address (multi-bit) buses + //***************************************************************** + + // Row/Column address + for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out + assign out_addr[m] + = mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] + + 12*ADDR_MAP[(12*m+4)+:2] + + ADDR_MAP[12*m+:4]]; + + if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10 + // For multi-bit buses, we also have to deal with transposition + // when going from the logic-side control bus to phy_dout + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + + 80*ADDR_MAP[(12*m+4)+:2] + + 8*ADDR_MAP[12*m+:4] + n] + = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; + end + end else begin: gen_ge10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + + 80*ADDR_MAP[(12*m+4)+:2] + + 8*(ADDR_MAP[12*m+:4]-5) + 4 + n] + = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; + end + end + end + + // Bank address + for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out + assign out_ba[m] + = mem_dq_out[48*BANK_MAP[(12*m+8)+:3] + + 12*BANK_MAP[(12*m+4)+:2] + + BANK_MAP[12*m+:4]]; + + if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + + 80*BANK_MAP[(12*m+4)+:2] + + 8*BANK_MAP[12*m+:4] + n] + = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; + end + end else begin: gen_ge10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + + 80*BANK_MAP[(12*m+4)+:2] + + 8*(BANK_MAP[12*m+:4]-5) + 4 + n] + = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; + end + end + end + + // Chip select + if (USE_CS_PORT == 1) begin: gen_cs_n_out + for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out + assign out_cs_n[m] + = mem_dq_out[48*CS_MAP[(12*m+8)+:3] + + 12*CS_MAP[(12*m+4)+:2] + + CS_MAP[12*m+:4]]; + if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*CS_MAP[(12*m+8)+:3] + + 80*CS_MAP[(12*m+4)+:2] + + 8*CS_MAP[12*m+:4] + n] + = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; + end + end else begin: gen_ge10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*CS_MAP[(12*m+8)+:3] + + 80*CS_MAP[(12*m+4)+:2] + + 8*(CS_MAP[12*m+:4]-5) + 4 + n] + = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; + end + end + end + end + + + if(CKE_ODT_AUX == "FALSE") begin + // ODT_ports + wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ; + + if(RANKS == 1) begin + for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin + assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ; + end + end else begin + for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin + assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ; + assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ; + end + end + + if (USE_ODT_PORT == 1) begin: gen_odt_out + for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1 + assign out_odt[m] + = mem_dq_out[48*ODT_MAP[(12*m+8)+:3] + + 12*ODT_MAP[(12*m+4)+:2] + + ODT_MAP[12*m+:4]]; + if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + + 80*ODT_MAP[(12*m+4)+:2] + + 8*ODT_MAP[12*m+:4] + n] + = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; + end + end else begin: gen_ge10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + + 80*ODT_MAP[(12*m+4)+:2] + + 8*(ODT_MAP[12*m+:4]-5) + 4 + n] + = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; + end + end + end + end + + + wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ; + + for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin + assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ; + end + + + + for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out + assign out_cke[m] + = mem_dq_out[48*CKE_MAP[(12*m+8)+:3] + + 12*CKE_MAP[(12*m+4)+:2] + + CKE_MAP[12*m+:4]]; + if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + + 80*CKE_MAP[(12*m+4)+:2] + + 8*CKE_MAP[12*m+:4] + n] + = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; + end + end else begin: gen_ge10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + + 80*CKE_MAP[(12*m+4)+:2] + + 8*(CKE_MAP[12*m+:4]-5) + 4 + n] + = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; + end + end + end + end + + //***************************************************************** + // Data mask + //***************************************************************** + + if (USE_DM_PORT == 1) begin: gen_dm_out + for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out + assign out_dm[m] + = mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] + + 12*FULL_MASK_MAP[(12*m+4)+:2] + + FULL_MASK_MAP[12*m+:4]]; + assign ts_dm[m] + = mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] + + 12*FULL_MASK_MAP[(12*m+4)+:2] + + FULL_MASK_MAP[12*m+:4]]; + for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose + assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] + + 80*FULL_MASK_MAP[(12*m+4)+:2] + + 8*FULL_MASK_MAP[12*m+:4] + n] + = mux_wrdata_mask[DM_WIDTH*n + m]; + end + end + end + + //***************************************************************** + // Input and output DQ + //***************************************************************** + + for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout + // to MC_PHY + assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] + + 10*FULL_DATA_MAP[(12*m+4)+:2] + + FULL_DATA_MAP[12*m+:4]] + = in_dq[m]; + // to I/O buffers + assign out_dq[m] + = mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] + + 12*FULL_DATA_MAP[(12*m+4)+:2] + + FULL_DATA_MAP[12*m+:4]]; + assign ts_dq[m] + = mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] + + 12*FULL_DATA_MAP[(12*m+4)+:2] + + FULL_DATA_MAP[12*m+:4]]; + for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose + assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] + + 80*FULL_DATA_MAP[(12*m+4)+:2] + + 8*FULL_DATA_MAP[12*m+:4] + n] + = mux_wrdata[DQ_WIDTH*n + m]; + end + end + + //***************************************************************** + // Input and output DQS + //***************************************************************** + + for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout + // to MC_PHY + assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]] + = in_dqs[m]; + // to I/O buffers + assign out_dqs[m] + = mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; + assign ts_dqs[m] + = mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; + end + endgenerate + + assign pd_out = pd_out_pre[byte_sel_cnt_w1]; + + + //*************************************************************************** + // Memory I/F output and I/O buffer instantiation + //*************************************************************************** + + // Note on instantiation - generally at the minimum, it's not required to + // instantiate the output buffers - they can be inferred by the synthesis + // tool, and there aren't any attributes that need to be associated with + // them. Consider as a future option to take out the OBUF instantiations + + OBUF u_cas_n_obuf + ( + .I (out_cas_n), + .O (ddr_cas_n) + ); + + OBUF u_ras_n_obuf + ( + .I (out_ras_n), + .O (ddr_ras_n) + ); + + OBUF u_we_n_obuf + ( + .I (out_we_n), + .O (ddr_we_n) + ); + + generate + genvar p; + + for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf + OBUF u_addr_obuf + ( + .I (out_addr[p]), + .O (ddr_addr[p]) + ); + end + + for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf + OBUF u_bank_obuf + ( + .I (out_ba[p]), + .O (ddr_ba[p]) + ); + end + + if (USE_CS_PORT == 1) begin: gen_cs_n_obuf + for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf + OBUF u_cs_n_obuf + ( + .I (out_cs_n[p]), + .O (ddr_cs_n[p]) + ); + end + end + if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo + if (USE_ODT_PORT== 1) begin: gen_odt_obuf + for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf + OBUF u_cs_n_obuf + ( + .I (out_odt[p]), + .O (ddr_odt[p]) + ); + end + end + for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf + OBUF u_cs_n_obuf + ( + .I (out_cke[p]), + .O (ddr_cke[p]) + ); + end + end + + if (REG_CTRL == "ON") begin: gen_parity_obuf + // Generate addr/ctrl parity output only for DDR3 registered DIMMs + OBUF u_parity_obuf + ( + .I (out_parity), + .O (ddr_parity) + ); + end else begin: gen_parity_tieoff + assign ddr_parity = 1'b0; + end + + if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf + // Generate reset output only for DDR3 and DDR2 RDIMMs + OBUF u_reset_obuf + ( + .I (mux_reset_n), + .O (ddr_reset_n) + ); + end else begin: gen_reset_tieoff + assign ddr_reset_n = 1'b1; + end + + if (USE_DM_PORT == 1) begin: gen_dm_obuf + for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm + OBUFT u_dm_obuf + ( + .I (out_dm[p]), + .T (ts_dm[p]), + .O (ddr_dm[p]) + ); + end + end else begin: gen_dm_tieoff + assign ddr_dm = 'b0; + end + + if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP + for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf + IOBUF_DCIEN # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR) + ) + u_iobuf_dq + ( + .DCITERMDISABLE (data_io_idle_pwrdwn), + .IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dq[p]), + .T (ts_dq[p]), + .O (in_dq[p]), + .IO (ddr_dq[p]) + ); + end + end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR + for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf + IOBUF_INTERMDISABLE # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR) + ) + u_iobuf_dq + ( + .INTERMDISABLE (data_io_idle_pwrdwn), + .IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dq[p]), + .T (ts_dq[p]), + .O (in_dq[p]), + .IO (ddr_dq[p]) + ); + end + end else begin: gen_dq_iobuf_default + for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf + IOBUF # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR) + ) + u_iobuf_dq + ( + .I (out_dq[p]), + .T (ts_dq[p]), + .O (in_dq[p]), + .IO (ddr_dq[p]) + ); + end + end + + //if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP + if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP + for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf + if ((DRAM_TYPE == "DDR2") && + (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se + IOBUF_DCIEN # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR) + ) + u_iobuf_dqs + ( + .DCITERMDISABLE (data_io_idle_pwrdwn), + .IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dqs[p]), + .T (ts_dqs[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]) + ); + assign ddr_dqs_n[p] = 1'b0; + assign pd_out_pre[p] = 1'b0; + end else if ((DRAM_TYPE == "DDR2") || + (tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff + IOBUFDS_DCIEN # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR), + .DQS_BIAS ("TRUE") + ) + u_iobuf_dqs + ( + .DCITERMDISABLE (data_io_idle_pwrdwn), + .IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dqs[p]), + .T (ts_dqs[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]), + .IOB (ddr_dqs_n[p]) + ); + assign pd_out_pre[p] = 1'b0; + end else begin: gen_dqs_diff + IOBUFDS_DIFF_OUT_DCIEN # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR), + .DQS_BIAS ("TRUE"), + .SIM_DEVICE ("7SERIES"), + .USE_IBUFDISABLE ("FALSE") + ) + u_iobuf_dqs + ( + .DCITERMDISABLE (data_io_idle_pwrdwn), + .I (out_dqs[p]), + .TM (ts_dqs[p]), + .TS (ts_dqs[p]), + .OB (in_dqs_lpbk_to_iddr[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]), + .IOB (ddr_dqs_n[p]) + ); + + mig_7series_v4_0_poc_pd # + ( + .TCQ (TCQ), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) + ) + u_iddr_edge_det + ( + .clk (clk), + .iddr_rst (iddr_rst_i), + .kclk (in_dqs_lpbk_to_iddr[p]), + .mmcm_ps_clk (mmcm_ps_clk), + .pd_out (pd_out_pre[p]) + ); + end + end + //end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR + end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR + for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf + if ((DRAM_TYPE == "DDR2") && + (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se + IOBUF_INTERMDISABLE # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR) + ) + u_iobuf_dqs + ( + .INTERMDISABLE (data_io_idle_pwrdwn), + .IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dqs[p]), + .T (ts_dqs[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]) + ); + assign ddr_dqs_n[p] = 1'b0; + assign pd_out_pre[p] = 1'b0; + end else if ((DRAM_TYPE == "DDR2") || + (tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff + IOBUFDS_INTERMDISABLE # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR), + .DQS_BIAS ("TRUE") + ) + u_iobuf_dqs + ( + .INTERMDISABLE (data_io_idle_pwrdwn), + .IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dqs[p]), + .T (ts_dqs[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]), + .IOB (ddr_dqs_n[p]) + ); + assign pd_out_pre[p] = 1'b0; + end else begin: gen_dqs_diff + IOBUFDS_DIFF_OUT_INTERMDISABLE # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR), + .DQS_BIAS ("TRUE"), + .SIM_DEVICE ("7SERIES"), + .USE_IBUFDISABLE ("FALSE") + ) + u_iobuf_dqs + ( + .INTERMDISABLE (data_io_idle_pwrdwn), + //.IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dqs[p]), + .TM (ts_dqs[p]), + .TS (ts_dqs[p]), + .OB (in_dqs_lpbk_to_iddr[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]), + .IOB (ddr_dqs_n[p]) + ); + + mig_7series_v4_0_poc_pd # + ( + .TCQ (TCQ), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) + ) + u_iddr_edge_det + ( + .clk (clk), + .iddr_rst (iddr_rst_i), + .kclk (in_dqs_lpbk_to_iddr[p]), + .mmcm_ps_clk (mmcm_ps_clk), + .pd_out (pd_out_pre[p]) + ); + end + end + end else begin: gen_dqs_iobuf_default + for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf + if ((DRAM_TYPE == "DDR2") && + (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se + IOBUF # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR) + ) + u_iobuf_dqs + ( + .I (out_dqs[p]), + .T (ts_dqs[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]) + ); + assign ddr_dqs_n[p] = 1'b0; + assign pd_out_pre[p] = 1'b0; + end else begin: gen_dqs_diff + IOBUFDS # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR), + .DQS_BIAS ("TRUE") + ) + u_iobuf_dqs + ( + .I (out_dqs[p]), + .T (ts_dqs[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]), + .IOB (ddr_dqs_n[p]) + ); + assign pd_out_pre[p] = 1'b0; + end + end + end + + endgenerate + + always @(posedge clk) begin + phy_ctl_wd_i1 <= #TCQ phy_ctl_wd; + phy_ctl_wr_i1 <= #TCQ phy_ctl_wr; + phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1; + phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1; + data_offset_1_i1 <= #TCQ data_offset_1; + data_offset_1_i2 <= #TCQ data_offset_1_i1; + data_offset_2_i1 <= #TCQ data_offset_2; + data_offset_2_i2 <= #TCQ data_offset_2_i1; + end + + + // 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it. + // 2:1 mode the command goes through pre fifo + assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of; + assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of; + assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of; + assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of; + + generate + begin + + mig_7series_v4_0_ddr_of_pre_fifo # + ( + .TCQ (25), + .DEPTH (8), + .WIDTH (32) + ) + phy_ctl_pre_fifo_0 + ( + .clk (clk), + .rst (rst), + .full_in (phy_ctl_full_temp[1]), + .wr_en_in (phy_ctl_wr), + .d_in (phy_ctl_wd), + .wr_en_out (phy_ctl_wr_of), + .d_out (phy_ctl_wd_of) + ); + + mig_7series_v4_0_ddr_of_pre_fifo # + ( + .TCQ (25), + .DEPTH (8), + .WIDTH (6) + ) + phy_ctl_pre_fifo_1 + ( + .clk (clk), + .rst (rst), + .full_in (phy_ctl_full_temp[2]), + .wr_en_in (phy_ctl_wr), + .d_in (data_offset_1), + .wr_en_out (), + .d_out (data_offset_1_of) + ); + + mig_7series_v4_0_ddr_of_pre_fifo # + ( + .TCQ (25), + .DEPTH (8), + .WIDTH (6) + ) + phy_ctl_pre_fifo_2 + ( + .clk (clk), + .rst (rst), + .full_in (phy_ctl_full_temp[3]), + .wr_en_in (phy_ctl_wr), + .d_in (data_offset_2), + .wr_en_out (), + .d_out (data_offset_2_of) + ); + + end + endgenerate + + + + //*************************************************************************** + // Hard PHY instantiation + //*************************************************************************** + + assign phy_ctl_full = phy_ctl_full_temp[0]; + + mig_7series_v4_0_ddr_mc_phy # + ( + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4), + .PHY_0_BITLANES (PHY_0_BITLANES), + .PHY_1_BITLANES (PHY_1_BITLANES), + .PHY_2_BITLANES (PHY_2_BITLANES), + .PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY), + .PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY), + .PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY), + .RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK), + .RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE), + //.CKE_ODT_AUX (CKE_ODT_AUX), + .GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP), + .BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK), + .NUM_DDR_CK (CK_WIDTH), + .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH), + .PO_CTL_COARSE_BYPASS ("FALSE"), + .PHYCTL_CMD_FIFO ("FALSE"), + .PHY_CLK_RATIO (nCK_PER_CLK), + .MASTER_PHY_CTL (MASTER_PHY_CTL), + .PHY_FOUR_WINDOW_CLOCKS (63), + .PHY_EVENTS_DELAY (18), + .PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN + .PHY_SYNC_MODE ("FALSE"), + .SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"), + .PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE" + .PHY_0_GENERATE_IDELAYCTRL ("FALSE"), + .PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV), + .PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE + .PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0), + .PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1), + .PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2), + .PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3), + .PHY_0_RD_DURATION_0 (6), + .PHY_0_RD_DURATION_1 (6), + .PHY_0_RD_DURATION_2 (6), + .PHY_0_RD_DURATION_3 (6), + .PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0), + .PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1), + .PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2), + .PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3), + .PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0), + .PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1), + .PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2), + .PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3), + .PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5), + .PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV), + .PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_1_GENERATE_IDELAYCTRL ("FALSE"), + //.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK), + //.PHY_1_NUM_DDR_CK (1), + .PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_2_GENERATE_IDELAYCTRL ("FALSE"), + //.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK), + //.PHY_2_NUM_DDR_CK (1), + .PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .TCK (tCK), + .PHY_0_IODELAY_GRP (IODELAY_GRP), + .PHY_1_IODELAY_GRP (IODELAY_GRP), + .PHY_2_IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .CKE_ODT_AUX (CKE_ODT_AUX), + .PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + u_ddr_mc_phy + ( + .rst (rst), + // Don't use MC_PHY to generate DDR_RESET_N output. Instead + // generate this output outside of MC_PHY (and synchronous to CLK) + .ddr_rst_in_n (1'b1), + .phy_clk (clk), + .clk_div2 (clk_div2), + .freq_refclk (freq_refclk), + .mem_refclk (mem_refclk), + // Remove later - always same connection as phy_clk port + .mem_refclk_div4 (clk), + .pll_lock (pll_lock), + .auxout_clk (), + .sync_pulse (sync_pulse), + // IDELAYCTRL instantiated outside of mc_phy module + .idelayctrl_refclk (), + .phy_dout (phy_dout), + .phy_cmd_wr_en (phy_cmd_wr_en), + .phy_data_wr_en (phy_data_wr_en), + .phy_rd_en (phy_rd_en), + .phy_ctl_wd (phy_ctl_wd_temp), + .phy_ctl_wr (phy_ctl_wr_temp), + .if_empty_def (phy_if_empty_def), + .if_rst (phy_if_reset), + .phyGo ('b1), + .aux_in_1 (aux_in_1), + .aux_in_2 (aux_in_2), + // No support yet for different data offsets for different I/O banks + // (possible use in supporting wider range of skew among bytes) + .data_offset_1 (data_offset_1_temp), + .data_offset_2 (data_offset_2_temp), + .cke_in (), + .if_a_empty (), + .if_empty (if_empty), + .if_empty_or (), + .if_empty_and (), + .of_ctl_a_full (), + // .of_data_a_full (phy_data_full), + .of_ctl_full (phy_cmd_full), + .of_data_full (), + .pre_data_a_full (phy_pre_data_a_full), + .idelay_ld (idelay_ld), + .idelay_ce (idelay_ce), + .idelay_inc (idelay_inc), + .input_sink (), + .phy_din (phy_din), + .phy_ctl_a_full (), + .phy_ctl_full (phy_ctl_full_temp), + .mem_dq_out (mem_dq_out), + .mem_dq_ts (mem_dq_ts), + .mem_dq_in (mem_dq_in), + .mem_dqs_out (mem_dqs_out), + .mem_dqs_ts (mem_dqs_ts), + .mem_dqs_in (mem_dqs_in), + .aux_out (aux_out), + .phy_ctl_ready (), + .rst_out (), + .ddr_clk (ddr_clk), + //.rclk (), + .mcGo (phy_mc_go), + .phy_write_calib (phy_write_calib), + .phy_read_calib (phy_read_calib), + .calib_sel (calib_sel), + .calib_in_common (calib_in_common), + .calib_zero_inputs (calib_zero_inputs), + .calib_zero_ctrl (calib_zero_ctrl), + .calib_zero_lanes ('b0), + .po_fine_enable (po_fine_enable), + .po_coarse_enable (po_coarse_enable), + .po_fine_inc (po_fine_inc), + .po_coarse_inc (po_coarse_inc), + .po_counter_load_en (po_counter_load_en), + .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay), + .po_counter_load_val (po_counter_load_val), + .po_counter_read_en (po_counter_read_en), + .po_coarse_overflow (), + .po_fine_overflow (), + .po_counter_read_val (po_counter_read_val), + .pi_rst_dqs_find (pi_rst_dqs_find), + .pi_fine_enable (pi_fine_enable), + .pi_fine_inc (pi_fine_inc), + .pi_counter_load_en (pi_counter_load_en), + .pi_counter_read_en (dbg_pi_counter_read_en), + .pi_counter_load_val (pi_counter_load_val), + .pi_fine_overflow (), + .pi_counter_read_val (pi_counter_read_val), + .pi_phase_locked (pi_phase_locked), + .pi_phase_locked_all (pi_phase_locked_all), + .pi_dqs_found (), + .pi_dqs_found_any (pi_dqs_found), + .pi_dqs_found_all (pi_dqs_found_all), + .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes), + // Currently not being used. May be used in future if periodic + // reads become a requirement. This output could be used to signal + // a catastrophic failure in read capture and the need for + // re-calibration. + .pi_dqs_out_of_range (pi_dqs_out_of_range) + + ,.ref_dll_lock (ref_dll_lock) + ,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes) + ,.fine_delay (fine_delay_mod) + ,.fine_delay_sel (fine_delay_sel_r) +// ,.rst_phaser_ref (rst_phaser_ref) + ); + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_of_pre_fifo.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_of_pre_fifo.v new file mode 100644 index 0000000..e496c23 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_of_pre_fifo.v @@ -0,0 +1,210 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : ddr_of_pre_fifo.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Feb 08 2011 +// \___\/\___\ +// +//Device : 7 Series +//Design Name : DDR3 SDRAM +//Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries +//Reference : +//Revision History : +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $ +**$Date: 2011/06/02 08:35:07 $ +**$Author: mishra $ +**$Revision: 1.1 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $ +******************************************************************************/ + +`timescale 1 ps / 1 ps + +module mig_7series_v4_0_ddr_of_pre_fifo # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter DEPTH = 4, // # of entries + parameter WIDTH = 32 // data bus width + ) + ( + input clk, // clock + input rst, // synchronous reset + input full_in, // FULL flag from OUT_FIFO + input wr_en_in, // write enable from controller + input [WIDTH-1:0] d_in, // write data from controller + output wr_en_out, // write enable to OUT_FIFO + output [WIDTH-1:0] d_out, // write data to OUT_FIFO + output afull // almost full signal to controller + ); + + // # of bits used to represent read/write pointers + localparam PTR_BITS + = (DEPTH == 2) ? 1 : + ((DEPTH == 3) || (DEPTH == 4)) ? 2 : + (((DEPTH == 5) || (DEPTH == 6) || + (DEPTH == 7) || (DEPTH == 8)) ? 3 : + DEPTH == 9 ? 4 : 'bx); + + // Set watermark. Always give the MC 5 cycles to engage flow control. + localparam ALMOST_FULL_VALUE = DEPTH - 5; + + integer i; + + reg [WIDTH-1:0] mem[0:DEPTH-1] ; + reg [8:0] my_empty /* synthesis syn_maxfan = 3 */; + reg [5:0] my_full /* synthesis syn_maxfan = 3 */; + reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */; + reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */; + (* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */; + (* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */; + reg [PTR_BITS:0] entry_cnt; + wire [PTR_BITS-1:0] nxt_rd_ptr; + wire [PTR_BITS-1:0] nxt_wr_ptr; + wire [WIDTH-1:0] mem_out; + (* max_fanout = 50 *) wire wr_en; + + assign d_out = my_empty[0] ? d_in : mem_out; + assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in); + assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in)); + + always @ (posedge clk) + if (wr_en) + mem[wr_ptr] <= #TCQ d_in; + + assign mem_out = mem[rd_ptr]; + + assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH; + + always @ (posedge clk) + begin + if (rst) begin + rd_ptr <= 'b0; + rd_ptr_timing <= 'b0; + end + else if ((!my_empty[4]) & (!full_in)) begin + rd_ptr <= nxt_rd_ptr; + rd_ptr_timing <= nxt_rd_ptr; + end + end + + always @ (posedge clk) + begin + if (rst) + my_empty <= 9'h1ff; + else begin + if (my_empty[2] & !my_full[3] & full_in & wr_en_in) + my_empty[3:0] <= 4'b0000; + else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin + my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing); + end + if (my_empty[8] & !my_full[5] & full_in & wr_en_in) + my_empty[8:4] <= 5'b00000; + else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin + my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing); + end + end + end + + assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH; + + always @ (posedge clk) + begin + if (rst) begin + wr_ptr <= 'b0; + wr_ptr_timing <= 'b0; + end + else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin + wr_ptr <= nxt_wr_ptr; + wr_ptr_timing <= nxt_wr_ptr; + end + end + + always @ (posedge clk) + begin + if (rst) + my_full <= 6'b000000; + else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in) + my_full <= 6'b000000; + else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin + my_full[0] <= (nxt_wr_ptr == rd_ptr_timing); + my_full[1] <= (nxt_wr_ptr == rd_ptr_timing); + my_full[2] <= (nxt_wr_ptr == rd_ptr_timing); + my_full[3] <= (nxt_wr_ptr == rd_ptr_timing); + my_full[4] <= (nxt_wr_ptr == rd_ptr_timing); + my_full[5] <= (nxt_wr_ptr == rd_ptr_timing); + end + end + + always @ (posedge clk) + begin + if (rst) + entry_cnt <= 'b0; + else if (wr_en_in & full_in & !my_full[4]) + entry_cnt <= entry_cnt + 1'b1; + else if (!wr_en_in & !full_in & !my_empty[7]) + entry_cnt <= entry_cnt - 1'b1; + end + + assign afull = (entry_cnt >= ALMOST_FULL_VALUE); + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_4lanes.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_4lanes.v new file mode 100644 index 0000000..847fcd4 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_4lanes.v @@ -0,0 +1,2056 @@ +/********************************************************** +-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). A Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +// +// THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +// +// +// Owner: Gary Martin +// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $ +// $Author: gary $ +// $DateTime: 2010/05/11 18:05:17 $ +// $Change: 490882 $ +// Description: +// This verilog file is the parameterizable 4-byte lane phy primitive top +// This module may be ganged to create an N-lane phy. +// +// History: +// Date Engineer Description +// 04/01/2010 G. Martin Initial Checkin. +// +/////////////////////////////////////////////////////////// +**********************************************************/ + +`timescale 1ps/1ps + +`define PC_DATA_OFFSET_RANGE 22:17 + +module mig_7series_v4_0_ddr_phy_4lanes #( +parameter GENERATE_IDELAYCTRL = "TRUE", +parameter IODELAY_GRP = "IODELAY_MIG", +parameter FPGA_SPEED_GRADE = 1, +parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" +parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010, +parameter NUM_DDR_CK = 1, +// next three parameter fields correspond to byte lanes for lane order DCBA +parameter BYTE_LANES = 4'b1111, // lane existence, one per lane +parameter DATA_CTL_N = 4'b1111, // data or control, per lane +parameter BITLANES = 48'hffff_ffff_ffff, +parameter BITLANES_OUTONLY = 48'h0000_0000_0000, +parameter LANE_REMAP = 16'h3210,// 4-bit index + // used to rewire to one of four + // input/output buss lanes + // example: 0321 remaps lanes as: + // D->A + // C->D + // B->C + // A->B +parameter LAST_BANK = "FALSE", +parameter USE_PRE_POST_FIFO = "FALSE", +parameter RCLK_SELECT_LANE = "B", +parameter real TCK = 0.00, +parameter SYNTHESIS = "FALSE", +parameter PO_CTL_COARSE_BYPASS = "FALSE", +parameter PO_FINE_DELAY = 0, +parameter PI_SEL_CLK_OFFSET = 0, + +// phy_control paramter used in other paramsters +parameter PC_CLK_RATIO = 4, + +//phaser_in parameters +parameter A_PI_FREQ_REF_DIV = "NONE", +parameter A_PI_CLKOUT_DIV = 2, +parameter A_PI_BURST_MODE = "TRUE", +parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF", +parameter A_PI_FINE_DELAY = 60, +parameter A_PI_SYNC_IN_DIV_RST = "TRUE", + +parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, +parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, +parameter B_PI_BURST_MODE = A_PI_BURST_MODE, +parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, +parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY, +parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, + +parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, +parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, +parameter C_PI_BURST_MODE = A_PI_BURST_MODE, +parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, +parameter C_PI_FINE_DELAY = 0, +parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, + +parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, +parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, +parameter D_PI_BURST_MODE = A_PI_BURST_MODE, +parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, +parameter D_PI_FINE_DELAY = 0, +parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, + +//phaser_out parameters +parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2, +parameter A_PO_FINE_DELAY = PO_FINE_DELAY, +parameter A_PO_COARSE_DELAY = 0, +parameter A_PO_OCLK_DELAY = 0, +parameter A_PO_OCLKDELAY_INV = "FALSE", +parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF", +parameter A_PO_SYNC_IN_DIV_RST = "TRUE", +//parameter A_PO_SYNC_IN_DIV_RST = "FALSE", + +parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2, +parameter B_PO_FINE_DELAY = PO_FINE_DELAY, +parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY, +parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY, +parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, +parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, +parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, + +parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2, +parameter C_PO_FINE_DELAY = PO_FINE_DELAY, +parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY, +parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY, +parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, +parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, +parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, + +parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2, +parameter D_PO_FINE_DELAY = PO_FINE_DELAY, +parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY, +parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY, +parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, +parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, +parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, + +parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE", +parameter A_IDELAYE2_IDELAY_VALUE = 00, +parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, +parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, +parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, +parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, +parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, +parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, + + +// phy_control parameters + +parameter PC_BURST_MODE = "TRUE", +parameter PC_DATA_CTL_N = DATA_CTL_N, +parameter PC_CMD_OFFSET = 0, +parameter PC_RD_CMD_OFFSET_0 = 0, +parameter PC_RD_CMD_OFFSET_1 = 0, +parameter PC_RD_CMD_OFFSET_2 = 0, +parameter PC_RD_CMD_OFFSET_3 = 0, +parameter PC_CO_DURATION = 1, +parameter PC_DI_DURATION = 1, +parameter PC_DO_DURATION = 1, +parameter PC_RD_DURATION_0 = 0, +parameter PC_RD_DURATION_1 = 0, +parameter PC_RD_DURATION_2 = 0, +parameter PC_RD_DURATION_3 = 0, +parameter PC_WR_CMD_OFFSET_0 = 5, +parameter PC_WR_CMD_OFFSET_1 = 5, +parameter PC_WR_CMD_OFFSET_2 = 5, +parameter PC_WR_CMD_OFFSET_3 = 5, +parameter PC_WR_DURATION_0 = 6, +parameter PC_WR_DURATION_1 = 6, +parameter PC_WR_DURATION_2 = 6, +parameter PC_WR_DURATION_3 = 6, +parameter PC_AO_WRLVL_EN = 0, +parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE) +parameter PC_FOUR_WINDOW_CLOCKS = 63, +parameter PC_EVENTS_DELAY = 18, +parameter PC_PHY_COUNT_EN = "TRUE", +parameter PC_SYNC_MODE = "TRUE", +parameter PC_DISABLE_SEQ_MATCH = "TRUE", +parameter PC_MULTI_REGION = "FALSE", + +// io fifo parameters + +parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", +parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", +parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", +parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", +parameter OF_ALMOST_EMPTY_VALUE = 1, +parameter OF_ALMOST_FULL_VALUE = 1, +parameter OF_OUTPUT_DISABLE = "TRUE", +parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE, + +parameter A_OS_DATA_RATE = "DDR", +parameter A_OS_DATA_WIDTH = 4, +parameter B_OS_DATA_RATE = A_OS_DATA_RATE, +parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH, +parameter C_OS_DATA_RATE = A_OS_DATA_RATE, +parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH, +parameter D_OS_DATA_RATE = A_OS_DATA_RATE, +parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH, + + +parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8", +parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE, +parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE, +parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE, +parameter IF_ALMOST_EMPTY_VALUE = 1, +parameter IF_ALMOST_FULL_VALUE = 1, +parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE, + + +// this is used locally, not for external pushdown +// NOTE: the 0+ is needed in each to coerce to integer for addition. +// otherwise 4x 1'b values are added producing a 1'b value. +parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1), +parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])), + +parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]), + +parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES, +// assume odt per rank + any declared cke's +parameter AUXOUT_WIDTH = 4, +parameter LP_DDR_CK_WIDTH = 2 +,parameter CKE_ODT_AUX = "FALSE" +,parameter PI_DIV2_INCDEC = "FALSE" +) +( + +//`include "phy.vh" + + input rst, + input phy_clk, + input clk_div2, + input phy_ctl_clk, + input freq_refclk, + input mem_refclk, + input mem_refclk_div4, + input pll_lock, + input sync_pulse, + input idelayctrl_refclk, + input [HIGHEST_LANE*80-1:0] phy_dout, + input phy_cmd_wr_en, + input phy_data_wr_en, + input phy_rd_en, + input phy_ctl_mstr_empty, + input [31:0] phy_ctl_wd, + input [`PC_DATA_OFFSET_RANGE] data_offset, + input phy_ctl_wr, + input if_empty_def, + input phyGo, + input input_sink, + + output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory + output rclk, + output if_a_empty, + output if_empty, + output byte_rd_en, + output if_empty_or, + output if_empty_and, + output of_ctl_a_full, + output of_data_a_full, + output of_ctl_full, + output of_data_full, + output pre_data_a_full, + output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus + output phy_ctl_empty, + output phy_ctl_a_full, + output phy_ctl_full, + output [HIGHEST_LANE*12-1:0]mem_dq_out, + output [HIGHEST_LANE*12-1:0]mem_dq_ts, + input [HIGHEST_LANE*10-1:0]mem_dq_in, + output [HIGHEST_LANE-1:0] mem_dqs_out, + output [HIGHEST_LANE-1:0] mem_dqs_ts, + input [HIGHEST_LANE-1:0] mem_dqs_in, + input [1:0] byte_rd_en_oth_banks, + + output [AUXOUT_WIDTH-1:0] aux_out, + output reg rst_out = 0, + output reg mcGo=0, + output phy_ctl_ready, + output ref_dll_lock, + input if_rst, + input phy_read_calib, + input phy_write_calib, + input idelay_inc, + input idelay_ce, + input idelay_ld, + input [2:0] calib_sel, + input calib_zero_ctrl, + input [HIGHEST_LANE-1:0] calib_zero_lanes, + input calib_in_common, + input po_fine_enable, + input po_coarse_enable, + input po_fine_inc, + input po_coarse_inc, + input po_counter_load_en, + input po_counter_read_en, + input [8:0] po_counter_load_val, + input po_sel_fine_oclk_delay, + output reg po_coarse_overflow, + output reg po_fine_overflow, + output reg [8:0] po_counter_read_val, + + + + input pi_rst_dqs_find, + input pi_fine_enable, + input pi_fine_inc, + input pi_counter_load_en, + input pi_counter_read_en, + input [5:0] pi_counter_load_val, + output reg pi_fine_overflow, + output reg [5:0] pi_counter_read_val, + + output reg pi_dqs_found, + output pi_dqs_found_all, + output pi_dqs_found_any, + output [HIGHEST_LANE-1:0] pi_phase_locked_lanes, + output [HIGHEST_LANE-1:0] pi_dqs_found_lanes, + output reg pi_dqs_out_of_range, + output reg pi_phase_locked, + output pi_phase_locked_all, + input [29:0] fine_delay, + input fine_delay_sel +); + +localparam DATA_CTL_A = (~DATA_CTL_N[0]); +localparam DATA_CTL_B = (~DATA_CTL_N[1]); +localparam DATA_CTL_C = (~DATA_CTL_N[2]); +localparam DATA_CTL_D = (~DATA_CTL_N[3]); +localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0]; +localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1]; +localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2]; +localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3]; +localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0]; +localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1]; +localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2]; +localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3]; +localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE"; +localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE"; +localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE"; +localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE"; +localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE"; +localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE"; +localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE"; +localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE"; + +localparam IO_A_START = 41; +localparam IO_A_END = 40; +localparam IO_B_START = 43; +localparam IO_B_END = 42; +localparam IO_C_START = 45; +localparam IO_C_END = 44; +localparam IO_D_START = 47; +localparam IO_D_END = 46; +localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1; +localparam IO_A_X_END = (IO_A_X_START-1); +localparam IO_B_X_START = (IO_A_X_START + 2); +localparam IO_B_X_END = (IO_B_X_START -1); +localparam IO_C_X_START = (IO_B_X_START + 2); +localparam IO_C_X_END = (IO_C_X_START -1); +localparam IO_D_X_START = (IO_C_X_START + 2); +localparam IO_D_X_END = (IO_D_X_START -1); + +localparam MSB_BURST_PEND_PO = 3; +localparam MSB_BURST_PEND_PI = 7; +localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8; +localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1; + +wire [1:0] oserdes_dqs; +wire [1:0] oserdes_dqs_ts; +wire [1:0] oserdes_dq_ts; + + +wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus; +wire [7:0] in_rank; +wire [11:0] IO_A; +wire [11:0] IO_B; +wire [11:0] IO_C; +wire [11:0] IO_D; + +wire [319:0] phy_din_remap; + +reg A_po_counter_read_en; +wire [8:0] A_po_counter_read_val; +reg A_pi_counter_read_en; +wire [5:0] A_pi_counter_read_val; +wire A_pi_fine_overflow; +wire A_po_coarse_overflow; +wire A_po_fine_overflow; +wire A_pi_dqs_found; +wire A_pi_dqs_out_of_range; +wire A_pi_phase_locked; +wire A_pi_iserdes_rst; +reg A_pi_fine_enable; +reg A_pi_fine_inc; +reg A_pi_counter_load_en; +reg [5:0] A_pi_counter_load_val; +reg A_pi_rst_dqs_find; + + +reg A_po_fine_enable; +reg A_po_coarse_enable; + reg A_po_fine_inc /* synthesis syn_maxfan = 3 */; +reg A_po_sel_fine_oclk_delay; +reg A_po_coarse_inc; +reg A_po_counter_load_en; +reg [8:0] A_po_counter_load_val; +wire A_rclk; +reg A_idelay_ce; +reg A_idelay_ld; +reg [29:0] A_fine_delay; +reg A_fine_delay_sel; + +reg B_po_counter_read_en; +wire [8:0] B_po_counter_read_val; +reg B_pi_counter_read_en; +wire [5:0] B_pi_counter_read_val; +wire B_pi_fine_overflow; +wire B_po_coarse_overflow; +wire B_po_fine_overflow; +wire B_pi_phase_locked; +wire B_pi_iserdes_rst; +wire B_pi_dqs_found; +wire B_pi_dqs_out_of_range; +reg B_pi_fine_enable; +reg B_pi_fine_inc; +reg B_pi_counter_load_en; +reg [5:0] B_pi_counter_load_val; +reg B_pi_rst_dqs_find; + + +reg B_po_fine_enable; +reg B_po_coarse_enable; + reg B_po_fine_inc /* synthesis syn_maxfan = 3 */; +reg B_po_coarse_inc; +reg B_po_sel_fine_oclk_delay; +reg B_po_counter_load_en; +reg [8:0] B_po_counter_load_val; +wire B_rclk; +reg B_idelay_ce; +reg B_idelay_ld; +reg [29:0] B_fine_delay; +reg B_fine_delay_sel; + + +reg C_pi_fine_inc; +reg D_pi_fine_inc; +reg C_pi_fine_enable; +reg D_pi_fine_enable; +reg C_po_counter_load_en; +reg D_po_counter_load_en; +reg C_po_coarse_inc; +reg D_po_coarse_inc; + reg C_po_fine_inc /* synthesis syn_maxfan = 3 */; + reg D_po_fine_inc /* synthesis syn_maxfan = 3 */; +reg C_po_sel_fine_oclk_delay; +reg D_po_sel_fine_oclk_delay; +reg [5:0] C_pi_counter_load_val; +reg [5:0] D_pi_counter_load_val; +reg [8:0] C_po_counter_load_val; +reg [8:0] D_po_counter_load_val; +reg C_po_coarse_enable; +reg D_po_coarse_enable; +reg C_po_fine_enable; +reg D_po_fine_enable; +wire C_po_coarse_overflow; +wire D_po_coarse_overflow; +wire C_po_fine_overflow; +wire D_po_fine_overflow; +wire [8:0] C_po_counter_read_val; +wire [8:0] D_po_counter_read_val; +reg C_po_counter_read_en; +reg D_po_counter_read_en; +wire C_pi_dqs_found; +wire D_pi_dqs_found; +wire C_pi_fine_overflow; +wire D_pi_fine_overflow; +reg C_pi_counter_read_en; +reg D_pi_counter_read_en; +reg C_pi_counter_load_en; +reg D_pi_counter_load_en; +wire C_pi_phase_locked; +wire C_pi_iserdes_rst; +wire D_pi_phase_locked; +wire D_pi_iserdes_rst; +wire C_pi_dqs_out_of_range; +wire D_pi_dqs_out_of_range; +wire [5:0] C_pi_counter_read_val; +wire [5:0] D_pi_counter_read_val; +wire C_rclk; +wire D_rclk; +reg C_idelay_ce; +reg D_idelay_ce; +reg C_idelay_ld; +reg D_idelay_ld; +reg C_pi_rst_dqs_find; +reg D_pi_rst_dqs_find; +reg [29:0] C_fine_delay; +reg [29:0] D_fine_delay; +reg C_fine_delay_sel; +reg D_fine_delay_sel; + +wire pi_iserdes_rst; + +wire A_if_empty; +wire B_if_empty; +wire C_if_empty; +wire D_if_empty; +wire A_byte_rd_en; +wire B_byte_rd_en; +wire C_byte_rd_en; +wire D_byte_rd_en; +wire A_if_a_empty; +wire B_if_a_empty; +wire C_if_a_empty; +wire D_if_a_empty; +//wire A_if_full; +//wire B_if_full; +//wire C_if_full; +//wire D_if_full; +//wire A_of_empty; +//wire B_of_empty; +//wire C_of_empty; +//wire D_of_empty; +wire A_of_full; +wire B_of_full; +wire C_of_full; +wire D_of_full; +wire A_of_ctl_full; +wire B_of_ctl_full; +wire C_of_ctl_full; +wire D_of_ctl_full; +wire A_of_data_full; +wire B_of_data_full; +wire C_of_data_full; +wire D_of_data_full; +wire A_of_a_full; +wire B_of_a_full; +wire C_of_a_full; +wire D_of_a_full; +wire A_pre_fifo_a_full; +wire B_pre_fifo_a_full; +wire C_pre_fifo_a_full; +wire D_pre_fifo_a_full; +wire A_of_ctl_a_full; +wire B_of_ctl_a_full; +wire C_of_ctl_a_full; +wire D_of_ctl_a_full; +wire A_of_data_a_full; +wire B_of_data_a_full; +wire C_of_data_a_full; +wire D_of_data_a_full; +wire A_pre_data_a_full; +wire B_pre_data_a_full; +wire C_pre_data_a_full; +wire D_pre_data_a_full; +wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation +wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; // +wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; // +wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; // + +wire [3:0] dummy_data; + +wire [31:0] _phy_ctl_wd; + +wire [1:0] phy_encalib; + +assign pi_dqs_found_all = + (! PRESENT_DATA_A | A_pi_dqs_found) & + (! PRESENT_DATA_B | B_pi_dqs_found) & + (! PRESENT_DATA_C | C_pi_dqs_found) & + (! PRESENT_DATA_D | D_pi_dqs_found) ; + +assign pi_dqs_found_any = + ( PRESENT_DATA_A & A_pi_dqs_found) | + ( PRESENT_DATA_B & B_pi_dqs_found) | + ( PRESENT_DATA_C & C_pi_dqs_found) | + ( PRESENT_DATA_D & D_pi_dqs_found) ; + +assign pi_phase_locked_all = + (! PRESENT_DATA_A | A_pi_phase_locked) & + (! PRESENT_DATA_B | B_pi_phase_locked) & + (! PRESENT_DATA_C | C_pi_phase_locked) & + (! PRESENT_DATA_D | D_pi_phase_locked); + +wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal + // which is combined into another signals such that + // the other signal isn't changed. The purpose + // is to fake the tools into ignoring dangling inputs. + // Because it is anded with 1'b0, the contributing signals + // are folded as constants or trimmed. + + +assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty); +assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) : + (A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en); +assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty); +assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty); +assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty; +//assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ; +//assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty; +assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ; +assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ; +assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ; +assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ; +assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full; + + +function [79:0] part_select_80; +input [319:0] vector; +input [1:0] select; +begin + case (select) + 2'b00 : part_select_80[79:0] = vector[1*80-1:0*80]; + 2'b01 : part_select_80[79:0] = vector[2*80-1:1*80]; + 2'b10 : part_select_80[79:0] = vector[3*80-1:2*80]; + 2'b11 : part_select_80[79:0] = vector[4*80-1:3*80]; + endcase +end +endfunction + +wire [319:0] phy_dout_remap; + +reg rst_out_trig = 1'b0; +reg [31:0] rclk_delay; +reg rst_edge1 = 1'b0; +reg rst_edge2 = 1'b0; +reg rst_edge3 = 1'b0; +reg rst_edge_detect = 1'b0; +wire rclk_; +reg rst_out_start = 1'b0 ; +reg rst_primitives=0; +reg A_rst_primitives=0; +reg B_rst_primitives=0; +reg C_rst_primitives=0; +reg D_rst_primitives=0; + +`ifdef USE_PHY_CONTROL_TEST + wire [15:0] test_output; + wire [15:0] test_input; + wire [2:0] test_select=0; + wire scan_enable = 0; +`endif + +generate + +genvar i; + +if (RCLK_SELECT_LANE == "A") begin + assign rclk_ = A_rclk; + assign pi_iserdes_rst = A_pi_iserdes_rst; + end +else if (RCLK_SELECT_LANE == "B") begin + assign rclk_ = B_rclk; + assign pi_iserdes_rst = B_pi_iserdes_rst; + end +else if (RCLK_SELECT_LANE == "C") begin + assign rclk_ = C_rclk; + assign pi_iserdes_rst = C_pi_iserdes_rst; + end +else if (RCLK_SELECT_LANE == "D") begin + assign rclk_ = D_rclk; + assign pi_iserdes_rst = D_pi_iserdes_rst; + end +else begin + assign rclk_ = B_rclk; // default + end + +endgenerate + +assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk; +assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk; +assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk; +assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk; + +assign pi_phase_locked_lanes = + {(! PRESENT_DATA_D[0] | D_pi_phase_locked), + (! PRESENT_DATA_C[0] | C_pi_phase_locked) , + (! PRESENT_DATA_B[0] | B_pi_phase_locked) , + (! PRESENT_DATA_A[0] | A_pi_phase_locked)}; + +assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found}; + +// this block scrubs X from rclk_delay[11] +reg rclk_delay_11; +always @(rclk_delay[11]) begin : rclk_delay_11_blk + if ( rclk_delay[11]) + rclk_delay_11 = 1; + else + rclk_delay_11 = 0; +end + +always @(posedge phy_clk or posedge rst ) begin +// scrub 4-state values from rclk_delay[11] + if ( rst) begin + rst_out <= #1 0; + end + else begin + if ( rclk_delay_11) + rst_out <= #1 1; + end +end + +always @(posedge phy_clk ) begin + // phy_ctl_ready drives reset of the system + rst_primitives <= !phy_ctl_ready ; + A_rst_primitives <= rst_primitives ; + B_rst_primitives <= rst_primitives ; + C_rst_primitives <= rst_primitives ; + D_rst_primitives <= rst_primitives ; + + rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo); + mcGo <= #1 rst_out ; + +end + +//reset synchronized to clk_div2 + (* ASYNC_REG = "TRUE" *) reg A_pi_rst_div2; + (* ASYNC_REG = "TRUE" *) reg B_pi_rst_div2; + (* ASYNC_REG = "TRUE" *) reg C_pi_rst_div2; + (* ASYNC_REG = "TRUE" *) reg D_pi_rst_div2; +generate + if (PI_DIV2_INCDEC == "TRUE") begin: phaser_in_div2 + (* ASYNC_REG = "TRUE" *) reg pi_rst_div2r1; + (* ASYNC_REG = "TRUE" *) reg pi_rst_div2r2; + + always @(posedge clk_div2) begin + pi_rst_div2r1 <= rst_primitives; + pi_rst_div2r2 <= pi_rst_div2r1; + A_pi_rst_div2 <= pi_rst_div2r2; + B_pi_rst_div2 <= pi_rst_div2r2; + C_pi_rst_div2 <= pi_rst_div2r2; + D_pi_rst_div2 <= pi_rst_div2r2; + end + end else begin: phaser_in_div4 + always @ (*) begin + A_pi_rst_div2 <= 1'b0; + B_pi_rst_div2 <= 1'b0; + C_pi_rst_div2 <= 1'b0; + D_pi_rst_div2 <= 1'b0; + end + end +endgenerate + +generate + + if (BYTE_LANES[0]) begin + assign dummy_data[0] = 0; + end + else begin + assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80]; + end + if (BYTE_LANES[1]) begin + assign dummy_data[1] = 0; + end + else begin + assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80]; + end + if (BYTE_LANES[2]) begin + assign dummy_data[2] = 0; + end + else begin + assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80]; + end + if (BYTE_LANES[3]) begin + assign dummy_data[3] = 0; + end + else begin + assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80]; + end + + if (PRESENT_DATA_A) begin + assign A_of_data_full = A_of_full; + assign A_of_ctl_full = 0; + assign A_of_data_a_full = A_of_a_full; + assign A_of_ctl_a_full = 0; + assign A_pre_data_a_full = A_pre_fifo_a_full; + end + else begin + assign A_of_ctl_full = A_of_full; + assign A_of_data_full = 0; + assign A_of_ctl_a_full = A_of_a_full; + assign A_of_data_a_full = 0; + assign A_pre_data_a_full = 0; + end + if (PRESENT_DATA_B) begin + assign B_of_data_full = B_of_full; + assign B_of_ctl_full = 0; + assign B_of_data_a_full = B_of_a_full; + assign B_of_ctl_a_full = 0; + assign B_pre_data_a_full = B_pre_fifo_a_full; + end + else begin + assign B_of_ctl_full = B_of_full; + assign B_of_data_full = 0; + assign B_of_ctl_a_full = B_of_a_full; + assign B_of_data_a_full = 0; + assign B_pre_data_a_full = 0; + end + if (PRESENT_DATA_C) begin + assign C_of_data_full = C_of_full; + assign C_of_ctl_full = 0; + assign C_of_data_a_full = C_of_a_full; + assign C_of_ctl_a_full = 0; + assign C_pre_data_a_full = C_pre_fifo_a_full; + end + else begin + assign C_of_ctl_full = C_of_full; + assign C_of_data_full = 0; + assign C_of_ctl_a_full = C_of_a_full; + assign C_of_data_a_full = 0; + assign C_pre_data_a_full = 0; + end + if (PRESENT_DATA_D) begin + assign D_of_data_full = D_of_full; + assign D_of_ctl_full = 0; + assign D_of_data_a_full = D_of_a_full; + assign D_of_ctl_a_full = 0; + assign D_pre_data_a_full = D_pre_fifo_a_full; + end + else begin + assign D_of_ctl_full = D_of_full; + assign D_of_data_full = 0; + assign D_of_ctl_a_full = D_of_a_full; + assign D_of_data_a_full = 0; + assign D_pre_data_a_full = 0; + end +// byte lane must exist and be data lane. + if (PRESENT_DATA_A ) + case ( LANE_REMAP[1:0] ) + 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0]; + 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0]; + 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0]; + 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0]; + endcase + else + case ( LANE_REMAP[1:0] ) + 2'b00 : assign phy_din[1*80-1:0] = 80'h0; + 2'b01 : assign phy_din[2*80-1:80] = 80'h0; + 2'b10 : assign phy_din[3*80-1:160] = 80'h0; + 2'b11 : assign phy_din[4*80-1:240] = 80'h0; + endcase + + if (PRESENT_DATA_B ) + case ( LANE_REMAP[5:4] ) + 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80]; + 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80]; + 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80]; + 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80]; + endcase + else + if (HIGHEST_LANE > 1) + case ( LANE_REMAP[5:4] ) + 2'b00 : assign phy_din[1*80-1:0] = 80'h0; + 2'b01 : assign phy_din[2*80-1:80] = 80'h0; + 2'b10 : assign phy_din[3*80-1:160] = 80'h0; + 2'b11 : assign phy_din[4*80-1:240] = 80'h0; + endcase + + if (PRESENT_DATA_C) + case ( LANE_REMAP[9:8] ) + 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160]; + 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160]; + 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160]; + 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160]; + endcase + else + if (HIGHEST_LANE > 2) + case ( LANE_REMAP[9:8] ) + 2'b00 : assign phy_din[1*80-1:0] = 80'h0; + 2'b01 : assign phy_din[2*80-1:80] = 80'h0; + 2'b10 : assign phy_din[3*80-1:160] = 80'h0; + 2'b11 : assign phy_din[4*80-1:240] = 80'h0; + endcase + + if (PRESENT_DATA_D ) + case ( LANE_REMAP[13:12] ) + 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240]; + 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240]; + 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240]; + 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240]; + endcase + else + if (HIGHEST_LANE > 3) + case ( LANE_REMAP[13:12] ) + 2'b00 : assign phy_din[1*80-1:0] = 80'h0; + 2'b01 : assign phy_din[2*80-1:80] = 80'h0; + 2'b10 : assign phy_din[3*80-1:160] = 80'h0; + 2'b11 : assign phy_din[4*80-1:240] = 80'h0; + endcase + +if (HIGHEST_LANE > 1) + assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]}; +if (HIGHEST_LANE == 1) + assign _phy_ctl_wd = phy_ctl_wd; + + +//BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst)); +BUFIO rclk_buf(.I(rclk_), .O(rclk) ); + +if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A + + assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0])); + + mig_7series_v4_0_ddr_byte_lane # + ( + .ABCD ("A"), + .PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"), + .BITLANES (BITLANES[11:0]), + .BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]), + .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), + .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), + .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), + //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), + //.OF_ARRAY_MODE (A_OF_ARRAY_MODE), + //.IF_ARRAY_MODE (IF_ARRAY_MODE), + .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), + .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), + .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .BYTELANES_DDR_CK (BYTELANES_DDR_CK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .TCK (TCK), + .PC_CLK_RATIO (PC_CLK_RATIO), + .PI_BURST_MODE (A_PI_BURST_MODE), + .PI_CLKOUT_DIV (A_PI_CLKOUT_DIV), + .PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV), + .PI_FINE_DELAY (A_PI_FINE_DELAY), + .PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC), + .PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST), + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + .PO_CLKOUT_DIV (A_PO_CLKOUT_DIV), + .PO_FINE_DELAY (A_PO_FINE_DELAY), + .PO_COARSE_BYPASS (A_PO_COARSE_BYPASS), + .PO_COARSE_DELAY (A_PO_COARSE_DELAY), + .PO_OCLK_DELAY (A_PO_OCLK_DELAY), + .PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV), + .PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC), + .PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST), + .OSERDES_DATA_RATE (A_OS_DATA_RATE), + .OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH), + .IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE), + .IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + ddr_byte_lane_A( + .mem_dq_out (mem_dq_out[11:0]), + .mem_dq_ts (mem_dq_ts[11:0]), + .mem_dq_in (mem_dq_in[9:0]), + .mem_dqs_out (mem_dqs_out[0]), + .mem_dqs_ts (mem_dqs_ts[0]), + .mem_dqs_in (mem_dqs_in[0]), + .rst (A_rst_primitives), + .rst_pi_div2 (A_pi_rst_div2), + .phy_clk (phy_clk), + .clk_div2 (clk_div2), + .freq_refclk (freq_refclk), + .mem_refclk (mem_refclk), + .idelayctrl_refclk (idelayctrl_refclk), + .sync_pulse (sync_pulse), + .ddr_ck_out (A_ddr_clk), + .rclk (A_rclk), + .pi_dqs_found (A_pi_dqs_found), + .dqs_out_of_range (A_pi_dqs_out_of_range), + .if_empty_def (if_empty_def), + .if_a_empty (A_if_a_empty), + .if_empty (A_if_empty), + .if_a_full (/*if_a_full*/), + .if_full (/*A_if_full*/), + .of_a_empty (/*of_a_empty*/), + .of_empty (/*A_of_empty*/), + .of_a_full (A_of_a_full), + .of_full (A_of_full), + .pre_fifo_a_full (A_pre_fifo_a_full), + .phy_din (phy_din_remap[79:0]), + .phy_dout (phy_dout_remap[79:0]), + .phy_cmd_wr_en (phy_cmd_wr_en), + .phy_data_wr_en (phy_data_wr_en), + .phy_rd_en (phy_rd_en), + .phaser_ctl_bus (phaser_ctl_bus), + .if_rst (if_rst), + .byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks), + .byte_rd_en (A_byte_rd_en), +// calibration signals + .idelay_inc (idelay_inc), + .idelay_ce (A_idelay_ce), + .idelay_ld (A_idelay_ld), + .pi_rst_dqs_find (A_pi_rst_dqs_find), + .po_en_calib (phy_encalib), + .po_fine_enable (A_po_fine_enable), + .po_coarse_enable (A_po_coarse_enable), + .po_fine_inc (A_po_fine_inc), + .po_coarse_inc (A_po_coarse_inc), + .po_counter_load_en (A_po_counter_load_en), + .po_counter_read_en (A_po_counter_read_en), + .po_counter_load_val (A_po_counter_load_val), + .po_coarse_overflow (A_po_coarse_overflow), + .po_fine_overflow (A_po_fine_overflow), + .po_counter_read_val (A_po_counter_read_val), + .po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay), + .pi_en_calib (phy_encalib), + .pi_fine_enable (A_pi_fine_enable), + .pi_fine_inc (A_pi_fine_inc), + .pi_counter_load_en (A_pi_counter_load_en), + .pi_counter_read_en (A_pi_counter_read_en), + .pi_counter_load_val (A_pi_counter_load_val), + .pi_fine_overflow (A_pi_fine_overflow), + .pi_counter_read_val (A_pi_counter_read_val), + .pi_iserdes_rst (A_pi_iserdes_rst), + .pi_phase_locked (A_pi_phase_locked), + .fine_delay (A_fine_delay), + .fine_delay_sel (A_fine_delay_sel) +); + +end +else begin : no_ddr_byte_lane_A + assign A_of_a_full = 1'b0; + assign A_of_full = 1'b0; + assign A_pre_fifo_a_full = 1'b0; + assign A_if_empty = 1'b0; + assign A_byte_rd_en = 1'b1; + assign A_if_a_empty = 1'b0; + assign A_pi_phase_locked = 1; + assign A_pi_dqs_found = 1; + assign A_rclk = 0; + assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; + assign A_pi_counter_read_val = 0; + assign A_po_counter_read_val = 0; + assign A_pi_fine_overflow = 0; + assign A_po_coarse_overflow = 0; + assign A_po_fine_overflow = 0; +end + +if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B + + assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4])); + mig_7series_v4_0_ddr_byte_lane # + ( + .ABCD ("B"), + .PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"), + .BITLANES (BITLANES[23:12]), + .BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]), + .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), + .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), + .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), + //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), + //.OF_ARRAY_MODE (B_OF_ARRAY_MODE), + //.IF_ARRAY_MODE (IF_ARRAY_MODE), + .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), + .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), + .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .BYTELANES_DDR_CK (BYTELANES_DDR_CK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .TCK (TCK), + .PC_CLK_RATIO (PC_CLK_RATIO), + .PI_BURST_MODE (B_PI_BURST_MODE), + .PI_CLKOUT_DIV (B_PI_CLKOUT_DIV), + .PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV), + .PI_FINE_DELAY (B_PI_FINE_DELAY), + .PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC), + .PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST), + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + .PO_CLKOUT_DIV (B_PO_CLKOUT_DIV), + .PO_FINE_DELAY (B_PO_FINE_DELAY), + .PO_COARSE_BYPASS (B_PO_COARSE_BYPASS), + .PO_COARSE_DELAY (B_PO_COARSE_DELAY), + .PO_OCLK_DELAY (B_PO_OCLK_DELAY), + .PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV), + .PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC), + .PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST), + .OSERDES_DATA_RATE (B_OS_DATA_RATE), + .OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH), + .IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE), + .IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + ddr_byte_lane_B( + .mem_dq_out (mem_dq_out[23:12]), + .mem_dq_ts (mem_dq_ts[23:12]), + .mem_dq_in (mem_dq_in[19:10]), + .mem_dqs_out (mem_dqs_out[1]), + .mem_dqs_ts (mem_dqs_ts[1]), + .mem_dqs_in (mem_dqs_in[1]), + .rst (B_rst_primitives), + .rst_pi_div2 (B_pi_rst_div2), + .phy_clk (phy_clk), + .clk_div2 (clk_div2), + .freq_refclk (freq_refclk), + .mem_refclk (mem_refclk), + .idelayctrl_refclk (idelayctrl_refclk), + .sync_pulse (sync_pulse), + .ddr_ck_out (B_ddr_clk), + .rclk (B_rclk), + .pi_dqs_found (B_pi_dqs_found), + .dqs_out_of_range (B_pi_dqs_out_of_range), + .if_empty_def (if_empty_def), + .if_a_empty (B_if_a_empty), + .if_empty (B_if_empty), + .if_a_full (/*if_a_full*/), + .if_full (/*B_if_full*/), + .of_a_empty (/*of_a_empty*/), + .of_empty (/*B_of_empty*/), + .of_a_full (B_of_a_full), + .of_full (B_of_full), + .pre_fifo_a_full (B_pre_fifo_a_full), + .phy_din (phy_din_remap[159:80]), + .phy_dout (phy_dout_remap[159:80]), + .phy_cmd_wr_en (phy_cmd_wr_en), + .phy_data_wr_en (phy_data_wr_en), + .phy_rd_en (phy_rd_en), + .phaser_ctl_bus (phaser_ctl_bus), + .if_rst (if_rst), + .byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks), + .byte_rd_en (B_byte_rd_en), +// calibration signals + .idelay_inc (idelay_inc), + .idelay_ce (B_idelay_ce), + .idelay_ld (B_idelay_ld), + .pi_rst_dqs_find (B_pi_rst_dqs_find), + .po_en_calib (phy_encalib), + .po_fine_enable (B_po_fine_enable), + .po_coarse_enable (B_po_coarse_enable), + .po_fine_inc (B_po_fine_inc), + .po_coarse_inc (B_po_coarse_inc), + .po_counter_load_en (B_po_counter_load_en), + .po_counter_read_en (B_po_counter_read_en), + .po_counter_load_val (B_po_counter_load_val), + .po_coarse_overflow (B_po_coarse_overflow), + .po_fine_overflow (B_po_fine_overflow), + .po_counter_read_val (B_po_counter_read_val), + .po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay), + .pi_en_calib (phy_encalib), + .pi_fine_enable (B_pi_fine_enable), + .pi_fine_inc (B_pi_fine_inc), + .pi_counter_load_en (B_pi_counter_load_en), + .pi_counter_read_en (B_pi_counter_read_en), + .pi_counter_load_val (B_pi_counter_load_val), + .pi_fine_overflow (B_pi_fine_overflow), + .pi_counter_read_val (B_pi_counter_read_val), + .pi_iserdes_rst (B_pi_iserdes_rst), + .pi_phase_locked (B_pi_phase_locked), + .fine_delay (B_fine_delay), + .fine_delay_sel (B_fine_delay_sel) +); +end +else begin : no_ddr_byte_lane_B + assign B_of_a_full = 1'b0; + assign B_of_full = 1'b0; + assign B_pre_fifo_a_full = 1'b0; + assign B_if_empty = 1'b0; + assign B_if_a_empty = 1'b0; + assign B_byte_rd_en = 1'b1; + assign B_pi_phase_locked = 1; + assign B_pi_dqs_found = 1; + assign B_rclk = 0; + assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; + assign B_pi_counter_read_val = 0; + assign B_po_counter_read_val = 0; + assign B_pi_fine_overflow = 0; + assign B_po_coarse_overflow = 0; + assign B_po_fine_overflow = 0; +end + +if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C + + assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8])); + mig_7series_v4_0_ddr_byte_lane # + ( + .ABCD ("C"), + .PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"), + .BITLANES (BITLANES[35:24]), + .BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]), + .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), + .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), + .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), + //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), + //.OF_ARRAY_MODE (C_OF_ARRAY_MODE), + //.IF_ARRAY_MODE (IF_ARRAY_MODE), + .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), + .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), + .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .BYTELANES_DDR_CK (BYTELANES_DDR_CK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .TCK (TCK), + .PC_CLK_RATIO (PC_CLK_RATIO), + .PI_BURST_MODE (C_PI_BURST_MODE), + .PI_CLKOUT_DIV (C_PI_CLKOUT_DIV), + .PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV), + .PI_FINE_DELAY (C_PI_FINE_DELAY), + .PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC), + .PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST), + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + .PO_CLKOUT_DIV (C_PO_CLKOUT_DIV), + .PO_FINE_DELAY (C_PO_FINE_DELAY), + .PO_COARSE_BYPASS (C_PO_COARSE_BYPASS), + .PO_COARSE_DELAY (C_PO_COARSE_DELAY), + .PO_OCLK_DELAY (C_PO_OCLK_DELAY), + .PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV), + .PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC), + .PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST), + .OSERDES_DATA_RATE (C_OS_DATA_RATE), + .OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH), + .IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE), + .IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + ddr_byte_lane_C( + .mem_dq_out (mem_dq_out[35:24]), + .mem_dq_ts (mem_dq_ts[35:24]), + .mem_dq_in (mem_dq_in[29:20]), + .mem_dqs_out (mem_dqs_out[2]), + .mem_dqs_ts (mem_dqs_ts[2]), + .mem_dqs_in (mem_dqs_in[2]), + .rst (C_rst_primitives), + .rst_pi_div2 (C_pi_rst_div2), + .phy_clk (phy_clk), + .clk_div2 (clk_div2), + .freq_refclk (freq_refclk), + .mem_refclk (mem_refclk), + .idelayctrl_refclk (idelayctrl_refclk), + .sync_pulse (sync_pulse), + .ddr_ck_out (C_ddr_clk), + .rclk (C_rclk), + .pi_dqs_found (C_pi_dqs_found), + .dqs_out_of_range (C_pi_dqs_out_of_range), + .if_empty_def (if_empty_def), + .if_a_empty (C_if_a_empty), + .if_empty (C_if_empty), + .if_a_full (/*if_a_full*/), + .if_full (/*C_if_full*/), + .of_a_empty (/*of_a_empty*/), + .of_empty (/*C_of_empty*/), + .of_a_full (C_of_a_full), + .of_full (C_of_full), + .pre_fifo_a_full (C_pre_fifo_a_full), + .phy_din (phy_din_remap[239:160]), + .phy_dout (phy_dout_remap[239:160]), + .phy_cmd_wr_en (phy_cmd_wr_en), + .phy_data_wr_en (phy_data_wr_en), + .phy_rd_en (phy_rd_en), + .phaser_ctl_bus (phaser_ctl_bus), + .if_rst (if_rst), + .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks), + .byte_rd_en (C_byte_rd_en), +// calibration signals + .idelay_inc (idelay_inc), + .idelay_ce (C_idelay_ce), + .idelay_ld (C_idelay_ld), + .pi_rst_dqs_find (C_pi_rst_dqs_find), + .po_en_calib (phy_encalib), + .po_fine_enable (C_po_fine_enable), + .po_coarse_enable (C_po_coarse_enable), + .po_fine_inc (C_po_fine_inc), + .po_coarse_inc (C_po_coarse_inc), + .po_counter_load_en (C_po_counter_load_en), + .po_counter_read_en (C_po_counter_read_en), + .po_counter_load_val (C_po_counter_load_val), + .po_coarse_overflow (C_po_coarse_overflow), + .po_fine_overflow (C_po_fine_overflow), + .po_counter_read_val (C_po_counter_read_val), + .po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay), + .pi_en_calib (phy_encalib), + .pi_fine_enable (C_pi_fine_enable), + .pi_fine_inc (C_pi_fine_inc), + .pi_counter_load_en (C_pi_counter_load_en), + .pi_counter_read_en (C_pi_counter_read_en), + .pi_counter_load_val (C_pi_counter_load_val), + .pi_fine_overflow (C_pi_fine_overflow), + .pi_counter_read_val (C_pi_counter_read_val), + .pi_iserdes_rst (C_pi_iserdes_rst), + .pi_phase_locked (C_pi_phase_locked), + .fine_delay (C_fine_delay), + .fine_delay_sel (C_fine_delay_sel) +); + +end +else begin : no_ddr_byte_lane_C + assign C_of_a_full = 1'b0; + assign C_of_full = 1'b0; + assign C_pre_fifo_a_full = 1'b0; + assign C_if_empty = 1'b0; + assign C_byte_rd_en = 1'b1; + assign C_if_a_empty = 1'b0; + assign C_pi_phase_locked = 1; + assign C_pi_dqs_found = 1; + assign C_rclk = 0; + assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; + assign C_pi_counter_read_val = 0; + assign C_po_counter_read_val = 0; + assign C_pi_fine_overflow = 0; + assign C_po_coarse_overflow = 0; + assign C_po_fine_overflow = 0; +end + +if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D + assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12])); + + mig_7series_v4_0_ddr_byte_lane # + ( + .ABCD ("D"), + .PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"), + .BITLANES (BITLANES[47:36]), + .BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]), + .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), + .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), + .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), + //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), + //.OF_ARRAY_MODE (D_OF_ARRAY_MODE), + //.IF_ARRAY_MODE (IF_ARRAY_MODE), + .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), + .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), + .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .BYTELANES_DDR_CK (BYTELANES_DDR_CK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .TCK (TCK), + .PC_CLK_RATIO (PC_CLK_RATIO), + .PI_BURST_MODE (D_PI_BURST_MODE), + .PI_CLKOUT_DIV (D_PI_CLKOUT_DIV), + .PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV), + .PI_FINE_DELAY (D_PI_FINE_DELAY), + .PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC), + .PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST), + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + .PO_CLKOUT_DIV (D_PO_CLKOUT_DIV), + .PO_FINE_DELAY (D_PO_FINE_DELAY), + .PO_COARSE_BYPASS (D_PO_COARSE_BYPASS), + .PO_COARSE_DELAY (D_PO_COARSE_DELAY), + .PO_OCLK_DELAY (D_PO_OCLK_DELAY), + .PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV), + .PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC), + .PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST), + .OSERDES_DATA_RATE (D_OS_DATA_RATE), + .OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH), + .IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE), + .IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + ddr_byte_lane_D( + .mem_dq_out (mem_dq_out[47:36]), + .mem_dq_ts (mem_dq_ts[47:36]), + .mem_dq_in (mem_dq_in[39:30]), + .mem_dqs_out (mem_dqs_out[3]), + .mem_dqs_ts (mem_dqs_ts[3]), + .mem_dqs_in (mem_dqs_in[3]), + .rst (D_rst_primitives), + .rst_pi_div2 (D_pi_rst_div2), + .phy_clk (phy_clk), + .clk_div2 (clk_div2), + .freq_refclk (freq_refclk), + .mem_refclk (mem_refclk), + .idelayctrl_refclk (idelayctrl_refclk), + .sync_pulse (sync_pulse), + .ddr_ck_out (D_ddr_clk), + .rclk (D_rclk), + .pi_dqs_found (D_pi_dqs_found), + .dqs_out_of_range (D_pi_dqs_out_of_range), + .if_empty_def (if_empty_def), + .if_a_empty (D_if_a_empty), + .if_empty (D_if_empty), + .if_a_full (/*if_a_full*/), + .if_full (/*D_if_full*/), + .of_a_empty (/*of_a_empty*/), + .of_empty (/*D_of_empty*/), + .of_a_full (D_of_a_full), + .of_full (D_of_full), + .pre_fifo_a_full (D_pre_fifo_a_full), + .phy_din (phy_din_remap[319:240]), + .phy_dout (phy_dout_remap[319:240]), + .phy_cmd_wr_en (phy_cmd_wr_en), + .phy_data_wr_en (phy_data_wr_en), + .phy_rd_en (phy_rd_en), + .phaser_ctl_bus (phaser_ctl_bus), + .idelay_inc (idelay_inc), + .idelay_ce (D_idelay_ce), + .idelay_ld (D_idelay_ld), + .if_rst (if_rst), + .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks), + .byte_rd_en (D_byte_rd_en), +// calibration signals + .pi_rst_dqs_find (D_pi_rst_dqs_find), + .po_en_calib (phy_encalib), + .po_fine_enable (D_po_fine_enable), + .po_coarse_enable (D_po_coarse_enable), + .po_fine_inc (D_po_fine_inc), + .po_coarse_inc (D_po_coarse_inc), + .po_counter_load_en (D_po_counter_load_en), + .po_counter_read_en (D_po_counter_read_en), + .po_counter_load_val (D_po_counter_load_val), + .po_coarse_overflow (D_po_coarse_overflow), + .po_fine_overflow (D_po_fine_overflow), + .po_counter_read_val (D_po_counter_read_val), + .po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay), + .pi_en_calib (phy_encalib), + .pi_fine_enable (D_pi_fine_enable), + .pi_fine_inc (D_pi_fine_inc), + .pi_counter_load_en (D_pi_counter_load_en), + .pi_counter_read_en (D_pi_counter_read_en), + .pi_counter_load_val (D_pi_counter_load_val), + .pi_fine_overflow (D_pi_fine_overflow), + .pi_counter_read_val (D_pi_counter_read_val), + .pi_iserdes_rst (D_pi_iserdes_rst), + .pi_phase_locked (D_pi_phase_locked), + .fine_delay (D_fine_delay), + .fine_delay_sel (D_fine_delay_sel) +); +end +else begin : no_ddr_byte_lane_D + assign D_of_a_full = 1'b0; + assign D_of_full = 1'b0; + assign D_pre_fifo_a_full = 1'b0; + assign D_if_empty = 1'b0; + assign D_byte_rd_en = 1'b1; + assign D_if_a_empty = 1'b0; + assign D_rclk = 0; + assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; + assign D_pi_dqs_found = 1; + assign D_pi_phase_locked = 1; + assign D_pi_counter_read_val = 0; + assign D_po_counter_read_val = 0; + assign D_pi_fine_overflow = 0; + assign D_po_coarse_overflow = 0; + assign D_po_fine_overflow = 0; +end +endgenerate + + +assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank; + +PHY_CONTROL #( + .AO_WRLVL_EN ( PC_AO_WRLVL_EN), + .AO_TOGGLE ( PC_AO_TOGGLE), + .BURST_MODE ( PC_BURST_MODE), + .CO_DURATION ( PC_CO_DURATION ), + .CLK_RATIO ( PC_CLK_RATIO), + .DATA_CTL_A_N ( PC_DATA_CTL_A), + .DATA_CTL_B_N ( PC_DATA_CTL_B), + .DATA_CTL_C_N ( PC_DATA_CTL_C), + .DATA_CTL_D_N ( PC_DATA_CTL_D), + .DI_DURATION ( PC_DI_DURATION ), + .DO_DURATION ( PC_DO_DURATION ), + .EVENTS_DELAY ( PC_EVENTS_DELAY), + .FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS), + .MULTI_REGION ( PC_MULTI_REGION ), + .PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN), + .DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH), + .SYNC_MODE ( PC_SYNC_MODE), + .CMD_OFFSET ( PC_CMD_OFFSET), + + .RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0), + .RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1), + .RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2), + .RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3), + .RD_DURATION_0 ( PC_RD_DURATION_0), + .RD_DURATION_1 ( PC_RD_DURATION_1), + .RD_DURATION_2 ( PC_RD_DURATION_2), + .RD_DURATION_3 ( PC_RD_DURATION_3), + .WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0), + .WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1), + .WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2), + .WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3), + .WR_DURATION_0 ( PC_WR_DURATION_0), + .WR_DURATION_1 ( PC_WR_DURATION_1), + .WR_DURATION_2 ( PC_WR_DURATION_2), + .WR_DURATION_3 ( PC_WR_DURATION_3) +) phy_control_i ( + .AUXOUTPUT (aux_out), + .INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]), + .INRANKA (in_rank[1:0]), + .INRANKB (in_rank[3:2]), + .INRANKC (in_rank[5:4]), + .INRANKD (in_rank[7:6]), + .OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]), + .PCENABLECALIB (phy_encalib), + .PHYCTLALMOSTFULL (phy_ctl_a_full), + .PHYCTLEMPTY (phy_ctl_empty), + .PHYCTLFULL (phy_ctl_full), + .PHYCTLREADY (phy_ctl_ready), + .MEMREFCLK (mem_refclk), + .PHYCLK (phy_ctl_clk), + .PHYCTLMSTREMPTY (phy_ctl_mstr_empty), + .PHYCTLWD (_phy_ctl_wd), + .PHYCTLWRENABLE (phy_ctl_wr), + .PLLLOCK (pll_lock), + .REFDLLLOCK (ref_dll_lock), // is reset while !locked + .RESET (rst), + .SYNCIN (sync_pulse), + .READCALIBENABLE (phy_read_calib), + .WRITECALIBENABLE (phy_write_calib) +`ifdef USE_PHY_CONTROL_TEST + , .TESTINPUT (16'b0), + .TESTOUTPUT (test_output), + .TESTSELECT (test_select), + .SCANENABLEN (scan_enable) +`endif +); + + + +// register outputs to give extra slack in timing +always @(posedge phy_clk ) begin + case (calib_sel[1:0]) + 2'h0: begin + po_coarse_overflow <= #1 A_po_coarse_overflow; + po_fine_overflow <= #1 A_po_fine_overflow; + po_counter_read_val <= #1 A_po_counter_read_val; + + pi_fine_overflow <= #1 A_pi_fine_overflow; + pi_counter_read_val<= #1 A_pi_counter_read_val; + + pi_phase_locked <= #1 A_pi_phase_locked; + if ( calib_in_common) + pi_dqs_found <= #1 pi_dqs_found_any; + else + pi_dqs_found <= #1 A_pi_dqs_found; + pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range; + end + + 2'h1: begin + po_coarse_overflow <= #1 B_po_coarse_overflow; + po_fine_overflow <= #1 B_po_fine_overflow; + po_counter_read_val <= #1 B_po_counter_read_val; + + pi_fine_overflow <= #1 B_pi_fine_overflow; + pi_counter_read_val <= #1 B_pi_counter_read_val; + + pi_phase_locked <= #1 B_pi_phase_locked; + if ( calib_in_common) + pi_dqs_found <= #1 pi_dqs_found_any; + else + pi_dqs_found <= #1 B_pi_dqs_found; + pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range; + end + + 2'h2: begin + po_coarse_overflow <= #1 C_po_coarse_overflow; + po_fine_overflow <= #1 C_po_fine_overflow; + po_counter_read_val <= #1 C_po_counter_read_val; + + pi_fine_overflow <= #1 C_pi_fine_overflow; + pi_counter_read_val <= #1 C_pi_counter_read_val; + + pi_phase_locked <= #1 C_pi_phase_locked; + if ( calib_in_common) + pi_dqs_found <= #1 pi_dqs_found_any; + else + pi_dqs_found <= #1 C_pi_dqs_found; + pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range; + end + + 2'h3: begin + po_coarse_overflow <= #1 D_po_coarse_overflow; + po_fine_overflow <= #1 D_po_fine_overflow; + po_counter_read_val <= #1 D_po_counter_read_val; + + pi_fine_overflow <= #1 D_pi_fine_overflow; + pi_counter_read_val <= #1 D_pi_counter_read_val; + + pi_phase_locked <= #1 D_pi_phase_locked; + if ( calib_in_common) + pi_dqs_found <= #1 pi_dqs_found_any; + else + pi_dqs_found <= #1 D_pi_dqs_found; + pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range; + + end + default: begin + po_coarse_overflow <= po_coarse_overflow; + end + endcase +end + +wire B_mux_ctrl; +wire C_mux_ctrl; +wire D_mux_ctrl; +generate + if (HIGHEST_LANE > 1) + assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1])); + else + assign B_mux_ctrl = 0; + if (HIGHEST_LANE > 2) + assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2])); + else + assign C_mux_ctrl = 0; + if (HIGHEST_LANE > 3) + assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3])); + else + assign D_mux_ctrl = 0; +endgenerate + +always @(*) begin + A_pi_fine_enable = 0; + A_pi_fine_inc = 0; + A_pi_counter_load_en = 0; + A_pi_counter_read_en = 0; + A_pi_counter_load_val = 0; + A_pi_rst_dqs_find = 0; + + + A_po_fine_enable = 0; + A_po_coarse_enable = 0; + A_po_fine_inc = 0; + A_po_coarse_inc = 0; + A_po_counter_load_en = 0; + A_po_counter_read_en = 0; + A_po_counter_load_val = 0; + A_po_sel_fine_oclk_delay = 0; + + A_idelay_ce = 0; + A_idelay_ld = 0; + A_fine_delay = 0; + A_fine_delay_sel = 0; + + B_pi_fine_enable = 0; + B_pi_fine_inc = 0; + B_pi_counter_load_en = 0; + B_pi_counter_read_en = 0; + B_pi_counter_load_val = 0; + B_pi_rst_dqs_find = 0; + + + B_po_fine_enable = 0; + B_po_coarse_enable = 0; + B_po_fine_inc = 0; + B_po_coarse_inc = 0; + B_po_counter_load_en = 0; + B_po_counter_read_en = 0; + B_po_counter_load_val = 0; + B_po_sel_fine_oclk_delay = 0; + + B_idelay_ce = 0; + B_idelay_ld = 0; + B_fine_delay = 0; + B_fine_delay_sel = 0; + + C_pi_fine_enable = 0; + C_pi_fine_inc = 0; + C_pi_counter_load_en = 0; + C_pi_counter_read_en = 0; + C_pi_counter_load_val = 0; + C_pi_rst_dqs_find = 0; + + + C_po_fine_enable = 0; + C_po_coarse_enable = 0; + C_po_fine_inc = 0; + C_po_coarse_inc = 0; + C_po_counter_load_en = 0; + C_po_counter_read_en = 0; + C_po_counter_load_val = 0; + C_po_sel_fine_oclk_delay = 0; + + C_idelay_ce = 0; + C_idelay_ld = 0; + C_fine_delay = 0; + C_fine_delay_sel = 0; + + D_pi_fine_enable = 0; + D_pi_fine_inc = 0; + D_pi_counter_load_en = 0; + D_pi_counter_read_en = 0; + D_pi_counter_load_val = 0; + D_pi_rst_dqs_find = 0; + + + D_po_fine_enable = 0; + D_po_coarse_enable = 0; + D_po_fine_inc = 0; + D_po_coarse_inc = 0; + D_po_counter_load_en = 0; + D_po_counter_read_en = 0; + D_po_counter_load_val = 0; + D_po_sel_fine_oclk_delay = 0; + + D_idelay_ce = 0; + D_idelay_ld = 0; + D_fine_delay = 0; + D_fine_delay_sel = 0; + + if ( calib_sel[2]) begin + // if this is asserted, all calib signals are deasserted + A_pi_fine_enable = 0; + A_pi_fine_inc = 0; + A_pi_counter_load_en = 0; + A_pi_counter_read_en = 0; + A_pi_counter_load_val = 0; + A_pi_rst_dqs_find = 0; + + + A_po_fine_enable = 0; + A_po_coarse_enable = 0; + A_po_fine_inc = 0; + A_po_coarse_inc = 0; + A_po_counter_load_en = 0; + A_po_counter_read_en = 0; + A_po_counter_load_val = 0; + A_po_sel_fine_oclk_delay = 0; + + A_idelay_ce = 0; + A_idelay_ld = 0; + A_fine_delay = 0; + A_fine_delay_sel = 0; + + B_pi_fine_enable = 0; + B_pi_fine_inc = 0; + B_pi_counter_load_en = 0; + B_pi_counter_read_en = 0; + B_pi_counter_load_val = 0; + B_pi_rst_dqs_find = 0; + + + B_po_fine_enable = 0; + B_po_coarse_enable = 0; + B_po_fine_inc = 0; + B_po_coarse_inc = 0; + B_po_counter_load_en = 0; + B_po_counter_read_en = 0; + B_po_counter_load_val = 0; + B_po_sel_fine_oclk_delay = 0; + + B_idelay_ce = 0; + B_idelay_ld = 0; + B_fine_delay = 0; + B_fine_delay_sel = 0; + + + C_pi_fine_enable = 0; + C_pi_fine_inc = 0; + C_pi_counter_load_en = 0; + C_pi_counter_read_en = 0; + C_pi_counter_load_val = 0; + C_pi_rst_dqs_find = 0; + + + C_po_fine_enable = 0; + C_po_coarse_enable = 0; + C_po_fine_inc = 0; + C_po_coarse_inc = 0; + C_po_counter_load_en = 0; + C_po_counter_read_en = 0; + C_po_counter_load_val = 0; + C_po_sel_fine_oclk_delay = 0; + + C_idelay_ce = 0; + C_idelay_ld = 0; + C_fine_delay = 0; + C_fine_delay_sel = 0; + + + D_pi_fine_enable = 0; + D_pi_fine_inc = 0; + D_pi_counter_load_en = 0; + D_pi_counter_read_en = 0; + D_pi_counter_load_val = 0; + D_pi_rst_dqs_find = 0; + + + D_po_fine_enable = 0; + D_po_coarse_enable = 0; + D_po_fine_inc = 0; + D_po_coarse_inc = 0; + D_po_counter_load_en = 0; + D_po_counter_read_en = 0; + D_po_counter_load_val = 0; + D_po_sel_fine_oclk_delay = 0; + + D_idelay_ce = 0; + D_idelay_ld = 0; + D_fine_delay = 0; + D_fine_delay_sel = 0; + + end else + if (calib_in_common) begin + // if this is asserted, each signal is broadcast to all phasers + // in common + if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin + A_pi_fine_enable = pi_fine_enable; + A_pi_fine_inc = pi_fine_inc; + A_pi_counter_load_en = pi_counter_load_en; + A_pi_counter_read_en = pi_counter_read_en; + A_pi_counter_load_val = pi_counter_load_val; + A_pi_rst_dqs_find = pi_rst_dqs_find; + + + A_po_fine_enable = po_fine_enable; + A_po_coarse_enable = po_coarse_enable; + A_po_fine_inc = po_fine_inc; + A_po_coarse_inc = po_coarse_inc; + A_po_counter_load_en = po_counter_load_en; + A_po_counter_read_en = po_counter_read_en; + A_po_counter_load_val = po_counter_load_val; + A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + A_idelay_ce = idelay_ce; + A_idelay_ld = idelay_ld; + A_fine_delay = fine_delay ; + A_fine_delay_sel = fine_delay_sel; + end + + if ( B_mux_ctrl) begin + B_pi_fine_enable = pi_fine_enable; + B_pi_fine_inc = pi_fine_inc; + B_pi_counter_load_en = pi_counter_load_en; + B_pi_counter_read_en = pi_counter_read_en; + B_pi_counter_load_val = pi_counter_load_val; + B_pi_rst_dqs_find = pi_rst_dqs_find; + + + B_po_fine_enable = po_fine_enable; + B_po_coarse_enable = po_coarse_enable; + B_po_fine_inc = po_fine_inc; + B_po_coarse_inc = po_coarse_inc; + B_po_counter_load_en = po_counter_load_en; + B_po_counter_read_en = po_counter_read_en; + B_po_counter_load_val = po_counter_load_val; + B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + B_idelay_ce = idelay_ce; + B_idelay_ld = idelay_ld; + B_fine_delay = fine_delay ; + B_fine_delay_sel = fine_delay_sel; + end + + if ( C_mux_ctrl) begin + C_pi_fine_enable = pi_fine_enable; + C_pi_fine_inc = pi_fine_inc; + C_pi_counter_load_en = pi_counter_load_en; + C_pi_counter_read_en = pi_counter_read_en; + C_pi_counter_load_val = pi_counter_load_val; + C_pi_rst_dqs_find = pi_rst_dqs_find; + + + C_po_fine_enable = po_fine_enable; + C_po_coarse_enable = po_coarse_enable; + C_po_fine_inc = po_fine_inc; + C_po_coarse_inc = po_coarse_inc; + C_po_counter_load_en = po_counter_load_en; + C_po_counter_read_en = po_counter_read_en; + C_po_counter_load_val = po_counter_load_val; + C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + C_idelay_ce = idelay_ce; + C_idelay_ld = idelay_ld; + C_fine_delay = fine_delay ; + C_fine_delay_sel = fine_delay_sel; + end + + if ( D_mux_ctrl) begin + D_pi_fine_enable = pi_fine_enable; + D_pi_fine_inc = pi_fine_inc; + D_pi_counter_load_en = pi_counter_load_en; + D_pi_counter_read_en = pi_counter_read_en; + D_pi_counter_load_val = pi_counter_load_val; + D_pi_rst_dqs_find = pi_rst_dqs_find; + + + D_po_fine_enable = po_fine_enable; + D_po_coarse_enable = po_coarse_enable; + D_po_fine_inc = po_fine_inc; + D_po_coarse_inc = po_coarse_inc; + D_po_counter_load_en = po_counter_load_en; + D_po_counter_read_en = po_counter_read_en; + D_po_counter_load_val = po_counter_load_val; + D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + D_idelay_ce = idelay_ce; + D_idelay_ld = idelay_ld; + D_fine_delay = fine_delay ; + D_fine_delay_sel = fine_delay_sel; + end + end + else begin + // otherwise, only a single phaser is selected + + + case (calib_sel[1:0]) + 0: begin + A_pi_fine_enable = pi_fine_enable; + A_pi_fine_inc = pi_fine_inc; + A_pi_counter_load_en = pi_counter_load_en; + A_pi_counter_read_en = pi_counter_read_en; + A_pi_counter_load_val = pi_counter_load_val; + A_pi_rst_dqs_find = pi_rst_dqs_find; + + + A_po_fine_enable = po_fine_enable; + A_po_coarse_enable = po_coarse_enable; + A_po_fine_inc = po_fine_inc; + A_po_coarse_inc = po_coarse_inc; + A_po_counter_load_en = po_counter_load_en; + A_po_counter_read_en = po_counter_read_en; + A_po_counter_load_val = po_counter_load_val; + A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + A_idelay_ce = idelay_ce; + A_idelay_ld = idelay_ld; + A_fine_delay = fine_delay ; + A_fine_delay_sel = fine_delay_sel; + + end + 1: begin + B_pi_fine_enable = pi_fine_enable; + B_pi_fine_inc = pi_fine_inc; + B_pi_counter_load_en = pi_counter_load_en; + B_pi_counter_read_en = pi_counter_read_en; + B_pi_counter_load_val = pi_counter_load_val; + B_pi_rst_dqs_find = pi_rst_dqs_find; + + + B_po_fine_enable = po_fine_enable; + B_po_coarse_enable = po_coarse_enable; + B_po_fine_inc = po_fine_inc; + B_po_coarse_inc = po_coarse_inc; + B_po_counter_load_en = po_counter_load_en; + B_po_counter_read_en = po_counter_read_en; + B_po_counter_load_val = po_counter_load_val; + B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + B_idelay_ce = idelay_ce; + B_idelay_ld = idelay_ld; + B_fine_delay = fine_delay ; + B_fine_delay_sel = fine_delay_sel; + + end + + 2: begin + C_pi_fine_enable = pi_fine_enable; + C_pi_fine_inc = pi_fine_inc; + C_pi_counter_load_en = pi_counter_load_en; + C_pi_counter_read_en = pi_counter_read_en; + C_pi_counter_load_val = pi_counter_load_val; + C_pi_rst_dqs_find = pi_rst_dqs_find; + + + C_po_fine_enable = po_fine_enable; + C_po_coarse_enable = po_coarse_enable; + C_po_fine_inc = po_fine_inc; + C_po_coarse_inc = po_coarse_inc; + C_po_counter_load_en = po_counter_load_en; + C_po_counter_read_en = po_counter_read_en; + C_po_counter_load_val = po_counter_load_val; + C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + C_idelay_ce = idelay_ce; + C_idelay_ld = idelay_ld; + C_fine_delay = fine_delay ; + C_fine_delay_sel = fine_delay_sel; + + end + + 3: begin + D_pi_fine_enable = pi_fine_enable; + D_pi_fine_inc = pi_fine_inc; + D_pi_counter_load_en = pi_counter_load_en; + D_pi_counter_read_en = pi_counter_read_en; + D_pi_counter_load_val = pi_counter_load_val; + D_pi_rst_dqs_find = pi_rst_dqs_find; + + + D_po_fine_enable = po_fine_enable; + D_po_coarse_enable = po_coarse_enable; + D_po_fine_inc = po_fine_inc; + D_po_coarse_inc = po_coarse_inc; + D_po_counter_load_en = po_counter_load_en; + D_po_counter_load_val = po_counter_load_val; + D_po_counter_read_en = po_counter_read_en; + D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + D_idelay_ce = idelay_ce; + D_idelay_ld = idelay_ld; + D_fine_delay = fine_delay ; + D_fine_delay_sel = fine_delay_sel; + + end + endcase + end +end + +//obligatory phaser-ref +PHASER_REF phaser_ref_i( + + .LOCKED (ref_dll_lock), + .CLKIN (freq_refclk), + .PWRDWN (1'b0), + .RST ( ! pll_lock) + +); + + +// optional idelay_ctrl +generate +if ( GENERATE_IDELAYCTRL == "TRUE") +IDELAYCTRL idelayctrl ( + .RDY (/*idelayctrl_rdy*/), + .REFCLK (idelayctrl_refclk), + .RST (rst) +); +endgenerate + + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v new file mode 100644 index 0000000..f00b202 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v @@ -0,0 +1,233 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_ck_addr_cmd_delay.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Shift CK/Address/Commands/Controls +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay # + ( + parameter TCQ = 100, + parameter tCK = 3636, + parameter DQS_CNT_WIDTH = 3, + parameter N_CTL_LANES = 3, + parameter SIM_CAL_OPTION = "NONE" + ) + ( + input clk, + input rst, + // Start only after PO_CIRC_BUF_DELAY decremented + input cmd_delay_start, + // Control lane being shifted using Phaser_Out fine delay taps + output reg [N_CTL_LANES-1:0] ctl_lane_cnt, + // Inc/dec Phaser_Out fine delay line + output reg po_stg2_f_incdec, + output reg po_en_stg2_f, + output reg po_stg2_c_incdec, + output reg po_en_stg2_c, + // Completed delaying CK/Address/Commands/Controls + output po_ck_addr_cmd_delay_done + ); + + localparam TAP_CNT_LIMIT = 63; + + //Calculate the tap resolution of the PHASER based on the clock period + localparam FREQ_REF_DIV = (tCK > 5000 ? 4 : + tCK > 2500 ? 2 : 1); + + localparam integer PHASER_TAP_RES = ((tCK/2)/64); + + // Determine whether 300 ps or 350 ps delay required + localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300; + + // Determine the number of Phaser_Out taps required to delay by 300 ps + // 300 ps is the PCB trace uncertainty between CK and DQS byte groups + + + // Increment control byte lanes + localparam TAP_CNT = 0; + //localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES; + //Decrement control byte lanes + localparam TAP_DEC = (SIM_CAL_OPTION == "FAST_CAL") ? 0 : 29; + + + + + reg delay_dec_done; + reg delay_done_r1; + reg delay_done_r2; + reg delay_done_r3; + reg delay_done_r4 /* synthesis syn_maxfan = 10 */; + reg [5:0] delay_cnt_r; + reg [5:0] delaydec_cnt_r; + reg po_cnt_inc; + reg po_cnt_dec; + reg [3:0] wait_cnt_r; + + assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4; + + always @(posedge clk) begin + if (rst || po_cnt_dec || po_cnt_inc) + wait_cnt_r <= #TCQ 'd8; + else if (cmd_delay_start && (wait_cnt_r > 'd0)) + wait_cnt_r <= #TCQ wait_cnt_r - 1; + end + + always @(posedge clk) begin + if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0)) + po_cnt_inc <= #TCQ 1'b0; + else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1)) + po_cnt_inc <= #TCQ 1'b1; + else + po_cnt_inc <= #TCQ 1'b0; + end + + //Tap decrement + always @(posedge clk) begin + if (rst || (delaydec_cnt_r == 'd0)) + po_cnt_dec <= #TCQ 1'b0; + else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1)) + po_cnt_dec <= #TCQ 1'b1; + else + po_cnt_dec <= #TCQ 1'b0; + end + + //po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane + //the alignment is started once the + always @(posedge clk) begin + if (rst) begin + po_stg2_f_incdec <= #TCQ 1'b0; + po_en_stg2_f <= #TCQ 1'b0; + po_stg2_c_incdec <= #TCQ 1'b0; + po_en_stg2_c <= #TCQ 1'b0; + end else begin + if (po_cnt_dec) begin + po_stg2_f_incdec <= #TCQ 1'b0; + po_en_stg2_f <= #TCQ 1'b1; + end else begin + po_stg2_f_incdec <= #TCQ 1'b0; + po_en_stg2_f <= #TCQ 1'b0; + end + if (po_cnt_inc) begin + po_stg2_c_incdec <= #TCQ 1'b1; + po_en_stg2_c <= #TCQ 1'b1; + end else begin + po_stg2_c_incdec <= #TCQ 1'b0; + po_en_stg2_c <= #TCQ 1'b0; + end + end + end + + // delay counter to count 2 cycles + // Increment coarse taps by 2 for all control byte lanes + // to mitigate late writes + always @(posedge clk) begin + // load delay counter with init value + if (rst || (tCK > 2500) || (SIM_CAL_OPTION == "FAST_CAL")) + delay_cnt_r <= #TCQ 'd0; + else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) + delay_cnt_r <= #TCQ 'd1; + else if (po_cnt_inc && (delay_cnt_r > 6'd0)) + delay_cnt_r <= #TCQ delay_cnt_r - 1; + end + + // delay counter to count TAP_DEC cycles + always @(posedge clk) begin + // load delay counter with init value of TAP_DEC + if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) + delaydec_cnt_r <= #TCQ TAP_DEC; + else if (po_cnt_dec && (delaydec_cnt_r > 6'd0)) + delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1; + end + + //ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle + //This ensures all ctrl byte lanes have had their output phase shifted. + always @(posedge clk) begin + if (rst || ~cmd_delay_start ) + ctl_lane_cnt <= #TCQ 6'b0; + else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1)) + ctl_lane_cnt <= #TCQ ctl_lane_cnt; + else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0)) + ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; + end + + // All control lanes have decremented to 31 fine taps from 46 + always @(posedge clk) begin + if (rst || ~cmd_delay_start) begin + delay_dec_done <= #TCQ 1'b0; + end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) || + ((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin + delay_dec_done <= #TCQ 1'b1; + end + end + + + + always @(posedge clk) begin + delay_done_r1 <= #TCQ delay_dec_done; + delay_done_r2 <= #TCQ delay_done_r1; + delay_done_r3 <= #TCQ delay_done_r2; + delay_done_r4 <= #TCQ delay_done_r3; + end + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal.v new file mode 100644 index 0000000..3949ed6 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal.v @@ -0,0 +1,1198 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: +// \ \ Application: MIG +// / / Filename: ddr_phy_dqs_found_cal.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// Read leveling calibration logic +// NOTES: +// 1. Phaser_In DQSFOUND calibration +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $ +**$Date: 2011/06/02 08:35:08 $ +**$Author: +**$Revision: +**$Source: +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_dqs_found_cal # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter nCK_PER_CLK = 2, // # of memory clocks per CLK + parameter nCL = 5, // Read CAS latency + parameter AL = "0", + parameter nCWL = 5, // Write CAS latency + parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" + parameter RANKS = 1, // # of memory ranks in the system + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter REG_CTRL = "ON", // "ON" for registered DIMM + parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps + parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate + parameter N_CTL_LANES = 3, // Number of control byte lanes + parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl) + parameter HIGHEST_BANK = 3, // Sum of I/O Banks + parameter BYTE_LANES_B0 = 4'b1111, + parameter BYTE_LANES_B1 = 4'b0000, + parameter BYTE_LANES_B2 = 4'b0000, + parameter BYTE_LANES_B3 = 4'b0000, + parameter BYTE_LANES_B4 = 4'b0000, + parameter DATA_CTL_B0 = 4'hc, + parameter DATA_CTL_B1 = 4'hf, + parameter DATA_CTL_B2 = 4'hf, + parameter DATA_CTL_B3 = 4'hf, + parameter DATA_CTL_B4 = 4'hf + ) + ( + input clk, + input rst, + input dqsfound_retry, + // From phy_init + input pi_dqs_found_start, + input detect_pi_found_dqs, + input prech_done, + // DQSFOUND per Phaser_IN + input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, + + output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal, + + // To phy_init + output [5:0] rd_data_offset_0, + output [5:0] rd_data_offset_1, + output [5:0] rd_data_offset_2, + output pi_dqs_found_rank_done, + output pi_dqs_found_done, + output reg pi_dqs_found_err, + output [6*RANKS-1:0] rd_data_offset_ranks_0, + output [6*RANKS-1:0] rd_data_offset_ranks_1, + output [6*RANKS-1:0] rd_data_offset_ranks_2, + output reg dqsfound_retry_done, + output reg dqs_found_prech_req, + //To MC + output [6*RANKS-1:0] rd_data_offset_ranks_mc_0, + output [6*RANKS-1:0] rd_data_offset_ranks_mc_1, + output [6*RANKS-1:0] rd_data_offset_ranks_mc_2, + + input [8:0] po_counter_read_val, + output rd_data_offset_cal_done, + output fine_adjust_done, + output [N_CTL_LANES-1:0] fine_adjust_lane_cnt, + output reg ck_po_stg2_f_indec, + output reg ck_po_stg2_f_en, + output [255:0] dbg_dqs_found_cal + ); + + + // For non-zero AL values + localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; + + // Adding the register dimm latency to write latency + localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; + + // Added to reduce simulation time + localparam LATENCY_FACTOR = 13; + + localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1; + + localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]), + (DATA_CTL_B4[2] & BYTE_LANES_B4[2]), + (DATA_CTL_B4[1] & BYTE_LANES_B4[1]), + (DATA_CTL_B4[0] & BYTE_LANES_B4[0]), + (DATA_CTL_B3[3] & BYTE_LANES_B3[3]), + (DATA_CTL_B3[2] & BYTE_LANES_B3[2]), + (DATA_CTL_B3[1] & BYTE_LANES_B3[1]), + (DATA_CTL_B3[0] & BYTE_LANES_B3[0]), + (DATA_CTL_B2[3] & BYTE_LANES_B2[3]), + (DATA_CTL_B2[2] & BYTE_LANES_B2[2]), + (DATA_CTL_B2[1] & BYTE_LANES_B2[1]), + (DATA_CTL_B2[0] & BYTE_LANES_B2[0]), + (DATA_CTL_B1[3] & BYTE_LANES_B1[3]), + (DATA_CTL_B1[2] & BYTE_LANES_B1[2]), + (DATA_CTL_B1[1] & BYTE_LANES_B1[1]), + (DATA_CTL_B1[0] & BYTE_LANES_B1[0]), + (DATA_CTL_B0[3] & BYTE_LANES_B0[3]), + (DATA_CTL_B0[2] & BYTE_LANES_B0[2]), + (DATA_CTL_B0[1] & BYTE_LANES_B0[1]), + (DATA_CTL_B0[0] & BYTE_LANES_B0[0])}; + + localparam FINE_ADJ_IDLE = 4'h0; + localparam RST_POSTWAIT = 4'h1; + localparam RST_POSTWAIT1 = 4'h2; + localparam RST_WAIT = 4'h3; + localparam FINE_ADJ_INIT = 4'h4; + localparam FINE_INC = 4'h5; + localparam FINE_INC_WAIT = 4'h6; + localparam FINE_INC_PREWAIT = 4'h7; + localparam DETECT_PREWAIT = 4'h8; + localparam DETECT_DQSFOUND = 4'h9; + localparam PRECH_WAIT = 4'hA; + localparam FINE_DEC = 4'hB; + localparam FINE_DEC_WAIT = 4'hC; + localparam FINE_DEC_PREWAIT = 4'hD; + localparam FINAL_WAIT = 4'hE; + localparam FINE_ADJ_DONE = 4'hF; + + + integer k,l,m,n,p,q,r,s; + + reg dqs_found_start_r; + reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1]; + reg rank_done_r; + reg rank_done_r1; + reg dqs_found_done_r; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3; + reg init_dqsfound_done_r; + reg init_dqsfound_done_r1; + reg init_dqsfound_done_r2; + reg init_dqsfound_done_r3; + reg init_dqsfound_done_r4; + reg init_dqsfound_done_r5; + reg [1:0] rnk_cnt_r; + reg [2:0 ] final_do_index[0:RANKS-1]; + reg [5:0 ] final_do_max[0:RANKS-1]; + reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1]; + reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1]; + reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r; + reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1; + reg [10*HIGHEST_BANK-1:0] retry_cnt; + reg dqsfound_retry_r1; + wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int; + reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank; + reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r; + reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank; + reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r; + reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r; + + // CK/Control byte lanes fine adjust stage + reg fine_adjust; + reg [N_CTL_LANES-1:0] ctl_lane_cnt; + reg [3:0] fine_adj_state_r; + reg fine_adjust_done_r; + reg rst_dqs_find; + reg rst_dqs_find_r1; + reg rst_dqs_find_r2; + reg [5:0] init_dec_cnt; + reg [5:0] dec_cnt; + reg [5:0] inc_cnt; + reg final_dec_done; + reg init_dec_done; + reg first_fail_detect; + reg second_fail_detect; + reg [5:0] first_fail_taps; + reg [5:0] second_fail_taps; + reg [5:0] stable_pass_cnt; + reg [3:0] detect_rd_cnt; + + + + + //*************************************************************************** + // Debug signals + // + //*************************************************************************** + assign dbg_dqs_found_cal[5:0] = first_fail_taps; + assign dbg_dqs_found_cal[11:6] = second_fail_taps; + assign dbg_dqs_found_cal[12] = first_fail_detect; + assign dbg_dqs_found_cal[13] = second_fail_detect; + assign dbg_dqs_found_cal[14] = fine_adjust_done_r; + + + assign pi_dqs_found_rank_done = rank_done_r; + assign pi_dqs_found_done = dqs_found_done_r; + + generate + genvar rnk_cnt; + if (HIGHEST_BANK == 3) begin // Three Bank Interface + for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop + assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; + assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; + assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12]; + assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; + assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; + assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12]; + end + end else if (HIGHEST_BANK == 2) begin // Two Bank Interface + for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop + assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; + assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; + assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; + assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; + assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; + end + end else begin // Single Bank Interface + for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop + assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; + assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; + assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; + end + end + endgenerate + + // final_data_offset is used during write calibration and during + // normal operation. One rd_data_offset value per rank for entire + // interface + generate + if (HIGHEST_BANK == 3) begin // Three I/O Bank interface + assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : + final_data_offset[rnk_cnt_r][0+:6]; + assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : + final_data_offset[rnk_cnt_r][6+:6]; + assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] : + final_data_offset[rnk_cnt_r][12+:6]; + end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface + assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : + final_data_offset[rnk_cnt_r][0+:6]; + assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : + final_data_offset[rnk_cnt_r][6+:6]; + assign rd_data_offset_2 = 'd0; + end else begin + assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : + final_data_offset[rnk_cnt_r][0+:6]; + assign rd_data_offset_1 = 'd0; + assign rd_data_offset_2 = 'd0; + end + endgenerate + + assign rd_data_offset_cal_done = init_dqsfound_done_r; + assign fine_adjust_lane_cnt = ctl_lane_cnt; + + //************************************************************************** + // DQSFOUND all and any generation + // pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are + // asserted + // pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx + // is asserted + //************************************************************************** + + generate + if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12)) + assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3; + else if ((HIGHEST_LANE == 3) || (HIGHEST_LANE == 7) || (HIGHEST_LANE == 11)) + assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3}; + else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10)) + assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3}; + else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9)) + assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3}; + endgenerate + + always @(posedge clk) begin + if (rst) begin + for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found + pi_dqs_found_all_bank[k] <= #TCQ 'b0; + pi_dqs_found_any_bank[k] <= #TCQ 'b0; + end + end else if (pi_dqs_found_start) begin + for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found + pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) & + (!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) & + (!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) & + (!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]); + pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) | + (DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) | + (DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) | + (DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]); + end + end + end + + + always @(posedge clk) begin + pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank; + pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank; + end + +//***************************************************************************** +// Counter to increase number of 4 back-to-back reads per rd_data_offset and +// per CK/A/C tap value +//***************************************************************************** + + always @(posedge clk) begin + if (rst || (detect_rd_cnt == 'd0)) + detect_rd_cnt <= #TCQ NUM_READS; + else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0)) + detect_rd_cnt <= #TCQ detect_rd_cnt - 1; + end + + + //************************************************************************** + // Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls + // + //************************************************************************** + + assign fine_adjust_done = fine_adjust_done_r; + + always @(posedge clk) begin + rst_dqs_find_r1 <= #TCQ rst_dqs_find; + rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1; + end + + always @(posedge clk) begin + if(rst)begin + fine_adjust <= #TCQ 1'b0; + ctl_lane_cnt <= #TCQ 'd0; + fine_adj_state_r <= #TCQ FINE_ADJ_IDLE; + fine_adjust_done_r <= #TCQ 1'b0; + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b0; + rst_dqs_find <= #TCQ 1'b0; + init_dec_cnt <= #TCQ 'd31; + dec_cnt <= #TCQ 'd0; + inc_cnt <= #TCQ 'd0; + init_dec_done <= #TCQ 1'b0; + final_dec_done <= #TCQ 1'b0; + first_fail_detect <= #TCQ 1'b0; + second_fail_detect <= #TCQ 1'b0; + first_fail_taps <= #TCQ 'd0; + second_fail_taps <= #TCQ 'd0; + stable_pass_cnt <= #TCQ 'd0; + dqs_found_prech_req<= #TCQ 1'b0; + end else begin + case (fine_adj_state_r) + + FINE_ADJ_IDLE: begin + if (init_dqsfound_done_r5) begin + if (SIM_CAL_OPTION == "FAST_CAL") begin + fine_adjust <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ FINE_ADJ_DONE; + rst_dqs_find <= #TCQ 1'b0; + end else begin + fine_adjust <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + rst_dqs_find <= #TCQ 1'b1; + end + end + end + + RST_WAIT: begin + if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin + rst_dqs_find <= #TCQ 1'b0; + if (|init_dec_cnt) + fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; + else if (final_dec_done) + fine_adj_state_r <= #TCQ FINE_ADJ_DONE; + else + fine_adj_state_r <= #TCQ RST_POSTWAIT; + end + end + + RST_POSTWAIT: begin + fine_adj_state_r <= #TCQ RST_POSTWAIT1; + end + + RST_POSTWAIT1: begin + fine_adj_state_r <= #TCQ FINE_ADJ_INIT; + end + + FINE_ADJ_INIT: begin + //if (detect_pi_found_dqs && (inc_cnt < 'd63)) + fine_adj_state_r <= #TCQ FINE_INC; + end + + FINE_INC: begin + fine_adj_state_r <= #TCQ FINE_INC_WAIT; + ck_po_stg2_f_indec <= #TCQ 1'b1; + ck_po_stg2_f_en <= #TCQ 1'b1; + if (ctl_lane_cnt == N_CTL_LANES-1) + inc_cnt <= #TCQ inc_cnt + 1; + end + + FINE_INC_WAIT: begin + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b0; + if (ctl_lane_cnt != N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; + fine_adj_state_r <= #TCQ FINE_INC_PREWAIT; + end else if (ctl_lane_cnt == N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ 'd0; + fine_adj_state_r <= #TCQ DETECT_PREWAIT; + end + end + + FINE_INC_PREWAIT: begin + fine_adj_state_r <= #TCQ FINE_INC; + end + + DETECT_PREWAIT: begin + if (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) + fine_adj_state_r <= #TCQ DETECT_DQSFOUND; + else + fine_adj_state_r <= #TCQ DETECT_PREWAIT; + end + + DETECT_DQSFOUND: begin + if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin + stable_pass_cnt <= #TCQ 'd0; + if (~first_fail_detect && (inc_cnt == 'd63)) begin + // First failing tap detected at 63 taps + // then decrement to 31 + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ 'd32; + end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin + // First failing tap detected at greater than 30 taps + // then stop looking for second edge and decrement + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ (inc_cnt>>1) + 1; + end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin + // First failing tap detected, continue incrementing + // until either second failing tap detected or 63 + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + rst_dqs_find <= #TCQ 1'b1; + if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin + dqs_found_prech_req <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ PRECH_WAIT; + end else + fine_adj_state_r <= #TCQ RST_WAIT; + end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin + // Consecutive 30 taps of passing region was not found + // continue incrementing + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + rst_dqs_find <= #TCQ 1'b1; + if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin + dqs_found_prech_req <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ PRECH_WAIT; + end else + fine_adj_state_r <= #TCQ RST_WAIT; + end else if (first_fail_detect && (inc_cnt == 'd63)) begin + if (stable_pass_cnt < 'd30) begin + // Consecutive 30 taps of passing region was not found + // from tap 0 to 63 so decrement back to 31 + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ 'd32; + end else begin + // Consecutive 30 taps of passing region was found + // between first_fail_taps and 63 + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + end + end else begin + // Second failing tap detected, decrement to center of + // failing taps + second_fail_detect <= #TCQ 1'b1; + second_fail_taps <= #TCQ inc_cnt; + dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + fine_adj_state_r <= #TCQ FINE_DEC; + end + end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin + stable_pass_cnt <= #TCQ stable_pass_cnt + 1; + if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) || + (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin + dqs_found_prech_req <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ PRECH_WAIT; + end else if (inc_cnt < 'd63) begin + rst_dqs_find <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + end else begin + fine_adj_state_r <= #TCQ FINE_DEC; + if (~first_fail_detect || (first_fail_taps > 'd33)) + // No failing taps detected, decrement by 31 + dec_cnt <= #TCQ 'd32; + //else if (first_fail_detect && (stable_pass_cnt > 'd28)) + // // First failing tap detected between 0 and 34 + // // decrement midpoint between 63 and failing tap + // dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + else + // First failing tap detected + // decrement to midpoint between 63 and failing tap + dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + end + end + end + + PRECH_WAIT: begin + if (prech_done) begin + dqs_found_prech_req <= #TCQ 1'b0; + rst_dqs_find <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + end + end + + + FINE_DEC: begin + fine_adj_state_r <= #TCQ FINE_DEC_WAIT; + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b1; + if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0)) + init_dec_cnt <= #TCQ init_dec_cnt - 1; + else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0)) + dec_cnt <= #TCQ dec_cnt - 1; + end + + FINE_DEC_WAIT: begin + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b0; + if (ctl_lane_cnt != N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; + fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; + end else if (ctl_lane_cnt == N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ 'd0; + if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0)) + fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; + else begin + fine_adj_state_r <= #TCQ FINAL_WAIT; + if ((init_dec_cnt == 'd0) && ~init_dec_done) + init_dec_done <= #TCQ 1'b1; + else + final_dec_done <= #TCQ 1'b1; + end + end + end + + FINE_DEC_PREWAIT: begin + fine_adj_state_r <= #TCQ FINE_DEC; + end + + FINAL_WAIT: begin + rst_dqs_find <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + end + + FINE_ADJ_DONE: begin + if (&pi_dqs_found_all_bank) begin + fine_adjust_done_r <= #TCQ 1'b1; + rst_dqs_find <= #TCQ 1'b0; + fine_adj_state_r <= #TCQ FINE_ADJ_DONE; + end + end + + endcase + end + end + + + + +//***************************************************************************** + + + always@(posedge clk) + dqs_found_start_r <= #TCQ pi_dqs_found_start; + + + always @(posedge clk) begin + if (rst) + rnk_cnt_r <= #TCQ 2'b00; + else if (init_dqsfound_done_r) + rnk_cnt_r <= #TCQ rnk_cnt_r; + else if (rank_done_r) + rnk_cnt_r <= #TCQ rnk_cnt_r + 1; + end + + //***************************************************************** + // Read data_offset calibration done signal + //***************************************************************** + + always @(posedge clk) begin + if (rst || (|pi_rst_stg1_cal_r)) + init_dqsfound_done_r <= #TCQ 1'b0; + else if (&pi_dqs_found_all_bank) begin + if (rnk_cnt_r == RANKS-1) + init_dqsfound_done_r <= #TCQ 1'b1; + else + init_dqsfound_done_r <= #TCQ 1'b0; + end + end + + always @(posedge clk) begin + if (rst || + (init_dqsfound_done_r && (rnk_cnt_r == RANKS-1))) + rank_done_r <= #TCQ 1'b0; + else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r)) + rank_done_r <= #TCQ 1'b1; + else + rank_done_r <= #TCQ 1'b0; + end + + always @(posedge clk) begin + pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes; + pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1; + pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2; + init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r; + init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1; + init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2; + init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3; + init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4; + rank_done_r1 <= #TCQ rank_done_r; + dqsfound_retry_r1 <= #TCQ dqsfound_retry; + end + + + always @(posedge clk) begin + if (rst) + dqs_found_done_r <= #TCQ 1'b0; + else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 && + (fine_adj_state_r == FINE_ADJ_DONE)) + dqs_found_done_r <= #TCQ 1'b1; + else + dqs_found_done_r <= #TCQ 1'b0; + end + + + generate + if (HIGHEST_BANK == 3) begin // Three I/O Bank interface + + // Reset read data offset calibration in all DQS Phaser_INs + // in a Bank after the read data offset value for a rank is determined + // or if within a Bank DQSFOUND is not asserted for all DQSs + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[0]) || + (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[1]) || + (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust) + pi_rst_stg1_cal_r[2] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[2]) || + (pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) || + (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) + pi_rst_stg1_cal_r[2] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[2]) + pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) + pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; + end + + //***************************************************************************** + // Retry counter to track number of DQSFOUND retries + //***************************************************************************** + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[0+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && + ~pi_dqs_found_all_bank[0]) + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; + else + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; + end + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[10+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) && + ~pi_dqs_found_all_bank[1]) + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; + else + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; + end + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[20+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)) && + ~pi_dqs_found_all_bank[2]) + retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1; + else + retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10]; + end + + // Error generation in case pi_dqs_found_all_bank + // is not asserted + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[0] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + pi_dqs_found_err_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[1] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) + pi_dqs_found_err_r[1] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[2] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) + pi_dqs_found_err_r[2] <= #TCQ 1'b1; + end + + // Read data offset value for all DQS in a Bank + always @(posedge clk) begin + if (rst) begin + for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop + rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && + //(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][0+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1; + end + + always @(posedge clk) begin + if (rst) begin + for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop + rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) + rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && + //(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][6+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1; + end + + always @(posedge clk) begin + if (rst) begin + for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop + rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) + rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] && + //(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL -1)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][12+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] - 1; + end + +//***************************************************************************** +// Two I/O Bank Interface +//***************************************************************************** + end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface + + // Reset read data offset calibration in all DQS Phaser_INs + // in a Bank after the read data offset value for a rank is determined + // or if within a Bank DQSFOUND is not asserted for all DQSs + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[0]) || + (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[1]) || + (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + end + + //***************************************************************************** + // Retry counter to track number of DQSFOUND retries + //***************************************************************************** + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[0+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && + ~pi_dqs_found_all_bank[0]) + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; + else + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; + end + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[10+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) && + ~pi_dqs_found_all_bank[1]) + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; + else + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; + end + + // Error generation in case pi_dqs_found_all_bank + // is not asserted + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[0] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + pi_dqs_found_err_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[1] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) + pi_dqs_found_err_r[1] <= #TCQ 1'b1; + end + + + // Read data offset value for all DQS in a Bank + always @(posedge clk) begin + if (rst) begin + for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop + rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && + //(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][0+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1; + end + + always @(posedge clk) begin + if (rst) begin + for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop + rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) + rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && + //(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][6+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1; + end +//***************************************************************************** +// One I/O Bank Interface +//***************************************************************************** + end else begin // One I/O Bank Interface + + // Read data offset value for all DQS in Bank0 + always @(posedge clk) begin + if (rst) begin + for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop + rd_byte_data_offset[l] <= #TCQ nCL + nAL + LATENCY_FACTOR; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL - 1))) + rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL + LATENCY_FACTOR; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && + //(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL -1)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r] + <= #TCQ rd_byte_data_offset[rnk_cnt_r] - 1; + end + + // Reset read data offset calibration in all DQS Phaser_INs + // in a Bank after the read data offset value for a rank is determined + // or if within a Bank DQSFOUND is not asserted for all DQSs + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[0]) || + (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + end + + //***************************************************************************** + // Retry counter to track number of DQSFOUND retries + //***************************************************************************** + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[0+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && + ~pi_dqs_found_all_bank[0]) + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; + else + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; + end + + // Error generation in case pi_dqs_found_all_bank + // is not asserted even with 3 dqfound retries + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[0] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + pi_dqs_found_err_r[0] <= #TCQ 1'b1; + end + + end + endgenerate + + always @(posedge clk) begin + if (rst) + pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}}; + else if (rst_dqs_find) + pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}}; + else + pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r; + end + + + + // Final read data offset value to be used during write calibration and + // normal operation + generate + genvar i; + genvar j; + for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop + reg [5:0] final_do_cand [RANKS-1:0]; + // combinatorially select the candidate offset for the bank + // indexed by final_do_index + if (HIGHEST_BANK == 3) begin + always @(*) begin + case (final_do_index[i]) + 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; + 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; + 3'b010: final_do_cand[i] = final_data_offset[i][17:12]; + default: final_do_cand[i] = 'd0; + endcase + end + end else if (HIGHEST_BANK == 2) begin + always @(*) begin + case (final_do_index[i]) + 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; + 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; + 3'b010: final_do_cand[i] = 'd0; + default: final_do_cand[i] = 'd0; + endcase + end + end else begin + always @(*) begin + case (final_do_index[i]) + 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; + 3'b001: final_do_cand[i] = 'd0; + 3'b010: final_do_cand[i] = 'd0; + default: final_do_cand[i] = 'd0; + endcase + end + end + + always @(posedge clk) begin + if (rst) + final_do_max[i] <= #TCQ 0; + else begin + final_do_max[i] <= #TCQ final_do_max[i]; // default + case (final_do_index[i]) + 3'b000: if ( | DATA_PRESENT[3:0]) + if (final_do_max[i] < final_do_cand[i]) + if (CWL_M % 2) // odd latency CAS slot 1 + final_do_max[i] <= #TCQ final_do_cand[i] - 1; + else + final_do_max[i] <= #TCQ final_do_cand[i]; + 3'b001: if ( | DATA_PRESENT[7:4]) + if (final_do_max[i] < final_do_cand[i]) + if (CWL_M % 2) // odd latency CAS slot 1 + final_do_max[i] <= #TCQ final_do_cand[i] - 1; + else + final_do_max[i] <= #TCQ final_do_cand[i]; + 3'b010: if ( | DATA_PRESENT[11:8]) + if (final_do_max[i] < final_do_cand[i]) + if (CWL_M % 2) // odd latency CAS slot 1 + final_do_max[i] <= #TCQ final_do_cand[i] - 1; + else + final_do_max[i] <= #TCQ final_do_cand[i]; + default: + final_do_max[i] <= #TCQ final_do_max[i]; + endcase + end + end + + always @(posedge clk) + if (rst) begin + final_do_index[i] <= #TCQ 0; + end + else begin + final_do_index[i] <= #TCQ final_do_index[i] + 1; + end + + for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop + + always @(posedge clk) begin + if (rst) begin + final_data_offset[i][6*j+:6] <= #TCQ 'b0; + end + else begin + //if (dqsfound_retry[j]) + // final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; + //else + if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin + if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane + final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; + if (CWL_M % 2) // odd latency CAS slot 1 + final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1; + else // even latency CAS slot 0 + final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; + end + end + else if (init_dqsfound_done_r5 ) begin + if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes + final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i]; + final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i]; + end + end + end + end + end + end + endgenerate + + + // Error generation in case pi_found_dqs signal from Phaser_IN + // is not asserted when a common rddata_offset value is used + + always @(posedge clk) begin + pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r; + end + + + +endmodule + + + + + + diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v new file mode 100644 index 0000000..fff16b6 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v @@ -0,0 +1,1199 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: +// \ \ Application: MIG +// / / Filename: ddr_phy_dqs_found_cal.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// Read leveling calibration logic +// NOTES: +// 1. Phaser_In DQSFOUND calibration +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $ +**$Date: 2011/06/02 08:35:08 $ +**$Author: +**$Revision: +**$Source: +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_dqs_found_cal_hr # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter nCK_PER_CLK = 2, // # of memory clocks per CLK + parameter nCL = 5, // Read CAS latency + parameter AL = "0", + parameter nCWL = 5, // Write CAS latency + parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" + parameter RANKS = 1, // # of memory ranks in the system + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter REG_CTRL = "ON", // "ON" for registered DIMM + parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps + parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate + parameter N_CTL_LANES = 3, // Number of control byte lanes + parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl) + parameter HIGHEST_BANK = 3, // Sum of I/O Banks + parameter BYTE_LANES_B0 = 4'b1111, + parameter BYTE_LANES_B1 = 4'b0000, + parameter BYTE_LANES_B2 = 4'b0000, + parameter BYTE_LANES_B3 = 4'b0000, + parameter BYTE_LANES_B4 = 4'b0000, + parameter DATA_CTL_B0 = 4'hc, + parameter DATA_CTL_B1 = 4'hf, + parameter DATA_CTL_B2 = 4'hf, + parameter DATA_CTL_B3 = 4'hf, + parameter DATA_CTL_B4 = 4'hf + ) + ( + input clk, + input rst, + input dqsfound_retry, + // From phy_init + input pi_dqs_found_start, + input detect_pi_found_dqs, + input prech_done, + // DQSFOUND per Phaser_IN + input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, + + output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal, + + // To phy_init + output [5:0] rd_data_offset_0, + output [5:0] rd_data_offset_1, + output [5:0] rd_data_offset_2, + output pi_dqs_found_rank_done, + output pi_dqs_found_done, + output reg pi_dqs_found_err, + output [6*RANKS-1:0] rd_data_offset_ranks_0, + output [6*RANKS-1:0] rd_data_offset_ranks_1, + output [6*RANKS-1:0] rd_data_offset_ranks_2, + output reg dqsfound_retry_done, + output reg dqs_found_prech_req, + //To MC + output [6*RANKS-1:0] rd_data_offset_ranks_mc_0, + output [6*RANKS-1:0] rd_data_offset_ranks_mc_1, + output [6*RANKS-1:0] rd_data_offset_ranks_mc_2, + + input [8:0] po_counter_read_val, + output rd_data_offset_cal_done, + output fine_adjust_done, + output [N_CTL_LANES-1:0] fine_adjust_lane_cnt, + output reg ck_po_stg2_f_indec, + output reg ck_po_stg2_f_en, + output [255:0] dbg_dqs_found_cal + ); + + + // For non-zero AL values + localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; + + // Adding the register dimm latency to write latency + localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; + + // Added to reduce simulation time + localparam LATENCY_FACTOR = 13; + + localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1; + + localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]), + (DATA_CTL_B4[2] & BYTE_LANES_B4[2]), + (DATA_CTL_B4[1] & BYTE_LANES_B4[1]), + (DATA_CTL_B4[0] & BYTE_LANES_B4[0]), + (DATA_CTL_B3[3] & BYTE_LANES_B3[3]), + (DATA_CTL_B3[2] & BYTE_LANES_B3[2]), + (DATA_CTL_B3[1] & BYTE_LANES_B3[1]), + (DATA_CTL_B3[0] & BYTE_LANES_B3[0]), + (DATA_CTL_B2[3] & BYTE_LANES_B2[3]), + (DATA_CTL_B2[2] & BYTE_LANES_B2[2]), + (DATA_CTL_B2[1] & BYTE_LANES_B2[1]), + (DATA_CTL_B2[0] & BYTE_LANES_B2[0]), + (DATA_CTL_B1[3] & BYTE_LANES_B1[3]), + (DATA_CTL_B1[2] & BYTE_LANES_B1[2]), + (DATA_CTL_B1[1] & BYTE_LANES_B1[1]), + (DATA_CTL_B1[0] & BYTE_LANES_B1[0]), + (DATA_CTL_B0[3] & BYTE_LANES_B0[3]), + (DATA_CTL_B0[2] & BYTE_LANES_B0[2]), + (DATA_CTL_B0[1] & BYTE_LANES_B0[1]), + (DATA_CTL_B0[0] & BYTE_LANES_B0[0])}; + + localparam FINE_ADJ_IDLE = 4'h0; + localparam RST_POSTWAIT = 4'h1; + localparam RST_POSTWAIT1 = 4'h2; + localparam RST_WAIT = 4'h3; + localparam FINE_ADJ_INIT = 4'h4; + localparam FINE_INC = 4'h5; + localparam FINE_INC_WAIT = 4'h6; + localparam FINE_INC_PREWAIT = 4'h7; + localparam DETECT_PREWAIT = 4'h8; + localparam DETECT_DQSFOUND = 4'h9; + localparam PRECH_WAIT = 4'hA; + localparam FINE_DEC = 4'hB; + localparam FINE_DEC_WAIT = 4'hC; + localparam FINE_DEC_PREWAIT = 4'hD; + localparam FINAL_WAIT = 4'hE; + localparam FINE_ADJ_DONE = 4'hF; + + + integer k,l,m,n,p,q,r,s; + + reg dqs_found_start_r; + reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1]; + reg rank_done_r; + reg rank_done_r1; + reg dqs_found_done_r; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3; + reg init_dqsfound_done_r; + reg init_dqsfound_done_r1; + reg init_dqsfound_done_r2; + reg init_dqsfound_done_r3; + reg init_dqsfound_done_r4; + reg init_dqsfound_done_r5; + reg [1:0] rnk_cnt_r; + reg [2:0 ] final_do_index[0:RANKS-1]; + reg [5:0 ] final_do_max[0:RANKS-1]; + reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1]; + reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1]; + reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r; + reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1; + reg [10*HIGHEST_BANK-1:0] retry_cnt; + reg dqsfound_retry_r1; + wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int; + reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank; + reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r; + reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank; + reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r; + reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r; + + // CK/Control byte lanes fine adjust stage + reg fine_adjust; + reg [N_CTL_LANES-1:0] ctl_lane_cnt; + reg [3:0] fine_adj_state_r; + reg fine_adjust_done_r; + reg rst_dqs_find; + reg rst_dqs_find_r1; + reg rst_dqs_find_r2; + reg [5:0] init_dec_cnt; + reg [5:0] dec_cnt; + reg [5:0] inc_cnt; + reg final_dec_done; + reg init_dec_done; + reg first_fail_detect; + reg second_fail_detect; + reg [5:0] first_fail_taps; + reg [5:0] second_fail_taps; + reg [5:0] stable_pass_cnt; + reg [3:0] detect_rd_cnt; + + + + + //*************************************************************************** + // Debug signals + // + //*************************************************************************** + assign dbg_dqs_found_cal[5:0] = first_fail_taps; + assign dbg_dqs_found_cal[11:6] = second_fail_taps; + assign dbg_dqs_found_cal[12] = first_fail_detect; + assign dbg_dqs_found_cal[13] = second_fail_detect; + assign dbg_dqs_found_cal[14] = fine_adjust_done_r; + + + assign pi_dqs_found_rank_done = rank_done_r; + assign pi_dqs_found_done = dqs_found_done_r; + + generate + genvar rnk_cnt; + if (HIGHEST_BANK == 3) begin // Three Bank Interface + for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop + assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; + assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; + assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12]; + assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; + assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; + assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12]; + end + end else if (HIGHEST_BANK == 2) begin // Two Bank Interface + for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop + assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; + assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; + assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; + assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; + assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; + end + end else begin // Single Bank Interface + for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop + assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; + assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; + assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; + end + end + endgenerate + + // final_data_offset is used during write calibration and during + // normal operation. One rd_data_offset value per rank for entire + // interface + generate + if (HIGHEST_BANK == 3) begin // Three I/O Bank interface + assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : + final_data_offset[rnk_cnt_r][0+:6]; + assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : + final_data_offset[rnk_cnt_r][6+:6]; + assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] : + final_data_offset[rnk_cnt_r][12+:6]; + end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface + assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : + final_data_offset[rnk_cnt_r][0+:6]; + assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : + final_data_offset[rnk_cnt_r][6+:6]; + assign rd_data_offset_2 = 'd0; + end else begin + assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : + final_data_offset[rnk_cnt_r][0+:6]; + assign rd_data_offset_1 = 'd0; + assign rd_data_offset_2 = 'd0; + end + endgenerate + + assign rd_data_offset_cal_done = init_dqsfound_done_r; + assign fine_adjust_lane_cnt = ctl_lane_cnt; + + //************************************************************************** + // DQSFOUND all and any generation + // pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are + // asserted + // pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx + // is asserted + //************************************************************************** + + generate + if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12)) + assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3; + else if ((HIGHEST_LANE == 3) || (HIGHEST_LANE == 7) || (HIGHEST_LANE == 11)) + assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3}; + else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10)) + assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3}; + else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9)) + assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3}; + endgenerate + + always @(posedge clk) begin + if (rst) begin + for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found + pi_dqs_found_all_bank[k] <= #TCQ 'b0; + pi_dqs_found_any_bank[k] <= #TCQ 'b0; + end + end else if (pi_dqs_found_start) begin + for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found + pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) & + (!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) & + (!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) & + (!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]); + pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) | + (DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) | + (DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) | + (DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]); + end + end + end + + + always @(posedge clk) begin + pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank; + pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank; + end + +//***************************************************************************** +// Counter to increase number of 4 back-to-back reads per rd_data_offset and +// per CK/A/C tap value +//***************************************************************************** + + always @(posedge clk) begin + if (rst || (detect_rd_cnt == 'd0)) + detect_rd_cnt <= #TCQ NUM_READS; + else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0)) + detect_rd_cnt <= #TCQ detect_rd_cnt - 1; + end + + //************************************************************************** + // Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls + // + //************************************************************************** + + assign fine_adjust_done = fine_adjust_done_r; + + always @(posedge clk) begin + rst_dqs_find_r1 <= #TCQ rst_dqs_find; + rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1; + end + + always @(posedge clk) begin + if(rst)begin + fine_adjust <= #TCQ 1'b0; + ctl_lane_cnt <= #TCQ 'd0; + fine_adj_state_r <= #TCQ FINE_ADJ_IDLE; + fine_adjust_done_r <= #TCQ 1'b0; + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b0; + rst_dqs_find <= #TCQ 1'b0; + init_dec_cnt <= #TCQ 'd31; + dec_cnt <= #TCQ 'd0; + inc_cnt <= #TCQ 'd0; + init_dec_done <= #TCQ 1'b0; + final_dec_done <= #TCQ 1'b0; + first_fail_detect <= #TCQ 1'b0; + second_fail_detect <= #TCQ 1'b0; + first_fail_taps <= #TCQ 'd0; + second_fail_taps <= #TCQ 'd0; + stable_pass_cnt <= #TCQ 'd0; + dqs_found_prech_req<= #TCQ 1'b0; + end else begin + case (fine_adj_state_r) + + FINE_ADJ_IDLE: begin + if (init_dqsfound_done_r5) begin + if (SIM_CAL_OPTION == "FAST_CAL") begin + fine_adjust <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ FINE_ADJ_DONE; + rst_dqs_find <= #TCQ 1'b0; + end else begin + fine_adjust <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + rst_dqs_find <= #TCQ 1'b1; + end + end + end + + RST_WAIT: begin + if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin + rst_dqs_find <= #TCQ 1'b0; + if (|init_dec_cnt) + fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; + else if (final_dec_done) + fine_adj_state_r <= #TCQ FINE_ADJ_DONE; + else + fine_adj_state_r <= #TCQ RST_POSTWAIT; + end + end + + RST_POSTWAIT: begin + fine_adj_state_r <= #TCQ RST_POSTWAIT1; + end + + RST_POSTWAIT1: begin + fine_adj_state_r <= #TCQ FINE_ADJ_INIT; + end + + FINE_ADJ_INIT: begin + //if (detect_pi_found_dqs && (inc_cnt < 'd63)) + fine_adj_state_r <= #TCQ FINE_INC; + end + + FINE_INC: begin + fine_adj_state_r <= #TCQ FINE_INC_WAIT; + ck_po_stg2_f_indec <= #TCQ 1'b1; + ck_po_stg2_f_en <= #TCQ 1'b1; + if (ctl_lane_cnt == N_CTL_LANES-1) + inc_cnt <= #TCQ inc_cnt + 1; + end + + FINE_INC_WAIT: begin + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b0; + if (ctl_lane_cnt != N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; + fine_adj_state_r <= #TCQ FINE_INC_PREWAIT; + end else if (ctl_lane_cnt == N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ 'd0; + fine_adj_state_r <= #TCQ DETECT_PREWAIT; + end + end + + FINE_INC_PREWAIT: begin + fine_adj_state_r <= #TCQ FINE_INC; + end + + DETECT_PREWAIT: begin + if (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) + fine_adj_state_r <= #TCQ DETECT_DQSFOUND; + else + fine_adj_state_r <= #TCQ DETECT_PREWAIT; + end + + DETECT_DQSFOUND: begin + if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin + stable_pass_cnt <= #TCQ 'd0; + if (~first_fail_detect && (inc_cnt == 'd63)) begin + // First failing tap detected at 63 taps + // then decrement to 31 + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ 'd32; + end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin + // First failing tap detected at greater than 30 taps + // then stop looking for second edge and decrement + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ (inc_cnt>>1) + 1; + end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin + // First failing tap detected, continue incrementing + // until either second failing tap detected or 63 + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + rst_dqs_find <= #TCQ 1'b1; + if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin + dqs_found_prech_req <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ PRECH_WAIT; + end else + fine_adj_state_r <= #TCQ RST_WAIT; + end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin + // Consecutive 30 taps of passing region was not found + // continue incrementing + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + rst_dqs_find <= #TCQ 1'b1; + if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin + dqs_found_prech_req <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ PRECH_WAIT; + end else + fine_adj_state_r <= #TCQ RST_WAIT; + end else if (first_fail_detect && (inc_cnt == 'd63)) begin + if (stable_pass_cnt < 'd30) begin + // Consecutive 30 taps of passing region was not found + // from tap 0 to 63 so decrement back to 31 + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ 'd32; + end else begin + // Consecutive 30 taps of passing region was found + // between first_fail_taps and 63 + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + end + end else begin + // Second failing tap detected, decrement to center of + // failing taps + second_fail_detect <= #TCQ 1'b1; + second_fail_taps <= #TCQ inc_cnt; + dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + fine_adj_state_r <= #TCQ FINE_DEC; + end + end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin + stable_pass_cnt <= #TCQ stable_pass_cnt + 1; + if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) || + (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin + dqs_found_prech_req <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ PRECH_WAIT; + end else if (inc_cnt < 'd63) begin + rst_dqs_find <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + end else begin + fine_adj_state_r <= #TCQ FINE_DEC; + if (~first_fail_detect || (first_fail_taps > 'd33)) + // No failing taps detected, decrement by 31 + dec_cnt <= #TCQ 'd32; + //else if (first_fail_detect && (stable_pass_cnt > 'd28)) + // // First failing tap detected between 0 and 34 + // // decrement midpoint between 63 and failing tap + // dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + else + // First failing tap detected + // decrement to midpoint between 63 and failing tap + dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + end + end + end + + PRECH_WAIT: begin + if (prech_done) begin + dqs_found_prech_req <= #TCQ 1'b0; + rst_dqs_find <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + end + end + + + FINE_DEC: begin + fine_adj_state_r <= #TCQ FINE_DEC_WAIT; + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b1; + if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0)) + init_dec_cnt <= #TCQ init_dec_cnt - 1; + else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0)) + dec_cnt <= #TCQ dec_cnt - 1; + end + + FINE_DEC_WAIT: begin + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b0; + if (ctl_lane_cnt != N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; + fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; + end else if (ctl_lane_cnt == N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ 'd0; + if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0)) + fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; + else begin + fine_adj_state_r <= #TCQ FINAL_WAIT; + if ((init_dec_cnt == 'd0) && ~init_dec_done) + init_dec_done <= #TCQ 1'b1; + else + final_dec_done <= #TCQ 1'b1; + end + end + end + + FINE_DEC_PREWAIT: begin + fine_adj_state_r <= #TCQ FINE_DEC; + end + + FINAL_WAIT: begin + rst_dqs_find <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + end + + FINE_ADJ_DONE: begin + if (&pi_dqs_found_all_bank) begin + fine_adjust_done_r <= #TCQ 1'b1; + rst_dqs_find <= #TCQ 1'b0; + fine_adj_state_r <= #TCQ FINE_ADJ_DONE; + end + end + + endcase + end + end + + + + +//***************************************************************************** + + + always@(posedge clk) + dqs_found_start_r <= #TCQ pi_dqs_found_start; + + + always @(posedge clk) begin + if (rst) + rnk_cnt_r <= #TCQ 2'b00; + else if (init_dqsfound_done_r) + rnk_cnt_r <= #TCQ rnk_cnt_r; + else if (rank_done_r) + rnk_cnt_r <= #TCQ rnk_cnt_r + 1; + end + + //***************************************************************** + // Read data_offset calibration done signal + //***************************************************************** + + always @(posedge clk) begin + if (rst || (|pi_rst_stg1_cal_r)) + init_dqsfound_done_r <= #TCQ 1'b0; + else if (&pi_dqs_found_all_bank) begin + if (rnk_cnt_r == RANKS-1) + init_dqsfound_done_r <= #TCQ 1'b1; + else + init_dqsfound_done_r <= #TCQ 1'b0; + end + end + + always @(posedge clk) begin + if (rst || + (init_dqsfound_done_r && (rnk_cnt_r == RANKS-1))) + rank_done_r <= #TCQ 1'b0; + else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r)) + rank_done_r <= #TCQ 1'b1; + else + rank_done_r <= #TCQ 1'b0; + end + + always @(posedge clk) begin + pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes; + pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1; + pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2; + init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r; + init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1; + init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2; + init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3; + init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4; + rank_done_r1 <= #TCQ rank_done_r; + dqsfound_retry_r1 <= #TCQ dqsfound_retry; + end + + + always @(posedge clk) begin + if (rst) + dqs_found_done_r <= #TCQ 1'b0; + else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 && + (fine_adj_state_r == FINE_ADJ_DONE)) + dqs_found_done_r <= #TCQ 1'b1; + else + dqs_found_done_r <= #TCQ 1'b0; + end + + + generate + if (HIGHEST_BANK == 3) begin // Three I/O Bank interface + + // Reset read data offset calibration in all DQS Phaser_INs + // in a Bank after the read data offset value for a rank is determined + // or if within a Bank DQSFOUND is not asserted for all DQSs + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[0]) || + (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[1]) || + (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust) + pi_rst_stg1_cal_r[2] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[2]) || + (pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) || + (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_rst_stg1_cal_r[2] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[2]) + pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) + pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; + end + + //***************************************************************************** + // Retry counter to track number of DQSFOUND retries + //***************************************************************************** + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[0+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && + ~pi_dqs_found_all_bank[0]) + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; + else + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; + end + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[10+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && + ~pi_dqs_found_all_bank[1]) + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; + else + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; + end + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[20+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && + ~pi_dqs_found_all_bank[2]) + retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1; + else + retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10]; + end + + // Error generation in case pi_dqs_found_all_bank + // is not asserted + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[0] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_dqs_found_err_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[1] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_dqs_found_err_r[1] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[2] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_dqs_found_err_r[2] <= #TCQ 1'b1; + end + + // Read data offset value for all DQS in a Bank + always @(posedge clk) begin + if (rst) begin + for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop + rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && + //(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][0+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1; + end + + always @(posedge clk) begin + if (rst) begin + for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop + rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && + //(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][6+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1; + end + + always @(posedge clk) begin + if (rst) begin + for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop + rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL - 2; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL - 2; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] && + //(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL + LATENCY_FACTOR)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][12+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] + 1; + end + +//***************************************************************************** +// Two I/O Bank Interface +//***************************************************************************** + end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface + + // Reset read data offset calibration in all DQS Phaser_INs + // in a Bank after the read data offset value for a rank is determined + // or if within a Bank DQSFOUND is not asserted for all DQSs + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[0]) || + (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[1]) || + (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + end + + //***************************************************************************** + // Retry counter to track number of DQSFOUND retries + //***************************************************************************** + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[0+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && + ~pi_dqs_found_all_bank[0]) + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; + else + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; + end + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[10+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && + ~pi_dqs_found_all_bank[1]) + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; + else + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; + end + + + // Error generation in case pi_dqs_found_all_bank + // is not asserted + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[0] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_dqs_found_err_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[1] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_dqs_found_err_r[1] <= #TCQ 1'b1; + end + + + // Read data offset value for all DQS in a Bank + always @(posedge clk) begin + if (rst) begin + for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop + rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && + //(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][0+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1; + end + + always @(posedge clk) begin + if (rst) begin + for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop + rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && + //(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][6+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1; + end +//***************************************************************************** +// One I/O Bank Interface +//***************************************************************************** + end else begin // One I/O Bank Interface + + // Read data offset value for all DQS in Bank0 + always @(posedge clk) begin + if (rst) begin + for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop + rd_byte_data_offset[l] <= #TCQ nCL + nAL - 2; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL + LATENCY_FACTOR - 1))) + rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL - 2; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && + //(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL + LATENCY_FACTOR)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r] + <= #TCQ rd_byte_data_offset[rnk_cnt_r] + 1; + end + + // Reset read data offset calibration in all DQS Phaser_INs + // in a Bank after the read data offset value for a rank is determined + // or if within a Bank DQSFOUND is not asserted for all DQSs + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[0]) || + (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + end + + //***************************************************************************** + // Retry counter to track number of DQSFOUND retries + //***************************************************************************** + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[0+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && + ~pi_dqs_found_all_bank[0]) + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; + else + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; + end + + + // Error generation in case pi_dqs_found_all_bank + // is not asserted even with 3 dqfound retries + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[0] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_dqs_found_err_r[0] <= #TCQ 1'b1; + end + + end + endgenerate + + always @(posedge clk) begin + if (rst) + pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}}; + else if (rst_dqs_find) + pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}}; + else + pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r; + end + + + + // Final read data offset value to be used during write calibration and + // normal operation + generate + genvar i; + genvar j; + for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop + reg [5:0] final_do_cand [RANKS-1:0]; + // combinatorially select the candidate offset for the bank + // indexed by final_do_index + if (HIGHEST_BANK == 3) begin + always @(*) begin + case (final_do_index[i]) + 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; + 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; + 3'b010: final_do_cand[i] = final_data_offset[i][17:12]; + default: final_do_cand[i] = 'd0; + endcase + end + end else if (HIGHEST_BANK == 2) begin + always @(*) begin + case (final_do_index[i]) + 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; + 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; + 3'b010: final_do_cand[i] = 'd0; + default: final_do_cand[i] = 'd0; + endcase + end + end else begin + always @(*) begin + case (final_do_index[i]) + 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; + 3'b001: final_do_cand[i] = 'd0; + 3'b010: final_do_cand[i] = 'd0; + default: final_do_cand[i] = 'd0; + endcase + end + end + + always @(posedge clk) begin + if (rst) + final_do_max[i] <= #TCQ 0; + else begin + final_do_max[i] <= #TCQ final_do_max[i]; // default + case (final_do_index[i]) + 3'b000: if ( | DATA_PRESENT[3:0]) + if (final_do_max[i] < final_do_cand[i]) + if (CWL_M % 2) // odd latency CAS slot 1 + final_do_max[i] <= #TCQ final_do_cand[i] - 1; + else + final_do_max[i] <= #TCQ final_do_cand[i]; + 3'b001: if ( | DATA_PRESENT[7:4]) + if (final_do_max[i] < final_do_cand[i]) + if (CWL_M % 2) // odd latency CAS slot 1 + final_do_max[i] <= #TCQ final_do_cand[i] - 1; + else + final_do_max[i] <= #TCQ final_do_cand[i]; + 3'b010: if ( | DATA_PRESENT[11:8]) + if (final_do_max[i] < final_do_cand[i]) + if (CWL_M % 2) // odd latency CAS slot 1 + final_do_max[i] <= #TCQ final_do_cand[i] - 1; + else + final_do_max[i] <= #TCQ final_do_cand[i]; + default: + final_do_max[i] <= #TCQ final_do_max[i]; + endcase + end + end + + always @(posedge clk) + if (rst) begin + final_do_index[i] <= #TCQ 0; + end + else begin + final_do_index[i] <= #TCQ final_do_index[i] + 1; + end + + for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop + + always @(posedge clk) begin + if (rst) begin + final_data_offset[i][6*j+:6] <= #TCQ 'b0; + end + else begin + //if (dqsfound_retry[j]) + // final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; + //else + if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin + if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane + final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; + if (CWL_M % 2) // odd latency CAS slot 1 + final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1; + else // even latency CAS slot 0 + final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; + end + end + else if (init_dqsfound_done_r5 ) begin + if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes + final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i]; + final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i]; + end + end + end + end + end + end + endgenerate + + + // Error generation in case pi_found_dqs signal from Phaser_IN + // is not asserted when a common rddata_offset value is used + + always @(posedge clk) begin + pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r; + end + + + +endmodule + + + + + + diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_init.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_init.v new file mode 100644 index 0000000..70bc94c --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_init.v @@ -0,0 +1,5497 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_init.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// Memory initialization and overall master state control during +// initialization and calibration. Specifically, the following functions +// are performed: +// 1. Memory initialization (initial AR, mode register programming, etc.) +// 2. Initiating write leveling +// 3. Generate training pattern writes for read leveling. Generate +// memory readback for read leveling. +// This module has an interface for providing control/address and write +// data to the PHY Control Block during initialization/calibration. +// Once initialization and calibration are complete, control is passed to the MC. +// +//Reference: +//Revision History: +// +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_init.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ +**$Date: 2011/06/02 08:35:09 $ +**$Author: mishra $ +**$Revision: 1.1 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_init.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + + +module mig_7series_v4_0_ddr_phy_init # + ( + parameter tCK = 1500, // DDRx SDRAM clock period + parameter TCQ = 100, + parameter nCK_PER_CLK = 4, // # of memory clocks per CLK + parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps) + parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA + // 1 - ODT output from FPGA + parameter DDR3_VDD_OP_VOLT = "150", // Voltage mode used for DDR3 + // 150 - 1.50 V + // 135 - 1.35 V + // 125 - 1.25 V + parameter VREF = "EXTERNAL", // Internal or external Vref + parameter PRBS_WIDTH = 8, // PRBS sequence = 2^PRBS_WIDTH + parameter BANK_WIDTH = 2, + parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank + parameter COL_WIDTH = 10, + parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for + // component I/F with CS_WIDTH=1, + // nCS_PER_RANK=# of components + parameter DQ_WIDTH = 64, + parameter DQS_WIDTH = 8, + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter ROW_WIDTH = 14, + parameter CS_WIDTH = 1, + parameter RANKS = 1, // # of memory ranks in the interface + parameter CKE_WIDTH = 1, // # of cke outputs + parameter DRAM_TYPE = "DDR3", + parameter REG_CTRL = "ON", + parameter ADDR_CMD_MODE= "1T", + + // calibration Address + parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address + parameter CALIB_COL_ADD = 12'h000, // Calibration column address + parameter CALIB_BA_ADD = 3'h0, // Calibration bank address + + // DRAM mode settings + parameter AL = "0", // Additive Latency option + parameter BURST_MODE = "8", // Burst length + parameter BURST_TYPE = "SEQ", // Burst type +// parameter nAL = 0, // Additive latency (in clk cyc) + parameter nCL = 5, // Read CAS latency (in clk cyc) + parameter nCWL = 5, // Write CAS latency (in clk cyc) + parameter tRFC = 110000, // Refresh-to-command delay (in ps) + parameter REFRESH_TIMER = 1553, // Refresh interval in fabrci cycles between 8 posted refreshes + parameter REFRESH_TIMER_WIDTH = 8, + parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option + parameter RTT_NOM = "60", // Nominal ODT termination value + parameter RTT_WR = "60", // Write ODT termination value + parameter WRLVL = "ON", // Enable write leveling +// parameter PHASE_DETECT = "ON", // Enable read phase detector + parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 + parameter nSLOTS = 1, // Number of DIMM SLOTs in the system + parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT" + parameter SIM_CAL_OPTION = "NONE", // "NONE", "FAST_CAL", "SKIP_CAL" + parameter CKE_ODT_AUX = "FALSE", + parameter PRE_REV3ES = "OFF", // Enable TG error detection during calibration + parameter TEST_AL = "0", // Internal use for ICM verification + parameter FIXED_VICTIM = "TRUE", + parameter BYPASS_COMPLEX_OCAL = "FALSE", + parameter SKIP_CALIB = "FALSE" + ) + ( + input clk, + input rst, + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o, + input delay_incdec_done, + input ck_addr_cmd_delay_done, + input pi_phase_locked_all, + input pi_dqs_found_done, + input dqsfound_retry, + input dqs_found_prech_req, + output reg pi_phaselock_start, + output pi_phase_locked_err, + output pi_calib_done, + input phy_if_empty, + // Read/write calibration interface + input wrlvl_done, + input wrlvl_rank_done, + input wrlvl_byte_done, + input wrlvl_byte_redo, + input wrlvl_final, + output reg wrlvl_final_if_rst, + input oclkdelay_calib_done, + input oclk_prech_req, + input oclk_calib_resume, + input lim_done, + input lim_wr_req, + output reg oclkdelay_calib_start, + //complex oclkdelay calibration + input complex_oclkdelay_calib_done, + input complex_oclk_prech_req, + input complex_oclk_calib_resume, + output reg complex_oclkdelay_calib_start, + input [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt, // same as oclkdelay_calib_cnt + output reg complex_ocal_num_samples_inc, + input complex_ocal_num_samples_done_r, + input [2:0] complex_ocal_rd_victim_sel, + output reg complex_ocal_reset_rd_addr, + input complex_ocal_ref_req, + output reg complex_ocal_ref_done, + + input done_dqs_tap_inc, + input [5:0] rd_data_offset_0, + input [5:0] rd_data_offset_1, + input [5:0] rd_data_offset_2, + input [6*RANKS-1:0] rd_data_offset_ranks_0, + input [6*RANKS-1:0] rd_data_offset_ranks_1, + input [6*RANKS-1:0] rd_data_offset_ranks_2, + input pi_dqs_found_rank_done, + input wrcal_done, + input wrcal_prech_req, + input wrcal_read_req, + input wrcal_act_req, + input temp_wrcal_done, + input [7:0] slot_0_present, + input [7:0] slot_1_present, + output reg wl_sm_start, + output reg wr_lvl_start, + output reg wrcal_start, + output reg wrcal_rd_wait, + output reg wrcal_sanity_chk, + output reg tg_timer_done, + output reg no_rst_tg_mc, + input rdlvl_stg1_done, + input rdlvl_stg1_rank_done, + output reg rdlvl_stg1_start, + output reg pi_dqs_found_start, + output reg detect_pi_found_dqs, + // rdlvl stage 1 precharge requested after each DQS + input rdlvl_prech_req, + input rdlvl_last_byte_done, + input wrcal_resume, + input wrcal_sanity_chk_done, + // MPR read leveling + input mpr_rdlvl_done, + input mpr_rnk_done, + input mpr_last_byte_done, + output reg mpr_rdlvl_start, + output reg mpr_end_if_reset, + + // PRBS Read Leveling + input prbs_rdlvl_done, + input prbs_last_byte_done, + input prbs_rdlvl_prech_req, + input complex_victim_inc, + input [2:0] rd_victim_sel, + input [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt, + output reg [2:0] victim_sel, + output reg [DQS_CNT_WIDTH:0]victim_byte_cnt, + output reg prbs_rdlvl_start, + output reg prbs_gen_clk_en, + output reg prbs_gen_oclk_clk_en, + output reg complex_sample_cnt_inc, + output reg complex_sample_cnt_inc_ocal, + output reg complex_wr_done, + + // Signals shared btw multiple calibration stages + output reg prech_done, + // Data select / status + output reg init_calib_complete, + // Signal to mask memory model error for Invalid latching edge + output reg calib_writes, + // PHY address/control + // 2 commands to PHY Control Block per div 2 clock in 2:1 mode + // 4 commands to PHY Control Block per div 4 clock in 4:1 mode + output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address, + output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank, + output reg [nCK_PER_CLK-1:0] phy_ras_n, + output reg [nCK_PER_CLK-1:0] phy_cas_n, + output reg [nCK_PER_CLK-1:0] phy_we_n, + output reg phy_reset_n, + output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n, + + // Hard PHY Interface signals + input phy_ctl_ready, + input phy_ctl_full, + input phy_cmd_full, + input phy_data_full, + output reg calib_ctl_wren, + output reg calib_cmd_wren, + output reg [1:0] calib_seq, + output reg write_calib, + output reg read_calib, + // PHY_Ctl_Wd + output reg [2:0] calib_cmd, + // calib_aux_out used for CKE and ODT + output reg [3:0] calib_aux_out, + output reg [1:0] calib_odt , + output reg [nCK_PER_CLK-1:0] calib_cke , + output [1:0] calib_rank_cnt, + output reg [1:0] calib_cas_slot, + output reg [5:0] calib_data_offset_0, + output reg [5:0] calib_data_offset_1, + output reg [5:0] calib_data_offset_2, + // PHY OUT_FIFO + output reg calib_wrdata_en, + output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata, + // PHY Read + output phy_rddata_en, + output phy_rddata_valid, + output [255:0] dbg_phy_init, + input reset_rd_addr, + //OCAL centering calibration + input oclkdelay_center_calib_start, + input oclk_center_write_resume, + input oclkdelay_center_calib_done, + input rdlvl_pi_incdec, //rdlvl pi dec + input complex_pi_incdec_done, + input num_samples_done_r, + input complex_init_pi_dec_done, + output reg complex_act_start, + output reg calib_tap_inc_start, + output reg calib_tap_end_if_reset, + input calib_tap_inc_done + ); + +//***************************************************************************** +// Assertions to be added +//***************************************************************************** +// The phy_ctl_full signal must never be asserted in synchronous mode of +// operation either 4:1 or 2:1 +// +// The RANKS parameter must never be set to '0' by the user +// valid values: 1 to 4 +// +//***************************************************************************** + + //*************************************************************************** + + // Number of Read level stage 1 writes limited to a SDRAM row + // The address of Read Level stage 1 reads must also be limited + // to a single SDRAM row + // (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128 + localparam NUM_STG1_WR_RD = (BURST_MODE == "8") ? 4 : + (BURST_MODE == "4") ? 8 : 4; + + + localparam ADDR_INC = (BURST_MODE == "8") ? 8 : + (BURST_MODE == "4") ? 4 : 8; + + // In a 2 slot dual rank per system RTT_NOM values + // for Rank2 and Rank3 default to 40 ohms + localparam RTT_NOM2 = "40"; + localparam RTT_NOM3 = "40"; + + localparam RTT_NOM_int = (USE_ODT_PORT == 1) ? RTT_NOM : RTT_WR; + + // Specifically for use with half-frequency controller (nCK_PER_CLK=2) + // = 1 if burst length = 4, = 0 if burst length = 8. Determines how + // often row command needs to be issued during read-leveling + // For DDR3 the burst length is fixed during calibration + localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 : + (BURST_MODE == "8") ? 1'b0 : + ((BURST_MODE == "4") ? 1'b1 : 1'b0); + + + + + //*************************************************************************** + // Counter values used to determine bus timing + // NOTE on all counter terminal counts - these can/should be one less than + // the actual delay to take into account extra clock cycle delay in + // generating the corresponding "done" signal + //*************************************************************************** + + localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK; + + // Calculate initial delay required in number of CLK clock cycles + // to delay initially. The counter is clocked by [CLK/1024] - which + // is approximately division by 1000 - note that the formulas below will + // result in more than the minimum wait time because of this approximation. + // NOTE: For DDR3 JEDEC specifies to delay reset + // by 200us, and CKE by an additional 500us after power-up + // For DDR2 CKE is delayed by 200us after power up. + localparam DDR3_RESET_DELAY_NS = 200000; + localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS; + localparam DDR2_CKE_DELAY_NS = 200000; + localparam PWRON_RESET_DELAY_CNT = + ((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD); + localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ? + (((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) : + (((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)); + // FOR DDR2 -1 taken out. With -1 not getting 200us. The equation + // needs to be reworked. + localparam DDR2_INIT_PRE_DELAY_PS = 400000; + localparam DDR2_INIT_PRE_CNT = + ((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1; + + // Calculate tXPR time: reset from CKE HIGH to valid command after power-up + // tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock + // cycles because this counter actually starts up before CKE is asserted + // to memory. + localparam TXPR_DELAY_CNT = + (5*CLK_MEM_PERIOD > tRFC+10000) ? + (((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 : + (((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11; + + // tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV + localparam TDLLK_TZQINIT_DELAY_CNT = 255; + + // TWR values in ns. Both DDR2 and DDR3 have the same value. + // 15000ns/tCK + localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ? + (15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD; + + // time to wait between consecutive commands in PHY_INIT - this is a + // generic number, and must be large enough to account for worst case + // timing parameter (tRFC - refresh-to-active) across all memory speed + // grades and operating frequencies. Expressed in clk + // (Divided by 4 or Divided by 2) clock cycles. + localparam CNTNEXT_CMD = 7'b1111111; + + // Counter values to keep track of which MR register to load during init + // Set value of INIT_CNT_MR_DONE to equal value of counter for last mode + // register configured during initialization. + // NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init + localparam INIT_CNT_MR2 = 2'b00; + localparam INIT_CNT_MR3 = 2'b01; + localparam INIT_CNT_MR1 = 2'b10; + localparam INIT_CNT_MR0 = 2'b11; + localparam INIT_CNT_MR_DONE = 2'b11; + + // Register chip programmable values for DDR3 + // The register chip for the registered DIMM needs to be programmed + // before the initialization of the registered DIMM. + // Address for the control word is in : DBA2, DA2, DA1, DA0 + // Data for the control word is in: DBA1 DBA0, DA4, DA3 + // The values will be stored in the local param in the following format + // {DBA[2:0], DA[4:0]} + + // RC0 is global features control word. Address == 000 + + localparam REG_RC0 = 8'b00000000; + + // RC1 Clock driver enable control word. Enables or disables the four + // output clocks in the register chip. For single rank and dual rank + // two clocks will be enabled and for quad rank all the four clocks + // will be enabled. Address == 000. Data = 0110 for single and dual rank. + // = 0000 for quad rank + localparam REG_RC1 = 8'b00000001; + + // RC2 timing control word. Set in 1T timing mode + // Address = 010. Data = 0000 + localparam REG_RC2 = 8'b00000010; + + // RC3 timing control word. Setting the data based on number of RANKS (inturn the number of loads) + // This setting is specific to RDIMMs from Micron Technology + localparam REG_RC3 = (RANKS >= 2) ? 8'b00101011 : 8'b00000011; + + // RC4 timing control work. Setting the data based on number of RANKS (inturn the number of loads) + // This setting is specific to RDIMMs from Micron Technology + localparam REG_RC4 = (RANKS >= 2) ? 8'b00101100 : 8'b00000100; + + // RC5 timing control work. Setting the data based on number of RANKS (inturn the number of loads) + // This setting is specific to RDIMMs from Micron Technology + localparam REG_RC5 = (RANKS >= 2) ? 8'b00101101 : 8'b00000101; + + // RC10 timing control work. Setting the data to 0000 + localparam [3:0] FREQUENCY_ENCODING = (tCK >= 1072 && tCK < 1250) ? 4'b0100 : + (tCK >= 1250 && tCK < 1500) ? 4'b0011 : + (tCK >= 1500 && tCK < 1875) ? 4'b0010 : + (tCK >= 1875 && tCK < 2500) ? 4'b0001 : 4'b0000; + + localparam REG_RC10 = {1'b1,FREQUENCY_ENCODING,3'b010}; + + localparam VREF_ENCODING = (VREF == "INTERNAL") ? 1'b1 : 1'b0; + localparam [3:0] DDR3_VOLTAGE_ENCODING = (DDR3_VDD_OP_VOLT == "125") ? {1'b0,VREF_ENCODING,2'b10} : + (DDR3_VDD_OP_VOLT == "135") ? {1'b0,VREF_ENCODING,2'b01} : + {1'b0,VREF_ENCODING,2'b00} ; + + localparam REG_RC11 = {1'b1,DDR3_VOLTAGE_ENCODING,3'b011}; + + // For non-zero AL values + localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; + + // Adding the register dimm latency to write latency + localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; + + // Count value to generate pi_phase_locked_err signal + localparam PHASELOCKED_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 16383 : 1000; + + // Timeout interval for detecting error with Traffic Generator + localparam [13:0] TG_TIMER_TIMEOUT + = (SIM_CAL_OPTION == "NONE") ? 14'h3FFF : 14'h0001; + + //bit num per DQS + localparam DQ_PER_DQS = DQ_WIDTH/DQS_WIDTH; + + //COMPLEX_ROW_CNT_BYTE + localparam COMPLEX_ROW_CNT_BYTE = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS*2: 2; + localparam COMPLEX_RD = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS : 1; + + // Master state machine encoding + localparam INIT_IDLE = 7'b0000000; //0 + localparam INIT_WAIT_CKE_EXIT = 7'b0000001; //1 + localparam INIT_LOAD_MR = 7'b0000010; //2 + localparam INIT_LOAD_MR_WAIT = 7'b0000011; //3 + localparam INIT_ZQCL = 7'b0000100; //4 + localparam INIT_WAIT_DLLK_ZQINIT = 7'b0000101; //5 + localparam INIT_WRLVL_START = 7'b0000110; //6 + localparam INIT_WRLVL_WAIT = 7'b0000111; //7 + localparam INIT_WRLVL_LOAD_MR = 7'b0001000; //8 + localparam INIT_WRLVL_LOAD_MR_WAIT = 7'b0001001; //9 + localparam INIT_WRLVL_LOAD_MR2 = 7'b0001010; //A + localparam INIT_WRLVL_LOAD_MR2_WAIT = 7'b0001011; //B + localparam INIT_RDLVL_ACT = 7'b0001100; //C + localparam INIT_RDLVL_ACT_WAIT = 7'b0001101; //D + localparam INIT_RDLVL_STG1_WRITE = 7'b0001110; //E + localparam INIT_RDLVL_STG1_WRITE_READ = 7'b0001111; //F + localparam INIT_RDLVL_STG1_READ = 7'b0010000; //10 + localparam INIT_RDLVL_STG2_READ = 7'b0010001; //11 + localparam INIT_RDLVL_STG2_READ_WAIT = 7'b0010010; //12 + localparam INIT_PRECHARGE_PREWAIT = 7'b0010011; //13 + localparam INIT_PRECHARGE = 7'b0010100; //14 + localparam INIT_PRECHARGE_WAIT = 7'b0010101; //15 + localparam INIT_DONE = 7'b0010110; //16 + localparam INIT_DDR2_PRECHARGE = 7'b0010111; //17 + localparam INIT_DDR2_PRECHARGE_WAIT = 7'b0011000; //18 + localparam INIT_REFRESH = 7'b0011001; //19 + localparam INIT_REFRESH_WAIT = 7'b0011010; //1A + localparam INIT_REG_WRITE = 7'b0011011; //1B + localparam INIT_REG_WRITE_WAIT = 7'b0011100; //1C + localparam INIT_DDR2_MULTI_RANK = 7'b0011101; //1D + localparam INIT_DDR2_MULTI_RANK_WAIT = 7'b0011110; //1E + localparam INIT_WRCAL_ACT = 7'b0011111; //1F + localparam INIT_WRCAL_ACT_WAIT = 7'b0100000; //20 + localparam INIT_WRCAL_WRITE = 7'b0100001; //21 + localparam INIT_WRCAL_WRITE_READ = 7'b0100010; //22 + localparam INIT_WRCAL_READ = 7'b0100011; //23 + localparam INIT_WRCAL_READ_WAIT = 7'b0100100; //24 + localparam INIT_WRCAL_MULT_READS = 7'b0100101; //25 + localparam INIT_PI_PHASELOCK_READS = 7'b0100110; //26 + localparam INIT_MPR_RDEN = 7'b0100111; //27 + localparam INIT_MPR_WAIT = 7'b0101000; //28 + localparam INIT_MPR_READ = 7'b0101001; //29 + localparam INIT_MPR_DISABLE_PREWAIT = 7'b0101010; //2A + localparam INIT_MPR_DISABLE = 7'b0101011; //2B + localparam INIT_MPR_DISABLE_WAIT = 7'b0101100; //2C + localparam INIT_OCLKDELAY_ACT = 7'b0101101; //2D + localparam INIT_OCLKDELAY_ACT_WAIT = 7'b0101110; //2E + localparam INIT_OCLKDELAY_WRITE = 7'b0101111; //2F + localparam INIT_OCLKDELAY_WRITE_WAIT = 7'b0110000; //30 + localparam INIT_OCLKDELAY_READ = 7'b0110001; //31 + localparam INIT_OCLKDELAY_READ_WAIT = 7'b0110010; //32 + localparam INIT_REFRESH_RNK2_WAIT = 7'b0110011; //33 + localparam INIT_RDLVL_COMPLEX_PRECHARGE = 7'b0110100; //34 + localparam INIT_RDLVL_COMPLEX_PRECHARGE_WAIT = 7'b0110101; //35 + localparam INIT_RDLVL_COMPLEX_ACT = 7'b0110110; //36 + localparam INIT_RDLVL_COMPLEX_ACT_WAIT = 7'b0110111; //37 + localparam INIT_RDLVL_COMPLEX_READ = 7'b0111000; //38 + localparam INIT_RDLVL_COMPLEX_READ_WAIT = 7'b0111001; //39 + localparam INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT = 7'b0111010; //3A + localparam INIT_OCAL_COMPLEX_ACT = 7'b0111011; //3B + localparam INIT_OCAL_COMPLEX_ACT_WAIT = 7'b0111100; //3C + localparam INIT_OCAL_COMPLEX_WRITE_WAIT = 7'b0111101; //3D + localparam INIT_OCAL_COMPLEX_RESUME_WAIT = 7'b0111110; //3E + localparam INIT_OCAL_CENTER_ACT = 7'b0111111; //3F + localparam INIT_OCAL_CENTER_WRITE = 7'b1000000; //40 + localparam INIT_OCAL_CENTER_WRITE_WAIT = 7'b1000001; //41 + localparam INIT_OCAL_CENTER_ACT_WAIT = 7'b1000010; //42 + localparam INIT_RDLVL_COMPLEX_PI_WAIT = 7'b1000011; //43 + localparam INIT_SKIP_CALIB_WAIT = 7'b1000100; //44 + + integer i, j, k, l, m, n, p, q; + + reg pi_dqs_found_all_r; + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r1; + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r2; + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r3; + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r4; + reg pi_calib_rank_done_r; + reg [13:0] pi_phaselock_timer; + reg stg1_wr_done; + reg rnk_ref_cnt; + reg pi_dqs_found_done_r1; + reg pi_dqs_found_rank_done_r; + reg read_calib_int; + reg read_calib_r; + reg pi_calib_done_r; + reg pi_calib_done_r1; + reg burst_addr_r; + reg [1:0] chip_cnt_r; + reg [6:0] cnt_cmd_r; + reg cnt_cmd_done_r; + reg cnt_cmd_done_m7_r; + reg [7:0] cnt_dllk_zqinit_r; + reg cnt_dllk_zqinit_done_r; + reg cnt_init_af_done_r; + reg [1:0] cnt_init_af_r; + reg [1:0] cnt_init_data_r; + reg [1:0] cnt_init_mr_r; + reg cnt_init_mr_done_r; + reg cnt_init_pre_wait_done_r; + reg [7:0] cnt_init_pre_wait_r; + reg [9:0] cnt_pwron_ce_r; + reg cnt_pwron_cke_done_r; + reg cnt_pwron_cke_done_r1; + reg [8:0] cnt_pwron_r; + reg cnt_pwron_reset_done_r; + reg cnt_txpr_done_r; + reg [7:0] cnt_txpr_r; + reg ddr2_pre_flag_r; + reg ddr2_refresh_flag_r; + reg ddr3_lm_done_r; + reg [4:0] enable_wrlvl_cnt; + reg init_complete_r; + reg init_complete_r1; + reg init_complete_r2; +(* keep = "true" *) reg init_complete_r_timing; +(* keep = "true" *) reg init_complete_r1_timing; + reg [6:0] init_next_state; + reg [6:0] init_state_r; + reg [6:0] init_state_r1; + wire [15:0] load_mr0; + wire [15:0] load_mr1; + wire [15:0] load_mr2; + wire [15:0] load_mr3; + reg mem_init_done_r; + reg [1:0] mr2_r [0:3]; + reg [2:0] mr1_r [0:3]; + reg new_burst_r; + reg [15:0] wrcal_start_dly_r; + wire wrcal_start_pre; + reg wrcal_resume_r; + // Only one ODT signal per rank in PHY Control Block + reg [nCK_PER_CLK-1:0] phy_tmp_odt_r; + reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1; + + reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r; + reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n; + wire prech_done_pre; + reg [15:0] prech_done_dly_r; + reg prech_pending_r; + reg prech_req_posedge_r; + reg prech_req_r; + reg pwron_ce_r; + reg first_rdlvl_pat_r; + reg first_wrcal_pat_r; + reg phy_wrdata_en; + reg phy_wrdata_en_r1; + reg [1:0] wrdata_pat_cnt; + reg [1:0] wrcal_pat_cnt; + reg [ROW_WIDTH-1:0] address_w; + reg [BANK_WIDTH-1:0] bank_w; + reg rdlvl_stg1_done_r1; + reg rdlvl_stg1_start_int; + reg [15:0] rdlvl_start_dly0_r; + reg rdlvl_start_pre; + reg rdlvl_last_byte_done_r; + wire rdlvl_rd; + wire rdlvl_wr; + reg rdlvl_wr_r; + wire rdlvl_wr_rd; + reg [3:0] reg_ctrl_cnt_r; + reg [1:0] tmp_mr2_r [0:3]; + reg [2:0] tmp_mr1_r [0:3]; + reg wrlvl_done_r; + reg wrlvl_done_r1; + reg wrlvl_rank_done_r1; + reg wrlvl_rank_done_r2; + reg wrlvl_rank_done_r3; + reg wrlvl_rank_done_r4; + reg wrlvl_rank_done_r5; + reg wrlvl_rank_done_r6; + reg wrlvl_rank_done_r7; + reg [2:0] wrlvl_rank_cntr; + reg wrlvl_odt_ctl; + reg wrlvl_odt; + reg wrlvl_active; + reg wrlvl_active_r1; + reg [2:0] num_reads; + reg temp_wrcal_done_r; + reg temp_lmr_done; + reg extend_cal_pat; + reg [13:0] tg_timer; + reg tg_timer_go; + reg cnt_wrcal_rd; + reg [3:0] cnt_wait; + reg [7:0] wrcal_reads; + reg [8:0] stg1_wr_rd_cnt; + reg phy_data_full_r; + reg wr_level_dqs_asrt; + reg wr_level_dqs_asrt_r1; + reg [1:0] dqs_asrt_cnt; + + + reg [3:0] num_refresh; + wire oclkdelay_calib_start_pre; + reg [15:0] oclkdelay_start_dly_r; + reg [3:0] oclk_wr_cnt; + reg [3:0] wrcal_wr_cnt; + reg wrlvl_final_r; + + + reg prbs_rdlvl_done_r1; + reg prbs_rdlvl_done_r2; + reg prbs_rdlvl_done_r3; + reg prbs_last_byte_done_r; + reg phy_if_empty_r; + reg prbs_pat_resume_int; + reg complex_row0_wr_done; + reg complex_row1_wr_done; + reg complex_row0_rd_done; + reg complex_row1_rd_done; + reg complex_row0_rd_done_r1; + reg [3:0] complex_wait_cnt; + reg [3:0] complex_num_reads; + reg [3:0] complex_num_reads_dec; + reg [ROW_WIDTH-1:0] complex_address; + reg wr_victim_inc; + reg [2:0] wr_victim_sel; + reg [7:0] complex_row_cnt; + + reg complex_sample_cnt_inc_r1; + reg complex_sample_cnt_inc_r2; + reg complex_odt_ext; + reg complex_ocal_odt_ext; + + reg wrcal_final_chk; + wire prech_req; + + reg reset_rd_addr_r1; + reg complex_rdlvl_int_ref_req; + reg ext_int_ref_req; + + //complex OCLK delay calibration + reg [7:0] complex_row_cnt_ocal; + reg [4:0] complex_num_writes; + reg [4:0] complex_num_writes_dec; + reg complex_oclkdelay_calib_start_int; + reg complex_oclkdelay_calib_start_r1; + reg complex_oclkdelay_calib_start_r2; + reg complex_oclkdelay_calib_done_r1; + // reg [DQS_CNT_WIDTH:0] wr_byte_cnt_ocal; + reg [2:0] wr_victim_sel_ocal; + + reg complex_row1_rd_done_r1; //time for switch to write + reg [2:0] complex_row1_rd_cnt; //row1 read number for the byte (8 (16 rows) row1) + reg complex_byte_rd_done; //read for the byte is done + reg complex_byte_rd_done_r1; + // reg complex_row_change; //every 16 rows of read, it is set to "0" for write + reg ocal_num_samples_inc; //1 read/write is done + reg complex_ocal_wr_start; //indicate complex ocal write is started. used for prbs rd addr gen + + reg prbs_rdlvl_done_pulse; //rising edge for prbs_rdlvl_done. used for pipelining + reg prech_done_r1, prech_done_r2, prech_done_r3; + reg mask_lim_done; + reg complex_mask_lim_done; + reg oclkdelay_calib_start_int; + reg [REFRESH_TIMER_WIDTH-1:0] oclkdelay_ref_cnt; + reg oclkdelay_int_ref_req; + reg [3:0] ocal_act_wait_cnt; + reg oclk_calib_resume_level; + reg ocal_last_byte_done; + wire mmcm_wr; //MMCM centering write. no CS will be set + + wire exit_ocal_complex_resume_wait = + init_state_r == INIT_OCAL_COMPLEX_RESUME_WAIT && complex_oclk_calib_resume; + + reg calib_tap_inc_done_r1; + + + + //*************************************************************************** + // Debug + //*************************************************************************** + + //synthesis translate_off + always @(posedge mem_init_done_r) begin + if (!rst) + $display ("PHY_INIT: Memory Initialization completed at %t", $time); + end + + always @(posedge wrlvl_done) begin + if (!rst && (WRLVL == "ON")) + $display ("PHY_INIT: Write Leveling completed at %t", $time); + end + + always @(posedge rdlvl_stg1_done) begin + if (!rst) + $display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time); + end + + always @(posedge mpr_rdlvl_done) begin + if (!rst) + $display ("PHY_INIT: MPR Read Leveling completed at %t", $time); + end + + always @(posedge oclkdelay_calib_done) begin + if (!rst) + $display ("PHY_INIT: OCLKDELAY calibration completed at %t", $time); + end + + always @(posedge pi_calib_done_r1) begin + if (!rst) + $display ("PHY_INIT: Phaser_In Phase Locked at %t", $time); + end + + always @(posedge pi_dqs_found_done) begin + if (!rst) + $display ("PHY_INIT: Phaser_In DQSFOUND completed at %t", $time); + end + + always @(posedge wrcal_done) begin + if (!rst && (WRLVL == "ON")) + $display ("PHY_INIT: Write Calibration completed at %t", $time); + end + + always@(posedge prbs_rdlvl_done)begin + if(!rst) + $display("PHY_INIT : PRBS/PER_BIT calibration completed at %t",$time); + end + + + always@(posedge complex_oclkdelay_calib_done)begin + if(!rst) + $display("PHY_INIT : COMPLEX OCLKDELAY calibration completed at %t",$time); + end + always@(posedge oclkdelay_center_calib_done)begin + if(!rst) + $display("PHY_INIT : OCLKDELAY CENTER CALIB calibration completed at %t",$time); + end + + //synthesis translate_on + + assign dbg_phy_init[5:0] = init_state_r; + assign dbg_phy_init[6+:8] = complex_row_cnt; + assign dbg_phy_init[14+:3] = victim_sel; + assign dbg_phy_init[17+:4] = victim_byte_cnt; + assign dbg_phy_init[21+:9] = stg1_wr_rd_cnt[8:0]; + assign dbg_phy_init[30+:15] = complex_address; + assign dbg_phy_init[(30+15)+:15] = phy_address[14:0]; + assign dbg_phy_init[60] =prbs_rdlvl_prech_req ; + assign dbg_phy_init[61] =prech_req_posedge_r ; + + + //*************************************************************************** + // DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage + //*************************************************************************** + +// assign pi_phaselock_calib_cnt = dqs_cnt_r; + + assign pi_calib_done = pi_calib_done_r1; + + //prevent PI incdec during complex read + always @ (posedge clk) + complex_act_start <= #TCQ (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT); + + //detect rising edge of prbs_rdlvl_done to reset all control sighals + always @ (posedge clk) begin + prbs_rdlvl_done_pulse <= #TCQ prbs_rdlvl_done & ~prbs_rdlvl_done_r1; + end + + always @(posedge clk) begin + if (rst) + wrcal_final_chk <= #TCQ 1'b0; + else if ((init_next_state == INIT_WRCAL_ACT) && (wrcal_done || (SKIP_CALIB == "TRUE")) && + (DRAM_TYPE == "DDR3")) + wrcal_final_chk <= #TCQ 1'b1; + end + + always @(posedge clk) begin + rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done; + prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done; + prbs_rdlvl_done_r2 <= #TCQ prbs_rdlvl_done_r1; + prbs_rdlvl_done_r3 <= #TCQ prbs_rdlvl_done_r2; + wrcal_resume_r <= #TCQ wrcal_resume; + wrcal_sanity_chk <= #TCQ wrcal_final_chk; + end + + always @(posedge clk) begin + if (rst) + mpr_end_if_reset <= #TCQ 1'b0; + else if (mpr_last_byte_done && (num_refresh != 'd0)) + mpr_end_if_reset <= #TCQ 1'b1; + else + mpr_end_if_reset <= #TCQ 1'b0; + end + + // Siganl to mask memory model error for Invalid latching edge + + always @(posedge clk) + if (rst) + calib_writes <= #TCQ 1'b0; + else if ((init_state_r == INIT_OCLKDELAY_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_WRCAL_WRITE_READ)) + calib_writes <= #TCQ 1'b1; + else + calib_writes <= #TCQ 1'b0; + + always @(posedge clk) + if (rst) + wrcal_rd_wait <= #TCQ 1'b0; + else if (init_state_r == INIT_WRCAL_READ_WAIT) + wrcal_rd_wait <= #TCQ 1'b1; + else + wrcal_rd_wait <= #TCQ 1'b0; + + //*************************************************************************** + // Signal PHY completion when calibration is finished + // Signal assertion is delayed by four clock cycles to account for the + // multi cycle path constraint to (phy_init_data_sel) signal. + //*************************************************************************** + + always @(posedge clk) + if (rst) begin + init_complete_r <= #TCQ 1'b0; + init_complete_r_timing <= #TCQ 1'b0; + init_complete_r1 <= #TCQ 1'b0; + init_complete_r1_timing <= #TCQ 1'b0; + init_complete_r2 <= #TCQ 1'b0; + init_calib_complete <= #TCQ 1'b0; + end else begin + if (init_state_r == INIT_DONE) begin + init_complete_r <= #TCQ 1'b1; + init_complete_r_timing <= #TCQ 1'b1; + end + init_complete_r1 <= #TCQ init_complete_r; + init_complete_r1_timing <= #TCQ init_complete_r_timing; + init_complete_r2 <= #TCQ init_complete_r1; + init_calib_complete <= #TCQ init_complete_r2; + end + + always @ (posedge clk) + if (rst) + complex_oclkdelay_calib_done_r1 <= #TCQ 1'b0; + else + complex_oclkdelay_calib_done_r1 <= #TCQ complex_oclkdelay_calib_done; + + //reset read address for starting complex ocaldealy calib + always @ (posedge clk) begin + complex_ocal_reset_rd_addr <= #TCQ ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd9)) || (prbs_last_byte_done && ~prbs_last_byte_done_r); + + end + + //first write for complex oclkdealy calib + always @ (posedge clk) begin + if (rst) + complex_ocal_wr_start <= #TCQ 'b0; + else + complex_ocal_wr_start <= #TCQ complex_ocal_reset_rd_addr? 1'b1 : complex_ocal_wr_start; + end + + //ocal stg3 centering start +// always @ (posedge clk) +// if(rst) oclkdelay_center_calib_start <= #TCQ 1'b0; +// else +// oclkdelay_center_calib_start <= #TCQ ((init_state_r == INIT_OCAL_CENTER_ACT) && lim_done)? 1'b1: oclkdelay_center_calib_start; + + //*************************************************************************** + // Instantiate FF for the phy_init_data_sel signal. A multi cycle path + // constraint will be assigned to this signal. This signal will only be + // used within the PHY + //*************************************************************************** + +// FDRSE u_ff_phy_init_data_sel +// ( +// .Q (phy_init_data_sel), +// .C (clk), +// .CE (1'b1), +// .D (init_complete_r), +// .R (1'b0), +// .S (1'b0) +// ) /* synthesis syn_preserve=1 */ +// /* synthesis syn_replicate = 0 */; + + + //*************************************************************************** + // Mode register programming + //*************************************************************************** + + //***************************************************************** + // DDR3 Load mode reg0 + // Mode Register (MR0): + // [15:13] - unused - 000 + // [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit), + // 1 (DLL maintained) + // [11:9] - write recovery for Auto Precharge (tWR/tCK = 6) + // [8] - DLL reset - 0 or 1 + // [7] - Test Mode - 0 (normal) + // [6:4],[2] - CAS latency - CAS_LAT + // [3] - Burst Type - BURST_TYPE + // [1:0] - Burst Length - BURST_LEN + // DDR2 Load mode register + // Mode Register (MR): + // [15:14] - unused - 00 + // [13] - reserved - 0 + // [12] - Power-down mode - 0 (normal) + // [11:9] - write recovery - write recovery for Auto Precharge + // (tWR/tCK = 6) + // [8] - DLL reset - 0 or 1 + // [7] - Test Mode - 0 (normal) + // [6:4] - CAS latency - CAS_LAT + // [3] - Burst Type - BURST_TYPE + // [2:0] - Burst Length - BURST_LEN + + //***************************************************************** + generate + if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3 + assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 : + (BURST_MODE == "OTF") ? 2'b01 : + (BURST_MODE == "4") ? 2'b10 : 2'b11; + assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency + assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; + assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 : + ((nCL == 6) || (nCL == 14)) ? 3'b010 : + (nCL == 7) ? 3'b011 : + (nCL == 8) ? 3'b100 : + (nCL == 9) ? 3'b101 : + (nCL == 10) ? 3'b110 : + (nCL == 11) ? 3'b111 : + (nCL == 12) ? 3'b000 : 3'b111; + assign load_mr0[7] = 1'b0; + assign load_mr0[8] = 1'b1; // Reset DLL (init only) + assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 : + (TWR_CYC == 6) ? 3'b010 : + (TWR_CYC == 7) ? 3'b011 : + (TWR_CYC == 8) ? 3'b100 : + (TWR_CYC == 9) ? 3'b101 : + (TWR_CYC == 10) ? 3'b101 : + (TWR_CYC == 11) ? 3'b110 : + (TWR_CYC == 12) ? 3'b110 : + (TWR_CYC == 13) ? 3'b111 : + (TWR_CYC == 14) ? 3'b111 : + (TWR_CYC == 15) ? 3'b000 : + (TWR_CYC == 16) ? 3'b000 : 3'b010; + assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit' + assign load_mr0[15:13] = 3'b000; + end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen + assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 : + (BURST_MODE == "4") ? 3'b010 : 3'b111; + assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; + assign load_mr0[6:4] = (nCL == 3) ? 3'b011 : + (nCL == 4) ? 3'b100 : + (nCL == 5) ? 3'b101 : + (nCL == 6) ? 3'b110 : 3'b111; + assign load_mr0[7] = 1'b0; + assign load_mr0[8] = 1'b1; // Reset DLL (init only) + assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 : + (TWR_CYC == 3) ? 3'b010 : + (TWR_CYC == 4) ? 3'b011 : + (TWR_CYC == 5) ? 3'b100 : + (TWR_CYC == 6) ? 3'b101 : 3'b010; + assign load_mr0[15:12]= 4'b0000; // Reserved + end + endgenerate + + //***************************************************************** + // DDR3 Load mode reg1 + // Mode Register (MR1): + // [15:13] - unused - 00 + // [12] - output enable - 0 (enabled for DQ, DQS, DQS#) + // [11] - TDQS enable - 0 (TDQS disabled and DM enabled) + // [10] - reserved - 0 (must be '0') + // [9] - RTT[2] - 0 + // [8] - reserved - 0 (must be '0') + // [7] - write leveling - 0 (disabled), 1 (enabled) + // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) + // [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7) + // [4:3] - Additive CAS - ADDITIVE_CAS + // [2] - RTT[0] + // [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7) + // [0] - DLL enable - 0 (normal) + // DDR2 ext mode register + // Extended Mode Register (MR): + // [15:14] - unused - 00 + // [13] - reserved - 0 + // [12] - output enable - 0 (enabled) + // [11] - RDQS enable - 0 (disabled) + // [10] - DQS# enable - 0 (enabled) + // [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init) + // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) + // [5:3] - Additive CAS - ADDITIVE_CAS + // [2] - RTT[0] + // [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced) + // [0] - DLL enable - 0 (normal) + //***************************************************************** + + generate + if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3 + assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization + assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1; + assign load_mr1[2] = ((RTT_NOM_int == "30") || (RTT_NOM_int == "40") || + (RTT_NOM_int == "60")) ? 1'b1 : 1'b0; + assign load_mr1[4:3] = (AL == "0") ? 2'b00 : + (AL == "CL-1") ? 2'b01 : + (AL == "CL-2") ? 2'b10 : 2'b11; + assign load_mr1[5] = 1'b0; + assign load_mr1[6] = ((RTT_NOM_int == "40") || (RTT_NOM_int == "120")) ? + 1'b1 : 1'b0; + assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence + assign load_mr1[8] = 1'b0; + assign load_mr1[9] = ((RTT_NOM_int == "20") || (RTT_NOM_int == "30")) ? + 1'b1 : 1'b0; + assign load_mr1[10] = 1'b0; + assign load_mr1[15:11] = 5'b00000; + end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2 + assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization + assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0; + assign load_mr1[2] = ((RTT_NOM_int == "75") || (RTT_NOM_int == "50")) ? + 1'b1 : 1'b0; + assign load_mr1[5:3] = (AL == "0") ? 3'b000 : + (AL == "1") ? 3'b001 : + (AL == "2") ? 3'b010 : + (AL == "3") ? 3'b011 : + (AL == "4") ? 3'b100 : 3'b111; + assign load_mr1[6] = ((RTT_NOM_int == "50") || + (RTT_NOM_int == "150")) ? 1'b1 : 1'b0; + assign load_mr1[9:7] = 3'b000; + assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1; + assign load_mr1[15:11] = 5'b00000; + + end + endgenerate + + //***************************************************************** + // DDR3 Load mode reg2 + // Mode Register (MR2): + // [15:11] - unused - 00 + // [10:9] - RTT_WR - 00 (Dynamic ODT off) + // [8] - reserved - 0 (must be '0') + // [7] - self-refresh temperature range - + // 0 (normal), 1 (extended) + // [6] - Auto Self-Refresh - 0 (manual), 1(auto) + // [5:3] - CAS Write Latency (CWL) - + // 000 (5 for 400 MHz device), + // 001 (6 for 400 MHz to 533 MHz devices), + // 010 (7 for 533 MHz to 667 MHz devices), + // 011 (8 for 667 MHz to 800 MHz) + // [2:0] - Partial Array Self-Refresh (Optional) - + // 000 (full array) + // Not used for DDR2 + //***************************************************************** + generate + if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3 + assign load_mr2[2:0] = 3'b000; + assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 : + (nCWL == 6) ? 3'b001 : + (nCWL == 7) ? 3'b010 : + (nCWL == 8) ? 3'b011 : + (nCWL == 9) ? 3'b100 : + (nCWL == 10) ? 3'b101 : + (nCWL == 11) ? 3'b110 : 3'b111; + assign load_mr2[6] = 1'b0; + assign load_mr2[7] = 1'b0; + assign load_mr2[8] = 1'b0; + // Dynamic ODT disabled + assign load_mr2[10:9] = 2'b00; + assign load_mr2[15:11] = 5'b00000; + end else begin: gen_load_mr2_DDR2 + assign load_mr2[15:0] = 16'd0; + end + endgenerate + + //***************************************************************** + // DDR3 Load mode reg3 + // Mode Register (MR3): + // [15:3] - unused - All zeros + // [2] - MPR Operation - 0(normal operation), 1(data flow from MPR) + // [1:0] - MPR location - 00 (Predefined pattern) + //***************************************************************** + + assign load_mr3[1:0] = 2'b00; + assign load_mr3[2] = 1'b0; + assign load_mr3[15:3] = 13'b0000000000000; + + // For multi-rank systems the rank being accessed during writes in + // Read Leveling must be sent to phy_write for the bitslip logic + assign calib_rank_cnt = chip_cnt_r; + + //*************************************************************************** + // Logic to begin initial calibration, and to handle precharge requests + // during read-leveling (to avoid tRAS violations if individual read + // levelling calibration stages take more than max{tRAS) to complete). + //*************************************************************************** + + // Assert when readback for each stage of read-leveling begins. However, + // note this indicates only when the read command is issued and when + // Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not + // indicate when the read data is present on the bus (when this happens + // after the read command is issued depends on CAS LATENCY) - there will + // need to be some delay before valid data is present on the bus. +// assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS); + + // Assert when read back for oclkdelay calibration begins + assign oclkdelay_calib_start_pre = (init_state_r == INIT_OCAL_CENTER_ACT); //(init_state_r == INIT_OCLKDELAY_READ); + + // Assert when read back for write calibration begins + assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS); + + // Common precharge signal done signal - pulses only when there has been + // a precharge issued as a result of a PRECH_REQ pulse. Note also a common + // PRECH_DONE signal is used for all blocks + assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || + ((rdlvl_last_byte_done_r || prbs_last_byte_done_r) && (init_state_r == INIT_RDLVL_ACT_WAIT) && cnt_cmd_done_r) || + (dqs_found_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || + (init_state_r == INIT_MPR_RDEN) || + ((init_state_r == INIT_WRCAL_ACT_WAIT) && cnt_cmd_done_r) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && complex_oclkdelay_calib_start_r1) || + ((init_state_r == INIT_OCLKDELAY_ACT_WAIT) && cnt_cmd_done_r) || + ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) && prbs_last_byte_done_r) || //prbs_rdlvl_done + (wrlvl_final && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r && ~oclkdelay_calib_done)) && + prech_pending_r && + !prech_req_posedge_r); + + always @(posedge clk) + if (rst) + calib_tap_inc_start <= #TCQ 1'b0; + else if (init_state_r == INIT_SKIP_CALIB_WAIT) + calib_tap_inc_start <= #TCQ 1'b1; + + always @(posedge clk) + calib_tap_inc_done_r1 <= #TCQ calib_tap_inc_done; + + always @(posedge clk) + if (rst || (init_state_r == INIT_WRCAL_WRITE)) + calib_tap_end_if_reset <= #TCQ 1'b0; + else if (calib_tap_inc_done && ~calib_tap_inc_done_r1) + calib_tap_end_if_reset <= #TCQ 1'b1; + + always @(posedge clk) + if (rst) + pi_phaselock_start <= #TCQ 1'b0; + else if (init_state_r == INIT_PI_PHASELOCK_READS) + pi_phaselock_start <= #TCQ 1'b1; + + // Delay start of each calibration by 16 clock cycles to ensure that when + // calibration logic begins, read data is already appearing on the bus. + // Each circuit should synthesize using an SRL16. Assume that reset is + // long enough to clear contents of SRL16. + always @(posedge clk) begin + rdlvl_last_byte_done_r <= #TCQ rdlvl_last_byte_done; + prbs_last_byte_done_r <= #TCQ prbs_last_byte_done; + rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0], + rdlvl_start_pre}; + wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0], + wrcal_start_pre}; + oclkdelay_start_dly_r <= #TCQ {oclkdelay_start_dly_r[14:0], + oclkdelay_calib_start_pre}; + prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0], + prech_done_pre}; + end + + always @(posedge clk) + if (rst) + oclkdelay_calib_start_int <= #TCQ 1'b0; + else if (oclkdelay_start_dly_r[5]) + oclkdelay_calib_start_int <= #TCQ 1'b1; + + always @(posedge clk) begin + if (rst) + ocal_last_byte_done <= #TCQ 1'b0; + else if ((complex_oclkdelay_calib_cnt == DQS_WIDTH-1) && oclkdelay_center_calib_done) + ocal_last_byte_done <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || (init_state_r == INIT_REFRESH) || prbs_rdlvl_done || ocal_last_byte_done || oclkdelay_center_calib_done) + oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; + else if (oclkdelay_calib_start_int) begin + if (oclkdelay_ref_cnt > 'd0) + oclkdelay_ref_cnt <= #TCQ oclkdelay_ref_cnt - 1; + else + oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; + end + end + + always @(posedge clk) begin + if (rst || (init_state_r == INIT_OCAL_CENTER_ACT) || oclkdelay_calib_done || ocal_last_byte_done || oclkdelay_center_calib_done) + oclkdelay_int_ref_req <= #TCQ 1'b0; + else if (oclkdelay_ref_cnt == 'd1) + oclkdelay_int_ref_req <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + ocal_act_wait_cnt <= #TCQ 'd0; + else if ((init_state_r == INIT_OCAL_CENTER_ACT_WAIT) && ocal_act_wait_cnt < 'd15) + ocal_act_wait_cnt <= #TCQ ocal_act_wait_cnt + 1; + else + ocal_act_wait_cnt <= #TCQ 'd0; + end + + always @(posedge clk) begin + if (rst || (init_state_r == INIT_OCLKDELAY_READ)) + oclk_calib_resume_level <= #TCQ 1'b0; + else if (oclk_calib_resume) + oclk_calib_resume_level <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || (init_state_r == INIT_RDLVL_ACT_WAIT) || prbs_rdlvl_done) + complex_rdlvl_int_ref_req <= #TCQ 1'b0; + else if (oclkdelay_ref_cnt == 'd1) +// complex_rdlvl_int_ref_req <= #TCQ 1'b1; + complex_rdlvl_int_ref_req <= #TCQ 1'b0; //temporary fix for read issue + end + + always @(posedge clk) begin + if (rst || (init_state_r == INIT_RDLVL_COMPLEX_READ)) + ext_int_ref_req <= #TCQ 1'b0; + else if ((init_state_r == INIT_RDLVL_ACT_WAIT) && complex_rdlvl_int_ref_req) + ext_int_ref_req <= #TCQ 1'b1; + end + + + always @(posedge clk) begin + prech_done <= #TCQ prech_done_dly_r[15]; + prech_done_r1 <= #TCQ prech_done_dly_r[15]; + prech_done_r2 <= #TCQ prech_done_r1; + prech_done_r3 <= #TCQ prech_done_r2; + end + + + always @(posedge clk) + if (rst) + mpr_rdlvl_start <= #TCQ 1'b0; + else if (pi_dqs_found_done && + (init_state_r == INIT_MPR_READ)) + mpr_rdlvl_start <= #TCQ 1'b1; + + always @(posedge clk) + phy_if_empty_r <= #TCQ phy_if_empty; + + always @(posedge clk) + if (rst || + ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || prbs_rdlvl_done) + prbs_gen_clk_en <= #TCQ 1'b0; + else if ((~phy_if_empty_r && rdlvl_stg1_done_r1 && ~prbs_rdlvl_done) || + ((init_state_r == INIT_RDLVL_ACT_WAIT) && rdlvl_stg1_done_r1 && (cnt_cmd_r == 'd127)) || + ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && rdlvl_stg1_done_r1 && (complex_wait_cnt == 'd14)) + || (init_state_r == INIT_RDLVL_COMPLEX_READ) || ((init_state_r == INIT_PRECHARGE_PREWAIT) && prbs_rdlvl_start)) + prbs_gen_clk_en <= #TCQ 1'b1; + + //Enable for complex oclkdelay - used in prbs gen + always @(posedge clk) + if (rst || + ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || complex_oclkdelay_calib_done || + (complex_wait_cnt == 'd15 && complex_num_writes == 1 && complex_ocal_wr_start) || + ( init_state_r == INIT_RDLVL_STG1_WRITE && complex_num_writes_dec == 'd2) || ~complex_ocal_wr_start || + (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT ) || + (init_state_r != INIT_OCAL_COMPLEX_RESUME_WAIT && init_state_r1 == INIT_OCAL_COMPLEX_RESUME_WAIT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT)) + prbs_gen_oclk_clk_en <= #TCQ 1'b0; + else if ((~phy_if_empty_r && ~complex_oclkdelay_calib_done && prbs_rdlvl_done_r1) || // changed for new algo 3/26 + ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd14)) || + ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14)) || + exit_ocal_complex_resume_wait || + ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && ~stg1_wr_done && ~complex_row1_wr_done && ~complex_ocal_num_samples_done_r && (complex_wait_cnt == 'd14)) + || (init_state_r == INIT_RDLVL_COMPLEX_READ) ) + prbs_gen_oclk_clk_en <= #TCQ 1'b1; + +generate +if (RANKS < 2) begin + always @(posedge clk) + if (rst) begin + rdlvl_stg1_start <= #TCQ 1'b0; + rdlvl_stg1_start_int <= #TCQ 1'b0; + rdlvl_start_pre <= #TCQ 1'b0; + prbs_rdlvl_start <= #TCQ 1'b0; + end else begin + if (pi_dqs_found_done && cnt_cmd_done_r && + (init_state_r == INIT_RDLVL_ACT_WAIT)) + rdlvl_stg1_start_int <= #TCQ 1'b1; + if (pi_dqs_found_done && + (init_state_r == INIT_RDLVL_STG1_READ))begin + rdlvl_start_pre <= #TCQ 1'b1; + rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; + end + if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && + (init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT) && (WRLVL == "ON")) begin + prbs_rdlvl_start <= #TCQ 1'b1; + end + end +end else begin + always @(posedge clk) + if (rst || rdlvl_stg1_rank_done) begin + rdlvl_stg1_start <= #TCQ 1'b0; + rdlvl_stg1_start_int <= #TCQ 1'b0; + rdlvl_start_pre <= #TCQ 1'b0; + prbs_rdlvl_start <= #TCQ 1'b0; + end else begin + if (pi_dqs_found_done && cnt_cmd_done_r && + (init_state_r == INIT_RDLVL_ACT_WAIT)) + rdlvl_stg1_start_int <= #TCQ 1'b1; + if (pi_dqs_found_done && + (init_state_r == INIT_RDLVL_STG1_READ))begin + rdlvl_start_pre <= #TCQ 1'b1; + rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; + end + if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && + (init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT) && (WRLVL == "ON")) begin + prbs_rdlvl_start <= #TCQ 1'b1; + end + end +end +endgenerate + + + always @(posedge clk) begin + if (rst || dqsfound_retry || wrlvl_byte_redo) begin + pi_dqs_found_start <= #TCQ 1'b0; + wrcal_start <= #TCQ 1'b0; + end else begin + if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ) + pi_dqs_found_start <= #TCQ 1'b1; + if (wrcal_start_dly_r[5]) + wrcal_start <= #TCQ 1'b1; + end + end // else: !if(rst) + + + always @(posedge clk) + if (rst) + oclkdelay_calib_start <= #TCQ 1'b0; + else if (oclkdelay_start_dly_r[5]) + oclkdelay_calib_start <= #TCQ 1'b1; + + always @(posedge clk) + if (rst) + pi_dqs_found_done_r1 <= #TCQ 1'b0; + else + pi_dqs_found_done_r1 <= #TCQ pi_dqs_found_done; + + + always @(posedge clk) + wrlvl_final_r <= #TCQ wrlvl_final; + + // Reset IN_FIFO after final write leveling to make sure the FIFO + // pointers are initialized + always @(posedge clk) + if (rst || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_REFRESH)) + wrlvl_final_if_rst <= #TCQ 1'b0; + else if (wrlvl_done_r && //(wrlvl_final_r && wrlvl_done_r && + (init_state_r == INIT_WRLVL_LOAD_MR2)) + wrlvl_final_if_rst <= #TCQ 1'b1; + + // Constantly enable DQS while write leveling is enabled in the memory + // This is more to get rid of warnings in simulation, can later change + // this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted + + always @(posedge clk) + if (rst || + ((init_state_r1 != INIT_WRLVL_START) && + (init_state_r == INIT_WRLVL_START))) + wrlvl_odt_ctl <= #TCQ 1'b0; + else if (wrlvl_rank_done && ~wrlvl_rank_done_r1) + wrlvl_odt_ctl <= #TCQ 1'b1; + + generate + if (nCK_PER_CLK == 4) begin: en_cnt_div4 + always @ (posedge clk) + if (rst) + enable_wrlvl_cnt <= #TCQ 5'd0; + else if ((init_state_r == INIT_WRLVL_START) || + (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) + enable_wrlvl_cnt <= #TCQ 5'd12; + else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) + enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; + + // ODT stays asserted as long as write_calib + // signal is asserted + always @(posedge clk) + if (rst || wrlvl_odt_ctl) + wrlvl_odt <= #TCQ 1'b0; + else if (enable_wrlvl_cnt == 5'd1) + wrlvl_odt <= #TCQ 1'b1; + + end else begin: en_cnt_div2 + always @ (posedge clk) + if (rst) + enable_wrlvl_cnt <= #TCQ 5'd0; + else if ((init_state_r == INIT_WRLVL_START) || + (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) + enable_wrlvl_cnt <= #TCQ 5'd21; + else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) + enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; + + // ODT stays asserted as long as write_calib + // signal is asserted + always @(posedge clk) + if (rst || wrlvl_odt_ctl) + wrlvl_odt <= #TCQ 1'b0; + else if (enable_wrlvl_cnt == 5'd1) + wrlvl_odt <= #TCQ 1'b1; + + end + endgenerate + + always @(posedge clk) + if (rst || wrlvl_rank_done || done_dqs_tap_inc) + wrlvl_active <= #TCQ 1'b0; + else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active) + wrlvl_active <= #TCQ 1'b1; + +// signal used to assert DQS for write leveling. +// the DQS will be asserted once every 16 clock cycles. + always @(posedge clk)begin + if(rst || (enable_wrlvl_cnt != 5'd1)) begin + wr_level_dqs_asrt <= #TCQ 1'd0; + end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin + wr_level_dqs_asrt <= #TCQ 1'd1; + end + end + + always @ (posedge clk) begin + if (rst || (wrlvl_done_r && ~wrlvl_done_r1)) + dqs_asrt_cnt <= #TCQ 2'd0; + else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3) + dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1); + end + + always @ (posedge clk) begin + if (rst || ~wrlvl_active) + wr_lvl_start <= #TCQ 1'd0; + else if (dqs_asrt_cnt == 2'd3) + wr_lvl_start <= #TCQ 1'd1; + end + + + always @(posedge clk) begin + if (rst) + wl_sm_start <= #TCQ 1'b0; + else + wl_sm_start <= #TCQ wr_level_dqs_asrt_r1; + end + + + always @(posedge clk) begin + wrlvl_active_r1 <= #TCQ wrlvl_active; + wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt; + wrlvl_done_r <= #TCQ wrlvl_done; + wrlvl_done_r1 <= #TCQ wrlvl_done_r; + wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done; + wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1; + wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2; + wrlvl_rank_done_r4 <= #TCQ wrlvl_rank_done_r3; + wrlvl_rank_done_r5 <= #TCQ wrlvl_rank_done_r4; + wrlvl_rank_done_r6 <= #TCQ wrlvl_rank_done_r5; + wrlvl_rank_done_r7 <= #TCQ wrlvl_rank_done_r6; + end + + always @ (posedge clk) begin + //if (rst) + wrlvl_rank_cntr <= #TCQ 3'd0; + //else if (wrlvl_rank_done) + // wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1; + end + + //***************************************************************** + // Precharge request logic - those calibration logic blocks + // that require greater than tRAS(max) to finish must break up + // their calibration into smaller units of time, with precharges + // issued in between. This is done using the XXX_PRECH_REQ and + // PRECH_DONE handshaking between PHY_INIT and those blocks + //***************************************************************** + + // Shared request from multiple sources + assign prech_req = oclk_prech_req | rdlvl_prech_req | wrcal_prech_req | prbs_rdlvl_prech_req | + (dqs_found_prech_req & (init_state_r == INIT_RDLVL_STG2_READ_WAIT)); + + // Handshaking logic to force precharge during read leveling, and to + // notify read leveling logic when precharge has been initiated and + // it's okay to proceed with leveling again + always @(posedge clk) + if (rst) begin + prech_req_r <= #TCQ 1'b0; + prech_req_posedge_r <= #TCQ 1'b0; + prech_pending_r <= #TCQ 1'b0; + end else begin + prech_req_r <= #TCQ prech_req; + prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r; + if (prech_req_posedge_r) + prech_pending_r <= #TCQ 1'b1; + // Clear after we've finished with the precharge and have + // returned to issuing read leveling calibration reads + else if (prech_done_pre) + prech_pending_r <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || prech_done_r3) + mask_lim_done <= #TCQ 1'b0; + else if (prech_pending_r) + mask_lim_done <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || prbs_rdlvl_done_r3) + complex_mask_lim_done <= #TCQ 1'b0; + else if (~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) + complex_mask_lim_done <= #TCQ 1'b1; + end + + //Complex oclkdelay calibrration + + //*************************************************************************** + // Various timing counters + //*************************************************************************** + + //***************************************************************** + // Generic delay for various states that require it (e.g. for turnaround + // between read and write). Make this a sufficiently large number of clock + // cycles to cover all possible frequencies and memory components) + // Requirements for this counter: + // 1. Greater than tMRD + // 2. tRFC (refresh-active) for DDR2 + // 3. (list the other requirements, slacker...) + //***************************************************************** + + always @(posedge clk) begin + case (init_state_r) + INIT_LOAD_MR_WAIT, + INIT_WRLVL_LOAD_MR_WAIT, + INIT_WRLVL_LOAD_MR2_WAIT, + INIT_MPR_WAIT, + INIT_MPR_DISABLE_PREWAIT, + INIT_MPR_DISABLE_WAIT, + INIT_OCLKDELAY_ACT_WAIT, + INIT_OCLKDELAY_WRITE_WAIT, + INIT_RDLVL_ACT_WAIT, + INIT_RDLVL_STG1_WRITE_READ, + INIT_RDLVL_STG2_READ_WAIT, + INIT_WRCAL_ACT_WAIT, + INIT_WRCAL_WRITE_READ, + INIT_WRCAL_READ_WAIT, + INIT_PRECHARGE_PREWAIT, + INIT_PRECHARGE_WAIT, + INIT_DDR2_PRECHARGE_WAIT, + INIT_REG_WRITE_WAIT, + INIT_REFRESH_WAIT, + INIT_REFRESH_RNK2_WAIT: begin + if (phy_ctl_full || phy_cmd_full) + cnt_cmd_r <= #TCQ cnt_cmd_r; + else + cnt_cmd_r <= #TCQ cnt_cmd_r + 1; + end + INIT_WRLVL_WAIT: + cnt_cmd_r <= #TCQ 'b0; + default: + cnt_cmd_r <= #TCQ 'b0; + endcase + end + + // pulse when count reaches terminal count + always @(posedge clk) + cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD); + + // For ODT deassertion - hold throughout post read/write wait stage, but + // deassert before next command. The post read/write stage is very long, so + // we simply address the longest case here plus some margin. + always @(posedge clk) + cnt_cmd_done_m7_r <= #TCQ (cnt_cmd_r == (CNTNEXT_CMD - 7)); + +//************************************************************************ +// Added to support PO fine delay inc when TG errors + always @(posedge clk) begin + case (init_state_r) + INIT_WRCAL_READ_WAIT: begin + if (phy_ctl_full || phy_cmd_full) + cnt_wait <= #TCQ cnt_wait; + else + cnt_wait <= #TCQ cnt_wait + 1; + end + default: + cnt_wait <= #TCQ 'b0; + endcase + end + + always @(posedge clk) + cnt_wrcal_rd <= #TCQ (cnt_wait == 'd4); + + always @(posedge clk) begin + if (rst || ~temp_wrcal_done) + temp_lmr_done <= #TCQ 1'b0; + else if (temp_wrcal_done && (init_state_r == INIT_LOAD_MR)) + temp_lmr_done <= #TCQ 1'b1; + end + + always @(posedge clk) + temp_wrcal_done_r <= #TCQ temp_wrcal_done; + + always @(posedge clk) + if (rst) begin + tg_timer_go <= #TCQ 1'b0; + end else if ((PRE_REV3ES == "ON") && temp_wrcal_done && temp_lmr_done && + (init_state_r == INIT_WRCAL_READ_WAIT)) begin + tg_timer_go <= #TCQ 1'b1; + end else begin + tg_timer_go <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || (temp_wrcal_done && ~temp_wrcal_done_r) || + (init_state_r == INIT_PRECHARGE_PREWAIT)) + tg_timer <= #TCQ 'd0; + else if ((pi_phaselock_timer == PHASELOCKED_TIMEOUT) && + tg_timer_go && + (tg_timer != TG_TIMER_TIMEOUT)) + tg_timer <= #TCQ tg_timer + 1; + end + + always @(posedge clk) begin + if (rst) + tg_timer_done <= #TCQ 1'b0; + else if (tg_timer == TG_TIMER_TIMEOUT) + tg_timer_done <= #TCQ 1'b1; + else + tg_timer_done <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst) + no_rst_tg_mc <= #TCQ 1'b0; + else if ((init_state_r == INIT_WRCAL_ACT) && wrcal_read_req) + no_rst_tg_mc <= #TCQ 1'b1; + else + no_rst_tg_mc <= #TCQ 1'b0; + end + +//************************************************************************ + + always @(posedge clk) begin + if (rst) + detect_pi_found_dqs <= #TCQ 1'b0; + else if ((cnt_cmd_r == 7'b0111111) && + (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) + detect_pi_found_dqs <= #TCQ 1'b1; + else + detect_pi_found_dqs <= #TCQ 1'b0; + end + + //***************************************************************** + // Initial delay after power-on for RESET, CKE + // NOTE: Could reduce power consumption by turning off these counters + // after initial power-up (at expense of more logic) + // NOTE: Likely can combine multiple counters into single counter + //***************************************************************** + + // Create divided by 1024 version of clock + always @(posedge clk) + if (rst) begin + cnt_pwron_ce_r <= #TCQ 10'h000; + pwron_ce_r <= #TCQ 1'b0; + end else begin + cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1; + pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF); + end + + // "Main" power-on counter - ticks every CLKDIV/1024 cycles + always @(posedge clk) + if (rst) + cnt_pwron_r <= #TCQ 'b0; + else if (pwron_ce_r) + cnt_pwron_r <= #TCQ cnt_pwron_r + 1; + + always @(posedge clk) + if (rst || ~phy_ctl_ready) begin + cnt_pwron_reset_done_r <= #TCQ 1'b0; + cnt_pwron_cke_done_r <= #TCQ 1'b0; + end else begin + // skip power-up count for simulation purposes only + if ((SIM_INIT_OPTION == "SKIP_PU_DLY") || + (SIM_INIT_OPTION == "SKIP_INIT")) begin + cnt_pwron_reset_done_r <= #TCQ 1'b1; + cnt_pwron_cke_done_r <= #TCQ 1'b1; + end else begin + // otherwise, create latched version of done signal for RESET, CKE + if (DRAM_TYPE == "DDR3") begin + if (!cnt_pwron_reset_done_r) + cnt_pwron_reset_done_r + <= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT); + if (!cnt_pwron_cke_done_r) + cnt_pwron_cke_done_r + <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); + end else begin // DDR2 + cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed + if (!cnt_pwron_cke_done_r) + cnt_pwron_cke_done_r + <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); + end + end + end // else: !if(rst || ~phy_ctl_ready) + + + always @(posedge clk) + cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r; + + // Keep RESET asserted and CKE deasserted until after power-on delay + always @(posedge clk or posedge rst) begin + if (rst) + phy_reset_n <= #TCQ 1'b0; + else + phy_reset_n <= #TCQ cnt_pwron_reset_done_r; +// phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}}; + end + + //***************************************************************** + // Counter for tXPR (pronouned "Tax-Payer") - wait time after + // CKE deassertion before first MRS command can be asserted + //***************************************************************** + + always @(posedge clk) + if (!cnt_pwron_cke_done_r) begin + cnt_txpr_r <= #TCQ 'b0; + cnt_txpr_done_r <= #TCQ 1'b0; + end else begin + cnt_txpr_r <= #TCQ cnt_txpr_r + 1; + if (!cnt_txpr_done_r) + cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT); + end + + //***************************************************************** + // Counter for the initial 400ns wait for issuing precharge all + // command after CKE assertion. Only for DDR2. + //***************************************************************** + + always @(posedge clk) + if (!cnt_pwron_cke_done_r) begin + cnt_init_pre_wait_r <= #TCQ 'b0; + cnt_init_pre_wait_done_r <= #TCQ 1'b0; + end else begin + cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1; + if (!cnt_init_pre_wait_done_r) + cnt_init_pre_wait_done_r + <= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT); + end + + //***************************************************************** + // Wait for both DLL to lock (tDLLK) and ZQ calibration to finish + // (tZQINIT). Both take the same amount of time (512*tCK) + //***************************************************************** + + always @(posedge clk) + if (init_state_r == INIT_ZQCL) begin + cnt_dllk_zqinit_r <= #TCQ 'b0; + cnt_dllk_zqinit_done_r <= #TCQ 1'b0; + end else if (~(phy_ctl_full || phy_cmd_full)) begin + cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1; + if (!cnt_dllk_zqinit_done_r) + cnt_dllk_zqinit_done_r + <= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT); + end + + //***************************************************************** + // Keep track of which MRS counter needs to be programmed during + // memory initialization + // The counter and the done signal are reset an additional time + // for DDR2. The same signals are used for the additional DDR2 + // initialization sequence. + //***************************************************************** + + always @(posedge clk) + if ((init_state_r == INIT_IDLE)|| + ((init_state_r == INIT_REFRESH) + && (~mem_init_done_r))) begin + cnt_init_mr_r <= #TCQ 'b0; + cnt_init_mr_done_r <= #TCQ 1'b0; + end else if (init_state_r == INIT_LOAD_MR) begin + cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1; + cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE); + end + + + //***************************************************************** + // Flag to tell if the first precharge for DDR2 init sequence is + // done + //***************************************************************** + + always @(posedge clk) + if (init_state_r == INIT_IDLE) + ddr2_pre_flag_r<= #TCQ 'b0; + else if (init_state_r == INIT_LOAD_MR) + ddr2_pre_flag_r<= #TCQ 1'b1; + // reset the flag for multi rank case + else if ((ddr2_refresh_flag_r) && + (init_state_r == INIT_LOAD_MR_WAIT)&& + (cnt_cmd_done_r) && (cnt_init_mr_done_r)) + ddr2_pre_flag_r <= #TCQ 'b0; + + //***************************************************************** + // Flag to tell if the refresh stat for DDR2 init sequence is + // reached + //***************************************************************** + + always @(posedge clk) + if (init_state_r == INIT_IDLE) + ddr2_refresh_flag_r<= #TCQ 'b0; + else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r)) + // reset the flag for multi rank case + ddr2_refresh_flag_r<= #TCQ 1'b1; + else if ((ddr2_refresh_flag_r) && + (init_state_r == INIT_LOAD_MR_WAIT)&& + (cnt_cmd_done_r) && (cnt_init_mr_done_r)) + ddr2_refresh_flag_r <= #TCQ 'b0; + + //***************************************************************** + // Keep track of the number of auto refreshes for DDR2 + // initialization. The spec asks for a minimum of two refreshes. + // Four refreshes are performed here. The two extra refreshes is to + // account for the 200 clock cycle wait between step h and l. + // Without the two extra refreshes we would have to have a + // wait state. + //***************************************************************** + + always @(posedge clk) + if (init_state_r == INIT_IDLE) begin + cnt_init_af_r <= #TCQ 'b0; + cnt_init_af_done_r <= #TCQ 1'b0; + end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin + cnt_init_af_r <= #TCQ cnt_init_af_r + 1; + cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11); + end + + //***************************************************************** + // Keep track of the register control word programming for + // DDR3 RDIMM + //***************************************************************** + + always @(posedge clk) + if (init_state_r == INIT_IDLE) + reg_ctrl_cnt_r <= #TCQ 'b0; + else if (init_state_r == INIT_REG_WRITE) + reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1; + + generate + if (RANKS < 2) begin: one_rank + always @(posedge clk) + if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || + (complex_byte_rd_done) || prbs_rdlvl_done_pulse ) + stg1_wr_done <= #TCQ 1'b0; + else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) + stg1_wr_done <= #TCQ 1'b1; + end else begin: two_ranks + always @(posedge clk) + if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || + (complex_byte_rd_done) || prbs_rdlvl_done_pulse || + (rdlvl_stg1_rank_done )) + stg1_wr_done <= #TCQ 1'b0; + else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) + stg1_wr_done <= #TCQ 1'b1; + end + endgenerate + + always @(posedge clk) + if (rst) + rnk_ref_cnt <= #TCQ 1'b0; + else if (stg1_wr_done && + (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r) + rnk_ref_cnt <= #TCQ ~rnk_ref_cnt; + + + always @(posedge clk) + if (rst || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r ==INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT)) + num_refresh <= #TCQ 'd0; + else if ((init_state_r == INIT_REFRESH) && + (~pi_dqs_found_done || ((DRAM_TYPE == "DDR3") && ~oclkdelay_calib_done) || + (rdlvl_stg1_done && ~prbs_rdlvl_done) || + (prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || + ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || + ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done))) + num_refresh <= #TCQ num_refresh + 1; + + + //*************************************************************************** + // Initialization state machine + //*************************************************************************** + + //***************************************************************** + // Next-state logic + //***************************************************************** + + always @(posedge clk) + if (rst)begin + init_state_r <= #TCQ INIT_IDLE; + init_state_r1 <= #TCQ INIT_IDLE; + end else begin + init_state_r <= #TCQ init_next_state; + init_state_r1 <= #TCQ init_state_r; + end + + always @(*) begin + init_next_state = init_state_r; + (* full_case, parallel_case *) case (init_state_r) + + //******************************************************* + // DRAM initialization + //******************************************************* + + // Initial state - wait for: + // 1. Power-on delays to pass + // 2. PHY Control Block to assert phy_ctl_ready + // 3. PHY Control FIFO must not be FULL + // 4. Read path initialization to finish + INIT_IDLE: + if (cnt_pwron_cke_done_r && phy_ctl_ready && ck_addr_cmd_delay_done && delay_incdec_done + && ~(phy_ctl_full || phy_cmd_full) ) begin + // If skipping memory initialization (simulation only) + if (SIM_INIT_OPTION == "SKIP_INIT") + //if (WRLVL == "ON") + // Proceed to write leveling + // init_next_state = INIT_WRLVL_START; + //else //if (SIM_CAL_OPTION != "SKIP_CAL") + // Proceed to Phaser_In phase lock + init_next_state = INIT_RDLVL_ACT; + // else + // Skip read leveling + //init_next_state = INIT_DONE; + else + init_next_state = INIT_WAIT_CKE_EXIT; + end + + // Wait minimum of Reset CKE exit time (tXPR = max(tXS, + INIT_WAIT_CKE_EXIT: + if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3") + && ~(phy_ctl_full || phy_cmd_full)) begin + if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) || + (RANKS > 1))) + //register write for reg dimm. Some register chips + // have the register chip in a pre-programmed state + // in that case the nCS_PER_RANK == 1 && RANKS == 1 + init_next_state = INIT_REG_WRITE; + else + // Load mode register - this state is repeated multiple times + init_next_state = INIT_LOAD_MR; + end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2") + && ~(phy_ctl_full || phy_cmd_full)) + // DDR2 start with a precharge all command + init_next_state = INIT_DDR2_PRECHARGE; + + INIT_REG_WRITE: + init_next_state = INIT_REG_WRITE_WAIT; + + INIT_REG_WRITE_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + if(reg_ctrl_cnt_r == 4'd8) + init_next_state = INIT_LOAD_MR; + else + init_next_state = INIT_REG_WRITE; + end + + INIT_LOAD_MR: + init_next_state = INIT_LOAD_MR_WAIT; + // After loading MR, wait at least tMRD + + INIT_LOAD_MR_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + // If finished loading all mode registers, proceed to next step + if (prbs_rdlvl_done && pi_dqs_found_done && rdlvl_stg1_done) + // for ddr3 when the correct burst length is writtern at end + init_next_state = INIT_PRECHARGE; + else if (~wrcal_done && temp_lmr_done) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (cnt_init_mr_done_r)begin + if(DRAM_TYPE == "DDR3") + init_next_state = INIT_ZQCL; + else begin //DDR2 + if(ddr2_refresh_flag_r)begin + // memory initialization per rank for multi-rank case + if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) + init_next_state = INIT_DDR2_MULTI_RANK; + else + init_next_state = INIT_RDLVL_ACT; + // ddr2 initialization done.load mode state after refresh + end else + init_next_state = INIT_DDR2_PRECHARGE; + end + end else + init_next_state = INIT_LOAD_MR; + end + + // DDR2 multi rank transition state + INIT_DDR2_MULTI_RANK: + init_next_state = INIT_DDR2_MULTI_RANK_WAIT; + + INIT_DDR2_MULTI_RANK_WAIT: + init_next_state = INIT_DDR2_PRECHARGE; + + // Initial ZQ calibration + INIT_ZQCL: + init_next_state = INIT_WAIT_DLLK_ZQINIT; + + // Wait until both DLL have locked, and ZQ calibration done + INIT_WAIT_DLLK_ZQINIT: + if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full)) + // memory initialization per rank for multi-rank case + if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) + init_next_state = INIT_LOAD_MR; + //else if (WRLVL == "ON") + // init_next_state = INIT_WRLVL_START; + else + // skip write-leveling (e.g. for DDR2 interface) + init_next_state = INIT_RDLVL_ACT; + + // Initial precharge for DDR2 + INIT_DDR2_PRECHARGE: + init_next_state = INIT_DDR2_PRECHARGE_WAIT; + + INIT_DDR2_PRECHARGE_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + if (ddr2_pre_flag_r) + init_next_state = INIT_REFRESH; + else // from precharge state initially go to load mode + init_next_state = INIT_LOAD_MR; + end + + INIT_REFRESH: + if ((SKIP_CALIB == "TRUE") && ~calib_tap_inc_done && pi_dqs_found_done) + init_next_state = INIT_SKIP_CALIB_WAIT; + else if ((RANKS == 2) && (chip_cnt_r == RANKS - 1)) + init_next_state = INIT_REFRESH_RNK2_WAIT; + else + init_next_state = INIT_REFRESH_WAIT; + + INIT_REFRESH_RNK2_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) + init_next_state = INIT_PRECHARGE; + + INIT_REFRESH_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin + if(cnt_init_af_done_r && (~mem_init_done_r)) + // go to lm state as part of DDR2 init sequence + init_next_state = INIT_LOAD_MR; + // Go to state to issue back-to-back writes during limit check and centering + else if (~oclkdelay_calib_done && (mpr_last_byte_done || mpr_rdlvl_done) && (DRAM_TYPE == "DDR3")) begin + if (num_refresh == 'd8) + init_next_state = INIT_OCAL_CENTER_ACT; + else + init_next_state = INIT_REFRESH; + end else if(rdlvl_stg1_done && oclkdelay_center_calib_done && + complex_oclkdelay_calib_done && ~wrlvl_done_r1 && (WRLVL == "ON")) + init_next_state = INIT_WRLVL_START; + else if (pi_dqs_found_done && ~wrlvl_done_r1 && ~wrlvl_final && ~wrlvl_byte_redo && (WRLVL == "ON")) + init_next_state = INIT_WRLVL_START; + else if ((((prbs_last_byte_done_r || prbs_rdlvl_done) && ~complex_oclkdelay_calib_done + && pi_dqs_found_done) && (WRLVL == "ON")) //&& rdlvl_stg1_done // changed for new algo 3/26 + && mem_init_done_r) begin + if (num_refresh == 'd8) begin + if (BYPASS_COMPLEX_OCAL == "FALSE") + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; + else + init_next_state = INIT_WRCAL_ACT; + end else + init_next_state = INIT_REFRESH; + end else if (~pi_dqs_found_done || + (rdlvl_stg1_done && ~prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || + ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || + ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)) begin + if (num_refresh == 'd8) + init_next_state = INIT_RDLVL_ACT; + else + init_next_state = INIT_REFRESH; + end else if ((~wrcal_done && wrlvl_byte_redo)&& (DRAM_TYPE == "DDR3") + && (CLK_PERIOD/nCK_PER_CLK > 2500)) + init_next_state = INIT_WRLVL_LOAD_MR2; + else if (((prbs_rdlvl_done && rdlvl_stg1_done && complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) + && mem_init_done_r && (CLK_PERIOD/nCK_PER_CLK > 2500)) + init_next_state = INIT_WRCAL_ACT; + else if (pi_dqs_found_done && (DRAM_TYPE == "DDR3") && ~(mpr_last_byte_done || mpr_rdlvl_done)) begin + if (num_refresh == 'd8) + init_next_state = INIT_MPR_RDEN; + else + init_next_state = INIT_REFRESH; + end else if (((oclkdelay_calib_done && wrlvl_final && ~wrlvl_done_r1) || // changed for new algo 3/25 + (~wrcal_done && wrlvl_byte_redo)) && (DRAM_TYPE == "DDR3")) + init_next_state = INIT_WRLVL_LOAD_MR2; + else if ((~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) + && pi_dqs_found_done) + init_next_state = INIT_WRCAL_ACT; + else if (mem_init_done_r) begin + if (RANKS < 2) + init_next_state = INIT_RDLVL_ACT; + else if (stg1_wr_done && ~rnk_ref_cnt && ~rdlvl_stg1_done) + init_next_state = INIT_PRECHARGE; + else + init_next_state = INIT_RDLVL_ACT; + end else // to DDR2 init state as part of DDR2 init sequence + init_next_state = INIT_REFRESH; + end + + INIT_SKIP_CALIB_WAIT: + if (calib_tap_inc_done) + init_next_state = INIT_WRCAL_ACT; + + + //****************************************************** + // Write Leveling + //******************************************************* + + // Enable write leveling in MR1 and start write leveling + // for current rank + INIT_WRLVL_START: + init_next_state = INIT_WRLVL_WAIT; + + // Wait for both MR load and write leveling to complete + // (write leveling should take much longer than MR load..) + INIT_WRLVL_WAIT: + if (wrlvl_rank_done_r7 && ~(phy_ctl_full || phy_cmd_full)) + init_next_state = INIT_WRLVL_LOAD_MR; + + // Disable write leveling in MR1 for current rank + INIT_WRLVL_LOAD_MR: + init_next_state = INIT_WRLVL_LOAD_MR_WAIT; + + INIT_WRLVL_LOAD_MR_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) + init_next_state = INIT_WRLVL_LOAD_MR2; + + // Load MR2 to set ODT: Dynamic ODT for single rank case + // And ODTs for multi-rank case as well + INIT_WRLVL_LOAD_MR2: + init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; + + // Wait tMRD before proceeding + INIT_WRLVL_LOAD_MR2_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + //if (wrlvl_byte_done) + // init_next_state = INIT_PRECHARGE_PREWAIT; + // else if ((RANKS == 2) && wrlvl_rank_done_r2) + // init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; + if (~wrlvl_done_r1) + init_next_state = INIT_WRLVL_START; + else if (SIM_CAL_OPTION == "SKIP_CAL") + // If skip rdlvl, then we're done + init_next_state = INIT_DONE; + else + // Otherwise, proceed to read leveling + //init_next_state = INIT_RDLVL_ACT; + init_next_state = INIT_PRECHARGE_PREWAIT; + end + + //******************************************************* + // Read Leveling + //******************************************************* + + // single row activate. All subsequent read leveling writes and + // read will take place in this row + INIT_RDLVL_ACT: + init_next_state = INIT_RDLVL_ACT_WAIT; + + // hang out for awhile before issuing subsequent column commands + // it's also possible to reach this state at various points + // during read leveling - determine what the current stage is + INIT_RDLVL_ACT_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + // Just finished an activate. Now either write, read, or precharge + // depending on where we are in the training sequence + if (!pi_calib_done_r1) + init_next_state = INIT_PI_PHASELOCK_READS; + else if (!pi_dqs_found_done) + // (!pi_dqs_found_start || pi_dqs_found_rank_done)) + init_next_state = INIT_RDLVL_STG2_READ; + else if (~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) + init_next_state = INIT_WRCAL_ACT_WAIT; + else if ((!rdlvl_stg1_done && ~stg1_wr_done && ~rdlvl_last_byte_done) || + (!prbs_rdlvl_done && ~stg1_wr_done && ~prbs_last_byte_done)) begin + // Added to avoid rdlvl_stg1 write data pattern at the start of PRBS rdlvl + if (!prbs_rdlvl_done && ~stg1_wr_done && rdlvl_last_byte_done) + init_next_state = INIT_RDLVL_ACT_WAIT; + else + init_next_state = INIT_RDLVL_STG1_WRITE; + end else if ((!rdlvl_stg1_done && rdlvl_stg1_start_int) || !prbs_rdlvl_done) begin + if (rdlvl_last_byte_done || prbs_last_byte_done) + // Added to avoid extra reads at the end of read leveling + init_next_state = INIT_RDLVL_ACT_WAIT; + else begin + // Case 2: If in stage 1, and just precharged after training + // previous byte, then continue reading + if (rdlvl_stg1_done) + init_next_state = INIT_RDLVL_STG1_WRITE_READ; + else + init_next_state = INIT_RDLVL_STG1_READ; + end + end else if ((prbs_rdlvl_done && rdlvl_stg1_done && (RANKS == 1)) && (WRLVL == "ON") && + (CLK_PERIOD/nCK_PER_CLK > 2500)) + init_next_state = INIT_WRCAL_ACT_WAIT; + else + // Otherwise, if we're finished with calibration, then precharge + // the row - silly, because we just opened it - possible to take + // this out by adding logic to avoid the ACT in first place. Make + // sure that cnt_cmd_done will handle tRAS(min) + init_next_state = INIT_PRECHARGE_PREWAIT; + end + + //************************************************** + // Back-to-back reads for Phaser_IN Phase locking + // DQS to FREQ_REF clock + //************************************************** + + INIT_PI_PHASELOCK_READS: + if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) + init_next_state = INIT_PRECHARGE_PREWAIT; + + //********************************************* + // Stage 1 read-leveling (write and continuous read) + //********************************************* + + // Write training pattern for stage 1 + // PRBS pattern of TBD length + INIT_RDLVL_STG1_WRITE: + // 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle + // 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words + // 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words + // An entire row worth of writes issued before proceeding to reads + // The number of write is (2^column width)/burst length to accomodate + // PRBS pattern for window detection. + //VCCO/VCCAUX write is not done + if ((complex_num_writes_dec == 1) && ~complex_row0_wr_done && prbs_rdlvl_done && rdlvl_stg1_done_r1) + init_next_state = INIT_OCAL_COMPLEX_WRITE_WAIT; + //back to back write from row1 + else if (stg1_wr_rd_cnt == 9'd1) begin + if (rdlvl_stg1_done_r1) + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; + else + init_next_state = INIT_RDLVL_STG1_WRITE_READ; + end + + INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT: + if (complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (complex_wait_cnt == 'd15) + //At the end of the byte, it goes to REFRESH + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE; + + INIT_RDLVL_COMPLEX_PRECHARGE: + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; + + INIT_RDLVL_COMPLEX_PRECHARGE_WAIT: + if (complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (complex_wait_cnt == 'd15) begin + if (prbs_rdlvl_done || prbs_last_byte_done_r) begin // changed for new algo 3/26 + // added condition to ensure that limit starts after rdlvl_stg1_done is asserted in the bypass complex rdlvl mode + if ((~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) || ~lim_done) + init_next_state = INIT_OCAL_CENTER_ACT; //INIT_OCAL_COMPLEX_ACT; // changed for new algo 3/26 + else if (lim_done && complex_oclkdelay_calib_start_r2) + init_next_state = INIT_RDLVL_COMPLEX_ACT; + else + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; + end else + init_next_state = INIT_RDLVL_COMPLEX_ACT; + end + + + INIT_RDLVL_COMPLEX_ACT: + //only for sampling boundary it need to wait + //when initial pi dec is not done in complex per-bit, it need to wait + if(prbs_rdlvl_start && (num_samples_done_r || ~complex_init_pi_dec_done)) + init_next_state = INIT_RDLVL_COMPLEX_PI_WAIT; + else init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT; + + //wait PI movement is done before proceeding read + INIT_RDLVL_COMPLEX_PI_WAIT: + if(complex_pi_incdec_done) + init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT; + + INIT_RDLVL_COMPLEX_ACT_WAIT: + if (complex_rdlvl_int_ref_req || prech_req_posedge_r) //prech req always happen in this state + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (complex_wait_cnt == 'd15) begin + if (oclkdelay_center_calib_start) + init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; + else if (stg1_wr_done) + init_next_state = INIT_RDLVL_COMPLEX_READ; + else if (~complex_row1_wr_done) + if (complex_oclkdelay_calib_start_int && complex_ocal_num_samples_done_r) //WAIT for resume signal for write + init_next_state = INIT_OCAL_COMPLEX_RESUME_WAIT; + else + init_next_state = INIT_RDLVL_STG1_WRITE; + else + init_next_state = INIT_RDLVL_STG1_WRITE_READ; + end + + // Write-read turnaround + INIT_RDLVL_STG1_WRITE_READ: + if (reset_rd_addr_r1) + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; + else if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin + if (rdlvl_stg1_done_r1) + //before going to read, wait for PI inc/dec done + init_next_state = INIT_RDLVL_COMPLEX_PI_WAIT; + else + init_next_state = INIT_RDLVL_STG1_READ; + end + + // Continuous read, where interruptible by precharge request from + // calibration logic. Also precharges when stage 1 is complete + // No precharges when reads provided to Phaser_IN for phase locking + // FREQ_REF to read DQS since data integrity is not important. + INIT_RDLVL_STG1_READ: + if (rdlvl_stg1_rank_done || (rdlvl_stg1_done && ~rdlvl_stg1_done_r1) || + prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) + init_next_state = INIT_PRECHARGE_PREWAIT; + + INIT_RDLVL_COMPLEX_READ: + if (prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) + init_next_state = INIT_PRECHARGE_PREWAIT; + //For non-back-to-back reads from row0 (VCCO and VCCAUX pattern) + else if (~prbs_rdlvl_done && (complex_num_reads_dec == 1) && ~complex_row0_rd_done) + init_next_state = INIT_RDLVL_COMPLEX_READ_WAIT; + //For back-to-back reads from row1 (ISI pattern) + else if (stg1_wr_rd_cnt == 'd1) + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; + + INIT_RDLVL_COMPLEX_READ_WAIT: + if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (stg1_wr_rd_cnt == 'd1) + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; + else if (complex_wait_cnt == 'd15) + init_next_state = INIT_RDLVL_COMPLEX_READ; + + + //********************************************* + // DQSFOUND calibration (set of 4 reads with gaps) + //********************************************* + + // Read of training data. Note that Stage 2 is not a constant read, + // instead there is a large gap between each set of back-to-back reads + INIT_RDLVL_STG2_READ: + // 4 read commands issued back-to-back + if (num_reads == 'b1) + init_next_state = INIT_RDLVL_STG2_READ_WAIT; + + // Wait before issuing the next set of reads. If a precharge request + // comes in then handle - this can occur after stage 2 calibration is + // completed for a DQS group + INIT_RDLVL_STG2_READ_WAIT: + if (~(phy_ctl_full || phy_cmd_full)) begin + if (pi_dqs_found_rank_done || + pi_dqs_found_done || prech_req_posedge_r) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (cnt_cmd_done_r) + init_next_state = INIT_RDLVL_STG2_READ; + end + + + //****************************************************************** + // MPR Read Leveling for DDR3 OCLK_DELAYED calibration + //****************************************************************** + + // Issue Load Mode Register 3 command with A[2]=1, A[1:0]=2'b00 + // to enable Multi Purpose Register (MPR) Read + INIT_MPR_RDEN: + init_next_state = INIT_MPR_WAIT; + + //Wait tMRD, tMOD + INIT_MPR_WAIT: + if (cnt_cmd_done_r) begin + init_next_state = INIT_MPR_READ; + end + + // Issue back-to-back read commands to read from MPR with + // Address bus 0x0000 for BL=8. DQ[0] will output the pre-defined + // MPR pattern of 01010101 (Rise0 = 1'b0, Fall0 = 1'b1 ...) + INIT_MPR_READ: + if (mpr_rdlvl_done || mpr_rnk_done || rdlvl_prech_req) + init_next_state = INIT_MPR_DISABLE_PREWAIT; + + INIT_MPR_DISABLE_PREWAIT: + if (cnt_cmd_done_r) + init_next_state = INIT_MPR_DISABLE; + + // Issue Load Mode Register 3 command with A[2]=0 to disable + // MPR read + INIT_MPR_DISABLE: + init_next_state = INIT_MPR_DISABLE_WAIT; + + INIT_MPR_DISABLE_WAIT: + init_next_state = INIT_PRECHARGE_PREWAIT; + + + //*********************************************************************** + // OCLKDELAY Calibration + //*********************************************************************** + + // This calibration requires single write followed by single read to + // determine the Phaser_Out stage 3 delay required to center write DQS + // in write DQ valid window. + + // Single Row Activate command before issuing Write command + INIT_OCLKDELAY_ACT: + init_next_state = INIT_OCLKDELAY_ACT_WAIT; + + INIT_OCLKDELAY_ACT_WAIT: + if (cnt_cmd_done_r && ~oclk_prech_req) + init_next_state = INIT_OCLKDELAY_WRITE; + else if (oclkdelay_calib_done || prech_req_posedge_r) + init_next_state = INIT_PRECHARGE_PREWAIT; + + INIT_OCLKDELAY_WRITE: + if (oclk_wr_cnt == 4'd1) + init_next_state = INIT_OCLKDELAY_WRITE_WAIT; + + INIT_OCLKDELAY_WRITE_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + if (oclkdelay_int_ref_req) + init_next_state = INIT_PRECHARGE_PREWAIT; + else + init_next_state = INIT_OCLKDELAY_READ; + end + + INIT_OCLKDELAY_READ: + init_next_state = INIT_OCLKDELAY_READ_WAIT; + + INIT_OCLKDELAY_READ_WAIT: + if (~(phy_ctl_full || phy_cmd_full)) begin + if ((oclk_calib_resume_level || oclk_calib_resume) && ~oclkdelay_int_ref_req) + init_next_state = INIT_OCLKDELAY_WRITE; + else if (oclkdelay_calib_done || prech_req_posedge_r || + wrlvl_final || oclkdelay_int_ref_req) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (oclkdelay_center_calib_start) + init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; + end + + + //********************************************* + // Write calibration + //********************************************* + + // single row activate + INIT_WRCAL_ACT: + init_next_state = INIT_WRCAL_ACT_WAIT; + + // hang out for awhile before issuing subsequent column command + INIT_WRCAL_ACT_WAIT: + if (cnt_cmd_done_r && ~wrcal_prech_req) + init_next_state = INIT_WRCAL_WRITE; + else if (wrcal_done || prech_req_posedge_r) + init_next_state = INIT_PRECHARGE_PREWAIT; + + // Write training pattern for write calibration + INIT_WRCAL_WRITE: + // Once we've issued enough commands for 8 words - proceed to reads + //if (burst_addr_r == 1'b1) + if (wrcal_wr_cnt == 4'd1) + init_next_state = INIT_WRCAL_WRITE_READ; + + // Write-read turnaround + INIT_WRCAL_WRITE_READ: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) + init_next_state = INIT_WRCAL_READ; + else if (dqsfound_retry) + init_next_state = INIT_RDLVL_STG2_READ_WAIT; + + + INIT_WRCAL_READ: + if (burst_addr_r == 1'b1) + init_next_state = INIT_WRCAL_READ_WAIT; + + INIT_WRCAL_READ_WAIT: + if (~(phy_ctl_full || phy_cmd_full)) begin + if (wrcal_resume_r) begin + if (wrcal_final_chk) + init_next_state = INIT_WRCAL_READ; + else + init_next_state = INIT_WRCAL_WRITE; + end else if (wrcal_done || prech_req_posedge_r || wrcal_act_req || + // Added to support PO fine delay inc when TG errors + wrlvl_byte_redo || (temp_wrcal_done && ~temp_lmr_done)) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (dqsfound_retry) + init_next_state = INIT_RDLVL_STG2_READ_WAIT; + else if (wrcal_read_req && cnt_wrcal_rd) + init_next_state = INIT_WRCAL_MULT_READS; + end + + INIT_WRCAL_MULT_READS: + // multiple read commands issued back-to-back + if (wrcal_reads == 'b1) + init_next_state = INIT_WRCAL_READ_WAIT; + + //********************************************* + // Handling of precharge during and in between read-level stages + //********************************************* + + // Make sure we aren't violating any timing specs by precharging + // immediately + INIT_PRECHARGE_PREWAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) + init_next_state = INIT_PRECHARGE; + + // Initiate precharge + INIT_PRECHARGE: + init_next_state = INIT_PRECHARGE_WAIT; + + INIT_PRECHARGE_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + if ((wrcal_sanity_chk_done && (DRAM_TYPE == "DDR3")) || + (rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && + (DRAM_TYPE == "DDR2"))) + init_next_state = INIT_DONE; + else if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done && prbs_rdlvl_done && + pi_dqs_found_done && complex_oclkdelay_calib_done && wrlvl_done_r1 && ((ddr3_lm_done_r) || (DRAM_TYPE == "DDR2"))) + init_next_state = INIT_WRCAL_ACT; + else if ((wrcal_done || (WRLVL == "OFF") || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) + && (rdlvl_stg1_done || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) + && prbs_rdlvl_done && complex_oclkdelay_calib_done && wrlvl_done_r1 &rdlvl_stg1_done && pi_dqs_found_done) begin + // after all calibration program the correct burst length + init_next_state = INIT_LOAD_MR; + // Added to support PO fine delay inc when TG errors + end else if (~wrcal_done && temp_wrcal_done && temp_lmr_done) + init_next_state = INIT_WRCAL_READ_WAIT; + else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == "ON")) + // If read leveling finished, proceed to write calibration + init_next_state = INIT_REFRESH; + else + // Otherwise, open row for read-leveling purposes + init_next_state = INIT_REFRESH; + end + + //******************************************************* + // COMPLEX OCLK calibration - for fragmented write + //******************************************************* + INIT_OCAL_COMPLEX_ACT: + init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; + + INIT_OCAL_COMPLEX_ACT_WAIT: + if (complex_wait_cnt =='d15) + init_next_state = INIT_RDLVL_STG1_WRITE; + + INIT_OCAL_COMPLEX_WRITE_WAIT: + if (prech_req_posedge_r || (complex_oclkdelay_calib_done && ~complex_oclkdelay_calib_done_r1)) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (stg1_wr_rd_cnt == 'd1) + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; + else if (complex_wait_cnt == 'd15) + init_next_state = INIT_RDLVL_STG1_WRITE; + + //wait for all srg2/stg3 tap movement is done and go back to write again + INIT_OCAL_COMPLEX_RESUME_WAIT: + if (complex_oclk_calib_resume) + init_next_state = INIT_RDLVL_STG1_WRITE; + else if (complex_oclkdelay_calib_done || complex_ocal_ref_req ) + init_next_state = INIT_PRECHARGE_PREWAIT; + + //******************************************************* + // OCAL STG3 Centering calibration + //******************************************************* + INIT_OCAL_CENTER_ACT: + init_next_state = INIT_OCAL_CENTER_ACT_WAIT; + + INIT_OCAL_CENTER_ACT_WAIT: + if (ocal_act_wait_cnt == 'd15) + init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; + + INIT_OCAL_CENTER_WRITE: + if(!oclk_center_write_resume && !lim_wr_req) + init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; + + INIT_OCAL_CENTER_WRITE_WAIT: + //if (oclkdelay_center_calib_done || prech_req_posedge_r) + if (prech_req_posedge_r) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && oclkdelay_calib_done && ~oclkdelay_center_calib_start) + init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; + else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && ~oclkdelay_center_calib_start) + init_next_state = INIT_OCLKDELAY_READ_WAIT; + else if (oclk_center_write_resume || lim_wr_req) + init_next_state = INIT_OCAL_CENTER_WRITE; + + //******************************************************* + // Initialization/Calibration done. Take a long rest, relax + //******************************************************* + + INIT_DONE: + init_next_state = INIT_DONE; + + endcase + end + + //***************************************************************** + // Initialization done signal - asserted before leveling starts + //***************************************************************** + + + always @(posedge clk) + if (rst) + mem_init_done_r <= #TCQ 1'b0; + else if ((!cnt_dllk_zqinit_done_r && + (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) && + (chip_cnt_r == RANKS-1) && (DRAM_TYPE == "DDR3")) + || ( (init_state_r == INIT_LOAD_MR_WAIT) && + (ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1) + && (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2"))) + mem_init_done_r <= #TCQ 1'b1; + + //***************************************************************** + // Write Calibration signal to PHY Control Block - asserted before + // Write Leveling starts + //***************************************************************** + + //generate + //if (RANKS < 2) begin: ranks_one + always @(posedge clk) begin + if (rst || (done_dqs_tap_inc && + (init_state_r == INIT_WRLVL_LOAD_MR2))) + write_calib <= #TCQ 1'b0; + else if (wrlvl_active_r1) + write_calib <= #TCQ 1'b1; + end + //end else begin: ranks_two + // always @(posedge clk) begin + // if (rst || + // ((init_state_r1 == INIT_WRLVL_LOAD_MR_WAIT) && + // ((wrlvl_rank_done_r2 && (chip_cnt_r == RANKS-1)) || + // (SIM_CAL_OPTION == "FAST_CAL")))) + // write_calib <= #TCQ 1'b0; + // else if (wrlvl_active_r1) + // write_calib <= #TCQ 1'b1; + // end + //end + //endgenerate + + //***************************************************************** + // Read Calibration signal to PHY Control Block - asserted after + // Write Leveling during PHASER_IN phase locking stage. + // Must be de-asserted before Read Leveling + //***************************************************************** + + always @(posedge clk) begin + if (rst || pi_calib_done_r1) + read_calib_int <= #TCQ 1'b0; + else if (~pi_calib_done_r1 && (init_state_r == INIT_RDLVL_ACT_WAIT) && + (cnt_cmd_r == CNTNEXT_CMD)) + read_calib_int <= #TCQ 1'b1; + end + + always @(posedge clk) + read_calib_r <= #TCQ read_calib_int; + + + always @(posedge clk) begin + if (rst || pi_calib_done_r1) + read_calib <= #TCQ 1'b0; + else if (~pi_calib_done_r1 && (init_state_r == INIT_PI_PHASELOCK_READS)) + read_calib <= #TCQ 1'b1; + end + + + always @(posedge clk) + if (rst) + pi_calib_done_r <= #TCQ 1'b0; + else if (pi_calib_rank_done_r)// && (chip_cnt_r == RANKS-1)) + pi_calib_done_r <= #TCQ 1'b1; + + always @(posedge clk) + if (rst) + pi_calib_rank_done_r <= #TCQ 1'b0; + else if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) + pi_calib_rank_done_r <= #TCQ 1'b1; + else + pi_calib_rank_done_r <= #TCQ 1'b0; + + always @(posedge clk) begin + if (rst || ((PRE_REV3ES == "ON") && temp_wrcal_done && ~temp_wrcal_done_r)) + pi_phaselock_timer <= #TCQ 'd0; + else if (((init_state_r == INIT_PI_PHASELOCK_READS) && + (pi_phaselock_timer != PHASELOCKED_TIMEOUT)) || + tg_timer_go) + pi_phaselock_timer <= #TCQ pi_phaselock_timer + 1; + else + pi_phaselock_timer <= #TCQ pi_phaselock_timer; + end + + assign pi_phase_locked_err = (pi_phaselock_timer == PHASELOCKED_TIMEOUT) ? 1'b1 : 1'b0; + + //***************************************************************** + // DDR3 final burst length programming done. For DDR3 during + // calibration the burst length is fixed to BL8. After calibration + // the correct burst length is programmed. + //***************************************************************** + always @(posedge clk) + if (rst) + ddr3_lm_done_r <= #TCQ 1'b0; + else if ((init_state_r == INIT_LOAD_MR_WAIT) && + (chip_cnt_r == RANKS-1) && wrcal_done) + ddr3_lm_done_r <= #TCQ 1'b1; + + always @(posedge clk) begin + pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done; + pi_phase_locked_all_r1 <= #TCQ pi_phase_locked_all; + pi_phase_locked_all_r2 <= #TCQ pi_phase_locked_all_r1; + pi_phase_locked_all_r3 <= #TCQ pi_phase_locked_all_r2; + pi_phase_locked_all_r4 <= #TCQ pi_phase_locked_all_r3; + pi_dqs_found_all_r <= #TCQ pi_dqs_found_done; + pi_calib_done_r1 <= #TCQ pi_calib_done_r; + end + + //*************************************************************************** + // Logic for deep memory (multi-rank) configurations + //*************************************************************************** + + // For DDR3 asserted when + +generate + if (RANKS < 2) begin: single_rank + always @(posedge clk) + chip_cnt_r <= #TCQ 2'b00; + end else begin: dual_rank + always @(posedge clk) + if (rst || + // Set chip_cnt_r to 2'b00 after both Ranks are read leveled + (rdlvl_stg1_done && prbs_rdlvl_done && ~wrcal_done && (SKIP_CALIB == "FALSE")) || + // Set chip_cnt_r to 2'b00 after both Ranks are write leveled + (wrlvl_done_r && + (init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin + chip_cnt_r <= #TCQ 2'b00; + end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) && + (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) && + (DRAM_TYPE == "DDR3")) || + ((init_state_r==INIT_REFRESH_RNK2_WAIT) && + (cnt_cmd_r=='d36)) || + //mpr_rnk_done || + //(rdlvl_stg1_rank_done && ~rdlvl_last_byte_done) || + //(stg1_wr_done && (init_state_r == INIT_REFRESH) && + //~(rnk_ref_cnt && rdlvl_last_byte_done)) || + + // Increment chip_cnt_r to issue Refresh to second rank + (~pi_dqs_found_all_r && + (init_state_r==INIT_PRECHARGE_PREWAIT) && + (cnt_cmd_r=='d36) && (SKIP_CALIB == "FALSE")) || + + // Increment chip_cnt_r when DQSFOUND done for the Rank + (pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r && (SKIP_CALIB == "FALSE")) || + ((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r + && wrcal_done) || + ((init_state_r == INIT_DDR2_MULTI_RANK) + && (DRAM_TYPE == "DDR2"))) begin + if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done || + // condition to increment chip_cnt during + // final burst length programming for DDR3 + ~pi_calib_done_r || wrcal_done) //~mpr_rdlvl_done || + && (chip_cnt_r != RANKS-1)) + chip_cnt_r <= #TCQ chip_cnt_r + 1; + else + chip_cnt_r <= #TCQ 2'b00; + end + end + endgenerate +// verilint STARC-2.2.3.3 off +generate + if ((REG_CTRL == "ON") && (RANKS == 1)) begin: DDR3_RDIMM_1rank + always @(posedge clk) begin + if (rst) + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + else if (init_state_r == INIT_REG_WRITE) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if(!(CWL_M%2)) begin + phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; + phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; + end else begin + phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; + phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; + end + end else if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if (!(CWL_M % 2)) //even CWL + phy_int_cs_n[0] <= #TCQ 1'b0; + else // odd CWL + phy_int_cs_n[1*nCS_PER_RANK] <= #TCQ 1'b0; + end else + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + end + end else if (RANKS == 1) begin: DDR3_1rank + always @(posedge clk) begin + if (rst) + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + else if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if (!(CWL_M % 2)) begin //even CWL + for (n = 0; n < nCS_PER_RANK; n = n + 1) begin + phy_int_cs_n[n] <= #TCQ 1'b0; + end + end else begin //odd CWL + for (p = nCS_PER_RANK; p < 2*nCS_PER_RANK; p = p + 1) begin + phy_int_cs_n[p] <= #TCQ 1'b0; + end + end + end else + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + end + end else if ((REG_CTRL == "ON") && (RANKS == 2)) begin: DDR3_2rank + always @(posedge clk) begin + if (rst) + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + else if (init_state_r == INIT_REG_WRITE) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if(!(CWL_M%2)) begin + phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; + phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; + end else begin + phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; + phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; + end + end else begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + case (chip_cnt_r) + 2'b00:begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if (!(CWL_M % 2)) //even CWL + phy_int_cs_n[0] <= #TCQ 1'b0; + else // odd CWL + phy_int_cs_n[1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; + end else + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin + // + // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; + //end + end + 2'b01:begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if (!(CWL_M % 2)) //even CWL + phy_int_cs_n[1] <= #TCQ 1'b0; + else // odd CWL + phy_int_cs_n[1+1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; + end else + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin + // + // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; + //end + end + endcase + end + end + end else if (RANKS == 2) begin: DDR3_2rank + always @(posedge clk) begin + if (rst) + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + else if (init_state_r == INIT_REG_WRITE) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if(!(CWL_M%2)) begin + phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; + phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; + end else begin + phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; + phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; + end + end else begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + case (chip_cnt_r) + 2'b00:begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if (!(CWL_M % 2)) begin //even CWL + for (n = 0; n < nCS_PER_RANK; n = n + 1) begin + phy_int_cs_n[n] <= #TCQ 1'b0; + end + end else begin // odd CWL + for (p = CS_WIDTH*nCS_PER_RANK; p < (CS_WIDTH*nCS_PER_RANK + nCS_PER_RANK); p = p + 1) begin + phy_int_cs_n[p] <= #TCQ 1'b0; + end + end + end else + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin + // + // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; + //end + end + 2'b01:begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if (!(CWL_M % 2)) begin //even CWL + for (q = nCS_PER_RANK; q < (2 * nCS_PER_RANK); q = q + 1) begin + phy_int_cs_n[q] <= #TCQ 1'b0; + end + end else begin // odd CWL + for (m = (nCS_PER_RANK*CS_WIDTH + nCS_PER_RANK); m < (nCS_PER_RANK*CS_WIDTH + 2*nCS_PER_RANK); m = m + 1) begin + phy_int_cs_n[m] <= #TCQ 1'b0; + end + end + end else + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin + // + // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; + //end + end + endcase + end + end // always @ (posedge clk) + end +// verilint STARC-2.2.3.3 on + // commented out for now. Need it for DDR2 2T timing + /* end else begin: DDR2 + always @(posedge clk) + if (rst) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + end else begin + if (init_state_r == INIT_REG_WRITE) begin + // All ranks selected simultaneously + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}}; + end else if ((wrlvl_odt) || + (init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_PI_PHASELOCK_READS) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_RDLVL_STG1_READ) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_RDLVL_STG2_READ) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_WRCAL_READ) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH)) begin + phy_int_cs_n[0] <= #TCQ 1'b0; + end + else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + end // else: !if(rst) + end // block: DDR2 */ +endgenerate + + assign phy_cs_n = phy_int_cs_n; + + //*************************************************************************** + // Write/read burst logic for calibration + //*************************************************************************** + + assign rdlvl_wr = (init_state_r == INIT_OCLKDELAY_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE); + assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) || + ((init_state_r == INIT_RDLVL_STG1_READ) && ~rdlvl_pi_incdec) || //rdlvl pi dec + (init_state_r == INIT_RDLVL_COMPLEX_READ) || + (init_state_r == INIT_RDLVL_STG2_READ) || + (init_state_r == INIT_OCLKDELAY_READ) || + (init_state_r == INIT_WRCAL_READ) || + ((init_state_r == INIT_MPR_READ) && ~rdlvl_pi_incdec) || + (init_state_r == INIT_WRCAL_MULT_READS); + assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd; + assign mmcm_wr = (init_state_r == INIT_OCAL_CENTER_WRITE); //used to de-assert cs_n during centering +// assign mmcm_wr = 'b0; // (init_state_r == INIT_OCAL_CENTER_WRITE); + + //*************************************************************************** + // Address generation and logic to count # of writes/reads issued during + // certain stages of calibration + //*************************************************************************** + + // Column address generation logic: + // Keep track of the current column address - since all bursts are in + // increments of 8 only during calibration, we need to keep track of + // addresses [COL_WIDTH-1:3], lower order address bits will always = 0 + + always @(posedge clk) + if (rst || wrcal_done) + burst_addr_r <= #TCQ 1'b0; + else if ((init_state_r == INIT_WRCAL_ACT_WAIT) || + (init_state_r == INIT_OCLKDELAY_ACT_WAIT) || + (init_state_r == INIT_OCLKDELAY_WRITE) || + (init_state_r == INIT_OCLKDELAY_READ) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_WRCAL_WRITE_READ) || + (init_state_r == INIT_WRCAL_READ) || + (init_state_r == INIT_WRCAL_MULT_READS) || + (init_state_r == INIT_WRCAL_READ_WAIT)) + burst_addr_r <= #TCQ 1'b1; + else if (rdlvl_wr_rd && new_burst_r) + burst_addr_r <= #TCQ ~burst_addr_r; + else + burst_addr_r <= #TCQ 1'b0; + + // Read Level Stage 1 requires writes to the entire row since + // a PRBS pattern is being written. This counter keeps track + // of the number of writes which depends on the column width + // The (stg1_wr_rd_cnt==9'd0) condition was added so the col + // address wraps around during stage1 reads + always @(posedge clk) + if (rst || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && + ~rdlvl_stg1_done)) + stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD; + else if (rdlvl_last_byte_done || (stg1_wr_rd_cnt == 9'd1) || + (prbs_rdlvl_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || + (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) ) begin + if (~complex_row0_wr_done || wr_victim_inc || + (complex_row1_wr_done && (~complex_row0_rd_done || (complex_row0_rd_done && complex_row1_rd_done)))) + stg1_wr_rd_cnt <= #TCQ 'd127; + else + stg1_wr_rd_cnt <= #TCQ prbs_rdlvl_done?'d30 :'d22; + end else if (((init_state_r == INIT_RDLVL_STG1_WRITE) && new_burst_r && ~phy_data_full) + ||((init_state_r == INIT_RDLVL_COMPLEX_READ) && rdlvl_stg1_done)) + stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1; + + always @(posedge clk) + if (rst) + wr_victim_inc <= #TCQ 1'b0; + else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2) && ~stg1_wr_done) + wr_victim_inc <= #TCQ 1'b1; + else + wr_victim_inc <= #TCQ 1'b0; + + always @(posedge clk) + reset_rd_addr_r1 <= #TCQ reset_rd_addr; + +generate + if (FIXED_VICTIM == "FALSE") begin: row_cnt_victim_rotate + always @(posedge clk) + if (rst || (wr_victim_inc && (complex_row_cnt == DQ_PER_DQS*2-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) + complex_row_cnt <= #TCQ 'd0; + else if ((((stg1_wr_rd_cnt == 'd22) && ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (complex_rdlvl_int_ref_req && (init_state_r == INIT_REFRESH_WAIT) && (cnt_cmd_r == 'd127)))) || + complex_victim_inc || (complex_sample_cnt_inc_r2 && ~complex_victim_inc) || wr_victim_inc || reset_rd_addr_r1)) begin + // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 + if ((complex_row_cnt < DQ_PER_DQS*2-1) && ~stg1_wr_done) + complex_row_cnt <= #TCQ complex_row_cnt + 1; + // During reads row count requires different conditions for increments + else if (stg1_wr_done) begin + if (reset_rd_addr_r1) + complex_row_cnt <= #TCQ 'd0; + // When looping multiple times in the same victim bit in a byte + else if (complex_sample_cnt_inc_r2 && ~complex_victim_inc) + complex_row_cnt <= #TCQ rd_victim_sel*2; + // When looping through victim bits within a byte + else if (complex_row_cnt < DQ_PER_DQS*2-1) + complex_row_cnt <= #TCQ complex_row_cnt + 1; + // When the number of samples is done and tap is incremented within a byte + else + complex_row_cnt <= #TCQ 'd0; + end + end + end else begin: row_cnt_victim_fixed + always @(posedge clk) + if (rst || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) + complex_row_cnt <= #TCQ 'd0; + else if ((stg1_wr_rd_cnt == 'd22) && (((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) && (complex_wait_cnt == 'd15)) || complex_rdlvl_int_ref_req)) + complex_row_cnt <= #TCQ 'd1; + else + complex_row_cnt <= #TCQ 'd0; + end +endgenerate + +//row count + + always @(posedge clk) + if (rst || (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done_pulse || complex_byte_rd_done) + complex_row_cnt_ocal <= #TCQ 'd0; + else if ( prbs_rdlvl_done && (((stg1_wr_rd_cnt == 'd30) && (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE)) || + (complex_sample_cnt_inc_r2) || wr_victim_inc)) begin + // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 + if (complex_row_cnt_ocal < COMPLEX_ROW_CNT_BYTE-1) begin + complex_row_cnt_ocal <= #TCQ complex_row_cnt_ocal + 1; + end + end + + always @(posedge clk) + if (rst) + complex_odt_ext <= #TCQ 1'b0; + else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE)) + complex_odt_ext <= #TCQ 1'b0; + else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd1) && (init_state_r == INIT_RDLVL_STG1_WRITE)) + complex_odt_ext <= #TCQ 1'b1; + + always @(posedge clk) + if (rst || (wr_victim_inc && (complex_row_cnt == DQ_PER_DQS*2-1))) begin + wr_victim_sel <= #TCQ 'd0; + end else if (rdlvl_stg1_done_r1 && wr_victim_inc) begin + wr_victim_sel <= #TCQ wr_victim_sel + 1; + end + + always @(posedge clk) + if (rst) begin + wr_victim_sel_ocal <= #TCQ 'd0; + end else if (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) begin + wr_victim_sel_ocal <= #TCQ 'd0; + end else if (prbs_rdlvl_done && wr_victim_inc) begin + wr_victim_sel_ocal <= #TCQ wr_victim_sel_ocal + 1; + end + + always @(posedge clk) + if (rst) begin + victim_sel <= #TCQ 'd0; + victim_byte_cnt <= #TCQ 'd0; + end else if ((~stg1_wr_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_wr_done)) begin + victim_sel <= #TCQ prbs_rdlvl_done? wr_victim_sel_ocal: wr_victim_sel; + victim_byte_cnt <= #TCQ 'd0; + end else begin + if( (init_state_r == INIT_RDLVL_COMPLEX_ACT) || reset_rd_addr) + victim_sel <= #TCQ prbs_rdlvl_done? complex_ocal_rd_victim_sel:rd_victim_sel; + victim_byte_cnt <= #TCQ 'd0; + end + +generate + if (FIXED_VICTIM == "FALSE") begin: wr_done_victim_rotate + always @(posedge clk) + if (rst || (wr_victim_inc && (complex_row_cnt < DQ_PER_DQS*2-1) && ~prbs_rdlvl_done) || + (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal 'd85) begin + if (complex_num_reads < 'd6) + complex_num_reads <= #TCQ complex_num_reads + 1; + else + complex_num_reads <= #TCQ 'd1; + // Initila value for VCCAUX pattern is 3, 7, and 12 + end else if (stg1_wr_rd_cnt > 'd73) begin + if (stg1_wr_rd_cnt == 'd85) + complex_num_reads <= #TCQ 'd3; + else if (complex_num_reads < 'd5) + complex_num_reads <= #TCQ complex_num_reads + 1; + end else if (stg1_wr_rd_cnt > 'd39) begin + if (stg1_wr_rd_cnt == 'd73) + complex_num_reads <= #TCQ 'd7; + else if (complex_num_reads < 'd10) + complex_num_reads <= #TCQ complex_num_reads + 1; + end else begin + if (stg1_wr_rd_cnt == 'd39) + complex_num_reads <= #TCQ 'd12; + else if (complex_num_reads < 'd14) + complex_num_reads <= #TCQ complex_num_reads + 1; + end + // Initialize to 1 at the start of reads or after precharge and activate + end else if ((((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && ~ext_int_ref_req) || + ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && (stg1_wr_rd_cnt == 'd22))) + complex_num_reads <= #TCQ 'd1; + + always @(posedge clk) + if (rst) + complex_num_reads_dec <= #TCQ 'd1; + else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || + ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) + complex_num_reads_dec <= #TCQ complex_num_reads; + else if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (complex_num_reads_dec > 'd0)) + complex_num_reads_dec <= #TCQ complex_num_reads_dec - 1; + + always @(posedge clk) + if (rst) + complex_address <= #TCQ 'd0; + else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ_WAIT)) || + ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (init_state_r1 != INIT_OCAL_COMPLEX_WRITE_WAIT))) + complex_address <= #TCQ phy_address[COL_WIDTH-1:0]; + + + always @ (posedge clk) + if (rst) + complex_oclkdelay_calib_start_int <= #TCQ 'b0; + else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && prbs_last_byte_done_r) // changed for new algo 3/26 + complex_oclkdelay_calib_start_int <= #TCQ 'b1; + + always @(posedge clk) begin + complex_oclkdelay_calib_start_r1 <= #TCQ complex_oclkdelay_calib_start_int; + complex_oclkdelay_calib_start_r2 <= #TCQ complex_oclkdelay_calib_start_r1; + end + + always @ (posedge clk) + if (rst) + complex_oclkdelay_calib_start <= #TCQ 'b0; + else if (complex_oclkdelay_calib_start_int && (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT) && prbs_rdlvl_done) // changed for new algo 3/26 + complex_oclkdelay_calib_start <= #TCQ 'b1; + + //packet fragmentation for complex oclkdealy calib write + always @(posedge clk) + if (rst || prbs_rdlvl_done_pulse) begin + complex_num_writes <= #TCQ 'd1; + end else if ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14) && ~complex_row0_wr_done) begin + if (stg1_wr_rd_cnt > 'd85) begin + if (complex_num_writes < 'd6) + complex_num_writes <= #TCQ complex_num_writes + 1; + else + complex_num_writes <= #TCQ 'd1; + // Initila value for VCCAUX pattern is 3, 7, and 12 + end else if (stg1_wr_rd_cnt > 'd73) begin + if (stg1_wr_rd_cnt == 'd85) + complex_num_writes <= #TCQ 'd3; + else if (complex_num_writes < 'd5) + complex_num_writes <= #TCQ complex_num_writes + 1; + end else if (stg1_wr_rd_cnt > 'd39) begin + if (stg1_wr_rd_cnt == 'd73) + complex_num_writes <= #TCQ 'd7; + else if (complex_num_writes < 'd10) + complex_num_writes <= #TCQ complex_num_writes + 1; + end else begin + if (stg1_wr_rd_cnt == 'd39) + complex_num_writes <= #TCQ 'd12; + else if (complex_num_writes < 'd14) + complex_num_writes <= #TCQ complex_num_writes + 1; + end + // Initialize to 1 at the start of write or after precharge and activate + end else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row0_wr_done) + complex_num_writes <= #TCQ 'd30; + else if (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) + complex_num_writes <= #TCQ 'd1; + + always @(posedge clk) + if (rst || prbs_rdlvl_done_pulse) + complex_num_writes_dec <= #TCQ 'd1; + else if (((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || + ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) + complex_num_writes_dec <= #TCQ complex_num_writes; + else if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (complex_num_writes_dec > 'd0)) + complex_num_writes_dec <= #TCQ complex_num_writes_dec - 1; + + always @(posedge clk) + if (rst) + complex_sample_cnt_inc_ocal <= #TCQ 1'b0; + else if ((stg1_wr_rd_cnt == 9'd1) && complex_byte_rd_done && prbs_rdlvl_done) + complex_sample_cnt_inc_ocal <= #TCQ 1'b1; + else + complex_sample_cnt_inc_ocal <= #TCQ 1'b0; + + always @(posedge clk) + if (rst) + complex_sample_cnt_inc <= #TCQ 1'b0; + else if ((stg1_wr_rd_cnt == 9'd1) && complex_row1_rd_done) + complex_sample_cnt_inc <= #TCQ 1'b1; + else + complex_sample_cnt_inc <= #TCQ 1'b0; + + always @(posedge clk) begin + complex_sample_cnt_inc_r1 <= #TCQ complex_sample_cnt_inc; + complex_sample_cnt_inc_r2 <= #TCQ complex_sample_cnt_inc_r1; + end + + //complex refresh req + always @ (posedge clk) begin + if(rst || (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_ACT)) ) + complex_ocal_ref_done <= #TCQ 1'b1; + else if (init_state_r == INIT_RDLVL_STG1_WRITE) + complex_ocal_ref_done <= #TCQ 1'b0; + end + + //complex ocal odt extention + always @(posedge clk) + if (rst) + complex_ocal_odt_ext <= #TCQ 1'b0; + else if (((init_state_r == INIT_PRECHARGE_PREWAIT) && cnt_cmd_done_m7_r) || (init_state_r == INIT_OCLKDELAY_READ_WAIT)) + complex_ocal_odt_ext <= #TCQ 1'b0; + else if ((init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT)) + complex_ocal_odt_ext <= #TCQ 1'b1; + + // OCLKDELAY calibration requires multiple writes because + // write can be up to 2 cycles early since OCLKDELAY tap + // can go down to 0 + always @(posedge clk) + if (rst || (init_state_r == INIT_OCLKDELAY_WRITE_WAIT) || + (oclk_wr_cnt == 4'd0)) + oclk_wr_cnt <= #TCQ NUM_STG1_WR_RD; + else if ((init_state_r == INIT_OCLKDELAY_WRITE) && + new_burst_r && ~phy_data_full) + oclk_wr_cnt <= #TCQ oclk_wr_cnt - 1; + + // Write calibration requires multiple writes because + // write can be up to 2 cycles early due to new write + // leveling algorithm to avoid late writes + always @(posedge clk) + if (rst || (init_state_r == INIT_WRCAL_WRITE_READ) || + (wrcal_wr_cnt == 4'd0)) + wrcal_wr_cnt <= #TCQ NUM_STG1_WR_RD; + else if ((init_state_r == INIT_WRCAL_WRITE) && + new_burst_r && ~phy_data_full) + wrcal_wr_cnt <= #TCQ wrcal_wr_cnt - 1; + + +generate +if(nCK_PER_CLK == 4) begin:back_to_back_reads_4_1 + // 4 back-to-back reads with gaps for + // read data_offset calibration (rdlvl stage 2) + always @(posedge clk) + if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) + num_reads <= #TCQ 3'b000; + else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) + num_reads <= #TCQ num_reads - 1; + else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || + phy_cmd_full && new_burst_r) + num_reads <= #TCQ 3'b011; +end else if(nCK_PER_CLK == 2) begin: back_to_back_reads_2_1 + // 4 back-to-back reads with gaps for + // read data_offset calibration (rdlvl stage 2) + always @(posedge clk) + if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) + num_reads <= #TCQ 3'b000; + else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) + num_reads <= #TCQ num_reads - 1; + else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || + phy_cmd_full && new_burst_r) + num_reads <= #TCQ 3'b111; +end +endgenerate + + // back-to-back reads during write calibration + always @(posedge clk) + if (rst ||(init_state_r == INIT_WRCAL_READ_WAIT)) + wrcal_reads <= #TCQ 2'b00; + else if ((wrcal_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full)) + wrcal_reads <= #TCQ wrcal_reads - 1; + else if ((init_state_r == INIT_WRCAL_MULT_READS) || phy_ctl_full || + phy_cmd_full && new_burst_r) + wrcal_reads <= #TCQ 'd255; + + // determine how often to issue row command during read leveling writes + // and reads + always @(posedge clk) + if (rdlvl_wr_rd) begin + // 2:1 mode - every other command issued is a data command + // 4:1 mode - every command issued is a data command + if (nCK_PER_CLK == 2) begin + if (!phy_ctl_full) + new_burst_r <= #TCQ ~new_burst_r; + end else + new_burst_r <= #TCQ 1'b1; + end else + new_burst_r <= #TCQ 1'b1; + + // indicate when a write is occurring. PHY_WRDATA_EN must be asserted + // simultaneous with the corresponding command/address for CWL = 5,6 + always @(posedge clk) begin + rdlvl_wr_r <= #TCQ rdlvl_wr; + calib_wrdata_en <= #TCQ phy_wrdata_en; + end + + always @(posedge clk) begin + if (rst || wrcal_done) + extend_cal_pat <= #TCQ 1'b0; + else if (temp_lmr_done && (PRE_REV3ES == "ON")) + extend_cal_pat <= #TCQ 1'b1; + end + + + generate + if ((nCK_PER_CLK == 4) || (BURST_MODE == "4")) begin: wrdqen_div4 + // Write data enable asserted for one DIV4 clock cycle + // Only BL8 supported with DIV4. DDR2 BL4 will use DIV2. + always @(*) begin + if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_WRCAL_WRITE))) + phy_wrdata_en = 1'b1; + else + phy_wrdata_en = 1'b0; + end + end else begin: wrdqen_div2 // block: wrdqen_div4 + always @(*) + if((rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full) + | phy_wrdata_en_r1) + phy_wrdata_en = 1'b1; + else + phy_wrdata_en = 1'b0; + + always @(posedge clk) + phy_wrdata_en_r1 <= #TCQ rdlvl_wr & ~phy_ctl_full & new_burst_r + & ~phy_data_full; + + always @(posedge clk) begin + if (!phy_wrdata_en & first_rdlvl_pat_r) + wrdata_pat_cnt <= #TCQ 2'b00; + else if (wrdata_pat_cnt == 2'b11) + wrdata_pat_cnt <= #TCQ 2'b10; + else + wrdata_pat_cnt <= #TCQ wrdata_pat_cnt + 1; + end + + always @(posedge clk) begin + if (!phy_wrdata_en & first_wrcal_pat_r) + wrcal_pat_cnt <= #TCQ 2'b00; + else if (extend_cal_pat && (wrcal_pat_cnt == 2'b01)) + wrcal_pat_cnt <= #TCQ 2'b00; + else if (wrcal_pat_cnt == 2'b11) + wrcal_pat_cnt <= #TCQ 2'b10; + else + wrcal_pat_cnt <= #TCQ wrcal_pat_cnt + 1; + end + + end + endgenerate + + + // indicate when a write is occurring. PHY_RDDATA_EN must be asserted + // simultaneous with the corresponding command/address. PHY_RDDATA_EN + // is used during read-leveling to determine read latency + assign phy_rddata_en = ~phy_if_empty; + + // Read data valid generation for MC and User Interface after calibration is + // complete + assign phy_rddata_valid = init_complete_r1_timing ? phy_rddata_en : 1'b0; + + //*************************************************************************** + // Generate training data written at start of each read-leveling stage + // For every stage of read leveling, 8 words are written into memory + // The format is as follows (shown as {rise,fall}): + // Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0 + // Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 + //*************************************************************************** + + + always @(posedge clk) + if ((init_state_r == INIT_IDLE) || + (init_state_r == INIT_RDLVL_STG1_WRITE)) + cnt_init_data_r <= #TCQ 2'b00; + else if (phy_wrdata_en) + cnt_init_data_r <= #TCQ cnt_init_data_r + 1; + else if (init_state_r == INIT_WRCAL_WRITE) + cnt_init_data_r <= #TCQ 2'b10; + + + // write different sequence for very + // first write to memory only. Used to help us differentiate + // if the writes are "early" or "on-time" during read leveling + always @(posedge clk) + if (rst || rdlvl_stg1_rank_done) + first_rdlvl_pat_r <= #TCQ 1'b1; + else if (phy_wrdata_en && (init_state_r == INIT_RDLVL_STG1_WRITE)) + first_rdlvl_pat_r <= #TCQ 1'b0; + + + always @(posedge clk) + if (rst || wrcal_resume || + (init_state_r == INIT_WRCAL_ACT_WAIT)) + first_wrcal_pat_r <= #TCQ 1'b1; + else if (phy_wrdata_en && (init_state_r == INIT_WRCAL_WRITE)) + first_wrcal_pat_r <= #TCQ 1'b0; + +generate + if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 2)) begin: wrdq_div2_2to1_rdlvl_first + + always @(posedge clk) + if (~oclkdelay_calib_done) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, + {DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}}, + {DQ_WIDTH/4{4'h0}}}; + else if (!rdlvl_stg1_done) begin + // The 16 words for stage 1 write data in 2:1 mode is written + // over 4 consecutive controller clock cycles. Note that write + // data follows phy_wrdata_en by one clock cycle + case (wrdata_pat_cnt) + 2'b00: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h3}}, + {DQ_WIDTH/4{4'h9}}}; + end + + 2'b01: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hC}}}; + end + + 2'b10: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h1}}, + {DQ_WIDTH/4{4'hB}}}; + end + + 2'b11: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hC}}}; + end + endcase + end else if (!prbs_rdlvl_done && ~phy_data_full) begin + phy_wrdata <= #TCQ prbs_o; + // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in + // prbs_o being concatenated 8 times resulting in DQ_WIDTH + /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, + {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, + {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, + {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ + end else if (!wrcal_done) begin + case (wrcal_pat_cnt) + 2'b00: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, + {DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}}}; + end + 2'b01: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, + {DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h5}}}; + end + 2'b10: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h1}}, + {DQ_WIDTH/4{4'hB}}}; + end + 2'b11: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, + {DQ_WIDTH/4{4'hD}}, + {DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h4}}}; + end + endcase + end + + end else if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 4)) begin: wrdq_div2_4to1_rdlvl_first + + always @(posedge clk) + if (~oclkdelay_calib_done) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; + else if (!rdlvl_stg1_done && ~phy_data_full) + // write different sequence for very + // first write to memory only. Used to help us differentiate + // if the writes are "early" or "on-time" during read leveling + if (first_rdlvl_pat_r) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, + {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; + else + // For all others, change the first two words written in order + // to differentiate the "early write" and "on-time write" + // readback patterns during read leveling + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, + {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; + else if (~(prbs_rdlvl_done || prbs_last_byte_done_r) && ~phy_data_full) + phy_wrdata <= #TCQ prbs_o; + // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in + // prbs_o being concatenated 8 times resulting in DQ_WIDTH + /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, + {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, + {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, + {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ + else if (!wrcal_done) + if (first_wrcal_pat_r) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, + {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; + else + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, + {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; + + + end else if (nCK_PER_CLK == 4) begin: wrdq_div1_4to1_wrcal_first + + always @(posedge clk) + if ((~oclkdelay_calib_done) && (DRAM_TYPE == "DDR3")) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; + else if ((!wrcal_done)&& (DRAM_TYPE == "DDR3")) begin + if (extend_cal_pat) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, + {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; + else if (first_wrcal_pat_r) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, + {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; + else + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, + {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; + end else if (!rdlvl_stg1_done && ~phy_data_full) begin + // write different sequence for very + // first write to memory only. Used to help us differentiate + // if the writes are "early" or "on-time" during read leveling + if (first_rdlvl_pat_r) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, + {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; + else + // For all others, change the first two words written in order + // to differentiate the "early write" and "on-time write" + // readback patterns during read leveling + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, + {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; + end else if (!prbs_rdlvl_done && ~phy_data_full) + phy_wrdata <= #TCQ prbs_o; + // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in + // prbs_o being concatenated 8 times resulting in DQ_WIDTH + /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, + {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, + {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, + {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ + else if (!complex_oclkdelay_calib_done && ~phy_data_full) + phy_wrdata <= #TCQ prbs_o; + end else begin: wrdq_div1_2to1_wrcal_first + + always @(posedge clk) + if ((~oclkdelay_calib_done)&& (DRAM_TYPE == "DDR3")) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, + {DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}}, + {DQ_WIDTH/4{4'h0}}}; + else if ((!wrcal_done) && (DRAM_TYPE == "DDR3"))begin + case (wrcal_pat_cnt) + 2'b00: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, + {DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}}}; + end + 2'b01: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, + {DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h5}}}; + end + 2'b10: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h1}}, + {DQ_WIDTH/4{4'hB}}}; + end + 2'b11: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, + {DQ_WIDTH/4{4'hD}}, + {DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h4}}}; + end + endcase + end else if (!rdlvl_stg1_done) begin + // The 16 words for stage 1 write data in 2:1 mode is written + // over 4 consecutive controller clock cycles. Note that write + // data follows phy_wrdata_en by one clock cycle + case (wrdata_pat_cnt) + 2'b00: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h3}}, + {DQ_WIDTH/4{4'h9}}}; + end + + 2'b01: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hC}}}; + end + + 2'b10: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h1}}, + {DQ_WIDTH/4{4'hB}}}; + end + + 2'b11: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hC}}}; + end + endcase + end else if (!prbs_rdlvl_done && ~phy_data_full) begin + phy_wrdata <= #TCQ prbs_o; + // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in + // prbs_o being concatenated 8 times resulting in DQ_WIDTH + /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, + {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, + {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, + {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ + end else if (!complex_oclkdelay_calib_done && ~phy_data_full) begin + phy_wrdata <= #TCQ prbs_o; + end + + end +endgenerate + + //*************************************************************************** + // Memory control/address + //*************************************************************************** + + + // Phases [2] and [3] are always deasserted for 4:1 mode + generate + if (nCK_PER_CLK == 4) begin: gen_div4_ca_tieoff + always @(posedge clk) begin + phy_ras_n[3:2] <= #TCQ 3'b11; + phy_cas_n[3:2] <= #TCQ 3'b11; + phy_we_n[3:2] <= #TCQ 3'b11; + end + end + endgenerate + + // Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging + // (4) auto refresh + // verilint STARC-2.7.3.3b off + generate + if (!(CWL_M % 2)) begin: even_cwl + always @(posedge clk) begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_REG_WRITE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT))begin + phy_ras_n[0] <= #TCQ 1'b0; + phy_ras_n[1] <= #TCQ 1'b1; + end else begin + phy_ras_n[0] <= #TCQ 1'b1; + phy_ras_n[1] <= #TCQ 1'b1; + end + end + + // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command + // (3) auto refresh + always @(posedge clk) begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_REG_WRITE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_REFRESH) || + (rdlvl_wr_rd && new_burst_r))begin + phy_cas_n[0] <= #TCQ 1'b0; + phy_cas_n[1] <= #TCQ 1'b1; + end else begin + phy_cas_n[0] <= #TCQ 1'b1; + phy_cas_n[1] <= #TCQ 1'b1; + end + end + // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only + // occur during read leveling), (3) Issuing ZQ Long Calib command, + // (4) Precharge + always @(posedge clk) begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_REG_WRITE) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE)|| + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (rdlvl_wr && new_burst_r))begin + phy_we_n[0] <= #TCQ 1'b0; + phy_we_n[1] <= #TCQ 1'b1; + end else begin + phy_we_n[0] <= #TCQ 1'b1; + phy_we_n[1] <= #TCQ 1'b1; + end + end + end else begin: odd_cwl + always @(posedge clk) begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_REG_WRITE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (init_state_r == INIT_REFRESH))begin + phy_ras_n[0] <= #TCQ 1'b1; + phy_ras_n[1] <= #TCQ 1'b0; + end else begin + phy_ras_n[0] <= #TCQ 1'b1; + phy_ras_n[1] <= #TCQ 1'b1; + end + end + // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command + // (3) auto refresh + always @(posedge clk) begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_REG_WRITE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_REFRESH) || + (rdlvl_wr_rd && new_burst_r))begin + phy_cas_n[0] <= #TCQ 1'b1; + phy_cas_n[1] <= #TCQ 1'b0; + end else begin + phy_cas_n[0] <= #TCQ 1'b1; + phy_cas_n[1] <= #TCQ 1'b1; + end + end + // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only + // occur during read leveling), (3) Issuing ZQ Long Calib command, + // (4) Precharge + always @(posedge clk) begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_REG_WRITE) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE)|| + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (rdlvl_wr && new_burst_r))begin + phy_we_n[0] <= #TCQ 1'b1; + phy_we_n[1] <= #TCQ 1'b0; + end else begin + phy_we_n[0] <= #TCQ 1'b1; + phy_we_n[1] <= #TCQ 1'b1; + end + end + end + endgenerate +// verilint STARC-2.7.3.3b on + + + // Assign calib_cmd for the command field in PHY_Ctl_Word + always @(posedge clk) begin + if (wr_level_dqs_asrt) begin + // Request to toggle DQS during write leveling + calib_cmd <= #TCQ 3'b001; + if (CWL_M % 2) begin // odd write latency + calib_data_offset_0 <= #TCQ CWL_M + 3; + calib_data_offset_1 <= #TCQ CWL_M + 3; + calib_data_offset_2 <= #TCQ CWL_M + 3; + calib_cas_slot <= #TCQ 2'b01; + end else begin // even write latency + calib_data_offset_0 <= #TCQ CWL_M + 2; + calib_data_offset_1 <= #TCQ CWL_M + 2; + calib_data_offset_2 <= #TCQ CWL_M + 2; + calib_cas_slot <= #TCQ 2'b00; + end + end else if (rdlvl_wr && new_burst_r) begin + // Write Command + calib_cmd <= #TCQ 3'b001; + if (CWL_M % 2) begin // odd write latency + calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; + calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; + calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; + calib_cas_slot <= #TCQ 2'b01; + end else begin // even write latency + calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; + calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; + calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; + calib_cas_slot <= #TCQ 2'b00; + end + end else if (rdlvl_rd && new_burst_r) begin + // Read Command + calib_cmd <= #TCQ 3'b011; + if (CWL_M % 2) + calib_cas_slot <= #TCQ 2'b01; + else + calib_cas_slot <= #TCQ 2'b00; + if (~pi_calib_done_r1) begin + calib_data_offset_0 <= #TCQ 6'd0; + calib_data_offset_1 <= #TCQ 6'd0; + calib_data_offset_2 <= #TCQ 6'd0; + end else if (~pi_dqs_found_done_r1) begin + calib_data_offset_0 <= #TCQ rd_data_offset_0; + calib_data_offset_1 <= #TCQ rd_data_offset_1; + calib_data_offset_2 <= #TCQ rd_data_offset_2; + end else begin + calib_data_offset_0 <= #TCQ rd_data_offset_ranks_0[6*chip_cnt_r+:6]; + calib_data_offset_1 <= #TCQ rd_data_offset_ranks_1[6*chip_cnt_r+:6]; + calib_data_offset_2 <= #TCQ rd_data_offset_ranks_2[6*chip_cnt_r+:6]; + end + end else begin + // Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge, + // Active, Refresh + calib_cmd <= #TCQ 3'b100; + calib_data_offset_0 <= #TCQ 6'd0; + calib_data_offset_1 <= #TCQ 6'd0; + calib_data_offset_2 <= #TCQ 6'd0; + if (CWL_M % 2) + calib_cas_slot <= #TCQ 2'b01; + else + calib_cas_slot <= #TCQ 2'b00; + end + end + + // Write Enable to PHY_Control FIFO always asserted + // No danger of this FIFO being Full with 4:1 sync clock ratio + // This is also the write enable to the command OUT_FIFO + always @(posedge clk) begin + if (rst) begin + calib_ctl_wren <= #TCQ 1'b0; + calib_cmd_wren <= #TCQ 1'b0; + calib_seq <= #TCQ 2'b00; + end else if (cnt_pwron_cke_done_r && phy_ctl_ready + && ~(phy_ctl_full || phy_cmd_full )) begin + calib_ctl_wren <= #TCQ 1'b1; + calib_cmd_wren <= #TCQ 1'b1; + calib_seq <= #TCQ calib_seq + 1; + end else begin + calib_ctl_wren <= #TCQ 1'b0; + calib_cmd_wren <= #TCQ 1'b0; + calib_seq <= #TCQ calib_seq; + end + end + + generate + genvar rnk_i; + for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk + always @(posedge clk) begin + if (rst) begin + mr2_r[rnk_i] <= #TCQ 2'b00; + mr1_r[rnk_i] <= #TCQ 3'b000; + end else begin + mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i]; + mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i]; + end + end + end + endgenerate + + // ODT assignment based on slot config and slot present + // For single slot systems slot_1_present input will be ignored + // Assuming component interfaces to be single slot systems + generate + if (nSLOTS == 1) begin: gen_single_slot_odt + always @(posedge clk) begin + if (rst) begin + tmp_mr2_r[1] <= #TCQ 2'b00; + tmp_mr2_r[2] <= #TCQ 2'b00; + tmp_mr2_r[3] <= #TCQ 2'b00; + tmp_mr1_r[1] <= #TCQ 3'b000; + tmp_mr1_r[2] <= #TCQ 3'b000; + tmp_mr1_r[3] <= #TCQ 3'b000; + phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; + phy_tmp_odt_r <= #TCQ 4'b0000; + phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; + end else begin + case ({slot_0_present[0],slot_0_present[1], + slot_0_present[2],slot_0_present[3]}) + // Single slot configuration with quad rank + // Assuming same behavior as single slot dual rank for now + // DDR2 does not have quad rank parts + 4'b1111: begin + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 RTT_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 RTT_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + phy_tmp_odt_r <= #TCQ 4'b0001; + // Chip Select assignments + phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) + ) +: nCS_PER_RANK] <= #TCQ 'b0; + end + + // Single slot configuration with single rank + 4'b1000: begin + phy_tmp_odt_r <= #TCQ 4'b0001; + if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin + phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0; + end else begin + phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; + end + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + ((cnt_init_mr_r == 2'd0) || (USE_ODT_PORT == 1)))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 RTT_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 RTT_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + + // Single slot configuration with dual rank + 4'b1100: begin + phy_tmp_odt_r <= #TCQ 4'b0001; + // Chip Select assignments + + phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) + ) +: nCS_PER_RANK] <= #TCQ 'b0; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + + default: begin + phy_tmp_odt_r <= #TCQ 4'b0001; + phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done)) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + endcase + end + end + end else if (nSLOTS == 2) begin: gen_dual_slot_odt + always @ (posedge clk) begin + if (rst) begin + tmp_mr2_r[1] <= #TCQ 2'b00; + tmp_mr2_r[2] <= #TCQ 2'b00; + tmp_mr2_r[3] <= #TCQ 2'b00; + tmp_mr1_r[1] <= #TCQ 3'b000; + tmp_mr1_r[2] <= #TCQ 3'b000; + tmp_mr1_r[3] <= #TCQ 3'b000; + phy_tmp_odt_r <= #TCQ 4'b0000; + phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; + phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; + end else begin + case ({slot_0_present[0],slot_0_present[1], + slot_1_present[0],slot_1_present[1]}) + // Two slot configuration, one slot present, single rank + 4'b10_00: begin + if (//wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + // odt turned on only during write + phy_tmp_odt_r <= #TCQ 4'b0001; + end + phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done)) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + 4'b00_10: begin + + //Rank1 ODT enabled + if (//wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + // odt turned on only during write + phy_tmp_odt_r <= #TCQ 4'b0001; + end + phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done)) begin + //Rank1 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank1 Rtt_NOM defaults to 120 ohms + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + // Two slot configuration, one slot present, dual rank + 4'b00_11: begin + if (//wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + // odt turned on only during write + phy_tmp_odt_r + <= #TCQ 4'b0001; + end + + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + 4'b11_00: begin + if (//wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + // odt turned on only during write + phy_tmp_odt_r <= #TCQ 4'b0001; + end + + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank1 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank1 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + // Two slot configuration, one rank per slot + 4'b10_10: begin + if(DRAM_TYPE == "DDR2")begin + if(chip_cnt_r == 2'b00)begin + phy_tmp_odt_r + <= #TCQ 4'b0010; //bit0 for rank0 + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0001; //bit0 for rank0 + end + end else begin + if((init_state_r == INIT_WRLVL_WAIT) || + (init_next_state == INIT_RDLVL_STG1_WRITE) || + (init_next_state == INIT_WRCAL_WRITE) || + (init_next_state == INIT_OCAL_CENTER_WRITE) || + (init_next_state == INIT_OCLKDELAY_WRITE)) + phy_tmp_odt_r <= #TCQ 4'b0011; // bit0 for rank0/1 (write) + else if ((init_next_state == INIT_PI_PHASELOCK_READS) || + (init_next_state == INIT_MPR_READ) || + (init_next_state == INIT_RDLVL_STG1_READ) || + (init_next_state == INIT_RDLVL_COMPLEX_READ) || + (init_next_state == INIT_RDLVL_STG2_READ) || + (init_next_state == INIT_OCLKDELAY_READ) || + (init_next_state == INIT_WRCAL_READ) || + (init_next_state == INIT_WRCAL_MULT_READS)) + phy_tmp_odt_r <= #TCQ 4'b0010; // bit0 for rank1 (rank 0 rd) + end + + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_WR == "60") ? 3'b001 : + (RTT_WR == "120") ? 3'b010 : + 3'b000; + //Rank1 Dynamic ODT disabled + tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011 : + 3'b000; + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011 : + 3'b000; + end + end + // Two Slots - One slot with dual rank and other with single rank + 4'b10_11: begin + + //Rank3 Rtt_NOM + tmp_mr1_r[2] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011 : + 3'b000; + tmp_mr2_r[2] <= #TCQ 2'b00; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + //Rank1 Dynamic ODT disabled + tmp_mr2_r[1] <= #TCQ 2'b00; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011 : + 3'b000; + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM after write leveling completes + tmp_mr1_r[1] <= #TCQ 3'b000; + end + //Slot1 Rank1 or Rank3 is being written + if(DRAM_TYPE == "DDR2")begin + if(chip_cnt_r == 2'b00)begin + phy_tmp_odt_r + <= #TCQ 4'b0010; + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0001; + end + end else begin + if (//wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + if (chip_cnt_r[0] == 1'b1) begin + phy_tmp_odt_r + <= #TCQ 4'b0011; + //Slot0 Rank0 is being written + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted + end + end else if ((init_state_r == INIT_RDLVL_STG1_READ) || + (init_state_r == INIT_RDLVL_COMPLEX_READ) || + (init_state_r == INIT_PI_PHASELOCK_READS) || + (init_state_r == INIT_RDLVL_STG2_READ) || + (init_state_r == INIT_OCLKDELAY_READ) || + (init_state_r == INIT_WRCAL_READ) || + (init_state_r == INIT_WRCAL_MULT_READS))begin + if (chip_cnt_r == 2'b00) begin + phy_tmp_odt_r + <= #TCQ 4'b0100; + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0001; + end + end + end + + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + + end + // Two Slots - One slot with dual rank and other with single rank + 4'b11_10: begin + + //Rank2 Rtt_NOM + tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : + (RTT_NOM2 == "120") ? 3'b010 : + (RTT_NOM2 == "20") ? 3'b100 : + (RTT_NOM2 == "30") ? 3'b101 : + (RTT_NOM2 == "40") ? 3'b011: + 3'b000; + tmp_mr2_r[2] <= #TCQ 2'b00; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + //Rank1 Dynamic ODT disabled + tmp_mr2_r[1] <= #TCQ 2'b00; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011: + 3'b000; + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + + if(DRAM_TYPE == "DDR2")begin + if(chip_cnt_r[1] == 1'b1)begin + phy_tmp_odt_r <= + #TCQ 4'b0001; + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0100; // rank 2 ODT asserted + end + end else begin + if (// wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + + if (chip_cnt_r[1] == 1'b1) begin + phy_tmp_odt_r + <= #TCQ 4'b0110; + end else begin + phy_tmp_odt_r <= + #TCQ 4'b0101; + end + end else if ((init_state_r == INIT_RDLVL_STG1_READ) || + (init_state_r == INIT_RDLVL_COMPLEX_READ) || + (init_state_r == INIT_PI_PHASELOCK_READS) || + (init_state_r == INIT_RDLVL_STG2_READ) || + (init_state_r == INIT_OCLKDELAY_READ) || + (init_state_r == INIT_WRCAL_READ) || + (init_state_r == INIT_WRCAL_MULT_READS)) begin + + if (chip_cnt_r[1] == 1'b1) begin + phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ 4'b0010; + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0100; + end + end + end + + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + end + // Two Slots - two ranks per slot + 4'b11_11: begin + //Rank2 Rtt_NOM + tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : + (RTT_NOM2 == "120") ? 3'b010 : + (RTT_NOM2 == "20") ? 3'b100 : + (RTT_NOM2 == "30") ? 3'b101 : + (RTT_NOM2 == "40") ? 3'b011 : + 3'b000; + //Rank3 Rtt_NOM + tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 : + (RTT_NOM3 == "120") ? 3'b010 : + (RTT_NOM3 == "20") ? 3'b100 : + (RTT_NOM3 == "30") ? 3'b101 : + (RTT_NOM3 == "40") ? 3'b011 : + 3'b000; + tmp_mr2_r[2] <= #TCQ 2'b00; + tmp_mr2_r[3] <= #TCQ 2'b00; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + //Rank1 Dynamic ODT disabled + tmp_mr2_r[1] <= #TCQ 2'b00; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM after write leveling completes + tmp_mr1_r[1] <= #TCQ 3'b000; + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + + if(DRAM_TYPE == "DDR2")begin + if(chip_cnt_r[1] == 1'b1)begin + phy_tmp_odt_r + <= #TCQ 4'b0001; + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0100; + end + end else begin + if (//wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + //Slot1 Rank1 or Rank3 is being written + if (chip_cnt_r[0] == 1'b1) begin + phy_tmp_odt_r + <= #TCQ 4'b0110; + //Slot0 Rank0 or Rank2 is being written + end else begin + phy_tmp_odt_r + <= #TCQ 4'b1001; + end + end else if ((init_state_r == INIT_RDLVL_STG1_READ) || + (init_state_r == INIT_RDLVL_COMPLEX_READ) || + (init_state_r == INIT_PI_PHASELOCK_READS) || + (init_state_r == INIT_RDLVL_STG2_READ) || + (init_state_r == INIT_OCLKDELAY_READ) || + (init_state_r == INIT_WRCAL_READ) || + (init_state_r == INIT_WRCAL_MULT_READS))begin + //Slot1 Rank1 or Rank3 is being read + if (chip_cnt_r[0] == 1'b1) begin + phy_tmp_odt_r + <= #TCQ 4'b0100; + //Slot0 Rank0 or Rank2 is being read + end else begin + phy_tmp_odt_r + <= #TCQ 4'b1000; + end + end + end + + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + end + default: begin + phy_tmp_odt_r <= #TCQ 4'b1111; + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done)) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + //Rank1 Dynamic ODT disabled + tmp_mr2_r[1] <= #TCQ 2'b00; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "60") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011 : + 3'b000; + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011 : + 3'b000; + end + end + endcase + end + end + end + endgenerate + + + // PHY only supports two ranks. + // calib_aux_out[0] is CKE for rank 0 and calib_aux_out[1] is ODT for rank 0 + // calib_aux_out[2] is CKE for rank 1 and calib_aux_out[3] is ODT for rank 1 + +generate +if(CKE_ODT_AUX == "FALSE") begin + if ((nSLOTS == 1) && (RANKS < 2)) begin + always @(posedge clk) + if (rst) begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; + calib_odt <= 2'b00 ; + end else begin + if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; + end else begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; + end + if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || + wrlvl_rank_done || wrlvl_rank_done_r1 || + (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin + calib_odt[0] <= #TCQ 1'b0; + calib_odt[1] <= #TCQ 1'b0; + end else if (((DRAM_TYPE == "DDR3") + ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) + && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt ) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || + (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || + complex_odt_ext || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_WRCAL_WRITE_READ) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + complex_ocal_odt_ext || + (init_state_r == INIT_OCLKDELAY_WRITE)|| + (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin + // Quad rank in a single slot + calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; + calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; + end else begin + calib_odt[0] <= #TCQ 1'b0; + calib_odt[1] <= #TCQ 1'b0; + end + end + end else if ((nSLOTS == 1) && (RANKS <= 2)) begin + always @(posedge clk) + if (rst) begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; + calib_odt <= 2'b00 ; + end else begin + if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; + end else begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; + end + if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || + wrlvl_rank_done_r2 || + (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin + calib_odt[0] <= #TCQ 1'b0; + calib_odt[1] <= #TCQ 1'b0; + end else if (((DRAM_TYPE == "DDR3") + ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) + && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt)|| + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || + (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || + complex_odt_ext || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_WRCAL_WRITE_READ) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + complex_ocal_odt_ext || + (init_state_r == INIT_OCLKDELAY_WRITE)|| + (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin + // Dual rank in a single slot + calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; + calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; + end else begin + calib_odt[0] <= #TCQ 1'b0; + calib_odt[1] <= #TCQ 1'b0; + end + end + end else if ((nSLOTS == 2) && (RANKS == 2)) begin + always @(posedge clk) + if (rst)begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; + calib_odt <= 2'b00 ; + end else begin + if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; + end else begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; + end + if (((DRAM_TYPE == "DDR2") && (RTT_NOM == "DISABLED")) || + ((DRAM_TYPE == "DDR3") && + (RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))) begin + calib_odt[0] <= #TCQ 1'b0; + calib_odt[1] <= #TCQ 1'b0; + end else if (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + // Quad rank in a single slot + if (nCK_PER_CLK == 2) begin + calib_odt[0] + <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; + calib_odt[1] + <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; + end else begin + calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; + calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; + end + // Turn on for idle rank during read if dynamic ODT is enabled in DDR3 + end else if(((DRAM_TYPE == "DDR3") && (RTT_WR != "OFF")) && + ((init_state_r == INIT_PI_PHASELOCK_READS) || + (init_state_r == INIT_MPR_READ) || + (init_state_r == INIT_RDLVL_STG1_READ) || + (init_state_r == INIT_RDLVL_COMPLEX_READ) || + (init_state_r == INIT_RDLVL_STG2_READ) || + (init_state_r == INIT_OCLKDELAY_READ) || + (init_state_r == INIT_WRCAL_READ) || + (init_state_r == INIT_WRCAL_MULT_READS))) begin + if (nCK_PER_CLK == 2) begin + calib_odt[0] + <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; + calib_odt[1] + <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; + end else begin + calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; + calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; + end + // disable well before next command and before disabling write leveling + end else if(cnt_cmd_done_m7_r || + (init_state_r == INIT_WRLVL_WAIT && ~wrlvl_odt)) + calib_odt <= #TCQ 2'b00; + end + end +end else begin//USE AUX OUTPUT for routing CKE and ODT. + if ((nSLOTS == 1) && (RANKS < 2)) begin + always @(posedge clk) + if (rst) begin + calib_aux_out <= #TCQ 4'b0000; + end else begin + if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin + calib_aux_out[0] <= #TCQ 1'b1; + calib_aux_out[2] <= #TCQ 1'b1; + end else begin + calib_aux_out[0] <= #TCQ 1'b0; + calib_aux_out[2] <= #TCQ 1'b0; + end + if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || + wrlvl_rank_done || wrlvl_rank_done_r1 || + (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin + calib_aux_out[1] <= #TCQ 1'b0; + calib_aux_out[3] <= #TCQ 1'b0; + end else if (((DRAM_TYPE == "DDR3") + ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) + && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE))) begin + // Quad rank in a single slot + calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; + calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; + end else begin + calib_aux_out[1] <= #TCQ 1'b0; + calib_aux_out[3] <= #TCQ 1'b0; + end + end + end else if ((nSLOTS == 1) && (RANKS <= 2)) begin + always @(posedge clk) + if (rst) begin + calib_aux_out <= #TCQ 4'b0000; + end else begin + if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin + calib_aux_out[0] <= #TCQ 1'b1; + calib_aux_out[2] <= #TCQ 1'b1; + end else begin + calib_aux_out[0] <= #TCQ 1'b0; + calib_aux_out[2] <= #TCQ 1'b0; + end + if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || + wrlvl_rank_done_r2 || + (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin + calib_aux_out[1] <= #TCQ 1'b0; + calib_aux_out[3] <= #TCQ 1'b0; + end else if (((DRAM_TYPE == "DDR3") + ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) + && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE))) begin + // Dual rank in a single slot + calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; + calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; + end else begin + calib_aux_out[1] <= #TCQ 1'b0; + calib_aux_out[3] <= #TCQ 1'b0; + end + end + end else if ((nSLOTS == 2) && (RANKS == 2)) begin + always @(posedge clk) + if (rst) + calib_aux_out <= #TCQ 4'b0000; + else begin + if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin + calib_aux_out[0] <= #TCQ 1'b1; + calib_aux_out[2] <= #TCQ 1'b1; + end else begin + calib_aux_out[0] <= #TCQ 1'b0; + calib_aux_out[2] <= #TCQ 1'b0; + end + if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || + wrlvl_rank_done_r2 || + (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin + calib_aux_out[1] <= #TCQ 1'b0; + calib_aux_out[3] <= #TCQ 1'b0; + end else if (((DRAM_TYPE == "DDR3") + ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) + && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE))) begin + // Quad rank in a single slot + if (nCK_PER_CLK == 2) begin + calib_aux_out[1] + <= #TCQ (!calib_aux_out[1]) ? phy_tmp_odt_r[0] : 1'b0; + calib_aux_out[3] + <= #TCQ (!calib_aux_out[3]) ? phy_tmp_odt_r[1] : 1'b0; + end else begin + calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; + calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; + end + end else begin + calib_aux_out[1] <= #TCQ 1'b0; + calib_aux_out[3] <= #TCQ 1'b0; + end + end + end +end +endgenerate + + //***************************************************************** + // memory address during init + //***************************************************************** + + always @(posedge clk) + phy_data_full_r <= #TCQ phy_data_full; +// verilint STARC-2.7.3.3b off + always @(*)begin + // Bus 0 for address/bank never used + address_w = 'b0; + bank_w = 'b0; + if ((init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_DDR2_PRECHARGE)) begin + // Set A10=1 for ZQ long calibration or Precharge All + address_w = 'b0; + address_w[10] = 1'b1; + bank_w = 'b0; + end else if (init_state_r == INIT_WRLVL_START) begin + // Enable wrlvl in MR1 + bank_w[1:0] = 2'b01; + address_w = load_mr1[ROW_WIDTH-1:0]; + address_w[2] = mr1_r[chip_cnt_r][0]; + address_w[6] = mr1_r[chip_cnt_r][1]; + address_w[9] = mr1_r[chip_cnt_r][2]; + address_w[7] = 1'b1; + end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin + // Finished with write leveling, disable wrlvl in MR1 + // For single rank disable Rtt_Nom + bank_w[1:0] = 2'b01; + address_w = load_mr1[ROW_WIDTH-1:0]; + address_w[2] = mr1_r[chip_cnt_r][0]; + address_w[6] = mr1_r[chip_cnt_r][1]; + address_w[9] = mr1_r[chip_cnt_r][2]; + end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin + // Set RTT_WR in MR2 after write leveling disabled + bank_w[1:0] = 2'b10; + address_w = load_mr2[ROW_WIDTH-1:0]; + address_w[10:9] = mr2_r[chip_cnt_r]; + end else if (init_state_r == INIT_MPR_READ) begin + address_w = 'b0; + bank_w = 'b0; + end else if (init_state_r == INIT_MPR_RDEN) begin + // Enable MPR read with LMR3 and A2=1 + bank_w[BANK_WIDTH-1:0] = 'd3; + address_w = {ROW_WIDTH{1'b0}}; + address_w[2] = 1'b1; + end else if (init_state_r == INIT_MPR_DISABLE) begin + // Disable MPR read with LMR3 and A2=0 + bank_w[BANK_WIDTH-1:0] = 'd3; + address_w = {ROW_WIDTH{1'b0}}; + end else if ((init_state_r == INIT_REG_WRITE)& + (DRAM_TYPE == "DDR3"))begin + // bank_w is assigned a 3 bit value. In some + // DDR2 cases there will be only two bank bits. + //Qualifying the condition with DDR3 + bank_w = 'b0; + address_w = 'b0; + case (reg_ctrl_cnt_r) + 4'h1:begin + address_w[4:0] = REG_RC1[4:0]; + bank_w = REG_RC1[7:5]; + end + 4'h2: address_w[4:0] = REG_RC2[4:0]; + 4'h3: begin + address_w[4:0] = REG_RC3[4:0]; + bank_w = REG_RC3[7:5]; + end + 4'h4: begin + address_w[4:0] = REG_RC4[4:0]; + bank_w = REG_RC4[7:5]; + end + 4'h5: begin + address_w[4:0] = REG_RC5[4:0]; + bank_w = REG_RC5[7:5]; + end + 4'h6: begin + address_w[4:0] = REG_RC10[4:0]; + bank_w = REG_RC10[7:5]; + end + 4'h7: begin + address_w[4:0] = REG_RC11[4:0]; + bank_w = REG_RC11[7:5]; + end + default: address_w[4:0] = REG_RC0[4:0]; + endcase + end else if (init_state_r == INIT_LOAD_MR) begin + // If loading mode register, look at cnt_init_mr to determine + // which MR is currently being programmed + address_w = 'b0; + bank_w = 'b0; + if(DRAM_TYPE == "DDR3")begin + if(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done)begin + // end of the calibration programming correct + // burst length + if (TEST_AL == "0") begin + bank_w[1:0] = 2'b00; + address_w = load_mr0[ROW_WIDTH-1:0]; + address_w[8]= 1'b0; //Don't reset DLL + end else begin + // programming correct AL value + bank_w[1:0] = 2'b01; + address_w = load_mr1[ROW_WIDTH-1:0]; + if (TEST_AL == "CL-1") + address_w[4:3]= 2'b01; // AL="CL-1" + else + address_w[4:3]= 2'b10; // AL="CL-2" + end + end else begin + case (cnt_init_mr_r) + INIT_CNT_MR2: begin + bank_w[1:0] = 2'b10; + address_w = load_mr2[ROW_WIDTH-1:0]; + address_w[10:9] = mr2_r[chip_cnt_r]; + end + INIT_CNT_MR3: begin + bank_w[1:0] = 2'b11; + address_w = load_mr3[ROW_WIDTH-1:0]; + end + INIT_CNT_MR1: begin + bank_w[1:0] = 2'b01; + address_w = load_mr1[ROW_WIDTH-1:0]; + address_w[2] = mr1_r[chip_cnt_r][0]; + address_w[6] = mr1_r[chip_cnt_r][1]; + address_w[9] = mr1_r[chip_cnt_r][2]; + end + INIT_CNT_MR0: begin + bank_w[1:0] = 2'b00; + address_w = load_mr0[ROW_WIDTH-1:0]; + // fixing it to BL8 for calibration + address_w[1:0] = 2'b00; + end + default: begin + bank_w = {BANK_WIDTH{1'bx}}; + address_w = {ROW_WIDTH{1'bx}}; + end + endcase + end + end else begin // DDR2 + case (cnt_init_mr_r) + INIT_CNT_MR2: begin + if(~ddr2_refresh_flag_r)begin + bank_w[1:0] = 2'b10; + address_w = load_mr2[ROW_WIDTH-1:0]; + end else begin // second set of lm commands + bank_w[1:0] = 2'b00; + address_w = load_mr0[ROW_WIDTH-1:0]; + address_w[8]= 1'b0; + //MRS command without resetting DLL + end + end + INIT_CNT_MR3: begin + if(~ddr2_refresh_flag_r)begin + bank_w[1:0] = 2'b11; + address_w = load_mr3[ROW_WIDTH-1:0]; + end else begin // second set of lm commands + bank_w[1:0] = 2'b00; + address_w = load_mr0[ROW_WIDTH-1:0]; + address_w[8]= 1'b0; + //MRS command without resetting DLL. Repeted again + // because there is an extra state. + end + end + INIT_CNT_MR1: begin + bank_w[1:0] = 2'b01; + if(~ddr2_refresh_flag_r)begin + address_w = load_mr1[ROW_WIDTH-1:0]; + end else begin // second set of lm commands + address_w = load_mr1[ROW_WIDTH-1:0]; + address_w[9:7] = 3'b111; + //OCD default state + end + end + INIT_CNT_MR0: begin + if(~ddr2_refresh_flag_r)begin + bank_w[1:0] = 2'b00; + address_w = load_mr0[ROW_WIDTH-1:0]; + end else begin // second set of lm commands + bank_w[1:0] = 2'b01; + address_w = load_mr1[ROW_WIDTH-1:0]; + if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin + // always disable odt for rank 1 and rank 3 as per SPEC + address_w[2] = 'b0; + address_w[6] = 'b0; + end + //OCD exit + end + end + default: begin + bank_w = {BANK_WIDTH{1'bx}}; + address_w = {ROW_WIDTH{1'bx}}; + end + endcase + end + end else if ( ~prbs_rdlvl_done && ((init_state_r == INIT_PI_PHASELOCK_READS) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_RDLVL_STG1_READ) || + (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin + // Writing and reading PRBS pattern for read leveling stage 1 + // Need to support burst length 4 or 8. PRBS pattern will be + // written to entire row and read back from the same row repeatedly + bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; + address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; + if (((stg1_wr_rd_cnt == NUM_STG1_WR_RD) && ~rdlvl_stg1_done) || (stg1_wr_rd_cnt == 'd127) || + ((stg1_wr_rd_cnt == 'd22) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin + address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; + end else if (phy_data_full_r || (!new_burst_r)) + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; + else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin + if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ) )// || + // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) + address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; + else + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; + end + //need to add address for complex oclkdelay calib + end else if (prbs_rdlvl_done && ((init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin + bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; + address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; + if ((stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd30) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin + address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; + end else if (phy_data_full_r || (!new_burst_r)) + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; + else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin + if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (init_state_r1 != INIT_RDLVL_STG1_WRITE) ) + // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) + address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; + else + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; + end + + end else if ((init_state_r == INIT_OCLKDELAY_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_READ)) begin + bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; + address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; + if (oclk_wr_cnt == NUM_STG1_WR_RD) + address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; + else if (phy_data_full_r || (!new_burst_r)) + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; + else if ((oclk_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; + end else if ((init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_WRCAL_READ)) begin + bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; + address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; + if (wrcal_wr_cnt == NUM_STG1_WR_RD) + address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; + else if (phy_data_full_r || (!new_burst_r)) + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; + else if ((wrcal_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; + end else if ((init_state_r == INIT_WRCAL_MULT_READS) || + (init_state_r == INIT_RDLVL_STG2_READ)) begin + // when writing or reading back training pattern for read leveling stage2 + // need to support burst length of 4 or 8. This may mean issuing + // multiple commands to cover the entire range of addresses accessed + // during read leveling. + // Hard coding A[12] to 1 so that it will always be burst length of 8 + // for DDR3. Does not have any effect on DDR2. + bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; + address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; + address_w[COL_WIDTH-1:0] = + {CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000}; + address_w[12] = 1'b1; + end else if ((init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT)) begin + + bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; + //if (stg1_wr_rd_cnt == 'd22) + // address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0] + 1; + //else + address_w = prbs_rdlvl_done ? CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt_ocal : + CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt; + end else begin + bank_w = {BANK_WIDTH{1'bx}}; + address_w = {ROW_WIDTH{1'bx}}; + end + end + // verilint STARC-2.7.3.3b on + // registring before sending out + generate + genvar r,s; + if ((DRAM_TYPE != "DDR3") || (CA_MIRROR != "ON")) begin: gen_no_mirror + for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: div_clk_loop + always @(posedge clk) begin + phy_address[(r*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w; + phy_bank[(r*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w; + end + end + end else begin: gen_mirror + // Control/addressing mirroring (optional for DDR3 dual rank DIMMs) + // Mirror for the 2nd rank only. Logic needs to be enhanced to account + // for multiple slots, currently only supports one slot, 2-rank config + + for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_ba_div_clk_loop + for (s = 0; s < BANK_WIDTH; s = s + 1) begin: gen_ba + + always @(posedge clk) + if (chip_cnt_r == 2'b00) begin + phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[s]; + end else begin + phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[(s == 0) ? 1 : ((s == 1) ? 0 : s)]; + end + + end + end + + for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_addr_div_clk_loop + for (s = 0; s < ROW_WIDTH; s = s + 1) begin: gen_addr + always @(posedge clk) + if (chip_cnt_r == 2'b00) begin + phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[s]; + end else begin + phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[ + (s == 3) ? 4 : + ((s == 4) ? 3 : + ((s == 5) ? 6 : + ((s == 6) ? 5 : + ((s == 7) ? 8 : + ((s == 8) ? 7 : s)))))]; + end + end + end + + end + endgenerate + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_cntlr.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_cntlr.v new file mode 100644 index 0000000..a27d7ce --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_cntlr.v @@ -0,0 +1,285 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_v4_0_phy_ocd_cntlr.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Steps through the major sections of the output clock +// delay algorithm. Enabling various subblocks at the right time. +// +// Steps through each byte of the interface. +// +// Implements both the simple and complex data pattern. +// +// for each byte in interface +// begin +// Limit +// Scan - which includes DQS centering +// Precharge +// end +// set _wrlvl and _done equal to one +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_ocd_cntlr # + (parameter TCQ = 100, + parameter DQS_CNT_WIDTH = 3, + parameter DQS_WIDTH = 8) + (/*AUTOARG*/ + // Outputs + wrlvl_final, complex_wrlvl_final, oclk_init_delay_done, + ocd_prech_req, lim_start, complex_oclkdelay_calib_done, + oclkdelay_calib_done, phy_rddata_en_1, phy_rddata_en_2, + phy_rddata_en_3, ocd_cntlr2stg2_dec, oclkdelay_calib_cnt, + reset_scan, + // Inputs + clk, rst, prech_done, oclkdelay_calib_start, + complex_oclkdelay_calib_start, lim_done, phy_rddata_en, + po_counter_read_val, po_rdy, scan_done + ); + + localparam ONE = 1; + + input clk; + input rst; + + output wrlvl_final, complex_wrlvl_final; + reg wrlvl_final_ns, wrlvl_final_r, complex_wrlvl_final_ns, complex_wrlvl_final_r; + always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final_ns; + always @(posedge clk) complex_wrlvl_final_r <= #TCQ complex_wrlvl_final_ns; + assign wrlvl_final = wrlvl_final_r; + assign complex_wrlvl_final = complex_wrlvl_final_r; + + // Completed initial delay increment + output oclk_init_delay_done; // may not need this... maybe for fast cal mode. + assign oclk_init_delay_done = 1'b1; + + // Precharge done status from ddr_phy_init + input prech_done; + reg ocd_prech_req_ns, ocd_prech_req_r; + always @(posedge clk) ocd_prech_req_r <= #TCQ ocd_prech_req_ns; + output ocd_prech_req; + assign ocd_prech_req = ocd_prech_req_r; + + input oclkdelay_calib_start, complex_oclkdelay_calib_start; + input lim_done; + + reg lim_start_ns, lim_start_r; + always @(posedge clk) lim_start_r <= #TCQ lim_start_ns; + output lim_start; + assign lim_start = lim_start_r; + + reg complex_oclkdelay_calib_done_ns, complex_oclkdelay_calib_done_r; + always @(posedge clk) complex_oclkdelay_calib_done_r <= #TCQ complex_oclkdelay_calib_done_ns; + output complex_oclkdelay_calib_done; + assign complex_oclkdelay_calib_done = complex_oclkdelay_calib_done_r; + + reg oclkdelay_calib_done_ns, oclkdelay_calib_done_r; + always @(posedge clk) oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done_ns; + output oclkdelay_calib_done; + assign oclkdelay_calib_done = oclkdelay_calib_done_r; + + input phy_rddata_en; + reg prde_r1, prde_r2; + always @(posedge clk) prde_r1 <= #TCQ phy_rddata_en; + always @(posedge clk) prde_r2 <= #TCQ prde_r1; + wire prde = complex_oclkdelay_calib_start ? prde_r2 : phy_rddata_en; + + reg phy_rddata_en_r1, phy_rddata_en_r2, phy_rddata_en_r3; + always @(posedge clk) phy_rddata_en_r1 <= #TCQ prde; + always @(posedge clk) phy_rddata_en_r2 <= #TCQ phy_rddata_en_r1; + always @(posedge clk) phy_rddata_en_r3 <= #TCQ phy_rddata_en_r2; + output phy_rddata_en_1, phy_rddata_en_2, phy_rddata_en_3; + assign phy_rddata_en_1 = phy_rddata_en_r1; + assign phy_rddata_en_2 = phy_rddata_en_r2; + assign phy_rddata_en_3 = phy_rddata_en_r3; + + input [8:0] po_counter_read_val; + reg ocd_cntlr2stg2_dec_r; + output ocd_cntlr2stg2_dec; + assign ocd_cntlr2stg2_dec = ocd_cntlr2stg2_dec_r; + input po_rdy; + + reg [3:0] po_rd_wait_ns, po_rd_wait_r; + always @(posedge clk) po_rd_wait_r <= #TCQ po_rd_wait_ns; + + reg [DQS_CNT_WIDTH-1:0] byte_ns, byte_r; + always @(posedge clk) byte_r <= #TCQ byte_ns; + output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + assign oclkdelay_calib_cnt = {1'b0, byte_r}; + + reg reset_scan_ns, reset_scan_r; + always @(posedge clk) reset_scan_r <= #TCQ reset_scan_ns; + output reset_scan; + assign reset_scan = reset_scan_r; + input scan_done; + + reg [2:0] sm_ns, sm_r; + always @(posedge clk) sm_r <= #TCQ sm_ns; + + // Primary state machine. + + always @(*) begin + + // Default next state assignments. + + byte_ns = byte_r; + complex_wrlvl_final_ns = complex_wrlvl_final_r; + lim_start_ns = lim_start_r; + oclkdelay_calib_done_ns = oclkdelay_calib_done_r; + complex_oclkdelay_calib_done_ns = complex_oclkdelay_calib_done_r; + ocd_cntlr2stg2_dec_r = 1'b0; + po_rd_wait_ns = po_rd_wait_r; + if (|po_rd_wait_r) po_rd_wait_ns = po_rd_wait_r - 4'b1; + reset_scan_ns = reset_scan_r; + wrlvl_final_ns = wrlvl_final_r; + sm_ns = sm_r; + ocd_prech_req_ns= 1'b0; + + if (rst == 1'b1) begin + + // RESET next states + complex_oclkdelay_calib_done_ns = 1'b0; + complex_wrlvl_final_ns = 1'b0; + sm_ns = /*AK("READY")*/3'd0; + lim_start_ns = 1'b0; + oclkdelay_calib_done_ns = 1'b0; + reset_scan_ns = 1'b1; + wrlvl_final_ns = 1'b0; + end else + + // State based actions and next states. + case (sm_r) + /*AL("READY")*/3'd0: begin + byte_ns = {DQS_CNT_WIDTH{1'b0}}; + if (oclkdelay_calib_start && ~oclkdelay_calib_done_r || + complex_oclkdelay_calib_start && ~complex_oclkdelay_calib_done_r) + begin + sm_ns = /*AK("LIMIT_START")*/3'd1; + lim_start_ns = 1'b1; + end + end + + /*AL("LIMIT_START")*/3'd1: + sm_ns = /*AK("LIMIT_WAIT")*/3'd2; + + /*AL("LIMIT_WAIT")*/3'd2:begin + if (lim_done) begin + lim_start_ns = 1'b0; + sm_ns = /*AK("SCAN")*/3'd3; + reset_scan_ns = 1'b0; + end + end + + /*AL("SCAN")*/3'd3:begin + if (scan_done) begin + reset_scan_ns = 1'b1; + sm_ns = /*AK("COMPUTE")*/3'd4; + end + end + + /*AL("COMPUTE")*/3'd4:begin + sm_ns = /*AK("PRECHARGE")*/3'd5; + ocd_prech_req_ns = 1'b1; + end + + /*AL("PRECHARGE")*/3'd5:begin + if (prech_done) sm_ns = /*AK("DONE")*/3'd6; + end + + /*AL("DONE")*/3'd6:begin + byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0]; + if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin + byte_ns = {DQS_CNT_WIDTH{1'b0}}; + po_rd_wait_ns = 4'd8; + sm_ns = /*AK("STG2_2_ZERO")*/3'd7; + end else begin + sm_ns = /*AK("LIMIT_START")*/3'd1; + lim_start_ns = 1'b1; + end + end + + /*AL("STG2_2_ZERO")*/3'd7: + if (~|po_rd_wait_r && po_rdy) + if (|po_counter_read_val[5:0]) ocd_cntlr2stg2_dec_r = 1'b1; + else begin + if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin + sm_ns = /*AK("READY")*/3'd0; + oclkdelay_calib_done_ns= 1'b1; + wrlvl_final_ns = 1'b1; + if (complex_oclkdelay_calib_start) begin + complex_oclkdelay_calib_done_ns = 1'b1; + complex_wrlvl_final_ns = 1'b1; + end + end else begin + byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0]; + po_rd_wait_ns = 4'd8; + end + end // else: !if(|po_counter_read_val[5:0]) + + endcase // case (sm_r) + end // always @ begin + +endmodule // mig_7series_v4_0_ddr_phy_ocd_cntlr + +// Local Variables: +// verilog-autolabel-prefix: "3'd" +// End: diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_data.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_data.v new file mode 100644 index 0000000..b82deb8 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_data.v @@ -0,0 +1,231 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_v4_0_phy_ocd_data.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Data comparison for both "non-complex" and "complex" data. +// +// Depending on complex_oclkdelay_calib_start, data provided on the phy_rddata +// bus is compared against a fixed ones and zeros pattern, or against data +// provided on the prob_o bus. +// +// In the case of complex data, the phy_rddata data is delayed by two +// clocks to match up with the prbs_o data. +// +// For 4:1 mode, in each fabric clock, a complete DRAM burst may be delivered. +// A DRAM burst is 8 times the width of the DQ bus. For an 8 byte DQ +// bus, 64 bytes are delivered on each clock. +// +// In 2:1 mode the DRAM burst is delivered on two fabric clocks. For +// an 8 byte bus, 32 bytes are delivered with each fabric clock. +// +// For the most part, this block does not use phy_rddata_en. It delivers +// its results and depends on downstream logic to know when its valid. +// +// phy_rddata_en is used for the PRBS compares when the last line of data +// needs to be carried over to a subsequent line. +// +// Since we work on a byte at a time, the comparison only works on +// one byte of the DQ bus at a time. The oclkdelay_calib_cnt field is used to +// select the proper 8 bytes out of both the phy_rddata and prob_o streams. +// +// Comparisons are computed for "zero" or "rise" data, and "oneeighty" or +// "fall" data. The "oneeighty" compares assumes the rising edge clock is +// landing in the oneeighty data. +// +// For the simple data, we don't need to worry about first byte or last +// byte conditions because the sampled data is taken from the middle +// of a 4 burst segment. +// +// The complex (or PRBS) data starts and stops. And we need to be +// careful about ignoring compares that might be using invalid latched +// data. The PRBS generator provides prbs_ignore_first_byte and +// prbs_ignore_last_bytes. The comparison block is procedural. It +// first compares across the entire line, then comes back and overwrites +// any byte compare results as indicated by the _ignore_ wires. +// +// The compares generate an eight bit vector, one for each byte. The +// final step is to bitwise AND this eight bit vector. We end up +// with two sets of two bits. Zero and oneeighty for the fixed pattern +// and the prbs. +// +// complex_oclkdelay_calib_start is used to +// select between the fixed and prbs compares. The final output +// is a two bit match bus. +// +// There is a deprecated feature to mask the compare for any byte. +// +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_ocd_data # + (parameter TCQ = 100, + parameter nCK_PER_CLK = 4, + parameter DQS_CNT_WIDTH = 3, + parameter DQ_WIDTH = 64) + (/*AUTOARG*/ + // Outputs + match, + // Inputs + clk, rst, complex_oclkdelay_calib_start, phy_rddata, prbs_o, + oclkdelay_calib_cnt, prbs_ignore_first_byte, prbs_ignore_last_bytes, + phy_rddata_en_1 + ); + + localparam [7:0] OCAL_DQ_MASK = 8'b0000_0000; + + input clk; + input rst; + + input complex_oclkdelay_calib_start; + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata; + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; + input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + + reg [DQ_WIDTH-1:0] word, word_shifted; + + reg [63:0] data_bytes_ns, data_bytes_r, data_bytes_r1, data_bytes_r2, prbs_bytes_ns, prbs_bytes_r; + always @(posedge clk) data_bytes_r <= #TCQ data_bytes_ns; + always @(posedge clk) data_bytes_r1 <= #TCQ data_bytes_r; + always @(posedge clk) data_bytes_r2 <= #TCQ data_bytes_r1; + always @(posedge clk) prbs_bytes_r <= #TCQ prbs_bytes_ns; + + input prbs_ignore_first_byte, prbs_ignore_last_bytes; + reg prbs_ignore_first_byte_r, prbs_ignore_last_bytes_r; + always @(posedge clk) prbs_ignore_first_byte_r <= #TCQ prbs_ignore_first_byte; + always @(posedge clk) prbs_ignore_last_bytes_r <= #TCQ prbs_ignore_last_bytes; + + input phy_rddata_en_1; + reg [7:0] last_byte_r; + wire [63:0] data_bytes = complex_oclkdelay_calib_start ? data_bytes_r2 : data_bytes_r; + + wire [7:0] last_byte_ns; + generate if (nCK_PER_CLK == 4) begin + assign last_byte_ns = phy_rddata_en_1 ? data_bytes[63:56] : last_byte_r; + end else begin + assign last_byte_ns = phy_rddata_en_1 ? data_bytes[31:24] : last_byte_r; + end endgenerate + always @(posedge clk) last_byte_r <= #TCQ last_byte_ns; + + reg second_half_ns, second_half_r; + always @(posedge clk) second_half_r <= #TCQ second_half_ns; + always @(*) begin + second_half_ns = second_half_r; + if (rst) second_half_ns = 1'b0; + else second_half_ns = phy_rddata_en_1 ^ second_half_r; + end + + reg [7:0] comp0, comp180, prbs0, prbs180; + + integer ii; + always @(*) begin + comp0 = 8'hff; + comp180 = 8'hff; + prbs0 = 8'hff; + prbs180 = 8'hff; + data_bytes_ns = 64'b0; + prbs_bytes_ns = 64'b0; + for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1) + begin + word = phy_rddata[ii*DQ_WIDTH+:DQ_WIDTH]; + word_shifted = word >> oclkdelay_calib_cnt*8; + data_bytes_ns[ii*8+:8] = word_shifted[7:0]; + + word = prbs_o[ii*DQ_WIDTH+:DQ_WIDTH]; + word_shifted = word >> oclkdelay_calib_cnt*8; + prbs_bytes_ns[ii*8+:8] = word_shifted[7:0]; + + comp0[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'hff : 8'h00); + comp180[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'h00 : 8'hff); + + prbs0[ii] = data_bytes[ii*8+:8] == prbs_bytes_r[ii*8+:8]; + end // for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1) + prbs180[0] = last_byte_r == prbs_bytes_r[7:0]; + for (ii=1; ii<2*nCK_PER_CLK; ii=ii+1) + prbs180[ii] = data_bytes[(ii-1)*8+:8] == prbs_bytes_r[ii*8+:8]; + if (nCK_PER_CLK == 4) begin + if (prbs_ignore_last_bytes_r) begin + prbs0[7:6] = 2'b11; + prbs180[7] = 1'b1; + end + if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1; + end else begin + if (second_half_r) begin + if (prbs_ignore_last_bytes_r) begin + prbs0[3:2] = 2'b11; + prbs180[3] = 1'b1; + end + end else if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1; + end // else: !if(nCK_PER_CLK == 4) + end // always @ (*) + + wire [7:0] comp0_masked = comp0 | OCAL_DQ_MASK; + wire [7:0] comp180_masked = comp180 | OCAL_DQ_MASK; + wire [7:0] prbs0_masked = prbs0 | OCAL_DQ_MASK; + wire [7:0] prbs180_masked = prbs180 | OCAL_DQ_MASK; + + output [1:0] match; + assign match = complex_oclkdelay_calib_start ? {&prbs180_masked, &prbs0_masked} : {&comp180_masked , &comp0_masked}; + + +endmodule // mig_7series_v4_0_ddr_phy_ocd_data + diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_edge.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_edge.v new file mode 100644 index 0000000..351f121 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_edge.v @@ -0,0 +1,231 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_v4_0_phy_ocd_edge.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Detects and stores edges as the test pattern is scanned via +// manipulating the phaser out stage 3 taps. +// +// Scanning always proceeds from the left to the right. For more +// on the scanning algorithm, see the _po_cntlr block. +// +// Four scan results are reported. The edges at fuzz2zero, +// zero2fuzz, fuzz2oneeighty, and oneeighty2fuzz. Each edge +// has a 6 bit stg3 tap value and a valid bit. The valid bits +// are reset before the scan starts. +// +// Once reset_scan is set low, this block waits for the first +// samp_done while scanning_right. This marks the left end +// of the scan, and initializes prev_samp_r with samp_result and +// sets the prev_samp_r valid bit to one. +// +// At each subesquent samp_done, the previous samp is compared +// to the current samp_result. The case statement details how +// edges are identified. +// +// Original design assumed fuzz between valid regions. Design +// has been updated to tolerate transitions from zero to oneeight +// and vice-versa without fuzz in between. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_ocd_edge # + (parameter TCQ = 100) + (/*AUTOARG*/ + // Outputs + scan_right, z2f, f2z, o2f, f2o, zero2fuzz, fuzz2zero, + oneeighty2fuzz, fuzz2oneeighty, + // Inputs + clk, samp_done, phy_rddata_en_2, reset_scan, scanning_right, + samp_result, stg3 + ); + + + localparam [1:0] NULL = 2'b11, + FUZZ = 2'b00, + ONEEIGHTY = 2'b10, + ZERO = 2'b01; + + input clk; + + input samp_done; + input phy_rddata_en_2; + wire samp_valid = samp_done && phy_rddata_en_2; + + input reset_scan; + + input scanning_right; + + reg prev_samp_valid_ns, prev_samp_valid_r; + always @(posedge clk) prev_samp_valid_r <= #TCQ prev_samp_valid_ns; + always @(*) begin + prev_samp_valid_ns = prev_samp_valid_r; + if (reset_scan) prev_samp_valid_ns = 1'b0; + else if (samp_valid) prev_samp_valid_ns = 1'b1; + end + + input [1:0] samp_result; + + reg [1:0] prev_samp_ns, prev_samp_r; + always @(posedge clk) prev_samp_r <= #TCQ prev_samp_ns; + always @(*) + if (samp_valid) prev_samp_ns = samp_result; + else prev_samp_ns = prev_samp_r; + + reg scan_right_ns, scan_right_r; + always @(posedge clk) scan_right_r <= #TCQ scan_right_ns; + output scan_right; + assign scan_right = scan_right_r; + + input [5:0] stg3; + + reg z2f_ns, z2f_r, f2z_ns, f2z_r, o2f_ns, o2f_r, f2o_ns, f2o_r; + always @(posedge clk) z2f_r <= #TCQ z2f_ns; + always @(posedge clk) f2z_r <= #TCQ f2z_ns; + always @(posedge clk) o2f_r <= #TCQ o2f_ns; + always @(posedge clk) f2o_r <= #TCQ f2o_ns; + + output z2f, f2z, o2f, f2o; + assign z2f = z2f_r; + assign f2z = f2z_r; + assign o2f = o2f_r; + assign f2o = f2o_r; + + reg [5:0] zero2fuzz_ns, zero2fuzz_r, fuzz2zero_ns, fuzz2zero_r, + oneeighty2fuzz_ns, oneeighty2fuzz_r, fuzz2oneeighty_ns, fuzz2oneeighty_r; + always @(posedge clk) zero2fuzz_r <= #TCQ zero2fuzz_ns; + always @(posedge clk) fuzz2zero_r <= #TCQ fuzz2zero_ns; + always @(posedge clk) oneeighty2fuzz_r <= #TCQ oneeighty2fuzz_ns; + always @(posedge clk) fuzz2oneeighty_r <= #TCQ fuzz2oneeighty_ns; + + output [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty; + assign zero2fuzz = zero2fuzz_r; + assign fuzz2zero = fuzz2zero_r; + assign oneeighty2fuzz = oneeighty2fuzz_r; + assign fuzz2oneeighty = fuzz2oneeighty_r; + + always @(*) begin + z2f_ns = z2f_r; + f2z_ns = f2z_r; + o2f_ns = o2f_r; + f2o_ns = f2o_r; + zero2fuzz_ns = zero2fuzz_r; + fuzz2zero_ns = fuzz2zero_r; + oneeighty2fuzz_ns = oneeighty2fuzz_r; + fuzz2oneeighty_ns = fuzz2oneeighty_r; + scan_right_ns = 1'b0; + + if (reset_scan) begin + z2f_ns = 1'b0; + f2z_ns = 1'b0; + o2f_ns = 1'b0; + f2o_ns = 1'b0; + end + else if (samp_valid && prev_samp_valid_r) + case (prev_samp_r) + FUZZ : + if (scanning_right) begin + if (samp_result == ZERO) begin + fuzz2zero_ns = stg3; + f2z_ns = 1'b1; + end + if (samp_result == ONEEIGHTY) begin + fuzz2oneeighty_ns = stg3; + f2o_ns = 1'b1; + end + end + ZERO : begin + if (samp_result == FUZZ || samp_result == ONEEIGHTY) scan_right_ns = !scanning_right; + if (scanning_right) begin + if (samp_result == FUZZ) begin + zero2fuzz_ns = stg3 - 6'b1; + z2f_ns = 1'b1; + end + if (samp_result == ONEEIGHTY) begin + zero2fuzz_ns = stg3 - 6'b1; + z2f_ns = 1'b1; + fuzz2oneeighty_ns = stg3; + f2o_ns = 1'b1; + end + end + end + ONEEIGHTY : + if (scanning_right) begin + if (samp_result == FUZZ) begin + oneeighty2fuzz_ns = stg3 - 6'b1; + o2f_ns = 1'b1; + end + if (samp_result == ZERO) + if (f2o_r) begin + oneeighty2fuzz_ns = stg3 - 6'b1; + o2f_ns = 1'b1; + end else begin + fuzz2zero_ns = stg3; + f2z_ns = 1'b1; + end + + end // if (scanning_right) +// NULL : // Should never happen + endcase + end + +endmodule // mig_7series_v4_0_ddr_phy_ocd_edge diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_lim.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_lim.v new file mode 100644 index 0000000..8417cfb --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_lim.v @@ -0,0 +1,598 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_oclkdelay_cal.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3 +// delay +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_ocd_lim # + (parameter TAPCNTRWIDTH = 7, + parameter DQS_CNT_WIDTH = 3, + parameter DQS_WIDTH = 9, + parameter TCQ = 100, + parameter TAPSPERKCLK = 56, + parameter TDQSS_DEGREES = 60, + parameter BYPASS_COMPLEX_OCAL = "FALSE") + (/*AUTOARG*/ + // Outputs + lim2init_write_request, lim2init_prech_req, lim2poc_rdy, lim2poc_ktap_right, + lim2stg3_inc, lim2stg3_dec, lim2stg2_inc, lim2stg2_dec, lim_done, + lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, dbg_ocd_lim, + // Inputs + clk, rst, lim_start, po_rdy, poc2lim_rise_align_taps_lead, + poc2lim_rise_align_taps_trail, poc2lim_fall_align_taps_lead, + poc2lim_fall_align_taps_trail, oclkdelay_init_val, wl_po_fine_cnt, + simp_stg3_final_sel, oclkdelay_calib_done, poc2lim_detect_done, + prech_done, oclkdelay_calib_cnt + ); + + function [TAPCNTRWIDTH:0] mod_sub (input [TAPCNTRWIDTH-1:0] a, + input [TAPCNTRWIDTH-1:0] b, + input integer base); + begin + mod_sub = (a>=b) ? a-b : a+base[TAPCNTRWIDTH-1:0]-b; + end + endfunction // mod_sub + + input clk; + input rst; + + input lim_start; + input po_rdy; + input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_lead; + input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_trail; + input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_lead; + input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_trail; + input [5:0] oclkdelay_init_val; + input [5:0] wl_po_fine_cnt; + input [5:0] simp_stg3_final_sel; + input oclkdelay_calib_done; + input poc2lim_detect_done; + input prech_done; + input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + + + output lim2init_write_request; + output lim2init_prech_req; + output lim2poc_rdy; + output lim2poc_ktap_right; // I think this can be defaulted. + output lim2stg3_inc; + output lim2stg3_dec; + output lim2stg2_inc; + output lim2stg2_dec; + output lim_done; + output [5:0] lim2ocal_stg3_right_lim; + output [5:0] lim2ocal_stg3_left_lim; + output [255:0] dbg_ocd_lim; + + // Stage 3 taps can move an additional + or - 60 degrees from the write level position + // Convert 60 degrees to MMCM taps. 360/60=6. + //localparam real DIV_FACTOR = 360/TDQSS_DEGREES; + //localparam real TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR; + localparam DIV_FACTOR = 360/TDQSS_DEGREES; + localparam TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR; + localparam WAIT_CNT = 15; + + localparam IDLE = 14'b00_0000_0000_0001; + localparam INIT = 14'b00_0000_0000_0010; + localparam WAIT_WR_REQ = 14'b00_0000_0000_0100; + localparam WAIT_POC_DONE = 14'b00_0000_0000_1000; + localparam WAIT_STG3 = 14'b00_0000_0001_0000; + localparam STAGE3_INC = 14'b00_0000_0010_0000; + localparam STAGE3_DEC = 14'b00_0000_0100_0000; + localparam STAGE2_INC = 14'b00_0000_1000_0000; + localparam STAGE2_DEC = 14'b00_0001_0000_0000; + localparam STG3_INCDEC_WAIT = 14'b00_0010_0000_0000; + localparam STG2_INCDEC_WAIT = 14'b00_0100_0000_0000; + localparam STAGE2_TAP_CHK = 14'b00_1000_0000_0000; + localparam PRECH_REQUEST = 14'b01_0000_0000_0000; + localparam LIMIT_DONE = 14'b10_0000_0000_0000; + +// Flip-flops + reg [5:0] stg3_init_val; + reg [13:0] lim_state; + reg lim_start_r; + reg ktap_right_r; + reg write_request_r; + reg prech_req_r; + reg poc_ready_r; + reg wait_cnt_en_r; + reg wait_cnt_done; + reg [3:0] wait_cnt_r; + reg [5:0] stg3_tap_cnt; + reg [5:0] stg2_tap_cnt; + reg [5:0] stg3_left_lim; + reg [5:0] stg3_right_lim; + reg [DQS_WIDTH*6-1:0] cmplx_stg3_left_lim; + reg [DQS_WIDTH*6-1:0] simp_stg3_left_lim; + reg [DQS_WIDTH*6-1:0] cmplx_stg3_right_lim; + reg [DQS_WIDTH*6-1:0] simp_stg3_right_lim; + reg [5:0] stg3_dec_val; + reg [5:0] stg3_inc_val; + reg detect_done_r; + reg stg3_dec_r; + reg stg2_inc_r; + reg stg3_inc2init_val_r; + reg stg3_inc2init_val_r1; + reg stg3_dec2init_val_r; + reg stg3_dec2init_val_r1; + reg stg3_dec_req_r; + reg stg3_inc_req_r; + reg stg2_dec_req_r; + reg stg2_inc_req_r; + reg stg3_init_dec_r; + reg [TAPCNTRWIDTH:0] mmcm_current; + reg [TAPCNTRWIDTH:0] mmcm_init_trail; + reg [TAPCNTRWIDTH:0] mmcm_init_lead; + reg done_r; + + reg [13:0] lim_nxt_state; + reg ktap_right; + reg write_request; + reg prech_req; + reg poc_ready; + reg stg3_dec; + reg stg2_inc; + reg stg3_inc2init_val; + reg stg3_dec2init_val; + reg stg3_dec_req; + reg stg3_inc_req; + reg stg2_dec_req; + reg stg2_inc_req; + reg stg3_init_dec; + reg done; + reg oclkdelay_calib_done_r; + + wire [TAPCNTRWIDTH:0] mmcm_sub_dec = mod_sub (mmcm_init_trail, mmcm_current, TAPSPERKCLK); + wire [TAPCNTRWIDTH:0] mmcm_sub_inc = mod_sub (mmcm_current, mmcm_init_lead, TAPSPERKCLK); + + /***************************************************************************/ + // Debug signals + /***************************************************************************/ + + assign dbg_ocd_lim[0+:DQS_WIDTH*6] = simp_stg3_left_lim[DQS_WIDTH*6-1:0]; + assign dbg_ocd_lim[54+:DQS_WIDTH*6] = simp_stg3_right_lim[DQS_WIDTH*6-1:0]; + assign dbg_ocd_lim[255:108] = 'd0; + + + + + assign lim2init_write_request = write_request_r; + assign lim2init_prech_req = prech_req_r; + assign lim2poc_ktap_right = ktap_right_r; + assign lim2poc_rdy = poc_ready_r; + assign lim2ocal_stg3_left_lim = stg3_left_lim; + assign lim2ocal_stg3_right_lim = stg3_right_lim; + assign lim2stg3_dec = stg3_dec_req_r; + assign lim2stg3_inc = stg3_inc_req_r; + assign lim2stg2_dec = stg2_dec_req_r; + assign lim2stg2_inc = stg2_inc_req_r; + assign lim_done = done_r; + + +/**************************Wait Counter Start*********************************/ +// Wait counter enable for wait states WAIT_WR_REQ and WAIT_STG3 +// To avoid DQS toggling when stage2 and 3 taps are moving + always @(posedge clk) begin + if ((lim_state == WAIT_WR_REQ) || + (lim_state == WAIT_STG3) || + (lim_state == INIT)) + wait_cnt_en_r <= #TCQ 1'b1; + else + wait_cnt_en_r <= #TCQ 1'b0; + end + +// Wait counter for wait states WAIT_WR_REQ and WAIT_STG3 +// To avoid DQS toggling when stage2 and 3 taps are moving + always @(posedge clk) begin + if (!wait_cnt_en_r) begin + wait_cnt_r <= #TCQ 'b0; + wait_cnt_done <= #TCQ 1'b0; + end else begin + if (wait_cnt_r != WAIT_CNT - 1) begin + wait_cnt_r <= #TCQ wait_cnt_r + 1; + wait_cnt_done <= #TCQ 1'b0; + end else begin + wait_cnt_r <= #TCQ 'b0; + wait_cnt_done <= #TCQ 1'b1; + end + end + end +/**************************Wait Counter End***********************************/ + +// Flip-flops + + always @(posedge clk) begin + if (rst) + oclkdelay_calib_done_r <= #TCQ 1'b0; + else + oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done; + end + + always @(posedge clk) begin + if (rst) + stg3_init_val <= #TCQ oclkdelay_init_val; + else if (oclkdelay_calib_done) + stg3_init_val <= #TCQ simp_stg3_final_sel; + else + stg3_init_val <= #TCQ oclkdelay_init_val; + end + + always @(posedge clk) begin + if (rst) begin + lim_state <= #TCQ IDLE; + lim_start_r <= #TCQ 1'b0; + ktap_right_r <= #TCQ 1'b0; + write_request_r <= #TCQ 1'b0; + prech_req_r <= #TCQ 1'b0; + poc_ready_r <= #TCQ 1'b0; + detect_done_r <= #TCQ 1'b0; + stg3_dec_r <= #TCQ 1'b0; + stg2_inc_r <= #TCQ 1'b0; + stg3_inc2init_val_r <= #TCQ 1'b0; + stg3_inc2init_val_r1<= #TCQ 1'b0; + stg3_dec2init_val_r <= #TCQ 1'b0; + stg3_dec2init_val_r1<= #TCQ 1'b0; + stg3_dec_req_r <= #TCQ 1'b0; + stg3_inc_req_r <= #TCQ 1'b0; + stg2_dec_req_r <= #TCQ 1'b0; + stg2_inc_req_r <= #TCQ 1'b0; + done_r <= #TCQ 1'b0; + stg3_dec_val <= #TCQ 'd0; + stg3_inc_val <= #TCQ 'd0; + stg3_init_dec_r <= #TCQ 1'b0; + end else begin + lim_state <= #TCQ lim_nxt_state; + lim_start_r <= #TCQ lim_start; + ktap_right_r <= #TCQ ktap_right; + write_request_r <= #TCQ write_request; + prech_req_r <= #TCQ prech_req; + poc_ready_r <= #TCQ poc_ready; + detect_done_r <= #TCQ poc2lim_detect_done; + stg3_dec_r <= #TCQ stg3_dec; + stg2_inc_r <= #TCQ stg2_inc; + stg3_inc2init_val_r <= #TCQ stg3_inc2init_val; + stg3_inc2init_val_r1<= #TCQ stg3_inc2init_val_r; + stg3_dec2init_val_r <= #TCQ stg3_dec2init_val; + stg3_dec2init_val_r1<= #TCQ stg3_dec2init_val_r; + stg3_dec_req_r <= #TCQ stg3_dec_req; + stg3_inc_req_r <= #TCQ stg3_inc_req; + stg2_dec_req_r <= #TCQ stg2_dec_req; + stg2_inc_req_r <= #TCQ stg2_inc_req; + stg3_init_dec_r <= #TCQ stg3_init_dec; + done_r <= #TCQ done; + if (stg3_init_val > (('d63 - wl_po_fine_cnt)/2)) + stg3_dec_val <= #TCQ (stg3_init_val - ('d63 - wl_po_fine_cnt)/2); + else + stg3_dec_val <= #TCQ 'd0; + if (stg3_init_val < 'd63 - ((wl_po_fine_cnt)/2)) + stg3_inc_val <= #TCQ (stg3_init_val + (wl_po_fine_cnt)/2); + else + stg3_inc_val <= #TCQ 'd63; + end + end + +// Keeping track of stage 3 tap count + always @(posedge clk) begin + if (rst) + stg3_tap_cnt <= #TCQ stg3_init_val; + else if ((lim_state == IDLE) || (lim_state == INIT)) + stg3_tap_cnt <= #TCQ stg3_init_val; + else if (lim_state == STAGE3_INC) + stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1; + else if (lim_state == STAGE3_DEC) + stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1; + end + +// Keeping track of stage 2 tap count + always @(posedge clk) begin + if (rst) + stg2_tap_cnt <= #TCQ 'd0; + else if ((lim_state == IDLE) || (lim_state == INIT)) + stg2_tap_cnt <= #TCQ wl_po_fine_cnt; + else if (lim_state == STAGE2_INC) + stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1; + else if (lim_state == STAGE2_DEC) + stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1; + end + +// Keeping track of MMCM tap count + always @(posedge clk) begin + if (rst) begin + mmcm_init_trail <= #TCQ 'd0; + mmcm_init_lead <= #TCQ 'd0; + end else if (poc2lim_detect_done && !detect_done_r) begin + if (stg3_tap_cnt == stg3_dec_val) + mmcm_init_trail <= #TCQ poc2lim_rise_align_taps_trail; + if (stg3_tap_cnt == stg3_inc_val) + mmcm_init_lead <= #TCQ poc2lim_rise_align_taps_lead; + end + end + + always @(posedge clk) begin + if (rst) begin + mmcm_current <= #TCQ 'd0; + end else if (stg3_dec_r) begin + if (stg3_tap_cnt == stg3_dec_val) + mmcm_current <= #TCQ mmcm_init_trail; + else + mmcm_current <= #TCQ poc2lim_rise_align_taps_lead; + end else begin + if (stg3_tap_cnt == stg3_inc_val) + mmcm_current <= #TCQ mmcm_init_lead; + else + mmcm_current <= #TCQ poc2lim_rise_align_taps_trail; + end + end + +// Record Stage3 Left Limit + always @(posedge clk) begin + if (rst) begin + stg3_left_lim <= #TCQ 'd0; + simp_stg3_left_lim <= #TCQ 'd0; + cmplx_stg3_left_lim <= #TCQ 'd0; + end else if (stg3_inc2init_val_r && !stg3_inc2init_val_r1) begin + stg3_left_lim <= #TCQ stg3_tap_cnt; + if (oclkdelay_calib_done) + cmplx_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; + else + simp_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; + end else if (lim_start && !lim_start_r) + stg3_left_lim <= #TCQ 'd0; + end + +// Record Stage3 Right Limit + always @(posedge clk) begin + if (rst) begin + stg3_right_lim <= #TCQ 'd0; + cmplx_stg3_right_lim <= #TCQ 'd0; + simp_stg3_right_lim <= #TCQ 'd0; + end else if (stg3_dec2init_val_r && !stg3_dec2init_val_r1) begin + stg3_right_lim <= #TCQ stg3_tap_cnt; + if (oclkdelay_calib_done) + cmplx_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; + else + simp_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; + end else if (lim_start && !lim_start_r) + stg3_right_lim <= #TCQ 'd0; + end + + always @(*) begin + lim_nxt_state = lim_state; + ktap_right = ktap_right_r; + write_request = write_request_r; + prech_req = prech_req_r; + poc_ready = poc_ready_r; + stg3_dec = stg3_dec_r; + stg2_inc = stg2_inc_r; + stg3_inc2init_val = stg3_inc2init_val_r; + stg3_dec2init_val = stg3_dec2init_val_r; + stg3_dec_req = stg3_dec_req_r; + stg3_inc_req = stg3_inc_req_r; + stg2_inc_req = stg2_inc_req_r; + stg2_dec_req = stg2_dec_req_r; + stg3_init_dec = stg3_init_dec_r; + done = done_r; + + + case(lim_state) + IDLE: begin + if (lim_start && !lim_start_r) begin + lim_nxt_state = INIT; + stg3_dec = 1'b1; + stg2_inc = 1'b1; + stg3_init_dec = 1'b1; + done = 1'b0; + end + //New start of limit module for complex oclkdelay calib + else if (oclkdelay_calib_done && !oclkdelay_calib_done_r && (BYPASS_COMPLEX_OCAL == "FALSE")) begin + done = 1'b0; + end + end + INIT: begin + ktap_right = 1'b1; + // Initial stage 2 increment to 63 for left limit + if (wait_cnt_done) + lim_nxt_state = STAGE2_TAP_CHK; + end + // Wait for DQS to toggle before asserting poc_ready + WAIT_WR_REQ: begin + write_request = 1'b1; + if (wait_cnt_done) begin + poc_ready = 1'b1; + lim_nxt_state = WAIT_POC_DONE; + end + end + // Wait for POC detect done signal + WAIT_POC_DONE: begin + if (poc2lim_detect_done) begin + write_request = 1'b0; + poc_ready = 1'b0; + lim_nxt_state = WAIT_STG3; + end + end + // Wait for DQS to stop toggling before stage3 inc/dec + WAIT_STG3: begin + if (wait_cnt_done) begin + if (stg3_dec_r) begin + // Check for Stage 3 underflow and MMCM tap limit + if ((stg3_tap_cnt > 'd0) && (mmcm_sub_dec < TDQSS_LIM_MMCM_TAPS)) + lim_nxt_state = STAGE3_DEC; + else begin + stg3_dec = 1'b0; + stg3_inc2init_val = 1'b1; + lim_nxt_state = STAGE3_INC; + end + end else begin // Stage 3 being incremented + // Check for Stage 3 overflow and MMCM tap limit + if ((stg3_tap_cnt < 'd63) && (mmcm_sub_inc < TDQSS_LIM_MMCM_TAPS)) + lim_nxt_state = STAGE3_INC; + else begin + stg3_dec2init_val = 1'b1; + lim_nxt_state = STAGE3_DEC; + end + end + end + end + STAGE3_INC: begin + stg3_inc_req = 1'b1; + lim_nxt_state = STG3_INCDEC_WAIT; + end + STAGE3_DEC: begin + stg3_dec_req = 1'b1; + lim_nxt_state = STG3_INCDEC_WAIT; + end + // Wait for stage3 inc/dec to complete (po_rdy) + STG3_INCDEC_WAIT: begin + stg3_dec_req = 1'b0; + stg3_inc_req = 1'b0; + if (!stg3_dec_req_r && !stg3_inc_req_r && po_rdy) begin + if (stg3_init_dec_r) begin + // Initial decrement of stage 3 + if (stg3_tap_cnt > stg3_dec_val) + lim_nxt_state = STAGE3_DEC; + else begin + lim_nxt_state = WAIT_WR_REQ; + stg3_init_dec = 1'b0; + end + end else if (stg3_dec2init_val_r) begin + if (stg3_tap_cnt > stg3_init_val) + lim_nxt_state = STAGE3_DEC; + else + lim_nxt_state = STAGE2_TAP_CHK; + end else if (stg3_inc2init_val_r) begin + if (stg3_tap_cnt < stg3_inc_val) + lim_nxt_state = STAGE3_INC; + else + lim_nxt_state = STAGE2_TAP_CHK; + end else begin + lim_nxt_state = WAIT_WR_REQ; + end + end + end + // Check for overflow and underflow of stage2 taps + STAGE2_TAP_CHK: begin + if (stg3_dec2init_val_r) begin + // Increment stage 2 to write level tap value at the end of limit detection + if (stg2_tap_cnt < wl_po_fine_cnt) + lim_nxt_state = STAGE2_INC; + else begin + lim_nxt_state = PRECH_REQUEST; + end + end else if (stg3_inc2init_val_r) begin + // Decrement stage 2 to '0' to determine right limit + if (stg2_tap_cnt > 'd0) + lim_nxt_state = STAGE2_DEC; + else begin + lim_nxt_state = PRECH_REQUEST; + stg3_inc2init_val = 1'b0; + end + end else if (stg2_inc_r && (stg2_tap_cnt < 'd63)) begin + // Initial increment to 63 + lim_nxt_state = STAGE2_INC; + end else begin + lim_nxt_state = STG3_INCDEC_WAIT; + stg2_inc = 1'b0; + end + end + STAGE2_INC: begin + stg2_inc_req = 1'b1; + lim_nxt_state = STG2_INCDEC_WAIT; + end + STAGE2_DEC: begin + stg2_dec_req = 1'b1; + lim_nxt_state = STG2_INCDEC_WAIT; + end + // Wait for stage3 inc/dec to complete (po_rdy) + STG2_INCDEC_WAIT: begin + stg2_inc_req = 1'b0; + stg2_dec_req = 1'b0; + if (!stg2_inc_req_r && !stg2_dec_req_r && po_rdy) + lim_nxt_state = STAGE2_TAP_CHK; + end + PRECH_REQUEST: begin + prech_req = 1'b1; + if (prech_done) begin + prech_req = 1'b0; + if (stg3_dec2init_val_r) + lim_nxt_state = LIMIT_DONE; + else + lim_nxt_state = WAIT_WR_REQ; + end + end + LIMIT_DONE: begin + done = 1'b1; + ktap_right = 1'b0; + stg3_dec2init_val = 1'b0; + lim_nxt_state = IDLE; + end + default: begin + lim_nxt_state = IDLE; + end + endcase + end + + +endmodule //mig_7_series_v4_0_ddr_phy_ocd_lim + diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_mux.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_mux.v new file mode 100644 index 0000000..b1fa615 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_mux.v @@ -0,0 +1,207 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_v4_0_phy_ocd_mux.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: The limit block and the _po_cntlr block both manipulate +// the phaser out and the POC. This block muxes those commands +// together, and encapsulates logic required for meeting phaser +// setup and wait times. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_ocd_mux # + (parameter DQS_CNT_WIDTH = 3, + parameter DQS_WIDTH = 8, + parameter TCQ = 100) + (/*AUTOARG*/ + // Outputs + ktap_at_left_edge, ktap_at_right_edge, mmcm_edge_detect_rdy, + po_stg3_incdec, po_en_stg3, po_en_stg23, po_stg23_sel, + po_stg23_incdec, po_rdy, wl_po_fine_cnt_sel, oclk_prech_req, + // Inputs + clk, rst, ocd_ktap_right, ocd_ktap_left, lim2poc_ktap_right, + lim2poc_rdy, ocd_edge_detect_rdy, lim2stg2_inc, lim2stg2_dec, + lim2stg3_inc, lim2stg3_dec, ocd2stg2_inc, ocd2stg2_dec, + ocd_cntlr2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, wl_po_fine_cnt, + oclkdelay_calib_cnt, lim2init_prech_req, ocd_prech_req + ); + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + localparam PO_WAIT = 15; + localparam POW_WIDTH = clogb2(PO_WAIT); + localparam ONE = 1; + localparam TWO = 2; + + input clk; + input rst; + + input ocd_ktap_right, ocd_ktap_left; + input lim2poc_ktap_right; + output ktap_at_left_edge, ktap_at_right_edge; + assign ktap_at_left_edge = ocd_ktap_left; + assign ktap_at_right_edge = lim2poc_ktap_right || ocd_ktap_right; + + input lim2poc_rdy; + input ocd_edge_detect_rdy; + output mmcm_edge_detect_rdy; + assign mmcm_edge_detect_rdy = lim2poc_rdy || ocd_edge_detect_rdy; + + // po_stg3_incdec and po_en_stg3 are deprecated and should be removed. + output po_stg3_incdec; + output po_en_stg3; + assign po_stg3_incdec = 1'b0; + assign po_en_stg3 = 1'b0; + + + reg [1:0] po_setup_ns, po_setup_r; + always @(posedge clk) po_setup_r <= #TCQ po_setup_ns; + + input lim2stg2_inc; + input lim2stg2_dec; + + input lim2stg3_inc; + input lim2stg3_dec; + + input ocd2stg2_inc; + input ocd2stg2_dec; + input ocd_cntlr2stg2_dec; + + input ocd2stg3_inc; + input ocd2stg3_dec; + + wire setup_po = + lim2stg2_inc || lim2stg2_dec || lim2stg3_inc || lim2stg3_dec || + ocd2stg2_inc || ocd2stg2_dec || ocd2stg3_inc || ocd2stg3_dec || ocd_cntlr2stg2_dec; + + always @(*) begin + po_setup_ns = po_setup_r; + if (rst) po_setup_ns = 2'b00; + else if (setup_po) po_setup_ns = 2'b11; + else if (|po_setup_r) po_setup_ns = po_setup_r - 2'b01; + end + + reg po_en_stg23_r; + wire po_en_stg23_ns = ~rst && po_setup_r == 2'b01; + always @(posedge clk) po_en_stg23_r <= #TCQ po_en_stg23_ns; + output po_en_stg23; + assign po_en_stg23 = po_en_stg23_r; + + wire sel_stg3 = lim2stg3_inc || lim2stg3_dec || ocd2stg3_inc || ocd2stg3_dec; + + reg [POW_WIDTH-1:0] po_wait_r, po_wait_ns; + reg po_stg23_sel_r; + // Reset to zero at the end. Makes adjust stg2 at end of centering + // get the correct value of po_counter_read_val. + wire po_stg23_sel_ns = ~rst && (setup_po + ? sel_stg3 + ? 1'b1 + : 1'b0 + : po_stg23_sel_r && !(po_wait_r == ONE[POW_WIDTH-1:0])); + always @(posedge clk) po_stg23_sel_r <= #TCQ po_stg23_sel_ns; + output po_stg23_sel; + assign po_stg23_sel = po_stg23_sel_r; + + wire po_inc = lim2stg2_inc || lim2stg3_inc || ocd2stg2_inc || ocd2stg3_inc; + + reg po_stg23_incdec_r; + wire po_stg23_incdec_ns = ~rst && (setup_po ? po_inc ? 1'b1 : 1'b0 : po_stg23_incdec_r); + always @(posedge clk) po_stg23_incdec_r <= #TCQ po_stg23_incdec_ns; + output po_stg23_incdec; + assign po_stg23_incdec = po_stg23_incdec_r; + + + always @(posedge clk) po_wait_r <= #TCQ po_wait_ns; + always @(*) begin + po_wait_ns = po_wait_r; + if (rst) po_wait_ns = {POW_WIDTH{1'b0}}; + else if (po_en_stg23_r) po_wait_ns = PO_WAIT[POW_WIDTH-1:0] - ONE[POW_WIDTH-1:0]; + else if (po_wait_r != {POW_WIDTH{1'b0}}) po_wait_ns = po_wait_r - ONE[POW_WIDTH-1:0]; + end + + wire po_rdy_ns = ~(setup_po || |po_setup_r || |po_wait_ns); + reg po_rdy_r; + always @(posedge clk) po_rdy_r <= #TCQ po_rdy_ns; + + output po_rdy; + assign po_rdy = po_rdy_r; + + input [6*DQS_WIDTH-1:0] wl_po_fine_cnt; + input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + wire [6*DQS_WIDTH-1:0] wl_po_fine_shifted = wl_po_fine_cnt >> oclkdelay_calib_cnt*6; + output [5:0] wl_po_fine_cnt_sel; + assign wl_po_fine_cnt_sel = wl_po_fine_shifted[5:0]; + + input lim2init_prech_req; + input ocd_prech_req; + output oclk_prech_req; + assign oclk_prech_req = ocd_prech_req || lim2init_prech_req; + +endmodule // mig_7series_v4_0_ddr_phy_ocd_mux + diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v new file mode 100644 index 0000000..b1174d9 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v @@ -0,0 +1,594 @@ + +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_v4_0_phy_ocd_po_cntlr.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Manipulates phaser out stg2f and stg3 on behalf of +// scan and DQS centering. +// +// Maintains a shadow of the phaser out stg2f and stg3 tap settings. +// The stg3 shadow is 6 bits, just like the phaser out. stg2f is +// 8 bits. This allows the po_cntlr to track how far past the stg2f +// saturation points we have gone when stepping to the limits of stg3. +// This way we're can stay in sync when we step back from the saturation +// limits. +// +// Looks at the edge values and determines which case has been +// detected by the scan. Uses the results to drive the centering. +// +// Main state machine waits until it sees reset_scan go to zero. While +// waiting it is writing the initialzation values to the stg2 and stg3 +// shadows. When reset_scan goes low, taps_set is pulsed. This +// tells the sampling block to begin sampling. When the sampling +// block has finished sampling this setting of the phaser out taps, +// is signals by setting samp_done. When the main state machine +// sees samp_done it sets the next value in the phaser out and +// waits for the phaser out to be ready before beginning the next +// sample. +// +// Turns out phy_init is sensitive to the length of the ocal_num_samples_done +// pulse. Something like a precharge and activate time. Added feature +// to resume_wait to wait at least 32 cycles between assertion and +// subsequent deassertion of ocal_num_samples_done. +// +// Also turns out phy_init needs help to get into consistent +// starting state for complex cal. This can be done by preseting +// ocal_num_samples_done to one. Then waiting for 32 fabric clocks, +// turn off _done and then assert _resume. +// +// Scanning algorithm. +// +// Phaser manipulation algoritm. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_ocd_po_cntlr # + (parameter DQS_CNT_WIDTH = 3, + parameter DQS_WIDTH = 8, + parameter nCK_PER_CLK = 4, + parameter SAMPLES = 128, + parameter TCQ = 100) + (/*AUTOARG*/ + // Outputs + scan_done, ocal_num_samples_done_r, oclkdelay_center_calib_start, + oclkdelay_center_calib_done, oclk_center_write_resume, ocd2stg2_inc, + ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, stg3, simp_stg3_final, + cmplx_stg3_final, simp_stg3_final_sel, ninety_offsets, + scanning_right, ocd_ktap_left, ocd_ktap_right, ocd_edge_detect_rdy, + taps_set, use_noise_window, ocal_scan_win_not_found, + // Inputs + clk, rst, reset_scan, oclkdelay_init_val, lim2ocal_stg3_right_lim, + lim2ocal_stg3_left_lim, complex_oclkdelay_calib_start, + po_counter_read_val, oclkdelay_calib_cnt, mmcm_edge_detect_done, + mmcm_lbclk_edge_aligned, poc_backup, phy_rddata_en_3, zero2fuzz, + fuzz2zero, oneeighty2fuzz, fuzz2oneeighty, z2f, f2z, o2f, f2o, + scan_right, samp_done, wl_po_fine_cnt_sel, po_rdy + ); + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + input clk; + input rst; + + input reset_scan; + reg scan_done_r; + output scan_done; + assign scan_done = scan_done_r; + output [5:0] simp_stg3_final_sel; + + reg cmplx_samples_done_ns, cmplx_samples_done_r; + always @(posedge clk) cmplx_samples_done_r <= #TCQ cmplx_samples_done_ns; + output ocal_num_samples_done_r; + assign ocal_num_samples_done_r = cmplx_samples_done_r; + + // Write Level signals during OCLKDELAY calibration + input [5:0] oclkdelay_init_val; + input [5:0] lim2ocal_stg3_right_lim; + input [5:0] lim2ocal_stg3_left_lim; + + input complex_oclkdelay_calib_start; + + reg oclkdelay_center_calib_start_ns, oclkdelay_center_calib_start_r; + always @(posedge clk) oclkdelay_center_calib_start_r <= #TCQ oclkdelay_center_calib_start_ns; + output oclkdelay_center_calib_start; + assign oclkdelay_center_calib_start = oclkdelay_center_calib_start_r; + + reg oclkdelay_center_calib_done_ns, oclkdelay_center_calib_done_r; + always @(posedge clk) oclkdelay_center_calib_done_r <= #TCQ oclkdelay_center_calib_done_ns; + output oclkdelay_center_calib_done; + assign oclkdelay_center_calib_done = oclkdelay_center_calib_done_r; + + reg oclk_center_write_resume_ns, oclk_center_write_resume_r; + always @(posedge clk) oclk_center_write_resume_r <= #TCQ oclk_center_write_resume_ns; + output oclk_center_write_resume; + assign oclk_center_write_resume = oclk_center_write_resume_r; + + reg ocd2stg2_inc_r, ocd2stg2_dec_r, ocd2stg3_inc_r, ocd2stg3_dec_r; + output ocd2stg2_inc, ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec; + assign ocd2stg2_inc = ocd2stg2_inc_r; + assign ocd2stg2_dec = ocd2stg2_dec_r; + assign ocd2stg3_inc = ocd2stg3_inc_r; + assign ocd2stg3_dec = ocd2stg3_dec_r; + + // Remember, two stage 2 steps for every stg 3 step. And we need a sign bit. + reg [8:0] stg2_ns, stg2_r; + always @(posedge clk) stg2_r <= #TCQ stg2_ns; + + reg [5:0] stg3_ns, stg3_r; + always @(posedge clk) stg3_r <= #TCQ stg3_ns; + output [5:0] stg3; + assign stg3 = stg3_r; + + input [5:0] wl_po_fine_cnt_sel; + + input [8:0] po_counter_read_val; + reg [5:0] po_counter_read_val_r; + always @(posedge clk) po_counter_read_val_r <= #TCQ po_counter_read_val[5:0]; + + reg [DQS_WIDTH*6-1:0] simp_stg3_final_ns, simp_stg3_final_r, cmplx_stg3_final_ns, cmplx_stg3_final_r; + always @(posedge clk) simp_stg3_final_r <= #TCQ simp_stg3_final_ns; + always @(posedge clk) cmplx_stg3_final_r <= #TCQ cmplx_stg3_final_ns; + output [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final; + assign simp_stg3_final = simp_stg3_final_r; + assign cmplx_stg3_final = cmplx_stg3_final_r; + + input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + wire [DQS_WIDTH*6-1:0] simp_stg3_final_shft = simp_stg3_final_r >> oclkdelay_calib_cnt * 6; + assign simp_stg3_final_sel = simp_stg3_final_shft[5:0]; + wire [5:0] stg3_init = complex_oclkdelay_calib_start ? simp_stg3_final_sel : oclkdelay_init_val; + + wire signed [8:0] stg2_steps = stg3_r > stg3_init + ? -9'sd2 * $signed({3'b0, (stg3_r - stg3_init)}) + : 9'sd2 * $signed({3'b0, (stg3_init - stg3_r)}); + + wire signed [8:0] stg2_target_ns = $signed({3'b0, wl_po_fine_cnt_sel}) + stg2_steps; + reg signed [8:0] stg2_target_r; + always @ (posedge clk) stg2_target_r <= #TCQ stg2_target_ns; + + reg [5:0] stg2_final_ns, stg2_final_r; + always @(posedge clk) stg2_final_r <= #TCQ stg2_final_ns; + always @(*) stg2_final_ns = stg2_target_r[8] == 1'b1 + ? 6'd0 + : stg2_target_r > 9'd63 + ? 6'd63 + : stg2_target_r[5:0]; + + wire final_stg2_inc = stg2_final_r > po_counter_read_val_r; + wire final_stg2_dec = stg2_final_r < po_counter_read_val_r; + + wire left_lim = stg3_r == lim2ocal_stg3_left_lim; + wire right_lim = stg3_r == lim2ocal_stg3_right_lim; + + reg [1:0] ninety_offsets_ns, ninety_offsets_r; + always @(posedge clk) ninety_offsets_r <= #TCQ ninety_offsets_ns; + output [1:0] ninety_offsets; + assign ninety_offsets = ninety_offsets_r; + + reg scanning_right_ns, scanning_right_r; + always @(posedge clk) scanning_right_r <= #TCQ scanning_right_ns; + output scanning_right; + assign scanning_right = scanning_right_r; + + reg ocd_ktap_left_ns, ocd_ktap_left_r, ocd_ktap_right_ns, ocd_ktap_right_r; + always @(posedge clk) ocd_ktap_left_r <= #TCQ ocd_ktap_left_ns; + always @(posedge clk) ocd_ktap_right_r <= #TCQ ocd_ktap_right_ns; + output ocd_ktap_left, ocd_ktap_right; + assign ocd_ktap_left = ocd_ktap_left_r; + assign ocd_ktap_right = ocd_ktap_right_r; + + reg ocd_edge_detect_rdy_ns, ocd_edge_detect_rdy_r; + always @(posedge clk) ocd_edge_detect_rdy_r <= #TCQ ocd_edge_detect_rdy_ns; + output ocd_edge_detect_rdy; + assign ocd_edge_detect_rdy = ocd_edge_detect_rdy_r; + + input mmcm_edge_detect_done; + input mmcm_lbclk_edge_aligned; + input poc_backup; + reg poc_backup_ns, poc_backup_r; + always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns; + + reg taps_set_r; + output taps_set; + assign taps_set = taps_set_r; + + input phy_rddata_en_3; + + input [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty; + input z2f, f2z, o2f, f2o; + + wire zero = f2z && z2f; + wire noise = z2f && f2o; + wire oneeighty = f2o && o2f; + + reg win_not_found; + reg [1:0] ninety_offsets_final_ns, ninety_offsets_final_r; + always @(posedge clk) ninety_offsets_final_r <= #TCQ ninety_offsets_final_ns; + reg [5:0] left, right, current_edge; + always @(*) begin + left = lim2ocal_stg3_left_lim; + right = lim2ocal_stg3_right_lim; + ninety_offsets_final_ns = 2'd0; + win_not_found = 1'b0; + if (zero) begin + left = fuzz2zero; + right = zero2fuzz; + end + else if (noise) begin + left = zero2fuzz; + right = fuzz2oneeighty; + ninety_offsets_final_ns = 2'd1; + end + else if (oneeighty) begin + left = fuzz2oneeighty; + right = oneeighty2fuzz; + ninety_offsets_final_ns = 2'd2; + end + else if (z2f) begin + right = zero2fuzz; + end + else if (f2o) begin + left = fuzz2oneeighty; + ninety_offsets_final_ns = 2'd2; + end + else if (f2z) begin + left = fuzz2zero; + end + else win_not_found = 1'b1; + current_edge = ocd_ktap_left_r ? left : right; + end // always @ begin + + output use_noise_window; + assign use_noise_window = ninety_offsets == 2'd1; + + reg ocal_scan_win_not_found_ns, ocal_scan_win_not_found_r; + always @(posedge clk) ocal_scan_win_not_found_r <= #TCQ ocal_scan_win_not_found_ns; + output ocal_scan_win_not_found; + assign ocal_scan_win_not_found = ocal_scan_win_not_found_r; + + wire inc_po_ns = current_edge > stg3_r; + wire dec_po_ns = current_edge < stg3_r; + reg inc_po_r, dec_po_r; + always @(posedge clk) inc_po_r <= #TCQ inc_po_ns; + always @(posedge clk) dec_po_r <= #TCQ dec_po_ns; + + input scan_right; + + wire left_stop = left_lim || scan_right; + wire right_stop = right_lim || o2f; + + // POC samples every other fabric clock. + localparam POC_SAMPLE_CLEAR_WAIT = SAMPLES * 2 > 15 ? SAMPLES * 2 : 15; + localparam MAX_RESUME_WAIT = POC_SAMPLE_CLEAR_WAIT > 31 ? POC_SAMPLE_CLEAR_WAIT : 31; + localparam RESUME_WAIT_WIDTH = clogb2(MAX_RESUME_WAIT + 1); + + reg [RESUME_WAIT_WIDTH-1:0] resume_wait_ns, resume_wait_r; + always @(posedge clk) resume_wait_r <= #TCQ resume_wait_ns; + + wire resume_wait = |resume_wait_r; + + reg po_done_ns, po_done_r; + always @(posedge clk) po_done_r <= #TCQ po_done_ns; + + input samp_done; + + input po_rdy; + + reg up_ns, up_r; + always @(posedge clk) up_r <= #TCQ up_ns; + + reg [1:0] two_ns, two_r; + always @(posedge clk) two_r <= #TCQ two_ns; + + +/* wire stg2_zero = ~|stg2_r; + wire [8:0] stg2_2_zero = stg2_r[8] ? 9'd0 + : stg2_r > 9'd63 + ? 9'd63 + : stg2_r; */ + + reg [3:0] sm_ns, sm_r; + always @(posedge clk) sm_r <= #TCQ sm_ns; + + reg phy_rddata_en_3_second_ns, phy_rddata_en_3_second_r; + always @(posedge clk) phy_rddata_en_3_second_r <= #TCQ phy_rddata_en_3_second_ns; + always @(*) phy_rddata_en_3_second_ns = ~reset_scan && (phy_rddata_en_3 + ? ~phy_rddata_en_3_second_r + : phy_rddata_en_3_second_r); + wire use_samp_done = nCK_PER_CLK == 2 ? phy_rddata_en_3 && phy_rddata_en_3_second_r : phy_rddata_en_3; + + reg po_center_wait; + reg po_slew; + reg po_finish_scan; + + always @(*) begin + + // Default next state assignments. + + cmplx_samples_done_ns = cmplx_samples_done_r; + cmplx_stg3_final_ns = cmplx_stg3_final_r; + scanning_right_ns = scanning_right_r; + ninety_offsets_ns = ninety_offsets_r; + ocal_scan_win_not_found_ns = ocal_scan_win_not_found_r; + ocd_edge_detect_rdy_ns = ocd_edge_detect_rdy_r; + ocd_ktap_left_ns = ocd_ktap_left_r; + ocd_ktap_right_ns = ocd_ktap_right_r; + ocd2stg2_inc_r = 1'b0; + ocd2stg2_dec_r = 1'b0; + ocd2stg3_inc_r = 1'b0; + ocd2stg3_dec_r = 1'b0; + oclkdelay_center_calib_start_ns = oclkdelay_center_calib_start_r; + oclkdelay_center_calib_done_ns = 1'b0; + oclk_center_write_resume_ns = oclk_center_write_resume_r; + po_center_wait = 1'b0; + po_done_ns = po_done_r; + po_finish_scan = 1'b0; + po_slew = 1'b0; + poc_backup_ns = poc_backup_r; + scan_done_r = 1'b0; + simp_stg3_final_ns = simp_stg3_final_r; + sm_ns = sm_r; + taps_set_r = 1'b0; + up_ns = up_r; + stg2_ns = stg2_r; + stg3_ns = stg3_r; + two_ns = two_r; + resume_wait_ns = resume_wait_r; + + if (rst == 1'b1) begin + + // RESET next states + cmplx_samples_done_ns = 1'b0; + ocal_scan_win_not_found_ns = 1'b0; + ocd_ktap_left_ns = 1'b0; + ocd_ktap_right_ns = 1'b0; + ocd_edge_detect_rdy_ns = 1'b0; + oclk_center_write_resume_ns = 1'b0; + oclkdelay_center_calib_start_ns = 1'b0; + po_done_ns = 1'b1; + resume_wait_ns = 5'd0; + sm_ns = /*AK("READY")*/4'd0; + + end else + + // State based actions and next states. + case (sm_r) + + /*AL("READY")*/4'd0:begin + poc_backup_ns = 1'b0; + stg2_ns = {3'b0, wl_po_fine_cnt_sel}; + stg3_ns = stg3_init; + scanning_right_ns = 1'b0; + if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1; + if (!reset_scan && ~resume_wait) begin + cmplx_samples_done_ns = 1'b0; + ocal_scan_win_not_found_ns = 1'b0; + taps_set_r = 1'b1; + sm_ns = /*AK("SAMPLING")*/4'd1; + end + end + + /*AL("SAMPLING")*/4'd1:begin + if (samp_done && use_samp_done) begin + if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1; + scanning_right_ns = scanning_right_r || left_stop; + if (right_stop && scanning_right_r) begin + oclkdelay_center_calib_start_ns = 1'b1; + ocd_ktap_left_ns = 1'b1; + ocal_scan_win_not_found_ns = win_not_found; + sm_ns = /*AK("SLEW_PO")*/4'd3; + end else begin + if (scanning_right_ns) ocd2stg3_inc_r = 1'b1; + else ocd2stg3_dec_r = 1'b1; + sm_ns = /*AK("PO_WAIT")*/4'd2; + end + end + end + + /*AL("PO_WAIT")*/4'd2:begin + if (po_done_r && ~resume_wait) begin + taps_set_r = 1'b1; + sm_ns = /*AK("SAMPLING")*/4'd1; + cmplx_samples_done_ns = 1'b0; + end + end + + /*AL("SLEW_PO")*/4'd3:begin + po_slew = 1'b1; + ninety_offsets_ns = |ninety_offsets_final_r ? 2'b01 : 2'b00; + if (~resume_wait) begin + if (po_done_r) begin + if (inc_po_r) ocd2stg3_inc_r = 1'b1; + else if (dec_po_r) ocd2stg3_dec_r = 1'b1; + else if (~resume_wait) begin + cmplx_samples_done_ns = 1'b0; + sm_ns = /*AK("ALIGN_EDGES")*/4'd4; + oclk_center_write_resume_ns = 1'b1; + end + end // if (po_done) + end + end // case: 3'd3 + + /*AL("ALIGN_EDGES")*/4'd4: + if (~resume_wait) begin + if (mmcm_edge_detect_done) begin + ocd_edge_detect_rdy_ns = 1'b0; + if (ocd_ktap_left_r) begin + ocd_ktap_left_ns = 1'b0; + ocd_ktap_right_ns = 1'b1; + oclk_center_write_resume_ns = 1'b0; + sm_ns = /*AK("SLEW_PO")*/4'd3; + end else if (ocd_ktap_right_r) begin + ocd_ktap_right_ns = 1'b0; + sm_ns = /*AK("WAIT_ONE")*/4'd5; + end else if (~mmcm_lbclk_edge_aligned) begin + sm_ns = /*AK("DQS_STOP_WAIT")*/4'd6; + oclk_center_write_resume_ns = 1'b0; + end else begin + if (ninety_offsets_r != ninety_offsets_final_r && ocd_edge_detect_rdy_r) begin + ninety_offsets_ns = ninety_offsets_r + 2'b01; + sm_ns = /*AK("WAIT_ONE")*/4'd5; + end else begin + oclk_center_write_resume_ns = 1'b0; + poc_backup_ns = poc_backup; +// stg2_ns = stg2_2_zero; + sm_ns = /*AK("FINISH_SCAN")*/4'd8; + end + end // else: !if(~mmcm_lbclk_edge_aligned) + end else ocd_edge_detect_rdy_ns = 1'b1; + end // if (~resume_wait) + + + /*AL("WAIT_ONE")*/4'd5: + sm_ns = /*AK("ALIGN_EDGES")*/4'd4; + + /*AL("DQS_STOP_WAIT")*/4'd6: + if (~resume_wait) begin + ocd2stg3_dec_r = 1'b1; + sm_ns = /*AK("CENTER_PO_WAIT")*/4'd7; + end + + /*AL("CENTER_PO_WAIT")*/4'd7: begin + po_center_wait = 1'b1; // Kludge to get around limitation of the AUTOs symbols. + if (po_done_r) begin + sm_ns = /*AK("ALIGN_EDGES")*/4'd4; + oclk_center_write_resume_ns = 1'b1; + end + end + + /*AL("FINISH_SCAN")*/4'd8: begin + po_finish_scan = 1'b1; + if (resume_wait_r == 5'd1) begin + if (~poc_backup_r) begin + oclkdelay_center_calib_done_ns = 1'b1; + oclkdelay_center_calib_start_ns = 1'b0; + end + end + if (~resume_wait) begin + if (po_rdy) + if (poc_backup_r) begin + ocd2stg3_inc_r = 1'b1; + poc_backup_ns = 1'b0; + end + else if (~final_stg2_inc && ~final_stg2_dec) begin + if (complex_oclkdelay_calib_start) cmplx_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r; + else simp_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r; + sm_ns = /*AK("READY")*/4'd0; + scan_done_r = 1'b1; + end else begin + ocd2stg2_inc_r = final_stg2_inc; + ocd2stg2_dec_r = final_stg2_dec; + end + end // if (~resume_wait) + end // case: 4'd8 + + endcase // case (sm_r) + + if (ocd2stg3_inc_r) begin + stg3_ns = stg3_r + 6'h1; + up_ns = 1'b0; + end + if (ocd2stg3_dec_r) begin + stg3_ns = stg3_r - 6'h1; + up_ns = 1'b1; + end + if (ocd2stg3_inc_r || ocd2stg3_dec_r) begin + po_done_ns = 1'b0; + two_ns = 2'b00; + end + + if (~po_done_r) + if (po_rdy) + if (two_r == 2'b10 || po_center_wait || po_slew || po_finish_scan) po_done_ns = 1'b1; + else begin + two_ns = two_r + 2'b1; + if (up_r) begin + stg2_ns = stg2_r + 9'b1; + if (stg2_r >= 9'd0 && stg2_r < 9'd63) ocd2stg2_inc_r = 1'b1; + end else begin + stg2_ns = stg2_r - 9'b1; + if (stg2_r > 9'd0 && stg2_r <= 9'd63) ocd2stg2_dec_r = 1'b1; + end + end // else: !if(two_r == 2'b10) + + if (ocd_ktap_left_ns && ~ocd_ktap_left_r) resume_wait_ns = 'b1; + else if (oclk_center_write_resume_ns && ~oclk_center_write_resume_r) + resume_wait_ns = POC_SAMPLE_CLEAR_WAIT[RESUME_WAIT_WIDTH-1:0]; + else if (~oclk_center_write_resume_ns && oclk_center_write_resume_r) resume_wait_ns = 'd15; + else if (cmplx_samples_done_ns & ~cmplx_samples_done_r || + complex_oclkdelay_calib_start & reset_scan || + poc_backup_r & ocd2stg3_inc_r) resume_wait_ns = 'd31; + else if (|resume_wait_r) resume_wait_ns = resume_wait_r - 'd1; + + end // always @ begin + +endmodule // mig_7series_v4_0_ddr_phy_ocd_po_cntlr + +// Local Variables: +// verilog-autolabel-prefix: "4'd" +// End: diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_samp.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_samp.v new file mode 100644 index 0000000..0f680be --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_samp.v @@ -0,0 +1,329 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_v4_0_phy_ocd_samp.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Controls the number of samples and generates an aggregate +//sampling result. +// +// The following shows the nesting of the sampling loop. Nominally built +// to accomodate the "complex" sampling protocol. Adapted for use with +// "simple" samplng. +// +// simple complex +// +// samples OCAL_SIMPLE_SCAN_SAMPS 1 or 50 Depends on SIM_CAL_OPTION +// rd_victim_sel 0 0 to 7 +// data_cnt 1 157 +// +// First it collects comparison results provided on the +// two bit "match" bus. A particular phaser tap setting may be recorded one +// or many times depending on various parameter settings. +// The two bit match bus corresponds to comparisons for the +// zero or rising phase, and the oneeighty or falling phase. The "aggregate" +// starts out as NULL and then begins collecting comparison results +// when phy_rddata_en_1 is high. The first result is always set into +// the aggregate result. Subsequent results that match aggregate, don't +// make any change. Subsequent compare results that don't match cause the aggregate +// to turn to FUZZ. +// +// A "sample" is defined as a single DRAM burst for the simple step, and +// an entire 157 DRAM data bursts across the 8 victim bits for complex. +// +// Once all samples have been taken, the samp_result is computed by +// comparing the number of successful compares against the threshold. +// +// The second function is to track and control the number of samples. For +// "simple" data, the number of samples is set by OCAL_SIMPLE_SCAN_SAMPS. +// For "complex" data, nominally +// the complex data pattern consists of a sequence of 157 DRAM chunks. This +// sequence is run with each bit in the byte designated as the "victim". This sequence +// is repeated 50 times, although when SIM_CAL_OPTION is set to none "NONE", it is only +// repeated once. +// +// This block generates oclk_calib_resume. For the simple pattern, a single DRAM +// burst is returned For complex its 157 which indicates the start of the 157*50 +// sequence for a bit. samp_done is pulsed. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_ocd_samp # + (parameter nCK_PER_CLK = 4, + parameter OCAL_SIMPLE_SCAN_SAMPS = 2, + parameter SCAN_PCT_SAMPS_SOLID = 95, + parameter TCQ = 100, + parameter SIM_CAL_OPTION = "NONE") + (/*AUTOARG*/ + // Outputs + samp_done, oclk_calib_resume, rd_victim_sel, samp_result, + // Inputs + complex_oclkdelay_calib_start, clk, rst, reset_scan, + ocal_num_samples_inc, match, phy_rddata_en_1, taps_set, + phy_rddata_en_2 + ); + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + localparam ONE = 1; + + localparam CMPLX_DATA_CNT = nCK_PER_CLK == 2 ? 157 * 2 : 157; + localparam SIMP_DATA_CNT = nCK_PER_CLK == 2 ? 2 : 1; + + localparam DATA_CNT_WIDTH = nCK_PER_CLK == 2 ? 9 : 8; + + localparam CMPLX_SAMPS = SIM_CAL_OPTION == "NONE" ? 50 : 1; + + // Plus one because were counting in natural numbers. + localparam SAMP_CNT_WIDTH = clogb2(OCAL_SIMPLE_SCAN_SAMPS > CMPLX_SAMPS + ? OCAL_SIMPLE_SCAN_SAMPS : CMPLX_SAMPS) + 1; + + // Remember SAMPLES is natural number counting. One corresponds to one sample. + localparam integer SIMP_SAMPS_SOLID_THRESH = OCAL_SIMPLE_SCAN_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01; + localparam integer SIMP_SAMPS_HALF_THRESH = SIMP_SAMPS_SOLID_THRESH/2; + localparam integer CMPLX_SAMPS_SOLID_THRESH = CMPLX_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01; + localparam integer CMPLX_SAMPS_HALF_THRESH = CMPLX_SAMPS_SOLID_THRESH/2; + + input complex_oclkdelay_calib_start; + + wire [SAMP_CNT_WIDTH-1:0] samples = complex_oclkdelay_calib_start + ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0] + : OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0]; + + localparam [1:0] NULL = 2'b11, + FUZZ = 2'b00, + ONEEIGHTY = 2'b10, + ZERO = 2'b01; + + input clk; + input rst; + + input reset_scan; + + // Given the need to count phy_data_en, this is not useful. + input ocal_num_samples_inc; + + input [1:0] match; + + input phy_rddata_en_1; + + input taps_set; + + reg samp_done_ns, samp_done_r; + always @(posedge clk) samp_done_r <= #TCQ samp_done_ns; + output samp_done; + assign samp_done = samp_done_r; + + input phy_rddata_en_2; + wire samp_valid = samp_done_r && phy_rddata_en_2; + + reg [1:0] agg_samp_ns, agg_samp_r; + always @(posedge clk) agg_samp_r <= #TCQ agg_samp_ns; + + reg oclk_calib_resume_ns, oclk_calib_resume_r; + always @(posedge clk) oclk_calib_resume_r <= #TCQ oclk_calib_resume_ns; + output oclk_calib_resume; + assign oclk_calib_resume = oclk_calib_resume_r; + + // Complex data counting. + // Inner most loop. 157 phy_data_en. + reg [DATA_CNT_WIDTH-1:0] data_cnt_ns, data_cnt_r; + always @(posedge clk) data_cnt_r <= #TCQ data_cnt_ns; + + // Nominally, 50 samples of the above 157 phy_data_en. + reg [SAMP_CNT_WIDTH-1:0] samps_ns, samps_r; + always @(posedge clk) samps_r <= #TCQ samps_ns; + + // Step through the 8 bits in the byte. + reg [2:0] rd_victim_sel_ns, rd_victim_sel_r; + always @(posedge clk) rd_victim_sel_r <= #TCQ rd_victim_sel_ns; + output [2:0] rd_victim_sel; + assign rd_victim_sel = rd_victim_sel_r; + + reg [SAMP_CNT_WIDTH-1:0] zero_ns, zero_r, oneeighty_ns, oneeighty_r; + always @(posedge clk) zero_r <= #TCQ zero_ns; + always @(posedge clk) oneeighty_r <= #TCQ oneeighty_ns; + + wire [SAMP_CNT_WIDTH-1:0] samp_thresh = (complex_oclkdelay_calib_start + ? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0] + : SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]); + + wire [SAMP_CNT_WIDTH-1:0] samp_half_thresh = (complex_oclkdelay_calib_start + ? CMPLX_SAMPS_HALF_THRESH[SAMP_CNT_WIDTH-1:0] + : SIMP_SAMPS_HALF_THRESH[SAMP_CNT_WIDTH-1:0]); + + wire zero_ge_thresh = zero_r >= samp_thresh; + wire zero_le_half_thresh = zero_r <= samp_half_thresh; + wire oneeighty_ge_thresh = oneeighty_r >= samp_thresh; + wire oneeighty_le_half_thresh = oneeighty_r <= samp_half_thresh; + + reg [1:0] samp_result_ns, samp_result_r; + always @(posedge clk) samp_result_r <= #TCQ samp_result_ns; + always @(*) + if (rst) samp_result_ns = 'b0; + else begin + samp_result_ns = samp_result_r; + if (samp_valid) begin + if (~samp_result_r[0] && zero_ge_thresh) samp_result_ns[0] = 'b1; + if (samp_result_r[0] && zero_le_half_thresh) samp_result_ns[0] = 'b0; + if (~samp_result_r[1] && oneeighty_ge_thresh) samp_result_ns[1] = 'b1; + if (samp_result_r[1] && oneeighty_le_half_thresh) samp_result_ns[1] = 'b0; + end + end + + output [1:0] samp_result; + assign samp_result = samp_result_ns; + + reg [0:0] sm_ns, sm_r; + always @(posedge clk) sm_r <= #TCQ sm_ns; + + wire [DATA_CNT_WIDTH-1:0] data_cnt = complex_oclkdelay_calib_start + ? CMPLX_DATA_CNT[DATA_CNT_WIDTH-1:0] + : SIMP_DATA_CNT[DATA_CNT_WIDTH-1:0]; + wire [2:0] rd_victim_end = complex_oclkdelay_calib_start ? 3'h7 : 3'h0; + wire data_end = data_cnt_r == ONE[DATA_CNT_WIDTH-1:0]; + wire samp_end = samps_r == ONE[SAMP_CNT_WIDTH-1:0]; + + // Primary state machine. + + always @(*) begin + + // Default next state assignments. + + agg_samp_ns = agg_samp_r; + data_cnt_ns = data_cnt_r; + oclk_calib_resume_ns = 1'b0; + oneeighty_ns = oneeighty_r; + rd_victim_sel_ns = rd_victim_sel_r; + samp_done_ns = samp_done_r; + samps_ns = samps_r; + sm_ns = sm_r; + zero_ns = zero_r; + + if (rst == 1'b1) begin + // RESET next states + sm_ns = /*AK("READY")*/1'd0; + + end else + + // State based actions and next states. + case (sm_r) + + /*AL("READY")*/1'd0:begin + agg_samp_ns = NULL; + data_cnt_ns = data_cnt; + oneeighty_ns = 'b0; + zero_ns = 'b0; + rd_victim_sel_ns = 3'b0; + samps_ns = complex_oclkdelay_calib_start ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0] + : OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0]; + + + if (taps_set) begin + samp_done_ns = 1'b0; + sm_ns = /*AK("AWAITING_DATA")*/1'd1; + oclk_calib_resume_ns = 1'b1; + end + end + + /*AL("AWAITING_DATA")*/1'd1:begin + if (phy_rddata_en_1) begin + + case (agg_samp_r) + NULL : if (~&match) agg_samp_ns = match; + ZERO, ONEEIGHTY : if (~(agg_samp_r == match || &match)) agg_samp_ns = FUZZ; + FUZZ : ; + endcase // case (agg_samp_r) + + if (~data_end) data_cnt_ns = data_cnt_r - ONE[DATA_CNT_WIDTH-1:0]; + else begin + data_cnt_ns = data_cnt; + if (rd_victim_end != rd_victim_sel_r) rd_victim_sel_ns = rd_victim_sel_r + 3'h1; + else begin + rd_victim_sel_ns = 3'h0; + if (agg_samp_ns == ZERO) zero_ns = zero_r + ONE[SAMP_CNT_WIDTH-1:0]; + if (agg_samp_ns == ONEEIGHTY) oneeighty_ns = oneeighty_r + ONE[SAMP_CNT_WIDTH-1:0]; + agg_samp_ns = NULL; + if (~samp_end) samps_ns = samps_r - ONE[SAMP_CNT_WIDTH-1:0]; + else samp_done_ns = 1'b1; + end + end + + if (samp_done_ns) sm_ns = /*AK("READY")*/1'd0; + else oclk_calib_resume_ns = ~complex_oclkdelay_calib_start && data_end; + end + end + + endcase // case (sm_r) + end // always @ begin + + +endmodule // mig_7series_v4_0_ddr_phy_ocd_samp + +// Local Variables: +// verilog-autolabel-prefix: "1'd" +// End: diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_oclkdelay_cal.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_oclkdelay_cal.v new file mode 100644 index 0000000..e3a998f --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_oclkdelay_cal.v @@ -0,0 +1,552 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_oclkdelay_cal.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3 +// delay +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_oclkdelay_cal # + (parameter TCQ = 100, + parameter nCK_PER_CLK = 4, + parameter DRAM_WIDTH = 8, + parameter DQS_CNT_WIDTH = 3, + parameter DQS_WIDTH = 8, + parameter DQ_WIDTH = 64, + parameter MMCM_SAMP_WAIT = 10, + parameter OCAL_SIMPLE_SCAN_SAMPS = 2, + parameter PCT_SAMPS_SOLID = 95, + parameter POC_USE_METASTABLE_SAMP = "FALSE", + parameter SCAN_PCT_SAMPS_SOLID = 95, + parameter SIM_CAL_OPTION = "NONE", + parameter SAMPCNTRWIDTH = 8, + parameter SAMPLES = 128, + parameter TAPCNTRWIDTH = 7, + parameter TAPSPERKCLK = 56, + parameter BYPASS_COMPLEX_OCAL = "FALSE") + (/*AUTOARG*/ + // Outputs + wrlvl_final, rd_victim_sel, psincdec, psen, poc_error, po_stg23_sel, + po_stg23_incdec, po_en_stg23, oclkdelay_center_calib_start, + oclkdelay_center_calib_done, oclk_prech_req, + oclk_center_write_resume, oclk_calib_resume, + ocal_num_samples_done_r, lim2init_write_request, dbg_poc, + complex_wrlvl_final, complex_oclkdelay_calib_done, + oclkdelay_calib_cnt, dbg_phy_oclkdelay_cal, dbg_oclkdelay_rd_data, + oclkdelay_calib_done, lim_done, dbg_ocd_lim, + // Inputs + wl_po_fine_cnt, rst, psdone, prech_done, prbs_o, + prbs_ignore_last_bytes, prbs_ignore_first_byte, poc_sample_pd, + po_counter_read_val, phy_rddata_en, phy_rddata, oclkdelay_init_val, + oclkdelay_calib_start, ocal_num_samples_inc, metaQ, + complex_oclkdelay_calib_start, clk + ); + + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input clk; // To u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v, ... + input complex_oclkdelay_calib_start;// To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v, ... + input metaQ; // To u_poc of mig_7series_v4_0_poc_top.v + input ocal_num_samples_inc; // To u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v + input oclkdelay_calib_start; // To u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v + input [5:0] oclkdelay_init_val; // To u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v, ... + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;// To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v + input phy_rddata_en; // To u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v + input [8:0] po_counter_read_val; // To u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v, ... + input poc_sample_pd; // To u_poc of mig_7series_v4_0_poc_top.v + input prbs_ignore_first_byte; // To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v + input prbs_ignore_last_bytes; // To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; // To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v + input prech_done; // To u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v, ... + input psdone; // To u_poc of mig_7series_v4_0_poc_top.v + input rst; // To u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v, ... + input [6*DQS_WIDTH-1:0] wl_po_fine_cnt; // To u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v + // End of automatics + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output complex_oclkdelay_calib_done;// From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v + output complex_wrlvl_final; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v + output [1023:0] dbg_poc; // From u_poc of mig_7series_v4_0_poc_top.v + output lim2init_write_request; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v + output ocal_num_samples_done_r;// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + output oclk_calib_resume; // From u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v + output oclk_center_write_resume;// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + output oclk_prech_req; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v + output oclkdelay_center_calib_done;// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + output oclkdelay_center_calib_start;// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + output po_en_stg23; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v + output po_stg23_incdec; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v + output po_stg23_sel; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v + output poc_error; // From u_poc of mig_7series_v4_0_poc_top.v + output psen; // From u_poc of mig_7series_v4_0_poc_top.v + output psincdec; // From u_poc of mig_7series_v4_0_poc_top.v + output [2:0] rd_victim_sel; // From u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v + output wrlvl_final; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v + // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire f2o; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v + wire f2z; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v + wire [5:0] fuzz2oneeighty; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v + wire [5:0] fuzz2zero; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v + wire ktap_at_left_edge; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v + wire ktap_at_right_edge; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v + wire lim2init_prech_req; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v + wire [5:0] lim2ocal_stg3_left_lim; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v + wire [5:0] lim2ocal_stg3_right_lim;// From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v + wire lim2poc_ktap_right; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v + wire lim2poc_rdy; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v + wire lim2stg2_dec; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v + wire lim2stg2_inc; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v + wire lim2stg3_dec; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v + wire lim2stg3_inc; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v + wire lim_start; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v + wire [1:0] match; // From u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v + wire mmcm_edge_detect_done; // From u_poc of mig_7series_v4_0_poc_top.v + wire mmcm_edge_detect_rdy; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v + wire mmcm_lbclk_edge_aligned;// From u_poc of mig_7series_v4_0_poc_top.v + wire [1:0] ninety_offsets; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire o2f; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v + wire ocd2stg2_dec; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire ocd2stg2_inc; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire ocd2stg3_dec; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire ocd2stg3_inc; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire ocd_cntlr2stg2_dec; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v + wire ocd_edge_detect_rdy; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire ocd_ktap_left; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire ocd_ktap_right; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire ocd_prech_req; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v + wire [5:0] oneeighty2fuzz; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v + wire phy_rddata_en_1; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v + wire phy_rddata_en_2; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v + wire phy_rddata_en_3; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v + wire po_rdy; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v + wire poc_backup; // From u_poc of mig_7series_v4_0_poc_top.v + wire reset_scan; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v + wire [TAPCNTRWIDTH-1:0] rise_lead_right; // From u_poc of mig_7series_v4_0_poc_top.v + wire [TAPCNTRWIDTH-1:0] rise_trail_right; // From u_poc of mig_7series_v4_0_poc_top.v + wire samp_done; // From u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v + wire [1:0] samp_result; // From u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v + wire scan_done; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire scan_right; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v + wire scanning_right; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire [5:0] simp_stg3_final_sel; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire [5:0] stg3; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire taps_set; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire use_noise_window; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v + wire [5:0] wl_po_fine_cnt_sel; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v + wire z2f; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v + wire [5:0] zero2fuzz; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v + // End of automatics + wire [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final; + wire ocal_scan_win_not_found; + + + output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + output [255:0] dbg_phy_oclkdelay_cal; + output [16*DRAM_WIDTH-1:0] dbg_oclkdelay_rd_data; + output oclkdelay_calib_done; + + output lim_done; + output [255:0] dbg_ocd_lim; + + // Debug signals + assign dbg_phy_oclkdelay_cal[0] = f2o; + assign dbg_phy_oclkdelay_cal[1] = f2z; + assign dbg_phy_oclkdelay_cal[2] = o2f; + assign dbg_phy_oclkdelay_cal[3] = z2f; + assign dbg_phy_oclkdelay_cal[4+:6] = fuzz2oneeighty; + assign dbg_phy_oclkdelay_cal[10+:6] = fuzz2zero; + assign dbg_phy_oclkdelay_cal[16+:6] = oneeighty2fuzz; + assign dbg_phy_oclkdelay_cal[22+:6] = zero2fuzz; + assign dbg_phy_oclkdelay_cal[28+:3] = oclkdelay_calib_cnt; + assign dbg_phy_oclkdelay_cal[31] = oclkdelay_calib_start; + assign dbg_phy_oclkdelay_cal[32] = lim_done; + assign dbg_phy_oclkdelay_cal[33+:6] =lim2ocal_stg3_left_lim ; + assign dbg_phy_oclkdelay_cal[39+:6] = lim2ocal_stg3_right_lim ; + assign dbg_phy_oclkdelay_cal[45+:8] = po_counter_read_val[8:0]; + assign dbg_phy_oclkdelay_cal[53+:54] = simp_stg3_final[DQS_WIDTH*6-1:0]; + assign dbg_phy_oclkdelay_cal[107] = ocal_scan_win_not_found; + assign dbg_phy_oclkdelay_cal[108] = oclkdelay_center_calib_start; + assign dbg_phy_oclkdelay_cal[109] = oclkdelay_center_calib_done; + assign dbg_phy_oclkdelay_cal[115:110] = stg3[5:0]; + + /*mig_7series_v4_0_ddr_phy_ocd_lim AUTO_TEMPLATE( + .TDQSS_DEGREES (), + .wl_po_fine_cnt (wl_po_fine_cnt_sel[5:0]), + .poc2lim_detect_done (mmcm_edge_detect_done), + .poc2lim_fall_align_taps_.* ({TAPCNTRWIDTH{1'b0}}), + .poc2lim_rise_align_taps_lead (rise_lead_right), + .poc2lim_rise_align_taps_trail (rise_trail_right),); */ + + mig_7series_v4_0_ddr_phy_ocd_lim # + (/*AUTOINSTPARAM*/ + // Parameters + .BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ), + .TDQSS_DEGREES ()) // Templated + u_ocd_lim + (/*AUTOINST*/ + // Outputs + .dbg_ocd_lim (dbg_ocd_lim[255:0]), + .lim2init_prech_req (lim2init_prech_req), + .lim2init_write_request (lim2init_write_request), + .lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]), + .lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]), + .lim2poc_ktap_right (lim2poc_ktap_right), + .lim2poc_rdy (lim2poc_rdy), + .lim2stg2_dec (lim2stg2_dec), + .lim2stg2_inc (lim2stg2_inc), + .lim2stg3_dec (lim2stg3_dec), + .lim2stg3_inc (lim2stg3_inc), + .lim_done (lim_done), + // Inputs + .clk (clk), + .lim_start (lim_start), + .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), + .oclkdelay_calib_done (oclkdelay_calib_done), + .oclkdelay_init_val (oclkdelay_init_val[5:0]), + .po_rdy (po_rdy), + .poc2lim_detect_done (mmcm_edge_detect_done), // Templated + .poc2lim_fall_align_taps_lead ({TAPCNTRWIDTH{1'b0}}), // Templated + .poc2lim_fall_align_taps_trail ({TAPCNTRWIDTH{1'b0}}), // Templated + .poc2lim_rise_align_taps_lead (rise_lead_right), // Templated + .poc2lim_rise_align_taps_trail (rise_trail_right), // Templated + .prech_done (prech_done), + .rst (rst), + .simp_stg3_final_sel (simp_stg3_final_sel[5:0]), + .wl_po_fine_cnt (wl_po_fine_cnt_sel[5:0])); // Templated + + /*mig_7series_v4_0_poc_top AUTO_TEMPLATE( + .CCENABLE (0), + .LANE_CNT_WIDTH (DQS_CNT_WIDTH), + .SCANFROMRIGHT (1), + .lane (oclkdelay_calib_cnt[DQS_CNT_WIDTH-1:0]), + .pd_out (metaQ),); */ + + mig_7series_v4_0_poc_top # + (/*AUTOINSTPARAM*/ + // Parameters + .CCENABLE (0), // Templated + .LANE_CNT_WIDTH (DQS_CNT_WIDTH), // Templated + .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), + .PCT_SAMPS_SOLID (PCT_SAMPS_SOLID), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), + .SAMPCNTRWIDTH (SAMPCNTRWIDTH), + .SAMPLES (SAMPLES), + .SCANFROMRIGHT (1), // Templated + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ)) + u_poc + (/*AUTOINST*/ + // Outputs + .dbg_poc (dbg_poc[1023:0]), + .mmcm_edge_detect_done (mmcm_edge_detect_done), + .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), + .poc_backup (poc_backup), + .poc_error (poc_error), + .psen (psen), + .psincdec (psincdec), + .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), + .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), + // Inputs + .clk (clk), + .ktap_at_left_edge (ktap_at_left_edge), + .ktap_at_right_edge (ktap_at_right_edge), + .lane (oclkdelay_calib_cnt[DQS_CNT_WIDTH-1:0]), // Templated + .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), + .ninety_offsets (ninety_offsets[1:0]), + .pd_out (metaQ), // Templated + .poc_sample_pd (poc_sample_pd), + .psdone (psdone), + .rst (rst), + .use_noise_window (use_noise_window)); + + /*mig_7series_v4_0_ddr_phy_ocd_mux AUTO_TEMPLATE( + .po_stg3_incdec (), + .po_en_stg3 (),); */ + + mig_7series_v4_0_ddr_phy_ocd_mux # + (/*AUTOINSTPARAM*/ + // Parameters + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .TCQ (TCQ)) + u_ocd_mux + (/*AUTOINST*/ + // Outputs + .ktap_at_left_edge (ktap_at_left_edge), + .ktap_at_right_edge (ktap_at_right_edge), + .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), + .oclk_prech_req (oclk_prech_req), + .po_en_stg23 (po_en_stg23), + .po_en_stg3 (), // Templated + .po_rdy (po_rdy), + .po_stg23_incdec (po_stg23_incdec), + .po_stg23_sel (po_stg23_sel), + .po_stg3_incdec (), // Templated + .wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]), + // Inputs + .clk (clk), + .lim2init_prech_req (lim2init_prech_req), + .lim2poc_ktap_right (lim2poc_ktap_right), + .lim2poc_rdy (lim2poc_rdy), + .lim2stg2_dec (lim2stg2_dec), + .lim2stg2_inc (lim2stg2_inc), + .lim2stg3_dec (lim2stg3_dec), + .lim2stg3_inc (lim2stg3_inc), + .ocd2stg2_dec (ocd2stg2_dec), + .ocd2stg2_inc (ocd2stg2_inc), + .ocd2stg3_dec (ocd2stg3_dec), + .ocd2stg3_inc (ocd2stg3_inc), + .ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec), + .ocd_edge_detect_rdy (ocd_edge_detect_rdy), + .ocd_ktap_left (ocd_ktap_left), + .ocd_ktap_right (ocd_ktap_right), + .ocd_prech_req (ocd_prech_req), + .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), + .rst (rst), + .wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0])); + + mig_7series_v4_0_ddr_phy_ocd_data # + (/*AUTOINSTPARAM*/ + // Parameters + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK)) + u_ocd_data + (/*AUTOINST*/ + // Outputs + .match (match[1:0]), + // Inputs + .clk (clk), + .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), + .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), + .phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]), + .phy_rddata_en_1 (phy_rddata_en_1), + .prbs_ignore_first_byte (prbs_ignore_first_byte), + .prbs_ignore_last_bytes (prbs_ignore_last_bytes), + .prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]), + .rst (rst)); + + mig_7series_v4_0_ddr_phy_ocd_samp # + (/*AUTOINSTPARAM*/ + // Parameters + .OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS), + .SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK)) + u_ocd_samp + (/*AUTOINST*/ + // Outputs + .oclk_calib_resume (oclk_calib_resume), + .rd_victim_sel (rd_victim_sel[2:0]), + .samp_done (samp_done), + .samp_result (samp_result[1:0]), + // Inputs + .clk (clk), + .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), + .match (match[1:0]), + .ocal_num_samples_inc (ocal_num_samples_inc), + .phy_rddata_en_1 (phy_rddata_en_1), + .phy_rddata_en_2 (phy_rddata_en_2), + .reset_scan (reset_scan), + .rst (rst), + .taps_set (taps_set)); + + mig_7series_v4_0_ddr_phy_ocd_edge # + (/*AUTOINSTPARAM*/ + // Parameters + .TCQ (TCQ)) + u_ocd_edge + (/*AUTOINST*/ + // Outputs + .f2o (f2o), + .f2z (f2z), + .fuzz2oneeighty (fuzz2oneeighty[5:0]), + .fuzz2zero (fuzz2zero[5:0]), + .o2f (o2f), + .oneeighty2fuzz (oneeighty2fuzz[5:0]), + .scan_right (scan_right), + .z2f (z2f), + .zero2fuzz (zero2fuzz[5:0]), + // Inputs + .clk (clk), + .phy_rddata_en_2 (phy_rddata_en_2), + .reset_scan (reset_scan), + .samp_done (samp_done), + .samp_result (samp_result[1:0]), + .scanning_right (scanning_right), + .stg3 (stg3[5:0])); + + /*mig_7series_v4_0_ddr_phy_ocd_cntlr AUTO_TEMPLATE( + .oclk_init_delay_done (),); */ + + mig_7series_v4_0_ddr_phy_ocd_cntlr # + (/*AUTOINSTPARAM*/ + // Parameters + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .TCQ (TCQ)) + u_ocd_cntlr + (/*AUTOINST*/ + // Outputs + .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done), + .complex_wrlvl_final (complex_wrlvl_final), + .lim_start (lim_start), + .ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec), + .ocd_prech_req (ocd_prech_req), + .oclk_init_delay_done (), // Templated + .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), + .oclkdelay_calib_done (oclkdelay_calib_done), + .phy_rddata_en_1 (phy_rddata_en_1), + .phy_rddata_en_2 (phy_rddata_en_2), + .phy_rddata_en_3 (phy_rddata_en_3), + .reset_scan (reset_scan), + .wrlvl_final (wrlvl_final), + // Inputs + .clk (clk), + .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), + .lim_done (lim_done), + .oclkdelay_calib_start (oclkdelay_calib_start), + .phy_rddata_en (phy_rddata_en), + .po_counter_read_val (po_counter_read_val[8:0]), + .po_rdy (po_rdy), + .prech_done (prech_done), + .rst (rst), + .scan_done (scan_done)); + + + mig_7series_v4_0_ddr_phy_ocd_po_cntlr # + (/*AUTOINSTPARAM*/ + // Parameters + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .SAMPLES (SAMPLES), + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK)) + u_ocd_po_cntlr + (.cmplx_stg3_final (cmplx_stg3_final[DQS_WIDTH*6-1:0]), + .ocal_scan_win_not_found (ocal_scan_win_not_found), + .simp_stg3_final (simp_stg3_final[DQS_WIDTH*6-1:0]), + /*AUTOINST*/ + // Outputs + .ninety_offsets (ninety_offsets[1:0]), + .ocal_num_samples_done_r (ocal_num_samples_done_r), + .ocd2stg2_dec (ocd2stg2_dec), + .ocd2stg2_inc (ocd2stg2_inc), + .ocd2stg3_dec (ocd2stg3_dec), + .ocd2stg3_inc (ocd2stg3_inc), + .ocd_edge_detect_rdy (ocd_edge_detect_rdy), + .ocd_ktap_left (ocd_ktap_left), + .ocd_ktap_right (ocd_ktap_right), + .oclk_center_write_resume (oclk_center_write_resume), + .oclkdelay_center_calib_done (oclkdelay_center_calib_done), + .oclkdelay_center_calib_start (oclkdelay_center_calib_start), + .scan_done (scan_done), + .scanning_right (scanning_right), + .simp_stg3_final_sel (simp_stg3_final_sel[5:0]), + .stg3 (stg3[5:0]), + .taps_set (taps_set), + .use_noise_window (use_noise_window), + // Inputs + .clk (clk), + .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), + .f2o (f2o), + .f2z (f2z), + .fuzz2oneeighty (fuzz2oneeighty[5:0]), + .fuzz2zero (fuzz2zero[5:0]), + .lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]), + .lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]), + .mmcm_edge_detect_done (mmcm_edge_detect_done), + .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), + .o2f (o2f), + .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), + .oclkdelay_init_val (oclkdelay_init_val[5:0]), + .oneeighty2fuzz (oneeighty2fuzz[5:0]), + .phy_rddata_en_3 (phy_rddata_en_3), + .po_counter_read_val (po_counter_read_val[8:0]), + .po_rdy (po_rdy), + .poc_backup (poc_backup), + .reset_scan (reset_scan), + .rst (rst), + .samp_done (samp_done), + .scan_right (scan_right), + .wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]), + .z2f (z2f), + .zero2fuzz (zero2fuzz[5:0])); + + +endmodule // mig_7series_v4_0_ddr_phy_oclkdelay_cal + +// Local Variables: +// verilog-library-directories:(".") +// verilog-library-extensions:(".v") +// End: diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_prbs_rdlvl.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_prbs_rdlvl.v new file mode 100644 index 0000000..b61456d --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_prbs_rdlvl.v @@ -0,0 +1,5683 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: +// \ \ Application: MIG +// / / Filename: ddr_phy_prbs_rdlvl.v +// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// PRBS Read leveling calibration logic +// NOTES: +// 1. Window detection with PRBS pattern. +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_prbs_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $ +**$Date: 2011/06/24 14:49:00 $ +**$Author: mgeorge $ +**$Revision: 1.2 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_prbs_rdlvl.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_prbs_rdlvl # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter nCK_PER_CLK = 2, // # of memory clocks per CLK + parameter DQ_WIDTH = 64, // # of DQ (data) + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter RANKS = 1, // # of DRAM ranks + parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps + parameter PRBS_WIDTH = 8, // PRBS generator output width + parameter FIXED_VICTIM = "TRUE", // No victim rotation when "TRUE" + parameter FINE_PER_BIT = "ON", + parameter CENTER_COMP_MODE = "ON", + parameter PI_VAL_ADJ = "ON" + ) + ( + input clk, + input rst, + // Calibration status, control signals + input prbs_rdlvl_start, + (* max_fanout = 100 *) output reg prbs_rdlvl_done, + output reg prbs_last_byte_done, + output reg prbs_rdlvl_prech_req, + input complex_sample_cnt_inc, + input prech_done, + input phy_if_empty, + // Captured data in fabric clock domain + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, + //Expected data from PRBS generator + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] compare_data, + // Decrement initial Phaser_IN Fine tap delay + input [5:0] pi_counter_read_val, + // Stage 1 calibration outputs + output reg pi_en_stg2_f, + output reg pi_stg2_f_incdec, + output [255:0] dbg_prbs_rdlvl, + output [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt, + output reg [2:0] rd_victim_sel, + output reg complex_victim_inc, + output reg reset_rd_addr, + + output reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r, + output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, + output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps, + output reg [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit + output reg fine_delay_sel, //fine delay selection - actual update of fine delay + output reg num_samples_done_r, + input complex_act_start, //read is done. ready for PI movement + output complex_init_pi_dec_done, //Initial PI incdec is done. ready for start + output reg complex_pi_incdec_done //PI incdec is done. ready for Read + ); + + + + + localparam [5:0] PRBS_IDLE = 6'h00; + localparam [5:0] PRBS_NEW_DQS_WAIT = 6'h01; + localparam [5:0] PRBS_PAT_COMPARE = 6'h02; + localparam [5:0] PRBS_DEC_DQS = 6'h03; + localparam [5:0] PRBS_DEC_DQS_WAIT = 6'h04; + localparam [5:0] PRBS_INC_DQS = 6'h05; + localparam [5:0] PRBS_INC_DQS_WAIT = 6'h06; + localparam [5:0] PRBS_CALC_TAPS = 6'h07; + localparam [5:0] PRBS_NEXT_DQS = 6'h08; + localparam [5:0] PRBS_NEW_DQS_PREWAIT = 6'h09; + localparam [5:0] PRBS_DONE = 6'h0A; + localparam [5:0] PRBS_CALC_TAPS_PRE = 6'h0B; + localparam [5:0] PRBS_CALC_TAPS_WAIT = 6'h0C; + + localparam [5:0] FINE_PI_DEC = 6'h0D; //go back to all fail or back to center + localparam [5:0] FINE_PI_DEC_WAIT = 6'h0E; //wait for PI tap dec settle + localparam [5:0] FINE_PI_INC = 6'h0F; //increse up to 1 fail + localparam [5:0] FINE_PI_INC_WAIT = 6'h10; //wait for PI tap int settle + localparam [5:0] FINE_PAT_COMPARE_PER_BIT = 6'h11; //compare per bit error and check left/right/gain/loss + localparam [5:0] FINE_CALC_TAPS = 6'h12; //setup fine_delay_incdec_pb for better window size + localparam [5:0] FINE_CALC_TAPS_WAIT = 6'h13; //wait for ROM value for dec cnt + localparam [5:0] RD_DONE_WAIT_FOR_PI_INC_INC = 6'h14; //wait for read is done before PI inc + localparam [5:0] RD_DONE_WAIT_FOR_PI_INC_DEC = 6'h15; //wait for read is done before PI dec + + localparam [11:0] NUM_SAMPLES_CNT = (SIM_CAL_OPTION == "NONE") ? 'd12 : 12'h001; //MG from 50 + localparam [11:0] NUM_SAMPLES_CNT1 = (SIM_CAL_OPTION == "NONE") ? 'd20 : 12'h001; + localparam [11:0] NUM_SAMPLES_CNT2 = (SIM_CAL_OPTION == "NONE") ? 'd10 : 12'h001; + + //minimum valid window for centering + localparam MIN_WIN = 8; + localparam [MIN_WIN-1:0] MATCH_ALL_ONE = {MIN_WIN{1'b1}}; + localparam [MIN_WIN-1:0] MIN_PASS = {MIN_WIN{1'b0}}; //8'b00000000 + localparam [MIN_WIN-1:0] MIN_LEFT = {1'b1,{{MIN_WIN-1}{1'b0}}}; //8'b10000000 + + wire [DQS_CNT_WIDTH+2:0]prbs_dqs_cnt_timing; + reg [DQS_CNT_WIDTH+2:0] prbs_dqs_cnt_timing_r; + reg [DQS_CNT_WIDTH:0] prbs_dqs_cnt_r; + reg prbs_prech_req_r; + reg [5:0] prbs_state_r; + reg [5:0] prbs_state_r1; + reg wait_state_cnt_en_r; + reg [3:0] wait_state_cnt_r; + reg cnt_wait_state; + reg err_chk_invalid; + // reg found_edge_r; + reg prbs_found_1st_edge_r; + reg prbs_found_2nd_edge_r; + reg [5:0] prbs_1st_edge_taps_r; + // reg found_stable_eye_r; + reg [5:0] prbs_dqs_tap_cnt_r; + reg [5:0] prbs_dec_tap_calc_plus_3; + reg [5:0] prbs_dec_tap_calc_minus_3; + reg prbs_dqs_tap_limit_r; + reg [5:0] prbs_inc_tap_cnt; + reg [5:0] prbs_dec_tap_cnt; + reg [DRAM_WIDTH-1:0] mux_rd_fall0_r1; + reg [DRAM_WIDTH-1:0] mux_rd_fall1_r1; + reg [DRAM_WIDTH-1:0] mux_rd_rise0_r1; + reg [DRAM_WIDTH-1:0] mux_rd_rise1_r1; + reg [DRAM_WIDTH-1:0] mux_rd_fall2_r1; + reg [DRAM_WIDTH-1:0] mux_rd_fall3_r1; + reg [DRAM_WIDTH-1:0] mux_rd_rise2_r1; + reg [DRAM_WIDTH-1:0] mux_rd_rise3_r1; + reg [DRAM_WIDTH-1:0] mux_rd_fall0_r2; + reg [DRAM_WIDTH-1:0] mux_rd_fall1_r2; + reg [DRAM_WIDTH-1:0] mux_rd_rise0_r2; + reg [DRAM_WIDTH-1:0] mux_rd_rise1_r2; + reg [DRAM_WIDTH-1:0] mux_rd_fall2_r2; + reg [DRAM_WIDTH-1:0] mux_rd_fall3_r2; + reg [DRAM_WIDTH-1:0] mux_rd_rise2_r2; + reg [DRAM_WIDTH-1:0] mux_rd_rise3_r2; + reg [DRAM_WIDTH-1:0] mux_rd_fall0_r3; + reg [DRAM_WIDTH-1:0] mux_rd_fall1_r3; + reg [DRAM_WIDTH-1:0] mux_rd_rise0_r3; + reg [DRAM_WIDTH-1:0] mux_rd_rise1_r3; + reg [DRAM_WIDTH-1:0] mux_rd_fall2_r3; + reg [DRAM_WIDTH-1:0] mux_rd_fall3_r3; + reg [DRAM_WIDTH-1:0] mux_rd_rise2_r3; + reg [DRAM_WIDTH-1:0] mux_rd_rise3_r3; + reg [DRAM_WIDTH-1:0] mux_rd_fall0_r4; + reg [DRAM_WIDTH-1:0] mux_rd_fall1_r4; + reg [DRAM_WIDTH-1:0] mux_rd_rise0_r4; + reg [DRAM_WIDTH-1:0] mux_rd_rise1_r4; + reg [DRAM_WIDTH-1:0] mux_rd_fall2_r4; + reg [DRAM_WIDTH-1:0] mux_rd_fall3_r4; + reg [DRAM_WIDTH-1:0] mux_rd_rise2_r4; + reg [DRAM_WIDTH-1:0] mux_rd_rise3_r4; + reg mux_rd_valid_r; + reg rd_valid_r1; + reg rd_valid_r2; + reg rd_valid_r3; + reg new_cnt_dqs_r; + reg prbs_tap_en_r; + reg prbs_tap_inc_r; + reg pi_en_stg2_f_timing; + reg pi_stg2_f_incdec_timing; + wire [DQ_WIDTH-1:0] rd_data_rise0; + wire [DQ_WIDTH-1:0] rd_data_fall0; + wire [DQ_WIDTH-1:0] rd_data_rise1; + wire [DQ_WIDTH-1:0] rd_data_fall1; + wire [DQ_WIDTH-1:0] rd_data_rise2; + wire [DQ_WIDTH-1:0] rd_data_fall2; + wire [DQ_WIDTH-1:0] rd_data_rise3; + wire [DQ_WIDTH-1:0] rd_data_fall3; + wire [DQ_WIDTH-1:0] compare_data_r0; + wire [DQ_WIDTH-1:0] compare_data_f0; + wire [DQ_WIDTH-1:0] compare_data_r1; + wire [DQ_WIDTH-1:0] compare_data_f1; + wire [DQ_WIDTH-1:0] compare_data_r2; + wire [DQ_WIDTH-1:0] compare_data_f2; + wire [DQ_WIDTH-1:0] compare_data_r3; + wire [DQ_WIDTH-1:0] compare_data_f3; + reg [DRAM_WIDTH-1:0] compare_data_rise0_r1; + reg [DRAM_WIDTH-1:0] compare_data_fall0_r1; + reg [DRAM_WIDTH-1:0] compare_data_rise1_r1; + reg [DRAM_WIDTH-1:0] compare_data_fall1_r1; + reg [DRAM_WIDTH-1:0] compare_data_rise2_r1; + reg [DRAM_WIDTH-1:0] compare_data_fall2_r1; + reg [DRAM_WIDTH-1:0] compare_data_rise3_r1; + reg [DRAM_WIDTH-1:0] compare_data_fall3_r1; + reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; + reg [5:0] prbs_2nd_edge_taps_r; + + // reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r; + reg [5:0] rdlvl_cpt_tap_cnt; + reg prbs_rdlvl_start_r; + + reg compare_err; + reg compare_err_r0; + reg compare_err_f0; + reg compare_err_r1; + reg compare_err_f1; + reg compare_err_r2; + reg compare_err_f2; + reg compare_err_r3; + reg compare_err_f3; + reg compare_err_latch; + + reg samples_cnt1_en_r; + reg samples_cnt2_en_r; + reg [11:0] samples_cnt_r; + reg num_samples_done_ind; //indicate num_samples_done_r is set in FINE_PAT_COMPARE_PER_BIT to prevent victim_sel_rd out of sync + reg [DQS_WIDTH-1:0] prbs_tap_mod; + + //reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps; + //reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps; + + //************************************************************************** + // signals for per-bit algorithm of fine_delay calculations + //************************************************************************** + reg [6*DRAM_WIDTH-1:0] left_edge_pb; //left edge value per bit + reg [6*DRAM_WIDTH-1:0] right_edge_pb; //right edge value per bit + reg [MIN_WIN*DRAM_WIDTH-1:0] match_flag_pb; //5 consecutive match flag per bit + reg [MIN_WIN-1:0] match_flag_and; //5 consecute match flag of all bits (1: all bit fail) + reg [MIN_WIN-1:0] match_flag_or; //5 consecute match flag of all bits (1: any bit fail) + reg [DRAM_WIDTH-1:0] left_edge_found_pb; //left_edge found per bit - use for loss calculation + reg [DRAM_WIDTH-1:0] left_edge_updated; //left edge was updated for this PI tap - used for largest left edge /ref bit update + reg [DRAM_WIDTH-1:0] right_edge_found_pb; //right_edge found per bit - use for gail calulation and smallest right edge update + reg right_edge_found; //smallest right_edge found + reg [DRAM_WIDTH*6-1:0] left_loss_pb; //left_edge loss per bit + reg [DRAM_WIDTH*6-1:0] right_gain_pb; //right_edge gain per bit + reg [DRAM_WIDTH-1:0] ref_bit; //bit number which has largest left edge (with smaller right edge) + reg [DRAM_WIDTH-1:0] bit_cnt; //bit number used to calculate ref bit + reg [DRAM_WIDTH-1:0] ref_bit_per_bit; //bit flags which have largest left edge + reg [5:0] ref_right_edge; //ref_bit right edge - keep the smallest edge of ref bits + reg [5:0] largest_left_edge; //biggest left edge of per bit - will be left edge of byte + reg [5:0] smallest_right_edge; //smallest right edge of per bit - will be right edge of byte + reg [5:0] fine_pi_dec_cnt; //Phase In tap decrement count (to go back to '0' or center) + reg [6:0] center_calc; //used for calculate the dec tap for centering + reg [5:0] right_edge_ref; //ref_bit right edge + reg [5:0] left_edge_ref; //ref_bit left edge + + reg [DRAM_WIDTH-1:0] compare_err_pb; //compare error per bit + reg [DRAM_WIDTH-1:0] compare_err_pb_latch_r; //sticky compare error per bit used for left/right edge + reg compare_err_pb_and; //indicate all bit fail + reg compare_err_pb_or; //indicate any bit fail + reg fine_inc_stage; //fine_inc_stage (1: increment all except ref_bit, 0: only inc for gain bit) + reg [1:0] stage_cnt; //stage cnt (0,1: fine delay inc stage, 2: fine delay dec stage) + wire fine_calib; //turn on/off fine delay calibration + + reg [5:0] mem_out_dec; + reg [5:0] dec_cnt; + reg fine_dly_error; //indicate it has wrong left/right edge + reg edge_det_error; //indicate it has wrong left/right edge + + wire center_comp; + wire pi_adj; + + reg no_err_win_detected; + reg no_err_win_detected_latch; + reg [1:0] valid_window_cnt; //number of valid window in the scan + reg double_window_ind; //indication of double window + + //if inital PI dec is not done, init SM should wait until it is done + reg complex_init_pi_dec_done_r; //if inital PI dec is not done, init SM should wait until it is done + wire complex_rdlvl_err; + + //************************************************************************** + // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 + // coarse delay + //************************************************************************** + assign pi_stg2_prbs_rdlvl_cnt = prbs_dqs_cnt_r; + + //fine delay turn on + assign fine_calib = (FINE_PER_BIT=="ON")? 1:0; + assign center_comp = (CENTER_COMP_MODE == "ON")? 1: 0; + assign pi_adj = (PI_VAL_ADJ == "ON")?1:0; + + //Debug error flag + assign complex_rdlvl_err = fine_dly_error | edge_det_error; + + //initial dec is only happening for per-bit + assign complex_init_pi_dec_done = fine_calib? complex_init_pi_dec_done_r : 1'b1; + + assign dbg_prbs_rdlvl[0+:6] = left_edge_pb[0+:6]; + assign dbg_prbs_rdlvl[7:6] = left_loss_pb[0+:2]; + assign dbg_prbs_rdlvl[8+:6] = left_edge_pb[6+:6]; + assign dbg_prbs_rdlvl[15:14] = left_loss_pb[6+:2]; + assign dbg_prbs_rdlvl[16+:6] = left_edge_pb[12+:6] ; + assign dbg_prbs_rdlvl[23:22] = left_loss_pb[12+:2]; + assign dbg_prbs_rdlvl[24+:6] = left_edge_pb[18+:6] ; + assign dbg_prbs_rdlvl[31:30] = left_loss_pb[18+:2]; + assign dbg_prbs_rdlvl[32+:6] = left_edge_pb[24+:6]; + assign dbg_prbs_rdlvl[39:38] = left_loss_pb[24+:2]; + assign dbg_prbs_rdlvl[40+:6] = left_edge_pb[30+:6]; + assign dbg_prbs_rdlvl[47:46] = left_loss_pb[30+:2]; + assign dbg_prbs_rdlvl[48+:6] = left_edge_pb[36+:6]; + assign dbg_prbs_rdlvl[55:54] = left_loss_pb[36+:2]; + assign dbg_prbs_rdlvl[56+:6] = left_edge_pb[42+:6]; + assign dbg_prbs_rdlvl[63:62] = left_loss_pb[42+:2]; + + assign dbg_prbs_rdlvl[64+:6] = right_edge_pb[0+:6]; + assign dbg_prbs_rdlvl[71:70] = right_gain_pb[0+:2]; + assign dbg_prbs_rdlvl[72+:6] = right_edge_pb[6+:6] ; + assign dbg_prbs_rdlvl[79:78] = right_gain_pb[6+:2]; + assign dbg_prbs_rdlvl[80+:6] = right_edge_pb[12+:6]; + assign dbg_prbs_rdlvl[87:86] = right_gain_pb[12+:2]; + assign dbg_prbs_rdlvl[88+:6] = right_edge_pb[18+:6]; + assign dbg_prbs_rdlvl[95:94] = right_gain_pb[18+:2]; + assign dbg_prbs_rdlvl[96+:6] = right_edge_pb[24+:6]; + assign dbg_prbs_rdlvl[103:102] = right_gain_pb[24+:2]; + assign dbg_prbs_rdlvl[104+:6] = right_edge_pb[30+:6]; + assign dbg_prbs_rdlvl[111:110] = right_gain_pb[30+:2]; + assign dbg_prbs_rdlvl[112+:6] = right_edge_pb[36+:6]; + assign dbg_prbs_rdlvl[119:118] = right_gain_pb[36+:2]; + assign dbg_prbs_rdlvl[120+:6] = right_edge_pb[42+:6]; + assign dbg_prbs_rdlvl[127:126] = right_gain_pb[42+:2]; + + assign dbg_prbs_rdlvl[128+:6] = pi_counter_read_val; + assign dbg_prbs_rdlvl[134+:6] = prbs_dqs_tap_cnt_r; + + assign dbg_prbs_rdlvl[140] = prbs_found_1st_edge_r; + assign dbg_prbs_rdlvl[141] = prbs_found_2nd_edge_r; + assign dbg_prbs_rdlvl[142] = compare_err; + assign dbg_prbs_rdlvl[143] = phy_if_empty; + assign dbg_prbs_rdlvl[144] = prbs_rdlvl_start; + assign dbg_prbs_rdlvl[145] = prbs_rdlvl_done; + assign dbg_prbs_rdlvl[146+:5] = prbs_dqs_cnt_r; + assign dbg_prbs_rdlvl[151+:6] = left_edge_pb[prbs_dqs_cnt_r*6+:6] ; + assign dbg_prbs_rdlvl[157+:6] = right_edge_pb[prbs_dqs_cnt_r*6+:6]; + assign dbg_prbs_rdlvl[163+:6] = {2'h0,complex_victim_inc, rd_victim_sel[2:0]}; + assign dbg_prbs_rdlvl[169+:6] =right_gain_pb[prbs_dqs_cnt_r*6+:6] ; + assign dbg_prbs_rdlvl[177:175] = ref_bit[2:0]; + + assign dbg_prbs_rdlvl[178+:6] = prbs_state_r1[5:0]; + assign dbg_prbs_rdlvl[184] = rd_valid_r2; + assign dbg_prbs_rdlvl[185] = compare_err_r0; + assign dbg_prbs_rdlvl[186] = compare_err_f0; + assign dbg_prbs_rdlvl[187] = compare_err_r1; + assign dbg_prbs_rdlvl[188] = compare_err_f1; + assign dbg_prbs_rdlvl[189] = compare_err_r2; + assign dbg_prbs_rdlvl[190] = compare_err_f2; + assign dbg_prbs_rdlvl[191] = compare_err_r3; + assign dbg_prbs_rdlvl[192] = compare_err_f3; + assign dbg_prbs_rdlvl[193+:8] = left_edge_found_pb; + assign dbg_prbs_rdlvl[201+:8] = right_edge_found_pb; + assign dbg_prbs_rdlvl[209+:6] =largest_left_edge ; + assign dbg_prbs_rdlvl[215+:6] =smallest_right_edge ; + assign dbg_prbs_rdlvl[221+:8] = fine_delay_incdec_pb; + assign dbg_prbs_rdlvl[229] = fine_delay_sel; + assign dbg_prbs_rdlvl[230+:8] = compare_err_pb_latch_r; + assign dbg_prbs_rdlvl[238+:6] = fine_pi_dec_cnt; + assign dbg_prbs_rdlvl[244+:5] = match_flag_and[4:0]; + assign dbg_prbs_rdlvl[249+:2] = stage_cnt; + assign dbg_prbs_rdlvl[251] = fine_inc_stage; + assign dbg_prbs_rdlvl[252] = compare_err_pb_and; + assign dbg_prbs_rdlvl[253] = right_edge_found; + assign dbg_prbs_rdlvl[254] = complex_rdlvl_err; + assign dbg_prbs_rdlvl[255] = double_window_ind; + + //************************************************************************** + // Record first and second edges found during calibration + //************************************************************************** + generate + always @(posedge clk) + if (rst) begin + dbg_prbs_first_edge_taps <= #TCQ 'b0; + dbg_prbs_second_edge_taps <= #TCQ 'b0; + end else if (prbs_state_r == PRBS_CALC_TAPS) begin + // Record tap counts of first and second edge edges during + // calibration for each DQS group. If neither edge has + // been found, then those taps will remain 0 + if (prbs_found_1st_edge_r) + dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] + <= #TCQ prbs_1st_edge_taps_r; + if (prbs_found_2nd_edge_r) + dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] + <= #TCQ prbs_2nd_edge_taps_r; + end else if (prbs_state_r == FINE_CALC_TAPS) begin + if(stage_cnt == 'd2) begin + dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] + <= #TCQ largest_left_edge; + dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] + <= #TCQ smallest_right_edge; + end + end + endgenerate + + //double window indication flag + always @ (posedge clk) + if (rst) double_window_ind <= #TCQ 1'd0; + else double_window_ind <= #TCQ double_window_ind? 1'b1: (valid_window_cnt > 1); + + //padded calculation + always @ (smallest_right_edge or largest_left_edge) + center_calc <= {1'b0, smallest_right_edge} + {1'b0,largest_left_edge}; + //*************************************************************************** + //*************************************************************************** + // Data mux to route appropriate bit to calibration logic - i.e. calibration + // is done sequentially, one bit (or DQS group) at a time + //*************************************************************************** + + generate + if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk + assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; + assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; + assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; + assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; + assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; + assign compare_data_r0 = compare_data[DQ_WIDTH-1:0]; + assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + assign compare_data_r2 = compare_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; + assign compare_data_f2 = compare_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; + assign compare_data_r3 = compare_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; + assign compare_data_f3 = compare_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; + end else begin: rd_data_div2_logic_clk + assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; + assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + assign compare_data_r0 = compare_data[DQ_WIDTH-1:0]; + assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + assign compare_data_r2 = 'h0; + assign compare_data_f2 = 'h0; + assign compare_data_r3 = 'h0; + assign compare_data_f3 = 'h0; + end + endgenerate + + always @(posedge clk) begin + rd_mux_sel_r <= #TCQ prbs_dqs_cnt_r; + end + + // Register outputs for improved timing. + // NOTE: Will need to change when per-bit DQ deskew is supported. + // Currenly all bits in DQS group are checked in aggregate + generate + genvar mux_i; + for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd + always @(posedge clk) begin + mux_rd_rise0_r1[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall0_r1[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise1_r1[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall1_r1[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise2_r1[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall2_r1[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise3_r1[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall3_r1[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + //Compare data + compare_data_rise0_r1[mux_i] <= #TCQ compare_data_r0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_fall0_r1[mux_i] <= #TCQ compare_data_f0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_rise1_r1[mux_i] <= #TCQ compare_data_r1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_fall1_r1[mux_i] <= #TCQ compare_data_f1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_rise2_r1[mux_i] <= #TCQ compare_data_r2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_fall2_r1[mux_i] <= #TCQ compare_data_f2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_rise3_r1[mux_i] <= #TCQ compare_data_r3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_fall3_r1[mux_i] <= #TCQ compare_data_f3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + end + end + endgenerate + + generate + genvar muxr2_i; + if (nCK_PER_CLK == 4) begin: gen_mux_div4 + for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_4 + always @(posedge clk) begin + if (mux_rd_valid_r) begin + mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i]; + mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i]; + mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i]; + mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i]; + mux_rd_rise2_r2[muxr2_i] <= #TCQ mux_rd_rise2_r1[muxr2_i]; + mux_rd_fall2_r2[muxr2_i] <= #TCQ mux_rd_fall2_r1[muxr2_i]; + mux_rd_rise3_r2[muxr2_i] <= #TCQ mux_rd_rise3_r1[muxr2_i]; + mux_rd_fall3_r2[muxr2_i] <= #TCQ mux_rd_fall3_r1[muxr2_i]; + end + //pipeline stage + mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i]; + mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i]; + mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i]; + mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i]; + mux_rd_rise2_r3[muxr2_i] <= #TCQ mux_rd_rise2_r2[muxr2_i]; + mux_rd_fall2_r3[muxr2_i] <= #TCQ mux_rd_fall2_r2[muxr2_i]; + mux_rd_rise3_r3[muxr2_i] <= #TCQ mux_rd_rise3_r2[muxr2_i]; + mux_rd_fall3_r3[muxr2_i] <= #TCQ mux_rd_fall3_r2[muxr2_i]; + //pipeline stage + mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i]; + mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i]; + mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i]; + mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i]; + mux_rd_rise2_r4[muxr2_i] <= #TCQ mux_rd_rise2_r3[muxr2_i]; + mux_rd_fall2_r4[muxr2_i] <= #TCQ mux_rd_fall2_r3[muxr2_i]; + mux_rd_rise3_r4[muxr2_i] <= #TCQ mux_rd_rise3_r3[muxr2_i]; + mux_rd_fall3_r4[muxr2_i] <= #TCQ mux_rd_fall3_r3[muxr2_i]; + end + end + end else if (nCK_PER_CLK == 2) begin: gen_mux_div2 + for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_2 + always @(posedge clk) begin + if (mux_rd_valid_r) begin + mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i]; + mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i]; + mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i]; + mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i]; + mux_rd_rise2_r2[muxr2_i] <= 'h0; + mux_rd_fall2_r2[muxr2_i] <= 'h0; + mux_rd_rise3_r2[muxr2_i] <= 'h0; + mux_rd_fall3_r2[muxr2_i] <= 'h0; + end + mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i]; + mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i]; + mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i]; + mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i]; + mux_rd_rise2_r3[muxr2_i] <= 'h0; + mux_rd_fall2_r3[muxr2_i] <= 'h0; + mux_rd_rise3_r3[muxr2_i] <= 'h0; + mux_rd_fall3_r3[muxr2_i] <= 'h0; + + //pipeline stage + mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i]; + mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i]; + mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i]; + mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i]; + mux_rd_rise2_r4[muxr2_i] <= 'h0; + mux_rd_fall2_r4[muxr2_i] <= 'h0; + mux_rd_rise3_r4[muxr2_i] <= 'h0; + mux_rd_fall3_r4[muxr2_i] <= 'h0; + end + end + end + endgenerate + + + // Registered signal indicates when mux_rd_rise/fall_r is valid + always @(posedge clk) begin + mux_rd_valid_r <= #TCQ ~phy_if_empty && prbs_rdlvl_start; + rd_valid_r1 <= #TCQ mux_rd_valid_r; + rd_valid_r2 <= #TCQ rd_valid_r1; + rd_valid_r3 <= #TCQ rd_valid_r2; + end + + + + +// Counter counts # of samples compared +// Reset sample counter when not "sampling" +// Otherwise, count # of samples compared +// Same counter is shared for three samples checked + always @(posedge clk) + if (rst) + samples_cnt_r <= #TCQ 'b0; + else if (samples_cnt_r == NUM_SAMPLES_CNT) begin + samples_cnt_r <= #TCQ 'b0; + end else if (complex_sample_cnt_inc) begin + samples_cnt_r <= #TCQ samples_cnt_r + 1; + /*if (!rd_valid_r1 || + (prbs_state_r == PRBS_DEC_DQS_WAIT) || + (prbs_state_r == PRBS_INC_DQS_WAIT) || + (prbs_state_r == PRBS_DEC_DQS) || + (prbs_state_r == PRBS_INC_DQS) || + (samples_cnt_r == NUM_SAMPLES_CNT) || + (samples_cnt_r == NUM_SAMPLES_CNT1)) + samples_cnt_r <= #TCQ 'b0; + else if (rd_valid_r1 && + (((samples_cnt_r < NUM_SAMPLES_CNT) && ~samples_cnt1_en_r) || + ((samples_cnt_r < NUM_SAMPLES_CNT1) && ~samples_cnt2_en_r) || + ((samples_cnt_r < NUM_SAMPLES_CNT2) && samples_cnt2_en_r))) + samples_cnt_r <= #TCQ samples_cnt_r + 1;*/ + end + +// Count #2 enable generation +// Assert when correct number of samples compared + always @(posedge clk) + if (rst) + samples_cnt1_en_r <= #TCQ 1'b0; + else begin + if ((prbs_state_r == PRBS_IDLE) || + (prbs_state_r == PRBS_DEC_DQS) || + (prbs_state_r == PRBS_INC_DQS) || + (prbs_state_r == FINE_PI_INC) || + (prbs_state_r == PRBS_NEW_DQS_PREWAIT)) + samples_cnt1_en_r <= #TCQ 1'b0; + else if ((samples_cnt_r == NUM_SAMPLES_CNT) && rd_valid_r1) + samples_cnt1_en_r <= #TCQ 1'b1; + end + +// Counter #3 enable generation +// Assert when correct number of samples compared + always @(posedge clk) + if (rst) + samples_cnt2_en_r <= #TCQ 1'b0; + else begin + if ((prbs_state_r == PRBS_IDLE) || + (prbs_state_r == PRBS_DEC_DQS) || + (prbs_state_r == PRBS_INC_DQS) || + (prbs_state_r == FINE_PI_INC) || + (prbs_state_r == PRBS_NEW_DQS_PREWAIT)) + samples_cnt2_en_r <= #TCQ 1'b0; + else if ((samples_cnt_r == NUM_SAMPLES_CNT1) && rd_valid_r1 && samples_cnt1_en_r) + samples_cnt2_en_r <= #TCQ 1'b1; + end + +// Victim selection logic + always @(posedge clk) + if (rst) + rd_victim_sel <= #TCQ 'd0; + else if (num_samples_done_r) + rd_victim_sel <= #TCQ 'd0; + else if (samples_cnt_r == NUM_SAMPLES_CNT) begin + if (rd_victim_sel < 'd7) + rd_victim_sel <= #TCQ rd_victim_sel + 1; + end + +// Output row count increment pulse to phy_init + always @(posedge clk) + if (rst) + complex_victim_inc <= #TCQ 1'b0; + else if (samples_cnt_r == NUM_SAMPLES_CNT) + complex_victim_inc <= #TCQ 1'b1; + else + complex_victim_inc <= #TCQ 1'b0; + +generate + if (FIXED_VICTIM == "TRUE") begin: victim_fixed + always @(posedge clk) + if (rst) + num_samples_done_r <= #TCQ 1'b0; + else if ((prbs_state_r == PRBS_DEC_DQS) || + (prbs_state_r == PRBS_INC_DQS)|| + (prbs_state_r == FINE_PI_INC) || + (prbs_state_r == FINE_PI_DEC)) + num_samples_done_r <= #TCQ 'b0; + else if (samples_cnt_r == NUM_SAMPLES_CNT) + num_samples_done_r <= #TCQ 1'b1; + end else begin: victim_not_fixed + always @(posedge clk) + if (rst) + num_samples_done_r <= #TCQ 1'b0; + else if ((prbs_state_r == PRBS_DEC_DQS) || + (prbs_state_r == PRBS_INC_DQS)|| + (prbs_state_r == FINE_PI_INC) || + (prbs_state_r == FINE_PI_DEC)) + num_samples_done_r <= #TCQ 'b0; + else if ((samples_cnt_r == NUM_SAMPLES_CNT) && (rd_victim_sel == 'd7)) + num_samples_done_r <= #TCQ 1'b1; + end +endgenerate + + + //*************************************************************************** + // Compare Read Data for the byte being Leveled with Expected data from PRBS + // generator. Resulting compare_err signal used to determine read data valid + // edge. + //*************************************************************************** + generate + if (nCK_PER_CLK == 4) begin: cmp_err_4to1 + always @ (posedge clk) begin + if (rst || new_cnt_dqs_r || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == PRBS_DEC_DQS)) begin + compare_err <= #TCQ 1'b0; + compare_err_r0 <= #TCQ 1'b0; + compare_err_f0 <= #TCQ 1'b0; + compare_err_r1 <= #TCQ 1'b0; + compare_err_f1 <= #TCQ 1'b0; + compare_err_r2 <= #TCQ 1'b0; + compare_err_f2 <= #TCQ 1'b0; + compare_err_r3 <= #TCQ 1'b0; + compare_err_f3 <= #TCQ 1'b0; + end else if (rd_valid_r2) begin + compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1); + compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1); + compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1); + compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1); + compare_err_r2 <= #TCQ (mux_rd_rise2_r3 != compare_data_rise2_r1); + compare_err_f2 <= #TCQ (mux_rd_fall2_r3 != compare_data_fall2_r1); + compare_err_r3 <= #TCQ (mux_rd_rise3_r3 != compare_data_rise3_r1); + compare_err_f3 <= #TCQ (mux_rd_fall3_r3 != compare_data_fall3_r1); + compare_err <= #TCQ (compare_err_r0 | compare_err_f0 | + compare_err_r1 | compare_err_f1 | + compare_err_r2 | compare_err_f2 | + compare_err_r3 | compare_err_f3); + end + end + end else begin: cmp_err_2to1 + always @ (posedge clk) begin + if (rst || new_cnt_dqs_r || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == PRBS_DEC_DQS)) begin + compare_err <= #TCQ 1'b0; + compare_err_r0 <= #TCQ 1'b0; + compare_err_f0 <= #TCQ 1'b0; + compare_err_r1 <= #TCQ 1'b0; + compare_err_f1 <= #TCQ 1'b0; + end else if (rd_valid_r2) begin + compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1); + compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1); + compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1); + compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1); + compare_err <= #TCQ (compare_err_r0 | compare_err_f0 | + compare_err_r1 | compare_err_f1); + end + end + end + endgenerate + + //Sticky bit compare_err + always @ (posedge clk) + if (prbs_state_r == PRBS_PAT_COMPARE) + compare_err_latch <= #TCQ compare_err? 1'b1: compare_err_latch; + else + compare_err_latch <= #TCQ 1'b0; + +//*************************************************************************** +// Decrement initial Phaser_IN fine delay value before proceeding with +// read calibration +//*************************************************************************** + + +//*************************************************************************** +// Demultiplexor to control Phaser_IN delay values +//*************************************************************************** + +// Read DQS + always @(posedge clk) begin + if (rst) begin + pi_en_stg2_f_timing <= #TCQ 'b0; + pi_stg2_f_incdec_timing <= #TCQ 'b0; + end else if (prbs_tap_en_r) begin +// Change only specified DQS + pi_en_stg2_f_timing <= #TCQ 1'b1; + pi_stg2_f_incdec_timing <= #TCQ prbs_tap_inc_r; + end else begin + pi_en_stg2_f_timing <= #TCQ 'b0; + pi_stg2_f_incdec_timing <= #TCQ 'b0; + end + end + +// registered for timing + always @(posedge clk) begin + pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing; + pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing; + end + +//*************************************************************************** +// generate request to PHY_INIT logic to issue precharged. Required when +// calibration can take a long time (during which there are only constant +// reads present on this bus). In this case need to issue perioidic +// precharges to avoid tRAS violation. This signal must meet the following +// requirements: (1) only transition from 0->1 when prech is first needed, +// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted +//*************************************************************************** + + always @(posedge clk) + if (rst) + prbs_rdlvl_prech_req <= #TCQ 1'b0; + else + prbs_rdlvl_prech_req <= #TCQ prbs_prech_req_r; + +//***************************************************************** +// keep track of edge tap counts found, and current capture clock +// tap count +//***************************************************************** + + always @(posedge clk) + if (rst) begin + prbs_dqs_tap_cnt_r <= #TCQ 'b0; + rdlvl_cpt_tap_cnt <= #TCQ 'b0; + end else if (new_cnt_dqs_r) begin + prbs_dqs_tap_cnt_r <= #TCQ pi_counter_read_val; + rdlvl_cpt_tap_cnt <= #TCQ pi_counter_read_val; + end else if (prbs_tap_en_r) begin + if (prbs_tap_inc_r) + prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r + 1; + else if (prbs_dqs_tap_cnt_r != 'd0) + prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r - 1; + end + + always @(posedge clk) + if (rst) begin + prbs_dec_tap_calc_plus_3 <= #TCQ 'b0; + prbs_dec_tap_calc_minus_3 <= #TCQ 'b0; + end else if (new_cnt_dqs_r) begin + prbs_dec_tap_calc_plus_3 <= #TCQ 'b000011; + prbs_dec_tap_calc_minus_3 <= #TCQ 'b111100; + end else begin + prbs_dec_tap_calc_plus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt + 3); + prbs_dec_tap_calc_minus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt - 3); + end + + always @(posedge clk) + if (rst || new_cnt_dqs_r) + prbs_dqs_tap_limit_r <= #TCQ 1'b0; + else if (prbs_dqs_tap_cnt_r == 6'd63) + prbs_dqs_tap_limit_r <= #TCQ 1'b1; + else + prbs_dqs_tap_limit_r <= #TCQ 1'b0; + + // Temp wire for timing. + // The following in the always block below causes timing issues + // due to DSP block inference + // 6*prbs_dqs_cnt_r. + // replacing this with two left shifts + one left shift to avoid + // DSP multiplier. + + assign prbs_dqs_cnt_timing = {2'd0, prbs_dqs_cnt_r}; + + + always @(posedge clk) + prbs_dqs_cnt_timing_r <= #TCQ prbs_dqs_cnt_timing; + + + // Storing DQS tap values at the end of each DQS read leveling + always @(posedge clk) begin + if (rst) begin + prbs_final_dqs_tap_cnt_r <= #TCQ 'b0; + end else if ((prbs_state_r == PRBS_NEXT_DQS) && (prbs_state_r1 != PRBS_NEXT_DQS)) begin + prbs_final_dqs_tap_cnt_r[(prbs_dqs_cnt_timing_r*6)+:6] + <= #TCQ prbs_dqs_tap_cnt_r; + end + end + + + + + //***************************************************************** + + always @(posedge clk) begin + prbs_state_r1 <= #TCQ prbs_state_r; + prbs_rdlvl_start_r <= #TCQ prbs_rdlvl_start; + end + +// Wait counter for wait states + always @(posedge clk) + if ((prbs_state_r == PRBS_NEW_DQS_WAIT) || + (prbs_state_r == PRBS_INC_DQS_WAIT) || + (prbs_state_r == PRBS_DEC_DQS_WAIT) || + (prbs_state_r == FINE_PI_DEC_WAIT) || + (prbs_state_r == FINE_PI_INC_WAIT) || + (prbs_state_r == PRBS_NEW_DQS_PREWAIT)) + wait_state_cnt_en_r <= #TCQ 1'b1; + else + wait_state_cnt_en_r <= #TCQ 1'b0; + + always @(posedge clk) + if (!wait_state_cnt_en_r) begin + wait_state_cnt_r <= #TCQ 'b0; + cnt_wait_state <= #TCQ 1'b0; + end else begin + if (wait_state_cnt_r < 'd15) begin + wait_state_cnt_r <= #TCQ wait_state_cnt_r + 1; + cnt_wait_state <= #TCQ 1'b0; + end else begin + // Need to reset to 0 to handle the case when there are two + // different WAIT states back-to-back + wait_state_cnt_r <= #TCQ 'b0; + cnt_wait_state <= #TCQ 1'b1; + end + end + + always @ (posedge clk) + err_chk_invalid <= #TCQ (wait_state_cnt_r < 'd14); + + +//***************************************************************** +// compare error checking per-bit +//**************************************************************** + + generate + genvar pb_i; + if (nCK_PER_CLK == 4) begin: cmp_err_pb_4to1 + for(pb_i=0 ; pb_i prbs_dqs_tap_cnt_r -(MIN_WIN-1))? 'd0 + : prbs_dqs_tap_cnt_r-(MIN_WIN-1)-left_edge_ref; + //right edge is updated when match flag becomes 000000001 (8 success, 1 fail) + end else if (match_flag_pb[eg*MIN_WIN+:MIN_WIN]== MIN_PASS && compare_err_pb_latch_r[eg]) begin + right_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r-1; + right_edge_found_pb[eg] <= #TCQ 1'b1; + //check the gain of bit - update only for right edge found + if(~right_edge_found_pb[eg]) + right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > prbs_dqs_tap_cnt_r-1)? + ((right_edge_pb[eg*6 +:6] > prbs_dqs_tap_cnt_r-1)? 0: prbs_dqs_tap_cnt_r-1- right_edge_pb[eg*6+:6]): + ((right_edge_pb[eg*6+:6] > right_edge_ref)? 0 : right_edge_ref - right_edge_pb[eg*6+:6]); + //no right edge found + end else if (prbs_dqs_tap_cnt_r == 6'h3f && ~right_edge_found_pb[eg]) begin + right_edge_pb[eg*6+:6] <= #TCQ 6'h3f; + right_edge_found_pb[eg] <= #TCQ 1'b1; + //right edge at 63. gain = max(0, ref_bit_right_tap - prev_right_edge) + right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > right_edge_pb[eg*6+:6])? + (right_edge_ref - right_edge_pb[eg*6+:6]) : 0; + end + //update match flag - shift and update + match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ {match_flag_pb[(eg*MIN_WIN)+:(MIN_WIN-1)],compare_err_pb_latch_r[eg]}; + end else if (prbs_state_r == FINE_PI_DEC) begin + left_edge_found_pb[eg] <= #TCQ 1'b0; + right_edge_found_pb[eg] <= #TCQ 1'b0; + left_loss_pb[eg*6+:6] <= #TCQ 'b0; + right_gain_pb[eg*6+:6] <= #TCQ 'b0; + match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ MATCH_ALL_ONE ; //new fix + left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge + end else if (prbs_state_r == FINE_PI_INC) begin + left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge + end + end + end //always + end //for + endgenerate + + //update fine_delay according to loss/gain value per bit + generate + genvar f_pb; + for(f_pb=0; f_pbleft_loss_pb[f_pb*6+:6])?1'b1:1'b0; + end + end + end + endgenerate + + //fine inc stage (stage cnt 0,1,2), fine dec stage (stage cnt 3) + always @ (posedge clk) begin + if (rst) + fine_inc_stage <= #TCQ 'b1; + else + fine_inc_stage <= #TCQ (stage_cnt!='d3); + end +//***************************************************************** + + always @(posedge clk) + if (rst) begin + prbs_dqs_cnt_r <= #TCQ 'b0; + prbs_tap_en_r <= #TCQ 1'b0; + prbs_tap_inc_r <= #TCQ 1'b0; + prbs_prech_req_r <= #TCQ 1'b0; + prbs_state_r <= #TCQ PRBS_IDLE; + prbs_found_1st_edge_r <= #TCQ 1'b0; + prbs_found_2nd_edge_r <= #TCQ 1'b0; + prbs_1st_edge_taps_r <= #TCQ 6'bxxxxxx; + prbs_inc_tap_cnt <= #TCQ 'b0; + prbs_dec_tap_cnt <= #TCQ 'b0; + new_cnt_dqs_r <= #TCQ 1'b0; + if (SIM_CAL_OPTION == "FAST_CAL") + prbs_rdlvl_done <= #TCQ 1'b1; + else + prbs_rdlvl_done <= #TCQ 1'b0; + prbs_2nd_edge_taps_r <= #TCQ 6'bxxxxxx; + prbs_last_byte_done <= #TCQ 1'b0; + prbs_tap_mod <= #TCQ 'd0; + reset_rd_addr <= #TCQ 'b0; + fine_pi_dec_cnt <= #TCQ 'b0; + match_flag_and <= #TCQ MATCH_ALL_ONE; + match_flag_or <= #TCQ MATCH_ALL_ONE; + no_err_win_detected <= #TCQ 1'b0; + no_err_win_detected_latch <= #TCQ 1'b0; + valid_window_cnt <= 2'd0; + stage_cnt <= #TCQ 2'b00; + right_edge_found <= #TCQ 1'b0; + largest_left_edge <= #TCQ 6'b000000; + smallest_right_edge <= #TCQ 6'b111111; + num_samples_done_ind <= #TCQ 'b0; + fine_delay_sel <= #TCQ 'b0; + fine_dly_error <= #TCQ 'b0; + edge_det_error <= #TCQ 'b0; + complex_pi_incdec_done <= #TCQ 1'b0; + complex_init_pi_dec_done_r <= #TCQ 1'b0; + end else begin + + case (prbs_state_r) + + PRBS_IDLE: begin + prbs_last_byte_done <= #TCQ 1'b0; + prbs_prech_req_r <= #TCQ 1'b0; + if (prbs_rdlvl_start && ~prbs_rdlvl_start_r) begin + if (SIM_CAL_OPTION == "SKIP_CAL" || SIM_CAL_OPTION == "FAST_CAL") begin + prbs_state_r <= #TCQ PRBS_DONE; + reset_rd_addr <= #TCQ 1'b1; + end else begin + new_cnt_dqs_r <= #TCQ 1'b1; + prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT; + fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//. + end + end + end + + // Wait for the new DQS group to change + // also gives time for the read data IN_FIFO to + // output the updated data for the new DQS group + PRBS_NEW_DQS_WAIT: begin + reset_rd_addr <= #TCQ 'b0; + prbs_last_byte_done <= #TCQ 1'b0; + prbs_prech_req_r <= #TCQ 1'b0; + stage_cnt <= #TCQ 2'b0; + match_flag_and <= #TCQ MATCH_ALL_ONE; + match_flag_or <= #TCQ MATCH_ALL_ONE; + no_err_win_detected <= #TCQ 1'b0; + no_err_win_detected_latch <= #TCQ 1'b0; + if (cnt_wait_state) begin + new_cnt_dqs_r <= #TCQ 1'b0; + prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC:PRBS_PAT_COMPARE; + //For normal, it doesn't have initial pi incdec + complex_pi_incdec_done <= #TCQ fine_calib? complex_pi_incdec_done: 1'b1; + end + end + + // Check for presence of data eye edge. During this state, we + // sample the read data multiple times, and look for changes + // in the read data, specifically: + // 1. A change in the read data compared with the value of + // read data from the previous delay tap. This indicates + // that the most recent tap delay increment has moved us + // into either a new window, or moved/kept us in the + // transition/jitter region between windows. Note that this + // condition only needs to be checked for once, and for + // logistical purposes, we check this soon after entering + // this state (see comment in PRBS_PAT_COMPARE below for + // why this is done) + // 2. A change in the read data while we are in this state + // (i.e. in the absence of a tap delay increment). This + // indicates that we're close enough to a window edge that + // jitter will cause the read data to change even in the + // absence of a tap delay change + PRBS_PAT_COMPARE: begin + // Continue to sample read data and look for edges until the + // appropriate time interval (shorter for simulation-only, + // much, much longer for actual h/w) has elapsed + //comparision started - wait for next PI movement after read + complex_pi_incdec_done <= #TCQ 1'b0; //need to be wait for new incdec done + if (num_samples_done_r) begin + if (prbs_dqs_tap_limit_r) + // Only one edge detected and ran out of taps since only one + // bit time worth of taps available for window detection. This + // can happen if at tap 0 DQS is in previous window which results + // in only left edge being detected. Or at tap 0 DQS is in the + // current window resulting in only right edge being detected. + // Depending on the frequency this case can also happen if at + // tap 0 DQS is in the left noise region resulting in only left + // edge being detected. + prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; + else if (compare_err_latch || (prbs_dqs_tap_cnt_r == 'd0)) begin + // Sticky bit - asserted after we encounter an edge, although + // the current edge may not be considered the "first edge" this + // just means we found at least one edge + prbs_found_1st_edge_r <= #TCQ 1'b1; + + // Both edges of data valid window found: + // If we've found a second edge after a region of stability + // then we must have just passed the second ("right" edge of + // the window. Record this second_edge_taps = current tap-1, + // because we're one past the actual second edge tap, where + // the edge taps represent the extremes of the data valid + // window (i.e. smallest & largest taps where data still valid + if (prbs_found_1st_edge_r) begin + prbs_found_2nd_edge_r <= #TCQ 1'b1; + prbs_2nd_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r - 1; + prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; + end else begin + // Otherwise, an edge was found (just not the "second" edge) + // Assuming DQS is in the correct window at tap 0 of Phaser IN + // fine tap. The first edge found is the right edge of the valid + // window and is the beginning of the jitter region hence done! + if (compare_err_latch) + prbs_1st_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r + 1; + else + prbs_1st_edge_taps_r <= #TCQ 'd0; + + prbs_inc_tap_cnt <= #TCQ rdlvl_cpt_tap_cnt - prbs_dqs_tap_cnt_r; + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC; + end + end else begin + // Otherwise, if we haven't found an edge.... + // If we still have taps left to use, then keep incrementing + if (prbs_found_1st_edge_r) + //prbs_state_r <= #TCQ PRBS_INC_DQS; + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC; + else + //prbs_state_r <= #TCQ PRBS_DEC_DQS; + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC; + end + end + end + + // Increment Phaser_IN delay for DQS + PRBS_INC_DQS: begin + prbs_state_r <= #TCQ PRBS_INC_DQS_WAIT; + if (prbs_inc_tap_cnt > 'd0) + prbs_inc_tap_cnt <= #TCQ prbs_inc_tap_cnt - 1; + if (~prbs_dqs_tap_limit_r) begin + prbs_tap_en_r <= #TCQ 1'b1; + prbs_tap_inc_r <= #TCQ 1'b1; + end + end + + // Wait for Phaser_In to settle, before checking again for an edge + // only all INC is done, incdec done is asserted + PRBS_INC_DQS_WAIT: begin + prbs_tap_en_r <= #TCQ 1'b0; + prbs_tap_inc_r <= #TCQ 1'b0; + if (cnt_wait_state) begin + if (prbs_inc_tap_cnt > 'd0) + prbs_state_r <= #TCQ PRBS_INC_DQS; //centering + else begin + prbs_state_r <= #TCQ PRBS_PAT_COMPARE; + complex_pi_incdec_done <= #TCQ 1'b1; + end + end + end + + // Calculate final value of Phaser_IN taps. At this point, one or both + // edges of data eye have been found, and/or all taps have been + // exhausted looking for the edges + // NOTE: The amount to be decrement by is calculated, not the + // absolute setting for DQS. + // CENTER compensation with shift by 1 + //wait finishing the read before PI dec to center + PRBS_CALC_TAPS: begin + if (center_comp) begin + prbs_dec_tap_cnt <= #TCQ (dec_cnt[5] & dec_cnt[0])? 'd32: dec_cnt + pi_adj; + fine_dly_error <= #TCQ (dec_cnt[5] & dec_cnt[0])? 1'b1: fine_dly_error; //sticky bit + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC; + end else begin //No center compensation + if (prbs_found_2nd_edge_r && prbs_found_1st_edge_r) begin + // Both edges detected + prbs_dec_tap_cnt + <= #TCQ ((prbs_2nd_edge_taps_r - + prbs_1st_edge_taps_r)>>1) + 1 + pi_adj; + edge_det_error <= #TCQ edge_det_error? 1'b1: + (prbs_1st_edge_taps_r >= prbs_2nd_edge_taps_r); + end else if (~prbs_found_2nd_edge_r && prbs_found_1st_edge_r) begin + // Only left edge detected + prbs_dec_tap_cnt + <= #TCQ ((prbs_dqs_tap_cnt_r - prbs_1st_edge_taps_r)>>1) + pi_adj; + end else begin + // No edges detected + edge_det_error <= #TCQ 1'b1; + prbs_dec_tap_cnt + <= #TCQ (prbs_dqs_tap_cnt_r>>1) + pi_adj; + end + // Now use the value we just calculated to decrement CPT taps + // to the desired calibration point + //wait finishing the read before PI dec to center + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC; + end + end + + // decrement capture clock for final adjustment - center + // capture clock in middle of data eye. This adjustment will occur + // only when both the edges are found usign CPT taps. Must do this + // incrementally to avoid clock glitching (since CPT drives clock + // divider within each ISERDES) + PRBS_DEC_DQS: begin + prbs_tap_en_r <= #TCQ 1'b1; + prbs_tap_inc_r <= #TCQ 1'b0; + // once adjustment is complete, we're done with calibration for + // this DQS, repeat for next DQS + if (prbs_dec_tap_cnt > 'd0) + prbs_dec_tap_cnt <= #TCQ prbs_dec_tap_cnt - 1; + if (prbs_dec_tap_cnt == 6'b000001) begin + prbs_state_r <= #TCQ PRBS_NEXT_DQS; + //only all DEC is done, incdec done is asserted + complex_pi_incdec_done <= #TCQ 1'b1; + end else + prbs_state_r <= #TCQ PRBS_DEC_DQS_WAIT; + end + + PRBS_DEC_DQS_WAIT: begin + prbs_tap_en_r <= #TCQ 1'b0; + prbs_tap_inc_r <= #TCQ 1'b0; + if (cnt_wait_state) begin + if (prbs_dec_tap_cnt > 'd0) + prbs_state_r <= #TCQ PRBS_DEC_DQS; + else begin + //PI movement is done, go to read and compare + complex_pi_incdec_done <= #TCQ 1'b1; + prbs_state_r <= #TCQ PRBS_PAT_COMPARE; + end + end + end + + // Determine whether we're done, or have more DQS's to calibrate + // Also request precharge after every byte, as appropriate + PRBS_NEXT_DQS: begin + //Need to do initial dec for per-bit algorithm + complex_init_pi_dec_done_r <= #TCQ 1'b0; + reset_rd_addr <= #TCQ 'b1; + prbs_prech_req_r <= #TCQ 1'b1; + prbs_tap_en_r <= #TCQ 1'b0; + prbs_tap_inc_r <= #TCQ 1'b0; + // Prepare for another iteration with next DQS group + prbs_found_1st_edge_r <= #TCQ 1'b0; + prbs_found_2nd_edge_r <= #TCQ 1'b0; + prbs_1st_edge_taps_r <= #TCQ 'd0; + prbs_2nd_edge_taps_r <= #TCQ 'd0; + largest_left_edge <= #TCQ 6'b000000; + smallest_right_edge <= #TCQ 6'b111111; + if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin + prbs_last_byte_done <= #TCQ 1'b1; + end + + // Wait until precharge that occurs in between calibration of + // DQS groups is finished + if (prech_done) begin + prbs_prech_req_r <= #TCQ 1'b0; + if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin + // All DQS groups done + prbs_state_r <= #TCQ PRBS_DONE; + end else begin + // Process next DQS group + new_cnt_dqs_r <= #TCQ 1'b1; + prbs_dqs_cnt_r <= #TCQ prbs_dqs_cnt_r + 1; + prbs_state_r <= #TCQ PRBS_NEW_DQS_PREWAIT; + end + end + end + + PRBS_NEW_DQS_PREWAIT: begin + if (cnt_wait_state) begin + prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT; + fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//. + end + end + + PRBS_CALC_TAPS_PRE: + begin + //Wait for new PI movement + complex_pi_incdec_done <= #TCQ 1'b0; + prbs_state_r <= #TCQ fine_calib? PRBS_NEXT_DQS:PRBS_CALC_TAPS_WAIT; + if(center_comp && ~fine_calib) begin + if(prbs_found_1st_edge_r) largest_left_edge <= #TCQ prbs_1st_edge_taps_r; + else largest_left_edge <= #TCQ 6'd0; + if(prbs_found_2nd_edge_r) smallest_right_edge <= #TCQ prbs_2nd_edge_taps_r; + else smallest_right_edge <= #TCQ 6'd63; + end + end + + //wait for center compensation + PRBS_CALC_TAPS_WAIT: + begin + prbs_state_r <= #TCQ PRBS_CALC_TAPS; + end + //if it is fine_inc stage (first/second stage): dec to 0 + //if it is fine_dec stage (third stage): dec to center + FINE_PI_DEC: begin + fine_delay_sel <= #TCQ 'b0; + if(fine_pi_dec_cnt > 0) begin + prbs_tap_en_r <= #TCQ 1'b1; + prbs_tap_inc_r <= #TCQ 1'b0; + fine_pi_dec_cnt <= #TCQ fine_pi_dec_cnt - 'd1; + end + prbs_state_r <= #TCQ FINE_PI_DEC_WAIT; + end + //wait for phaser_in tap decrement. + //if first/second stage is done, goes to FINE_PI_INC + //if last stage is done, goes to NEXT_DQS + //All PI DEC is done, incdec done is asserted + FINE_PI_DEC_WAIT: begin + prbs_tap_en_r <= #TCQ 1'b0; + prbs_tap_inc_r <= #TCQ 1'b0; + if(cnt_wait_state) begin + if(fine_pi_dec_cnt >0) + prbs_state_r <= #TCQ FINE_PI_DEC; + else begin + complex_pi_incdec_done <= #TCQ 1'b1; + if(fine_inc_stage) + prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT; //start from pi tap "0" + else + prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; //finish the process and go to the next DQS + end + end + end + + //finish the read before PI increament + RD_DONE_WAIT_FOR_PI_INC_INC: begin + if(complex_act_start) + prbs_state_r <= #TCQ fine_calib? FINE_PI_INC: PRBS_INC_DQS; + end + + FINE_PI_INC: begin + //prevent left edge update after valid window found + if(|left_edge_updated && ~no_err_win_detected_latch) largest_left_edge <= #TCQ prbs_dqs_tap_cnt_r- (MIN_WIN-1); + + if (no_err_win_detected) begin + //ignore previous right edge updated if valid window shown after + right_edge_found <= #TCQ 'b0; + end else if(|right_edge_found_pb && ~right_edge_found) begin + smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r -1 ; + right_edge_found <= #TCQ 'b1; + end + //until minimum window is detected, left edge can be updated + //once minimum window is detected, no further left edge update will be done + if(no_err_win_detected) no_err_win_detected_latch <= #TCQ 1'b1; + prbs_state_r <= #TCQ FINE_PI_INC_WAIT; + if(~prbs_dqs_tap_limit_r) begin + prbs_tap_en_r <= #TCQ 1'b1; + prbs_tap_inc_r <= #TCQ 1'b1; + end + end + + //wait for phase_in tap increment + //need to do pattern compare for every bit + FINE_PI_INC_WAIT: begin + prbs_tap_en_r <= #TCQ 1'b0; + prbs_tap_inc_r <= #TCQ 1'b0; + if (cnt_wait_state) begin + prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT; + //PI movement is done, go to read and compare + complex_pi_incdec_done <= #TCQ 1'b1; + end + end + + //compare per bit data and update flags,left/right edge + FINE_PAT_COMPARE_PER_BIT: begin + //comparision started - initial pi dec is done, wait for another pi movement after read + complex_init_pi_dec_done_r <= #TCQ 1'b1; + complex_pi_incdec_done <= #TCQ 1'b0; + if(num_samples_done_r) begin //sampling boundary + //update and_flag - shift and add + match_flag_and <= #TCQ {match_flag_and[MIN_WIN-2:0],compare_err_pb_and}; + match_flag_or <= #TCQ {match_flag_or[MIN_WIN-2:0],compare_err_pb_or}; + + //to solve false left/right edge detection + if({match_flag_or[MIN_WIN-2:0],compare_err_pb_or} == MIN_PASS) begin //if it detect minimum window + no_err_win_detected <= #TCQ 1'b1; + valid_window_cnt <= #TCQ valid_window_cnt + 'd1; + end else begin + no_err_win_detected <= #TCQ 1'b0; + end + //if it is consecutive 8 passing taps followed by fail or tap limit (finish the search) + //don't go to fine_FINE_CALC_TAPS to prevent to skip whole stage + //Or if all right edge are found + if((match_flag_and == MIN_PASS && compare_err_pb_and && (prbs_dqs_tap_cnt_r > MIN_WIN )) || prbs_dqs_tap_limit_r || (&right_edge_found_pb)) begin + prbs_state_r <= #TCQ FINE_CALC_TAPS; + //if all right edge are alined (all right edge found at the same time), update smallest right edge in here + //doesnt need to set right_edge_found to 1 since it is not used after this stage + if(!right_edge_found) smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r-1; + end else begin + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC; //keep increase until all fail + end + num_samples_done_ind <= num_samples_done_r; + end + end + //for fine_inc stage, inc all fine delay + //for fine_dec stage, apply dec fine delay for specific bits (by calculating the loss/gain) + // put phaser_in taps to the center + FINE_CALC_TAPS: begin + if(num_samples_done_ind || num_samples_done_r) begin + num_samples_done_ind <= #TCQ 'b0; //indicate num_samples_done_r is set + right_edge_found <= #TCQ 1'b0; //reset right edge found + match_flag_and <= #TCQ MATCH_ALL_ONE; //reset match flag for all bits + match_flag_or <= #TCQ MATCH_ALL_ONE; //reset match flag for all bits + no_err_win_detected <= #TCQ 1'b0; + no_err_win_detected_latch <= #TCQ 1'b0; + prbs_state_r <= #TCQ FINE_CALC_TAPS_WAIT; + valid_window_cnt <= #TCQ 2'd0; //reset valid window counter + end + end + + FINE_CALC_TAPS_WAIT: begin //wait for ROM read out + if(stage_cnt == 'd2) begin //last stage : back to center + if(center_comp) begin + fine_pi_dec_cnt <= #TCQ (dec_cnt[5]&dec_cnt[0])? 'd32: prbs_dqs_tap_cnt_r - smallest_right_edge + dec_cnt - 1 + pi_adj ; //going to the center value & shift by 1 + fine_dly_error <= #TCQ (dec_cnt[5]&dec_cnt[0]) ? 1'b1: fine_dly_error; + end else begin + fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r - center_calc[6:1] - center_calc[0] + pi_adj; //going to the center value & shift left by 1 + fine_dly_error <= #TCQ 1'b0; + end + end else begin + fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r; + end + if (bit_cnt == DRAM_WIDTH) begin + fine_delay_sel <= #TCQ 'b1; + stage_cnt <= #TCQ stage_cnt + 1; + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC; + end + + end + + //wait for finishing the read before PI movement + RD_DONE_WAIT_FOR_PI_INC_DEC: begin + if (complex_act_start & ~complex_rdlvl_err) + prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC: PRBS_DEC_DQS; + end + + // Done with this stage of calibration + PRBS_DONE: begin + prbs_prech_req_r <= #TCQ 1'b0; + prbs_last_byte_done <= #TCQ 1'b0; + prbs_rdlvl_done <= #TCQ ~complex_rdlvl_err; + reset_rd_addr <= #TCQ 1'b0; + end + + endcase + end + + //ROM generation for dec counter + always @ (largest_left_edge or smallest_right_edge) begin + case ({largest_left_edge, smallest_right_edge}) + 12'd0 : mem_out_dec = 6'b111111; + 12'd1 : mem_out_dec = 6'b111111; + 12'd2 : mem_out_dec = 6'b111111; + 12'd3 : mem_out_dec = 6'b111111; + 12'd4 : mem_out_dec = 6'b111111; + 12'd5 : mem_out_dec = 6'b111111; + 12'd6 : mem_out_dec = 6'b000100; + 12'd7 : mem_out_dec = 6'b000101; + 12'd8 : mem_out_dec = 6'b000101; + 12'd9 : mem_out_dec = 6'b000110; + 12'd10 : mem_out_dec = 6'b000110; + 12'd11 : mem_out_dec = 6'b000111; + 12'd12 : mem_out_dec = 6'b001000; + 12'd13 : mem_out_dec = 6'b001000; + 12'd14 : mem_out_dec = 6'b001001; + 12'd15 : mem_out_dec = 6'b001010; + 12'd16 : mem_out_dec = 6'b001010; + 12'd17 : mem_out_dec = 6'b001011; + 12'd18 : mem_out_dec = 6'b001011; + 12'd19 : mem_out_dec = 6'b001100; + 12'd20 : mem_out_dec = 6'b001100; + 12'd21 : mem_out_dec = 6'b001100; + 12'd22 : mem_out_dec = 6'b001100; + 12'd23 : mem_out_dec = 6'b001101; + 12'd24 : mem_out_dec = 6'b001100; + 12'd25 : mem_out_dec = 6'b001100; + 12'd26 : mem_out_dec = 6'b001101; + 12'd27 : mem_out_dec = 6'b001110; + 12'd28 : mem_out_dec = 6'b001110; + 12'd29 : mem_out_dec = 6'b001111; + 12'd30 : mem_out_dec = 6'b010000; + 12'd31 : mem_out_dec = 6'b010001; + 12'd32 : mem_out_dec = 6'b010001; + 12'd33 : mem_out_dec = 6'b010010; + 12'd34 : mem_out_dec = 6'b010010; + 12'd35 : mem_out_dec = 6'b010010; + 12'd36 : mem_out_dec = 6'b010011; + 12'd37 : mem_out_dec = 6'b010100; + 12'd38 : mem_out_dec = 6'b010100; + 12'd39 : mem_out_dec = 6'b010101; + 12'd40 : mem_out_dec = 6'b010101; + 12'd41 : mem_out_dec = 6'b010110; + 12'd42 : mem_out_dec = 6'b010110; + 12'd43 : mem_out_dec = 6'b010111; + 12'd44 : mem_out_dec = 6'b011000; + 12'd45 : mem_out_dec = 6'b011001; + 12'd46 : mem_out_dec = 6'b011001; + 12'd47 : mem_out_dec = 6'b011010; + 12'd48 : mem_out_dec = 6'b011010; + 12'd49 : mem_out_dec = 6'b011011; + 12'd50 : mem_out_dec = 6'b011011; + 12'd51 : mem_out_dec = 6'b011100; + 12'd52 : mem_out_dec = 6'b011100; + 12'd53 : mem_out_dec = 6'b011100; + 12'd54 : mem_out_dec = 6'b011100; + 12'd55 : mem_out_dec = 6'b011100; + 12'd56 : mem_out_dec = 6'b011100; + 12'd57 : mem_out_dec = 6'b011100; + 12'd58 : mem_out_dec = 6'b011100; + 12'd59 : mem_out_dec = 6'b011101; + 12'd60 : mem_out_dec = 6'b011110; + 12'd61 : mem_out_dec = 6'b011111; + 12'd62 : mem_out_dec = 6'b100000; + 12'd63 : mem_out_dec = 6'b100000; + 12'd64 : mem_out_dec = 6'b111111; + 12'd65 : mem_out_dec = 6'b111111; + 12'd66 : mem_out_dec = 6'b111111; + 12'd67 : mem_out_dec = 6'b111111; + 12'd68 : mem_out_dec = 6'b111111; + 12'd69 : mem_out_dec = 6'b111111; + 12'd70 : mem_out_dec = 6'b111111; + 12'd71 : mem_out_dec = 6'b000100; + 12'd72 : mem_out_dec = 6'b000100; + 12'd73 : mem_out_dec = 6'b000101; + 12'd74 : mem_out_dec = 6'b000110; + 12'd75 : mem_out_dec = 6'b000111; + 12'd76 : mem_out_dec = 6'b000111; + 12'd77 : mem_out_dec = 6'b001000; + 12'd78 : mem_out_dec = 6'b001001; + 12'd79 : mem_out_dec = 6'b001001; + 12'd80 : mem_out_dec = 6'b001010; + 12'd81 : mem_out_dec = 6'b001010; + 12'd82 : mem_out_dec = 6'b001011; + 12'd83 : mem_out_dec = 6'b001011; + 12'd84 : mem_out_dec = 6'b001011; + 12'd85 : mem_out_dec = 6'b001011; + 12'd86 : mem_out_dec = 6'b001011; + 12'd87 : mem_out_dec = 6'b001100; + 12'd88 : mem_out_dec = 6'b001011; + 12'd89 : mem_out_dec = 6'b001100; + 12'd90 : mem_out_dec = 6'b001100; + 12'd91 : mem_out_dec = 6'b001101; + 12'd92 : mem_out_dec = 6'b001110; + 12'd93 : mem_out_dec = 6'b001111; + 12'd94 : mem_out_dec = 6'b001111; + 12'd95 : mem_out_dec = 6'b010000; + 12'd96 : mem_out_dec = 6'b010001; + 12'd97 : mem_out_dec = 6'b010001; + 12'd98 : mem_out_dec = 6'b010010; + 12'd99 : mem_out_dec = 6'b010010; + 12'd100 : mem_out_dec = 6'b010011; + 12'd101 : mem_out_dec = 6'b010011; + 12'd102 : mem_out_dec = 6'b010100; + 12'd103 : mem_out_dec = 6'b010100; + 12'd104 : mem_out_dec = 6'b010100; + 12'd105 : mem_out_dec = 6'b010101; + 12'd106 : mem_out_dec = 6'b010110; + 12'd107 : mem_out_dec = 6'b010111; + 12'd108 : mem_out_dec = 6'b010111; + 12'd109 : mem_out_dec = 6'b011000; + 12'd110 : mem_out_dec = 6'b011001; + 12'd111 : mem_out_dec = 6'b011001; + 12'd112 : mem_out_dec = 6'b011010; + 12'd113 : mem_out_dec = 6'b011010; + 12'd114 : mem_out_dec = 6'b011011; + 12'd115 : mem_out_dec = 6'b011011; + 12'd116 : mem_out_dec = 6'b011011; + 12'd117 : mem_out_dec = 6'b011011; + 12'd118 : mem_out_dec = 6'b011011; + 12'd119 : mem_out_dec = 6'b011011; + 12'd120 : mem_out_dec = 6'b011011; + 12'd121 : mem_out_dec = 6'b011011; + 12'd122 : mem_out_dec = 6'b011100; + 12'd123 : mem_out_dec = 6'b011101; + 12'd124 : mem_out_dec = 6'b011110; + 12'd125 : mem_out_dec = 6'b011110; + 12'd126 : mem_out_dec = 6'b011111; + 12'd127 : mem_out_dec = 6'b100000; + 12'd128 : mem_out_dec = 6'b111111; + 12'd129 : mem_out_dec = 6'b111111; + 12'd130 : mem_out_dec = 6'b111111; + 12'd131 : mem_out_dec = 6'b111111; + 12'd132 : mem_out_dec = 6'b111111; + 12'd133 : mem_out_dec = 6'b111111; + 12'd134 : mem_out_dec = 6'b111111; + 12'd135 : mem_out_dec = 6'b111111; + 12'd136 : mem_out_dec = 6'b000100; + 12'd137 : mem_out_dec = 6'b000101; + 12'd138 : mem_out_dec = 6'b000101; + 12'd139 : mem_out_dec = 6'b000110; + 12'd140 : mem_out_dec = 6'b000110; + 12'd141 : mem_out_dec = 6'b000111; + 12'd142 : mem_out_dec = 6'b001000; + 12'd143 : mem_out_dec = 6'b001001; + 12'd144 : mem_out_dec = 6'b001001; + 12'd145 : mem_out_dec = 6'b001010; + 12'd146 : mem_out_dec = 6'b001010; + 12'd147 : mem_out_dec = 6'b001010; + 12'd148 : mem_out_dec = 6'b001010; + 12'd149 : mem_out_dec = 6'b001010; + 12'd150 : mem_out_dec = 6'b001010; + 12'd151 : mem_out_dec = 6'b001011; + 12'd152 : mem_out_dec = 6'b001010; + 12'd153 : mem_out_dec = 6'b001011; + 12'd154 : mem_out_dec = 6'b001100; + 12'd155 : mem_out_dec = 6'b001101; + 12'd156 : mem_out_dec = 6'b001101; + 12'd157 : mem_out_dec = 6'b001110; + 12'd158 : mem_out_dec = 6'b001111; + 12'd159 : mem_out_dec = 6'b010000; + 12'd160 : mem_out_dec = 6'b010000; + 12'd161 : mem_out_dec = 6'b010001; + 12'd162 : mem_out_dec = 6'b010001; + 12'd163 : mem_out_dec = 6'b010010; + 12'd164 : mem_out_dec = 6'b010010; + 12'd165 : mem_out_dec = 6'b010011; + 12'd166 : mem_out_dec = 6'b010011; + 12'd167 : mem_out_dec = 6'b010100; + 12'd168 : mem_out_dec = 6'b010100; + 12'd169 : mem_out_dec = 6'b010101; + 12'd170 : mem_out_dec = 6'b010101; + 12'd171 : mem_out_dec = 6'b010110; + 12'd172 : mem_out_dec = 6'b010111; + 12'd173 : mem_out_dec = 6'b010111; + 12'd174 : mem_out_dec = 6'b011000; + 12'd175 : mem_out_dec = 6'b011001; + 12'd176 : mem_out_dec = 6'b011001; + 12'd177 : mem_out_dec = 6'b011010; + 12'd178 : mem_out_dec = 6'b011010; + 12'd179 : mem_out_dec = 6'b011010; + 12'd180 : mem_out_dec = 6'b011010; + 12'd181 : mem_out_dec = 6'b011010; + 12'd182 : mem_out_dec = 6'b011010; + 12'd183 : mem_out_dec = 6'b011010; + 12'd184 : mem_out_dec = 6'b011010; + 12'd185 : mem_out_dec = 6'b011011; + 12'd186 : mem_out_dec = 6'b011100; + 12'd187 : mem_out_dec = 6'b011100; + 12'd188 : mem_out_dec = 6'b011101; + 12'd189 : mem_out_dec = 6'b011110; + 12'd190 : mem_out_dec = 6'b011111; + 12'd191 : mem_out_dec = 6'b100000; + 12'd192 : mem_out_dec = 6'b111111; + 12'd193 : mem_out_dec = 6'b111111; + 12'd194 : mem_out_dec = 6'b111111; + 12'd195 : mem_out_dec = 6'b111111; + 12'd196 : mem_out_dec = 6'b111111; + 12'd197 : mem_out_dec = 6'b111111; + 12'd198 : mem_out_dec = 6'b111111; + 12'd199 : mem_out_dec = 6'b111111; + 12'd200 : mem_out_dec = 6'b111111; + 12'd201 : mem_out_dec = 6'b000100; + 12'd202 : mem_out_dec = 6'b000100; + 12'd203 : mem_out_dec = 6'b000101; + 12'd204 : mem_out_dec = 6'b000110; + 12'd205 : mem_out_dec = 6'b000111; + 12'd206 : mem_out_dec = 6'b001000; + 12'd207 : mem_out_dec = 6'b001000; + 12'd208 : mem_out_dec = 6'b001001; + 12'd209 : mem_out_dec = 6'b001001; + 12'd210 : mem_out_dec = 6'b001001; + 12'd211 : mem_out_dec = 6'b001001; + 12'd212 : mem_out_dec = 6'b001001; + 12'd213 : mem_out_dec = 6'b001001; + 12'd214 : mem_out_dec = 6'b001001; + 12'd215 : mem_out_dec = 6'b001010; + 12'd216 : mem_out_dec = 6'b001010; + 12'd217 : mem_out_dec = 6'b001011; + 12'd218 : mem_out_dec = 6'b001011; + 12'd219 : mem_out_dec = 6'b001100; + 12'd220 : mem_out_dec = 6'b001101; + 12'd221 : mem_out_dec = 6'b001110; + 12'd222 : mem_out_dec = 6'b001111; + 12'd223 : mem_out_dec = 6'b001111; + 12'd224 : mem_out_dec = 6'b010000; + 12'd225 : mem_out_dec = 6'b010000; + 12'd226 : mem_out_dec = 6'b010001; + 12'd227 : mem_out_dec = 6'b010001; + 12'd228 : mem_out_dec = 6'b010010; + 12'd229 : mem_out_dec = 6'b010010; + 12'd230 : mem_out_dec = 6'b010011; + 12'd231 : mem_out_dec = 6'b010011; + 12'd232 : mem_out_dec = 6'b010011; + 12'd233 : mem_out_dec = 6'b010100; + 12'd234 : mem_out_dec = 6'b010100; + 12'd235 : mem_out_dec = 6'b010101; + 12'd236 : mem_out_dec = 6'b010110; + 12'd237 : mem_out_dec = 6'b010111; + 12'd238 : mem_out_dec = 6'b011000; + 12'd239 : mem_out_dec = 6'b011000; + 12'd240 : mem_out_dec = 6'b011001; + 12'd241 : mem_out_dec = 6'b011001; + 12'd242 : mem_out_dec = 6'b011001; + 12'd243 : mem_out_dec = 6'b011001; + 12'd244 : mem_out_dec = 6'b011001; + 12'd245 : mem_out_dec = 6'b011001; + 12'd246 : mem_out_dec = 6'b011001; + 12'd247 : mem_out_dec = 6'b011001; + 12'd248 : mem_out_dec = 6'b011010; + 12'd249 : mem_out_dec = 6'b011010; + 12'd250 : mem_out_dec = 6'b011011; + 12'd251 : mem_out_dec = 6'b011100; + 12'd252 : mem_out_dec = 6'b011101; + 12'd253 : mem_out_dec = 6'b011110; + 12'd254 : mem_out_dec = 6'b011110; + 12'd255 : mem_out_dec = 6'b011111; + 12'd256 : mem_out_dec = 6'b111111; + 12'd257 : mem_out_dec = 6'b111111; + 12'd258 : mem_out_dec = 6'b111111; + 12'd259 : mem_out_dec = 6'b111111; + 12'd260 : mem_out_dec = 6'b111111; + 12'd261 : mem_out_dec = 6'b111111; + 12'd262 : mem_out_dec = 6'b111111; + 12'd263 : mem_out_dec = 6'b111111; + 12'd264 : mem_out_dec = 6'b111111; + 12'd265 : mem_out_dec = 6'b111111; + 12'd266 : mem_out_dec = 6'b000100; + 12'd267 : mem_out_dec = 6'b000101; + 12'd268 : mem_out_dec = 6'b000110; + 12'd269 : mem_out_dec = 6'b000110; + 12'd270 : mem_out_dec = 6'b000111; + 12'd271 : mem_out_dec = 6'b001000; + 12'd272 : mem_out_dec = 6'b001000; + 12'd273 : mem_out_dec = 6'b001000; + 12'd274 : mem_out_dec = 6'b001000; + 12'd275 : mem_out_dec = 6'b001000; + 12'd276 : mem_out_dec = 6'b001000; + 12'd277 : mem_out_dec = 6'b001000; + 12'd278 : mem_out_dec = 6'b001000; + 12'd279 : mem_out_dec = 6'b001001; + 12'd280 : mem_out_dec = 6'b001001; + 12'd281 : mem_out_dec = 6'b001010; + 12'd282 : mem_out_dec = 6'b001011; + 12'd283 : mem_out_dec = 6'b001100; + 12'd284 : mem_out_dec = 6'b001101; + 12'd285 : mem_out_dec = 6'b001101; + 12'd286 : mem_out_dec = 6'b001110; + 12'd287 : mem_out_dec = 6'b001111; + 12'd288 : mem_out_dec = 6'b001111; + 12'd289 : mem_out_dec = 6'b010000; + 12'd290 : mem_out_dec = 6'b010000; + 12'd291 : mem_out_dec = 6'b010001; + 12'd292 : mem_out_dec = 6'b010001; + 12'd293 : mem_out_dec = 6'b010010; + 12'd294 : mem_out_dec = 6'b010010; + 12'd295 : mem_out_dec = 6'b010011; + 12'd296 : mem_out_dec = 6'b010010; + 12'd297 : mem_out_dec = 6'b010011; + 12'd298 : mem_out_dec = 6'b010100; + 12'd299 : mem_out_dec = 6'b010101; + 12'd300 : mem_out_dec = 6'b010110; + 12'd301 : mem_out_dec = 6'b010110; + 12'd302 : mem_out_dec = 6'b010111; + 12'd303 : mem_out_dec = 6'b011000; + 12'd304 : mem_out_dec = 6'b011000; + 12'd305 : mem_out_dec = 6'b011000; + 12'd306 : mem_out_dec = 6'b011000; + 12'd307 : mem_out_dec = 6'b011000; + 12'd308 : mem_out_dec = 6'b011000; + 12'd309 : mem_out_dec = 6'b011000; + 12'd310 : mem_out_dec = 6'b011000; + 12'd311 : mem_out_dec = 6'b011001; + 12'd312 : mem_out_dec = 6'b011001; + 12'd313 : mem_out_dec = 6'b011010; + 12'd314 : mem_out_dec = 6'b011011; + 12'd315 : mem_out_dec = 6'b011100; + 12'd316 : mem_out_dec = 6'b011100; + 12'd317 : mem_out_dec = 6'b011101; + 12'd318 : mem_out_dec = 6'b011110; + 12'd319 : mem_out_dec = 6'b011111; + 12'd320 : mem_out_dec = 6'b111111; + 12'd321 : mem_out_dec = 6'b111111; + 12'd322 : mem_out_dec = 6'b111111; + 12'd323 : mem_out_dec = 6'b111111; + 12'd324 : mem_out_dec = 6'b111111; + 12'd325 : mem_out_dec = 6'b111111; + 12'd326 : mem_out_dec = 6'b111111; + 12'd327 : mem_out_dec = 6'b111111; + 12'd328 : mem_out_dec = 6'b111111; + 12'd329 : mem_out_dec = 6'b111111; + 12'd330 : mem_out_dec = 6'b111111; + 12'd331 : mem_out_dec = 6'b000100; + 12'd332 : mem_out_dec = 6'b000101; + 12'd333 : mem_out_dec = 6'b000110; + 12'd334 : mem_out_dec = 6'b000111; + 12'd335 : mem_out_dec = 6'b001000; + 12'd336 : mem_out_dec = 6'b000111; + 12'd337 : mem_out_dec = 6'b000111; + 12'd338 : mem_out_dec = 6'b000111; + 12'd339 : mem_out_dec = 6'b000111; + 12'd340 : mem_out_dec = 6'b000111; + 12'd341 : mem_out_dec = 6'b000111; + 12'd342 : mem_out_dec = 6'b001000; + 12'd343 : mem_out_dec = 6'b001001; + 12'd344 : mem_out_dec = 6'b001001; + 12'd345 : mem_out_dec = 6'b001010; + 12'd346 : mem_out_dec = 6'b001011; + 12'd347 : mem_out_dec = 6'b001011; + 12'd348 : mem_out_dec = 6'b001100; + 12'd349 : mem_out_dec = 6'b001101; + 12'd350 : mem_out_dec = 6'b001110; + 12'd351 : mem_out_dec = 6'b001110; + 12'd352 : mem_out_dec = 6'b001111; + 12'd353 : mem_out_dec = 6'b001111; + 12'd354 : mem_out_dec = 6'b010000; + 12'd355 : mem_out_dec = 6'b010000; + 12'd356 : mem_out_dec = 6'b010001; + 12'd357 : mem_out_dec = 6'b010001; + 12'd358 : mem_out_dec = 6'b010001; + 12'd359 : mem_out_dec = 6'b010010; + 12'd360 : mem_out_dec = 6'b010010; + 12'd361 : mem_out_dec = 6'b010011; + 12'd362 : mem_out_dec = 6'b010100; + 12'd363 : mem_out_dec = 6'b010100; + 12'd364 : mem_out_dec = 6'b010101; + 12'd365 : mem_out_dec = 6'b010110; + 12'd366 : mem_out_dec = 6'b010111; + 12'd367 : mem_out_dec = 6'b011000; + 12'd368 : mem_out_dec = 6'b010111; + 12'd369 : mem_out_dec = 6'b010111; + 12'd370 : mem_out_dec = 6'b010111; + 12'd371 : mem_out_dec = 6'b010111; + 12'd372 : mem_out_dec = 6'b010111; + 12'd373 : mem_out_dec = 6'b010111; + 12'd374 : mem_out_dec = 6'b011000; + 12'd375 : mem_out_dec = 6'b011001; + 12'd376 : mem_out_dec = 6'b011001; + 12'd377 : mem_out_dec = 6'b011010; + 12'd378 : mem_out_dec = 6'b011010; + 12'd379 : mem_out_dec = 6'b011011; + 12'd380 : mem_out_dec = 6'b011100; + 12'd381 : mem_out_dec = 6'b011101; + 12'd382 : mem_out_dec = 6'b011101; + 12'd383 : mem_out_dec = 6'b011110; + 12'd384 : mem_out_dec = 6'b111111; + 12'd385 : mem_out_dec = 6'b111111; + 12'd386 : mem_out_dec = 6'b111111; + 12'd387 : mem_out_dec = 6'b111111; + 12'd388 : mem_out_dec = 6'b111111; + 12'd389 : mem_out_dec = 6'b111111; + 12'd390 : mem_out_dec = 6'b111111; + 12'd391 : mem_out_dec = 6'b111111; + 12'd392 : mem_out_dec = 6'b111111; + 12'd393 : mem_out_dec = 6'b111111; + 12'd394 : mem_out_dec = 6'b111111; + 12'd395 : mem_out_dec = 6'b111111; + 12'd396 : mem_out_dec = 6'b000101; + 12'd397 : mem_out_dec = 6'b000110; + 12'd398 : mem_out_dec = 6'b000110; + 12'd399 : mem_out_dec = 6'b000111; + 12'd400 : mem_out_dec = 6'b000110; + 12'd401 : mem_out_dec = 6'b000110; + 12'd402 : mem_out_dec = 6'b000110; + 12'd403 : mem_out_dec = 6'b000110; + 12'd404 : mem_out_dec = 6'b000110; + 12'd405 : mem_out_dec = 6'b000111; + 12'd406 : mem_out_dec = 6'b001000; + 12'd407 : mem_out_dec = 6'b001000; + 12'd408 : mem_out_dec = 6'b001001; + 12'd409 : mem_out_dec = 6'b001001; + 12'd410 : mem_out_dec = 6'b001010; + 12'd411 : mem_out_dec = 6'b001011; + 12'd412 : mem_out_dec = 6'b001100; + 12'd413 : mem_out_dec = 6'b001100; + 12'd414 : mem_out_dec = 6'b001101; + 12'd415 : mem_out_dec = 6'b001110; + 12'd416 : mem_out_dec = 6'b001110; + 12'd417 : mem_out_dec = 6'b001111; + 12'd418 : mem_out_dec = 6'b001111; + 12'd419 : mem_out_dec = 6'b010000; + 12'd420 : mem_out_dec = 6'b010000; + 12'd421 : mem_out_dec = 6'b010000; + 12'd422 : mem_out_dec = 6'b010001; + 12'd423 : mem_out_dec = 6'b010001; + 12'd424 : mem_out_dec = 6'b010010; + 12'd425 : mem_out_dec = 6'b010011; + 12'd426 : mem_out_dec = 6'b010011; + 12'd427 : mem_out_dec = 6'b010100; + 12'd428 : mem_out_dec = 6'b010101; + 12'd429 : mem_out_dec = 6'b010110; + 12'd430 : mem_out_dec = 6'b010111; + 12'd431 : mem_out_dec = 6'b010111; + 12'd432 : mem_out_dec = 6'b010110; + 12'd433 : mem_out_dec = 6'b010110; + 12'd434 : mem_out_dec = 6'b010110; + 12'd435 : mem_out_dec = 6'b010110; + 12'd436 : mem_out_dec = 6'b010110; + 12'd437 : mem_out_dec = 6'b010111; + 12'd438 : mem_out_dec = 6'b010111; + 12'd439 : mem_out_dec = 6'b011000; + 12'd440 : mem_out_dec = 6'b011001; + 12'd441 : mem_out_dec = 6'b011001; + 12'd442 : mem_out_dec = 6'b011010; + 12'd443 : mem_out_dec = 6'b011011; + 12'd444 : mem_out_dec = 6'b011011; + 12'd445 : mem_out_dec = 6'b011100; + 12'd446 : mem_out_dec = 6'b011101; + 12'd447 : mem_out_dec = 6'b011110; + 12'd448 : mem_out_dec = 6'b111111; + 12'd449 : mem_out_dec = 6'b111111; + 12'd450 : mem_out_dec = 6'b111111; + 12'd451 : mem_out_dec = 6'b111111; + 12'd452 : mem_out_dec = 6'b111111; + 12'd453 : mem_out_dec = 6'b111111; + 12'd454 : mem_out_dec = 6'b111111; + 12'd455 : mem_out_dec = 6'b111111; + 12'd456 : mem_out_dec = 6'b111111; + 12'd457 : mem_out_dec = 6'b111111; + 12'd458 : mem_out_dec = 6'b111111; + 12'd459 : mem_out_dec = 6'b111111; + 12'd460 : mem_out_dec = 6'b111111; + 12'd461 : mem_out_dec = 6'b000101; + 12'd462 : mem_out_dec = 6'b000110; + 12'd463 : mem_out_dec = 6'b000110; + 12'd464 : mem_out_dec = 6'b000110; + 12'd465 : mem_out_dec = 6'b000110; + 12'd466 : mem_out_dec = 6'b000110; + 12'd467 : mem_out_dec = 6'b000110; + 12'd468 : mem_out_dec = 6'b000110; + 12'd469 : mem_out_dec = 6'b000111; + 12'd470 : mem_out_dec = 6'b000111; + 12'd471 : mem_out_dec = 6'b001000; + 12'd472 : mem_out_dec = 6'b001000; + 12'd473 : mem_out_dec = 6'b001001; + 12'd474 : mem_out_dec = 6'b001010; + 12'd475 : mem_out_dec = 6'b001011; + 12'd476 : mem_out_dec = 6'b001011; + 12'd477 : mem_out_dec = 6'b001100; + 12'd478 : mem_out_dec = 6'b001101; + 12'd479 : mem_out_dec = 6'b001110; + 12'd480 : mem_out_dec = 6'b001110; + 12'd481 : mem_out_dec = 6'b001110; + 12'd482 : mem_out_dec = 6'b001111; + 12'd483 : mem_out_dec = 6'b001111; + 12'd484 : mem_out_dec = 6'b010000; + 12'd485 : mem_out_dec = 6'b010000; + 12'd486 : mem_out_dec = 6'b010000; + 12'd487 : mem_out_dec = 6'b010001; + 12'd488 : mem_out_dec = 6'b010001; + 12'd489 : mem_out_dec = 6'b010010; + 12'd490 : mem_out_dec = 6'b010011; + 12'd491 : mem_out_dec = 6'b010100; + 12'd492 : mem_out_dec = 6'b010101; + 12'd493 : mem_out_dec = 6'b010101; + 12'd494 : mem_out_dec = 6'b010110; + 12'd495 : mem_out_dec = 6'b010110; + 12'd496 : mem_out_dec = 6'b010110; + 12'd497 : mem_out_dec = 6'b010110; + 12'd498 : mem_out_dec = 6'b010101; + 12'd499 : mem_out_dec = 6'b010101; + 12'd500 : mem_out_dec = 6'b010110; + 12'd501 : mem_out_dec = 6'b010111; + 12'd502 : mem_out_dec = 6'b010111; + 12'd503 : mem_out_dec = 6'b011000; + 12'd504 : mem_out_dec = 6'b011000; + 12'd505 : mem_out_dec = 6'b011001; + 12'd506 : mem_out_dec = 6'b011010; + 12'd507 : mem_out_dec = 6'b011010; + 12'd508 : mem_out_dec = 6'b011011; + 12'd509 : mem_out_dec = 6'b011100; + 12'd510 : mem_out_dec = 6'b011101; + 12'd511 : mem_out_dec = 6'b011101; + 12'd512 : mem_out_dec = 6'b111111; + 12'd513 : mem_out_dec = 6'b111111; + 12'd514 : mem_out_dec = 6'b111111; + 12'd515 : mem_out_dec = 6'b111111; + 12'd516 : mem_out_dec = 6'b111111; + 12'd517 : mem_out_dec = 6'b111111; + 12'd518 : mem_out_dec = 6'b111111; + 12'd519 : mem_out_dec = 6'b111111; + 12'd520 : mem_out_dec = 6'b111111; + 12'd521 : mem_out_dec = 6'b111111; + 12'd522 : mem_out_dec = 6'b111111; + 12'd523 : mem_out_dec = 6'b111111; + 12'd524 : mem_out_dec = 6'b111111; + 12'd525 : mem_out_dec = 6'b111111; + 12'd526 : mem_out_dec = 6'b000100; + 12'd527 : mem_out_dec = 6'b000101; + 12'd528 : mem_out_dec = 6'b000100; + 12'd529 : mem_out_dec = 6'b000100; + 12'd530 : mem_out_dec = 6'b000100; + 12'd531 : mem_out_dec = 6'b000101; + 12'd532 : mem_out_dec = 6'b000101; + 12'd533 : mem_out_dec = 6'b000110; + 12'd534 : mem_out_dec = 6'b000111; + 12'd535 : mem_out_dec = 6'b000111; + 12'd536 : mem_out_dec = 6'b000111; + 12'd537 : mem_out_dec = 6'b001000; + 12'd538 : mem_out_dec = 6'b001001; + 12'd539 : mem_out_dec = 6'b001010; + 12'd540 : mem_out_dec = 6'b001011; + 12'd541 : mem_out_dec = 6'b001011; + 12'd542 : mem_out_dec = 6'b001100; + 12'd543 : mem_out_dec = 6'b001101; + 12'd544 : mem_out_dec = 6'b001101; + 12'd545 : mem_out_dec = 6'b001101; + 12'd546 : mem_out_dec = 6'b001110; + 12'd547 : mem_out_dec = 6'b001110; + 12'd548 : mem_out_dec = 6'b001110; + 12'd549 : mem_out_dec = 6'b001111; + 12'd550 : mem_out_dec = 6'b010000; + 12'd551 : mem_out_dec = 6'b010000; + 12'd552 : mem_out_dec = 6'b010001; + 12'd553 : mem_out_dec = 6'b010001; + 12'd554 : mem_out_dec = 6'b010010; + 12'd555 : mem_out_dec = 6'b010010; + 12'd556 : mem_out_dec = 6'b010011; + 12'd557 : mem_out_dec = 6'b010100; + 12'd558 : mem_out_dec = 6'b010100; + 12'd559 : mem_out_dec = 6'b010100; + 12'd560 : mem_out_dec = 6'b010100; + 12'd561 : mem_out_dec = 6'b010100; + 12'd562 : mem_out_dec = 6'b010100; + 12'd563 : mem_out_dec = 6'b010101; + 12'd564 : mem_out_dec = 6'b010101; + 12'd565 : mem_out_dec = 6'b010110; + 12'd566 : mem_out_dec = 6'b010111; + 12'd567 : mem_out_dec = 6'b010111; + 12'd568 : mem_out_dec = 6'b010111; + 12'd569 : mem_out_dec = 6'b011000; + 12'd570 : mem_out_dec = 6'b011001; + 12'd571 : mem_out_dec = 6'b011010; + 12'd572 : mem_out_dec = 6'b011010; + 12'd573 : mem_out_dec = 6'b011011; + 12'd574 : mem_out_dec = 6'b011100; + 12'd575 : mem_out_dec = 6'b011101; + 12'd576 : mem_out_dec = 6'b111111; + 12'd577 : mem_out_dec = 6'b111111; + 12'd578 : mem_out_dec = 6'b111111; + 12'd579 : mem_out_dec = 6'b111111; + 12'd580 : mem_out_dec = 6'b111111; + 12'd581 : mem_out_dec = 6'b111111; + 12'd582 : mem_out_dec = 6'b111111; + 12'd583 : mem_out_dec = 6'b111111; + 12'd584 : mem_out_dec = 6'b111111; + 12'd585 : mem_out_dec = 6'b111111; + 12'd586 : mem_out_dec = 6'b111111; + 12'd587 : mem_out_dec = 6'b111111; + 12'd588 : mem_out_dec = 6'b111111; + 12'd589 : mem_out_dec = 6'b111111; + 12'd590 : mem_out_dec = 6'b111111; + 12'd591 : mem_out_dec = 6'b000100; + 12'd592 : mem_out_dec = 6'b000011; + 12'd593 : mem_out_dec = 6'b000011; + 12'd594 : mem_out_dec = 6'b000100; + 12'd595 : mem_out_dec = 6'b000101; + 12'd596 : mem_out_dec = 6'b000101; + 12'd597 : mem_out_dec = 6'b000110; + 12'd598 : mem_out_dec = 6'b000110; + 12'd599 : mem_out_dec = 6'b000111; + 12'd600 : mem_out_dec = 6'b000111; + 12'd601 : mem_out_dec = 6'b001000; + 12'd602 : mem_out_dec = 6'b001001; + 12'd603 : mem_out_dec = 6'b001010; + 12'd604 : mem_out_dec = 6'b001010; + 12'd605 : mem_out_dec = 6'b001011; + 12'd606 : mem_out_dec = 6'b001100; + 12'd607 : mem_out_dec = 6'b001101; + 12'd608 : mem_out_dec = 6'b001101; + 12'd609 : mem_out_dec = 6'b001101; + 12'd610 : mem_out_dec = 6'b001110; + 12'd611 : mem_out_dec = 6'b001110; + 12'd612 : mem_out_dec = 6'b001110; + 12'd613 : mem_out_dec = 6'b001111; + 12'd614 : mem_out_dec = 6'b010000; + 12'd615 : mem_out_dec = 6'b010000; + 12'd616 : mem_out_dec = 6'b010000; + 12'd617 : mem_out_dec = 6'b010001; + 12'd618 : mem_out_dec = 6'b010001; + 12'd619 : mem_out_dec = 6'b010010; + 12'd620 : mem_out_dec = 6'b010010; + 12'd621 : mem_out_dec = 6'b010011; + 12'd622 : mem_out_dec = 6'b010011; + 12'd623 : mem_out_dec = 6'b010100; + 12'd624 : mem_out_dec = 6'b010011; + 12'd625 : mem_out_dec = 6'b010011; + 12'd626 : mem_out_dec = 6'b010100; + 12'd627 : mem_out_dec = 6'b010100; + 12'd628 : mem_out_dec = 6'b010101; + 12'd629 : mem_out_dec = 6'b010110; + 12'd630 : mem_out_dec = 6'b010110; + 12'd631 : mem_out_dec = 6'b010111; + 12'd632 : mem_out_dec = 6'b010111; + 12'd633 : mem_out_dec = 6'b011000; + 12'd634 : mem_out_dec = 6'b011001; + 12'd635 : mem_out_dec = 6'b011001; + 12'd636 : mem_out_dec = 6'b011010; + 12'd637 : mem_out_dec = 6'b011011; + 12'd638 : mem_out_dec = 6'b011100; + 12'd639 : mem_out_dec = 6'b011100; + 12'd640 : mem_out_dec = 6'b111111; + 12'd641 : mem_out_dec = 6'b111111; + 12'd642 : mem_out_dec = 6'b111111; + 12'd643 : mem_out_dec = 6'b111111; + 12'd644 : mem_out_dec = 6'b111111; + 12'd645 : mem_out_dec = 6'b111111; + 12'd646 : mem_out_dec = 6'b111111; + 12'd647 : mem_out_dec = 6'b111111; + 12'd648 : mem_out_dec = 6'b111111; + 12'd649 : mem_out_dec = 6'b111111; + 12'd650 : mem_out_dec = 6'b111111; + 12'd651 : mem_out_dec = 6'b111111; + 12'd652 : mem_out_dec = 6'b111111; + 12'd653 : mem_out_dec = 6'b111111; + 12'd654 : mem_out_dec = 6'b111111; + 12'd655 : mem_out_dec = 6'b111111; + 12'd656 : mem_out_dec = 6'b000011; + 12'd657 : mem_out_dec = 6'b000011; + 12'd658 : mem_out_dec = 6'b000100; + 12'd659 : mem_out_dec = 6'b000100; + 12'd660 : mem_out_dec = 6'b000101; + 12'd661 : mem_out_dec = 6'b000110; + 12'd662 : mem_out_dec = 6'b000110; + 12'd663 : mem_out_dec = 6'b000111; + 12'd664 : mem_out_dec = 6'b000111; + 12'd665 : mem_out_dec = 6'b001000; + 12'd666 : mem_out_dec = 6'b001001; + 12'd667 : mem_out_dec = 6'b001001; + 12'd668 : mem_out_dec = 6'b001010; + 12'd669 : mem_out_dec = 6'b001011; + 12'd670 : mem_out_dec = 6'b001100; + 12'd671 : mem_out_dec = 6'b001100; + 12'd672 : mem_out_dec = 6'b001100; + 12'd673 : mem_out_dec = 6'b001101; + 12'd674 : mem_out_dec = 6'b001101; + 12'd675 : mem_out_dec = 6'b001101; + 12'd676 : mem_out_dec = 6'b001110; + 12'd677 : mem_out_dec = 6'b001111; + 12'd678 : mem_out_dec = 6'b001111; + 12'd679 : mem_out_dec = 6'b010000; + 12'd680 : mem_out_dec = 6'b010000; + 12'd681 : mem_out_dec = 6'b010000; + 12'd682 : mem_out_dec = 6'b010001; + 12'd683 : mem_out_dec = 6'b010001; + 12'd684 : mem_out_dec = 6'b010010; + 12'd685 : mem_out_dec = 6'b010010; + 12'd686 : mem_out_dec = 6'b010011; + 12'd687 : mem_out_dec = 6'b010011; + 12'd688 : mem_out_dec = 6'b010011; + 12'd689 : mem_out_dec = 6'b010011; + 12'd690 : mem_out_dec = 6'b010100; + 12'd691 : mem_out_dec = 6'b010100; + 12'd692 : mem_out_dec = 6'b010101; + 12'd693 : mem_out_dec = 6'b010101; + 12'd694 : mem_out_dec = 6'b010110; + 12'd695 : mem_out_dec = 6'b010111; + 12'd696 : mem_out_dec = 6'b010111; + 12'd697 : mem_out_dec = 6'b011000; + 12'd698 : mem_out_dec = 6'b011000; + 12'd699 : mem_out_dec = 6'b011001; + 12'd700 : mem_out_dec = 6'b011010; + 12'd701 : mem_out_dec = 6'b011011; + 12'd702 : mem_out_dec = 6'b011011; + 12'd703 : mem_out_dec = 6'b011100; + 12'd704 : mem_out_dec = 6'b111111; + 12'd705 : mem_out_dec = 6'b111111; + 12'd706 : mem_out_dec = 6'b111111; + 12'd707 : mem_out_dec = 6'b111111; + 12'd708 : mem_out_dec = 6'b111111; + 12'd709 : mem_out_dec = 6'b111111; + 12'd710 : mem_out_dec = 6'b111111; + 12'd711 : mem_out_dec = 6'b111111; + 12'd712 : mem_out_dec = 6'b111111; + 12'd713 : mem_out_dec = 6'b111111; + 12'd714 : mem_out_dec = 6'b111111; + 12'd715 : mem_out_dec = 6'b111111; + 12'd716 : mem_out_dec = 6'b111111; + 12'd717 : mem_out_dec = 6'b111111; + 12'd718 : mem_out_dec = 6'b111111; + 12'd719 : mem_out_dec = 6'b111111; + 12'd720 : mem_out_dec = 6'b111111; + 12'd721 : mem_out_dec = 6'b000011; + 12'd722 : mem_out_dec = 6'b000100; + 12'd723 : mem_out_dec = 6'b000100; + 12'd724 : mem_out_dec = 6'b000101; + 12'd725 : mem_out_dec = 6'b000101; + 12'd726 : mem_out_dec = 6'b000110; + 12'd727 : mem_out_dec = 6'b000111; + 12'd728 : mem_out_dec = 6'b000111; + 12'd729 : mem_out_dec = 6'b000111; + 12'd730 : mem_out_dec = 6'b001000; + 12'd731 : mem_out_dec = 6'b001001; + 12'd732 : mem_out_dec = 6'b001010; + 12'd733 : mem_out_dec = 6'b001011; + 12'd734 : mem_out_dec = 6'b001011; + 12'd735 : mem_out_dec = 6'b001100; + 12'd736 : mem_out_dec = 6'b001100; + 12'd737 : mem_out_dec = 6'b001101; + 12'd738 : mem_out_dec = 6'b001101; + 12'd739 : mem_out_dec = 6'b001101; + 12'd740 : mem_out_dec = 6'b001110; + 12'd741 : mem_out_dec = 6'b001110; + 12'd742 : mem_out_dec = 6'b001111; + 12'd743 : mem_out_dec = 6'b010000; + 12'd744 : mem_out_dec = 6'b001111; + 12'd745 : mem_out_dec = 6'b010000; + 12'd746 : mem_out_dec = 6'b010000; + 12'd747 : mem_out_dec = 6'b010001; + 12'd748 : mem_out_dec = 6'b010001; + 12'd749 : mem_out_dec = 6'b010010; + 12'd750 : mem_out_dec = 6'b010010; + 12'd751 : mem_out_dec = 6'b010011; + 12'd752 : mem_out_dec = 6'b010010; + 12'd753 : mem_out_dec = 6'b010011; + 12'd754 : mem_out_dec = 6'b010011; + 12'd755 : mem_out_dec = 6'b010100; + 12'd756 : mem_out_dec = 6'b010101; + 12'd757 : mem_out_dec = 6'b010101; + 12'd758 : mem_out_dec = 6'b010110; + 12'd759 : mem_out_dec = 6'b010110; + 12'd760 : mem_out_dec = 6'b010111; + 12'd761 : mem_out_dec = 6'b010111; + 12'd762 : mem_out_dec = 6'b011000; + 12'd763 : mem_out_dec = 6'b011001; + 12'd764 : mem_out_dec = 6'b011010; + 12'd765 : mem_out_dec = 6'b011010; + 12'd766 : mem_out_dec = 6'b011011; + 12'd767 : mem_out_dec = 6'b011100; + 12'd768 : mem_out_dec = 6'b111111; + 12'd769 : mem_out_dec = 6'b111111; + 12'd770 : mem_out_dec = 6'b111111; + 12'd771 : mem_out_dec = 6'b111111; + 12'd772 : mem_out_dec = 6'b111111; + 12'd773 : mem_out_dec = 6'b111111; + 12'd774 : mem_out_dec = 6'b111111; + 12'd775 : mem_out_dec = 6'b111111; + 12'd776 : mem_out_dec = 6'b111111; + 12'd777 : mem_out_dec = 6'b111111; + 12'd778 : mem_out_dec = 6'b111111; + 12'd779 : mem_out_dec = 6'b111111; + 12'd780 : mem_out_dec = 6'b111111; + 12'd781 : mem_out_dec = 6'b111111; + 12'd782 : mem_out_dec = 6'b111111; + 12'd783 : mem_out_dec = 6'b111111; + 12'd784 : mem_out_dec = 6'b111111; + 12'd785 : mem_out_dec = 6'b111111; + 12'd786 : mem_out_dec = 6'b000011; + 12'd787 : mem_out_dec = 6'b000100; + 12'd788 : mem_out_dec = 6'b000101; + 12'd789 : mem_out_dec = 6'b000101; + 12'd790 : mem_out_dec = 6'b000110; + 12'd791 : mem_out_dec = 6'b000110; + 12'd792 : mem_out_dec = 6'b000110; + 12'd793 : mem_out_dec = 6'b000111; + 12'd794 : mem_out_dec = 6'b001000; + 12'd795 : mem_out_dec = 6'b001001; + 12'd796 : mem_out_dec = 6'b001010; + 12'd797 : mem_out_dec = 6'b001010; + 12'd798 : mem_out_dec = 6'b001011; + 12'd799 : mem_out_dec = 6'b001100; + 12'd800 : mem_out_dec = 6'b001100; + 12'd801 : mem_out_dec = 6'b001100; + 12'd802 : mem_out_dec = 6'b001101; + 12'd803 : mem_out_dec = 6'b001101; + 12'd804 : mem_out_dec = 6'b001110; + 12'd805 : mem_out_dec = 6'b001110; + 12'd806 : mem_out_dec = 6'b001111; + 12'd807 : mem_out_dec = 6'b010000; + 12'd808 : mem_out_dec = 6'b001111; + 12'd809 : mem_out_dec = 6'b001111; + 12'd810 : mem_out_dec = 6'b010000; + 12'd811 : mem_out_dec = 6'b010000; + 12'd812 : mem_out_dec = 6'b010001; + 12'd813 : mem_out_dec = 6'b010001; + 12'd814 : mem_out_dec = 6'b010010; + 12'd815 : mem_out_dec = 6'b010010; + 12'd816 : mem_out_dec = 6'b010010; + 12'd817 : mem_out_dec = 6'b010011; + 12'd818 : mem_out_dec = 6'b010011; + 12'd819 : mem_out_dec = 6'b010100; + 12'd820 : mem_out_dec = 6'b010100; + 12'd821 : mem_out_dec = 6'b010101; + 12'd822 : mem_out_dec = 6'b010110; + 12'd823 : mem_out_dec = 6'b010110; + 12'd824 : mem_out_dec = 6'b010110; + 12'd825 : mem_out_dec = 6'b010111; + 12'd826 : mem_out_dec = 6'b011000; + 12'd827 : mem_out_dec = 6'b011001; + 12'd828 : mem_out_dec = 6'b011001; + 12'd829 : mem_out_dec = 6'b011010; + 12'd830 : mem_out_dec = 6'b011011; + 12'd831 : mem_out_dec = 6'b011100; + 12'd832 : mem_out_dec = 6'b111111; + 12'd833 : mem_out_dec = 6'b111111; + 12'd834 : mem_out_dec = 6'b111111; + 12'd835 : mem_out_dec = 6'b111111; + 12'd836 : mem_out_dec = 6'b111111; + 12'd837 : mem_out_dec = 6'b111111; + 12'd838 : mem_out_dec = 6'b111111; + 12'd839 : mem_out_dec = 6'b111111; + 12'd840 : mem_out_dec = 6'b111111; + 12'd841 : mem_out_dec = 6'b111111; + 12'd842 : mem_out_dec = 6'b111111; + 12'd843 : mem_out_dec = 6'b111111; + 12'd844 : mem_out_dec = 6'b111111; + 12'd845 : mem_out_dec = 6'b111111; + 12'd846 : mem_out_dec = 6'b111111; + 12'd847 : mem_out_dec = 6'b111111; + 12'd848 : mem_out_dec = 6'b111111; + 12'd849 : mem_out_dec = 6'b111111; + 12'd850 : mem_out_dec = 6'b111111; + 12'd851 : mem_out_dec = 6'b000100; + 12'd852 : mem_out_dec = 6'b000100; + 12'd853 : mem_out_dec = 6'b000101; + 12'd854 : mem_out_dec = 6'b000101; + 12'd855 : mem_out_dec = 6'b000110; + 12'd856 : mem_out_dec = 6'b000110; + 12'd857 : mem_out_dec = 6'b000111; + 12'd858 : mem_out_dec = 6'b001000; + 12'd859 : mem_out_dec = 6'b001001; + 12'd860 : mem_out_dec = 6'b001001; + 12'd861 : mem_out_dec = 6'b001010; + 12'd862 : mem_out_dec = 6'b001011; + 12'd863 : mem_out_dec = 6'b001100; + 12'd864 : mem_out_dec = 6'b001100; + 12'd865 : mem_out_dec = 6'b001100; + 12'd866 : mem_out_dec = 6'b001100; + 12'd867 : mem_out_dec = 6'b001101; + 12'd868 : mem_out_dec = 6'b001101; + 12'd869 : mem_out_dec = 6'b001110; + 12'd870 : mem_out_dec = 6'b001111; + 12'd871 : mem_out_dec = 6'b001111; + 12'd872 : mem_out_dec = 6'b001110; + 12'd873 : mem_out_dec = 6'b001111; + 12'd874 : mem_out_dec = 6'b001111; + 12'd875 : mem_out_dec = 6'b010000; + 12'd876 : mem_out_dec = 6'b010000; + 12'd877 : mem_out_dec = 6'b010001; + 12'd878 : mem_out_dec = 6'b010001; + 12'd879 : mem_out_dec = 6'b010010; + 12'd880 : mem_out_dec = 6'b010010; + 12'd881 : mem_out_dec = 6'b010010; + 12'd882 : mem_out_dec = 6'b010011; + 12'd883 : mem_out_dec = 6'b010100; + 12'd884 : mem_out_dec = 6'b010100; + 12'd885 : mem_out_dec = 6'b010101; + 12'd886 : mem_out_dec = 6'b010101; + 12'd887 : mem_out_dec = 6'b010110; + 12'd888 : mem_out_dec = 6'b010110; + 12'd889 : mem_out_dec = 6'b010111; + 12'd890 : mem_out_dec = 6'b011000; + 12'd891 : mem_out_dec = 6'b011000; + 12'd892 : mem_out_dec = 6'b011001; + 12'd893 : mem_out_dec = 6'b011010; + 12'd894 : mem_out_dec = 6'b011011; + 12'd895 : mem_out_dec = 6'b011011; + 12'd896 : mem_out_dec = 6'b111111; + 12'd897 : mem_out_dec = 6'b111111; + 12'd898 : mem_out_dec = 6'b111111; + 12'd899 : mem_out_dec = 6'b111111; + 12'd900 : mem_out_dec = 6'b111111; + 12'd901 : mem_out_dec = 6'b111111; + 12'd902 : mem_out_dec = 6'b111111; + 12'd903 : mem_out_dec = 6'b111111; + 12'd904 : mem_out_dec = 6'b111111; + 12'd905 : mem_out_dec = 6'b111111; + 12'd906 : mem_out_dec = 6'b111111; + 12'd907 : mem_out_dec = 6'b111111; + 12'd908 : mem_out_dec = 6'b111111; + 12'd909 : mem_out_dec = 6'b111111; + 12'd910 : mem_out_dec = 6'b111111; + 12'd911 : mem_out_dec = 6'b111111; + 12'd912 : mem_out_dec = 6'b111111; + 12'd913 : mem_out_dec = 6'b111111; + 12'd914 : mem_out_dec = 6'b111111; + 12'd915 : mem_out_dec = 6'b111111; + 12'd916 : mem_out_dec = 6'b000100; + 12'd917 : mem_out_dec = 6'b000101; + 12'd918 : mem_out_dec = 6'b000101; + 12'd919 : mem_out_dec = 6'b000110; + 12'd920 : mem_out_dec = 6'b000110; + 12'd921 : mem_out_dec = 6'b000111; + 12'd922 : mem_out_dec = 6'b001000; + 12'd923 : mem_out_dec = 6'b001000; + 12'd924 : mem_out_dec = 6'b001001; + 12'd925 : mem_out_dec = 6'b001010; + 12'd926 : mem_out_dec = 6'b001011; + 12'd927 : mem_out_dec = 6'b001011; + 12'd928 : mem_out_dec = 6'b001011; + 12'd929 : mem_out_dec = 6'b001100; + 12'd930 : mem_out_dec = 6'b001100; + 12'd931 : mem_out_dec = 6'b001101; + 12'd932 : mem_out_dec = 6'b001101; + 12'd933 : mem_out_dec = 6'b001110; + 12'd934 : mem_out_dec = 6'b001110; + 12'd935 : mem_out_dec = 6'b001111; + 12'd936 : mem_out_dec = 6'b001110; + 12'd937 : mem_out_dec = 6'b001110; + 12'd938 : mem_out_dec = 6'b001111; + 12'd939 : mem_out_dec = 6'b001111; + 12'd940 : mem_out_dec = 6'b010000; + 12'd941 : mem_out_dec = 6'b010000; + 12'd942 : mem_out_dec = 6'b010001; + 12'd943 : mem_out_dec = 6'b010001; + 12'd944 : mem_out_dec = 6'b010010; + 12'd945 : mem_out_dec = 6'b010010; + 12'd946 : mem_out_dec = 6'b010011; + 12'd947 : mem_out_dec = 6'b010011; + 12'd948 : mem_out_dec = 6'b010100; + 12'd949 : mem_out_dec = 6'b010100; + 12'd950 : mem_out_dec = 6'b010101; + 12'd951 : mem_out_dec = 6'b010110; + 12'd952 : mem_out_dec = 6'b010110; + 12'd953 : mem_out_dec = 6'b010111; + 12'd954 : mem_out_dec = 6'b010111; + 12'd955 : mem_out_dec = 6'b011000; + 12'd956 : mem_out_dec = 6'b011001; + 12'd957 : mem_out_dec = 6'b011010; + 12'd958 : mem_out_dec = 6'b011010; + 12'd959 : mem_out_dec = 6'b011011; + 12'd960 : mem_out_dec = 6'b111111; + 12'd961 : mem_out_dec = 6'b111111; + 12'd962 : mem_out_dec = 6'b111111; + 12'd963 : mem_out_dec = 6'b111111; + 12'd964 : mem_out_dec = 6'b111111; + 12'd965 : mem_out_dec = 6'b111111; + 12'd966 : mem_out_dec = 6'b111111; + 12'd967 : mem_out_dec = 6'b111111; + 12'd968 : mem_out_dec = 6'b111111; + 12'd969 : mem_out_dec = 6'b111111; + 12'd970 : mem_out_dec = 6'b111111; + 12'd971 : mem_out_dec = 6'b111111; + 12'd972 : mem_out_dec = 6'b111111; + 12'd973 : mem_out_dec = 6'b111111; + 12'd974 : mem_out_dec = 6'b111111; + 12'd975 : mem_out_dec = 6'b111111; + 12'd976 : mem_out_dec = 6'b111111; + 12'd977 : mem_out_dec = 6'b111111; + 12'd978 : mem_out_dec = 6'b111111; + 12'd979 : mem_out_dec = 6'b111111; + 12'd980 : mem_out_dec = 6'b111111; + 12'd981 : mem_out_dec = 6'b000100; + 12'd982 : mem_out_dec = 6'b000101; + 12'd983 : mem_out_dec = 6'b000110; + 12'd984 : mem_out_dec = 6'b000110; + 12'd985 : mem_out_dec = 6'b000111; + 12'd986 : mem_out_dec = 6'b000111; + 12'd987 : mem_out_dec = 6'b001000; + 12'd988 : mem_out_dec = 6'b001001; + 12'd989 : mem_out_dec = 6'b001010; + 12'd990 : mem_out_dec = 6'b001010; + 12'd991 : mem_out_dec = 6'b001011; + 12'd992 : mem_out_dec = 6'b001011; + 12'd993 : mem_out_dec = 6'b001011; + 12'd994 : mem_out_dec = 6'b001100; + 12'd995 : mem_out_dec = 6'b001100; + 12'd996 : mem_out_dec = 6'b001101; + 12'd997 : mem_out_dec = 6'b001110; + 12'd998 : mem_out_dec = 6'b001110; + 12'd999 : mem_out_dec = 6'b001110; + 12'd1000 : mem_out_dec = 6'b001101; + 12'd1001 : mem_out_dec = 6'b001110; + 12'd1002 : mem_out_dec = 6'b001110; + 12'd1003 : mem_out_dec = 6'b001111; + 12'd1004 : mem_out_dec = 6'b001111; + 12'd1005 : mem_out_dec = 6'b010000; + 12'd1006 : mem_out_dec = 6'b010000; + 12'd1007 : mem_out_dec = 6'b010001; + 12'd1008 : mem_out_dec = 6'b010001; + 12'd1009 : mem_out_dec = 6'b010010; + 12'd1010 : mem_out_dec = 6'b010011; + 12'd1011 : mem_out_dec = 6'b010011; + 12'd1012 : mem_out_dec = 6'b010100; + 12'd1013 : mem_out_dec = 6'b010100; + 12'd1014 : mem_out_dec = 6'b010101; + 12'd1015 : mem_out_dec = 6'b010110; + 12'd1016 : mem_out_dec = 6'b010110; + 12'd1017 : mem_out_dec = 6'b010110; + 12'd1018 : mem_out_dec = 6'b010111; + 12'd1019 : mem_out_dec = 6'b011000; + 12'd1020 : mem_out_dec = 6'b011001; + 12'd1021 : mem_out_dec = 6'b011001; + 12'd1022 : mem_out_dec = 6'b011010; + 12'd1023 : mem_out_dec = 6'b011011; + 12'd1024 : mem_out_dec = 6'b111111; + 12'd1025 : mem_out_dec = 6'b111111; + 12'd1026 : mem_out_dec = 6'b111111; + 12'd1027 : mem_out_dec = 6'b111111; + 12'd1028 : mem_out_dec = 6'b111111; + 12'd1029 : mem_out_dec = 6'b111111; + 12'd1030 : mem_out_dec = 6'b111111; + 12'd1031 : mem_out_dec = 6'b111111; + 12'd1032 : mem_out_dec = 6'b111111; + 12'd1033 : mem_out_dec = 6'b111111; + 12'd1034 : mem_out_dec = 6'b111111; + 12'd1035 : mem_out_dec = 6'b111111; + 12'd1036 : mem_out_dec = 6'b111111; + 12'd1037 : mem_out_dec = 6'b111111; + 12'd1038 : mem_out_dec = 6'b111111; + 12'd1039 : mem_out_dec = 6'b111111; + 12'd1040 : mem_out_dec = 6'b111111; + 12'd1041 : mem_out_dec = 6'b111111; + 12'd1042 : mem_out_dec = 6'b111111; + 12'd1043 : mem_out_dec = 6'b111111; + 12'd1044 : mem_out_dec = 6'b111111; + 12'd1045 : mem_out_dec = 6'b111111; + 12'd1046 : mem_out_dec = 6'b000100; + 12'd1047 : mem_out_dec = 6'b000101; + 12'd1048 : mem_out_dec = 6'b000101; + 12'd1049 : mem_out_dec = 6'b000110; + 12'd1050 : mem_out_dec = 6'b000110; + 12'd1051 : mem_out_dec = 6'b000111; + 12'd1052 : mem_out_dec = 6'b001000; + 12'd1053 : mem_out_dec = 6'b001001; + 12'd1054 : mem_out_dec = 6'b001001; + 12'd1055 : mem_out_dec = 6'b001010; + 12'd1056 : mem_out_dec = 6'b001010; + 12'd1057 : mem_out_dec = 6'b001011; + 12'd1058 : mem_out_dec = 6'b001011; + 12'd1059 : mem_out_dec = 6'b001100; + 12'd1060 : mem_out_dec = 6'b001100; + 12'd1061 : mem_out_dec = 6'b001100; + 12'd1062 : mem_out_dec = 6'b001100; + 12'd1063 : mem_out_dec = 6'b001100; + 12'd1064 : mem_out_dec = 6'b001100; + 12'd1065 : mem_out_dec = 6'b001100; + 12'd1066 : mem_out_dec = 6'b001101; + 12'd1067 : mem_out_dec = 6'b001101; + 12'd1068 : mem_out_dec = 6'b001110; + 12'd1069 : mem_out_dec = 6'b001111; + 12'd1070 : mem_out_dec = 6'b010000; + 12'd1071 : mem_out_dec = 6'b010000; + 12'd1072 : mem_out_dec = 6'b010001; + 12'd1073 : mem_out_dec = 6'b010001; + 12'd1074 : mem_out_dec = 6'b010010; + 12'd1075 : mem_out_dec = 6'b010010; + 12'd1076 : mem_out_dec = 6'b010011; + 12'd1077 : mem_out_dec = 6'b010011; + 12'd1078 : mem_out_dec = 6'b010100; + 12'd1079 : mem_out_dec = 6'b010101; + 12'd1080 : mem_out_dec = 6'b010101; + 12'd1081 : mem_out_dec = 6'b010110; + 12'd1082 : mem_out_dec = 6'b010110; + 12'd1083 : mem_out_dec = 6'b010111; + 12'd1084 : mem_out_dec = 6'b011000; + 12'd1085 : mem_out_dec = 6'b011000; + 12'd1086 : mem_out_dec = 6'b011001; + 12'd1087 : mem_out_dec = 6'b011010; + 12'd1088 : mem_out_dec = 6'b111111; + 12'd1089 : mem_out_dec = 6'b111111; + 12'd1090 : mem_out_dec = 6'b111111; + 12'd1091 : mem_out_dec = 6'b111111; + 12'd1092 : mem_out_dec = 6'b111111; + 12'd1093 : mem_out_dec = 6'b111111; + 12'd1094 : mem_out_dec = 6'b111111; + 12'd1095 : mem_out_dec = 6'b111111; + 12'd1096 : mem_out_dec = 6'b111111; + 12'd1097 : mem_out_dec = 6'b111111; + 12'd1098 : mem_out_dec = 6'b111111; + 12'd1099 : mem_out_dec = 6'b111111; + 12'd1100 : mem_out_dec = 6'b111111; + 12'd1101 : mem_out_dec = 6'b111111; + 12'd1102 : mem_out_dec = 6'b111111; + 12'd1103 : mem_out_dec = 6'b111111; + 12'd1104 : mem_out_dec = 6'b111111; + 12'd1105 : mem_out_dec = 6'b111111; + 12'd1106 : mem_out_dec = 6'b111111; + 12'd1107 : mem_out_dec = 6'b111111; + 12'd1108 : mem_out_dec = 6'b111111; + 12'd1109 : mem_out_dec = 6'b111111; + 12'd1110 : mem_out_dec = 6'b111111; + 12'd1111 : mem_out_dec = 6'b000100; + 12'd1112 : mem_out_dec = 6'b000100; + 12'd1113 : mem_out_dec = 6'b000101; + 12'd1114 : mem_out_dec = 6'b000110; + 12'd1115 : mem_out_dec = 6'b000111; + 12'd1116 : mem_out_dec = 6'b000111; + 12'd1117 : mem_out_dec = 6'b001000; + 12'd1118 : mem_out_dec = 6'b001001; + 12'd1119 : mem_out_dec = 6'b001001; + 12'd1120 : mem_out_dec = 6'b001010; + 12'd1121 : mem_out_dec = 6'b001010; + 12'd1122 : mem_out_dec = 6'b001011; + 12'd1123 : mem_out_dec = 6'b001011; + 12'd1124 : mem_out_dec = 6'b001011; + 12'd1125 : mem_out_dec = 6'b001011; + 12'd1126 : mem_out_dec = 6'b001011; + 12'd1127 : mem_out_dec = 6'b001011; + 12'd1128 : mem_out_dec = 6'b001011; + 12'd1129 : mem_out_dec = 6'b001011; + 12'd1130 : mem_out_dec = 6'b001100; + 12'd1131 : mem_out_dec = 6'b001101; + 12'd1132 : mem_out_dec = 6'b001110; + 12'd1133 : mem_out_dec = 6'b001110; + 12'd1134 : mem_out_dec = 6'b001111; + 12'd1135 : mem_out_dec = 6'b010000; + 12'd1136 : mem_out_dec = 6'b010000; + 12'd1137 : mem_out_dec = 6'b010001; + 12'd1138 : mem_out_dec = 6'b010001; + 12'd1139 : mem_out_dec = 6'b010010; + 12'd1140 : mem_out_dec = 6'b010010; + 12'd1141 : mem_out_dec = 6'b010011; + 12'd1142 : mem_out_dec = 6'b010100; + 12'd1143 : mem_out_dec = 6'b010100; + 12'd1144 : mem_out_dec = 6'b010100; + 12'd1145 : mem_out_dec = 6'b010101; + 12'd1146 : mem_out_dec = 6'b010110; + 12'd1147 : mem_out_dec = 6'b010110; + 12'd1148 : mem_out_dec = 6'b010111; + 12'd1149 : mem_out_dec = 6'b011000; + 12'd1150 : mem_out_dec = 6'b011000; + 12'd1151 : mem_out_dec = 6'b011001; + 12'd1152 : mem_out_dec = 6'b111111; + 12'd1153 : mem_out_dec = 6'b111111; + 12'd1154 : mem_out_dec = 6'b111111; + 12'd1155 : mem_out_dec = 6'b111111; + 12'd1156 : mem_out_dec = 6'b111111; + 12'd1157 : mem_out_dec = 6'b111111; + 12'd1158 : mem_out_dec = 6'b111111; + 12'd1159 : mem_out_dec = 6'b111111; + 12'd1160 : mem_out_dec = 6'b111111; + 12'd1161 : mem_out_dec = 6'b111111; + 12'd1162 : mem_out_dec = 6'b111111; + 12'd1163 : mem_out_dec = 6'b111111; + 12'd1164 : mem_out_dec = 6'b111111; + 12'd1165 : mem_out_dec = 6'b111111; + 12'd1166 : mem_out_dec = 6'b111111; + 12'd1167 : mem_out_dec = 6'b111111; + 12'd1168 : mem_out_dec = 6'b111111; + 12'd1169 : mem_out_dec = 6'b111111; + 12'd1170 : mem_out_dec = 6'b111111; + 12'd1171 : mem_out_dec = 6'b111111; + 12'd1172 : mem_out_dec = 6'b111111; + 12'd1173 : mem_out_dec = 6'b111111; + 12'd1174 : mem_out_dec = 6'b111111; + 12'd1175 : mem_out_dec = 6'b111111; + 12'd1176 : mem_out_dec = 6'b000100; + 12'd1177 : mem_out_dec = 6'b000101; + 12'd1178 : mem_out_dec = 6'b000101; + 12'd1179 : mem_out_dec = 6'b000110; + 12'd1180 : mem_out_dec = 6'b000111; + 12'd1181 : mem_out_dec = 6'b000111; + 12'd1182 : mem_out_dec = 6'b001000; + 12'd1183 : mem_out_dec = 6'b001001; + 12'd1184 : mem_out_dec = 6'b001001; + 12'd1185 : mem_out_dec = 6'b001010; + 12'd1186 : mem_out_dec = 6'b001010; + 12'd1187 : mem_out_dec = 6'b001010; + 12'd1188 : mem_out_dec = 6'b001010; + 12'd1189 : mem_out_dec = 6'b001010; + 12'd1190 : mem_out_dec = 6'b001010; + 12'd1191 : mem_out_dec = 6'b001010; + 12'd1192 : mem_out_dec = 6'b001010; + 12'd1193 : mem_out_dec = 6'b001011; + 12'd1194 : mem_out_dec = 6'b001100; + 12'd1195 : mem_out_dec = 6'b001100; + 12'd1196 : mem_out_dec = 6'b001101; + 12'd1197 : mem_out_dec = 6'b001110; + 12'd1198 : mem_out_dec = 6'b001111; + 12'd1199 : mem_out_dec = 6'b010000; + 12'd1200 : mem_out_dec = 6'b010000; + 12'd1201 : mem_out_dec = 6'b010000; + 12'd1202 : mem_out_dec = 6'b010001; + 12'd1203 : mem_out_dec = 6'b010001; + 12'd1204 : mem_out_dec = 6'b010010; + 12'd1205 : mem_out_dec = 6'b010011; + 12'd1206 : mem_out_dec = 6'b010011; + 12'd1207 : mem_out_dec = 6'b010100; + 12'd1208 : mem_out_dec = 6'b010100; + 12'd1209 : mem_out_dec = 6'b010100; + 12'd1210 : mem_out_dec = 6'b010101; + 12'd1211 : mem_out_dec = 6'b010110; + 12'd1212 : mem_out_dec = 6'b010110; + 12'd1213 : mem_out_dec = 6'b010111; + 12'd1214 : mem_out_dec = 6'b011000; + 12'd1215 : mem_out_dec = 6'b011001; + 12'd1216 : mem_out_dec = 6'b111111; + 12'd1217 : mem_out_dec = 6'b111111; + 12'd1218 : mem_out_dec = 6'b111111; + 12'd1219 : mem_out_dec = 6'b111111; + 12'd1220 : mem_out_dec = 6'b111111; + 12'd1221 : mem_out_dec = 6'b111111; + 12'd1222 : mem_out_dec = 6'b111111; + 12'd1223 : mem_out_dec = 6'b111111; + 12'd1224 : mem_out_dec = 6'b111111; + 12'd1225 : mem_out_dec = 6'b111111; + 12'd1226 : mem_out_dec = 6'b111111; + 12'd1227 : mem_out_dec = 6'b111111; + 12'd1228 : mem_out_dec = 6'b111111; + 12'd1229 : mem_out_dec = 6'b111111; + 12'd1230 : mem_out_dec = 6'b111111; + 12'd1231 : mem_out_dec = 6'b111111; + 12'd1232 : mem_out_dec = 6'b111111; + 12'd1233 : mem_out_dec = 6'b111111; + 12'd1234 : mem_out_dec = 6'b111111; + 12'd1235 : mem_out_dec = 6'b111111; + 12'd1236 : mem_out_dec = 6'b111111; + 12'd1237 : mem_out_dec = 6'b111111; + 12'd1238 : mem_out_dec = 6'b111111; + 12'd1239 : mem_out_dec = 6'b111111; + 12'd1240 : mem_out_dec = 6'b111111; + 12'd1241 : mem_out_dec = 6'b000100; + 12'd1242 : mem_out_dec = 6'b000100; + 12'd1243 : mem_out_dec = 6'b000101; + 12'd1244 : mem_out_dec = 6'b000110; + 12'd1245 : mem_out_dec = 6'b000111; + 12'd1246 : mem_out_dec = 6'b001000; + 12'd1247 : mem_out_dec = 6'b001000; + 12'd1248 : mem_out_dec = 6'b001001; + 12'd1249 : mem_out_dec = 6'b001001; + 12'd1250 : mem_out_dec = 6'b001001; + 12'd1251 : mem_out_dec = 6'b001001; + 12'd1252 : mem_out_dec = 6'b001001; + 12'd1253 : mem_out_dec = 6'b001001; + 12'd1254 : mem_out_dec = 6'b001001; + 12'd1255 : mem_out_dec = 6'b001001; + 12'd1256 : mem_out_dec = 6'b001010; + 12'd1257 : mem_out_dec = 6'b001010; + 12'd1258 : mem_out_dec = 6'b001011; + 12'd1259 : mem_out_dec = 6'b001100; + 12'd1260 : mem_out_dec = 6'b001101; + 12'd1261 : mem_out_dec = 6'b001110; + 12'd1262 : mem_out_dec = 6'b001110; + 12'd1263 : mem_out_dec = 6'b001111; + 12'd1264 : mem_out_dec = 6'b001111; + 12'd1265 : mem_out_dec = 6'b010000; + 12'd1266 : mem_out_dec = 6'b010000; + 12'd1267 : mem_out_dec = 6'b010001; + 12'd1268 : mem_out_dec = 6'b010001; + 12'd1269 : mem_out_dec = 6'b010010; + 12'd1270 : mem_out_dec = 6'b010011; + 12'd1271 : mem_out_dec = 6'b010011; + 12'd1272 : mem_out_dec = 6'b010011; + 12'd1273 : mem_out_dec = 6'b010100; + 12'd1274 : mem_out_dec = 6'b010100; + 12'd1275 : mem_out_dec = 6'b010101; + 12'd1276 : mem_out_dec = 6'b010110; + 12'd1277 : mem_out_dec = 6'b010111; + 12'd1278 : mem_out_dec = 6'b011000; + 12'd1279 : mem_out_dec = 6'b011000; + 12'd1280 : mem_out_dec = 6'b111111; + 12'd1281 : mem_out_dec = 6'b111111; + 12'd1282 : mem_out_dec = 6'b111111; + 12'd1283 : mem_out_dec = 6'b111111; + 12'd1284 : mem_out_dec = 6'b111111; + 12'd1285 : mem_out_dec = 6'b111111; + 12'd1286 : mem_out_dec = 6'b111111; + 12'd1287 : mem_out_dec = 6'b111111; + 12'd1288 : mem_out_dec = 6'b111111; + 12'd1289 : mem_out_dec = 6'b111111; + 12'd1290 : mem_out_dec = 6'b111111; + 12'd1291 : mem_out_dec = 6'b111111; + 12'd1292 : mem_out_dec = 6'b111111; + 12'd1293 : mem_out_dec = 6'b111111; + 12'd1294 : mem_out_dec = 6'b111111; + 12'd1295 : mem_out_dec = 6'b111111; + 12'd1296 : mem_out_dec = 6'b111111; + 12'd1297 : mem_out_dec = 6'b111111; + 12'd1298 : mem_out_dec = 6'b111111; + 12'd1299 : mem_out_dec = 6'b111111; + 12'd1300 : mem_out_dec = 6'b111111; + 12'd1301 : mem_out_dec = 6'b111111; + 12'd1302 : mem_out_dec = 6'b111111; + 12'd1303 : mem_out_dec = 6'b111111; + 12'd1304 : mem_out_dec = 6'b111111; + 12'd1305 : mem_out_dec = 6'b111111; + 12'd1306 : mem_out_dec = 6'b000100; + 12'd1307 : mem_out_dec = 6'b000101; + 12'd1308 : mem_out_dec = 6'b000110; + 12'd1309 : mem_out_dec = 6'b000110; + 12'd1310 : mem_out_dec = 6'b000111; + 12'd1311 : mem_out_dec = 6'b001000; + 12'd1312 : mem_out_dec = 6'b001000; + 12'd1313 : mem_out_dec = 6'b001000; + 12'd1314 : mem_out_dec = 6'b001000; + 12'd1315 : mem_out_dec = 6'b001000; + 12'd1316 : mem_out_dec = 6'b001000; + 12'd1317 : mem_out_dec = 6'b001000; + 12'd1318 : mem_out_dec = 6'b001000; + 12'd1319 : mem_out_dec = 6'b001001; + 12'd1320 : mem_out_dec = 6'b001001; + 12'd1321 : mem_out_dec = 6'b001010; + 12'd1322 : mem_out_dec = 6'b001011; + 12'd1323 : mem_out_dec = 6'b001100; + 12'd1324 : mem_out_dec = 6'b001100; + 12'd1325 : mem_out_dec = 6'b001101; + 12'd1326 : mem_out_dec = 6'b001110; + 12'd1327 : mem_out_dec = 6'b001111; + 12'd1328 : mem_out_dec = 6'b001111; + 12'd1329 : mem_out_dec = 6'b001111; + 12'd1330 : mem_out_dec = 6'b010000; + 12'd1331 : mem_out_dec = 6'b010000; + 12'd1332 : mem_out_dec = 6'b010001; + 12'd1333 : mem_out_dec = 6'b010001; + 12'd1334 : mem_out_dec = 6'b010010; + 12'd1335 : mem_out_dec = 6'b010011; + 12'd1336 : mem_out_dec = 6'b010010; + 12'd1337 : mem_out_dec = 6'b010011; + 12'd1338 : mem_out_dec = 6'b010100; + 12'd1339 : mem_out_dec = 6'b010101; + 12'd1340 : mem_out_dec = 6'b010110; + 12'd1341 : mem_out_dec = 6'b010110; + 12'd1342 : mem_out_dec = 6'b010111; + 12'd1343 : mem_out_dec = 6'b011000; + 12'd1344 : mem_out_dec = 6'b111111; + 12'd1345 : mem_out_dec = 6'b111111; + 12'd1346 : mem_out_dec = 6'b111111; + 12'd1347 : mem_out_dec = 6'b111111; + 12'd1348 : mem_out_dec = 6'b111111; + 12'd1349 : mem_out_dec = 6'b111111; + 12'd1350 : mem_out_dec = 6'b111111; + 12'd1351 : mem_out_dec = 6'b111111; + 12'd1352 : mem_out_dec = 6'b111111; + 12'd1353 : mem_out_dec = 6'b111111; + 12'd1354 : mem_out_dec = 6'b111111; + 12'd1355 : mem_out_dec = 6'b111111; + 12'd1356 : mem_out_dec = 6'b111111; + 12'd1357 : mem_out_dec = 6'b111111; + 12'd1358 : mem_out_dec = 6'b111111; + 12'd1359 : mem_out_dec = 6'b111111; + 12'd1360 : mem_out_dec = 6'b111111; + 12'd1361 : mem_out_dec = 6'b111111; + 12'd1362 : mem_out_dec = 6'b111111; + 12'd1363 : mem_out_dec = 6'b111111; + 12'd1364 : mem_out_dec = 6'b111111; + 12'd1365 : mem_out_dec = 6'b111111; + 12'd1366 : mem_out_dec = 6'b111111; + 12'd1367 : mem_out_dec = 6'b111111; + 12'd1368 : mem_out_dec = 6'b111111; + 12'd1369 : mem_out_dec = 6'b111111; + 12'd1370 : mem_out_dec = 6'b111111; + 12'd1371 : mem_out_dec = 6'b000101; + 12'd1372 : mem_out_dec = 6'b000101; + 12'd1373 : mem_out_dec = 6'b000110; + 12'd1374 : mem_out_dec = 6'b000111; + 12'd1375 : mem_out_dec = 6'b001000; + 12'd1376 : mem_out_dec = 6'b000111; + 12'd1377 : mem_out_dec = 6'b000111; + 12'd1378 : mem_out_dec = 6'b000111; + 12'd1379 : mem_out_dec = 6'b000111; + 12'd1380 : mem_out_dec = 6'b000111; + 12'd1381 : mem_out_dec = 6'b000111; + 12'd1382 : mem_out_dec = 6'b001000; + 12'd1383 : mem_out_dec = 6'b001001; + 12'd1384 : mem_out_dec = 6'b001001; + 12'd1385 : mem_out_dec = 6'b001010; + 12'd1386 : mem_out_dec = 6'b001010; + 12'd1387 : mem_out_dec = 6'b001011; + 12'd1388 : mem_out_dec = 6'b001100; + 12'd1389 : mem_out_dec = 6'b001101; + 12'd1390 : mem_out_dec = 6'b001110; + 12'd1391 : mem_out_dec = 6'b001110; + 12'd1392 : mem_out_dec = 6'b001111; + 12'd1393 : mem_out_dec = 6'b001111; + 12'd1394 : mem_out_dec = 6'b010000; + 12'd1395 : mem_out_dec = 6'b010000; + 12'd1396 : mem_out_dec = 6'b010001; + 12'd1397 : mem_out_dec = 6'b010001; + 12'd1398 : mem_out_dec = 6'b010010; + 12'd1399 : mem_out_dec = 6'b010010; + 12'd1400 : mem_out_dec = 6'b010010; + 12'd1401 : mem_out_dec = 6'b010011; + 12'd1402 : mem_out_dec = 6'b010100; + 12'd1403 : mem_out_dec = 6'b010100; + 12'd1404 : mem_out_dec = 6'b010101; + 12'd1405 : mem_out_dec = 6'b010110; + 12'd1406 : mem_out_dec = 6'b010111; + 12'd1407 : mem_out_dec = 6'b010111; + 12'd1408 : mem_out_dec = 6'b111111; + 12'd1409 : mem_out_dec = 6'b111111; + 12'd1410 : mem_out_dec = 6'b111111; + 12'd1411 : mem_out_dec = 6'b111111; + 12'd1412 : mem_out_dec = 6'b111111; + 12'd1413 : mem_out_dec = 6'b111111; + 12'd1414 : mem_out_dec = 6'b111111; + 12'd1415 : mem_out_dec = 6'b111111; + 12'd1416 : mem_out_dec = 6'b111111; + 12'd1417 : mem_out_dec = 6'b111111; + 12'd1418 : mem_out_dec = 6'b111111; + 12'd1419 : mem_out_dec = 6'b111111; + 12'd1420 : mem_out_dec = 6'b111111; + 12'd1421 : mem_out_dec = 6'b111111; + 12'd1422 : mem_out_dec = 6'b111111; + 12'd1423 : mem_out_dec = 6'b111111; + 12'd1424 : mem_out_dec = 6'b111111; + 12'd1425 : mem_out_dec = 6'b111111; + 12'd1426 : mem_out_dec = 6'b111111; + 12'd1427 : mem_out_dec = 6'b111111; + 12'd1428 : mem_out_dec = 6'b111111; + 12'd1429 : mem_out_dec = 6'b111111; + 12'd1430 : mem_out_dec = 6'b111111; + 12'd1431 : mem_out_dec = 6'b111111; + 12'd1432 : mem_out_dec = 6'b111111; + 12'd1433 : mem_out_dec = 6'b111111; + 12'd1434 : mem_out_dec = 6'b111111; + 12'd1435 : mem_out_dec = 6'b111111; + 12'd1436 : mem_out_dec = 6'b000101; + 12'd1437 : mem_out_dec = 6'b000110; + 12'd1438 : mem_out_dec = 6'b000111; + 12'd1439 : mem_out_dec = 6'b000111; + 12'd1440 : mem_out_dec = 6'b000110; + 12'd1441 : mem_out_dec = 6'b000110; + 12'd1442 : mem_out_dec = 6'b000110; + 12'd1443 : mem_out_dec = 6'b000110; + 12'd1444 : mem_out_dec = 6'b000110; + 12'd1445 : mem_out_dec = 6'b000111; + 12'd1446 : mem_out_dec = 6'b000111; + 12'd1447 : mem_out_dec = 6'b001000; + 12'd1448 : mem_out_dec = 6'b001001; + 12'd1449 : mem_out_dec = 6'b001001; + 12'd1450 : mem_out_dec = 6'b001010; + 12'd1451 : mem_out_dec = 6'b001011; + 12'd1452 : mem_out_dec = 6'b001100; + 12'd1453 : mem_out_dec = 6'b001100; + 12'd1454 : mem_out_dec = 6'b001101; + 12'd1455 : mem_out_dec = 6'b001110; + 12'd1456 : mem_out_dec = 6'b001110; + 12'd1457 : mem_out_dec = 6'b001111; + 12'd1458 : mem_out_dec = 6'b001111; + 12'd1459 : mem_out_dec = 6'b010000; + 12'd1460 : mem_out_dec = 6'b010000; + 12'd1461 : mem_out_dec = 6'b010001; + 12'd1462 : mem_out_dec = 6'b010001; + 12'd1463 : mem_out_dec = 6'b010010; + 12'd1464 : mem_out_dec = 6'b010010; + 12'd1465 : mem_out_dec = 6'b010011; + 12'd1466 : mem_out_dec = 6'b010011; + 12'd1467 : mem_out_dec = 6'b010100; + 12'd1468 : mem_out_dec = 6'b010101; + 12'd1469 : mem_out_dec = 6'b010110; + 12'd1470 : mem_out_dec = 6'b010110; + 12'd1471 : mem_out_dec = 6'b010111; + 12'd1472 : mem_out_dec = 6'b111111; + 12'd1473 : mem_out_dec = 6'b111111; + 12'd1474 : mem_out_dec = 6'b111111; + 12'd1475 : mem_out_dec = 6'b111111; + 12'd1476 : mem_out_dec = 6'b111111; + 12'd1477 : mem_out_dec = 6'b111111; + 12'd1478 : mem_out_dec = 6'b111111; + 12'd1479 : mem_out_dec = 6'b111111; + 12'd1480 : mem_out_dec = 6'b111111; + 12'd1481 : mem_out_dec = 6'b111111; + 12'd1482 : mem_out_dec = 6'b111111; + 12'd1483 : mem_out_dec = 6'b111111; + 12'd1484 : mem_out_dec = 6'b111111; + 12'd1485 : mem_out_dec = 6'b111111; + 12'd1486 : mem_out_dec = 6'b111111; + 12'd1487 : mem_out_dec = 6'b111111; + 12'd1488 : mem_out_dec = 6'b111111; + 12'd1489 : mem_out_dec = 6'b111111; + 12'd1490 : mem_out_dec = 6'b111111; + 12'd1491 : mem_out_dec = 6'b111111; + 12'd1492 : mem_out_dec = 6'b111111; + 12'd1493 : mem_out_dec = 6'b111111; + 12'd1494 : mem_out_dec = 6'b111111; + 12'd1495 : mem_out_dec = 6'b111111; + 12'd1496 : mem_out_dec = 6'b111111; + 12'd1497 : mem_out_dec = 6'b111111; + 12'd1498 : mem_out_dec = 6'b111111; + 12'd1499 : mem_out_dec = 6'b111111; + 12'd1500 : mem_out_dec = 6'b111111; + 12'd1501 : mem_out_dec = 6'b000101; + 12'd1502 : mem_out_dec = 6'b000110; + 12'd1503 : mem_out_dec = 6'b000110; + 12'd1504 : mem_out_dec = 6'b000110; + 12'd1505 : mem_out_dec = 6'b000110; + 12'd1506 : mem_out_dec = 6'b000101; + 12'd1507 : mem_out_dec = 6'b000101; + 12'd1508 : mem_out_dec = 6'b000110; + 12'd1509 : mem_out_dec = 6'b000111; + 12'd1510 : mem_out_dec = 6'b000111; + 12'd1511 : mem_out_dec = 6'b001000; + 12'd1512 : mem_out_dec = 6'b001000; + 12'd1513 : mem_out_dec = 6'b001001; + 12'd1514 : mem_out_dec = 6'b001010; + 12'd1515 : mem_out_dec = 6'b001011; + 12'd1516 : mem_out_dec = 6'b001011; + 12'd1517 : mem_out_dec = 6'b001100; + 12'd1518 : mem_out_dec = 6'b001101; + 12'd1519 : mem_out_dec = 6'b001110; + 12'd1520 : mem_out_dec = 6'b001110; + 12'd1521 : mem_out_dec = 6'b001110; + 12'd1522 : mem_out_dec = 6'b001111; + 12'd1523 : mem_out_dec = 6'b001111; + 12'd1524 : mem_out_dec = 6'b010000; + 12'd1525 : mem_out_dec = 6'b010000; + 12'd1526 : mem_out_dec = 6'b010001; + 12'd1527 : mem_out_dec = 6'b010001; + 12'd1528 : mem_out_dec = 6'b010001; + 12'd1529 : mem_out_dec = 6'b010010; + 12'd1530 : mem_out_dec = 6'b010011; + 12'd1531 : mem_out_dec = 6'b010100; + 12'd1532 : mem_out_dec = 6'b010101; + 12'd1533 : mem_out_dec = 6'b010101; + 12'd1534 : mem_out_dec = 6'b010110; + 12'd1535 : mem_out_dec = 6'b010110; + 12'd1536 : mem_out_dec = 6'b111111; + 12'd1537 : mem_out_dec = 6'b111111; + 12'd1538 : mem_out_dec = 6'b111111; + 12'd1539 : mem_out_dec = 6'b111111; + 12'd1540 : mem_out_dec = 6'b111111; + 12'd1541 : mem_out_dec = 6'b111111; + 12'd1542 : mem_out_dec = 6'b111111; + 12'd1543 : mem_out_dec = 6'b111111; + 12'd1544 : mem_out_dec = 6'b111111; + 12'd1545 : mem_out_dec = 6'b111111; + 12'd1546 : mem_out_dec = 6'b111111; + 12'd1547 : mem_out_dec = 6'b111111; + 12'd1548 : mem_out_dec = 6'b111111; + 12'd1549 : mem_out_dec = 6'b111111; + 12'd1550 : mem_out_dec = 6'b111111; + 12'd1551 : mem_out_dec = 6'b111111; + 12'd1552 : mem_out_dec = 6'b111111; + 12'd1553 : mem_out_dec = 6'b111111; + 12'd1554 : mem_out_dec = 6'b111111; + 12'd1555 : mem_out_dec = 6'b111111; + 12'd1556 : mem_out_dec = 6'b111111; + 12'd1557 : mem_out_dec = 6'b111111; + 12'd1558 : mem_out_dec = 6'b111111; + 12'd1559 : mem_out_dec = 6'b111111; + 12'd1560 : mem_out_dec = 6'b111111; + 12'd1561 : mem_out_dec = 6'b111111; + 12'd1562 : mem_out_dec = 6'b111111; + 12'd1563 : mem_out_dec = 6'b111111; + 12'd1564 : mem_out_dec = 6'b111111; + 12'd1565 : mem_out_dec = 6'b111111; + 12'd1566 : mem_out_dec = 6'b000100; + 12'd1567 : mem_out_dec = 6'b000100; + 12'd1568 : mem_out_dec = 6'b000100; + 12'd1569 : mem_out_dec = 6'b000100; + 12'd1570 : mem_out_dec = 6'b000100; + 12'd1571 : mem_out_dec = 6'b000101; + 12'd1572 : mem_out_dec = 6'b000101; + 12'd1573 : mem_out_dec = 6'b000110; + 12'd1574 : mem_out_dec = 6'b000111; + 12'd1575 : mem_out_dec = 6'b000111; + 12'd1576 : mem_out_dec = 6'b000111; + 12'd1577 : mem_out_dec = 6'b001000; + 12'd1578 : mem_out_dec = 6'b001001; + 12'd1579 : mem_out_dec = 6'b001010; + 12'd1580 : mem_out_dec = 6'b001010; + 12'd1581 : mem_out_dec = 6'b001011; + 12'd1582 : mem_out_dec = 6'b001100; + 12'd1583 : mem_out_dec = 6'b001101; + 12'd1584 : mem_out_dec = 6'b001101; + 12'd1585 : mem_out_dec = 6'b001101; + 12'd1586 : mem_out_dec = 6'b001110; + 12'd1587 : mem_out_dec = 6'b001110; + 12'd1588 : mem_out_dec = 6'b001111; + 12'd1589 : mem_out_dec = 6'b001111; + 12'd1590 : mem_out_dec = 6'b010000; + 12'd1591 : mem_out_dec = 6'b010001; + 12'd1592 : mem_out_dec = 6'b010001; + 12'd1593 : mem_out_dec = 6'b010001; + 12'd1594 : mem_out_dec = 6'b010010; + 12'd1595 : mem_out_dec = 6'b010010; + 12'd1596 : mem_out_dec = 6'b010011; + 12'd1597 : mem_out_dec = 6'b010011; + 12'd1598 : mem_out_dec = 6'b010100; + 12'd1599 : mem_out_dec = 6'b010100; + 12'd1600 : mem_out_dec = 6'b111111; + 12'd1601 : mem_out_dec = 6'b111111; + 12'd1602 : mem_out_dec = 6'b111111; + 12'd1603 : mem_out_dec = 6'b111111; + 12'd1604 : mem_out_dec = 6'b111111; + 12'd1605 : mem_out_dec = 6'b111111; + 12'd1606 : mem_out_dec = 6'b111111; + 12'd1607 : mem_out_dec = 6'b111111; + 12'd1608 : mem_out_dec = 6'b111111; + 12'd1609 : mem_out_dec = 6'b111111; + 12'd1610 : mem_out_dec = 6'b111111; + 12'd1611 : mem_out_dec = 6'b111111; + 12'd1612 : mem_out_dec = 6'b111111; + 12'd1613 : mem_out_dec = 6'b111111; + 12'd1614 : mem_out_dec = 6'b111111; + 12'd1615 : mem_out_dec = 6'b111111; + 12'd1616 : mem_out_dec = 6'b111111; + 12'd1617 : mem_out_dec = 6'b111111; + 12'd1618 : mem_out_dec = 6'b111111; + 12'd1619 : mem_out_dec = 6'b111111; + 12'd1620 : mem_out_dec = 6'b111111; + 12'd1621 : mem_out_dec = 6'b111111; + 12'd1622 : mem_out_dec = 6'b111111; + 12'd1623 : mem_out_dec = 6'b111111; + 12'd1624 : mem_out_dec = 6'b111111; + 12'd1625 : mem_out_dec = 6'b111111; + 12'd1626 : mem_out_dec = 6'b111111; + 12'd1627 : mem_out_dec = 6'b111111; + 12'd1628 : mem_out_dec = 6'b111111; + 12'd1629 : mem_out_dec = 6'b111111; + 12'd1630 : mem_out_dec = 6'b111111; + 12'd1631 : mem_out_dec = 6'b000100; + 12'd1632 : mem_out_dec = 6'b000011; + 12'd1633 : mem_out_dec = 6'b000011; + 12'd1634 : mem_out_dec = 6'b000100; + 12'd1635 : mem_out_dec = 6'b000100; + 12'd1636 : mem_out_dec = 6'b000101; + 12'd1637 : mem_out_dec = 6'b000110; + 12'd1638 : mem_out_dec = 6'b000110; + 12'd1639 : mem_out_dec = 6'b000111; + 12'd1640 : mem_out_dec = 6'b000111; + 12'd1641 : mem_out_dec = 6'b001000; + 12'd1642 : mem_out_dec = 6'b001001; + 12'd1643 : mem_out_dec = 6'b001001; + 12'd1644 : mem_out_dec = 6'b001010; + 12'd1645 : mem_out_dec = 6'b001011; + 12'd1646 : mem_out_dec = 6'b001100; + 12'd1647 : mem_out_dec = 6'b001101; + 12'd1648 : mem_out_dec = 6'b001101; + 12'd1649 : mem_out_dec = 6'b001101; + 12'd1650 : mem_out_dec = 6'b001110; + 12'd1651 : mem_out_dec = 6'b001110; + 12'd1652 : mem_out_dec = 6'b001110; + 12'd1653 : mem_out_dec = 6'b001111; + 12'd1654 : mem_out_dec = 6'b010000; + 12'd1655 : mem_out_dec = 6'b010000; + 12'd1656 : mem_out_dec = 6'b010001; + 12'd1657 : mem_out_dec = 6'b010001; + 12'd1658 : mem_out_dec = 6'b010001; + 12'd1659 : mem_out_dec = 6'b010010; + 12'd1660 : mem_out_dec = 6'b010010; + 12'd1661 : mem_out_dec = 6'b010011; + 12'd1662 : mem_out_dec = 6'b010011; + 12'd1663 : mem_out_dec = 6'b010100; + 12'd1664 : mem_out_dec = 6'b111111; + 12'd1665 : mem_out_dec = 6'b111111; + 12'd1666 : mem_out_dec = 6'b111111; + 12'd1667 : mem_out_dec = 6'b111111; + 12'd1668 : mem_out_dec = 6'b111111; + 12'd1669 : mem_out_dec = 6'b111111; + 12'd1670 : mem_out_dec = 6'b111111; + 12'd1671 : mem_out_dec = 6'b111111; + 12'd1672 : mem_out_dec = 6'b111111; + 12'd1673 : mem_out_dec = 6'b111111; + 12'd1674 : mem_out_dec = 6'b111111; + 12'd1675 : mem_out_dec = 6'b111111; + 12'd1676 : mem_out_dec = 6'b111111; + 12'd1677 : mem_out_dec = 6'b111111; + 12'd1678 : mem_out_dec = 6'b111111; + 12'd1679 : mem_out_dec = 6'b111111; + 12'd1680 : mem_out_dec = 6'b111111; + 12'd1681 : mem_out_dec = 6'b111111; + 12'd1682 : mem_out_dec = 6'b111111; + 12'd1683 : mem_out_dec = 6'b111111; + 12'd1684 : mem_out_dec = 6'b111111; + 12'd1685 : mem_out_dec = 6'b111111; + 12'd1686 : mem_out_dec = 6'b111111; + 12'd1687 : mem_out_dec = 6'b111111; + 12'd1688 : mem_out_dec = 6'b111111; + 12'd1689 : mem_out_dec = 6'b111111; + 12'd1690 : mem_out_dec = 6'b111111; + 12'd1691 : mem_out_dec = 6'b111111; + 12'd1692 : mem_out_dec = 6'b111111; + 12'd1693 : mem_out_dec = 6'b111111; + 12'd1694 : mem_out_dec = 6'b111111; + 12'd1695 : mem_out_dec = 6'b111111; + 12'd1696 : mem_out_dec = 6'b000011; + 12'd1697 : mem_out_dec = 6'b000011; + 12'd1698 : mem_out_dec = 6'b000100; + 12'd1699 : mem_out_dec = 6'b000100; + 12'd1700 : mem_out_dec = 6'b000101; + 12'd1701 : mem_out_dec = 6'b000101; + 12'd1702 : mem_out_dec = 6'b000110; + 12'd1703 : mem_out_dec = 6'b000111; + 12'd1704 : mem_out_dec = 6'b000111; + 12'd1705 : mem_out_dec = 6'b001000; + 12'd1706 : mem_out_dec = 6'b001000; + 12'd1707 : mem_out_dec = 6'b001001; + 12'd1708 : mem_out_dec = 6'b001010; + 12'd1709 : mem_out_dec = 6'b001011; + 12'd1710 : mem_out_dec = 6'b001100; + 12'd1711 : mem_out_dec = 6'b001100; + 12'd1712 : mem_out_dec = 6'b001100; + 12'd1713 : mem_out_dec = 6'b001101; + 12'd1714 : mem_out_dec = 6'b001101; + 12'd1715 : mem_out_dec = 6'b001110; + 12'd1716 : mem_out_dec = 6'b001110; + 12'd1717 : mem_out_dec = 6'b001111; + 12'd1718 : mem_out_dec = 6'b001111; + 12'd1719 : mem_out_dec = 6'b010000; + 12'd1720 : mem_out_dec = 6'b010000; + 12'd1721 : mem_out_dec = 6'b010000; + 12'd1722 : mem_out_dec = 6'b010001; + 12'd1723 : mem_out_dec = 6'b010001; + 12'd1724 : mem_out_dec = 6'b010010; + 12'd1725 : mem_out_dec = 6'b010010; + 12'd1726 : mem_out_dec = 6'b010011; + 12'd1727 : mem_out_dec = 6'b010011; + 12'd1728 : mem_out_dec = 6'b111111; + 12'd1729 : mem_out_dec = 6'b111111; + 12'd1730 : mem_out_dec = 6'b111111; + 12'd1731 : mem_out_dec = 6'b111111; + 12'd1732 : mem_out_dec = 6'b111111; + 12'd1733 : mem_out_dec = 6'b111111; + 12'd1734 : mem_out_dec = 6'b111111; + 12'd1735 : mem_out_dec = 6'b111111; + 12'd1736 : mem_out_dec = 6'b111111; + 12'd1737 : mem_out_dec = 6'b111111; + 12'd1738 : mem_out_dec = 6'b111111; + 12'd1739 : mem_out_dec = 6'b111111; + 12'd1740 : mem_out_dec = 6'b111111; + 12'd1741 : mem_out_dec = 6'b111111; + 12'd1742 : mem_out_dec = 6'b111111; + 12'd1743 : mem_out_dec = 6'b111111; + 12'd1744 : mem_out_dec = 6'b111111; + 12'd1745 : mem_out_dec = 6'b111111; + 12'd1746 : mem_out_dec = 6'b111111; + 12'd1747 : mem_out_dec = 6'b111111; + 12'd1748 : mem_out_dec = 6'b111111; + 12'd1749 : mem_out_dec = 6'b111111; + 12'd1750 : mem_out_dec = 6'b111111; + 12'd1751 : mem_out_dec = 6'b111111; + 12'd1752 : mem_out_dec = 6'b111111; + 12'd1753 : mem_out_dec = 6'b111111; + 12'd1754 : mem_out_dec = 6'b111111; + 12'd1755 : mem_out_dec = 6'b111111; + 12'd1756 : mem_out_dec = 6'b111111; + 12'd1757 : mem_out_dec = 6'b111111; + 12'd1758 : mem_out_dec = 6'b111111; + 12'd1759 : mem_out_dec = 6'b111111; + 12'd1760 : mem_out_dec = 6'b111111; + 12'd1761 : mem_out_dec = 6'b000011; + 12'd1762 : mem_out_dec = 6'b000011; + 12'd1763 : mem_out_dec = 6'b000100; + 12'd1764 : mem_out_dec = 6'b000101; + 12'd1765 : mem_out_dec = 6'b000101; + 12'd1766 : mem_out_dec = 6'b000110; + 12'd1767 : mem_out_dec = 6'b000111; + 12'd1768 : mem_out_dec = 6'b000111; + 12'd1769 : mem_out_dec = 6'b000111; + 12'd1770 : mem_out_dec = 6'b001000; + 12'd1771 : mem_out_dec = 6'b001001; + 12'd1772 : mem_out_dec = 6'b001010; + 12'd1773 : mem_out_dec = 6'b001011; + 12'd1774 : mem_out_dec = 6'b001011; + 12'd1775 : mem_out_dec = 6'b001100; + 12'd1776 : mem_out_dec = 6'b001100; + 12'd1777 : mem_out_dec = 6'b001101; + 12'd1778 : mem_out_dec = 6'b001101; + 12'd1779 : mem_out_dec = 6'b001101; + 12'd1780 : mem_out_dec = 6'b001110; + 12'd1781 : mem_out_dec = 6'b001111; + 12'd1782 : mem_out_dec = 6'b001111; + 12'd1783 : mem_out_dec = 6'b010000; + 12'd1784 : mem_out_dec = 6'b010000; + 12'd1785 : mem_out_dec = 6'b010000; + 12'd1786 : mem_out_dec = 6'b010000; + 12'd1787 : mem_out_dec = 6'b010001; + 12'd1788 : mem_out_dec = 6'b010001; + 12'd1789 : mem_out_dec = 6'b010010; + 12'd1790 : mem_out_dec = 6'b010010; + 12'd1791 : mem_out_dec = 6'b010011; + 12'd1792 : mem_out_dec = 6'b111111; + 12'd1793 : mem_out_dec = 6'b111111; + 12'd1794 : mem_out_dec = 6'b111111; + 12'd1795 : mem_out_dec = 6'b111111; + 12'd1796 : mem_out_dec = 6'b111111; + 12'd1797 : mem_out_dec = 6'b111111; + 12'd1798 : mem_out_dec = 6'b111111; + 12'd1799 : mem_out_dec = 6'b111111; + 12'd1800 : mem_out_dec = 6'b111111; + 12'd1801 : mem_out_dec = 6'b111111; + 12'd1802 : mem_out_dec = 6'b111111; + 12'd1803 : mem_out_dec = 6'b111111; + 12'd1804 : mem_out_dec = 6'b111111; + 12'd1805 : mem_out_dec = 6'b111111; + 12'd1806 : mem_out_dec = 6'b111111; + 12'd1807 : mem_out_dec = 6'b111111; + 12'd1808 : mem_out_dec = 6'b111111; + 12'd1809 : mem_out_dec = 6'b111111; + 12'd1810 : mem_out_dec = 6'b111111; + 12'd1811 : mem_out_dec = 6'b111111; + 12'd1812 : mem_out_dec = 6'b111111; + 12'd1813 : mem_out_dec = 6'b111111; + 12'd1814 : mem_out_dec = 6'b111111; + 12'd1815 : mem_out_dec = 6'b111111; + 12'd1816 : mem_out_dec = 6'b111111; + 12'd1817 : mem_out_dec = 6'b111111; + 12'd1818 : mem_out_dec = 6'b111111; + 12'd1819 : mem_out_dec = 6'b111111; + 12'd1820 : mem_out_dec = 6'b111111; + 12'd1821 : mem_out_dec = 6'b111111; + 12'd1822 : mem_out_dec = 6'b111111; + 12'd1823 : mem_out_dec = 6'b111111; + 12'd1824 : mem_out_dec = 6'b111111; + 12'd1825 : mem_out_dec = 6'b111111; + 12'd1826 : mem_out_dec = 6'b000011; + 12'd1827 : mem_out_dec = 6'b000100; + 12'd1828 : mem_out_dec = 6'b000100; + 12'd1829 : mem_out_dec = 6'b000101; + 12'd1830 : mem_out_dec = 6'b000110; + 12'd1831 : mem_out_dec = 6'b000110; + 12'd1832 : mem_out_dec = 6'b000110; + 12'd1833 : mem_out_dec = 6'b000111; + 12'd1834 : mem_out_dec = 6'b001000; + 12'd1835 : mem_out_dec = 6'b001001; + 12'd1836 : mem_out_dec = 6'b001010; + 12'd1837 : mem_out_dec = 6'b001010; + 12'd1838 : mem_out_dec = 6'b001011; + 12'd1839 : mem_out_dec = 6'b001100; + 12'd1840 : mem_out_dec = 6'b001100; + 12'd1841 : mem_out_dec = 6'b001100; + 12'd1842 : mem_out_dec = 6'b001101; + 12'd1843 : mem_out_dec = 6'b001101; + 12'd1844 : mem_out_dec = 6'b001110; + 12'd1845 : mem_out_dec = 6'b001110; + 12'd1846 : mem_out_dec = 6'b001111; + 12'd1847 : mem_out_dec = 6'b010000; + 12'd1848 : mem_out_dec = 6'b001111; + 12'd1849 : mem_out_dec = 6'b001111; + 12'd1850 : mem_out_dec = 6'b010000; + 12'd1851 : mem_out_dec = 6'b010000; + 12'd1852 : mem_out_dec = 6'b010001; + 12'd1853 : mem_out_dec = 6'b010001; + 12'd1854 : mem_out_dec = 6'b010010; + 12'd1855 : mem_out_dec = 6'b010010; + 12'd1856 : mem_out_dec = 6'b111111; + 12'd1857 : mem_out_dec = 6'b111111; + 12'd1858 : mem_out_dec = 6'b111111; + 12'd1859 : mem_out_dec = 6'b111111; + 12'd1860 : mem_out_dec = 6'b111111; + 12'd1861 : mem_out_dec = 6'b111111; + 12'd1862 : mem_out_dec = 6'b111111; + 12'd1863 : mem_out_dec = 6'b111111; + 12'd1864 : mem_out_dec = 6'b111111; + 12'd1865 : mem_out_dec = 6'b111111; + 12'd1866 : mem_out_dec = 6'b111111; + 12'd1867 : mem_out_dec = 6'b111111; + 12'd1868 : mem_out_dec = 6'b111111; + 12'd1869 : mem_out_dec = 6'b111111; + 12'd1870 : mem_out_dec = 6'b111111; + 12'd1871 : mem_out_dec = 6'b111111; + 12'd1872 : mem_out_dec = 6'b111111; + 12'd1873 : mem_out_dec = 6'b111111; + 12'd1874 : mem_out_dec = 6'b111111; + 12'd1875 : mem_out_dec = 6'b111111; + 12'd1876 : mem_out_dec = 6'b111111; + 12'd1877 : mem_out_dec = 6'b111111; + 12'd1878 : mem_out_dec = 6'b111111; + 12'd1879 : mem_out_dec = 6'b111111; + 12'd1880 : mem_out_dec = 6'b111111; + 12'd1881 : mem_out_dec = 6'b111111; + 12'd1882 : mem_out_dec = 6'b111111; + 12'd1883 : mem_out_dec = 6'b111111; + 12'd1884 : mem_out_dec = 6'b111111; + 12'd1885 : mem_out_dec = 6'b111111; + 12'd1886 : mem_out_dec = 6'b111111; + 12'd1887 : mem_out_dec = 6'b111111; + 12'd1888 : mem_out_dec = 6'b111111; + 12'd1889 : mem_out_dec = 6'b111111; + 12'd1890 : mem_out_dec = 6'b111111; + 12'd1891 : mem_out_dec = 6'b000100; + 12'd1892 : mem_out_dec = 6'b000100; + 12'd1893 : mem_out_dec = 6'b000101; + 12'd1894 : mem_out_dec = 6'b000101; + 12'd1895 : mem_out_dec = 6'b000110; + 12'd1896 : mem_out_dec = 6'b000110; + 12'd1897 : mem_out_dec = 6'b000111; + 12'd1898 : mem_out_dec = 6'b001000; + 12'd1899 : mem_out_dec = 6'b001001; + 12'd1900 : mem_out_dec = 6'b001001; + 12'd1901 : mem_out_dec = 6'b001010; + 12'd1902 : mem_out_dec = 6'b001011; + 12'd1903 : mem_out_dec = 6'b001100; + 12'd1904 : mem_out_dec = 6'b001100; + 12'd1905 : mem_out_dec = 6'b001100; + 12'd1906 : mem_out_dec = 6'b001100; + 12'd1907 : mem_out_dec = 6'b001101; + 12'd1908 : mem_out_dec = 6'b001110; + 12'd1909 : mem_out_dec = 6'b001110; + 12'd1910 : mem_out_dec = 6'b001111; + 12'd1911 : mem_out_dec = 6'b001111; + 12'd1912 : mem_out_dec = 6'b001111; + 12'd1913 : mem_out_dec = 6'b001111; + 12'd1914 : mem_out_dec = 6'b001111; + 12'd1915 : mem_out_dec = 6'b010000; + 12'd1916 : mem_out_dec = 6'b010000; + 12'd1917 : mem_out_dec = 6'b010001; + 12'd1918 : mem_out_dec = 6'b010001; + 12'd1919 : mem_out_dec = 6'b010010; + 12'd1920 : mem_out_dec = 6'b111111; + 12'd1921 : mem_out_dec = 6'b111111; + 12'd1922 : mem_out_dec = 6'b111111; + 12'd1923 : mem_out_dec = 6'b111111; + 12'd1924 : mem_out_dec = 6'b111111; + 12'd1925 : mem_out_dec = 6'b111111; + 12'd1926 : mem_out_dec = 6'b111111; + 12'd1927 : mem_out_dec = 6'b111111; + 12'd1928 : mem_out_dec = 6'b111111; + 12'd1929 : mem_out_dec = 6'b111111; + 12'd1930 : mem_out_dec = 6'b111111; + 12'd1931 : mem_out_dec = 6'b111111; + 12'd1932 : mem_out_dec = 6'b111111; + 12'd1933 : mem_out_dec = 6'b111111; + 12'd1934 : mem_out_dec = 6'b111111; + 12'd1935 : mem_out_dec = 6'b111111; + 12'd1936 : mem_out_dec = 6'b111111; + 12'd1937 : mem_out_dec = 6'b111111; + 12'd1938 : mem_out_dec = 6'b111111; + 12'd1939 : mem_out_dec = 6'b111111; + 12'd1940 : mem_out_dec = 6'b111111; + 12'd1941 : mem_out_dec = 6'b111111; + 12'd1942 : mem_out_dec = 6'b111111; + 12'd1943 : mem_out_dec = 6'b111111; + 12'd1944 : mem_out_dec = 6'b111111; + 12'd1945 : mem_out_dec = 6'b111111; + 12'd1946 : mem_out_dec = 6'b111111; + 12'd1947 : mem_out_dec = 6'b111111; + 12'd1948 : mem_out_dec = 6'b111111; + 12'd1949 : mem_out_dec = 6'b111111; + 12'd1950 : mem_out_dec = 6'b111111; + 12'd1951 : mem_out_dec = 6'b111111; + 12'd1952 : mem_out_dec = 6'b111111; + 12'd1953 : mem_out_dec = 6'b111111; + 12'd1954 : mem_out_dec = 6'b111111; + 12'd1955 : mem_out_dec = 6'b111111; + 12'd1956 : mem_out_dec = 6'b000100; + 12'd1957 : mem_out_dec = 6'b000101; + 12'd1958 : mem_out_dec = 6'b000101; + 12'd1959 : mem_out_dec = 6'b000110; + 12'd1960 : mem_out_dec = 6'b000110; + 12'd1961 : mem_out_dec = 6'b000111; + 12'd1962 : mem_out_dec = 6'b001000; + 12'd1963 : mem_out_dec = 6'b001000; + 12'd1964 : mem_out_dec = 6'b001001; + 12'd1965 : mem_out_dec = 6'b001010; + 12'd1966 : mem_out_dec = 6'b001011; + 12'd1967 : mem_out_dec = 6'b001011; + 12'd1968 : mem_out_dec = 6'b001011; + 12'd1969 : mem_out_dec = 6'b001100; + 12'd1970 : mem_out_dec = 6'b001100; + 12'd1971 : mem_out_dec = 6'b001101; + 12'd1972 : mem_out_dec = 6'b001101; + 12'd1973 : mem_out_dec = 6'b001110; + 12'd1974 : mem_out_dec = 6'b001111; + 12'd1975 : mem_out_dec = 6'b001111; + 12'd1976 : mem_out_dec = 6'b001110; + 12'd1977 : mem_out_dec = 6'b001110; + 12'd1978 : mem_out_dec = 6'b001111; + 12'd1979 : mem_out_dec = 6'b001111; + 12'd1980 : mem_out_dec = 6'b010000; + 12'd1981 : mem_out_dec = 6'b010000; + 12'd1982 : mem_out_dec = 6'b010001; + 12'd1983 : mem_out_dec = 6'b010001; + 12'd1984 : mem_out_dec = 6'b111111; + 12'd1985 : mem_out_dec = 6'b111111; + 12'd1986 : mem_out_dec = 6'b111111; + 12'd1987 : mem_out_dec = 6'b111111; + 12'd1988 : mem_out_dec = 6'b111111; + 12'd1989 : mem_out_dec = 6'b111111; + 12'd1990 : mem_out_dec = 6'b111111; + 12'd1991 : mem_out_dec = 6'b111111; + 12'd1992 : mem_out_dec = 6'b111111; + 12'd1993 : mem_out_dec = 6'b111111; + 12'd1994 : mem_out_dec = 6'b111111; + 12'd1995 : mem_out_dec = 6'b111111; + 12'd1996 : mem_out_dec = 6'b111111; + 12'd1997 : mem_out_dec = 6'b111111; + 12'd1998 : mem_out_dec = 6'b111111; + 12'd1999 : mem_out_dec = 6'b111111; + 12'd2000 : mem_out_dec = 6'b111111; + 12'd2001 : mem_out_dec = 6'b111111; + 12'd2002 : mem_out_dec = 6'b111111; + 12'd2003 : mem_out_dec = 6'b111111; + 12'd2004 : mem_out_dec = 6'b111111; + 12'd2005 : mem_out_dec = 6'b111111; + 12'd2006 : mem_out_dec = 6'b111111; + 12'd2007 : mem_out_dec = 6'b111111; + 12'd2008 : mem_out_dec = 6'b111111; + 12'd2009 : mem_out_dec = 6'b111111; + 12'd2010 : mem_out_dec = 6'b111111; + 12'd2011 : mem_out_dec = 6'b111111; + 12'd2012 : mem_out_dec = 6'b111111; + 12'd2013 : mem_out_dec = 6'b111111; + 12'd2014 : mem_out_dec = 6'b111111; + 12'd2015 : mem_out_dec = 6'b111111; + 12'd2016 : mem_out_dec = 6'b111111; + 12'd2017 : mem_out_dec = 6'b111111; + 12'd2018 : mem_out_dec = 6'b111111; + 12'd2019 : mem_out_dec = 6'b111111; + 12'd2020 : mem_out_dec = 6'b111111; + 12'd2021 : mem_out_dec = 6'b000100; + 12'd2022 : mem_out_dec = 6'b000101; + 12'd2023 : mem_out_dec = 6'b000110; + 12'd2024 : mem_out_dec = 6'b000110; + 12'd2025 : mem_out_dec = 6'b000111; + 12'd2026 : mem_out_dec = 6'b000111; + 12'd2027 : mem_out_dec = 6'b001000; + 12'd2028 : mem_out_dec = 6'b001001; + 12'd2029 : mem_out_dec = 6'b001010; + 12'd2030 : mem_out_dec = 6'b001010; + 12'd2031 : mem_out_dec = 6'b001011; + 12'd2032 : mem_out_dec = 6'b001011; + 12'd2033 : mem_out_dec = 6'b001011; + 12'd2034 : mem_out_dec = 6'b001100; + 12'd2035 : mem_out_dec = 6'b001101; + 12'd2036 : mem_out_dec = 6'b001101; + 12'd2037 : mem_out_dec = 6'b001110; + 12'd2038 : mem_out_dec = 6'b001110; + 12'd2039 : mem_out_dec = 6'b001110; + 12'd2040 : mem_out_dec = 6'b001101; + 12'd2041 : mem_out_dec = 6'b001110; + 12'd2042 : mem_out_dec = 6'b001110; + 12'd2043 : mem_out_dec = 6'b001111; + 12'd2044 : mem_out_dec = 6'b001111; + 12'd2045 : mem_out_dec = 6'b010000; + 12'd2046 : mem_out_dec = 6'b010000; + 12'd2047 : mem_out_dec = 6'b010001; + 12'd2048 : mem_out_dec = 6'b111111; + 12'd2049 : mem_out_dec = 6'b111111; + 12'd2050 : mem_out_dec = 6'b111111; + 12'd2051 : mem_out_dec = 6'b111111; + 12'd2052 : mem_out_dec = 6'b111111; + 12'd2053 : mem_out_dec = 6'b111111; + 12'd2054 : mem_out_dec = 6'b111111; + 12'd2055 : mem_out_dec = 6'b111111; + 12'd2056 : mem_out_dec = 6'b111111; + 12'd2057 : mem_out_dec = 6'b111111; + 12'd2058 : mem_out_dec = 6'b111111; + 12'd2059 : mem_out_dec = 6'b111111; + 12'd2060 : mem_out_dec = 6'b111111; + 12'd2061 : mem_out_dec = 6'b111111; + 12'd2062 : mem_out_dec = 6'b111111; + 12'd2063 : mem_out_dec = 6'b111111; + 12'd2064 : mem_out_dec = 6'b111111; + 12'd2065 : mem_out_dec = 6'b111111; + 12'd2066 : mem_out_dec = 6'b111111; + 12'd2067 : mem_out_dec = 6'b111111; + 12'd2068 : mem_out_dec = 6'b111111; + 12'd2069 : mem_out_dec = 6'b111111; + 12'd2070 : mem_out_dec = 6'b111111; + 12'd2071 : mem_out_dec = 6'b111111; + 12'd2072 : mem_out_dec = 6'b111111; + 12'd2073 : mem_out_dec = 6'b111111; + 12'd2074 : mem_out_dec = 6'b111111; + 12'd2075 : mem_out_dec = 6'b111111; + 12'd2076 : mem_out_dec = 6'b111111; + 12'd2077 : mem_out_dec = 6'b111111; + 12'd2078 : mem_out_dec = 6'b111111; + 12'd2079 : mem_out_dec = 6'b111111; + 12'd2080 : mem_out_dec = 6'b111111; + 12'd2081 : mem_out_dec = 6'b111111; + 12'd2082 : mem_out_dec = 6'b111111; + 12'd2083 : mem_out_dec = 6'b111111; + 12'd2084 : mem_out_dec = 6'b111111; + 12'd2085 : mem_out_dec = 6'b111111; + 12'd2086 : mem_out_dec = 6'b000100; + 12'd2087 : mem_out_dec = 6'b000101; + 12'd2088 : mem_out_dec = 6'b000101; + 12'd2089 : mem_out_dec = 6'b000110; + 12'd2090 : mem_out_dec = 6'b000110; + 12'd2091 : mem_out_dec = 6'b000111; + 12'd2092 : mem_out_dec = 6'b001000; + 12'd2093 : mem_out_dec = 6'b001001; + 12'd2094 : mem_out_dec = 6'b001001; + 12'd2095 : mem_out_dec = 6'b001010; + 12'd2096 : mem_out_dec = 6'b001010; + 12'd2097 : mem_out_dec = 6'b001011; + 12'd2098 : mem_out_dec = 6'b001011; + 12'd2099 : mem_out_dec = 6'b001100; + 12'd2100 : mem_out_dec = 6'b001100; + 12'd2101 : mem_out_dec = 6'b001100; + 12'd2102 : mem_out_dec = 6'b001100; + 12'd2103 : mem_out_dec = 6'b001101; + 12'd2104 : mem_out_dec = 6'b001100; + 12'd2105 : mem_out_dec = 6'b001100; + 12'd2106 : mem_out_dec = 6'b001101; + 12'd2107 : mem_out_dec = 6'b001101; + 12'd2108 : mem_out_dec = 6'b001110; + 12'd2109 : mem_out_dec = 6'b001111; + 12'd2110 : mem_out_dec = 6'b010000; + 12'd2111 : mem_out_dec = 6'b010000; + 12'd2112 : mem_out_dec = 6'b111111; + 12'd2113 : mem_out_dec = 6'b111111; + 12'd2114 : mem_out_dec = 6'b111111; + 12'd2115 : mem_out_dec = 6'b111111; + 12'd2116 : mem_out_dec = 6'b111111; + 12'd2117 : mem_out_dec = 6'b111111; + 12'd2118 : mem_out_dec = 6'b111111; + 12'd2119 : mem_out_dec = 6'b111111; + 12'd2120 : mem_out_dec = 6'b111111; + 12'd2121 : mem_out_dec = 6'b111111; + 12'd2122 : mem_out_dec = 6'b111111; + 12'd2123 : mem_out_dec = 6'b111111; + 12'd2124 : mem_out_dec = 6'b111111; + 12'd2125 : mem_out_dec = 6'b111111; + 12'd2126 : mem_out_dec = 6'b111111; + 12'd2127 : mem_out_dec = 6'b111111; + 12'd2128 : mem_out_dec = 6'b111111; + 12'd2129 : mem_out_dec = 6'b111111; + 12'd2130 : mem_out_dec = 6'b111111; + 12'd2131 : mem_out_dec = 6'b111111; + 12'd2132 : mem_out_dec = 6'b111111; + 12'd2133 : mem_out_dec = 6'b111111; + 12'd2134 : mem_out_dec = 6'b111111; + 12'd2135 : mem_out_dec = 6'b111111; + 12'd2136 : mem_out_dec = 6'b111111; + 12'd2137 : mem_out_dec = 6'b111111; + 12'd2138 : mem_out_dec = 6'b111111; + 12'd2139 : mem_out_dec = 6'b111111; + 12'd2140 : mem_out_dec = 6'b111111; + 12'd2141 : mem_out_dec = 6'b111111; + 12'd2142 : mem_out_dec = 6'b111111; + 12'd2143 : mem_out_dec = 6'b111111; + 12'd2144 : mem_out_dec = 6'b111111; + 12'd2145 : mem_out_dec = 6'b111111; + 12'd2146 : mem_out_dec = 6'b111111; + 12'd2147 : mem_out_dec = 6'b111111; + 12'd2148 : mem_out_dec = 6'b111111; + 12'd2149 : mem_out_dec = 6'b111111; + 12'd2150 : mem_out_dec = 6'b111111; + 12'd2151 : mem_out_dec = 6'b000100; + 12'd2152 : mem_out_dec = 6'b000100; + 12'd2153 : mem_out_dec = 6'b000101; + 12'd2154 : mem_out_dec = 6'b000110; + 12'd2155 : mem_out_dec = 6'b000111; + 12'd2156 : mem_out_dec = 6'b000111; + 12'd2157 : mem_out_dec = 6'b001000; + 12'd2158 : mem_out_dec = 6'b001001; + 12'd2159 : mem_out_dec = 6'b001001; + 12'd2160 : mem_out_dec = 6'b001010; + 12'd2161 : mem_out_dec = 6'b001010; + 12'd2162 : mem_out_dec = 6'b001011; + 12'd2163 : mem_out_dec = 6'b001011; + 12'd2164 : mem_out_dec = 6'b001011; + 12'd2165 : mem_out_dec = 6'b001011; + 12'd2166 : mem_out_dec = 6'b001011; + 12'd2167 : mem_out_dec = 6'b001100; + 12'd2168 : mem_out_dec = 6'b001011; + 12'd2169 : mem_out_dec = 6'b001011; + 12'd2170 : mem_out_dec = 6'b001100; + 12'd2171 : mem_out_dec = 6'b001101; + 12'd2172 : mem_out_dec = 6'b001110; + 12'd2173 : mem_out_dec = 6'b001110; + 12'd2174 : mem_out_dec = 6'b001111; + 12'd2175 : mem_out_dec = 6'b010000; + 12'd2176 : mem_out_dec = 6'b111111; + 12'd2177 : mem_out_dec = 6'b111111; + 12'd2178 : mem_out_dec = 6'b111111; + 12'd2179 : mem_out_dec = 6'b111111; + 12'd2180 : mem_out_dec = 6'b111111; + 12'd2181 : mem_out_dec = 6'b111111; + 12'd2182 : mem_out_dec = 6'b111111; + 12'd2183 : mem_out_dec = 6'b111111; + 12'd2184 : mem_out_dec = 6'b111111; + 12'd2185 : mem_out_dec = 6'b111111; + 12'd2186 : mem_out_dec = 6'b111111; + 12'd2187 : mem_out_dec = 6'b111111; + 12'd2188 : mem_out_dec = 6'b111111; + 12'd2189 : mem_out_dec = 6'b111111; + 12'd2190 : mem_out_dec = 6'b111111; + 12'd2191 : mem_out_dec = 6'b111111; + 12'd2192 : mem_out_dec = 6'b111111; + 12'd2193 : mem_out_dec = 6'b111111; + 12'd2194 : mem_out_dec = 6'b111111; + 12'd2195 : mem_out_dec = 6'b111111; + 12'd2196 : mem_out_dec = 6'b111111; + 12'd2197 : mem_out_dec = 6'b111111; + 12'd2198 : mem_out_dec = 6'b111111; + 12'd2199 : mem_out_dec = 6'b111111; + 12'd2200 : mem_out_dec = 6'b111111; + 12'd2201 : mem_out_dec = 6'b111111; + 12'd2202 : mem_out_dec = 6'b111111; + 12'd2203 : mem_out_dec = 6'b111111; + 12'd2204 : mem_out_dec = 6'b111111; + 12'd2205 : mem_out_dec = 6'b111111; + 12'd2206 : mem_out_dec = 6'b111111; + 12'd2207 : mem_out_dec = 6'b111111; + 12'd2208 : mem_out_dec = 6'b111111; + 12'd2209 : mem_out_dec = 6'b111111; + 12'd2210 : mem_out_dec = 6'b111111; + 12'd2211 : mem_out_dec = 6'b111111; + 12'd2212 : mem_out_dec = 6'b111111; + 12'd2213 : mem_out_dec = 6'b111111; + 12'd2214 : mem_out_dec = 6'b111111; + 12'd2215 : mem_out_dec = 6'b111111; + 12'd2216 : mem_out_dec = 6'b000100; + 12'd2217 : mem_out_dec = 6'b000101; + 12'd2218 : mem_out_dec = 6'b000101; + 12'd2219 : mem_out_dec = 6'b000110; + 12'd2220 : mem_out_dec = 6'b000111; + 12'd2221 : mem_out_dec = 6'b000111; + 12'd2222 : mem_out_dec = 6'b001000; + 12'd2223 : mem_out_dec = 6'b001001; + 12'd2224 : mem_out_dec = 6'b001001; + 12'd2225 : mem_out_dec = 6'b001010; + 12'd2226 : mem_out_dec = 6'b001010; + 12'd2227 : mem_out_dec = 6'b001010; + 12'd2228 : mem_out_dec = 6'b001010; + 12'd2229 : mem_out_dec = 6'b001010; + 12'd2230 : mem_out_dec = 6'b001010; + 12'd2231 : mem_out_dec = 6'b001010; + 12'd2232 : mem_out_dec = 6'b001010; + 12'd2233 : mem_out_dec = 6'b001011; + 12'd2234 : mem_out_dec = 6'b001100; + 12'd2235 : mem_out_dec = 6'b001100; + 12'd2236 : mem_out_dec = 6'b001101; + 12'd2237 : mem_out_dec = 6'b001110; + 12'd2238 : mem_out_dec = 6'b001111; + 12'd2239 : mem_out_dec = 6'b010000; + 12'd2240 : mem_out_dec = 6'b111111; + 12'd2241 : mem_out_dec = 6'b111111; + 12'd2242 : mem_out_dec = 6'b111111; + 12'd2243 : mem_out_dec = 6'b111111; + 12'd2244 : mem_out_dec = 6'b111111; + 12'd2245 : mem_out_dec = 6'b111111; + 12'd2246 : mem_out_dec = 6'b111111; + 12'd2247 : mem_out_dec = 6'b111111; + 12'd2248 : mem_out_dec = 6'b111111; + 12'd2249 : mem_out_dec = 6'b111111; + 12'd2250 : mem_out_dec = 6'b111111; + 12'd2251 : mem_out_dec = 6'b111111; + 12'd2252 : mem_out_dec = 6'b111111; + 12'd2253 : mem_out_dec = 6'b111111; + 12'd2254 : mem_out_dec = 6'b111111; + 12'd2255 : mem_out_dec = 6'b111111; + 12'd2256 : mem_out_dec = 6'b111111; + 12'd2257 : mem_out_dec = 6'b111111; + 12'd2258 : mem_out_dec = 6'b111111; + 12'd2259 : mem_out_dec = 6'b111111; + 12'd2260 : mem_out_dec = 6'b111111; + 12'd2261 : mem_out_dec = 6'b111111; + 12'd2262 : mem_out_dec = 6'b111111; + 12'd2263 : mem_out_dec = 6'b111111; + 12'd2264 : mem_out_dec = 6'b111111; + 12'd2265 : mem_out_dec = 6'b111111; + 12'd2266 : mem_out_dec = 6'b111111; + 12'd2267 : mem_out_dec = 6'b111111; + 12'd2268 : mem_out_dec = 6'b111111; + 12'd2269 : mem_out_dec = 6'b111111; + 12'd2270 : mem_out_dec = 6'b111111; + 12'd2271 : mem_out_dec = 6'b111111; + 12'd2272 : mem_out_dec = 6'b111111; + 12'd2273 : mem_out_dec = 6'b111111; + 12'd2274 : mem_out_dec = 6'b111111; + 12'd2275 : mem_out_dec = 6'b111111; + 12'd2276 : mem_out_dec = 6'b111111; + 12'd2277 : mem_out_dec = 6'b111111; + 12'd2278 : mem_out_dec = 6'b111111; + 12'd2279 : mem_out_dec = 6'b111111; + 12'd2280 : mem_out_dec = 6'b111111; + 12'd2281 : mem_out_dec = 6'b000100; + 12'd2282 : mem_out_dec = 6'b000101; + 12'd2283 : mem_out_dec = 6'b000101; + 12'd2284 : mem_out_dec = 6'b000110; + 12'd2285 : mem_out_dec = 6'b000111; + 12'd2286 : mem_out_dec = 6'b001000; + 12'd2287 : mem_out_dec = 6'b001001; + 12'd2288 : mem_out_dec = 6'b001001; + 12'd2289 : mem_out_dec = 6'b001001; + 12'd2290 : mem_out_dec = 6'b001001; + 12'd2291 : mem_out_dec = 6'b001001; + 12'd2292 : mem_out_dec = 6'b001001; + 12'd2293 : mem_out_dec = 6'b001001; + 12'd2294 : mem_out_dec = 6'b001001; + 12'd2295 : mem_out_dec = 6'b001001; + 12'd2296 : mem_out_dec = 6'b001010; + 12'd2297 : mem_out_dec = 6'b001010; + 12'd2298 : mem_out_dec = 6'b001011; + 12'd2299 : mem_out_dec = 6'b001100; + 12'd2300 : mem_out_dec = 6'b001101; + 12'd2301 : mem_out_dec = 6'b001110; + 12'd2302 : mem_out_dec = 6'b001110; + 12'd2303 : mem_out_dec = 6'b001111; + 12'd2304 : mem_out_dec = 6'b111111; + 12'd2305 : mem_out_dec = 6'b111111; + 12'd2306 : mem_out_dec = 6'b111111; + 12'd2307 : mem_out_dec = 6'b111111; + 12'd2308 : mem_out_dec = 6'b111111; + 12'd2309 : mem_out_dec = 6'b111111; + 12'd2310 : mem_out_dec = 6'b111111; + 12'd2311 : mem_out_dec = 6'b111111; + 12'd2312 : mem_out_dec = 6'b111111; + 12'd2313 : mem_out_dec = 6'b111111; + 12'd2314 : mem_out_dec = 6'b111111; + 12'd2315 : mem_out_dec = 6'b111111; + 12'd2316 : mem_out_dec = 6'b111111; + 12'd2317 : mem_out_dec = 6'b111111; + 12'd2318 : mem_out_dec = 6'b111111; + 12'd2319 : mem_out_dec = 6'b111111; + 12'd2320 : mem_out_dec = 6'b111111; + 12'd2321 : mem_out_dec = 6'b111111; + 12'd2322 : mem_out_dec = 6'b111111; + 12'd2323 : mem_out_dec = 6'b111111; + 12'd2324 : mem_out_dec = 6'b111111; + 12'd2325 : mem_out_dec = 6'b111111; + 12'd2326 : mem_out_dec = 6'b111111; + 12'd2327 : mem_out_dec = 6'b111111; + 12'd2328 : mem_out_dec = 6'b111111; + 12'd2329 : mem_out_dec = 6'b111111; + 12'd2330 : mem_out_dec = 6'b111111; + 12'd2331 : mem_out_dec = 6'b111111; + 12'd2332 : mem_out_dec = 6'b111111; + 12'd2333 : mem_out_dec = 6'b111111; + 12'd2334 : mem_out_dec = 6'b111111; + 12'd2335 : mem_out_dec = 6'b111111; + 12'd2336 : mem_out_dec = 6'b111111; + 12'd2337 : mem_out_dec = 6'b111111; + 12'd2338 : mem_out_dec = 6'b111111; + 12'd2339 : mem_out_dec = 6'b111111; + 12'd2340 : mem_out_dec = 6'b111111; + 12'd2341 : mem_out_dec = 6'b111111; + 12'd2342 : mem_out_dec = 6'b111111; + 12'd2343 : mem_out_dec = 6'b111111; + 12'd2344 : mem_out_dec = 6'b111111; + 12'd2345 : mem_out_dec = 6'b111111; + 12'd2346 : mem_out_dec = 6'b000100; + 12'd2347 : mem_out_dec = 6'b000101; + 12'd2348 : mem_out_dec = 6'b000110; + 12'd2349 : mem_out_dec = 6'b000111; + 12'd2350 : mem_out_dec = 6'b000111; + 12'd2351 : mem_out_dec = 6'b001000; + 12'd2352 : mem_out_dec = 6'b001000; + 12'd2353 : mem_out_dec = 6'b001000; + 12'd2354 : mem_out_dec = 6'b001000; + 12'd2355 : mem_out_dec = 6'b001000; + 12'd2356 : mem_out_dec = 6'b001000; + 12'd2357 : mem_out_dec = 6'b001000; + 12'd2358 : mem_out_dec = 6'b001000; + 12'd2359 : mem_out_dec = 6'b001001; + 12'd2360 : mem_out_dec = 6'b001001; + 12'd2361 : mem_out_dec = 6'b001010; + 12'd2362 : mem_out_dec = 6'b001011; + 12'd2363 : mem_out_dec = 6'b001100; + 12'd2364 : mem_out_dec = 6'b001100; + 12'd2365 : mem_out_dec = 6'b001101; + 12'd2366 : mem_out_dec = 6'b001110; + 12'd2367 : mem_out_dec = 6'b001111; + 12'd2368 : mem_out_dec = 6'b111111; + 12'd2369 : mem_out_dec = 6'b111111; + 12'd2370 : mem_out_dec = 6'b111111; + 12'd2371 : mem_out_dec = 6'b111111; + 12'd2372 : mem_out_dec = 6'b111111; + 12'd2373 : mem_out_dec = 6'b111111; + 12'd2374 : mem_out_dec = 6'b111111; + 12'd2375 : mem_out_dec = 6'b111111; + 12'd2376 : mem_out_dec = 6'b111111; + 12'd2377 : mem_out_dec = 6'b111111; + 12'd2378 : mem_out_dec = 6'b111111; + 12'd2379 : mem_out_dec = 6'b111111; + 12'd2380 : mem_out_dec = 6'b111111; + 12'd2381 : mem_out_dec = 6'b111111; + 12'd2382 : mem_out_dec = 6'b111111; + 12'd2383 : mem_out_dec = 6'b111111; + 12'd2384 : mem_out_dec = 6'b111111; + 12'd2385 : mem_out_dec = 6'b111111; + 12'd2386 : mem_out_dec = 6'b111111; + 12'd2387 : mem_out_dec = 6'b111111; + 12'd2388 : mem_out_dec = 6'b111111; + 12'd2389 : mem_out_dec = 6'b111111; + 12'd2390 : mem_out_dec = 6'b111111; + 12'd2391 : mem_out_dec = 6'b111111; + 12'd2392 : mem_out_dec = 6'b111111; + 12'd2393 : mem_out_dec = 6'b111111; + 12'd2394 : mem_out_dec = 6'b111111; + 12'd2395 : mem_out_dec = 6'b111111; + 12'd2396 : mem_out_dec = 6'b111111; + 12'd2397 : mem_out_dec = 6'b111111; + 12'd2398 : mem_out_dec = 6'b111111; + 12'd2399 : mem_out_dec = 6'b111111; + 12'd2400 : mem_out_dec = 6'b111111; + 12'd2401 : mem_out_dec = 6'b111111; + 12'd2402 : mem_out_dec = 6'b111111; + 12'd2403 : mem_out_dec = 6'b111111; + 12'd2404 : mem_out_dec = 6'b111111; + 12'd2405 : mem_out_dec = 6'b111111; + 12'd2406 : mem_out_dec = 6'b111111; + 12'd2407 : mem_out_dec = 6'b111111; + 12'd2408 : mem_out_dec = 6'b111111; + 12'd2409 : mem_out_dec = 6'b111111; + 12'd2410 : mem_out_dec = 6'b111111; + 12'd2411 : mem_out_dec = 6'b000101; + 12'd2412 : mem_out_dec = 6'b000101; + 12'd2413 : mem_out_dec = 6'b000110; + 12'd2414 : mem_out_dec = 6'b000111; + 12'd2415 : mem_out_dec = 6'b001000; + 12'd2416 : mem_out_dec = 6'b000111; + 12'd2417 : mem_out_dec = 6'b000111; + 12'd2418 : mem_out_dec = 6'b000111; + 12'd2419 : mem_out_dec = 6'b000111; + 12'd2420 : mem_out_dec = 6'b000111; + 12'd2421 : mem_out_dec = 6'b000111; + 12'd2422 : mem_out_dec = 6'b001000; + 12'd2423 : mem_out_dec = 6'b001001; + 12'd2424 : mem_out_dec = 6'b001001; + 12'd2425 : mem_out_dec = 6'b001010; + 12'd2426 : mem_out_dec = 6'b001010; + 12'd2427 : mem_out_dec = 6'b001011; + 12'd2428 : mem_out_dec = 6'b001100; + 12'd2429 : mem_out_dec = 6'b001101; + 12'd2430 : mem_out_dec = 6'b001101; + 12'd2431 : mem_out_dec = 6'b001110; + 12'd2432 : mem_out_dec = 6'b111111; + 12'd2433 : mem_out_dec = 6'b111111; + 12'd2434 : mem_out_dec = 6'b111111; + 12'd2435 : mem_out_dec = 6'b111111; + 12'd2436 : mem_out_dec = 6'b111111; + 12'd2437 : mem_out_dec = 6'b111111; + 12'd2438 : mem_out_dec = 6'b111111; + 12'd2439 : mem_out_dec = 6'b111111; + 12'd2440 : mem_out_dec = 6'b111111; + 12'd2441 : mem_out_dec = 6'b111111; + 12'd2442 : mem_out_dec = 6'b111111; + 12'd2443 : mem_out_dec = 6'b111111; + 12'd2444 : mem_out_dec = 6'b111111; + 12'd2445 : mem_out_dec = 6'b111111; + 12'd2446 : mem_out_dec = 6'b111111; + 12'd2447 : mem_out_dec = 6'b111111; + 12'd2448 : mem_out_dec = 6'b111111; + 12'd2449 : mem_out_dec = 6'b111111; + 12'd2450 : mem_out_dec = 6'b111111; + 12'd2451 : mem_out_dec = 6'b111111; + 12'd2452 : mem_out_dec = 6'b111111; + 12'd2453 : mem_out_dec = 6'b111111; + 12'd2454 : mem_out_dec = 6'b111111; + 12'd2455 : mem_out_dec = 6'b111111; + 12'd2456 : mem_out_dec = 6'b111111; + 12'd2457 : mem_out_dec = 6'b111111; + 12'd2458 : mem_out_dec = 6'b111111; + 12'd2459 : mem_out_dec = 6'b111111; + 12'd2460 : mem_out_dec = 6'b111111; + 12'd2461 : mem_out_dec = 6'b111111; + 12'd2462 : mem_out_dec = 6'b111111; + 12'd2463 : mem_out_dec = 6'b111111; + 12'd2464 : mem_out_dec = 6'b111111; + 12'd2465 : mem_out_dec = 6'b111111; + 12'd2466 : mem_out_dec = 6'b111111; + 12'd2467 : mem_out_dec = 6'b111111; + 12'd2468 : mem_out_dec = 6'b111111; + 12'd2469 : mem_out_dec = 6'b111111; + 12'd2470 : mem_out_dec = 6'b111111; + 12'd2471 : mem_out_dec = 6'b111111; + 12'd2472 : mem_out_dec = 6'b111111; + 12'd2473 : mem_out_dec = 6'b111111; + 12'd2474 : mem_out_dec = 6'b111111; + 12'd2475 : mem_out_dec = 6'b111111; + 12'd2476 : mem_out_dec = 6'b000101; + 12'd2477 : mem_out_dec = 6'b000110; + 12'd2478 : mem_out_dec = 6'b000111; + 12'd2479 : mem_out_dec = 6'b000111; + 12'd2480 : mem_out_dec = 6'b000110; + 12'd2481 : mem_out_dec = 6'b000110; + 12'd2482 : mem_out_dec = 6'b000110; + 12'd2483 : mem_out_dec = 6'b000110; + 12'd2484 : mem_out_dec = 6'b000110; + 12'd2485 : mem_out_dec = 6'b000111; + 12'd2486 : mem_out_dec = 6'b000111; + 12'd2487 : mem_out_dec = 6'b001000; + 12'd2488 : mem_out_dec = 6'b001001; + 12'd2489 : mem_out_dec = 6'b001001; + 12'd2490 : mem_out_dec = 6'b001010; + 12'd2491 : mem_out_dec = 6'b001011; + 12'd2492 : mem_out_dec = 6'b001011; + 12'd2493 : mem_out_dec = 6'b001100; + 12'd2494 : mem_out_dec = 6'b001101; + 12'd2495 : mem_out_dec = 6'b001110; + 12'd2496 : mem_out_dec = 6'b111111; + 12'd2497 : mem_out_dec = 6'b111111; + 12'd2498 : mem_out_dec = 6'b111111; + 12'd2499 : mem_out_dec = 6'b111111; + 12'd2500 : mem_out_dec = 6'b111111; + 12'd2501 : mem_out_dec = 6'b111111; + 12'd2502 : mem_out_dec = 6'b111111; + 12'd2503 : mem_out_dec = 6'b111111; + 12'd2504 : mem_out_dec = 6'b111111; + 12'd2505 : mem_out_dec = 6'b111111; + 12'd2506 : mem_out_dec = 6'b111111; + 12'd2507 : mem_out_dec = 6'b111111; + 12'd2508 : mem_out_dec = 6'b111111; + 12'd2509 : mem_out_dec = 6'b111111; + 12'd2510 : mem_out_dec = 6'b111111; + 12'd2511 : mem_out_dec = 6'b111111; + 12'd2512 : mem_out_dec = 6'b111111; + 12'd2513 : mem_out_dec = 6'b111111; + 12'd2514 : mem_out_dec = 6'b111111; + 12'd2515 : mem_out_dec = 6'b111111; + 12'd2516 : mem_out_dec = 6'b111111; + 12'd2517 : mem_out_dec = 6'b111111; + 12'd2518 : mem_out_dec = 6'b111111; + 12'd2519 : mem_out_dec = 6'b111111; + 12'd2520 : mem_out_dec = 6'b111111; + 12'd2521 : mem_out_dec = 6'b111111; + 12'd2522 : mem_out_dec = 6'b111111; + 12'd2523 : mem_out_dec = 6'b111111; + 12'd2524 : mem_out_dec = 6'b111111; + 12'd2525 : mem_out_dec = 6'b111111; + 12'd2526 : mem_out_dec = 6'b111111; + 12'd2527 : mem_out_dec = 6'b111111; + 12'd2528 : mem_out_dec = 6'b111111; + 12'd2529 : mem_out_dec = 6'b111111; + 12'd2530 : mem_out_dec = 6'b111111; + 12'd2531 : mem_out_dec = 6'b111111; + 12'd2532 : mem_out_dec = 6'b111111; + 12'd2533 : mem_out_dec = 6'b111111; + 12'd2534 : mem_out_dec = 6'b111111; + 12'd2535 : mem_out_dec = 6'b111111; + 12'd2536 : mem_out_dec = 6'b111111; + 12'd2537 : mem_out_dec = 6'b111111; + 12'd2538 : mem_out_dec = 6'b111111; + 12'd2539 : mem_out_dec = 6'b111111; + 12'd2540 : mem_out_dec = 6'b111111; + 12'd2541 : mem_out_dec = 6'b000101; + 12'd2542 : mem_out_dec = 6'b000110; + 12'd2543 : mem_out_dec = 6'b000110; + 12'd2544 : mem_out_dec = 6'b000110; + 12'd2545 : mem_out_dec = 6'b000110; + 12'd2546 : mem_out_dec = 6'b000101; + 12'd2547 : mem_out_dec = 6'b000101; + 12'd2548 : mem_out_dec = 6'b000110; + 12'd2549 : mem_out_dec = 6'b000111; + 12'd2550 : mem_out_dec = 6'b000111; + 12'd2551 : mem_out_dec = 6'b001000; + 12'd2552 : mem_out_dec = 6'b001000; + 12'd2553 : mem_out_dec = 6'b001001; + 12'd2554 : mem_out_dec = 6'b001010; + 12'd2555 : mem_out_dec = 6'b001010; + 12'd2556 : mem_out_dec = 6'b001011; + 12'd2557 : mem_out_dec = 6'b001100; + 12'd2558 : mem_out_dec = 6'b001101; + 12'd2559 : mem_out_dec = 6'b001101; + 12'd2560 : mem_out_dec = 6'b111111; + 12'd2561 : mem_out_dec = 6'b111111; + 12'd2562 : mem_out_dec = 6'b111111; + 12'd2563 : mem_out_dec = 6'b111111; + 12'd2564 : mem_out_dec = 6'b111111; + 12'd2565 : mem_out_dec = 6'b111111; + 12'd2566 : mem_out_dec = 6'b111111; + 12'd2567 : mem_out_dec = 6'b111111; + 12'd2568 : mem_out_dec = 6'b111111; + 12'd2569 : mem_out_dec = 6'b111111; + 12'd2570 : mem_out_dec = 6'b111111; + 12'd2571 : mem_out_dec = 6'b111111; + 12'd2572 : mem_out_dec = 6'b111111; + 12'd2573 : mem_out_dec = 6'b111111; + 12'd2574 : mem_out_dec = 6'b111111; + 12'd2575 : mem_out_dec = 6'b111111; + 12'd2576 : mem_out_dec = 6'b111111; + 12'd2577 : mem_out_dec = 6'b111111; + 12'd2578 : mem_out_dec = 6'b111111; + 12'd2579 : mem_out_dec = 6'b111111; + 12'd2580 : mem_out_dec = 6'b111111; + 12'd2581 : mem_out_dec = 6'b111111; + 12'd2582 : mem_out_dec = 6'b111111; + 12'd2583 : mem_out_dec = 6'b111111; + 12'd2584 : mem_out_dec = 6'b111111; + 12'd2585 : mem_out_dec = 6'b111111; + 12'd2586 : mem_out_dec = 6'b111111; + 12'd2587 : mem_out_dec = 6'b111111; + 12'd2588 : mem_out_dec = 6'b111111; + 12'd2589 : mem_out_dec = 6'b111111; + 12'd2590 : mem_out_dec = 6'b111111; + 12'd2591 : mem_out_dec = 6'b111111; + 12'd2592 : mem_out_dec = 6'b111111; + 12'd2593 : mem_out_dec = 6'b111111; + 12'd2594 : mem_out_dec = 6'b111111; + 12'd2595 : mem_out_dec = 6'b111111; + 12'd2596 : mem_out_dec = 6'b111111; + 12'd2597 : mem_out_dec = 6'b111111; + 12'd2598 : mem_out_dec = 6'b111111; + 12'd2599 : mem_out_dec = 6'b111111; + 12'd2600 : mem_out_dec = 6'b111111; + 12'd2601 : mem_out_dec = 6'b111111; + 12'd2602 : mem_out_dec = 6'b111111; + 12'd2603 : mem_out_dec = 6'b111111; + 12'd2604 : mem_out_dec = 6'b111111; + 12'd2605 : mem_out_dec = 6'b111111; + 12'd2606 : mem_out_dec = 6'b000100; + 12'd2607 : mem_out_dec = 6'b000101; + 12'd2608 : mem_out_dec = 6'b000100; + 12'd2609 : mem_out_dec = 6'b000100; + 12'd2610 : mem_out_dec = 6'b000100; + 12'd2611 : mem_out_dec = 6'b000101; + 12'd2612 : mem_out_dec = 6'b000101; + 12'd2613 : mem_out_dec = 6'b000110; + 12'd2614 : mem_out_dec = 6'b000111; + 12'd2615 : mem_out_dec = 6'b000111; + 12'd2616 : mem_out_dec = 6'b000111; + 12'd2617 : mem_out_dec = 6'b001000; + 12'd2618 : mem_out_dec = 6'b001001; + 12'd2619 : mem_out_dec = 6'b001010; + 12'd2620 : mem_out_dec = 6'b001010; + 12'd2621 : mem_out_dec = 6'b001011; + 12'd2622 : mem_out_dec = 6'b001100; + 12'd2623 : mem_out_dec = 6'b001101; + 12'd2624 : mem_out_dec = 6'b111111; + 12'd2625 : mem_out_dec = 6'b111111; + 12'd2626 : mem_out_dec = 6'b111111; + 12'd2627 : mem_out_dec = 6'b111111; + 12'd2628 : mem_out_dec = 6'b111111; + 12'd2629 : mem_out_dec = 6'b111111; + 12'd2630 : mem_out_dec = 6'b111111; + 12'd2631 : mem_out_dec = 6'b111111; + 12'd2632 : mem_out_dec = 6'b111111; + 12'd2633 : mem_out_dec = 6'b111111; + 12'd2634 : mem_out_dec = 6'b111111; + 12'd2635 : mem_out_dec = 6'b111111; + 12'd2636 : mem_out_dec = 6'b111111; + 12'd2637 : mem_out_dec = 6'b111111; + 12'd2638 : mem_out_dec = 6'b111111; + 12'd2639 : mem_out_dec = 6'b111111; + 12'd2640 : mem_out_dec = 6'b111111; + 12'd2641 : mem_out_dec = 6'b111111; + 12'd2642 : mem_out_dec = 6'b111111; + 12'd2643 : mem_out_dec = 6'b111111; + 12'd2644 : mem_out_dec = 6'b111111; + 12'd2645 : mem_out_dec = 6'b111111; + 12'd2646 : mem_out_dec = 6'b111111; + 12'd2647 : mem_out_dec = 6'b111111; + 12'd2648 : mem_out_dec = 6'b111111; + 12'd2649 : mem_out_dec = 6'b111111; + 12'd2650 : mem_out_dec = 6'b111111; + 12'd2651 : mem_out_dec = 6'b111111; + 12'd2652 : mem_out_dec = 6'b111111; + 12'd2653 : mem_out_dec = 6'b111111; + 12'd2654 : mem_out_dec = 6'b111111; + 12'd2655 : mem_out_dec = 6'b111111; + 12'd2656 : mem_out_dec = 6'b111111; + 12'd2657 : mem_out_dec = 6'b111111; + 12'd2658 : mem_out_dec = 6'b111111; + 12'd2659 : mem_out_dec = 6'b111111; + 12'd2660 : mem_out_dec = 6'b111111; + 12'd2661 : mem_out_dec = 6'b111111; + 12'd2662 : mem_out_dec = 6'b111111; + 12'd2663 : mem_out_dec = 6'b111111; + 12'd2664 : mem_out_dec = 6'b111111; + 12'd2665 : mem_out_dec = 6'b111111; + 12'd2666 : mem_out_dec = 6'b111111; + 12'd2667 : mem_out_dec = 6'b111111; + 12'd2668 : mem_out_dec = 6'b111111; + 12'd2669 : mem_out_dec = 6'b111111; + 12'd2670 : mem_out_dec = 6'b111111; + 12'd2671 : mem_out_dec = 6'b000100; + 12'd2672 : mem_out_dec = 6'b000011; + 12'd2673 : mem_out_dec = 6'b000011; + 12'd2674 : mem_out_dec = 6'b000100; + 12'd2675 : mem_out_dec = 6'b000100; + 12'd2676 : mem_out_dec = 6'b000101; + 12'd2677 : mem_out_dec = 6'b000110; + 12'd2678 : mem_out_dec = 6'b000110; + 12'd2679 : mem_out_dec = 6'b000111; + 12'd2680 : mem_out_dec = 6'b000111; + 12'd2681 : mem_out_dec = 6'b001000; + 12'd2682 : mem_out_dec = 6'b001001; + 12'd2683 : mem_out_dec = 6'b001001; + 12'd2684 : mem_out_dec = 6'b001010; + 12'd2685 : mem_out_dec = 6'b001011; + 12'd2686 : mem_out_dec = 6'b001100; + 12'd2687 : mem_out_dec = 6'b001100; + 12'd2688 : mem_out_dec = 6'b111111; + 12'd2689 : mem_out_dec = 6'b111111; + 12'd2690 : mem_out_dec = 6'b111111; + 12'd2691 : mem_out_dec = 6'b111111; + 12'd2692 : mem_out_dec = 6'b111111; + 12'd2693 : mem_out_dec = 6'b111111; + 12'd2694 : mem_out_dec = 6'b111111; + 12'd2695 : mem_out_dec = 6'b111111; + 12'd2696 : mem_out_dec = 6'b111111; + 12'd2697 : mem_out_dec = 6'b111111; + 12'd2698 : mem_out_dec = 6'b111111; + 12'd2699 : mem_out_dec = 6'b111111; + 12'd2700 : mem_out_dec = 6'b111111; + 12'd2701 : mem_out_dec = 6'b111111; + 12'd2702 : mem_out_dec = 6'b111111; + 12'd2703 : mem_out_dec = 6'b111111; + 12'd2704 : mem_out_dec = 6'b111111; + 12'd2705 : mem_out_dec = 6'b111111; + 12'd2706 : mem_out_dec = 6'b111111; + 12'd2707 : mem_out_dec = 6'b111111; + 12'd2708 : mem_out_dec = 6'b111111; + 12'd2709 : mem_out_dec = 6'b111111; + 12'd2710 : mem_out_dec = 6'b111111; + 12'd2711 : mem_out_dec = 6'b111111; + 12'd2712 : mem_out_dec = 6'b111111; + 12'd2713 : mem_out_dec = 6'b111111; + 12'd2714 : mem_out_dec = 6'b111111; + 12'd2715 : mem_out_dec = 6'b111111; + 12'd2716 : mem_out_dec = 6'b111111; + 12'd2717 : mem_out_dec = 6'b111111; + 12'd2718 : mem_out_dec = 6'b111111; + 12'd2719 : mem_out_dec = 6'b111111; + 12'd2720 : mem_out_dec = 6'b111111; + 12'd2721 : mem_out_dec = 6'b111111; + 12'd2722 : mem_out_dec = 6'b111111; + 12'd2723 : mem_out_dec = 6'b111111; + 12'd2724 : mem_out_dec = 6'b111111; + 12'd2725 : mem_out_dec = 6'b111111; + 12'd2726 : mem_out_dec = 6'b111111; + 12'd2727 : mem_out_dec = 6'b111111; + 12'd2728 : mem_out_dec = 6'b111111; + 12'd2729 : mem_out_dec = 6'b111111; + 12'd2730 : mem_out_dec = 6'b111111; + 12'd2731 : mem_out_dec = 6'b111111; + 12'd2732 : mem_out_dec = 6'b111111; + 12'd2733 : mem_out_dec = 6'b111111; + 12'd2734 : mem_out_dec = 6'b111111; + 12'd2735 : mem_out_dec = 6'b111111; + 12'd2736 : mem_out_dec = 6'b000011; + 12'd2737 : mem_out_dec = 6'b000011; + 12'd2738 : mem_out_dec = 6'b000100; + 12'd2739 : mem_out_dec = 6'b000100; + 12'd2740 : mem_out_dec = 6'b000101; + 12'd2741 : mem_out_dec = 6'b000101; + 12'd2742 : mem_out_dec = 6'b000110; + 12'd2743 : mem_out_dec = 6'b000111; + 12'd2744 : mem_out_dec = 6'b000111; + 12'd2745 : mem_out_dec = 6'b001000; + 12'd2746 : mem_out_dec = 6'b001000; + 12'd2747 : mem_out_dec = 6'b001001; + 12'd2748 : mem_out_dec = 6'b001010; + 12'd2749 : mem_out_dec = 6'b001011; + 12'd2750 : mem_out_dec = 6'b001011; + 12'd2751 : mem_out_dec = 6'b001100; + 12'd2752 : mem_out_dec = 6'b111111; + 12'd2753 : mem_out_dec = 6'b111111; + 12'd2754 : mem_out_dec = 6'b111111; + 12'd2755 : mem_out_dec = 6'b111111; + 12'd2756 : mem_out_dec = 6'b111111; + 12'd2757 : mem_out_dec = 6'b111111; + 12'd2758 : mem_out_dec = 6'b111111; + 12'd2759 : mem_out_dec = 6'b111111; + 12'd2760 : mem_out_dec = 6'b111111; + 12'd2761 : mem_out_dec = 6'b111111; + 12'd2762 : mem_out_dec = 6'b111111; + 12'd2763 : mem_out_dec = 6'b111111; + 12'd2764 : mem_out_dec = 6'b111111; + 12'd2765 : mem_out_dec = 6'b111111; + 12'd2766 : mem_out_dec = 6'b111111; + 12'd2767 : mem_out_dec = 6'b111111; + 12'd2768 : mem_out_dec = 6'b111111; + 12'd2769 : mem_out_dec = 6'b111111; + 12'd2770 : mem_out_dec = 6'b111111; + 12'd2771 : mem_out_dec = 6'b111111; + 12'd2772 : mem_out_dec = 6'b111111; + 12'd2773 : mem_out_dec = 6'b111111; + 12'd2774 : mem_out_dec = 6'b111111; + 12'd2775 : mem_out_dec = 6'b111111; + 12'd2776 : mem_out_dec = 6'b111111; + 12'd2777 : mem_out_dec = 6'b111111; + 12'd2778 : mem_out_dec = 6'b111111; + 12'd2779 : mem_out_dec = 6'b111111; + 12'd2780 : mem_out_dec = 6'b111111; + 12'd2781 : mem_out_dec = 6'b111111; + 12'd2782 : mem_out_dec = 6'b111111; + 12'd2783 : mem_out_dec = 6'b111111; + 12'd2784 : mem_out_dec = 6'b111111; + 12'd2785 : mem_out_dec = 6'b111111; + 12'd2786 : mem_out_dec = 6'b111111; + 12'd2787 : mem_out_dec = 6'b111111; + 12'd2788 : mem_out_dec = 6'b111111; + 12'd2789 : mem_out_dec = 6'b111111; + 12'd2790 : mem_out_dec = 6'b111111; + 12'd2791 : mem_out_dec = 6'b111111; + 12'd2792 : mem_out_dec = 6'b111111; + 12'd2793 : mem_out_dec = 6'b111111; + 12'd2794 : mem_out_dec = 6'b111111; + 12'd2795 : mem_out_dec = 6'b111111; + 12'd2796 : mem_out_dec = 6'b111111; + 12'd2797 : mem_out_dec = 6'b111111; + 12'd2798 : mem_out_dec = 6'b111111; + 12'd2799 : mem_out_dec = 6'b111111; + 12'd2800 : mem_out_dec = 6'b111111; + 12'd2801 : mem_out_dec = 6'b000011; + 12'd2802 : mem_out_dec = 6'b000011; + 12'd2803 : mem_out_dec = 6'b000100; + 12'd2804 : mem_out_dec = 6'b000101; + 12'd2805 : mem_out_dec = 6'b000101; + 12'd2806 : mem_out_dec = 6'b000110; + 12'd2807 : mem_out_dec = 6'b000111; + 12'd2808 : mem_out_dec = 6'b000111; + 12'd2809 : mem_out_dec = 6'b000111; + 12'd2810 : mem_out_dec = 6'b001000; + 12'd2811 : mem_out_dec = 6'b001001; + 12'd2812 : mem_out_dec = 6'b001010; + 12'd2813 : mem_out_dec = 6'b001010; + 12'd2814 : mem_out_dec = 6'b001011; + 12'd2815 : mem_out_dec = 6'b001100; + 12'd2816 : mem_out_dec = 6'b111111; + 12'd2817 : mem_out_dec = 6'b111111; + 12'd2818 : mem_out_dec = 6'b111111; + 12'd2819 : mem_out_dec = 6'b111111; + 12'd2820 : mem_out_dec = 6'b111111; + 12'd2821 : mem_out_dec = 6'b111111; + 12'd2822 : mem_out_dec = 6'b111111; + 12'd2823 : mem_out_dec = 6'b111111; + 12'd2824 : mem_out_dec = 6'b111111; + 12'd2825 : mem_out_dec = 6'b111111; + 12'd2826 : mem_out_dec = 6'b111111; + 12'd2827 : mem_out_dec = 6'b111111; + 12'd2828 : mem_out_dec = 6'b111111; + 12'd2829 : mem_out_dec = 6'b111111; + 12'd2830 : mem_out_dec = 6'b111111; + 12'd2831 : mem_out_dec = 6'b111111; + 12'd2832 : mem_out_dec = 6'b111111; + 12'd2833 : mem_out_dec = 6'b111111; + 12'd2834 : mem_out_dec = 6'b111111; + 12'd2835 : mem_out_dec = 6'b111111; + 12'd2836 : mem_out_dec = 6'b111111; + 12'd2837 : mem_out_dec = 6'b111111; + 12'd2838 : mem_out_dec = 6'b111111; + 12'd2839 : mem_out_dec = 6'b111111; + 12'd2840 : mem_out_dec = 6'b111111; + 12'd2841 : mem_out_dec = 6'b111111; + 12'd2842 : mem_out_dec = 6'b111111; + 12'd2843 : mem_out_dec = 6'b111111; + 12'd2844 : mem_out_dec = 6'b111111; + 12'd2845 : mem_out_dec = 6'b111111; + 12'd2846 : mem_out_dec = 6'b111111; + 12'd2847 : mem_out_dec = 6'b111111; + 12'd2848 : mem_out_dec = 6'b111111; + 12'd2849 : mem_out_dec = 6'b111111; + 12'd2850 : mem_out_dec = 6'b111111; + 12'd2851 : mem_out_dec = 6'b111111; + 12'd2852 : mem_out_dec = 6'b111111; + 12'd2853 : mem_out_dec = 6'b111111; + 12'd2854 : mem_out_dec = 6'b111111; + 12'd2855 : mem_out_dec = 6'b111111; + 12'd2856 : mem_out_dec = 6'b111111; + 12'd2857 : mem_out_dec = 6'b111111; + 12'd2858 : mem_out_dec = 6'b111111; + 12'd2859 : mem_out_dec = 6'b111111; + 12'd2860 : mem_out_dec = 6'b111111; + 12'd2861 : mem_out_dec = 6'b111111; + 12'd2862 : mem_out_dec = 6'b111111; + 12'd2863 : mem_out_dec = 6'b111111; + 12'd2864 : mem_out_dec = 6'b111111; + 12'd2865 : mem_out_dec = 6'b111111; + 12'd2866 : mem_out_dec = 6'b000011; + 12'd2867 : mem_out_dec = 6'b000100; + 12'd2868 : mem_out_dec = 6'b000100; + 12'd2869 : mem_out_dec = 6'b000101; + 12'd2870 : mem_out_dec = 6'b000110; + 12'd2871 : mem_out_dec = 6'b000110; + 12'd2872 : mem_out_dec = 6'b000110; + 12'd2873 : mem_out_dec = 6'b000111; + 12'd2874 : mem_out_dec = 6'b001000; + 12'd2875 : mem_out_dec = 6'b001001; + 12'd2876 : mem_out_dec = 6'b001001; + 12'd2877 : mem_out_dec = 6'b001010; + 12'd2878 : mem_out_dec = 6'b001011; + 12'd2879 : mem_out_dec = 6'b001100; + 12'd2880 : mem_out_dec = 6'b111111; + 12'd2881 : mem_out_dec = 6'b111111; + 12'd2882 : mem_out_dec = 6'b111111; + 12'd2883 : mem_out_dec = 6'b111111; + 12'd2884 : mem_out_dec = 6'b111111; + 12'd2885 : mem_out_dec = 6'b111111; + 12'd2886 : mem_out_dec = 6'b111111; + 12'd2887 : mem_out_dec = 6'b111111; + 12'd2888 : mem_out_dec = 6'b111111; + 12'd2889 : mem_out_dec = 6'b111111; + 12'd2890 : mem_out_dec = 6'b111111; + 12'd2891 : mem_out_dec = 6'b111111; + 12'd2892 : mem_out_dec = 6'b111111; + 12'd2893 : mem_out_dec = 6'b111111; + 12'd2894 : mem_out_dec = 6'b111111; + 12'd2895 : mem_out_dec = 6'b111111; + 12'd2896 : mem_out_dec = 6'b111111; + 12'd2897 : mem_out_dec = 6'b111111; + 12'd2898 : mem_out_dec = 6'b111111; + 12'd2899 : mem_out_dec = 6'b111111; + 12'd2900 : mem_out_dec = 6'b111111; + 12'd2901 : mem_out_dec = 6'b111111; + 12'd2902 : mem_out_dec = 6'b111111; + 12'd2903 : mem_out_dec = 6'b111111; + 12'd2904 : mem_out_dec = 6'b111111; + 12'd2905 : mem_out_dec = 6'b111111; + 12'd2906 : mem_out_dec = 6'b111111; + 12'd2907 : mem_out_dec = 6'b111111; + 12'd2908 : mem_out_dec = 6'b111111; + 12'd2909 : mem_out_dec = 6'b111111; + 12'd2910 : mem_out_dec = 6'b111111; + 12'd2911 : mem_out_dec = 6'b111111; + 12'd2912 : mem_out_dec = 6'b111111; + 12'd2913 : mem_out_dec = 6'b111111; + 12'd2914 : mem_out_dec = 6'b111111; + 12'd2915 : mem_out_dec = 6'b111111; + 12'd2916 : mem_out_dec = 6'b111111; + 12'd2917 : mem_out_dec = 6'b111111; + 12'd2918 : mem_out_dec = 6'b111111; + 12'd2919 : mem_out_dec = 6'b111111; + 12'd2920 : mem_out_dec = 6'b111111; + 12'd2921 : mem_out_dec = 6'b111111; + 12'd2922 : mem_out_dec = 6'b111111; + 12'd2923 : mem_out_dec = 6'b111111; + 12'd2924 : mem_out_dec = 6'b111111; + 12'd2925 : mem_out_dec = 6'b111111; + 12'd2926 : mem_out_dec = 6'b111111; + 12'd2927 : mem_out_dec = 6'b111111; + 12'd2928 : mem_out_dec = 6'b111111; + 12'd2929 : mem_out_dec = 6'b111111; + 12'd2930 : mem_out_dec = 6'b111111; + 12'd2931 : mem_out_dec = 6'b000100; + 12'd2932 : mem_out_dec = 6'b000100; + 12'd2933 : mem_out_dec = 6'b000101; + 12'd2934 : mem_out_dec = 6'b000101; + 12'd2935 : mem_out_dec = 6'b000110; + 12'd2936 : mem_out_dec = 6'b000110; + 12'd2937 : mem_out_dec = 6'b000111; + 12'd2938 : mem_out_dec = 6'b001000; + 12'd2939 : mem_out_dec = 6'b001000; + 12'd2940 : mem_out_dec = 6'b001001; + 12'd2941 : mem_out_dec = 6'b001010; + 12'd2942 : mem_out_dec = 6'b001011; + 12'd2943 : mem_out_dec = 6'b001011; + 12'd2944 : mem_out_dec = 6'b111111; + 12'd2945 : mem_out_dec = 6'b111111; + 12'd2946 : mem_out_dec = 6'b111111; + 12'd2947 : mem_out_dec = 6'b111111; + 12'd2948 : mem_out_dec = 6'b111111; + 12'd2949 : mem_out_dec = 6'b111111; + 12'd2950 : mem_out_dec = 6'b111111; + 12'd2951 : mem_out_dec = 6'b111111; + 12'd2952 : mem_out_dec = 6'b111111; + 12'd2953 : mem_out_dec = 6'b111111; + 12'd2954 : mem_out_dec = 6'b111111; + 12'd2955 : mem_out_dec = 6'b111111; + 12'd2956 : mem_out_dec = 6'b111111; + 12'd2957 : mem_out_dec = 6'b111111; + 12'd2958 : mem_out_dec = 6'b111111; + 12'd2959 : mem_out_dec = 6'b111111; + 12'd2960 : mem_out_dec = 6'b111111; + 12'd2961 : mem_out_dec = 6'b111111; + 12'd2962 : mem_out_dec = 6'b111111; + 12'd2963 : mem_out_dec = 6'b111111; + 12'd2964 : mem_out_dec = 6'b111111; + 12'd2965 : mem_out_dec = 6'b111111; + 12'd2966 : mem_out_dec = 6'b111111; + 12'd2967 : mem_out_dec = 6'b111111; + 12'd2968 : mem_out_dec = 6'b111111; + 12'd2969 : mem_out_dec = 6'b111111; + 12'd2970 : mem_out_dec = 6'b111111; + 12'd2971 : mem_out_dec = 6'b111111; + 12'd2972 : mem_out_dec = 6'b111111; + 12'd2973 : mem_out_dec = 6'b111111; + 12'd2974 : mem_out_dec = 6'b111111; + 12'd2975 : mem_out_dec = 6'b111111; + 12'd2976 : mem_out_dec = 6'b111111; + 12'd2977 : mem_out_dec = 6'b111111; + 12'd2978 : mem_out_dec = 6'b111111; + 12'd2979 : mem_out_dec = 6'b111111; + 12'd2980 : mem_out_dec = 6'b111111; + 12'd2981 : mem_out_dec = 6'b111111; + 12'd2982 : mem_out_dec = 6'b111111; + 12'd2983 : mem_out_dec = 6'b111111; + 12'd2984 : mem_out_dec = 6'b111111; + 12'd2985 : mem_out_dec = 6'b111111; + 12'd2986 : mem_out_dec = 6'b111111; + 12'd2987 : mem_out_dec = 6'b111111; + 12'd2988 : mem_out_dec = 6'b111111; + 12'd2989 : mem_out_dec = 6'b111111; + 12'd2990 : mem_out_dec = 6'b111111; + 12'd2991 : mem_out_dec = 6'b111111; + 12'd2992 : mem_out_dec = 6'b111111; + 12'd2993 : mem_out_dec = 6'b111111; + 12'd2994 : mem_out_dec = 6'b111111; + 12'd2995 : mem_out_dec = 6'b111111; + 12'd2996 : mem_out_dec = 6'b000100; + 12'd2997 : mem_out_dec = 6'b000101; + 12'd2998 : mem_out_dec = 6'b000101; + 12'd2999 : mem_out_dec = 6'b000110; + 12'd3000 : mem_out_dec = 6'b000110; + 12'd3001 : mem_out_dec = 6'b000111; + 12'd3002 : mem_out_dec = 6'b000111; + 12'd3003 : mem_out_dec = 6'b001000; + 12'd3004 : mem_out_dec = 6'b001001; + 12'd3005 : mem_out_dec = 6'b001010; + 12'd3006 : mem_out_dec = 6'b001010; + 12'd3007 : mem_out_dec = 6'b001011; + 12'd3008 : mem_out_dec = 6'b111111; + 12'd3009 : mem_out_dec = 6'b111111; + 12'd3010 : mem_out_dec = 6'b111111; + 12'd3011 : mem_out_dec = 6'b111111; + 12'd3012 : mem_out_dec = 6'b111111; + 12'd3013 : mem_out_dec = 6'b111111; + 12'd3014 : mem_out_dec = 6'b111111; + 12'd3015 : mem_out_dec = 6'b111111; + 12'd3016 : mem_out_dec = 6'b111111; + 12'd3017 : mem_out_dec = 6'b111111; + 12'd3018 : mem_out_dec = 6'b111111; + 12'd3019 : mem_out_dec = 6'b111111; + 12'd3020 : mem_out_dec = 6'b111111; + 12'd3021 : mem_out_dec = 6'b111111; + 12'd3022 : mem_out_dec = 6'b111111; + 12'd3023 : mem_out_dec = 6'b111111; + 12'd3024 : mem_out_dec = 6'b111111; + 12'd3025 : mem_out_dec = 6'b111111; + 12'd3026 : mem_out_dec = 6'b111111; + 12'd3027 : mem_out_dec = 6'b111111; + 12'd3028 : mem_out_dec = 6'b111111; + 12'd3029 : mem_out_dec = 6'b111111; + 12'd3030 : mem_out_dec = 6'b111111; + 12'd3031 : mem_out_dec = 6'b111111; + 12'd3032 : mem_out_dec = 6'b111111; + 12'd3033 : mem_out_dec = 6'b111111; + 12'd3034 : mem_out_dec = 6'b111111; + 12'd3035 : mem_out_dec = 6'b111111; + 12'd3036 : mem_out_dec = 6'b111111; + 12'd3037 : mem_out_dec = 6'b111111; + 12'd3038 : mem_out_dec = 6'b111111; + 12'd3039 : mem_out_dec = 6'b111111; + 12'd3040 : mem_out_dec = 6'b111111; + 12'd3041 : mem_out_dec = 6'b111111; + 12'd3042 : mem_out_dec = 6'b111111; + 12'd3043 : mem_out_dec = 6'b111111; + 12'd3044 : mem_out_dec = 6'b111111; + 12'd3045 : mem_out_dec = 6'b111111; + 12'd3046 : mem_out_dec = 6'b111111; + 12'd3047 : mem_out_dec = 6'b111111; + 12'd3048 : mem_out_dec = 6'b111111; + 12'd3049 : mem_out_dec = 6'b111111; + 12'd3050 : mem_out_dec = 6'b111111; + 12'd3051 : mem_out_dec = 6'b111111; + 12'd3052 : mem_out_dec = 6'b111111; + 12'd3053 : mem_out_dec = 6'b111111; + 12'd3054 : mem_out_dec = 6'b111111; + 12'd3055 : mem_out_dec = 6'b111111; + 12'd3056 : mem_out_dec = 6'b111111; + 12'd3057 : mem_out_dec = 6'b111111; + 12'd3058 : mem_out_dec = 6'b111111; + 12'd3059 : mem_out_dec = 6'b111111; + 12'd3060 : mem_out_dec = 6'b111111; + 12'd3061 : mem_out_dec = 6'b000100; + 12'd3062 : mem_out_dec = 6'b000101; + 12'd3063 : mem_out_dec = 6'b000110; + 12'd3064 : mem_out_dec = 6'b000110; + 12'd3065 : mem_out_dec = 6'b000111; + 12'd3066 : mem_out_dec = 6'b000111; + 12'd3067 : mem_out_dec = 6'b001000; + 12'd3068 : mem_out_dec = 6'b001001; + 12'd3069 : mem_out_dec = 6'b001001; + 12'd3070 : mem_out_dec = 6'b001010; + 12'd3071 : mem_out_dec = 6'b001011; + 12'd3072 : mem_out_dec = 6'b111111; + 12'd3073 : mem_out_dec = 6'b111111; + 12'd3074 : mem_out_dec = 6'b111111; + 12'd3075 : mem_out_dec = 6'b111111; + 12'd3076 : mem_out_dec = 6'b111111; + 12'd3077 : mem_out_dec = 6'b111111; + 12'd3078 : mem_out_dec = 6'b111111; + 12'd3079 : mem_out_dec = 6'b111111; + 12'd3080 : mem_out_dec = 6'b111111; + 12'd3081 : mem_out_dec = 6'b111111; + 12'd3082 : mem_out_dec = 6'b111111; + 12'd3083 : mem_out_dec = 6'b111111; + 12'd3084 : mem_out_dec = 6'b111111; + 12'd3085 : mem_out_dec = 6'b111111; + 12'd3086 : mem_out_dec = 6'b111111; + 12'd3087 : mem_out_dec = 6'b111111; + 12'd3088 : mem_out_dec = 6'b111111; + 12'd3089 : mem_out_dec = 6'b111111; + 12'd3090 : mem_out_dec = 6'b111111; + 12'd3091 : mem_out_dec = 6'b111111; + 12'd3092 : mem_out_dec = 6'b111111; + 12'd3093 : mem_out_dec = 6'b111111; + 12'd3094 : mem_out_dec = 6'b111111; + 12'd3095 : mem_out_dec = 6'b111111; + 12'd3096 : mem_out_dec = 6'b111111; + 12'd3097 : mem_out_dec = 6'b111111; + 12'd3098 : mem_out_dec = 6'b111111; + 12'd3099 : mem_out_dec = 6'b111111; + 12'd3100 : mem_out_dec = 6'b111111; + 12'd3101 : mem_out_dec = 6'b111111; + 12'd3102 : mem_out_dec = 6'b111111; + 12'd3103 : mem_out_dec = 6'b111111; + 12'd3104 : mem_out_dec = 6'b111111; + 12'd3105 : mem_out_dec = 6'b111111; + 12'd3106 : mem_out_dec = 6'b111111; + 12'd3107 : mem_out_dec = 6'b111111; + 12'd3108 : mem_out_dec = 6'b111111; + 12'd3109 : mem_out_dec = 6'b111111; + 12'd3110 : mem_out_dec = 6'b111111; + 12'd3111 : mem_out_dec = 6'b111111; + 12'd3112 : mem_out_dec = 6'b111111; + 12'd3113 : mem_out_dec = 6'b111111; + 12'd3114 : mem_out_dec = 6'b111111; + 12'd3115 : mem_out_dec = 6'b111111; + 12'd3116 : mem_out_dec = 6'b111111; + 12'd3117 : mem_out_dec = 6'b111111; + 12'd3118 : mem_out_dec = 6'b111111; + 12'd3119 : mem_out_dec = 6'b111111; + 12'd3120 : mem_out_dec = 6'b111111; + 12'd3121 : mem_out_dec = 6'b111111; + 12'd3122 : mem_out_dec = 6'b111111; + 12'd3123 : mem_out_dec = 6'b111111; + 12'd3124 : mem_out_dec = 6'b111111; + 12'd3125 : mem_out_dec = 6'b111111; + 12'd3126 : mem_out_dec = 6'b000100; + 12'd3127 : mem_out_dec = 6'b000101; + 12'd3128 : mem_out_dec = 6'b000101; + 12'd3129 : mem_out_dec = 6'b000110; + 12'd3130 : mem_out_dec = 6'b000110; + 12'd3131 : mem_out_dec = 6'b000111; + 12'd3132 : mem_out_dec = 6'b001000; + 12'd3133 : mem_out_dec = 6'b001000; + 12'd3134 : mem_out_dec = 6'b001001; + 12'd3135 : mem_out_dec = 6'b001010; + 12'd3136 : mem_out_dec = 6'b111111; + 12'd3137 : mem_out_dec = 6'b111111; + 12'd3138 : mem_out_dec = 6'b111111; + 12'd3139 : mem_out_dec = 6'b111111; + 12'd3140 : mem_out_dec = 6'b111111; + 12'd3141 : mem_out_dec = 6'b111111; + 12'd3142 : mem_out_dec = 6'b111111; + 12'd3143 : mem_out_dec = 6'b111111; + 12'd3144 : mem_out_dec = 6'b111111; + 12'd3145 : mem_out_dec = 6'b111111; + 12'd3146 : mem_out_dec = 6'b111111; + 12'd3147 : mem_out_dec = 6'b111111; + 12'd3148 : mem_out_dec = 6'b111111; + 12'd3149 : mem_out_dec = 6'b111111; + 12'd3150 : mem_out_dec = 6'b111111; + 12'd3151 : mem_out_dec = 6'b111111; + 12'd3152 : mem_out_dec = 6'b111111; + 12'd3153 : mem_out_dec = 6'b111111; + 12'd3154 : mem_out_dec = 6'b111111; + 12'd3155 : mem_out_dec = 6'b111111; + 12'd3156 : mem_out_dec = 6'b111111; + 12'd3157 : mem_out_dec = 6'b111111; + 12'd3158 : mem_out_dec = 6'b111111; + 12'd3159 : mem_out_dec = 6'b111111; + 12'd3160 : mem_out_dec = 6'b111111; + 12'd3161 : mem_out_dec = 6'b111111; + 12'd3162 : mem_out_dec = 6'b111111; + 12'd3163 : mem_out_dec = 6'b111111; + 12'd3164 : mem_out_dec = 6'b111111; + 12'd3165 : mem_out_dec = 6'b111111; + 12'd3166 : mem_out_dec = 6'b111111; + 12'd3167 : mem_out_dec = 6'b111111; + 12'd3168 : mem_out_dec = 6'b111111; + 12'd3169 : mem_out_dec = 6'b111111; + 12'd3170 : mem_out_dec = 6'b111111; + 12'd3171 : mem_out_dec = 6'b111111; + 12'd3172 : mem_out_dec = 6'b111111; + 12'd3173 : mem_out_dec = 6'b111111; + 12'd3174 : mem_out_dec = 6'b111111; + 12'd3175 : mem_out_dec = 6'b111111; + 12'd3176 : mem_out_dec = 6'b111111; + 12'd3177 : mem_out_dec = 6'b111111; + 12'd3178 : mem_out_dec = 6'b111111; + 12'd3179 : mem_out_dec = 6'b111111; + 12'd3180 : mem_out_dec = 6'b111111; + 12'd3181 : mem_out_dec = 6'b111111; + 12'd3182 : mem_out_dec = 6'b111111; + 12'd3183 : mem_out_dec = 6'b111111; + 12'd3184 : mem_out_dec = 6'b111111; + 12'd3185 : mem_out_dec = 6'b111111; + 12'd3186 : mem_out_dec = 6'b111111; + 12'd3187 : mem_out_dec = 6'b111111; + 12'd3188 : mem_out_dec = 6'b111111; + 12'd3189 : mem_out_dec = 6'b111111; + 12'd3190 : mem_out_dec = 6'b111111; + 12'd3191 : mem_out_dec = 6'b000100; + 12'd3192 : mem_out_dec = 6'b000100; + 12'd3193 : mem_out_dec = 6'b000101; + 12'd3194 : mem_out_dec = 6'b000110; + 12'd3195 : mem_out_dec = 6'b000110; + 12'd3196 : mem_out_dec = 6'b000111; + 12'd3197 : mem_out_dec = 6'b001000; + 12'd3198 : mem_out_dec = 6'b001000; + 12'd3199 : mem_out_dec = 6'b001001; + 12'd3200 : mem_out_dec = 6'b111111; + 12'd3201 : mem_out_dec = 6'b111111; + 12'd3202 : mem_out_dec = 6'b111111; + 12'd3203 : mem_out_dec = 6'b111111; + 12'd3204 : mem_out_dec = 6'b111111; + 12'd3205 : mem_out_dec = 6'b111111; + 12'd3206 : mem_out_dec = 6'b111111; + 12'd3207 : mem_out_dec = 6'b111111; + 12'd3208 : mem_out_dec = 6'b111111; + 12'd3209 : mem_out_dec = 6'b111111; + 12'd3210 : mem_out_dec = 6'b111111; + 12'd3211 : mem_out_dec = 6'b111111; + 12'd3212 : mem_out_dec = 6'b111111; + 12'd3213 : mem_out_dec = 6'b111111; + 12'd3214 : mem_out_dec = 6'b111111; + 12'd3215 : mem_out_dec = 6'b111111; + 12'd3216 : mem_out_dec = 6'b111111; + 12'd3217 : mem_out_dec = 6'b111111; + 12'd3218 : mem_out_dec = 6'b111111; + 12'd3219 : mem_out_dec = 6'b111111; + 12'd3220 : mem_out_dec = 6'b111111; + 12'd3221 : mem_out_dec = 6'b111111; + 12'd3222 : mem_out_dec = 6'b111111; + 12'd3223 : mem_out_dec = 6'b111111; + 12'd3224 : mem_out_dec = 6'b111111; + 12'd3225 : mem_out_dec = 6'b111111; + 12'd3226 : mem_out_dec = 6'b111111; + 12'd3227 : mem_out_dec = 6'b111111; + 12'd3228 : mem_out_dec = 6'b111111; + 12'd3229 : mem_out_dec = 6'b111111; + 12'd3230 : mem_out_dec = 6'b111111; + 12'd3231 : mem_out_dec = 6'b111111; + 12'd3232 : mem_out_dec = 6'b111111; + 12'd3233 : mem_out_dec = 6'b111111; + 12'd3234 : mem_out_dec = 6'b111111; + 12'd3235 : mem_out_dec = 6'b111111; + 12'd3236 : mem_out_dec = 6'b111111; + 12'd3237 : mem_out_dec = 6'b111111; + 12'd3238 : mem_out_dec = 6'b111111; + 12'd3239 : mem_out_dec = 6'b111111; + 12'd3240 : mem_out_dec = 6'b111111; + 12'd3241 : mem_out_dec = 6'b111111; + 12'd3242 : mem_out_dec = 6'b111111; + 12'd3243 : mem_out_dec = 6'b111111; + 12'd3244 : mem_out_dec = 6'b111111; + 12'd3245 : mem_out_dec = 6'b111111; + 12'd3246 : mem_out_dec = 6'b111111; + 12'd3247 : mem_out_dec = 6'b111111; + 12'd3248 : mem_out_dec = 6'b111111; + 12'd3249 : mem_out_dec = 6'b111111; + 12'd3250 : mem_out_dec = 6'b111111; + 12'd3251 : mem_out_dec = 6'b111111; + 12'd3252 : mem_out_dec = 6'b111111; + 12'd3253 : mem_out_dec = 6'b111111; + 12'd3254 : mem_out_dec = 6'b111111; + 12'd3255 : mem_out_dec = 6'b111111; + 12'd3256 : mem_out_dec = 6'b000100; + 12'd3257 : mem_out_dec = 6'b000100; + 12'd3258 : mem_out_dec = 6'b000101; + 12'd3259 : mem_out_dec = 6'b000110; + 12'd3260 : mem_out_dec = 6'b000110; + 12'd3261 : mem_out_dec = 6'b000111; + 12'd3262 : mem_out_dec = 6'b001000; + 12'd3263 : mem_out_dec = 6'b001001; + 12'd3264 : mem_out_dec = 6'b111111; + 12'd3265 : mem_out_dec = 6'b111111; + 12'd3266 : mem_out_dec = 6'b111111; + 12'd3267 : mem_out_dec = 6'b111111; + 12'd3268 : mem_out_dec = 6'b111111; + 12'd3269 : mem_out_dec = 6'b111111; + 12'd3270 : mem_out_dec = 6'b111111; + 12'd3271 : mem_out_dec = 6'b111111; + 12'd3272 : mem_out_dec = 6'b111111; + 12'd3273 : mem_out_dec = 6'b111111; + 12'd3274 : mem_out_dec = 6'b111111; + 12'd3275 : mem_out_dec = 6'b111111; + 12'd3276 : mem_out_dec = 6'b111111; + 12'd3277 : mem_out_dec = 6'b111111; + 12'd3278 : mem_out_dec = 6'b111111; + 12'd3279 : mem_out_dec = 6'b111111; + 12'd3280 : mem_out_dec = 6'b111111; + 12'd3281 : mem_out_dec = 6'b111111; + 12'd3282 : mem_out_dec = 6'b111111; + 12'd3283 : mem_out_dec = 6'b111111; + 12'd3284 : mem_out_dec = 6'b111111; + 12'd3285 : mem_out_dec = 6'b111111; + 12'd3286 : mem_out_dec = 6'b111111; + 12'd3287 : mem_out_dec = 6'b111111; + 12'd3288 : mem_out_dec = 6'b111111; + 12'd3289 : mem_out_dec = 6'b111111; + 12'd3290 : mem_out_dec = 6'b111111; + 12'd3291 : mem_out_dec = 6'b111111; + 12'd3292 : mem_out_dec = 6'b111111; + 12'd3293 : mem_out_dec = 6'b111111; + 12'd3294 : mem_out_dec = 6'b111111; + 12'd3295 : mem_out_dec = 6'b111111; + 12'd3296 : mem_out_dec = 6'b111111; + 12'd3297 : mem_out_dec = 6'b111111; + 12'd3298 : mem_out_dec = 6'b111111; + 12'd3299 : mem_out_dec = 6'b111111; + 12'd3300 : mem_out_dec = 6'b111111; + 12'd3301 : mem_out_dec = 6'b111111; + 12'd3302 : mem_out_dec = 6'b111111; + 12'd3303 : mem_out_dec = 6'b111111; + 12'd3304 : mem_out_dec = 6'b111111; + 12'd3305 : mem_out_dec = 6'b111111; + 12'd3306 : mem_out_dec = 6'b111111; + 12'd3307 : mem_out_dec = 6'b111111; + 12'd3308 : mem_out_dec = 6'b111111; + 12'd3309 : mem_out_dec = 6'b111111; + 12'd3310 : mem_out_dec = 6'b111111; + 12'd3311 : mem_out_dec = 6'b111111; + 12'd3312 : mem_out_dec = 6'b111111; + 12'd3313 : mem_out_dec = 6'b111111; + 12'd3314 : mem_out_dec = 6'b111111; + 12'd3315 : mem_out_dec = 6'b111111; + 12'd3316 : mem_out_dec = 6'b111111; + 12'd3317 : mem_out_dec = 6'b111111; + 12'd3318 : mem_out_dec = 6'b111111; + 12'd3319 : mem_out_dec = 6'b111111; + 12'd3320 : mem_out_dec = 6'b111111; + 12'd3321 : mem_out_dec = 6'b000100; + 12'd3322 : mem_out_dec = 6'b000100; + 12'd3323 : mem_out_dec = 6'b000101; + 12'd3324 : mem_out_dec = 6'b000110; + 12'd3325 : mem_out_dec = 6'b000111; + 12'd3326 : mem_out_dec = 6'b001000; + 12'd3327 : mem_out_dec = 6'b001000; + 12'd3328 : mem_out_dec = 6'b111111; + 12'd3329 : mem_out_dec = 6'b111111; + 12'd3330 : mem_out_dec = 6'b111111; + 12'd3331 : mem_out_dec = 6'b111111; + 12'd3332 : mem_out_dec = 6'b111111; + 12'd3333 : mem_out_dec = 6'b111111; + 12'd3334 : mem_out_dec = 6'b111111; + 12'd3335 : mem_out_dec = 6'b111111; + 12'd3336 : mem_out_dec = 6'b111111; + 12'd3337 : mem_out_dec = 6'b111111; + 12'd3338 : mem_out_dec = 6'b111111; + 12'd3339 : mem_out_dec = 6'b111111; + 12'd3340 : mem_out_dec = 6'b111111; + 12'd3341 : mem_out_dec = 6'b111111; + 12'd3342 : mem_out_dec = 6'b111111; + 12'd3343 : mem_out_dec = 6'b111111; + 12'd3344 : mem_out_dec = 6'b111111; + 12'd3345 : mem_out_dec = 6'b111111; + 12'd3346 : mem_out_dec = 6'b111111; + 12'd3347 : mem_out_dec = 6'b111111; + 12'd3348 : mem_out_dec = 6'b111111; + 12'd3349 : mem_out_dec = 6'b111111; + 12'd3350 : mem_out_dec = 6'b111111; + 12'd3351 : mem_out_dec = 6'b111111; + 12'd3352 : mem_out_dec = 6'b111111; + 12'd3353 : mem_out_dec = 6'b111111; + 12'd3354 : mem_out_dec = 6'b111111; + 12'd3355 : mem_out_dec = 6'b111111; + 12'd3356 : mem_out_dec = 6'b111111; + 12'd3357 : mem_out_dec = 6'b111111; + 12'd3358 : mem_out_dec = 6'b111111; + 12'd3359 : mem_out_dec = 6'b111111; + 12'd3360 : mem_out_dec = 6'b111111; + 12'd3361 : mem_out_dec = 6'b111111; + 12'd3362 : mem_out_dec = 6'b111111; + 12'd3363 : mem_out_dec = 6'b111111; + 12'd3364 : mem_out_dec = 6'b111111; + 12'd3365 : mem_out_dec = 6'b111111; + 12'd3366 : mem_out_dec = 6'b111111; + 12'd3367 : mem_out_dec = 6'b111111; + 12'd3368 : mem_out_dec = 6'b111111; + 12'd3369 : mem_out_dec = 6'b111111; + 12'd3370 : mem_out_dec = 6'b111111; + 12'd3371 : mem_out_dec = 6'b111111; + 12'd3372 : mem_out_dec = 6'b111111; + 12'd3373 : mem_out_dec = 6'b111111; + 12'd3374 : mem_out_dec = 6'b111111; + 12'd3375 : mem_out_dec = 6'b111111; + 12'd3376 : mem_out_dec = 6'b111111; + 12'd3377 : mem_out_dec = 6'b111111; + 12'd3378 : mem_out_dec = 6'b111111; + 12'd3379 : mem_out_dec = 6'b111111; + 12'd3380 : mem_out_dec = 6'b111111; + 12'd3381 : mem_out_dec = 6'b111111; + 12'd3382 : mem_out_dec = 6'b111111; + 12'd3383 : mem_out_dec = 6'b111111; + 12'd3384 : mem_out_dec = 6'b111111; + 12'd3385 : mem_out_dec = 6'b111111; + 12'd3386 : mem_out_dec = 6'b000100; + 12'd3387 : mem_out_dec = 6'b000101; + 12'd3388 : mem_out_dec = 6'b000110; + 12'd3389 : mem_out_dec = 6'b000110; + 12'd3390 : mem_out_dec = 6'b000111; + 12'd3391 : mem_out_dec = 6'b001000; + 12'd3392 : mem_out_dec = 6'b111111; + 12'd3393 : mem_out_dec = 6'b111111; + 12'd3394 : mem_out_dec = 6'b111111; + 12'd3395 : mem_out_dec = 6'b111111; + 12'd3396 : mem_out_dec = 6'b111111; + 12'd3397 : mem_out_dec = 6'b111111; + 12'd3398 : mem_out_dec = 6'b111111; + 12'd3399 : mem_out_dec = 6'b111111; + 12'd3400 : mem_out_dec = 6'b111111; + 12'd3401 : mem_out_dec = 6'b111111; + 12'd3402 : mem_out_dec = 6'b111111; + 12'd3403 : mem_out_dec = 6'b111111; + 12'd3404 : mem_out_dec = 6'b111111; + 12'd3405 : mem_out_dec = 6'b111111; + 12'd3406 : mem_out_dec = 6'b111111; + 12'd3407 : mem_out_dec = 6'b111111; + 12'd3408 : mem_out_dec = 6'b111111; + 12'd3409 : mem_out_dec = 6'b111111; + 12'd3410 : mem_out_dec = 6'b111111; + 12'd3411 : mem_out_dec = 6'b111111; + 12'd3412 : mem_out_dec = 6'b111111; + 12'd3413 : mem_out_dec = 6'b111111; + 12'd3414 : mem_out_dec = 6'b111111; + 12'd3415 : mem_out_dec = 6'b111111; + 12'd3416 : mem_out_dec = 6'b111111; + 12'd3417 : mem_out_dec = 6'b111111; + 12'd3418 : mem_out_dec = 6'b111111; + 12'd3419 : mem_out_dec = 6'b111111; + 12'd3420 : mem_out_dec = 6'b111111; + 12'd3421 : mem_out_dec = 6'b111111; + 12'd3422 : mem_out_dec = 6'b111111; + 12'd3423 : mem_out_dec = 6'b111111; + 12'd3424 : mem_out_dec = 6'b111111; + 12'd3425 : mem_out_dec = 6'b111111; + 12'd3426 : mem_out_dec = 6'b111111; + 12'd3427 : mem_out_dec = 6'b111111; + 12'd3428 : mem_out_dec = 6'b111111; + 12'd3429 : mem_out_dec = 6'b111111; + 12'd3430 : mem_out_dec = 6'b111111; + 12'd3431 : mem_out_dec = 6'b111111; + 12'd3432 : mem_out_dec = 6'b111111; + 12'd3433 : mem_out_dec = 6'b111111; + 12'd3434 : mem_out_dec = 6'b111111; + 12'd3435 : mem_out_dec = 6'b111111; + 12'd3436 : mem_out_dec = 6'b111111; + 12'd3437 : mem_out_dec = 6'b111111; + 12'd3438 : mem_out_dec = 6'b111111; + 12'd3439 : mem_out_dec = 6'b111111; + 12'd3440 : mem_out_dec = 6'b111111; + 12'd3441 : mem_out_dec = 6'b111111; + 12'd3442 : mem_out_dec = 6'b111111; + 12'd3443 : mem_out_dec = 6'b111111; + 12'd3444 : mem_out_dec = 6'b111111; + 12'd3445 : mem_out_dec = 6'b111111; + 12'd3446 : mem_out_dec = 6'b111111; + 12'd3447 : mem_out_dec = 6'b111111; + 12'd3448 : mem_out_dec = 6'b111111; + 12'd3449 : mem_out_dec = 6'b111111; + 12'd3450 : mem_out_dec = 6'b111111; + 12'd3451 : mem_out_dec = 6'b000100; + 12'd3452 : mem_out_dec = 6'b000101; + 12'd3453 : mem_out_dec = 6'b000110; + 12'd3454 : mem_out_dec = 6'b000111; + 12'd3455 : mem_out_dec = 6'b001000; + 12'd3456 : mem_out_dec = 6'b111111; + 12'd3457 : mem_out_dec = 6'b111111; + 12'd3458 : mem_out_dec = 6'b111111; + 12'd3459 : mem_out_dec = 6'b111111; + 12'd3460 : mem_out_dec = 6'b111111; + 12'd3461 : mem_out_dec = 6'b111111; + 12'd3462 : mem_out_dec = 6'b111111; + 12'd3463 : mem_out_dec = 6'b111111; + 12'd3464 : mem_out_dec = 6'b111111; + 12'd3465 : mem_out_dec = 6'b111111; + 12'd3466 : mem_out_dec = 6'b111111; + 12'd3467 : mem_out_dec = 6'b111111; + 12'd3468 : mem_out_dec = 6'b111111; + 12'd3469 : mem_out_dec = 6'b111111; + 12'd3470 : mem_out_dec = 6'b111111; + 12'd3471 : mem_out_dec = 6'b111111; + 12'd3472 : mem_out_dec = 6'b111111; + 12'd3473 : mem_out_dec = 6'b111111; + 12'd3474 : mem_out_dec = 6'b111111; + 12'd3475 : mem_out_dec = 6'b111111; + 12'd3476 : mem_out_dec = 6'b111111; + 12'd3477 : mem_out_dec = 6'b111111; + 12'd3478 : mem_out_dec = 6'b111111; + 12'd3479 : mem_out_dec = 6'b111111; + 12'd3480 : mem_out_dec = 6'b111111; + 12'd3481 : mem_out_dec = 6'b111111; + 12'd3482 : mem_out_dec = 6'b111111; + 12'd3483 : mem_out_dec = 6'b111111; + 12'd3484 : mem_out_dec = 6'b111111; + 12'd3485 : mem_out_dec = 6'b111111; + 12'd3486 : mem_out_dec = 6'b111111; + 12'd3487 : mem_out_dec = 6'b111111; + 12'd3488 : mem_out_dec = 6'b111111; + 12'd3489 : mem_out_dec = 6'b111111; + 12'd3490 : mem_out_dec = 6'b111111; + 12'd3491 : mem_out_dec = 6'b111111; + 12'd3492 : mem_out_dec = 6'b111111; + 12'd3493 : mem_out_dec = 6'b111111; + 12'd3494 : mem_out_dec = 6'b111111; + 12'd3495 : mem_out_dec = 6'b111111; + 12'd3496 : mem_out_dec = 6'b111111; + 12'd3497 : mem_out_dec = 6'b111111; + 12'd3498 : mem_out_dec = 6'b111111; + 12'd3499 : mem_out_dec = 6'b111111; + 12'd3500 : mem_out_dec = 6'b111111; + 12'd3501 : mem_out_dec = 6'b111111; + 12'd3502 : mem_out_dec = 6'b111111; + 12'd3503 : mem_out_dec = 6'b111111; + 12'd3504 : mem_out_dec = 6'b111111; + 12'd3505 : mem_out_dec = 6'b111111; + 12'd3506 : mem_out_dec = 6'b111111; + 12'd3507 : mem_out_dec = 6'b111111; + 12'd3508 : mem_out_dec = 6'b111111; + 12'd3509 : mem_out_dec = 6'b111111; + 12'd3510 : mem_out_dec = 6'b111111; + 12'd3511 : mem_out_dec = 6'b111111; + 12'd3512 : mem_out_dec = 6'b111111; + 12'd3513 : mem_out_dec = 6'b111111; + 12'd3514 : mem_out_dec = 6'b111111; + 12'd3515 : mem_out_dec = 6'b111111; + 12'd3516 : mem_out_dec = 6'b000101; + 12'd3517 : mem_out_dec = 6'b000110; + 12'd3518 : mem_out_dec = 6'b000110; + 12'd3519 : mem_out_dec = 6'b000111; + 12'd3520 : mem_out_dec = 6'b111111; + 12'd3521 : mem_out_dec = 6'b111111; + 12'd3522 : mem_out_dec = 6'b111111; + 12'd3523 : mem_out_dec = 6'b111111; + 12'd3524 : mem_out_dec = 6'b111111; + 12'd3525 : mem_out_dec = 6'b111111; + 12'd3526 : mem_out_dec = 6'b111111; + 12'd3527 : mem_out_dec = 6'b111111; + 12'd3528 : mem_out_dec = 6'b111111; + 12'd3529 : mem_out_dec = 6'b111111; + 12'd3530 : mem_out_dec = 6'b111111; + 12'd3531 : mem_out_dec = 6'b111111; + 12'd3532 : mem_out_dec = 6'b111111; + 12'd3533 : mem_out_dec = 6'b111111; + 12'd3534 : mem_out_dec = 6'b111111; + 12'd3535 : mem_out_dec = 6'b111111; + 12'd3536 : mem_out_dec = 6'b111111; + 12'd3537 : mem_out_dec = 6'b111111; + 12'd3538 : mem_out_dec = 6'b111111; + 12'd3539 : mem_out_dec = 6'b111111; + 12'd3540 : mem_out_dec = 6'b111111; + 12'd3541 : mem_out_dec = 6'b111111; + 12'd3542 : mem_out_dec = 6'b111111; + 12'd3543 : mem_out_dec = 6'b111111; + 12'd3544 : mem_out_dec = 6'b111111; + 12'd3545 : mem_out_dec = 6'b111111; + 12'd3546 : mem_out_dec = 6'b111111; + 12'd3547 : mem_out_dec = 6'b111111; + 12'd3548 : mem_out_dec = 6'b111111; + 12'd3549 : mem_out_dec = 6'b111111; + 12'd3550 : mem_out_dec = 6'b111111; + 12'd3551 : mem_out_dec = 6'b111111; + 12'd3552 : mem_out_dec = 6'b111111; + 12'd3553 : mem_out_dec = 6'b111111; + 12'd3554 : mem_out_dec = 6'b111111; + 12'd3555 : mem_out_dec = 6'b111111; + 12'd3556 : mem_out_dec = 6'b111111; + 12'd3557 : mem_out_dec = 6'b111111; + 12'd3558 : mem_out_dec = 6'b111111; + 12'd3559 : mem_out_dec = 6'b111111; + 12'd3560 : mem_out_dec = 6'b111111; + 12'd3561 : mem_out_dec = 6'b111111; + 12'd3562 : mem_out_dec = 6'b111111; + 12'd3563 : mem_out_dec = 6'b111111; + 12'd3564 : mem_out_dec = 6'b111111; + 12'd3565 : mem_out_dec = 6'b111111; + 12'd3566 : mem_out_dec = 6'b111111; + 12'd3567 : mem_out_dec = 6'b111111; + 12'd3568 : mem_out_dec = 6'b111111; + 12'd3569 : mem_out_dec = 6'b111111; + 12'd3570 : mem_out_dec = 6'b111111; + 12'd3571 : mem_out_dec = 6'b111111; + 12'd3572 : mem_out_dec = 6'b111111; + 12'd3573 : mem_out_dec = 6'b111111; + 12'd3574 : mem_out_dec = 6'b111111; + 12'd3575 : mem_out_dec = 6'b111111; + 12'd3576 : mem_out_dec = 6'b111111; + 12'd3577 : mem_out_dec = 6'b111111; + 12'd3578 : mem_out_dec = 6'b111111; + 12'd3579 : mem_out_dec = 6'b111111; + 12'd3580 : mem_out_dec = 6'b111111; + 12'd3581 : mem_out_dec = 6'b000101; + 12'd3582 : mem_out_dec = 6'b000110; + 12'd3583 : mem_out_dec = 6'b000110; + 12'd3584 : mem_out_dec = 6'b111111; + 12'd3585 : mem_out_dec = 6'b111111; + 12'd3586 : mem_out_dec = 6'b111111; + 12'd3587 : mem_out_dec = 6'b111111; + 12'd3588 : mem_out_dec = 6'b111111; + 12'd3589 : mem_out_dec = 6'b111111; + 12'd3590 : mem_out_dec = 6'b111111; + 12'd3591 : mem_out_dec = 6'b111111; + 12'd3592 : mem_out_dec = 6'b111111; + 12'd3593 : mem_out_dec = 6'b111111; + 12'd3594 : mem_out_dec = 6'b111111; + 12'd3595 : mem_out_dec = 6'b111111; + 12'd3596 : mem_out_dec = 6'b111111; + 12'd3597 : mem_out_dec = 6'b111111; + 12'd3598 : mem_out_dec = 6'b111111; + 12'd3599 : mem_out_dec = 6'b111111; + 12'd3600 : mem_out_dec = 6'b111111; + 12'd3601 : mem_out_dec = 6'b111111; + 12'd3602 : mem_out_dec = 6'b111111; + 12'd3603 : mem_out_dec = 6'b111111; + 12'd3604 : mem_out_dec = 6'b111111; + 12'd3605 : mem_out_dec = 6'b111111; + 12'd3606 : mem_out_dec = 6'b111111; + 12'd3607 : mem_out_dec = 6'b111111; + 12'd3608 : mem_out_dec = 6'b111111; + 12'd3609 : mem_out_dec = 6'b111111; + 12'd3610 : mem_out_dec = 6'b111111; + 12'd3611 : mem_out_dec = 6'b111111; + 12'd3612 : mem_out_dec = 6'b111111; + 12'd3613 : mem_out_dec = 6'b111111; + 12'd3614 : mem_out_dec = 6'b111111; + 12'd3615 : mem_out_dec = 6'b111111; + 12'd3616 : mem_out_dec = 6'b111111; + 12'd3617 : mem_out_dec = 6'b111111; + 12'd3618 : mem_out_dec = 6'b111111; + 12'd3619 : mem_out_dec = 6'b111111; + 12'd3620 : mem_out_dec = 6'b111111; + 12'd3621 : mem_out_dec = 6'b111111; + 12'd3622 : mem_out_dec = 6'b111111; + 12'd3623 : mem_out_dec = 6'b111111; + 12'd3624 : mem_out_dec = 6'b111111; + 12'd3625 : mem_out_dec = 6'b111111; + 12'd3626 : mem_out_dec = 6'b111111; + 12'd3627 : mem_out_dec = 6'b111111; + 12'd3628 : mem_out_dec = 6'b111111; + 12'd3629 : mem_out_dec = 6'b111111; + 12'd3630 : mem_out_dec = 6'b111111; + 12'd3631 : mem_out_dec = 6'b111111; + 12'd3632 : mem_out_dec = 6'b111111; + 12'd3633 : mem_out_dec = 6'b111111; + 12'd3634 : mem_out_dec = 6'b111111; + 12'd3635 : mem_out_dec = 6'b111111; + 12'd3636 : mem_out_dec = 6'b111111; + 12'd3637 : mem_out_dec = 6'b111111; + 12'd3638 : mem_out_dec = 6'b111111; + 12'd3639 : mem_out_dec = 6'b111111; + 12'd3640 : mem_out_dec = 6'b111111; + 12'd3641 : mem_out_dec = 6'b111111; + 12'd3642 : mem_out_dec = 6'b111111; + 12'd3643 : mem_out_dec = 6'b111111; + 12'd3644 : mem_out_dec = 6'b111111; + 12'd3645 : mem_out_dec = 6'b111111; + 12'd3646 : mem_out_dec = 6'b000100; + 12'd3647 : mem_out_dec = 6'b000101; + 12'd3648 : mem_out_dec = 6'b111111; + 12'd3649 : mem_out_dec = 6'b111111; + 12'd3650 : mem_out_dec = 6'b111111; + 12'd3651 : mem_out_dec = 6'b111111; + 12'd3652 : mem_out_dec = 6'b111111; + 12'd3653 : mem_out_dec = 6'b111111; + 12'd3654 : mem_out_dec = 6'b111111; + 12'd3655 : mem_out_dec = 6'b111111; + 12'd3656 : mem_out_dec = 6'b111111; + 12'd3657 : mem_out_dec = 6'b111111; + 12'd3658 : mem_out_dec = 6'b111111; + 12'd3659 : mem_out_dec = 6'b111111; + 12'd3660 : mem_out_dec = 6'b111111; + 12'd3661 : mem_out_dec = 6'b111111; + 12'd3662 : mem_out_dec = 6'b111111; + 12'd3663 : mem_out_dec = 6'b111111; + 12'd3664 : mem_out_dec = 6'b111111; + 12'd3665 : mem_out_dec = 6'b111111; + 12'd3666 : mem_out_dec = 6'b111111; + 12'd3667 : mem_out_dec = 6'b111111; + 12'd3668 : mem_out_dec = 6'b111111; + 12'd3669 : mem_out_dec = 6'b111111; + 12'd3670 : mem_out_dec = 6'b111111; + 12'd3671 : mem_out_dec = 6'b111111; + 12'd3672 : mem_out_dec = 6'b111111; + 12'd3673 : mem_out_dec = 6'b111111; + 12'd3674 : mem_out_dec = 6'b111111; + 12'd3675 : mem_out_dec = 6'b111111; + 12'd3676 : mem_out_dec = 6'b111111; + 12'd3677 : mem_out_dec = 6'b111111; + 12'd3678 : mem_out_dec = 6'b111111; + 12'd3679 : mem_out_dec = 6'b111111; + 12'd3680 : mem_out_dec = 6'b111111; + 12'd3681 : mem_out_dec = 6'b111111; + 12'd3682 : mem_out_dec = 6'b111111; + 12'd3683 : mem_out_dec = 6'b111111; + 12'd3684 : mem_out_dec = 6'b111111; + 12'd3685 : mem_out_dec = 6'b111111; + 12'd3686 : mem_out_dec = 6'b111111; + 12'd3687 : mem_out_dec = 6'b111111; + 12'd3688 : mem_out_dec = 6'b111111; + 12'd3689 : mem_out_dec = 6'b111111; + 12'd3690 : mem_out_dec = 6'b111111; + 12'd3691 : mem_out_dec = 6'b111111; + 12'd3692 : mem_out_dec = 6'b111111; + 12'd3693 : mem_out_dec = 6'b111111; + 12'd3694 : mem_out_dec = 6'b111111; + 12'd3695 : mem_out_dec = 6'b111111; + 12'd3696 : mem_out_dec = 6'b111111; + 12'd3697 : mem_out_dec = 6'b111111; + 12'd3698 : mem_out_dec = 6'b111111; + 12'd3699 : mem_out_dec = 6'b111111; + 12'd3700 : mem_out_dec = 6'b111111; + 12'd3701 : mem_out_dec = 6'b111111; + 12'd3702 : mem_out_dec = 6'b111111; + 12'd3703 : mem_out_dec = 6'b111111; + 12'd3704 : mem_out_dec = 6'b111111; + 12'd3705 : mem_out_dec = 6'b111111; + 12'd3706 : mem_out_dec = 6'b111111; + 12'd3707 : mem_out_dec = 6'b111111; + 12'd3708 : mem_out_dec = 6'b111111; + 12'd3709 : mem_out_dec = 6'b111111; + 12'd3710 : mem_out_dec = 6'b111111; + 12'd3711 : mem_out_dec = 6'b000100; + 12'd3712 : mem_out_dec = 6'b111111; + 12'd3713 : mem_out_dec = 6'b111111; + 12'd3714 : mem_out_dec = 6'b111111; + 12'd3715 : mem_out_dec = 6'b111111; + 12'd3716 : mem_out_dec = 6'b111111; + 12'd3717 : mem_out_dec = 6'b111111; + 12'd3718 : mem_out_dec = 6'b111111; + 12'd3719 : mem_out_dec = 6'b111111; + 12'd3720 : mem_out_dec = 6'b111111; + 12'd3721 : mem_out_dec = 6'b111111; + 12'd3722 : mem_out_dec = 6'b111111; + 12'd3723 : mem_out_dec = 6'b111111; + 12'd3724 : mem_out_dec = 6'b111111; + 12'd3725 : mem_out_dec = 6'b111111; + 12'd3726 : mem_out_dec = 6'b111111; + 12'd3727 : mem_out_dec = 6'b111111; + 12'd3728 : mem_out_dec = 6'b111111; + 12'd3729 : mem_out_dec = 6'b111111; + 12'd3730 : mem_out_dec = 6'b111111; + 12'd3731 : mem_out_dec = 6'b111111; + 12'd3732 : mem_out_dec = 6'b111111; + 12'd3733 : mem_out_dec = 6'b111111; + 12'd3734 : mem_out_dec = 6'b111111; + 12'd3735 : mem_out_dec = 6'b111111; + 12'd3736 : mem_out_dec = 6'b111111; + 12'd3737 : mem_out_dec = 6'b111111; + 12'd3738 : mem_out_dec = 6'b111111; + 12'd3739 : mem_out_dec = 6'b111111; + 12'd3740 : mem_out_dec = 6'b111111; + 12'd3741 : mem_out_dec = 6'b111111; + 12'd3742 : mem_out_dec = 6'b111111; + 12'd3743 : mem_out_dec = 6'b111111; + 12'd3744 : mem_out_dec = 6'b111111; + 12'd3745 : mem_out_dec = 6'b111111; + 12'd3746 : mem_out_dec = 6'b111111; + 12'd3747 : mem_out_dec = 6'b111111; + 12'd3748 : mem_out_dec = 6'b111111; + 12'd3749 : mem_out_dec = 6'b111111; + 12'd3750 : mem_out_dec = 6'b111111; + 12'd3751 : mem_out_dec = 6'b111111; + 12'd3752 : mem_out_dec = 6'b111111; + 12'd3753 : mem_out_dec = 6'b111111; + 12'd3754 : mem_out_dec = 6'b111111; + 12'd3755 : mem_out_dec = 6'b111111; + 12'd3756 : mem_out_dec = 6'b111111; + 12'd3757 : mem_out_dec = 6'b111111; + 12'd3758 : mem_out_dec = 6'b111111; + 12'd3759 : mem_out_dec = 6'b111111; + 12'd3760 : mem_out_dec = 6'b111111; + 12'd3761 : mem_out_dec = 6'b111111; + 12'd3762 : mem_out_dec = 6'b111111; + 12'd3763 : mem_out_dec = 6'b111111; + 12'd3764 : mem_out_dec = 6'b111111; + 12'd3765 : mem_out_dec = 6'b111111; + 12'd3766 : mem_out_dec = 6'b111111; + 12'd3767 : mem_out_dec = 6'b111111; + 12'd3768 : mem_out_dec = 6'b111111; + 12'd3769 : mem_out_dec = 6'b111111; + 12'd3770 : mem_out_dec = 6'b111111; + 12'd3771 : mem_out_dec = 6'b111111; + 12'd3772 : mem_out_dec = 6'b111111; + 12'd3773 : mem_out_dec = 6'b111111; + 12'd3774 : mem_out_dec = 6'b111111; + 12'd3775 : mem_out_dec = 6'b111111; + 12'd3776 : mem_out_dec = 6'b111111; + 12'd3777 : mem_out_dec = 6'b111111; + 12'd3778 : mem_out_dec = 6'b111111; + 12'd3779 : mem_out_dec = 6'b111111; + 12'd3780 : mem_out_dec = 6'b111111; + 12'd3781 : mem_out_dec = 6'b111111; + 12'd3782 : mem_out_dec = 6'b111111; + 12'd3783 : mem_out_dec = 6'b111111; + 12'd3784 : mem_out_dec = 6'b111111; + 12'd3785 : mem_out_dec = 6'b111111; + 12'd3786 : mem_out_dec = 6'b111111; + 12'd3787 : mem_out_dec = 6'b111111; + 12'd3788 : mem_out_dec = 6'b111111; + 12'd3789 : mem_out_dec = 6'b111111; + 12'd3790 : mem_out_dec = 6'b111111; + 12'd3791 : mem_out_dec = 6'b111111; + 12'd3792 : mem_out_dec = 6'b111111; + 12'd3793 : mem_out_dec = 6'b111111; + 12'd3794 : mem_out_dec = 6'b111111; + 12'd3795 : mem_out_dec = 6'b111111; + 12'd3796 : mem_out_dec = 6'b111111; + 12'd3797 : mem_out_dec = 6'b111111; + 12'd3798 : mem_out_dec = 6'b111111; + 12'd3799 : mem_out_dec = 6'b111111; + 12'd3800 : mem_out_dec = 6'b111111; + 12'd3801 : mem_out_dec = 6'b111111; + 12'd3802 : mem_out_dec = 6'b111111; + 12'd3803 : mem_out_dec = 6'b111111; + 12'd3804 : mem_out_dec = 6'b111111; + 12'd3805 : mem_out_dec = 6'b111111; + 12'd3806 : mem_out_dec = 6'b111111; + 12'd3807 : mem_out_dec = 6'b111111; + 12'd3808 : mem_out_dec = 6'b111111; + 12'd3809 : mem_out_dec = 6'b111111; + 12'd3810 : mem_out_dec = 6'b111111; + 12'd3811 : mem_out_dec = 6'b111111; + 12'd3812 : mem_out_dec = 6'b111111; + 12'd3813 : mem_out_dec = 6'b111111; + 12'd3814 : mem_out_dec = 6'b111111; + 12'd3815 : mem_out_dec = 6'b111111; + 12'd3816 : mem_out_dec = 6'b111111; + 12'd3817 : mem_out_dec = 6'b111111; + 12'd3818 : mem_out_dec = 6'b111111; + 12'd3819 : mem_out_dec = 6'b111111; + 12'd3820 : mem_out_dec = 6'b111111; + 12'd3821 : mem_out_dec = 6'b111111; + 12'd3822 : mem_out_dec = 6'b111111; + 12'd3823 : mem_out_dec = 6'b111111; + 12'd3824 : mem_out_dec = 6'b111111; + 12'd3825 : mem_out_dec = 6'b111111; + 12'd3826 : mem_out_dec = 6'b111111; + 12'd3827 : mem_out_dec = 6'b111111; + 12'd3828 : mem_out_dec = 6'b111111; + 12'd3829 : mem_out_dec = 6'b111111; + 12'd3830 : mem_out_dec = 6'b111111; + 12'd3831 : mem_out_dec = 6'b111111; + 12'd3832 : mem_out_dec = 6'b111111; + 12'd3833 : mem_out_dec = 6'b111111; + 12'd3834 : mem_out_dec = 6'b111111; + 12'd3835 : mem_out_dec = 6'b111111; + 12'd3836 : mem_out_dec = 6'b111111; + 12'd3837 : mem_out_dec = 6'b111111; + 12'd3838 : mem_out_dec = 6'b111111; + 12'd3839 : mem_out_dec = 6'b111111; + 12'd3840 : mem_out_dec = 6'b111111; + 12'd3841 : mem_out_dec = 6'b111111; + 12'd3842 : mem_out_dec = 6'b111111; + 12'd3843 : mem_out_dec = 6'b111111; + 12'd3844 : mem_out_dec = 6'b111111; + 12'd3845 : mem_out_dec = 6'b111111; + 12'd3846 : mem_out_dec = 6'b111111; + 12'd3847 : mem_out_dec = 6'b111111; + 12'd3848 : mem_out_dec = 6'b111111; + 12'd3849 : mem_out_dec = 6'b111111; + 12'd3850 : mem_out_dec = 6'b111111; + 12'd3851 : mem_out_dec = 6'b111111; + 12'd3852 : mem_out_dec = 6'b111111; + 12'd3853 : mem_out_dec = 6'b111111; + 12'd3854 : mem_out_dec = 6'b111111; + 12'd3855 : mem_out_dec = 6'b111111; + 12'd3856 : mem_out_dec = 6'b111111; + 12'd3857 : mem_out_dec = 6'b111111; + 12'd3858 : mem_out_dec = 6'b111111; + 12'd3859 : mem_out_dec = 6'b111111; + 12'd3860 : mem_out_dec = 6'b111111; + 12'd3861 : mem_out_dec = 6'b111111; + 12'd3862 : mem_out_dec = 6'b111111; + 12'd3863 : mem_out_dec = 6'b111111; + 12'd3864 : mem_out_dec = 6'b111111; + 12'd3865 : mem_out_dec = 6'b111111; + 12'd3866 : mem_out_dec = 6'b111111; + 12'd3867 : mem_out_dec = 6'b111111; + 12'd3868 : mem_out_dec = 6'b111111; + 12'd3869 : mem_out_dec = 6'b111111; + 12'd3870 : mem_out_dec = 6'b111111; + 12'd3871 : mem_out_dec = 6'b111111; + 12'd3872 : mem_out_dec = 6'b111111; + 12'd3873 : mem_out_dec = 6'b111111; + 12'd3874 : mem_out_dec = 6'b111111; + 12'd3875 : mem_out_dec = 6'b111111; + 12'd3876 : mem_out_dec = 6'b111111; + 12'd3877 : mem_out_dec = 6'b111111; + 12'd3878 : mem_out_dec = 6'b111111; + 12'd3879 : mem_out_dec = 6'b111111; + 12'd3880 : mem_out_dec = 6'b111111; + 12'd3881 : mem_out_dec = 6'b111111; + 12'd3882 : mem_out_dec = 6'b111111; + 12'd3883 : mem_out_dec = 6'b111111; + 12'd3884 : mem_out_dec = 6'b111111; + 12'd3885 : mem_out_dec = 6'b111111; + 12'd3886 : mem_out_dec = 6'b111111; + 12'd3887 : mem_out_dec = 6'b111111; + 12'd3888 : mem_out_dec = 6'b111111; + 12'd3889 : mem_out_dec = 6'b111111; + 12'd3890 : mem_out_dec = 6'b111111; + 12'd3891 : mem_out_dec = 6'b111111; + 12'd3892 : mem_out_dec = 6'b111111; + 12'd3893 : mem_out_dec = 6'b111111; + 12'd3894 : mem_out_dec = 6'b111111; + 12'd3895 : mem_out_dec = 6'b111111; + 12'd3896 : mem_out_dec = 6'b111111; + 12'd3897 : mem_out_dec = 6'b111111; + 12'd3898 : mem_out_dec = 6'b111111; + 12'd3899 : mem_out_dec = 6'b111111; + 12'd3900 : mem_out_dec = 6'b111111; + 12'd3901 : mem_out_dec = 6'b111111; + 12'd3902 : mem_out_dec = 6'b111111; + 12'd3903 : mem_out_dec = 6'b111111; + 12'd3904 : mem_out_dec = 6'b111111; + 12'd3905 : mem_out_dec = 6'b111111; + 12'd3906 : mem_out_dec = 6'b111111; + 12'd3907 : mem_out_dec = 6'b111111; + 12'd3908 : mem_out_dec = 6'b111111; + 12'd3909 : mem_out_dec = 6'b111111; + 12'd3910 : mem_out_dec = 6'b111111; + 12'd3911 : mem_out_dec = 6'b111111; + 12'd3912 : mem_out_dec = 6'b111111; + 12'd3913 : mem_out_dec = 6'b111111; + 12'd3914 : mem_out_dec = 6'b111111; + 12'd3915 : mem_out_dec = 6'b111111; + 12'd3916 : mem_out_dec = 6'b111111; + 12'd3917 : mem_out_dec = 6'b111111; + 12'd3918 : mem_out_dec = 6'b111111; + 12'd3919 : mem_out_dec = 6'b111111; + 12'd3920 : mem_out_dec = 6'b111111; + 12'd3921 : mem_out_dec = 6'b111111; + 12'd3922 : mem_out_dec = 6'b111111; + 12'd3923 : mem_out_dec = 6'b111111; + 12'd3924 : mem_out_dec = 6'b111111; + 12'd3925 : mem_out_dec = 6'b111111; + 12'd3926 : mem_out_dec = 6'b111111; + 12'd3927 : mem_out_dec = 6'b111111; + 12'd3928 : mem_out_dec = 6'b111111; + 12'd3929 : mem_out_dec = 6'b111111; + 12'd3930 : mem_out_dec = 6'b111111; + 12'd3931 : mem_out_dec = 6'b111111; + 12'd3932 : mem_out_dec = 6'b111111; + 12'd3933 : mem_out_dec = 6'b111111; + 12'd3934 : mem_out_dec = 6'b111111; + 12'd3935 : mem_out_dec = 6'b111111; + 12'd3936 : mem_out_dec = 6'b111111; + 12'd3937 : mem_out_dec = 6'b111111; + 12'd3938 : mem_out_dec = 6'b111111; + 12'd3939 : mem_out_dec = 6'b111111; + 12'd3940 : mem_out_dec = 6'b111111; + 12'd3941 : mem_out_dec = 6'b111111; + 12'd3942 : mem_out_dec = 6'b111111; + 12'd3943 : mem_out_dec = 6'b111111; + 12'd3944 : mem_out_dec = 6'b111111; + 12'd3945 : mem_out_dec = 6'b111111; + 12'd3946 : mem_out_dec = 6'b111111; + 12'd3947 : mem_out_dec = 6'b111111; + 12'd3948 : mem_out_dec = 6'b111111; + 12'd3949 : mem_out_dec = 6'b111111; + 12'd3950 : mem_out_dec = 6'b111111; + 12'd3951 : mem_out_dec = 6'b111111; + 12'd3952 : mem_out_dec = 6'b111111; + 12'd3953 : mem_out_dec = 6'b111111; + 12'd3954 : mem_out_dec = 6'b111111; + 12'd3955 : mem_out_dec = 6'b111111; + 12'd3956 : mem_out_dec = 6'b111111; + 12'd3957 : mem_out_dec = 6'b111111; + 12'd3958 : mem_out_dec = 6'b111111; + 12'd3959 : mem_out_dec = 6'b111111; + 12'd3960 : mem_out_dec = 6'b111111; + 12'd3961 : mem_out_dec = 6'b111111; + 12'd3962 : mem_out_dec = 6'b111111; + 12'd3963 : mem_out_dec = 6'b111111; + 12'd3964 : mem_out_dec = 6'b111111; + 12'd3965 : mem_out_dec = 6'b111111; + 12'd3966 : mem_out_dec = 6'b111111; + 12'd3967 : mem_out_dec = 6'b111111; + 12'd3968 : mem_out_dec = 6'b111111; + 12'd3969 : mem_out_dec = 6'b111111; + 12'd3970 : mem_out_dec = 6'b111111; + 12'd3971 : mem_out_dec = 6'b111111; + 12'd3972 : mem_out_dec = 6'b111111; + 12'd3973 : mem_out_dec = 6'b111111; + 12'd3974 : mem_out_dec = 6'b111111; + 12'd3975 : mem_out_dec = 6'b111111; + 12'd3976 : mem_out_dec = 6'b111111; + 12'd3977 : mem_out_dec = 6'b111111; + 12'd3978 : mem_out_dec = 6'b111111; + 12'd3979 : mem_out_dec = 6'b111111; + 12'd3980 : mem_out_dec = 6'b111111; + 12'd3981 : mem_out_dec = 6'b111111; + 12'd3982 : mem_out_dec = 6'b111111; + 12'd3983 : mem_out_dec = 6'b111111; + 12'd3984 : mem_out_dec = 6'b111111; + 12'd3985 : mem_out_dec = 6'b111111; + 12'd3986 : mem_out_dec = 6'b111111; + 12'd3987 : mem_out_dec = 6'b111111; + 12'd3988 : mem_out_dec = 6'b111111; + 12'd3989 : mem_out_dec = 6'b111111; + 12'd3990 : mem_out_dec = 6'b111111; + 12'd3991 : mem_out_dec = 6'b111111; + 12'd3992 : mem_out_dec = 6'b111111; + 12'd3993 : mem_out_dec = 6'b111111; + 12'd3994 : mem_out_dec = 6'b111111; + 12'd3995 : mem_out_dec = 6'b111111; + 12'd3996 : mem_out_dec = 6'b111111; + 12'd3997 : mem_out_dec = 6'b111111; + 12'd3998 : mem_out_dec = 6'b111111; + 12'd3999 : mem_out_dec = 6'b111111; + 12'd4000 : mem_out_dec = 6'b111111; + 12'd4001 : mem_out_dec = 6'b111111; + 12'd4002 : mem_out_dec = 6'b111111; + 12'd4003 : mem_out_dec = 6'b111111; + 12'd4004 : mem_out_dec = 6'b111111; + 12'd4005 : mem_out_dec = 6'b111111; + 12'd4006 : mem_out_dec = 6'b111111; + 12'd4007 : mem_out_dec = 6'b111111; + 12'd4008 : mem_out_dec = 6'b111111; + 12'd4009 : mem_out_dec = 6'b111111; + 12'd4010 : mem_out_dec = 6'b111111; + 12'd4011 : mem_out_dec = 6'b111111; + 12'd4012 : mem_out_dec = 6'b111111; + 12'd4013 : mem_out_dec = 6'b111111; + 12'd4014 : mem_out_dec = 6'b111111; + 12'd4015 : mem_out_dec = 6'b111111; + 12'd4016 : mem_out_dec = 6'b111111; + 12'd4017 : mem_out_dec = 6'b111111; + 12'd4018 : mem_out_dec = 6'b111111; + 12'd4019 : mem_out_dec = 6'b111111; + 12'd4020 : mem_out_dec = 6'b111111; + 12'd4021 : mem_out_dec = 6'b111111; + 12'd4022 : mem_out_dec = 6'b111111; + 12'd4023 : mem_out_dec = 6'b111111; + 12'd4024 : mem_out_dec = 6'b111111; + 12'd4025 : mem_out_dec = 6'b111111; + 12'd4026 : mem_out_dec = 6'b111111; + 12'd4027 : mem_out_dec = 6'b111111; + 12'd4028 : mem_out_dec = 6'b111111; + 12'd4029 : mem_out_dec = 6'b111111; + 12'd4030 : mem_out_dec = 6'b111111; + 12'd4031 : mem_out_dec = 6'b111111; + 12'd4032 : mem_out_dec = 6'b111111; + 12'd4033 : mem_out_dec = 6'b111111; + 12'd4034 : mem_out_dec = 6'b111111; + 12'd4035 : mem_out_dec = 6'b111111; + 12'd4036 : mem_out_dec = 6'b111111; + 12'd4037 : mem_out_dec = 6'b111111; + 12'd4038 : mem_out_dec = 6'b111111; + 12'd4039 : mem_out_dec = 6'b111111; + 12'd4040 : mem_out_dec = 6'b111111; + 12'd4041 : mem_out_dec = 6'b111111; + 12'd4042 : mem_out_dec = 6'b111111; + 12'd4043 : mem_out_dec = 6'b111111; + 12'd4044 : mem_out_dec = 6'b111111; + 12'd4045 : mem_out_dec = 6'b111111; + 12'd4046 : mem_out_dec = 6'b111111; + 12'd4047 : mem_out_dec = 6'b111111; + 12'd4048 : mem_out_dec = 6'b111111; + 12'd4049 : mem_out_dec = 6'b111111; + 12'd4050 : mem_out_dec = 6'b111111; + 12'd4051 : mem_out_dec = 6'b111111; + 12'd4052 : mem_out_dec = 6'b111111; + 12'd4053 : mem_out_dec = 6'b111111; + 12'd4054 : mem_out_dec = 6'b111111; + 12'd4055 : mem_out_dec = 6'b111111; + 12'd4056 : mem_out_dec = 6'b111111; + 12'd4057 : mem_out_dec = 6'b111111; + 12'd4058 : mem_out_dec = 6'b111111; + 12'd4059 : mem_out_dec = 6'b111111; + 12'd4060 : mem_out_dec = 6'b111111; + 12'd4061 : mem_out_dec = 6'b111111; + 12'd4062 : mem_out_dec = 6'b111111; + 12'd4063 : mem_out_dec = 6'b111111; + 12'd4064 : mem_out_dec = 6'b111111; + 12'd4065 : mem_out_dec = 6'b111111; + 12'd4066 : mem_out_dec = 6'b111111; + 12'd4067 : mem_out_dec = 6'b111111; + 12'd4068 : mem_out_dec = 6'b111111; + 12'd4069 : mem_out_dec = 6'b111111; + 12'd4070 : mem_out_dec = 6'b111111; + 12'd4071 : mem_out_dec = 6'b111111; + 12'd4072 : mem_out_dec = 6'b111111; + 12'd4073 : mem_out_dec = 6'b111111; + 12'd4074 : mem_out_dec = 6'b111111; + 12'd4075 : mem_out_dec = 6'b111111; + 12'd4076 : mem_out_dec = 6'b111111; + 12'd4077 : mem_out_dec = 6'b111111; + 12'd4078 : mem_out_dec = 6'b111111; + 12'd4079 : mem_out_dec = 6'b111111; + 12'd4080 : mem_out_dec = 6'b111111; + 12'd4081 : mem_out_dec = 6'b111111; + 12'd4082 : mem_out_dec = 6'b111111; + 12'd4083 : mem_out_dec = 6'b111111; + 12'd4084 : mem_out_dec = 6'b111111; + 12'd4085 : mem_out_dec = 6'b111111; + 12'd4086 : mem_out_dec = 6'b111111; + 12'd4087 : mem_out_dec = 6'b111111; + 12'd4088 : mem_out_dec = 6'b111111; + 12'd4089 : mem_out_dec = 6'b111111; + 12'd4090 : mem_out_dec = 6'b111111; + 12'd4091 : mem_out_dec = 6'b111111; + 12'd4092 : mem_out_dec = 6'b111111; + 12'd4093 : mem_out_dec = 6'b111111; + 12'd4094 : mem_out_dec = 6'b111111; + 12'd4095 : mem_out_dec = 6'b111111; + endcase + end + + always @ (posedge clk) begin + dec_cnt <= #TCQ mem_out_dec; + end +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_rdlvl.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_rdlvl.v new file mode 100644 index 0000000..04a4264 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_rdlvl.v @@ -0,0 +1,3380 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: +// \ \ Application: MIG +// / / Filename: ddr_phy_rdlvl.v +// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// Read leveling Stage1 calibration logic +// NOTES: +// 1. Window detection with PRBS pattern. +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $ +**$Date: 2011/06/24 14:49:00 $ +**$Author: mgeorge $ +**$Revision: 1.2 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_rdlvl.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + +(* use_dsp48 = "no" *) + +module mig_7series_v4_0_ddr_phy_rdlvl # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter nCK_PER_CLK = 2, // # of memory clocks per CLK + parameter CLK_PERIOD = 3333, // Internal clock period (in ps) + parameter DQ_WIDTH = 64, // # of DQ (data) + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter RANKS = 1, // # of DRAM ranks + parameter PER_BIT_DESKEW = "ON", // Enable per-bit DQ deskew + parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps + parameter DEBUG_PORT = "OFF", // Enable debug port + parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" + parameter OCAL_EN = "ON", + parameter IDELAY_ADJ = "ON", + parameter PI_DIV2_INCDEC = "TRUE" + ) + ( + input clk, + input rst, + // Calibration status, control signals + input mpr_rdlvl_start, + output mpr_rdlvl_done, + output reg mpr_last_byte_done, + output mpr_rnk_done, + input rdlvl_stg1_start, + output rdlvl_stg1_done /* synthesis syn_maxfan = 30 */, + output rdlvl_stg1_rnk_done, + output reg rdlvl_stg1_err, + output mpr_rdlvl_err, + output rdlvl_err, + output reg rdlvl_prech_req, + output rdlvl_last_byte_done, + output reg rdlvl_assrt_common, + input prech_done, + input phy_if_empty, + input [4:0] idelaye2_init_val, + // Captured data in fabric clock domain + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, + // Decrement initial Phaser_IN Fine tap delay + input dqs_po_dec_done, + input [5:0] pi_counter_read_val, + // Stage 1 calibration outputs + output reg pi_fine_dly_dec_done, + output reg pi_en_stg2_f, + output reg pi_stg2_f_incdec, + output reg pi_stg2_load, + output reg [5:0] pi_stg2_reg_l, + output [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt, + // To DQ IDELAY required to find left edge of + // valid window + output idelay_ce, + output idelay_inc, + input idelay_ld, + input [DQS_CNT_WIDTH:0] wrcal_cnt, + // Only output if Per-bit de-skew enabled + output reg [5*RANKS*DQ_WIDTH-1:0] dlyval_dq, + //output to prevent read during PI movement + output reg rdlvl_pi_incdec, + // Debug Port + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, + output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, + + input dbg_idel_up_all, + input dbg_idel_down_all, + input dbg_idel_up_cpt, + input dbg_idel_down_cpt, + input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, + input dbg_sel_all_idel_cpt, + output [255:0] dbg_phy_rdlvl + ); + + // minimum time (in IDELAY taps) for which capture data must be stable for + // algorithm to consider a valid data eye to be found. The read leveling + // logic will ignore any window found smaller than this value. Limitations + // on how small this number can be is determined by: (1) the algorithmic + // limitation of how many taps wide the data eye can be (3 taps), and (2) + // how wide regions of "instability" that occur around the edges of the + // read valid window can be (i.e. need to be able to filter out "false" + // windows that occur for a short # of taps around the edges of the true + // data window, although with multi-sampling during read leveling, this is + // not as much a concern) - the larger the value, the more protection + // against "false" windows + localparam MIN_EYE_SIZE = 16; + + // Length of calibration sequence (in # of words) + localparam CAL_PAT_LEN = 8; + // Read data shift register length + localparam RD_SHIFT_LEN = CAL_PAT_LEN / (2*nCK_PER_CLK); + + // # of cycles required to perform read data shift register compare + // This is defined as from the cycle the new data is loaded until + // signal found_edge_r is valid + localparam RD_SHIFT_COMP_DELAY = 5; + + // worst-case # of cycles to wait to ensure that both the SR and + // PREV_SR shift registers have valid data, and that the comparison + // of the two shift register values is valid. The "+1" at the end of + // this equation is a fudge factor, I freely admit that + localparam SR_VALID_DELAY = (2 * RD_SHIFT_LEN) + RD_SHIFT_COMP_DELAY + 1; + + // # of clock cycles to wait after changing tap value or read data MUX + // to allow: (1) tap chain to settle, (2) for delayed input to propagate + // thru ISERDES, (3) for the read data comparison logic to have time to + // output the comparison of two consecutive samples of the settled read data + // The minimum delay is 16 cycles, which should be good enough to handle all + // three of the above conditions for the simulation-only case with a short + // training pattern. For H/W (or for simulation with longer training + // pattern), it will take longer to store and compare two consecutive + // samples, and the value of this parameter will reflect that + // put the maximum number for 2:1 mode + localparam PIPE_WAIT_CNT = (nCK_PER_CLK == 2) ? 31 : (SR_VALID_DELAY < 8) ? 16 + : (SR_VALID_DELAY + 8); + + // # of read data samples to examine when detecting whether an edge has + // occured during stage 1 calibration. Width of local param must be + // changed as appropriate. Note that there are two counters used, each + // counter can be changed independently of the other - they are used in + // cascade to create a larger counter + localparam [11:0] DETECT_EDGE_SAMPLE_CNT0 = 12'h001; //12'hFFF; + localparam [11:0] DETECT_EDGE_SAMPLE_CNT1 = 12'h001; // 12'h1FF Must be > 0 + + localparam [5:0] CAL1_IDLE = 6'h00; + localparam [5:0] CAL1_NEW_DQS_WAIT = 6'h01; + localparam [5:0] CAL1_STORE_FIRST_WAIT = 6'h02; + localparam [5:0] CAL1_PAT_DETECT = 6'h03; + localparam [5:0] CAL1_DQ_IDEL_TAP_INC = 6'h04; + localparam [5:0] CAL1_DQ_IDEL_TAP_INC_WAIT = 6'h05; + localparam [5:0] CAL1_DQ_IDEL_TAP_DEC = 6'h06; + localparam [5:0] CAL1_DQ_IDEL_TAP_DEC_WAIT = 6'h07; + localparam [5:0] CAL1_DETECT_EDGE = 6'h08; + localparam [5:0] CAL1_IDEL_INC_CPT = 6'h09; + localparam [5:0] CAL1_IDEL_INC_CPT_WAIT = 6'h0A; + localparam [5:0] CAL1_CALC_IDEL = 6'h0B; + localparam [5:0] CAL1_IDEL_DEC_CPT = 6'h0C; + localparam [5:0] CAL1_IDEL_DEC_CPT_WAIT = 6'h0D; + localparam [5:0] CAL1_NEXT_DQS = 6'h0E; + localparam [5:0] CAL1_DONE = 6'h0F; + localparam [5:0] CAL1_PB_STORE_FIRST_WAIT = 6'h10; + localparam [5:0] CAL1_PB_DETECT_EDGE = 6'h11; + localparam [5:0] CAL1_PB_INC_CPT = 6'h12; + localparam [5:0] CAL1_PB_INC_CPT_WAIT = 6'h13; + localparam [5:0] CAL1_PB_DEC_CPT_LEFT = 6'h14; + localparam [5:0] CAL1_PB_DEC_CPT_LEFT_WAIT = 6'h15; + localparam [5:0] CAL1_PB_DETECT_EDGE_DQ = 6'h16; + localparam [5:0] CAL1_PB_INC_DQ = 6'h17; + localparam [5:0] CAL1_PB_INC_DQ_WAIT = 6'h18; + localparam [5:0] CAL1_PB_DEC_CPT = 6'h19; + localparam [5:0] CAL1_PB_DEC_CPT_WAIT = 6'h1A; + localparam [5:0] CAL1_REGL_LOAD = 6'h1B; + localparam [5:0] CAL1_RDLVL_ERR = 6'h1C; + localparam [5:0] CAL1_MPR_NEW_DQS_WAIT = 6'h1D; + localparam [5:0] CAL1_VALID_WAIT = 6'h1E; + localparam [5:0] CAL1_MPR_PAT_DETECT = 6'h1F; + localparam [5:0] CAL1_NEW_DQS_PREWAIT = 6'h20; + localparam [5:0] CAL1_RD_STOP_FOR_PI_INC = 6'h21; + localparam [5:0] CAL1_CENTER_WAIT = 6'h22; + + integer a; + integer b; + integer d; + integer e; + integer f; + integer h; + integer g; + integer i; + integer j; + integer k; + integer l; + integer m; + integer n; + integer r; + integer p; + integer q; + integer s; + integer t; + integer u; + integer w; + integer ce_i; + integer ce_rnk_i; + integer aa; + integer bb; + integer cc; + integer dd; + genvar x; + genvar z; + + reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_r; + wire [DQS_CNT_WIDTH+2:0]cal1_cnt_cpt_timing; + reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_timing_r; + reg cal1_dq_idel_ce; + reg cal1_dq_idel_inc; + reg cal1_dlyce_cpt_r; + reg cal1_dlyinc_cpt_r; + reg cal1_dlyce_dq_r; + reg cal1_dlyinc_dq_r; + reg cal1_wait_cnt_en_r; + reg [4:0] cal1_wait_cnt_r; + reg cal1_wait_r; + reg [DQ_WIDTH-1:0] dlyce_dq_r; + reg dlyinc_dq_r; + reg [4:0] dlyval_dq_reg_r [0:RANKS-1][0:DQ_WIDTH-1]; + reg cal1_prech_req_r; + reg [5:0] cal1_state_r; + reg [5:0] cal1_state_r1; + reg [5:0] cal1_state_r2; + reg [5:0] cal1_state_r3; + reg [5:0] cnt_idel_dec_cpt_r; + reg [3:0] cnt_shift_r; + reg detect_edge_done_r; + reg [5:0] right_edge_taps_r; + reg [5:0] first_edge_taps_r; + reg found_edge_r; + reg found_first_edge_r; + reg found_second_edge_r; + reg found_stable_eye_r; + reg found_stable_eye_last_r; + reg found_edge_all_r; + reg [5:0] tap_cnt_cpt_r; + reg tap_limit_cpt_r; + reg [4:0] idel_tap_cnt_dq_pb_r; + reg idel_tap_limit_dq_pb_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; + reg mux_rd_valid_r; + reg new_cnt_cpt_r; + reg [RD_SHIFT_LEN-1:0] old_sr_fall0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_fall1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_rise0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_rise1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_fall2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_fall3_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_rise2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_rise3_r [DRAM_WIDTH-1:0]; + reg [DRAM_WIDTH-1:0] old_sr_match_fall0_r; + reg [DRAM_WIDTH-1:0] old_sr_match_fall1_r; + reg [DRAM_WIDTH-1:0] old_sr_match_rise0_r; + reg [DRAM_WIDTH-1:0] old_sr_match_rise1_r; + reg [DRAM_WIDTH-1:0] old_sr_match_fall2_r; + reg [DRAM_WIDTH-1:0] old_sr_match_fall3_r; + reg [DRAM_WIDTH-1:0] old_sr_match_rise2_r; + reg [DRAM_WIDTH-1:0] old_sr_match_rise3_r; + reg [4:0] pb_cnt_eye_size_r [DRAM_WIDTH-1:0]; + reg [DRAM_WIDTH-1:0] pb_detect_edge_done_r; + reg [DRAM_WIDTH-1:0] pb_found_edge_last_r; + reg [DRAM_WIDTH-1:0] pb_found_edge_r; + reg [DRAM_WIDTH-1:0] pb_found_first_edge_r; + reg [DRAM_WIDTH-1:0] pb_found_stable_eye_r; + reg [DRAM_WIDTH-1:0] pb_last_tap_jitter_r; + reg pi_en_stg2_f_timing; + reg pi_stg2_f_incdec_timing; + reg pi_stg2_load_timing; + reg [5:0] pi_stg2_reg_l_timing; + reg [DRAM_WIDTH-1:0] prev_sr_diff_r; + reg [RD_SHIFT_LEN-1:0] prev_sr_fall0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_fall1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_rise0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_rise1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_fall2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_fall3_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_rise2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_rise3_r [DRAM_WIDTH-1:0]; + reg [DRAM_WIDTH-1:0] prev_sr_match_cyc2_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_fall0_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_fall1_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_rise0_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_rise1_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_fall2_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_fall3_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_rise2_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_rise3_r; + wire [DQ_WIDTH-1:0] rd_data_rise0; + wire [DQ_WIDTH-1:0] rd_data_fall0; + wire [DQ_WIDTH-1:0] rd_data_rise1; + wire [DQ_WIDTH-1:0] rd_data_fall1; + wire [DQ_WIDTH-1:0] rd_data_rise2; + wire [DQ_WIDTH-1:0] rd_data_fall2; + wire [DQ_WIDTH-1:0] rd_data_rise3; + wire [DQ_WIDTH-1:0] rd_data_fall3; + reg samp_cnt_done_r; + reg samp_edge_cnt0_en_r; + reg [11:0] samp_edge_cnt0_r; + reg samp_edge_cnt1_en_r; + reg [11:0] samp_edge_cnt1_r; + reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; + reg [5:0] second_edge_taps_r; + reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; + reg store_sr_r; + reg store_sr_req_pulsed_r; + reg store_sr_req_r; + reg sr_valid_r; + reg sr_valid_r1; + reg sr_valid_r2; + reg [DRAM_WIDTH-1:0] old_sr_diff_r; + reg [DRAM_WIDTH-1:0] old_sr_match_cyc2_r; + reg pat0_data_match_r; + reg pat1_data_match_r; + wire pat_data_match_r; + wire [RD_SHIFT_LEN-1:0] pat0_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat0_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat0_fall2 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat0_fall3 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_fall2 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_fall3 [3:0]; + reg [DRAM_WIDTH-1:0] pat0_match_fall0_r; + reg pat0_match_fall0_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_fall1_r; + reg pat0_match_fall1_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_fall2_r; + reg pat0_match_fall2_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_fall3_r; + reg pat0_match_fall3_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_rise0_r; + reg pat0_match_rise0_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_rise1_r; + reg pat0_match_rise1_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_rise2_r; + reg pat0_match_rise2_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_rise3_r; + reg pat0_match_rise3_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; + reg pat1_match_fall0_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; + reg pat1_match_fall1_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_fall2_r; + reg pat1_match_fall2_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_fall3_r; + reg pat1_match_fall3_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; + reg pat1_match_rise0_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; + reg pat1_match_rise1_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_rise2_r; + reg pat1_match_rise2_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_rise3_r; + reg pat1_match_rise3_and_r; + reg [4:0] idelay_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; + reg [5*DQS_WIDTH*RANKS-1:0] idelay_tap_cnt_w; + reg [4:0] idelay_tap_cnt_slice_r; + reg idelay_tap_limit_r; + + wire [RD_SHIFT_LEN-1:0] pat0_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat0_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat0_rise2 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat0_rise3 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_rise2 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_rise3 [3:0]; + + wire [RD_SHIFT_LEN-1:0] idel_pat0_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_rise2 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_fall2 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_rise3 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_fall3 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_rise2 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_fall2 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_rise3 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_fall3 [3:0]; + + reg [DRAM_WIDTH-1:0] idel_pat0_match_rise0_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_fall0_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_rise1_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_fall1_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_rise2_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_fall2_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_rise3_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_fall3_r; + + reg [DRAM_WIDTH-1:0] idel_pat1_match_rise0_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_fall0_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_rise1_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_fall1_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_rise2_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_fall2_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_rise3_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_fall3_r; + + reg idel_pat0_match_rise0_and_r; + reg idel_pat0_match_fall0_and_r; + reg idel_pat0_match_rise1_and_r; + reg idel_pat0_match_fall1_and_r; + reg idel_pat0_match_rise2_and_r; + reg idel_pat0_match_fall2_and_r; + reg idel_pat0_match_rise3_and_r; + reg idel_pat0_match_fall3_and_r; + + reg idel_pat1_match_rise0_and_r; + reg idel_pat1_match_fall0_and_r; + reg idel_pat1_match_rise1_and_r; + reg idel_pat1_match_fall1_and_r; + reg idel_pat1_match_rise2_and_r; + reg idel_pat1_match_fall2_and_r; + reg idel_pat1_match_rise3_and_r; + reg idel_pat1_match_fall3_and_r; + + reg idel_pat0_data_match_r; + reg idel_pat1_data_match_r; + + reg idel_pat_data_match; + reg idel_pat_data_match_r; + + reg [4:0] idel_dec_cnt; + + reg [5:0] rdlvl_dqs_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; + reg [1:0] rnk_cnt_r; + reg rdlvl_rank_done_r; + + reg [3:0] done_cnt; + reg [1:0] regl_rank_cnt; + reg [DQS_CNT_WIDTH:0] regl_dqs_cnt; + reg [DQS_CNT_WIDTH:0] regl_dqs_cnt_r; + wire [DQS_CNT_WIDTH+2:0]regl_dqs_cnt_timing; + reg regl_rank_done_r; + reg rdlvl_stg1_start_r; + + reg dqs_po_dec_done_r1; + reg dqs_po_dec_done_r2; + reg fine_dly_dec_done_r1; + reg fine_dly_dec_done_r2; + reg fine_dly_dec_done_r3; + reg fine_dly_dec_done_r4; + reg [3:0] wait_cnt_r; + reg [5:0] pi_rdval_cnt; + reg pi_cnt_dec; + + reg mpr_valid_r; + reg mpr_valid_r1; + reg mpr_valid_r2; + reg mpr_rd_rise0_prev_r; + reg mpr_rd_fall0_prev_r; + reg mpr_rd_rise1_prev_r; + reg mpr_rd_fall1_prev_r; + reg mpr_rd_rise2_prev_r; + reg mpr_rd_fall2_prev_r; + reg mpr_rd_rise3_prev_r; + reg mpr_rd_fall3_prev_r; + reg mpr_rdlvl_done_r; + reg mpr_rdlvl_done_r1; + reg mpr_rdlvl_done_r2; + reg mpr_rdlvl_start_r; + reg mpr_rank_done_r; + reg [2:0] stable_idel_cnt; + reg inhibit_edge_detect_r; + reg idel_pat_detect_valid_r; + reg idel_mpr_pat_detect_r; + reg mpr_pat_detect_r; + reg mpr_dec_cpt_r; + reg idel_adj_inc; //IDELAY adjustment + wire [1:0] idelay_adj; + wire pb_detect_edge_setup; + wire pb_detect_edge; + // Debug + reg [6*DQS_WIDTH-1:0] dbg_cpt_first_edge_taps; + reg [6*DQS_WIDTH-1:0] dbg_cpt_second_edge_taps; + reg [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt_w; + reg rdlvl_stg1_done_int; + reg rdlvl_stg1_done_int_r1, rdlvl_stg1_done_int_r2, rdlvl_stg1_done_int_r3; + reg rdlvl_last_byte_done_int; + reg rdlvl_last_byte_done_int_r1, rdlvl_last_byte_done_int_r2, rdlvl_last_byte_done_int_r3; + + + //IDELAY adjustment setting for -1 + //2'b10 : IDELAY - 1 + //2'b01 : IDELAY + 1 + //2'b00 : No IDELAY adjustment + assign idelay_adj = (IDELAY_ADJ == "ON") ? 2'b10: 2'b00; + + //*************************************************************************** + // Debug + //*************************************************************************** + + always @(*) begin + for (d = 0; d < RANKS; d = d + 1) begin + for (e = 0; e < DQS_WIDTH; e = e + 1) begin + idelay_tap_cnt_w[(5*e+5*DQS_WIDTH*d)+:5] = idelay_tap_cnt_r[d][e]; + dbg_cpt_tap_cnt_w[(6*e+6*DQS_WIDTH*d)+:6] = rdlvl_dqs_tap_cnt_r[d][e]; + end + end + end + + assign mpr_rdlvl_err = rdlvl_stg1_err & (!mpr_rdlvl_done); + assign rdlvl_err = rdlvl_stg1_err & (mpr_rdlvl_done); + + + assign dbg_phy_rdlvl[0] = rdlvl_stg1_start; + assign dbg_phy_rdlvl[1] = pat_data_match_r; + assign dbg_phy_rdlvl[2] = mux_rd_valid_r; + assign dbg_phy_rdlvl[3] = idelay_tap_limit_r; + assign dbg_phy_rdlvl[8:4] = 'b0; + assign dbg_phy_rdlvl[14:9] = cal1_state_r[5:0]; + assign dbg_phy_rdlvl[20:15] = cnt_idel_dec_cpt_r; + assign dbg_phy_rdlvl[21] = found_first_edge_r; + assign dbg_phy_rdlvl[22] = found_second_edge_r; + assign dbg_phy_rdlvl[23] = found_edge_r; + assign dbg_phy_rdlvl[24] = store_sr_r; + // [40:25] previously used for sr, old_sr shift registers. If connecting + // these signals again, don't forget to parameterize based on RD_SHIFT_LEN + assign dbg_phy_rdlvl[40:25] = 'b0; + assign dbg_phy_rdlvl[41] = sr_valid_r; + assign dbg_phy_rdlvl[42] = found_stable_eye_r; + assign dbg_phy_rdlvl[48:43] = tap_cnt_cpt_r; + assign dbg_phy_rdlvl[54:49] = first_edge_taps_r; + assign dbg_phy_rdlvl[60:55] = second_edge_taps_r; + assign dbg_phy_rdlvl[64:61] = cal1_cnt_cpt_timing_r; + assign dbg_phy_rdlvl[65] = cal1_dlyce_cpt_r; + assign dbg_phy_rdlvl[66] = cal1_dlyinc_cpt_r; + assign dbg_phy_rdlvl[67] = found_edge_r; + assign dbg_phy_rdlvl[68] = found_first_edge_r; + assign dbg_phy_rdlvl[73:69] = 'b0; + assign dbg_phy_rdlvl[74] = idel_pat_data_match; + assign dbg_phy_rdlvl[75] = idel_pat0_data_match_r; + assign dbg_phy_rdlvl[76] = idel_pat1_data_match_r; + assign dbg_phy_rdlvl[77] = pat0_data_match_r; + assign dbg_phy_rdlvl[78] = pat1_data_match_r; + assign dbg_phy_rdlvl[79+:5*DQS_WIDTH*RANKS] = idelay_tap_cnt_w; + assign dbg_phy_rdlvl[170+:8] = mux_rd_rise0_r; + assign dbg_phy_rdlvl[178+:8] = mux_rd_fall0_r; + assign dbg_phy_rdlvl[186+:8] = mux_rd_rise1_r; + assign dbg_phy_rdlvl[194+:8] = mux_rd_fall1_r; + assign dbg_phy_rdlvl[202+:8] = mux_rd_rise2_r; + assign dbg_phy_rdlvl[210+:8] = mux_rd_fall2_r; + assign dbg_phy_rdlvl[218+:8] = mux_rd_rise3_r; + assign dbg_phy_rdlvl[226+:8] = mux_rd_fall3_r; + + //*************************************************************************** + // Debug output + //*************************************************************************** + + // CPT taps + assign dbg_cpt_first_edge_cnt = dbg_cpt_first_edge_taps; + assign dbg_cpt_second_edge_cnt = dbg_cpt_second_edge_taps; + assign dbg_cpt_tap_cnt = dbg_cpt_tap_cnt_w; + assign dbg_dq_idelay_tap_cnt = idelay_tap_cnt_w; + + // Record first and second edges found during CPT calibration + + generate + always @(posedge clk) + if (rst || (rdlvl_stg1_start && ~rdlvl_stg1_start_r)) begin + dbg_cpt_first_edge_taps <= #TCQ 'b0; + dbg_cpt_second_edge_taps <= #TCQ 'b0; + end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_CALC_IDEL)) begin + //for (ce_rnk_i = 0; ce_rnk_i < RANKS; ce_rnk_i = ce_rnk_i + 1) begin: gen_dbg_cpt_rnk + for (ce_i = 0; ce_i < DQS_WIDTH; ce_i = ce_i + 1) begin: gen_dbg_cpt_edge + if (found_first_edge_r) + dbg_cpt_first_edge_taps[(6*ce_i)+:6] + <= #TCQ first_edge_taps_r; + if (found_second_edge_r) + dbg_cpt_second_edge_taps[(6*ce_i)+:6] + <= #TCQ second_edge_taps_r; + end + //end + end else if (cal1_state_r == CAL1_CALC_IDEL) begin + // Record tap counts of first and second edge edges during + // CPT calibration for each DQS group. If neither edge has + // been found, then those taps will remain 0 + if (found_first_edge_r) + dbg_cpt_first_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] + <= #TCQ first_edge_taps_r; + if (found_second_edge_r) + dbg_cpt_second_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] + <= #TCQ second_edge_taps_r; + end + endgenerate + + assign rdlvl_stg1_rnk_done = rdlvl_rank_done_r;// || regl_rank_done_r; + assign mpr_rnk_done = mpr_rank_done_r; + assign mpr_rdlvl_done = ((DRAM_TYPE == "DDR3") && (OCAL_EN == "ON")) ? //&& (SIM_CAL_OPTION == "NONE") + mpr_rdlvl_done_r : 1'b1; + + //************************************************************************** + // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 + // coarse delay + //************************************************************************** + assign pi_stg2_rdlvl_cnt = (((PI_DIV2_INCDEC == "TRUE") && (cal1_state_r3 == CAL1_REGL_LOAD)) || ((PI_DIV2_INCDEC == "FALSE") && (cal1_state_r == CAL1_REGL_LOAD))) ? regl_dqs_cnt_r : cal1_cnt_cpt_r; + assign rdlvl_stg1_done = (PI_DIV2_INCDEC == "TRUE") ? rdlvl_stg1_done_int_r3 : rdlvl_stg1_done_int; + assign rdlvl_last_byte_done = (PI_DIV2_INCDEC == "TRUE") ? rdlvl_last_byte_done_int_r3 : rdlvl_last_byte_done_int; + + always @ (posedge clk) begin + rdlvl_stg1_done_int_r1 <= #TCQ rdlvl_stg1_done_int; + rdlvl_stg1_done_int_r2 <= #TCQ rdlvl_stg1_done_int_r1; + rdlvl_stg1_done_int_r3 <= #TCQ rdlvl_stg1_done_int_r2; + rdlvl_last_byte_done_int_r1 <= #TCQ rdlvl_last_byte_done_int; + rdlvl_last_byte_done_int_r2 <= #TCQ rdlvl_last_byte_done_int_r1; + rdlvl_last_byte_done_int_r3 <= #TCQ rdlvl_last_byte_done_int_r2; + end + + assign idelay_ce = cal1_dq_idel_ce; + assign idelay_inc = cal1_dq_idel_inc; + + //*************************************************************************** + // Assert calib_in_common in FAST_CAL mode for IDELAY tap increments to all + // DQs simultaneously + //*************************************************************************** + + always @(posedge clk) begin + if (rst) + rdlvl_assrt_common <= #TCQ 1'b0; + else if ((SIM_CAL_OPTION == "FAST_CAL") & rdlvl_stg1_start & + !rdlvl_stg1_start_r) + rdlvl_assrt_common <= #TCQ 1'b1; + else if (!idel_pat_data_match_r & idel_pat_data_match) + rdlvl_assrt_common <= #TCQ 1'b0; + end + + //*************************************************************************** + // Data mux to route appropriate bit to calibration logic - i.e. calibration + // is done sequentially, one bit (or DQS group) at a time + //*************************************************************************** + + generate + if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk + assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; + assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; + assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; + assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; + assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; + end else begin: rd_data_div2_logic_clk + assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; + assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + end + endgenerate + + always @(posedge clk) begin + rd_mux_sel_r <= #TCQ cal1_cnt_cpt_r; + end + + // Register outputs for improved timing. + // NOTE: Will need to change when per-bit DQ deskew is supported. + // Currenly all bits in DQS group are checked in aggregate + generate + genvar mux_i; + for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd + always @(posedge clk) begin + mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + end + end + endgenerate + + //*************************************************************************** + // MPR Read Leveling + //*************************************************************************** + + // storing the previous read data for checking later. Only bit 0 is used + // since MPR contents (01010101) are available generally on DQ[0] per + // JEDEC spec. + always @(posedge clk)begin + if ((cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || + ((cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r)))begin + mpr_rd_rise0_prev_r <= #TCQ mux_rd_rise0_r[0]; + mpr_rd_fall0_prev_r <= #TCQ mux_rd_fall0_r[0]; + mpr_rd_rise1_prev_r <= #TCQ mux_rd_rise1_r[0]; + mpr_rd_fall1_prev_r <= #TCQ mux_rd_fall1_r[0]; + mpr_rd_rise2_prev_r <= #TCQ mux_rd_rise2_r[0]; + mpr_rd_fall2_prev_r <= #TCQ mux_rd_fall2_r[0]; + mpr_rd_rise3_prev_r <= #TCQ mux_rd_rise3_r[0]; + mpr_rd_fall3_prev_r <= #TCQ mux_rd_fall3_r[0]; + end + end + + generate + if (nCK_PER_CLK == 4) begin: mpr_4to1 + // changed stable count of 2 IDELAY taps at 78 ps resolution + always @(posedge clk) begin + if (rst | (cal1_state_r == CAL1_NEW_DQS_PREWAIT) | + //(cal1_state_r == CAL1_DETECT_EDGE) | + (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | + (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | + (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | + (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) | + (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) | + (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) | + (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) | + (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0])) + stable_idel_cnt <= #TCQ 3'd0; + else if ((|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) & + ((cal1_state_r == CAL1_MPR_PAT_DETECT) & + (idel_pat_detect_valid_r))) begin + if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & + (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & + (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & + (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & + (mpr_rd_rise2_prev_r == mux_rd_rise2_r[0]) & + (mpr_rd_fall2_prev_r == mux_rd_fall2_r[0]) & + (mpr_rd_rise3_prev_r == mux_rd_rise3_r[0]) & + (mpr_rd_fall3_prev_r == mux_rd_fall3_r[0]) & + (stable_idel_cnt < 3'd2)) + stable_idel_cnt <= #TCQ stable_idel_cnt + 1; + end + end + + always @(posedge clk) begin + if (rst | + (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & + mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & + mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & + mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r)) + inhibit_edge_detect_r <= 1'b1; + // Wait for settling time after idelay tap increment before + // de-asserting inhibit_edge_detect_r + else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & + (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & + (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & + ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & + ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & + ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r)) + inhibit_edge_detect_r <= 1'b0; + end + + //checking for transition from 01010101 to 10101010 + always @(posedge clk)begin + if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | + inhibit_edge_detect_r) + idel_mpr_pat_detect_r <= #TCQ 1'b0; + // 10101010 is not the correct pattern + else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & + mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & + mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & + mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r) || + ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) + && (idel_pat_detect_valid_r))) + //|| (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) + idel_mpr_pat_detect_r <= #TCQ 1'b0; + // 01010101 to 10101010 is the correct transition + else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & + ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & + ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & + ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r) & + (stable_idel_cnt == 3'd2) & + ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || + (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || + (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || + (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) || + (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) || + (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) || + (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) || + (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0]))) + idel_mpr_pat_detect_r <= #TCQ 1'b1; + end + end else if (nCK_PER_CLK == 2) begin: mpr_2to1 + // changed stable count of 2 IDELAY taps at 78 ps resolution + always @(posedge clk) begin + if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | + (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | + (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | + (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | + (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0])) + stable_idel_cnt <= #TCQ 3'd0; + else if ((idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd0) & + ((cal1_state_r == CAL1_MPR_PAT_DETECT) & + (idel_pat_detect_valid_r))) begin + if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & + (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & + (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & + (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & + (stable_idel_cnt < 3'd2)) + stable_idel_cnt <= #TCQ stable_idel_cnt + 1; + end + end + + always @(posedge clk) begin + if (rst | + (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & + mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r)) + inhibit_edge_detect_r <= 1'b1; + else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & + (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & + (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & + ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r)) + inhibit_edge_detect_r <= 1'b0; + end + + //checking for transition from 01010101 to 10101010 + always @(posedge clk)begin + if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | + inhibit_edge_detect_r) + idel_mpr_pat_detect_r <= #TCQ 1'b0; + // 1010 is not the correct pattern + else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & + mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r) || + ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) + & (idel_pat_detect_valid_r))) + // ||(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) + idel_mpr_pat_detect_r <= #TCQ 1'b0; + // 0101 to 1010 is the correct transition + else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & + ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r) & + (stable_idel_cnt == 3'd2) & + ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || + (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || + (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || + (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]))) + idel_mpr_pat_detect_r <= #TCQ 1'b1; + end + end + endgenerate + + + + // Registered signal indicates when mux_rd_rise/fall_r is valid + always @(posedge clk) + mux_rd_valid_r <= #TCQ ~phy_if_empty; + + + //*************************************************************************** + // Decrement initial Phaser_IN fine delay value before proceeding with + // read calibration + //*************************************************************************** + + always @(posedge clk) begin + dqs_po_dec_done_r1 <= #TCQ dqs_po_dec_done; + dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1; + fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1; + fine_dly_dec_done_r3 <= #TCQ fine_dly_dec_done_r2; + fine_dly_dec_done_r4 <= #TCQ fine_dly_dec_done_r3; + if (PI_DIV2_INCDEC == "TRUE") + pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r4; + else + pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r2; + end + + always @(posedge clk) begin + if (rst || pi_cnt_dec) + wait_cnt_r <= #TCQ 'd8; + else if (dqs_po_dec_done_r2 && (wait_cnt_r > 'd0)) + wait_cnt_r <= #TCQ wait_cnt_r - 1; + end + + always @(posedge clk) begin + if (rst) begin + pi_rdval_cnt <= #TCQ 'd0; + end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin + pi_rdval_cnt <= #TCQ pi_counter_read_val; + end else if (pi_rdval_cnt > 'd0) begin + if (pi_cnt_dec) + pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1; + else + pi_rdval_cnt <= #TCQ pi_rdval_cnt; + end else if (pi_rdval_cnt == 'd0) begin + pi_rdval_cnt <= #TCQ pi_rdval_cnt; + end + end + + always @(posedge clk) begin + if (rst || (pi_rdval_cnt == 'd0)) + pi_cnt_dec <= #TCQ 1'b0; + else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0) + && (wait_cnt_r == 'd1)) + pi_cnt_dec <= #TCQ 1'b1; + else + pi_cnt_dec <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst) begin + fine_dly_dec_done_r1 <= #TCQ 1'b0; + end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) || + (dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin + fine_dly_dec_done_r1 <= #TCQ 1'b1; + end + end + + //*************************************************************************** + // Demultiplexor to control Phaser_IN delay values + //*************************************************************************** + + // Read DQS + always @(posedge clk) begin + if (rst) begin + pi_en_stg2_f_timing <= #TCQ 'b0; + pi_stg2_f_incdec_timing <= #TCQ 'b0; + end else if (pi_cnt_dec) begin + pi_en_stg2_f_timing <= #TCQ 'b1; + pi_stg2_f_incdec_timing <= #TCQ 'b0; + end else if (cal1_dlyce_cpt_r) begin + if ((SIM_CAL_OPTION == "NONE") || + (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin + // Change only specified DQS + pi_en_stg2_f_timing <= #TCQ 1'b1; + pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; + end else if (SIM_CAL_OPTION == "FAST_CAL") begin + // if simulating, and "shortcuts" for calibration enabled, apply + // results to all DQSs (i.e. assume same delay on all + // DQSs). + pi_en_stg2_f_timing <= #TCQ 1'b1; + pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; + end + end else begin + pi_en_stg2_f_timing <= #TCQ 'b0; + pi_stg2_f_incdec_timing <= #TCQ 'b0; + end + end + + // registered for timing + always @(posedge clk) begin + pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing; + pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing; + end + + // This counter used to implement settling time between + // Phaser_IN rank register loads to different DQSs + always @(posedge clk) begin + if (rst) + done_cnt <= #TCQ 'b0; + else if (((cal1_state_r == CAL1_REGL_LOAD) && + (cal1_state_r1 == CAL1_NEXT_DQS)) || + ((done_cnt == 4'd1) && (cal1_state_r != CAL1_DONE))) + done_cnt <= #TCQ 4'b1010; + else if (done_cnt > 'b0) + done_cnt <= #TCQ done_cnt - 1; + end + + // During rank register loading the rank count must be sent to + // Phaser_IN via the phy_ctl_wd?? If so phy_init will have to + // issue NOPs during rank register loading with the appropriate + // rank count + always @(posedge clk) begin + if (rst || (regl_rank_done_r == 1'b1)) + regl_rank_done_r <= #TCQ 1'b0; + else if ((regl_dqs_cnt == DQS_WIDTH-1) && + (regl_rank_cnt != RANKS-1) && + (done_cnt == 4'd1)) + regl_rank_done_r <= #TCQ 1'b1; + end + + // Temp wire for timing. + // The following in the always block below causes timing issues + // due to DSP block inference + // 6*regl_dqs_cnt. + // replacing this with two left shifts + 1 left shift to avoid + // DSP multiplier. + assign regl_dqs_cnt_timing = {2'd0, regl_dqs_cnt}; + + // Load Phaser_OUT rank register with rdlvl delay value + // for each DQS per rank. + always @(posedge clk) begin + if (rst || (done_cnt == 4'd0)) begin + pi_stg2_load_timing <= #TCQ 'b0; + pi_stg2_reg_l_timing <= #TCQ 'b0; + end else if ((cal1_state_r == CAL1_REGL_LOAD) && + (regl_dqs_cnt <= DQS_WIDTH-1) && (done_cnt == 4'd1)) begin + pi_stg2_load_timing <= #TCQ 'b1; + pi_stg2_reg_l_timing <= #TCQ + rdlvl_dqs_tap_cnt_r[rnk_cnt_r][regl_dqs_cnt]; + end else begin + pi_stg2_load_timing <= #TCQ 'b0; + pi_stg2_reg_l_timing <= #TCQ 'b0; + end + end + + // registered for timing + always @(posedge clk) begin + pi_stg2_load <= #TCQ pi_stg2_load_timing; + pi_stg2_reg_l <= #TCQ pi_stg2_reg_l_timing; + end + + always @(posedge clk) begin + if (rst || (done_cnt == 4'd0) || + (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) + regl_rank_cnt <= #TCQ 2'b00; + else if ((cal1_state_r == CAL1_REGL_LOAD) && + (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin + if (regl_rank_cnt == RANKS-1) + regl_rank_cnt <= #TCQ regl_rank_cnt; + else + regl_rank_cnt <= #TCQ regl_rank_cnt + 1; + end + end + + always @(posedge clk) begin + if (rst || (done_cnt == 4'd0) || + (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) + regl_dqs_cnt <= #TCQ {DQS_CNT_WIDTH+1{1'b0}}; + else if ((cal1_state_r == CAL1_REGL_LOAD) && + (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin + if (regl_rank_cnt == RANKS-1) + regl_dqs_cnt <= #TCQ regl_dqs_cnt; + else + regl_dqs_cnt <= #TCQ 'b0; + end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt != DQS_WIDTH-1) + && (done_cnt == 4'd1)) + regl_dqs_cnt <= #TCQ regl_dqs_cnt + 1; + else + regl_dqs_cnt <= #TCQ regl_dqs_cnt; + end + + + always @(posedge clk) + regl_dqs_cnt_r <= #TCQ regl_dqs_cnt; + //***************************************************************** + // DQ Stage 1 CALIBRATION INCREMENT/DECREMENT LOGIC: + // The actual IDELAY elements for each of the DQ bits is set via the + // DLYVAL parallel load port. However, the stage 1 calibration + // algorithm (well most of it) only needs to increment or decrement the DQ + // IDELAY value by 1 at any one time. + //***************************************************************** + + // Chip-select generation for each of the individual counters tracking + // IDELAY tap values for each DQ + generate + for (z = 0; z < DQS_WIDTH; z = z + 1) begin: gen_dlyce_dq + always @(posedge clk) + if (rst) + dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; + else + if (SIM_CAL_OPTION == "SKIP_CAL") + // If skipping calibration altogether (only for simulation), no + // need to set DQ IODELAY values - they are hardcoded + dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; + else if (SIM_CAL_OPTION == "FAST_CAL") begin + // If fast calibration option (simulation only) selected, DQ + // IODELAYs across all bytes are updated simultaneously + // (although per-bit deskew within DQS[0] is still supported) + for (h = 0; h < DRAM_WIDTH; h = h + 1) begin + dlyce_dq_r[DRAM_WIDTH*z + h] <= #TCQ cal1_dlyce_dq_r; + end + end else if ((SIM_CAL_OPTION == "NONE") || + (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin + if (cal1_cnt_cpt_r == z) begin + for (g = 0; g < DRAM_WIDTH; g = g + 1) begin + dlyce_dq_r[DRAM_WIDTH*z + g] + <= #TCQ cal1_dlyce_dq_r; + end + end else + dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; + end + end + endgenerate + + // Also delay increment/decrement control to match delay on DLYCE + always @(posedge clk) + if (rst) + dlyinc_dq_r <= #TCQ 1'b0; + else + dlyinc_dq_r <= #TCQ cal1_dlyinc_dq_r; + + + // Each DQ has a counter associated with it to record current read-leveling + // delay value + always @(posedge clk) + // Reset or skipping calibration all together + if (rst | (SIM_CAL_OPTION == "SKIP_CAL")) begin + for (aa = 0; aa < RANKS; aa = aa + 1) begin: rst_dlyval_dq_reg_r + for (bb = 0; bb < DQ_WIDTH; bb = bb + 1) + dlyval_dq_reg_r[aa][bb] <= #TCQ 'b0; + end + end else if (SIM_CAL_OPTION == "FAST_CAL") begin + for (n = 0; n < RANKS; n = n + 1) begin: gen_dlyval_dq_reg_rnk + for (r = 0; r < DQ_WIDTH; r = r + 1) begin: gen_dlyval_dq_reg + if (dlyce_dq_r[r]) begin + if (dlyinc_dq_r) + dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] + 5'h01; + else + dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] - 5'h01; + end + end + end + end else begin + if (dlyce_dq_r[cal1_cnt_cpt_r]) begin + if (dlyinc_dq_r) + dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ + dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] + 5'h01; + else + dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ + dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] - 5'h01; + end + end + + // Register for timing (help with logic placement) + always @(posedge clk) begin + for (cc = 0; cc < RANKS; cc = cc + 1) begin: dlyval_dq_assgn + for (dd = 0; dd < DQ_WIDTH; dd = dd + 1) + dlyval_dq[((5*dd)+(cc*DQ_WIDTH*5))+:5] <= #TCQ dlyval_dq_reg_r[cc][dd]; + end + end + + //*************************************************************************** + // Generate signal used to delay calibration state machine - used when: + // (1) IDELAY value changed + // (2) RD_MUX_SEL value changed + // Use when a delay is necessary to give the change time to propagate + // through the data pipeline (through IDELAY and ISERDES, and fabric + // pipeline stages) + //*************************************************************************** + + + // List all the stage 1 calibration wait states here. + // verilint STARC-2.7.3.3b off + always @(posedge clk) + if ((cal1_state_r == CAL1_NEW_DQS_WAIT) || + (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || + (cal1_state_r == CAL1_NEW_DQS_PREWAIT) || + (cal1_state_r == CAL1_VALID_WAIT) || + (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || + (cal1_state_r == CAL1_PB_INC_CPT_WAIT) || + (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT) || + (cal1_state_r == CAL1_PB_INC_DQ_WAIT) || + (cal1_state_r == CAL1_PB_DEC_CPT_WAIT) || + (cal1_state_r == CAL1_IDEL_INC_CPT_WAIT) || + (cal1_state_r == CAL1_IDEL_DEC_CPT_WAIT) || + (cal1_state_r == CAL1_STORE_FIRST_WAIT) || + (cal1_state_r == CAL1_DQ_IDEL_TAP_INC_WAIT) || + (cal1_state_r == CAL1_DQ_IDEL_TAP_DEC_WAIT) || + (cal1_state_r == CAL1_CENTER_WAIT) || + (cal1_state_r == CAL1_RD_STOP_FOR_PI_INC)) + cal1_wait_cnt_en_r <= #TCQ 1'b1; + else + cal1_wait_cnt_en_r <= #TCQ 1'b0; +// verilint STARC-2.7.3.3b on + always @(posedge clk) + if (!cal1_wait_cnt_en_r) begin + cal1_wait_cnt_r <= #TCQ 5'b00000; + cal1_wait_r <= #TCQ 1'b1; + end else begin + if (cal1_wait_cnt_r != PIPE_WAIT_CNT - 1) begin + cal1_wait_cnt_r <= #TCQ cal1_wait_cnt_r + 1; + cal1_wait_r <= #TCQ 1'b1; + end else begin + // Need to reset to 0 to handle the case when there are two + // different WAIT states back-to-back + cal1_wait_cnt_r <= #TCQ 5'b00000; + cal1_wait_r <= #TCQ 1'b0; + end + end + + //*************************************************************************** + // generate request to PHY_INIT logic to issue precharged. Required when + // calibration can take a long time (during which there are only constant + // reads present on this bus). In this case need to issue perioidic + // precharges to avoid tRAS violation. This signal must meet the following + // requirements: (1) only transition from 0->1 when prech is first needed, + // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted + //*************************************************************************** + + always @(posedge clk) + if (rst) + rdlvl_prech_req <= #TCQ 1'b0; + else + rdlvl_prech_req <= #TCQ cal1_prech_req_r; + + //*************************************************************************** + // Serial-to-parallel register to store last RDDATA_SHIFT_LEN cycles of + // data from ISERDES. The value of this register is also stored, so that + // previous and current values of the ISERDES data can be compared while + // varying the IODELAY taps to see if an "edge" of the data valid window + // has been encountered since the last IODELAY tap adjustment + //*************************************************************************** + + //*************************************************************************** + // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES + // NOTE: Written using discrete flops, but SRL can be used if the matching + // logic does the comparison sequentially, rather than parallel + //*************************************************************************** + + generate + genvar rd_i; + if (nCK_PER_CLK == 4) begin: gen_sr_div4 + if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 + for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr + always @(posedge clk) begin + if (mux_rd_valid_r) begin + sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; + sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; + sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; + sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; + sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; + sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; + sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; + sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; + end + end + end + end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 + for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr + always @(posedge clk) begin + if (mux_rd_valid_r) begin + sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_rise0_r[rd_i]}; + sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_fall0_r[rd_i]}; + sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_rise1_r[rd_i]}; + sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_fall1_r[rd_i]}; + sr_rise2_r[rd_i] <= #TCQ {sr_rise2_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_rise2_r[rd_i]}; + sr_fall2_r[rd_i] <= #TCQ {sr_fall2_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_fall2_r[rd_i]}; + sr_rise3_r[rd_i] <= #TCQ {sr_rise3_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_rise3_r[rd_i]}; + sr_fall3_r[rd_i] <= #TCQ {sr_fall3_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_fall3_r[rd_i]}; + end + end + end + end + end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 + if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 + for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr + always @(posedge clk) begin + if (mux_rd_valid_r) begin + sr_rise0_r[rd_i] <= #TCQ {mux_rd_rise0_r[rd_i]}; + sr_fall0_r[rd_i] <= #TCQ {mux_rd_fall0_r[rd_i]}; + sr_rise1_r[rd_i] <= #TCQ {mux_rd_rise1_r[rd_i]}; + sr_fall1_r[rd_i] <= #TCQ {mux_rd_fall1_r[rd_i]}; + end + end + end + end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 + for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr + always @(posedge clk) begin + if (mux_rd_valid_r) begin + sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_rise0_r[rd_i]}; + sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_fall0_r[rd_i]}; + sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_rise1_r[rd_i]}; + sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_fall1_r[rd_i]}; + end + end + end + end + end + endgenerate + + //*************************************************************************** + // Conversion to pattern calibration + //*************************************************************************** + + // Pattern for DQ IDELAY calibration + + //***************************************************************** + // Expected data pattern when DQ shifted to the right such that + // DQS before the left edge of the DVW: + // Based on pattern of ({rise,fall}) = + // 0x1, 0xB, 0x4, 0x4, 0xB, 0x9 + // Each nibble will look like: + // bit3: 0, 1, 0, 0, 1, 1 + // bit2: 0, 0, 1, 1, 0, 0 + // bit1: 0, 1, 0, 0, 1, 0 + // bit0: 1, 1, 0, 0, 1, 1 + // Or if the write is early it could look like: + // 0x4, 0x4, 0xB, 0x9, 0x6, 0xE + // bit3: 0, 0, 1, 1, 0, 1 + // bit2: 1, 1, 0, 0, 1, 1 + // bit1: 0, 0, 1, 0, 1, 1 + // bit0: 0, 0, 1, 1, 0, 0 + // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN + // and the actual training pattern contents change + //***************************************************************** + + generate + if (nCK_PER_CLK == 4) begin: gen_pat_div4 + // Pattern for DQ IDELAY increment + + // Target pattern for "early write" + assign {idel_pat0_rise0[3], idel_pat0_rise0[2], + idel_pat0_rise0[1], idel_pat0_rise0[0]} = 4'h1; + assign {idel_pat0_fall0[3], idel_pat0_fall0[2], + idel_pat0_fall0[1], idel_pat0_fall0[0]} = 4'h7; + assign {idel_pat0_rise1[3], idel_pat0_rise1[2], + idel_pat0_rise1[1], idel_pat0_rise1[0]} = 4'hE; + assign {idel_pat0_fall1[3], idel_pat0_fall1[2], + idel_pat0_fall1[1], idel_pat0_fall1[0]} = 4'hC; + assign {idel_pat0_rise2[3], idel_pat0_rise2[2], + idel_pat0_rise2[1], idel_pat0_rise2[0]} = 4'h9; + assign {idel_pat0_fall2[3], idel_pat0_fall2[2], + idel_pat0_fall2[1], idel_pat0_fall2[0]} = 4'h2; + assign {idel_pat0_rise3[3], idel_pat0_rise3[2], + idel_pat0_rise3[1], idel_pat0_rise3[0]} = 4'h4; + assign {idel_pat0_fall3[3], idel_pat0_fall3[2], + idel_pat0_fall3[1], idel_pat0_fall3[0]} = 4'hB; + + // Target pattern for "on-time write" + assign {idel_pat1_rise0[3], idel_pat1_rise0[2], + idel_pat1_rise0[1], idel_pat1_rise0[0]} = 4'h4; + assign {idel_pat1_fall0[3], idel_pat1_fall0[2], + idel_pat1_fall0[1], idel_pat1_fall0[0]} = 4'h9; + assign {idel_pat1_rise1[3], idel_pat1_rise1[2], + idel_pat1_rise1[1], idel_pat1_rise1[0]} = 4'h3; + assign {idel_pat1_fall1[3], idel_pat1_fall1[2], + idel_pat1_fall1[1], idel_pat1_fall1[0]} = 4'h7; + assign {idel_pat1_rise2[3], idel_pat1_rise2[2], + idel_pat1_rise2[1], idel_pat1_rise2[0]} = 4'hE; + assign {idel_pat1_fall2[3], idel_pat1_fall2[2], + idel_pat1_fall2[1], idel_pat1_fall2[0]} = 4'hC; + assign {idel_pat1_rise3[3], idel_pat1_rise3[2], + idel_pat1_rise3[1], idel_pat1_rise3[0]} = 4'h9; + assign {idel_pat1_fall3[3], idel_pat1_fall3[2], + idel_pat1_fall3[1], idel_pat1_fall3[0]} = 4'h2; + + + // Correct data valid window for "early write" + assign {pat0_rise0[3], pat0_rise0[2], + pat0_rise0[1], pat0_rise0[0]} = 4'h7; + assign {pat0_fall0[3], pat0_fall0[2], + pat0_fall0[1], pat0_fall0[0]} = 4'hE; + assign {pat0_rise1[3], pat0_rise1[2], + pat0_rise1[1], pat0_rise1[0]} = 4'hC; + assign {pat0_fall1[3], pat0_fall1[2], + pat0_fall1[1], pat0_fall1[0]} = 4'h9; + assign {pat0_rise2[3], pat0_rise2[2], + pat0_rise2[1], pat0_rise2[0]} = 4'h2; + assign {pat0_fall2[3], pat0_fall2[2], + pat0_fall2[1], pat0_fall2[0]} = 4'h4; + assign {pat0_rise3[3], pat0_rise3[2], + pat0_rise3[1], pat0_rise3[0]} = 4'hB; + assign {pat0_fall3[3], pat0_fall3[2], + pat0_fall3[1], pat0_fall3[0]} = 4'h1; + + // Correct data valid window for "on-time write" + assign {pat1_rise0[3], pat1_rise0[2], + pat1_rise0[1], pat1_rise0[0]} = 4'h9; + assign {pat1_fall0[3], pat1_fall0[2], + pat1_fall0[1], pat1_fall0[0]} = 4'h3; + assign {pat1_rise1[3], pat1_rise1[2], + pat1_rise1[1], pat1_rise1[0]} = 4'h7; + assign {pat1_fall1[3], pat1_fall1[2], + pat1_fall1[1], pat1_fall1[0]} = 4'hE; + assign {pat1_rise2[3], pat1_rise2[2], + pat1_rise2[1], pat1_rise2[0]} = 4'hC; + assign {pat1_fall2[3], pat1_fall2[2], + pat1_fall2[1], pat1_fall2[0]} = 4'h9; + assign {pat1_rise3[3], pat1_rise3[2], + pat1_rise3[1], pat1_rise3[0]} = 4'h2; + assign {pat1_fall3[3], pat1_fall3[2], + pat1_fall3[1], pat1_fall3[0]} = 4'h4; + + end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 + + // Pattern for DQ IDELAY increment + + // Target pattern for "early write" + assign idel_pat0_rise0[3] = 2'b01; + assign idel_pat0_fall0[3] = 2'b00; + assign idel_pat0_rise1[3] = 2'b10; + assign idel_pat0_fall1[3] = 2'b11; + + assign idel_pat0_rise0[2] = 2'b00; + assign idel_pat0_fall0[2] = 2'b10; + assign idel_pat0_rise1[2] = 2'b11; + assign idel_pat0_fall1[2] = 2'b10; + + assign idel_pat0_rise0[1] = 2'b00; + assign idel_pat0_fall0[1] = 2'b11; + assign idel_pat0_rise1[1] = 2'b10; + assign idel_pat0_fall1[1] = 2'b01; + + assign idel_pat0_rise0[0] = 2'b11; + assign idel_pat0_fall0[0] = 2'b10; + assign idel_pat0_rise1[0] = 2'b00; + assign idel_pat0_fall1[0] = 2'b01; + + + // Target pattern for "on-time write" + assign idel_pat1_rise0[3] = 2'b01; + assign idel_pat1_fall0[3] = 2'b11; + assign idel_pat1_rise1[3] = 2'b01; + assign idel_pat1_fall1[3] = 2'b00; + + assign idel_pat1_rise0[2] = 2'b11; + assign idel_pat1_fall0[2] = 2'b01; + assign idel_pat1_rise1[2] = 2'b00; + assign idel_pat1_fall1[2] = 2'b10; + + assign idel_pat1_rise0[1] = 2'b01; + assign idel_pat1_fall0[1] = 2'b00; + assign idel_pat1_rise1[1] = 2'b10; + assign idel_pat1_fall1[1] = 2'b11; + + assign idel_pat1_rise0[0] = 2'b00; + assign idel_pat1_fall0[0] = 2'b10; + assign idel_pat1_rise1[0] = 2'b11; + assign idel_pat1_fall1[0] = 2'b10; + + + // Correct data valid window for "early write" + assign pat0_rise0[3] = 2'b00; + assign pat0_fall0[3] = 2'b10; + assign pat0_rise1[3] = 2'b11; + assign pat0_fall1[3] = 2'b10; + + assign pat0_rise0[2] = 2'b10; + assign pat0_fall0[2] = 2'b11; + assign pat0_rise1[2] = 2'b10; + assign pat0_fall1[2] = 2'b00; + + assign pat0_rise0[1] = 2'b11; + assign pat0_fall0[1] = 2'b10; + assign pat0_rise1[1] = 2'b01; + assign pat0_fall1[1] = 2'b00; + + assign pat0_rise0[0] = 2'b10; + assign pat0_fall0[0] = 2'b00; + assign pat0_rise1[0] = 2'b01; + assign pat0_fall1[0] = 2'b11; + + // Correct data valid window for "on-time write" + assign pat1_rise0[3] = 2'b11; + assign pat1_fall0[3] = 2'b01; + assign pat1_rise1[3] = 2'b00; + assign pat1_fall1[3] = 2'b10; + + assign pat1_rise0[2] = 2'b01; + assign pat1_fall0[2] = 2'b00; + assign pat1_rise1[2] = 2'b10; + assign pat1_fall1[2] = 2'b11; + + assign pat1_rise0[1] = 2'b00; + assign pat1_fall0[1] = 2'b10; + assign pat1_rise1[1] = 2'b11; + assign pat1_fall1[1] = 2'b10; + + assign pat1_rise0[0] = 2'b10; + assign pat1_fall0[0] = 2'b11; + assign pat1_rise1[0] = 2'b10; + assign pat1_fall1[0] = 2'b00; + end + endgenerate + + // Each bit of each byte is compared to expected pattern. + // This was done to prevent (and "drastically decrease") the chance that + // invalid data clocked in when the DQ bus is tri-state (along with a + // combination of the correct data) will resemble the expected data + // pattern. A better fix for this is to change the training pattern and/or + // make the pattern longer. + generate + genvar pt_i; + if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 + for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match + + // DQ IDELAY pattern detection + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) + idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) + idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) + idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) + idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == idel_pat0_rise2[pt_i%4]) + idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == idel_pat0_fall2[pt_i%4]) + idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == idel_pat0_rise3[pt_i%4]) + idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == idel_pat0_fall3[pt_i%4]) + idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) + idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) + idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) + idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) + idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == idel_pat1_rise2[pt_i%4]) + idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == idel_pat1_fall2[pt_i%4]) + idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == idel_pat1_rise3[pt_i%4]) + idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == idel_pat1_fall3[pt_i%4]) + idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + + // DQS DVW pattern detection + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) + pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) + pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) + pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) + pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == pat0_rise2[pt_i%4]) + pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == pat0_fall2[pt_i%4]) + pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == pat0_rise3[pt_i%4]) + pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == pat0_fall3[pt_i%4]) + pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) + pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) + pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) + pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) + pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == pat1_rise2[pt_i%4]) + pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == pat1_fall2[pt_i%4]) + pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == pat1_rise3[pt_i%4]) + pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == pat1_fall3[pt_i%4]) + pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + + end + + // Combine pattern match "subterms" for DQ-IDELAY stage + always @(posedge clk) begin + idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; + idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; + idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; + idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; + idel_pat0_match_rise2_and_r <= #TCQ &idel_pat0_match_rise2_r; + idel_pat0_match_fall2_and_r <= #TCQ &idel_pat0_match_fall2_r; + idel_pat0_match_rise3_and_r <= #TCQ &idel_pat0_match_rise3_r; + idel_pat0_match_fall3_and_r <= #TCQ &idel_pat0_match_fall3_r; + idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && + idel_pat0_match_fall0_and_r && + idel_pat0_match_rise1_and_r && + idel_pat0_match_fall1_and_r && + idel_pat0_match_rise2_and_r && + idel_pat0_match_fall2_and_r && + idel_pat0_match_rise3_and_r && + idel_pat0_match_fall3_and_r); + end + + always @(posedge clk) begin + idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; + idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; + idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; + idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; + idel_pat1_match_rise2_and_r <= #TCQ &idel_pat1_match_rise2_r; + idel_pat1_match_fall2_and_r <= #TCQ &idel_pat1_match_fall2_r; + idel_pat1_match_rise3_and_r <= #TCQ &idel_pat1_match_rise3_r; + idel_pat1_match_fall3_and_r <= #TCQ &idel_pat1_match_fall3_r; + idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && + idel_pat1_match_fall0_and_r && + idel_pat1_match_rise1_and_r && + idel_pat1_match_fall1_and_r && + idel_pat1_match_rise2_and_r && + idel_pat1_match_fall2_and_r && + idel_pat1_match_rise3_and_r && + idel_pat1_match_fall3_and_r); + end + + always @(*) + idel_pat_data_match <= #TCQ idel_pat0_data_match_r | + idel_pat1_data_match_r; + + always @(posedge clk) + idel_pat_data_match_r <= #TCQ idel_pat_data_match; + + // Combine pattern match "subterms" for DQS-PHASER_IN stage + always @(posedge clk) begin + pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; + pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; + pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; + pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; + pat0_match_rise2_and_r <= #TCQ &pat0_match_rise2_r; + pat0_match_fall2_and_r <= #TCQ &pat0_match_fall2_r; + pat0_match_rise3_and_r <= #TCQ &pat0_match_rise3_r; + pat0_match_fall3_and_r <= #TCQ &pat0_match_fall3_r; + pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && + pat0_match_fall0_and_r && + pat0_match_rise1_and_r && + pat0_match_fall1_and_r && + pat0_match_rise2_and_r && + pat0_match_fall2_and_r && + pat0_match_rise3_and_r && + pat0_match_fall3_and_r); + end + + always @(posedge clk) begin + pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; + pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; + pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; + pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; + pat1_match_rise2_and_r <= #TCQ &pat1_match_rise2_r; + pat1_match_fall2_and_r <= #TCQ &pat1_match_fall2_r; + pat1_match_rise3_and_r <= #TCQ &pat1_match_rise3_r; + pat1_match_fall3_and_r <= #TCQ &pat1_match_fall3_r; + pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && + pat1_match_fall0_and_r && + pat1_match_rise1_and_r && + pat1_match_fall1_and_r && + pat1_match_rise2_and_r && + pat1_match_fall2_and_r && + pat1_match_rise3_and_r && + pat1_match_fall3_and_r); + end + + assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; + + end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 + for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match + + // DQ IDELAY pattern detection + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) + idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) + idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) + idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) + idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) + idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) + idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) + idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) + idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + // DQS DVW pattern detection + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) + pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) + pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) + pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) + pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) + pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) + pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) + pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) + pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + end + + // Combine pattern match "subterms" for DQ-IDELAY stage + always @(posedge clk) begin + idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; + idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; + idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; + idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; + idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && + idel_pat0_match_fall0_and_r && + idel_pat0_match_rise1_and_r && + idel_pat0_match_fall1_and_r); + end + + always @(posedge clk) begin + idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; + idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; + idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; + idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; + idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && + idel_pat1_match_fall0_and_r && + idel_pat1_match_rise1_and_r && + idel_pat1_match_fall1_and_r); + end + + always @(posedge clk) begin + if (sr_valid_r2) + idel_pat_data_match <= #TCQ idel_pat0_data_match_r | + idel_pat1_data_match_r; + end + + //assign idel_pat_data_match = idel_pat0_data_match_r | + // idel_pat1_data_match_r; + + always @(posedge clk) + idel_pat_data_match_r <= #TCQ idel_pat_data_match; + + // Combine pattern match "subterms" for DQS-PHASER_IN stage + always @(posedge clk) begin + pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; + pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; + pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; + pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; + pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && + pat0_match_fall0_and_r && + pat0_match_rise1_and_r && + pat0_match_fall1_and_r); + end + + always @(posedge clk) begin + pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; + pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; + pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; + pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; + pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && + pat1_match_fall0_and_r && + pat1_match_rise1_and_r && + pat1_match_fall1_and_r); + end + + assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; + + end + + endgenerate + + + always @(posedge clk) begin + rdlvl_stg1_start_r <= #TCQ rdlvl_stg1_start; + mpr_rdlvl_done_r1 <= #TCQ mpr_rdlvl_done_r; + mpr_rdlvl_done_r2 <= #TCQ mpr_rdlvl_done_r1; + mpr_rdlvl_start_r <= #TCQ mpr_rdlvl_start; + end + + //*************************************************************************** + // First stage calibration: Capture clock + //*************************************************************************** + + //***************************************************************** + // Keep track of how many samples have been written to shift registers + // Every time RD_SHIFT_LEN samples have been written, then we have a + // full read training pattern loaded into the sr_* registers. Then assert + // sr_valid_r to indicate that: (1) comparison between the sr_* and + // old_sr_* and prev_sr_* registers can take place, (2) transfer of + // the contents of sr_* to old_sr_* and prev_sr_* registers can also + // take place + //***************************************************************** +// verilint STARC-2.2.3.3 off + always @(posedge clk) + if (rst || (mpr_rdlvl_done_r && ~rdlvl_stg1_start)) begin + cnt_shift_r <= #TCQ 'b1; + sr_valid_r <= #TCQ 1'b0; + mpr_valid_r <= #TCQ 1'b0; + end else begin + if (mux_rd_valid_r && mpr_rdlvl_start && ~mpr_rdlvl_done_r) begin + if (cnt_shift_r == 'b0) + mpr_valid_r <= #TCQ 1'b1; + else begin + mpr_valid_r <= #TCQ 1'b0; + cnt_shift_r <= #TCQ cnt_shift_r + 1; + end + end else + mpr_valid_r <= #TCQ 1'b0; + + if (mux_rd_valid_r && rdlvl_stg1_start) begin + if (cnt_shift_r == RD_SHIFT_LEN-1) begin + sr_valid_r <= #TCQ 1'b1; + cnt_shift_r <= #TCQ 'b0; + end else begin + sr_valid_r <= #TCQ 1'b0; + cnt_shift_r <= #TCQ cnt_shift_r + 1; + end + end else + // When the current mux_rd_* contents are not valid, then + // retain the current value of cnt_shift_r, and make sure + // that sr_valid_r = 0 to prevent any downstream loads or + // comparisons + sr_valid_r <= #TCQ 1'b0; + end +// verilint STARC-2.2.3.3 on + //***************************************************************** + // Logic to determine when either edge of the data eye encountered + // Pre- and post-IDELAY update data pattern is compared, if they + // differ, than an edge has been encountered. Currently no attempt + // made to determine if the data pattern itself is "correct", only + // whether it changes after incrementing the IDELAY (possible + // future enhancement) + //***************************************************************** + + // One-way control for ensuring that state machine request to store + // current read data into OLD SR shift register only occurs on a + // valid clock cycle. The FSM provides a one-cycle request pulse. + // It is the responsibility of the FSM to wait the worst-case time + // before relying on any downstream results of this load. + always @(posedge clk) + if (rst) + store_sr_r <= #TCQ 1'b0; + else begin + if (store_sr_req_r) + store_sr_r <= #TCQ 1'b1; + else if ((sr_valid_r || mpr_valid_r) && store_sr_r) + store_sr_r <= #TCQ 1'b0; + end + + // Transfer current data to old data, prior to incrementing delay + // Also store data from current sampling window - so that we can detect + // if the current delay tap yields data that is "jittery" + generate + if (nCK_PER_CLK == 4) begin: gen_old_sr_div4 + for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr + always @(posedge clk) begin + if (sr_valid_r || mpr_valid_r) begin + // Load last sample (i.e. from current sampling interval) + prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; + prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; + prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; + prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; + prev_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; + prev_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; + prev_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; + prev_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; + end + if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin + old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; + old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; + old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; + old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; + old_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; + old_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; + old_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; + old_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; + end + end + end + end else if (nCK_PER_CLK == 2) begin: gen_old_sr_div2 + for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr + always @(posedge clk) begin + if (sr_valid_r || mpr_valid_r) begin + prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; + prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; + prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; + prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; + end + if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin + old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; + old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; + old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; + old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; + end + end + end + end + endgenerate + + //******************************************************* + // Match determination occurs over 3 cycles - pipelined for better timing + //******************************************************* + + // Match valid with # of cycles of pipelining in match determination + always @(posedge clk) begin + sr_valid_r1 <= #TCQ sr_valid_r; + sr_valid_r2 <= #TCQ sr_valid_r1; + mpr_valid_r1 <= #TCQ mpr_valid_r; + mpr_valid_r2 <= #TCQ mpr_valid_r1; + end + + generate + if (nCK_PER_CLK == 4) begin: gen_sr_match_div4 + for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match + always @(posedge clk) begin + // CYCLE1: Compare all bits in DQS grp, generate separate term for + // each bit over four bit times. For example, if there are 8-bits + // per DQS group, 32 terms are generated on cycle 1 + // NOTE: Structure HDL such that X on data bus will result in a + // mismatch. This is required for memory models that can drive the + // bus with X's to model uncertainty regions (e.g. Denali) + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) + old_sr_match_rise0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; + else + old_sr_match_rise0_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) + old_sr_match_fall0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; + else + old_sr_match_fall0_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) + old_sr_match_rise1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; + else + old_sr_match_rise1_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) + old_sr_match_fall1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; + else + old_sr_match_fall1_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == old_sr_rise2_r[z])) + old_sr_match_rise2_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_rise2_r[z] <= #TCQ old_sr_match_rise2_r[z]; + else + old_sr_match_rise2_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == old_sr_fall2_r[z])) + old_sr_match_fall2_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_fall2_r[z] <= #TCQ old_sr_match_fall2_r[z]; + else + old_sr_match_fall2_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == old_sr_rise3_r[z])) + old_sr_match_rise3_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_rise3_r[z] <= #TCQ old_sr_match_rise3_r[z]; + else + old_sr_match_rise3_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == old_sr_fall3_r[z])) + old_sr_match_fall3_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_fall3_r[z] <= #TCQ old_sr_match_fall3_r[z]; + else + old_sr_match_fall3_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) + prev_sr_match_rise0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; + else + prev_sr_match_rise0_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) + prev_sr_match_fall0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; + else + prev_sr_match_fall0_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) + prev_sr_match_rise1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; + else + prev_sr_match_rise1_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) + prev_sr_match_fall1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; + else + prev_sr_match_fall1_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == prev_sr_rise2_r[z])) + prev_sr_match_rise2_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_rise2_r[z] <= #TCQ prev_sr_match_rise2_r[z]; + else + prev_sr_match_rise2_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == prev_sr_fall2_r[z])) + prev_sr_match_fall2_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_fall2_r[z] <= #TCQ prev_sr_match_fall2_r[z]; + else + prev_sr_match_fall2_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == prev_sr_rise3_r[z])) + prev_sr_match_rise3_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_rise3_r[z] <= #TCQ prev_sr_match_rise3_r[z]; + else + prev_sr_match_rise3_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == prev_sr_fall3_r[z])) + prev_sr_match_fall3_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_fall3_r[z] <= #TCQ prev_sr_match_fall3_r[z]; + else + prev_sr_match_fall3_r[z] <= #TCQ 1'b0; + + // CYCLE2: Combine all the comparisons for every 8 words (rise0, + // fall0,rise1, fall1) in the calibration sequence. Now we're down + // to DRAM_WIDTH terms + old_sr_match_cyc2_r[z] <= #TCQ + old_sr_match_rise0_r[z] & + old_sr_match_fall0_r[z] & + old_sr_match_rise1_r[z] & + old_sr_match_fall1_r[z] & + old_sr_match_rise2_r[z] & + old_sr_match_fall2_r[z] & + old_sr_match_rise3_r[z] & + old_sr_match_fall3_r[z]; + prev_sr_match_cyc2_r[z] <= #TCQ + prev_sr_match_rise0_r[z] & + prev_sr_match_fall0_r[z] & + prev_sr_match_rise1_r[z] & + prev_sr_match_fall1_r[z] & + prev_sr_match_rise2_r[z] & + prev_sr_match_fall2_r[z] & + prev_sr_match_rise3_r[z] & + prev_sr_match_fall3_r[z]; + + // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), + // and qualify with pipelined valid signal) - probably don't need + // a cycle just do do this.... + if (sr_valid_r2 || mpr_valid_r2) begin + old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; + prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; + end else begin + old_sr_diff_r[z] <= #TCQ 'b0; + prev_sr_diff_r[z] <= #TCQ 'b0; + end + end + end + end if (nCK_PER_CLK == 2) begin: gen_sr_match_div2 + for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match + always @(posedge clk) begin + if ((sr_valid_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) + old_sr_match_rise0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; + else + old_sr_match_rise0_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) + old_sr_match_fall0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; + else + old_sr_match_fall0_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) + old_sr_match_rise1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; + else + old_sr_match_rise1_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) + old_sr_match_fall1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; + else + old_sr_match_fall1_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) + prev_sr_match_rise0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; + else + prev_sr_match_rise0_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) + prev_sr_match_fall0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; + else + prev_sr_match_fall0_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) + prev_sr_match_rise1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; + else + prev_sr_match_rise1_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) + prev_sr_match_fall1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; + else + prev_sr_match_fall1_r[z] <= #TCQ 1'b0; + + old_sr_match_cyc2_r[z] <= #TCQ + old_sr_match_rise0_r[z] & + old_sr_match_fall0_r[z] & + old_sr_match_rise1_r[z] & + old_sr_match_fall1_r[z]; + prev_sr_match_cyc2_r[z] <= #TCQ + prev_sr_match_rise0_r[z] & + prev_sr_match_fall0_r[z] & + prev_sr_match_rise1_r[z] & + prev_sr_match_fall1_r[z]; + + // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), + // and qualify with pipelined valid signal) - probably don't need + // a cycle just do do this.... + if (sr_valid_r2 || mpr_valid_r2) begin + old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; + prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; + end else begin + old_sr_diff_r[z] <= #TCQ 'b0; + prev_sr_diff_r[z] <= #TCQ 'b0; + end + end + end + end + endgenerate + + //*************************************************************************** + // First stage calibration: DQS Capture + //*************************************************************************** + + + //******************************************************* + // Counters for tracking # of samples compared + // For each comparision point (i.e. to determine if an edge has + // occurred after each IODELAY increment when read leveling), + // multiple samples are compared in order to average out the effects + // of jitter. If any one of these samples is different than the "old" + // sample corresponding to the previous IODELAY value, then an edge + // is declared to be detected. + //******************************************************* + + // Two cascaded counters are used to keep track of # of samples compared, + // in order to make it easier to meeting timing on these paths. Once + // optimal sampling interval is determined, it may be possible to remove + // the second counter + always @(posedge clk) + samp_edge_cnt0_en_r <= #TCQ + (cal1_state_r == CAL1_PAT_DETECT) || + (cal1_state_r == CAL1_DETECT_EDGE) || + (cal1_state_r == CAL1_PB_DETECT_EDGE) || + (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); + + // First counter counts # of samples compared + always @(posedge clk) + if (rst) + samp_edge_cnt0_r <= #TCQ 'b0; + else begin + if (!samp_edge_cnt0_en_r) + // Reset sample counter when not in any of the "sampling" states + samp_edge_cnt0_r <= #TCQ 'b0; + else if (sr_valid_r2 || mpr_valid_r2) + // Otherwise, count # of samples compared + samp_edge_cnt0_r <= #TCQ samp_edge_cnt0_r + 1; + end + + // Counter #2 enable generation + always @(posedge clk) + if (rst) + samp_edge_cnt1_en_r <= #TCQ 1'b0; + else begin + // Assert pulse when correct number of samples compared + if ((samp_edge_cnt0_r == DETECT_EDGE_SAMPLE_CNT0) && + (sr_valid_r2 || mpr_valid_r2)) + samp_edge_cnt1_en_r <= #TCQ 1'b1; + else + samp_edge_cnt1_en_r <= #TCQ 1'b0; + end + + // Counter #2 + always @(posedge clk) + if (rst) + samp_edge_cnt1_r <= #TCQ 'b0; + else + if (!samp_edge_cnt0_en_r) + samp_edge_cnt1_r <= #TCQ 'b0; + else if (samp_edge_cnt1_en_r) + samp_edge_cnt1_r <= #TCQ samp_edge_cnt1_r + 1; + + always @(posedge clk) + if (rst) + samp_cnt_done_r <= #TCQ 1'b0; + else begin + if (!samp_edge_cnt0_en_r) + samp_cnt_done_r <= #TCQ 'b0; + else if ((SIM_CAL_OPTION == "FAST_CAL") || + (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin + if (samp_edge_cnt0_r == SR_VALID_DELAY-1) + // For simulation only, stay in edge detection mode a minimum + // amount of time - just enough for two data compares to finish + samp_cnt_done_r <= #TCQ 1'b1; + end else begin + if (samp_edge_cnt1_r == DETECT_EDGE_SAMPLE_CNT1) + samp_cnt_done_r <= #TCQ 1'b1; + end + end + + //***************************************************************** + // Logic to keep track of (on per-bit basis): + // 1. When a region of stability preceded by a known edge occurs + // 2. If for the current tap, the read data jitters + // 3. If an edge occured between the current and previous tap + // 4. When the current edge detection/sampling interval can end + // Essentially, these are a series of status bits - the stage 1 + // calibration FSM monitors these to determine when an edge is + // found. Additional information is provided to help the FSM + // determine if a left or right edge has been found. + //**************************************************************** + + assign pb_detect_edge_setup + = (cal1_state_r == CAL1_STORE_FIRST_WAIT) || + (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || + (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT); + + assign pb_detect_edge + = (cal1_state_r == CAL1_PAT_DETECT) || + (cal1_state_r == CAL1_DETECT_EDGE) || + (cal1_state_r == CAL1_PB_DETECT_EDGE) || + (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); + + generate + for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_track_left_edge + always @(posedge clk) begin + if (pb_detect_edge_setup) begin + // Reset eye size, stable eye marker, and jitter marker before + // starting new edge detection iteration + pb_cnt_eye_size_r[z] <= #TCQ 5'd0; + pb_detect_edge_done_r[z] <= #TCQ 1'b0; + pb_found_stable_eye_r[z] <= #TCQ 1'b0; + pb_last_tap_jitter_r[z] <= #TCQ 1'b0; + pb_found_edge_last_r[z] <= #TCQ 1'b0; + pb_found_edge_r[z] <= #TCQ 1'b0; + pb_found_first_edge_r[z] <= #TCQ 1'b0; + end else if (pb_detect_edge) begin + // Save information on which DQ bits are already out of the + // data valid window - those DQ bits will later not have their + // IDELAY tap value incremented + pb_found_edge_last_r[z] <= #TCQ pb_found_edge_r[z]; + + if (!pb_detect_edge_done_r[z]) begin + if (samp_cnt_done_r) begin + // If we've reached end of sampling interval, no jitter on + // current tap has been found (although an edge could have + // been found between the current and previous taps), and + // the sampling interval is complete. Increment the stable + // eye counter if no edge found, and always clear the jitter + // flag in preparation for the next tap. + pb_last_tap_jitter_r[z] <= #TCQ 1'b0; + pb_detect_edge_done_r[z] <= #TCQ 1'b1; + if (!pb_found_edge_r[z] && !pb_last_tap_jitter_r[z]) begin + // If the data was completely stable during this tap and + // no edge was found between this and the previous tap + // then increment the stable eye counter "as appropriate" + if (pb_cnt_eye_size_r[z] != MIN_EYE_SIZE-1) + pb_cnt_eye_size_r[z] <= #TCQ pb_cnt_eye_size_r[z] + 1; + else //if (pb_found_first_edge_r[z]) + // We've reached minimum stable eye width + pb_found_stable_eye_r[z] <= #TCQ 1'b1; + end else begin + // Otherwise, an edge was found, either because of a + // difference between this and the previous tap's read + // data, and/or because the previous tap's data jittered + // (but not the current tap's data), then just set the + // edge found flag, and enable the stable eye counter + pb_cnt_eye_size_r[z] <= #TCQ 5'd0; + pb_found_stable_eye_r[z] <= #TCQ 1'b0; + pb_found_edge_r[z] <= #TCQ 1'b1; + pb_detect_edge_done_r[z] <= #TCQ 1'b1; + end + end else if (prev_sr_diff_r[z]) begin + // If we find that the current tap read data jitters, then + // set edge and jitter found flags, "enable" the eye size + // counter, and stop sampling interval for this bit + pb_cnt_eye_size_r[z] <= #TCQ 5'd0; + pb_found_stable_eye_r[z] <= #TCQ 1'b0; + pb_last_tap_jitter_r[z] <= #TCQ 1'b1; + pb_found_edge_r[z] <= #TCQ 1'b1; + pb_found_first_edge_r[z] <= #TCQ 1'b1; + pb_detect_edge_done_r[z] <= #TCQ 1'b1; + end else if (old_sr_diff_r[z] || pb_last_tap_jitter_r[z]) begin + // If either an edge was found (i.e. difference between + // current tap and previous tap read data), or the previous + // tap exhibited jitter (which means by definition that the + // current tap cannot match the previous tap because the + // previous tap gave unstable data), then set the edge found + // flag, and "enable" eye size counter. But do not stop + // sampling interval - we still need to check if the current + // tap exhibits jitter + pb_cnt_eye_size_r[z] <= #TCQ 5'd0; + pb_found_stable_eye_r[z] <= #TCQ 1'b0; + pb_found_edge_r[z] <= #TCQ 1'b1; + pb_found_first_edge_r[z] <= #TCQ 1'b1; + end + end + end else begin + // Before every edge detection interval, reset "intra-tap" flags + pb_found_edge_r[z] <= #TCQ 1'b0; + pb_detect_edge_done_r[z] <= #TCQ 1'b0; + end + end + end + endgenerate + + // Combine the above per-bit status flags into combined terms when + // performing deskew on the aggregate data window + always @(posedge clk) begin + detect_edge_done_r <= #TCQ &pb_detect_edge_done_r; + found_edge_r <= #TCQ |pb_found_edge_r; + found_edge_all_r <= #TCQ &pb_found_edge_r; + found_stable_eye_r <= #TCQ &pb_found_stable_eye_r; + end + + // last IODELAY "stable eye" indicator is updated only after + // detect_edge_done_r is asserted - so that when we do find the "right edge" + // of the data valid window, found_edge_r = 1, AND found_stable_eye_r = 1 + // when detect_edge_done_r = 1 (otherwise, if found_stable_eye_r updates + // immediately, then it never possible to have found_stable_eye_r = 1 + // when we detect an edge - and we'll never know whether we've found + // a "right edge") + always @(posedge clk) + if (pb_detect_edge_setup) + found_stable_eye_last_r <= #TCQ 1'b0; + else if (detect_edge_done_r) + found_stable_eye_last_r <= #TCQ found_stable_eye_r; + + //***************************************************************** + // Keep track of DQ IDELAYE2 taps used + //***************************************************************** + + // Added additional register stage to improve timing + always @(posedge clk) + if (rst) + idelay_tap_cnt_slice_r <= 5'h0; + else + idelay_tap_cnt_slice_r <= idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; + + always @(posedge clk) + if (rst || (SIM_CAL_OPTION == "SKIP_CAL")) begin //|| new_cnt_cpt_r + for (s = 0; s < RANKS; s = s + 1) begin + for (t = 0; t < DQS_WIDTH; t = t + 1) begin + idelay_tap_cnt_r[s][t] <= #TCQ idelaye2_init_val; + end + end + end else if (SIM_CAL_OPTION == "FAST_CAL") begin + for (u = 0; u < RANKS; u = u + 1) begin + for (w = 0; w < DQS_WIDTH; w = w + 1) begin + if (cal1_dq_idel_ce) begin + if (cal1_dq_idel_inc) + idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] + 1; + else + idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] - 1; + end + end + end + end else if ((rnk_cnt_r == RANKS-1) && (RANKS == 2) && + rdlvl_rank_done_r && (cal1_state_r == CAL1_IDLE)) begin + for (f = 0; f < DQS_WIDTH; f = f + 1) begin + idelay_tap_cnt_r[rnk_cnt_r][f] <= #TCQ idelay_tap_cnt_r[(rnk_cnt_r-1)][f]; + end + end else if (cal1_dq_idel_ce) begin + if (cal1_dq_idel_inc) + idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r + 5'h1; + else + idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r - 5'h1; + end else if (idelay_ld) + idelay_tap_cnt_r[0][wrcal_cnt] <= #TCQ 5'b00000; + + always @(posedge clk) + if (rst || new_cnt_cpt_r) + idelay_tap_limit_r <= #TCQ 1'b0; + else if (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_r] == 'd31) + idelay_tap_limit_r <= #TCQ 1'b1; + + //***************************************************************** + // keep track of edge tap counts found, and current capture clock + // tap count + //***************************************************************** + + always @(posedge clk) + if (rst || new_cnt_cpt_r || + (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) + tap_cnt_cpt_r <= #TCQ 'b0; + else if (cal1_dlyce_cpt_r) begin + if (cal1_dlyinc_cpt_r) + tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r + 1; + else if (tap_cnt_cpt_r != 'd0) + tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r - 1; + end + + always @(posedge clk) + if (rst || new_cnt_cpt_r || + (cal1_state_r1 == CAL1_DQ_IDEL_TAP_INC) || + (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) + tap_limit_cpt_r <= #TCQ 1'b0; + else if (tap_cnt_cpt_r == 6'd63) + tap_limit_cpt_r <= #TCQ 1'b1; + + always @(posedge clk) + cal1_cnt_cpt_timing_r <= #TCQ cal1_cnt_cpt_r; + + assign cal1_cnt_cpt_timing = {2'b00, cal1_cnt_cpt_r}; + + // Storing DQS tap values at the end of each DQS read leveling + always @(posedge clk) begin + if (rst) begin + for (a = 0; a < RANKS; a = a + 1) begin: rst_rdlvl_dqs_tap_count_loop + for (b = 0; b < DQS_WIDTH; b = b + 1) + rdlvl_dqs_tap_cnt_r[a][b] <= #TCQ 'b0; + end + end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_NEXT_DQS)) begin + for (p = 0; p < RANKS; p = p +1) begin: rdlvl_dqs_tap_rank_cnt + for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt + rdlvl_dqs_tap_cnt_r[p][q] <= #TCQ tap_cnt_cpt_r; + end + end + end else if (SIM_CAL_OPTION == "SKIP_CAL") begin + for (j = 0; j < RANKS; j = j +1) begin: rdlvl_dqs_tap_rnk_cnt + for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt + rdlvl_dqs_tap_cnt_r[j][i] <= #TCQ 6'd31; + end + end + end else if (cal1_state_r1 == CAL1_NEXT_DQS) begin + rdlvl_dqs_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing_r] <= #TCQ tap_cnt_cpt_r; + end + end + + + // Counter to track maximum DQ IODELAY tap usage during the per-bit + // deskew portion of stage 1 calibration + always @(posedge clk) + if (rst) begin + idel_tap_cnt_dq_pb_r <= #TCQ 'b0; + idel_tap_limit_dq_pb_r <= #TCQ 1'b0; + end else + if (new_cnt_cpt_r) begin + idel_tap_cnt_dq_pb_r <= #TCQ 'b0; + idel_tap_limit_dq_pb_r <= #TCQ 1'b0; + end else if (|cal1_dlyce_dq_r) begin + if (cal1_dlyinc_dq_r) + idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r + 1; + else + idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r - 1; + + if (idel_tap_cnt_dq_pb_r == 31) + idel_tap_limit_dq_pb_r <= #TCQ 1'b1; + else + idel_tap_limit_dq_pb_r <= #TCQ 1'b0; + end + + + //***************************************************************** + + always @(posedge clk) begin + cal1_state_r1 <= #TCQ cal1_state_r; + cal1_state_r2 <= #TCQ cal1_state_r1; + cal1_state_r3 <= #TCQ cal1_state_r2; + end + + always @(posedge clk) + if (rst) begin + cal1_cnt_cpt_r <= #TCQ 'b0; + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + cal1_dq_idel_ce <= #TCQ 1'b0; + cal1_dq_idel_inc <= #TCQ 1'b0; + cal1_prech_req_r <= #TCQ 1'b0; + cal1_state_r <= #TCQ CAL1_IDLE; + cnt_idel_dec_cpt_r <= #TCQ 6'bxxxxxx; + found_first_edge_r <= #TCQ 1'b0; + found_second_edge_r <= #TCQ 1'b0; + right_edge_taps_r <= #TCQ 6'b000000; + first_edge_taps_r <= #TCQ 6'bxxxxxx; + new_cnt_cpt_r <= #TCQ 1'b0; + rdlvl_stg1_done_int <= #TCQ 1'b0; + rdlvl_stg1_err <= #TCQ 1'b0; + second_edge_taps_r <= #TCQ 6'bxxxxxx; + store_sr_req_pulsed_r <= #TCQ 1'b0; + store_sr_req_r <= #TCQ 1'b0; + rnk_cnt_r <= #TCQ 2'b00; + rdlvl_rank_done_r <= #TCQ 1'b0; + idel_dec_cnt <= #TCQ 'd0; + rdlvl_last_byte_done_int <= #TCQ 1'b0; + idel_pat_detect_valid_r <= #TCQ 1'b0; + mpr_rank_done_r <= #TCQ 1'b0; + mpr_last_byte_done <= #TCQ 1'b0; + idel_adj_inc <= #TCQ 1'b0; + if (OCAL_EN == "ON") + mpr_rdlvl_done_r <= #TCQ 1'b0; + else + mpr_rdlvl_done_r <= #TCQ 1'b1; + mpr_dec_cpt_r <= #TCQ 1'b0; + rdlvl_pi_incdec <= #TCQ 1'b0; + end else begin + // default (inactive) states for all "pulse" outputs + // verilint STARC-2.2.3.3 off + cal1_prech_req_r <= #TCQ 1'b0; + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + cal1_dq_idel_ce <= #TCQ 1'b0; + cal1_dq_idel_inc <= #TCQ 1'b0; + new_cnt_cpt_r <= #TCQ 1'b0; + store_sr_req_pulsed_r <= #TCQ 1'b0; + store_sr_req_r <= #TCQ 1'b0; + + case (cal1_state_r) + + CAL1_IDLE: begin + rdlvl_rank_done_r <= #TCQ 1'b0; + rdlvl_last_byte_done_int <= #TCQ 1'b0; + mpr_rank_done_r <= #TCQ 1'b0; + mpr_last_byte_done <= #TCQ 1'b0; + if (mpr_rdlvl_start && ~mpr_rdlvl_start_r) begin + rdlvl_pi_incdec <= #TCQ 1'b0; + cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; + end else begin + rdlvl_pi_incdec <= #TCQ 1'b1; + if (rdlvl_stg1_start && ~rdlvl_stg1_start_r) begin + if (SIM_CAL_OPTION == "SKIP_CAL") + cal1_state_r <= #TCQ CAL1_REGL_LOAD; + else if (SIM_CAL_OPTION == "FAST_CAL") + cal1_state_r <= #TCQ CAL1_NEXT_DQS; + else begin + new_cnt_cpt_r <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; + end + end + end + end + + CAL1_MPR_NEW_DQS_WAIT: begin + cal1_prech_req_r <= #TCQ 1'b0; + if (!cal1_wait_r && mpr_valid_r) + cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; + end + + // Wait for the new DQS group to change + // also gives time for the read data IN_FIFO to + // output the updated data for the new DQS group + CAL1_NEW_DQS_WAIT: begin + rdlvl_rank_done_r <= #TCQ 1'b0; + rdlvl_last_byte_done_int <= #TCQ 1'b0; + mpr_rank_done_r <= #TCQ 1'b0; + mpr_last_byte_done <= #TCQ 1'b0; + cal1_prech_req_r <= #TCQ 1'b0; + if (|pi_counter_read_val) begin //VK_REVIEW + mpr_dec_cpt_r <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; + cnt_idel_dec_cpt_r <= #TCQ pi_counter_read_val; + rdlvl_pi_incdec <= #TCQ 1'b1; //every byte dec first so no read needed + end else if (!cal1_wait_r) begin + rdlvl_pi_incdec <= #TCQ 1'b0; + + // Store "previous tap" read data. Technically there is no + // "previous" read data, since we are starting a new DQS + // group, so we'll never find an edge at tap 0 unless the + // data is fluctuating/jittering + store_sr_req_r <= #TCQ 1'b1; + // If per-bit deskew is disabled, then skip the first + // portion of stage 1 calibration + if (PER_BIT_DESKEW == "OFF") + cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; + else if (PER_BIT_DESKEW == "ON") + cal1_state_r <= #TCQ CAL1_PB_STORE_FIRST_WAIT; + end else + rdlvl_pi_incdec <= #TCQ 1'b1; //every byte dec first so no read needed + end + //***************************************************************** + // Per-bit deskew states + //***************************************************************** + + // Wait state following storage of initial read data + CAL1_PB_STORE_FIRST_WAIT: + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; + + // Look for an edge on all DQ bits in current DQS group + CAL1_PB_DETECT_EDGE: + if (detect_edge_done_r) begin + if (found_stable_eye_r) begin + // If we've found the left edge for all bits (or more precisely, + // we've found the left edge, and then part of the stable + // window thereafter), then proceed to positioning the CPT clock + // right before the left margin + cnt_idel_dec_cpt_r <= #TCQ MIN_EYE_SIZE + 1; + cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT; + end else begin + // If we've reached the end of the sampling time, and haven't + // yet found the left margin of all the DQ bits, then: + if (!tap_limit_cpt_r) begin + // If we still have taps left to use, then store current value + // of read data, increment the capture clock, and continue to + // look for (left) edges + store_sr_req_r <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_PB_INC_CPT; + end else begin + // If we ran out of taps moving the capture clock, and we + // haven't finished edge detection, then reset the capture + // clock taps to 0 (gradually, one tap at a time... + // then exit the per-bit portion of the algorithm - + // i.e. proceed to adjust the capture clock and DQ IODELAYs as + cnt_idel_dec_cpt_r <= #TCQ 6'd63; + cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; + end + end + end + + // Increment delay for DQS + CAL1_PB_INC_CPT: begin + cal1_dlyce_cpt_r <= #TCQ 1'b1; + cal1_dlyinc_cpt_r <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_PB_INC_CPT_WAIT; + end + + // Wait for IODELAY for both capture and internal nodes within + // ISERDES to settle, before checking again for an edge + CAL1_PB_INC_CPT_WAIT: begin + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + if (!cal1_wait_r) begin + cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; + + end + end + // We've found the left edges of the windows for all DQ bits + // (actually, we found it MIN_EYE_SIZE taps ago) Decrement capture + // clock IDELAY to position just outside left edge of data window + CAL1_PB_DEC_CPT_LEFT: + if (cnt_idel_dec_cpt_r == 6'b000000) + cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT_WAIT; + else begin + cal1_dlyce_cpt_r <= #TCQ 1'b1; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; + end + + CAL1_PB_DEC_CPT_LEFT_WAIT: + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; + + // If there is skew between individual DQ bits, then after we've + // positioned the CPT clock, we will be "in the window" for some + // DQ bits ("early" DQ bits), and "out of the window" for others + // ("late" DQ bits). Increase DQ taps until we are out of the + // window for all DQ bits + CAL1_PB_DETECT_EDGE_DQ: + if (detect_edge_done_r) + if (found_edge_all_r) begin + // We're out of the window for all DQ bits in this DQS group + // We're done with per-bit deskew for this group - now decr + // capture clock IODELAY tap count back to 0, and proceed + // with the rest of stage 1 calibration for this DQS group + cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; + cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; + end else + if (!idel_tap_limit_dq_pb_r) + // If we still have DQ taps available for deskew, keep + // incrementing IODELAY tap count for the appropriate DQ bits + cal1_state_r <= #TCQ CAL1_PB_INC_DQ; + else begin + // Otherwise, stop immediately (we've done the best we can) + // and proceed with rest of stage 1 calibration + cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; + cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; + end + + CAL1_PB_INC_DQ: begin + // Increment only those DQ for which an edge hasn't been found yet + cal1_dlyce_dq_r <= #TCQ ~pb_found_edge_last_r; + cal1_dlyinc_dq_r <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_PB_INC_DQ_WAIT; + end + + CAL1_PB_INC_DQ_WAIT: + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; + + // Decrement capture clock taps back to initial value + CAL1_PB_DEC_CPT: + if (cnt_idel_dec_cpt_r == 6'b000000) + cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_WAIT; + else begin + cal1_dlyce_cpt_r <= #TCQ 1'b1; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; + end + + // Wait for capture clock to settle, then proceed to rest of + // state 1 calibration for this DQS group + CAL1_PB_DEC_CPT_WAIT: + if (!cal1_wait_r) begin + store_sr_req_r <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; + end + + // When first starting calibration for a DQS group, save the + // current value of the read data shift register, and use this + // as a reference. Note that for the first iteration of the + // edge detection loop, we will in effect be checking for an edge + // at IODELAY taps = 0 - normally, we are comparing the read data + // for IODELAY taps = N, with the read data for IODELAY taps = N-1 + // An edge can only be found at IODELAY taps = 0 if the read data + // is changing during this time (possible due to jitter) + CAL1_STORE_FIRST_WAIT: begin + mpr_dec_cpt_r <= #TCQ 1'b0; + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_PAT_DETECT; + end + + CAL1_VALID_WAIT: begin + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; + end + + CAL1_MPR_PAT_DETECT: begin + rdlvl_pi_incdec <= #TCQ 1'b0; + // MPR read leveling for centering DQS in valid window before + // OCLKDELAYED calibration begins in order to eliminate read issues + if (idel_pat_detect_valid_r == 1'b0) begin + cal1_state_r <= #TCQ CAL1_VALID_WAIT; + idel_pat_detect_valid_r <= #TCQ 1'b1; + end else if (idel_pat_detect_valid_r && idel_mpr_pat_detect_r) begin + cal1_state_r <= #TCQ CAL1_DETECT_EDGE; + idel_dec_cnt <= #TCQ 'd0; + end else if (!idelay_tap_limit_r) + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; + else + cal1_state_r <= #TCQ CAL1_RDLVL_ERR; + end + + CAL1_PAT_DETECT: begin + // All DQ bits associated with a DQS are pushed to the right one IDELAY + // tap at a time until first rising DQS is in the tri-state region + // before first rising edge window. + // The detect_edge_done_r condition included to support averaging + // during IDELAY tap increments + rdlvl_pi_incdec <= #TCQ 1'b0; + if (detect_edge_done_r) begin + if (idel_pat_data_match) begin + case (idelay_adj) + 2'b01: begin + cal1_state_r <= CAL1_DQ_IDEL_TAP_INC; + idel_dec_cnt <= #TCQ 5'd0; + idel_adj_inc <= #TCQ 1'b1; + end + 2'b10: begin //DEC by 1 + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC ; + idel_dec_cnt <= #TCQ 5'd1; + idel_adj_inc <= #TCQ 1'b0; + end + default: begin + cal1_state_r <= #TCQ CAL1_DETECT_EDGE; + idel_dec_cnt <= #TCQ 5'd0; + idel_adj_inc <= #TCQ 1'b0; + end + endcase + end else if (!idelay_tap_limit_r) begin + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; + end else begin + cal1_state_r <= #TCQ CAL1_RDLVL_ERR; + end + end + end + + // Increment IDELAY tap by 1 for DQ bits in the byte being calibrated + // until left edge of valid window detected + CAL1_DQ_IDEL_TAP_INC: begin + cal1_dq_idel_ce <= #TCQ 1'b1; + cal1_dq_idel_inc <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC_WAIT; + idel_pat_detect_valid_r <= #TCQ 1'b0; + end + + CAL1_DQ_IDEL_TAP_INC_WAIT: begin + cal1_dq_idel_ce <= #TCQ 1'b0; + cal1_dq_idel_inc <= #TCQ 1'b0; + if (!cal1_wait_r) begin + idel_adj_inc <= #TCQ 1'b0; + if (idel_adj_inc) + cal1_state_r <= #TCQ CAL1_DETECT_EDGE; + else if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) + cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; + else + cal1_state_r <= #TCQ CAL1_PAT_DETECT; + end + end + + // Decrement by 2 IDELAY taps once idel_pat_data_match detected + CAL1_DQ_IDEL_TAP_DEC: begin + cal1_dq_idel_inc <= #TCQ 1'b0; + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC_WAIT; + if (idel_dec_cnt >= 'd0) + cal1_dq_idel_ce <= #TCQ 1'b1; + else + cal1_dq_idel_ce <= #TCQ 1'b0; + if (idel_dec_cnt > 'd0) + idel_dec_cnt <= #TCQ idel_dec_cnt - 1; + else + idel_dec_cnt <= #TCQ idel_dec_cnt; + end + + CAL1_DQ_IDEL_TAP_DEC_WAIT: begin + cal1_dq_idel_ce <= #TCQ 1'b0; + cal1_dq_idel_inc <= #TCQ 1'b0; + if (!cal1_wait_r) begin + if ((idel_dec_cnt > 'd0) || (pi_rdval_cnt > 'd0)) + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; + else if (mpr_dec_cpt_r) + cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; + else + cal1_state_r <= #TCQ CAL1_DETECT_EDGE; + end + end + + // Check for presence of data eye edge. During this state, we + // sample the read data multiple times, and look for changes + // in the read data, specifically: + // 1. A change in the read data compared with the value of + // read data from the previous delay tap. This indicates + // that the most recent tap delay increment has moved us + // into either a new window, or moved/kept us in the + // transition/jitter region between windows. Note that this + // condition only needs to be checked for once, and for + // logistical purposes, we check this soon after entering + // this state (see comment in CAL1_DETECT_EDGE below for + // why this is done) + // 2. A change in the read data while we are in this state + // (i.e. in the absence of a tap delay increment). This + // indicates that we're close enough to a window edge that + // jitter will cause the read data to change even in the + // absence of a tap delay change + CAL1_DETECT_EDGE: begin + // Essentially wait for the first comparision to finish, then + // store current data into "old" data register. This store + // happens now, rather than later (e.g. when we've have already + // left this state) in order to avoid the situation the data that + // is stored as "old" data has not been used in an "active + // comparison" - i.e. data is stored after the last comparison + // of this state. In this case, we can miss an edge if the + // following sequence occurs: + // 1. Comparison completes in this state - no edge found + // 2. "Momentary jitter" occurs which "pushes" the data out the + // equivalent of one delay tap + // 3. We store this jittered data as the "old" data + // 4. "Jitter" no longer present + // 5. We increment the delay tap by one + // 6. Now we compare the current with the "old" data - they're + // the same, and no edge is detected + // NOTE: Given the large # of comparisons done in this state, it's + // highly unlikely the above sequence will occur in actual H/W + + // Wait for the first load of read data into the comparison + // shift register to finish, then load the current read data + // into the "old" data register. This allows us to do one + // initial comparision between the current read data, and + // stored data corresponding to the previous delay tap + idel_pat_detect_valid_r <= #TCQ 1'b0; + if (!store_sr_req_pulsed_r) begin + // Pulse store_sr_req_r only once in this state + store_sr_req_r <= #TCQ 1'b1; + store_sr_req_pulsed_r <= #TCQ 1'b1; + end else begin + store_sr_req_r <= #TCQ 1'b0; + store_sr_req_pulsed_r <= #TCQ 1'b1; + end + + // Continue to sample read data and look for edges until the + // appropriate time interval (shorter for simulation-only, + // much, much longer for actual h/w) has elapsed + if (detect_edge_done_r) begin + if (tap_limit_cpt_r) + // Only one edge detected and ran out of taps since only one + // bit time worth of taps available for window detection. This + // can happen if at tap 0 DQS is in previous window which results + // in only left edge being detected. Or at tap 0 DQS is in the + // current window resulting in only right edge being detected. + // Depending on the frequency this case can also happen if at + // tap 0 DQS is in the left noise region resulting in only left + // edge being detected. + cal1_state_r <= #TCQ CAL1_CALC_IDEL; + else if (found_edge_r) begin + // Sticky bit - asserted after we encounter an edge, although + // the current edge may not be considered the "first edge" this + // just means we found at least one edge + found_first_edge_r <= #TCQ 1'b1; + + // Only the right edge of the data valid window is found + // Record the inner right edge tap value + if (!found_first_edge_r && found_stable_eye_last_r) begin + if (tap_cnt_cpt_r == 'd0) + right_edge_taps_r <= #TCQ 'd0; + else + right_edge_taps_r <= #TCQ tap_cnt_cpt_r; + end + + // Both edges of data valid window found: + // If we've found a second edge after a region of stability + // then we must have just passed the second ("right" edge of + // the window. Record this second_edge_taps = current tap-1, + // because we're one past the actual second edge tap, where + // the edge taps represent the extremes of the data valid + // window (i.e. smallest & largest taps where data still valid + if (found_first_edge_r && found_stable_eye_last_r) begin + found_second_edge_r <= #TCQ 1'b1; + second_edge_taps_r <= #TCQ tap_cnt_cpt_r - 1; + cal1_state_r <= #TCQ CAL1_CALC_IDEL; + end else begin + // Otherwise, an edge was found (just not the "second" edge) + // Assuming DQS is in the correct window at tap 0 of Phaser IN + // fine tap. The first edge found is the right edge of the valid + // window and is the beginning of the jitter region hence done! + first_edge_taps_r <= #TCQ tap_cnt_cpt_r; + //wait for read stop before PI increament + cal1_state_r <= #TCQ CAL1_RD_STOP_FOR_PI_INC; + end + end else + // Otherwise, if we haven't found an edge.... + // If we still have taps left to use, then keep incrementing + //wait for read stop before PI increament + cal1_state_r <= #TCQ CAL1_RD_STOP_FOR_PI_INC; + end + end + + //before increment PI, read command sending should be stopped. + //Also need to wait existing read is finished + CAL1_RD_STOP_FOR_PI_INC: begin + rdlvl_pi_incdec <= #TCQ 1'b1; + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT; + end + + // Increment Phaser_IN delay for DQS + CAL1_IDEL_INC_CPT: begin + cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT_WAIT; + if (~tap_limit_cpt_r) begin + cal1_dlyce_cpt_r <= #TCQ 1'b1; + cal1_dlyinc_cpt_r <= #TCQ 1'b1; + end else begin + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + end + end + + // Wait for Phaser_In to settle, before checking again for an edge + CAL1_IDEL_INC_CPT_WAIT: begin + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + if (!cal1_wait_r) begin + cal1_state_r <= #TCQ CAL1_DETECT_EDGE; + rdlvl_pi_incdec <= #TCQ 1'b0; //return to normal read + end + end + + // Calculate final value of Phaser_IN taps. At this point, one or both + // edges of data eye have been found, and/or all taps have been + // exhausted looking for the edges + // NOTE: We're calculating the amount to decrement by, not the + // absolute setting for DQS. + CAL1_CALC_IDEL: begin + // CASE1: If 2 edges found. + if (found_second_edge_r) + cnt_idel_dec_cpt_r + <= #TCQ ((second_edge_taps_r - + first_edge_taps_r)>>1) + 1; + else if (right_edge_taps_r > 6'd0) + // Only right edge detected + // right_edge_taps_r is the inner right edge tap value + // hence used for calculation + cnt_idel_dec_cpt_r + <= #TCQ (tap_cnt_cpt_r - (right_edge_taps_r>>1)); + else if (found_first_edge_r) + // Only left edge detected + cnt_idel_dec_cpt_r + <= #TCQ ((tap_cnt_cpt_r - first_edge_taps_r)>>1); + else + cnt_idel_dec_cpt_r + <= #TCQ (tap_cnt_cpt_r>>1); + // Now use the value we just calculated to decrement CPT taps + // to the desired calibration point + //cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; + cal1_state_r <= #TCQ CAL1_CENTER_WAIT; + rdlvl_pi_incdec <= #TCQ 1'b1; + end + + CAL1_CENTER_WAIT: begin + if(!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; + end + // decrement capture clock for final adjustment - center + // capture clock in middle of data eye. This adjustment will occur + // only when both the edges are found usign CPT taps. Must do this + // incrementally to avoid clock glitching (since CPT drives clock + // divider within each ISERDES) + CAL1_IDEL_DEC_CPT: begin + cal1_dlyce_cpt_r <= #TCQ 1'b1; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + // once adjustment is complete, we're done with calibration for + // this DQS, repeat for next DQS + cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; + if (cnt_idel_dec_cpt_r == 6'b000001) begin + if (mpr_dec_cpt_r) begin + if (|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) begin + idel_dec_cnt <= #TCQ idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; + end else + cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; + end else + cal1_state_r <= #TCQ CAL1_NEXT_DQS; + end else + cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT; + end + + CAL1_IDEL_DEC_CPT_WAIT: begin + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; + end + + // Determine whether we're done, or have more DQS's to calibrate + // Also request precharge after every byte, as appropriate + CAL1_NEXT_DQS: begin + //if (mpr_rdlvl_done_r || (DRAM_TYPE == "DDR2")) + cal1_prech_req_r <= #TCQ 1'b1; + //else + // cal1_prech_req_r <= #TCQ 1'b0; + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + // Prepare for another iteration with next DQS group + found_first_edge_r <= #TCQ 1'b0; + found_second_edge_r <= #TCQ 1'b0; + first_edge_taps_r <= #TCQ 'd0; + second_edge_taps_r <= #TCQ 'd0; + right_edge_taps_r <= #TCQ 'd0; + if ((SIM_CAL_OPTION == "FAST_CAL") || + (cal1_cnt_cpt_r >= DQS_WIDTH-1)) begin + if (mpr_rdlvl_done_r) begin + rdlvl_last_byte_done_int <= #TCQ 1'b1; + mpr_last_byte_done <= #TCQ 1'b0; + end else begin + rdlvl_last_byte_done_int <= #TCQ 1'b0; + mpr_last_byte_done <= #TCQ 1'b1; + end + end + + // Wait until precharge that occurs in between calibration of + // DQS groups is finished + if (prech_done) begin // || (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))) begin + if (SIM_CAL_OPTION == "FAST_CAL") begin + //rdlvl_rank_done_r <= #TCQ 1'b1; + rdlvl_last_byte_done_int <= #TCQ 1'b0; + mpr_last_byte_done <= #TCQ 1'b0; + cal1_state_r <= #TCQ CAL1_DONE; //CAL1_REGL_LOAD; + end else if (cal1_cnt_cpt_r >= DQS_WIDTH-1) begin + if (~mpr_rdlvl_done_r) begin + mpr_rank_done_r <= #TCQ 1'b1; + // if (rnk_cnt_r == RANKS-1) begin + // All DQS groups in all ranks done + cal1_state_r <= #TCQ CAL1_DONE; + cal1_cnt_cpt_r <= #TCQ 'b0; + // end else begin + // // Process DQS groups in next rank + // rnk_cnt_r <= #TCQ rnk_cnt_r + 1; + // new_cnt_cpt_r <= #TCQ 1'b1; + // cal1_cnt_cpt_r <= #TCQ 'b0; + // cal1_state_r <= #TCQ CAL1_IDLE; + // end + end else begin + // All DQS groups in a rank done + rdlvl_rank_done_r <= #TCQ 1'b1; + if (rnk_cnt_r == RANKS-1) begin + // All DQS groups in all ranks done + cal1_state_r <= #TCQ CAL1_REGL_LOAD; + end else begin + // Process DQS groups in next rank + rnk_cnt_r <= #TCQ rnk_cnt_r + 1; + new_cnt_cpt_r <= #TCQ 1'b1; + cal1_cnt_cpt_r <= #TCQ 'b0; + cal1_state_r <= #TCQ CAL1_IDLE; + end + end + end else begin + // Process next DQS group + new_cnt_cpt_r <= #TCQ 1'b1; + cal1_cnt_cpt_r <= #TCQ cal1_cnt_cpt_r + 1; + cal1_state_r <= #TCQ CAL1_NEW_DQS_PREWAIT; + end + end + end + + CAL1_NEW_DQS_PREWAIT: begin + if (!cal1_wait_r) begin + rdlvl_pi_incdec <= #TCQ 1'b0; + if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) + cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; + else + cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; + end + end + + // Load rank registers in Phaser_IN + CAL1_REGL_LOAD: begin + rdlvl_rank_done_r <= #TCQ 1'b0; + mpr_rank_done_r <= #TCQ 1'b0; + cal1_prech_req_r <= #TCQ 1'b0; + cal1_cnt_cpt_r <= #TCQ 'b0; + rnk_cnt_r <= #TCQ 2'b00; + if ((regl_rank_cnt == RANKS-1) && + ((regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1))) begin + cal1_state_r <= #TCQ CAL1_DONE; + rdlvl_last_byte_done_int <= #TCQ 1'b0; + mpr_last_byte_done <= #TCQ 1'b0; + end else + cal1_state_r <= #TCQ CAL1_REGL_LOAD; + end + + CAL1_RDLVL_ERR: begin + rdlvl_stg1_err <= #TCQ 1'b1; + end + + // Done with this stage of calibration + // if used, allow DEBUG_PORT to control taps + CAL1_DONE: begin + mpr_rdlvl_done_r <= #TCQ 1'b1; + cal1_prech_req_r <= #TCQ 1'b0; + if (~mpr_rdlvl_done_r && (OCAL_EN=="ON") && (DRAM_TYPE == "DDR3")) begin + rdlvl_stg1_done_int <= #TCQ 1'b0; + cal1_state_r <= #TCQ CAL1_IDLE; + end else + rdlvl_stg1_done_int <= #TCQ 1'b1; + end + + endcase + end +// verilint STARC-2.2.3.3 on + + + + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_tempmon.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_tempmon.v new file mode 100644 index 0000000..1719afd --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_tempmon.v @@ -0,0 +1,559 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : mig_7series_v4_0_ddr_phy_tempmon.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Dec 20 2013 +// \___\/\___\ +// +//Device : 7 Series +//Design Name : DDR3 SDRAM +//Purpose : Monitors chip temperature via the XADC and adjusts the +// stage 2 tap values as appropriate. +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_0_ddr_phy_tempmon # +( + parameter SKIP_CALIB = "FALSE", + parameter TCQ = 100, // Register delay (simulation only) + // Temperature bands must be in order. To disable bands, set to extreme. + parameter TEMP_INCDEC = 1465, // Degrees C * 100 (14.65 * 100) + parameter TEMP_HYST = 1, + parameter TEMP_MIN_LIMIT = 12'h8ac, + parameter TEMP_MAX_LIMIT = 12'hca4 +) +( + input clk, // Fabric clock + input rst, // System reset + input calib_complete, // Calibration complete + input tempmon_sample_en, // Signal to enable sampling + input [11:0] device_temp, // Current device temperature + input [11:0] calib_device_temp, // Calibration device temperature + output tempmon_pi_f_inc, // Increment PHASER_IN taps + output tempmon_pi_f_dec, // Decrement PHASER_IN taps + output tempmon_sel_pi_incdec, // Assume control of PHASER_IN taps + output tempmon_done_skip +); + + // translate hysteresis into XADC units + localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504; + + localparam TEMP_INCDEC_OFFSET = ((TEMP_INCDEC * 4096) / 50400) ; + + // Temperature sampler FSM encoding + localparam IDLE = 11'b000_0000_0001; + localparam INIT = 11'b000_0000_0010; + localparam FOUR_INC = 11'b000_0000_0100; + localparam THREE_INC = 11'b000_0000_1000; + localparam TWO_INC = 11'b000_0001_0000; + localparam ONE_INC = 11'b000_0010_0000; + localparam NEUTRAL = 11'b000_0100_0000; + localparam ONE_DEC = 11'b000_1000_0000; + localparam TWO_DEC = 11'b001_0000_0000; + localparam THREE_DEC = 11'b010_0000_0000; + localparam FOUR_DEC = 11'b100_0000_0000; + + + //=========================================================================== + // Reg declarations + //=========================================================================== + + // Output port flops. Inc and dec are mutex. + reg pi_f_dec; // Flop output + reg pi_f_inc; // Flop output + reg pi_f_dec_nxt; // FSM output + reg pi_f_inc_nxt; // FSM output + + // FSM state + reg [10:0] tempmon_state; + reg [10:0] tempmon_state_nxt; + + // FSM output used to capture the initial device termperature + reg tempmon_state_init; + + // Flag to indicate the initial device temperature is captured and normal operation can begin + reg tempmon_init_complete; + + // Temperature band/state boundaries + reg [11:0] four_inc_max_limit; + reg [11:0] three_inc_max_limit; + reg [11:0] two_inc_max_limit; + reg [11:0] one_inc_max_limit; + reg [11:0] neutral_max_limit; + reg [11:0] one_dec_max_limit; + reg [11:0] two_dec_max_limit; + reg [11:0] three_dec_max_limit; + reg [11:0] three_inc_min_limit; + reg [11:0] two_inc_min_limit; + reg [11:0] one_inc_min_limit; + reg [11:0] neutral_min_limit; + reg [11:0] one_dec_min_limit; + reg [11:0] two_dec_min_limit; + reg [11:0] three_dec_min_limit; + reg [11:0] four_dec_min_limit; + reg [11:0] device_temp_init; + + // Flops for capturing and storing the current device temperature + reg tempmon_sample_en_101; + reg tempmon_sample_en_102; + reg [11:0] device_temp_101; + reg [11:0] device_temp_capture_102; + reg update_temp_102; + + // Flops for comparing temperature to max limits + reg temp_cmp_four_inc_max_102; + reg temp_cmp_three_inc_max_102; + reg temp_cmp_two_inc_max_102; + reg temp_cmp_one_inc_max_102; + reg temp_cmp_neutral_max_102; + reg temp_cmp_one_dec_max_102; + reg temp_cmp_two_dec_max_102; + reg temp_cmp_three_dec_max_102; + + // Flops for comparing temperature to min limits + reg temp_cmp_three_inc_min_102; + reg temp_cmp_two_inc_min_102; + reg temp_cmp_one_inc_min_102; + reg temp_cmp_neutral_min_102; + reg temp_cmp_one_dec_min_102; + reg temp_cmp_two_dec_min_102; + reg temp_cmp_three_dec_min_102; + reg temp_cmp_four_dec_min_102; + + reg calib_complete_r; + reg tempmon_done; + reg [2:0] sample_en_cnt; + + always @ (posedge clk) + calib_complete_r <= #TCQ calib_complete; + + wire [11:0] device_temp_in = ((tempmon_state_init | ~calib_complete_r) & (SKIP_CALIB == "TRUE")) ? calib_device_temp : device_temp; + + always @ (posedge clk) begin + if (rst) + sample_en_cnt <= #TCQ 'd0; + else if ((tempmon_sample_en & ~tempmon_sample_en_101) & ((SKIP_CALIB == "TRUE")) & (sample_en_cnt < 'd5)) + sample_en_cnt <= #TCQ sample_en_cnt + 1; + end + + always @ (posedge clk) begin + if (rst) + tempmon_done <= #TCQ 1'b0; + else if ((sample_en_cnt == 'd5) & ((SKIP_CALIB == "TRUE"))) + tempmon_done <= #TCQ 1'b1; + end + + assign tempmon_done_skip = tempmon_done; + + //=========================================================================== + // Overview and temperature band limits + //=========================================================================== + + // The main feature of the tempmon block is an FSM that tracks the temerature provided by the ADC and decides if the phaser needs to be adjusted. The FSM + // has nine temperature bands or states, centered around an initial device temperature. The name of each state is the net number of phaser increments or + // decrements that have been issued in getting to the state. There are two temperature boundaries or limits between adjacent states. These two boundaries are + // offset by a small amount to provide hysteresis. The max limits are the boundaries that are used to determine when to move to the next higher temperature state + // and decrement the phaser. The min limits determine when to move to the next lower temperature state and increment the phaser. The limits are calculated when + // the initial device temperature is taken, and will always be at fixed offsets from the initial device temperature. States with limits below 0C or above + // 125C will never be entered. + + // Temperature lowest highest + // <------------------------------------------------------------------------------------------------------------------------------------------------> + // + // Temp four three two one neutral one two three four + // band/state inc inc inc inc dec dec dec dec + // + // Max limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| + // Min limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| | + // | | | | | | | + // | | | | | | | + // three_inc_min_limit | HYST_OFFSET--->| |<-- | four_dec_min_limit | + // | device_temp_init | + // four_inc_max_limit three_dec_max_limit + + + + // Boundaries for moving from lower temp bands to higher temp bands. + // Note that only three_dec_max_limit can roll over, assuming device_temp_init is between 0C and 125C and TEMP_INCDEC_OFFSET is 14.65C, + // and none of the min or max limits can roll under. So three_dec_max_limit has a check for being out of the 0x0 to 0xFFF range. + wire [11:0] four_inc_max_limit_nxt = device_temp_init - 7*TEMP_INCDEC_OFFSET; // upper boundary of lowest temp band + wire [11:0] three_inc_max_limit_nxt = device_temp_init - 5*TEMP_INCDEC_OFFSET; + wire [11:0] two_inc_max_limit_nxt = device_temp_init - 3*TEMP_INCDEC_OFFSET; + wire [11:0] one_inc_max_limit_nxt = device_temp_init - TEMP_INCDEC_OFFSET; + wire [11:0] neutral_max_limit_nxt = device_temp_init + TEMP_INCDEC_OFFSET; // upper boundary of init temp band + wire [11:0] one_dec_max_limit_nxt = device_temp_init + 3*TEMP_INCDEC_OFFSET; + wire [11:0] two_dec_max_limit_nxt = device_temp_init + 5*TEMP_INCDEC_OFFSET; + wire [12:0] three_dec_max_limit_tmp = device_temp_init + 7*TEMP_INCDEC_OFFSET; // upper boundary of 2nd highest temp band + wire [11:0] three_dec_max_limit_nxt = three_dec_max_limit_tmp[12] ? 12'hFFF : three_dec_max_limit_tmp[11:0]; + + + // Boundaries for moving from higher temp bands to lower temp bands + wire [11:0] three_inc_min_limit_nxt = four_inc_max_limit - HYST_OFFSET; // lower boundary of 2nd lowest temp band + wire [11:0] two_inc_min_limit_nxt = three_inc_max_limit - HYST_OFFSET; + wire [11:0] one_inc_min_limit_nxt = two_inc_max_limit - HYST_OFFSET; + wire [11:0] neutral_min_limit_nxt = one_inc_max_limit - HYST_OFFSET; // lower boundary of init temp band + wire [11:0] one_dec_min_limit_nxt = neutral_max_limit - HYST_OFFSET; + wire [11:0] two_dec_min_limit_nxt = one_dec_max_limit - HYST_OFFSET; + wire [11:0] three_dec_min_limit_nxt = two_dec_max_limit - HYST_OFFSET; + wire [11:0] four_dec_min_limit_nxt = three_dec_max_limit - HYST_OFFSET; // lower boundary of highest temp band + + + + //=========================================================================== + // Capture device temperature + //=========================================================================== + + // There is a three stage pipeline used to capture temperature, calculate the next state + // of the FSM, and update the tempmon outputs. + // + // Stage 100 Inputs device_temp and tempmon_sample_en become valid and are flopped. + // Input device_temp is compared to ADC codes for 0C and 125C and limited + // at the flop input if needed. + // + // Stage 101 The flopped version of device_temp is compared to the FSM temperature band boundaries + // to determine if a state change is needed. State changes are only enabled on the + // rising edge of the flopped tempmon_sample_en signal. If there is a state change a phaser + // increment or decrement signal is generated and flopped. + // + // Stage 102 The flopped versions of the phaser inc/dec signals drive the module outputs. + + // Limit device_temp to 0C to 125C and assign it to flop input device_temp_100 + // temp C = ( ( ADC CODE * 503.975 ) / 4096 ) - 273.15 + wire device_temp_high = device_temp_in > TEMP_MAX_LIMIT; + wire device_temp_low = device_temp_in < TEMP_MIN_LIMIT; + wire [11:0] device_temp_100 = ( { 12 { device_temp_high } } & TEMP_MAX_LIMIT ) + | ( { 12 { device_temp_low } } & TEMP_MIN_LIMIT ) + | ( { 12 { ~device_temp_high & ~device_temp_low } } & device_temp_in ); + + // Capture/hold the initial temperature used in setting temperature bands and set init complete flag + // to enable normal sample operation. + wire [11:0] device_temp_init_nxt = tempmon_state_init ? device_temp_101 : device_temp_init; + wire tempmon_init_complete_nxt = tempmon_state_init ? 1'b1 : tempmon_init_complete; + + // Capture/hold the current temperature on the sample enable signal rising edge after init is complete. + // The captured current temp is not used functionaly. It is just useful for debug and waveform review. + wire update_temp_101 = tempmon_init_complete & ~tempmon_sample_en_102 & tempmon_sample_en_101; + wire [11:0] device_temp_capture_101 = update_temp_101 ? device_temp_101 : device_temp_capture_102; + + + //=========================================================================== + // Generate FSM arc signals + //=========================================================================== + + // Temperature comparisons for increasing temperature. + wire temp_cmp_four_inc_max_101 = device_temp_101 >= four_inc_max_limit ; + wire temp_cmp_three_inc_max_101 = device_temp_101 >= three_inc_max_limit ; + wire temp_cmp_two_inc_max_101 = device_temp_101 >= two_inc_max_limit ; + wire temp_cmp_one_inc_max_101 = device_temp_101 >= one_inc_max_limit ; + wire temp_cmp_neutral_max_101 = device_temp_101 >= neutral_max_limit ; + wire temp_cmp_one_dec_max_101 = device_temp_101 >= one_dec_max_limit ; + wire temp_cmp_two_dec_max_101 = device_temp_101 >= two_dec_max_limit ; + wire temp_cmp_three_dec_max_101 = device_temp_101 >= three_dec_max_limit ; + + // Temperature comparisons for decreasing temperature. + wire temp_cmp_three_inc_min_101 = device_temp_101 < three_inc_min_limit ; + wire temp_cmp_two_inc_min_101 = device_temp_101 < two_inc_min_limit ; + wire temp_cmp_one_inc_min_101 = device_temp_101 < one_inc_min_limit ; + wire temp_cmp_neutral_min_101 = device_temp_101 < neutral_min_limit ; + wire temp_cmp_one_dec_min_101 = device_temp_101 < one_dec_min_limit ; + wire temp_cmp_two_dec_min_101 = device_temp_101 < two_dec_min_limit ; + wire temp_cmp_three_dec_min_101 = device_temp_101 < three_dec_min_limit ; + wire temp_cmp_four_dec_min_101 = device_temp_101 < four_dec_min_limit ; + + // FSM arcs for increasing temperature. + wire temp_gte_four_inc_max = update_temp_102 & temp_cmp_four_inc_max_102; + wire temp_gte_three_inc_max = update_temp_102 & temp_cmp_three_inc_max_102; + wire temp_gte_two_inc_max = update_temp_102 & temp_cmp_two_inc_max_102; + wire temp_gte_one_inc_max = update_temp_102 & temp_cmp_one_inc_max_102; + wire temp_gte_neutral_max = update_temp_102 & temp_cmp_neutral_max_102; + wire temp_gte_one_dec_max = update_temp_102 & temp_cmp_one_dec_max_102; + wire temp_gte_two_dec_max = update_temp_102 & temp_cmp_two_dec_max_102; + wire temp_gte_three_dec_max = update_temp_102 & temp_cmp_three_dec_max_102; + + // FSM arcs for decreasing temperature. + wire temp_lte_three_inc_min = update_temp_102 & temp_cmp_three_inc_min_102; + wire temp_lte_two_inc_min = update_temp_102 & temp_cmp_two_inc_min_102; + wire temp_lte_one_inc_min = update_temp_102 & temp_cmp_one_inc_min_102; + wire temp_lte_neutral_min = update_temp_102 & temp_cmp_neutral_min_102; + wire temp_lte_one_dec_min = update_temp_102 & temp_cmp_one_dec_min_102; + wire temp_lte_two_dec_min = update_temp_102 & temp_cmp_two_dec_min_102; + wire temp_lte_three_dec_min = update_temp_102 & temp_cmp_three_dec_min_102; + wire temp_lte_four_dec_min = update_temp_102 & temp_cmp_four_dec_min_102; + + + //=========================================================================== + // Implement FSM + //=========================================================================== + + // In addition to the nine temperature states, there are also IDLE and INIT states. + // The INIT state triggers the calculation of the temperature boundaries between the + // other states. After INIT, the FSM will always go to the NEUTRAL state. There is + // no timing restriction required between calib_complete and tempmon_sample_en. + + always @(*) begin + + tempmon_state_nxt = tempmon_state; + tempmon_state_init = 1'b0; + pi_f_inc_nxt = 1'b0; + pi_f_dec_nxt = 1'b0; + + casez (tempmon_state) + IDLE: begin + if (calib_complete) tempmon_state_nxt = INIT; + end + INIT: begin + tempmon_state_nxt = NEUTRAL; + tempmon_state_init = 1'b1; + end + FOUR_INC: begin + if (temp_gte_four_inc_max) begin + tempmon_state_nxt = THREE_INC; + pi_f_dec_nxt = 1'b1; + end + end + THREE_INC: begin + if (temp_gte_three_inc_max) begin + tempmon_state_nxt = TWO_INC; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_three_inc_min) begin + tempmon_state_nxt = FOUR_INC; + pi_f_inc_nxt = 1'b1; + end + end + TWO_INC: begin + if (temp_gte_two_inc_max) begin + tempmon_state_nxt = ONE_INC; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_two_inc_min) begin + tempmon_state_nxt = THREE_INC; + pi_f_inc_nxt = 1'b1; + end + end + ONE_INC: begin + if (temp_gte_one_inc_max) begin + tempmon_state_nxt = NEUTRAL; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_one_inc_min) begin + tempmon_state_nxt = TWO_INC; + pi_f_inc_nxt = 1'b1; + end + end + NEUTRAL: begin + if (temp_gte_neutral_max) begin + tempmon_state_nxt = ONE_DEC; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_neutral_min) begin + tempmon_state_nxt = ONE_INC; + pi_f_inc_nxt = 1'b1; + end + end + ONE_DEC: begin + if (temp_gte_one_dec_max) begin + tempmon_state_nxt = TWO_DEC; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_one_dec_min) begin + tempmon_state_nxt = NEUTRAL; + pi_f_inc_nxt = 1'b1; + end + end + TWO_DEC: begin + if (temp_gte_two_dec_max) begin + tempmon_state_nxt = THREE_DEC; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_two_dec_min) begin + tempmon_state_nxt = ONE_DEC; + pi_f_inc_nxt = 1'b1; + end + end + THREE_DEC: begin + if (temp_gte_three_dec_max) begin + tempmon_state_nxt = FOUR_DEC; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_three_dec_min) begin + tempmon_state_nxt = TWO_DEC; + pi_f_inc_nxt = 1'b1; + end + end + FOUR_DEC: begin + if (temp_lte_four_dec_min) begin + tempmon_state_nxt = THREE_DEC; + pi_f_inc_nxt = 1'b1; + end + end + default: begin + tempmon_state_nxt = IDLE; + end + endcase + + end //always + +//synopsys translate_off +reg [71:0] tempmon_state_name; +always @(*) casez (tempmon_state) + IDLE : tempmon_state_name = "IDLE"; + INIT : tempmon_state_name = "INIT"; + FOUR_INC : tempmon_state_name = "FOUR_INC"; + THREE_INC : tempmon_state_name = "THREE_INC"; + TWO_INC : tempmon_state_name = "TWO_INC"; + ONE_INC : tempmon_state_name = "ONE_INC"; + NEUTRAL : tempmon_state_name = "NEUTRAL"; + ONE_DEC : tempmon_state_name = "ONE_DEC"; + TWO_DEC : tempmon_state_name = "TWO_DEC"; + THREE_DEC : tempmon_state_name = "THREE_DEC"; + FOUR_DEC : tempmon_state_name = "FOUR_DEC"; + default : tempmon_state_name = "BAD_STATE"; +endcase +//synopsys translate_on + + //=========================================================================== + // Generate final output and implement flops + //=========================================================================== + + // Generate output + assign tempmon_pi_f_inc = pi_f_inc; + assign tempmon_pi_f_dec = pi_f_dec; + assign tempmon_sel_pi_incdec = pi_f_inc | pi_f_dec; + + + // Implement reset flops + always @(posedge clk) begin + if(rst) begin + tempmon_state <= #TCQ 11'b000_0000_0001; + pi_f_inc <= #TCQ 1'b0; + pi_f_dec <= #TCQ 1'b0; + four_inc_max_limit <= #TCQ 12'b0; + three_inc_max_limit <= #TCQ 12'b0; + two_inc_max_limit <= #TCQ 12'b0; + one_inc_max_limit <= #TCQ 12'b0; + neutral_max_limit <= #TCQ 12'b0; + one_dec_max_limit <= #TCQ 12'b0; + two_dec_max_limit <= #TCQ 12'b0; + three_dec_max_limit <= #TCQ 12'b0; + three_inc_min_limit <= #TCQ 12'b0; + two_inc_min_limit <= #TCQ 12'b0; + one_inc_min_limit <= #TCQ 12'b0; + neutral_min_limit <= #TCQ 12'b0; + one_dec_min_limit <= #TCQ 12'b0; + two_dec_min_limit <= #TCQ 12'b0; + three_dec_min_limit <= #TCQ 12'b0; + four_dec_min_limit <= #TCQ 12'b0; + device_temp_init <= #TCQ 12'b0; + tempmon_init_complete <= #TCQ 1'b0; + tempmon_sample_en_101 <= #TCQ 1'b0; + tempmon_sample_en_102 <= #TCQ 1'b0; + device_temp_101 <= #TCQ 12'b0; + device_temp_capture_102 <= #TCQ 12'b0; + end + else begin + tempmon_state <= #TCQ tempmon_state_nxt; + pi_f_inc <= #TCQ pi_f_inc_nxt; + pi_f_dec <= #TCQ pi_f_dec_nxt; + four_inc_max_limit <= #TCQ four_inc_max_limit_nxt; + three_inc_max_limit <= #TCQ three_inc_max_limit_nxt; + two_inc_max_limit <= #TCQ two_inc_max_limit_nxt; + one_inc_max_limit <= #TCQ one_inc_max_limit_nxt; + neutral_max_limit <= #TCQ neutral_max_limit_nxt; + one_dec_max_limit <= #TCQ one_dec_max_limit_nxt; + two_dec_max_limit <= #TCQ two_dec_max_limit_nxt; + three_dec_max_limit <= #TCQ three_dec_max_limit_nxt; + three_inc_min_limit <= #TCQ three_inc_min_limit_nxt; + two_inc_min_limit <= #TCQ two_inc_min_limit_nxt; + one_inc_min_limit <= #TCQ one_inc_min_limit_nxt; + neutral_min_limit <= #TCQ neutral_min_limit_nxt; + one_dec_min_limit <= #TCQ one_dec_min_limit_nxt; + two_dec_min_limit <= #TCQ two_dec_min_limit_nxt; + three_dec_min_limit <= #TCQ three_dec_min_limit_nxt; + four_dec_min_limit <= #TCQ four_dec_min_limit_nxt; + device_temp_init <= #TCQ device_temp_init_nxt; + tempmon_init_complete <= #TCQ tempmon_init_complete_nxt; + tempmon_sample_en_101 <= #TCQ tempmon_sample_en; + tempmon_sample_en_102 <= #TCQ tempmon_sample_en_101; + device_temp_101 <= #TCQ device_temp_100; + device_temp_capture_102 <= #TCQ device_temp_capture_101; + end + end + + // Implement non-reset flops + always @(posedge clk) begin + temp_cmp_four_inc_max_102 <= #TCQ temp_cmp_four_inc_max_101; + temp_cmp_three_inc_max_102 <= #TCQ temp_cmp_three_inc_max_101; + temp_cmp_two_inc_max_102 <= #TCQ temp_cmp_two_inc_max_101; + temp_cmp_one_inc_max_102 <= #TCQ temp_cmp_one_inc_max_101; + temp_cmp_neutral_max_102 <= #TCQ temp_cmp_neutral_max_101; + temp_cmp_one_dec_max_102 <= #TCQ temp_cmp_one_dec_max_101; + temp_cmp_two_dec_max_102 <= #TCQ temp_cmp_two_dec_max_101; + temp_cmp_three_dec_max_102 <= #TCQ temp_cmp_three_dec_max_101; + temp_cmp_three_inc_min_102 <= #TCQ temp_cmp_three_inc_min_101; + temp_cmp_two_inc_min_102 <= #TCQ temp_cmp_two_inc_min_101; + temp_cmp_one_inc_min_102 <= #TCQ temp_cmp_one_inc_min_101; + temp_cmp_neutral_min_102 <= #TCQ temp_cmp_neutral_min_101; + temp_cmp_one_dec_min_102 <= #TCQ temp_cmp_one_dec_min_101; + temp_cmp_two_dec_min_102 <= #TCQ temp_cmp_two_dec_min_101; + temp_cmp_three_dec_min_102 <= #TCQ temp_cmp_three_dec_min_101; + temp_cmp_four_dec_min_102 <= #TCQ temp_cmp_four_dec_min_101; + update_temp_102 <= #TCQ update_temp_101; + end + + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_top.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_top.v new file mode 100644 index 0000000..9c084c6 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_top.v @@ -0,0 +1,1444 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 4.0 +// \ \ Application : MIG +// / / Filename : ddr_phy_top.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Aug 03 2009 +// \___\/\___\ +// +//Device : 7 Series +//Design Name : DDR3 SDRAM +//Purpose : Top level memory interface block. Instantiates a clock +// and reset generator, the memory controller, the phy and +// the user interface blocks. +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_0_ddr_phy_top # + ( + parameter TCQ = 100, // Register delay (simulation only) + parameter DDR3_VDD_OP_VOLT = 135, // Voltage mode used for DDR3 + parameter AL = "0", // Additive Latency option + parameter BANK_WIDTH = 3, // # of bank bits + parameter BURST_MODE = "8", // Burst length + parameter BURST_TYPE = "SEQ", // Burst type + parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank + parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory + parameter CL = 5, + parameter COL_WIDTH = 12, // column address width + parameter CS_WIDTH = 1, // # of unique CS outputs + parameter CKE_WIDTH = 1, // # of cke outputs + parameter CWL = 5, + parameter DM_WIDTH = 8, // # of DM (data mask) + parameter DQ_WIDTH = 64, // # of DQ (data) + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_TYPE = "DDR3", + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides + parameter LP_DDR_CK_WIDTH = 2, + + // Hard PHY parameters + parameter PHYCTL_CMD_FIFO = "FALSE", + // five fields, one per possible I/O bank, 4 bits in each field, + // 1 per lane data=1/ctl=0 + parameter DATA_CTL_B0 = 4'hc, + parameter DATA_CTL_B1 = 4'hf, + parameter DATA_CTL_B2 = 4'hf, + parameter DATA_CTL_B3 = 4'hf, + parameter DATA_CTL_B4 = 4'hf, + // defines the byte lanes in I/O banks being used in the interface + // 1- Used, 0- Unused + parameter BYTE_LANES_B0 = 4'b1111, + parameter BYTE_LANES_B1 = 4'b0000, + parameter BYTE_LANES_B2 = 4'b0000, + parameter BYTE_LANES_B3 = 4'b0000, + parameter BYTE_LANES_B4 = 4'b0000, + // defines the bit lanes in I/O banks being used in the interface. Each + // parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused + parameter PHY_0_BITLANES = 48'h0000_0000_0000, + parameter PHY_1_BITLANES = 48'h0000_0000_0000, + parameter PHY_2_BITLANES = 48'h0000_0000_0000, + + // control/address/data pin mapping parameters + parameter CK_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, + parameter ADDR_MAP + = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, + parameter BANK_MAP = 36'h000_000_000, + parameter CAS_MAP = 12'h000, + parameter CKE_ODT_BYTE_MAP = 8'h00, + parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000, + parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000, + parameter CKE_ODT_AUX = "FALSE", + parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, + parameter PARITY_MAP = 12'h000, + parameter RAS_MAP = 12'h000, + parameter WE_MAP = 12'h000, + parameter DQS_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, + parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, + parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, + parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, + + // This parameter must be set based on memory clock frequency + // It must be set to 4 for frequencies above 533 MHz?? (undecided) + // and set to 2 for 533 MHz and below + parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly + parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK + parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank + parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T" + parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" + parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" + parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" + parameter IODELAY_GRP = "IODELAY_MIG", + parameter FPGA_SPEED_GRADE = 1, + parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option + parameter OUTPUT_DRV = "HIGH", // to calib_top + parameter REG_CTRL = "OFF", // to calib_top + parameter RTT_NOM = "60", // to calib_top + parameter RTT_WR = "120", // to calib_top + parameter tCK = 2500, // pS + parameter tRFC = 110000, // pS + parameter tREFI = 7800000, // pS + parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 + parameter WRLVL = "OFF", // to calib_top + parameter DEBUG_PORT = "OFF", // to calib_top + parameter RANKS = 4, + parameter ODT_WIDTH = 1, + parameter ROW_WIDTH = 16, // DRAM address bus width + parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000, + // calibration Address. The address given below will be used for calibration + // read and write operations. + parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address + parameter CALIB_COL_ADD = 12'h000, // Calibration column address + parameter CALIB_BA_ADD = 3'h0, // Calibration bank address + // Simulation /debug options + parameter SIM_BYPASS_INIT_CAL = "OFF", + // Parameter used to force skipping + // or abbreviation of initialization + // and calibration. Overrides + // SIM_INIT_OPTION, SIM_CAL_OPTION, + // and disables various other blocks + //parameter SIM_INIT_OPTION = "SKIP_PU_DLY", // Skip various init steps + //parameter SIM_CAL_OPTION = "NONE", // Skip various calib steps + parameter REFCLK_FREQ = 200.0, // IODELAY ref clock freq (MHz) + parameter USE_CS_PORT = 1, // Support chip select output + parameter USE_DM_PORT = 1, // Support data mask output + parameter USE_ODT_PORT = 1, // Support ODT output + parameter RD_PATH_REG = 0, // optional registers in the read path + // to MC for timing improvement. + // =1 enabled, = 0 disabled + parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change + parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl + parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation + parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering + parameter TAPSPERKCLK = 56, + parameter POC_USE_METASTABLE_SAMP = "FALSE", + parameter SKIP_CALIB = "FALSE", + parameter FPGA_VOLT_TYPE = "N" + ) + ( + input clk, // Fabric logic clock + // To MC, calib_top, hard PHY + input clk_div2, // mem_refclk divided by 2 for PI incdec + input rst_div2, // reset in clk_div2 domain + input clk_ref, // Idelay_ctrl reference clock + // To hard PHY (external source) + input freq_refclk, // To hard PHY for Phasers + input mem_refclk, // Memory clock to hard PHY + input pll_lock, // System PLL lock signal + input sync_pulse, // 1/N sync pulse used to synchronize all PHASERS + input mmcm_ps_clk, // Phase shift clock for oclk stg3 centering + input poc_sample_pd, // Tell POC how to avoid metastability. + + input error, // Support for TG error detect + output rst_tg_mc, // Support for TG error detect + + input [11:0] device_temp, + input tempmon_sample_en, + + input dbg_sel_pi_incdec, + input dbg_sel_po_incdec, + input [DQS_CNT_WIDTH:0] dbg_byte_sel, + input dbg_pi_f_inc, + input dbg_pi_f_dec, + input dbg_po_f_inc, + input dbg_po_f_stg23_sel, + input dbg_po_f_dec, + input dbg_idel_down_all, + input dbg_idel_down_cpt, + input dbg_idel_up_all, + input dbg_idel_up_cpt, + input dbg_sel_all_idel_cpt, + input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, + input rst, + input iddr_rst, + input [7:0] slot_0_present, + input [7:0] slot_1_present, + // From MC + input [nCK_PER_CLK-1:0] mc_ras_n, + input [nCK_PER_CLK-1:0] mc_cas_n, + input [nCK_PER_CLK-1:0] mc_we_n, + input [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, + input [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, + input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, + input mc_reset_n, + input [1:0] mc_odt, + input [nCK_PER_CLK-1:0] mc_cke, + // AUX - For ODT and CKE assertion during reads and writes + input [3:0] mc_aux_out0, + input [3:0] mc_aux_out1, + input mc_cmd_wren, + input mc_ctl_wren, + input [2:0] mc_cmd, + input [1:0] mc_cas_slot, + input [5:0] mc_data_offset, + input [5:0] mc_data_offset_1, + input [5:0] mc_data_offset_2, + input [1:0] mc_rank_cnt, + // Write + input mc_wrdata_en, + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata, + input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mc_wrdata_mask, + input idle, + // DDR bus signals + output [ROW_WIDTH-1:0] ddr_addr, + output [BANK_WIDTH-1:0] ddr_ba, + output ddr_cas_n, + output [CK_WIDTH-1:0] ddr_ck_n, + output [CK_WIDTH-1:0] ddr_ck, + output [CKE_WIDTH-1:0] ddr_cke, + output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, + output [DM_WIDTH-1:0] ddr_dm, + output [ODT_WIDTH-1:0] ddr_odt, + output ddr_ras_n, + output ddr_reset_n, + output ddr_parity, + output ddr_we_n, + inout [DQ_WIDTH-1:0] ddr_dq, + inout [DQS_WIDTH-1:0] ddr_dqs_n, + inout [DQS_WIDTH-1:0] ddr_dqs, + + // Ports to be used when SKIP_CALIB="TRUE" + output calib_tap_req, + input [6:0] calib_tap_addr, + input calib_tap_load, + input [7:0] calib_tap_val, + input calib_tap_load_done, + + //phase shift clock control + output psen, + output psincdec, + input psdone, + // Debug Port Outputs + output [255:0] dbg_calib_top, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, + output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, + output [255:0] dbg_phy_rdlvl, + output [99:0] dbg_phy_wrcal, + output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, + output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect, + output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata, + output dbg_rddata_valid, + output [1:0] dbg_rdlvl_done, + output [1:0] dbg_rdlvl_err, + output [1:0] dbg_rdlvl_start, + output [5:0] dbg_tap_cnt_during_wrlvl, + output dbg_wl_edge_detect_valid, + output dbg_wrlvl_done, + output dbg_wrlvl_err, + output dbg_wrlvl_start, + output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, + output [255:0] dbg_phy_wrlvl, + output dbg_pi_phaselock_start, + output dbg_pi_phaselocked_done, + output dbg_pi_phaselock_err, + output [11:0] dbg_pi_phase_locked_phy4lanes, + output dbg_pi_dqsfound_start, + output dbg_pi_dqsfound_done, + output dbg_pi_dqsfound_err, + output [11:0] dbg_pi_dqs_found_lanes_phy4lanes, + output dbg_wrcal_start, + output dbg_wrcal_done, + output dbg_wrcal_err, + output [1023:0] dbg_poc, + // FIFO status flags + output phy_mc_ctl_full, + output phy_mc_cmd_full, + output phy_mc_data_full, + // Calibration status and resultant outputs + output init_calib_complete, + output init_wrcal_complete, + output [6*RANKS-1:0] calib_rd_data_offset_0, + output [6*RANKS-1:0] calib_rd_data_offset_1, + output [6*RANKS-1:0] calib_rd_data_offset_2, + output phy_rddata_valid, + output [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data, + + output ref_dll_lock, + input rst_phaser_ref, + output [6*RANKS-1:0] dbg_rd_data_offset, + output [255:0] dbg_phy_init, + output [255:0] dbg_prbs_rdlvl, + output [255:0] dbg_dqs_found_cal, + output [5:0] dbg_pi_counter_read_val, + output [8:0] dbg_po_counter_read_val, + output dbg_oclkdelay_calib_start, + output dbg_oclkdelay_calib_done, + output [255:0] dbg_phy_oclkdelay_cal, + output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data, + output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r, + output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, + output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps + ); + + // Calculate number of slots in the system + localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0); + localparam CLK_PERIOD = tCK * nCK_PER_CLK; + + // Parameter used to force skipping or abbreviation of initialization + // and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and + // disables various other blocks depending on the option selected + // This option should only be used during simulation. In the case of + // the "SKIP" option, the testbench used should also not be modeling + // propagation delays. + // Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"} + // "NONE" = options determined by the individual parameter settings + // "SIM_FULL" = skip power-up delay. FULL calibration performed without + // averaging algorithm turned ON during window detection. + // "SKIP" = skip power-up delay. Skip calibration not yet supported. + // "FAST" = skip power-up delay, and calibrate (read leveling, write + // leveling, and phase detector) only using one DQS group, and + // apply the results to all other DQS groups. + localparam SIM_INIT_OPTION + = ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_INIT" : + ((SIM_BYPASS_INIT_CAL == "FAST") || + (SIM_BYPASS_INIT_CAL == "SIM_FULL")) ? "SKIP_PU_DLY" : + "NONE"); + localparam SIM_CAL_OPTION + = ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_CAL" : + (SIM_BYPASS_INIT_CAL == "FAST") ? "FAST_CAL" : + ((SIM_BYPASS_INIT_CAL == "SIM_FULL") || + (SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")) ? "FAST_WIN_DETECT" : + "NONE"); + localparam WRLVL_W + = (SIM_BYPASS_INIT_CAL == "SKIP") ? "OFF" : WRLVL; + + localparam HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : + (BYTE_LANES_B2 != 0 ? 3 : + (BYTE_LANES_B1 != 0 ? 2 : 1)))); + + localparam HIGHEST_LANE_B0 = BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : + BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : + 0; + localparam HIGHEST_LANE_B1 = BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : + BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : + 0; + localparam HIGHEST_LANE_B2 = BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : + BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : + 0; + localparam HIGHEST_LANE_B3 = BYTE_LANES_B3[3] ? 4 : BYTE_LANES_B3[2] ? 3 : + BYTE_LANES_B3[1] ? 2 : BYTE_LANES_B3[0] ? 1 : + 0; + localparam HIGHEST_LANE_B4 = BYTE_LANES_B4[3] ? 4 : BYTE_LANES_B4[2] ? 3 : + BYTE_LANES_B4[1] ? 2 : BYTE_LANES_B4[0] ? 1 : + 0; + localparam HIGHEST_LANE = + (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : + ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : + ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : + ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : + HIGHEST_LANE_B0))); + + localparam N_CTL_LANES = ((0+(!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) + + (0+(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) + + (0+(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) + + (0+(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) + + ((0+(!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) + + (0+(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) + + (0+(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) + + (0+(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) + + ((0+(!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) + + (0+(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) + + (0+(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) + + (0+(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) + + ((0+(!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) + + (0+(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) + + (0+(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) + + (0+(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) + + ((0+(!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) + + (0+(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) + + (0+(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) + + (0+(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])); + + // Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank + // This should be the case since the PLL should be placed adjacent + // to the same IO Bank as Ck/Addr/Cmd and Control + localparam [2:0] CTL_BANK = (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) | + ((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) | + ((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | + ((!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) ? + 3'b000 : + (((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) | + ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) | + ((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | + ((!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) ? + 3'b001 : + (((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) | + ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) | + ((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | + ((!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) ? + 3'b010 : + (((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) | + ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) | + ((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | + ((!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) ? + 3'b011 : + (((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) | + ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) | + ((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) | + ((!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])) ? + 3'b100 : 3'b000; + + localparam [7:0] CTL_BYTE_LANE = (N_CTL_LANES == 4) ? 8'b11_10_01_00 : + ((N_CTL_LANES == 3) & + (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & + (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & + (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | + ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & + (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & + (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | + ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & + (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & + (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | + ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & + (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & + (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | + ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & + (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & + (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ? + 8'b00_10_01_00 : + ((N_CTL_LANES == 3) & + (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & + (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & + (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | + ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & + (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & + (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | + ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & + (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & + (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | + ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & + (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & + (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | + ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & + (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & + (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? + 8'b00_11_01_00 : + ((N_CTL_LANES == 3) & + (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & + (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] & + (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | + ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & + (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] & + (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | + ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & + (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] & + (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | + ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & + (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] & + (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | + ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & + (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] & + (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? + 8'b00_11_10_00 : + ((N_CTL_LANES == 3) & + (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & + (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] & + (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | + ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & + (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] & + (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | + ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & + (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] & + (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | + ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & + (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] & + (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | + ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & + (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] & + (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? + 8'b00_11_10_01 : + ((N_CTL_LANES == 2) & + (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & + (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) | + ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & + (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) | + ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & + (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) | + ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & + (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) | + ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & + (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]))) ? + 8'b00_00_01_00 : + ((N_CTL_LANES == 2) & + (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & + (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | + ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & + (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | + ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & + (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | + ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & + (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | + ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & + (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? + 8'b00_00_11_00 : + ((N_CTL_LANES == 2) & + (((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] & + (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | + ((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] & + (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | + ((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] & + (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | + ((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] & + (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | + ((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] & + (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? + 8'b00_00_11_10 : + ((N_CTL_LANES == 2) & + (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & + (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | + ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & + (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | + ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & + (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | + ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & + (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | + ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & + (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ? + 8'b00_00_10_01 : + ((N_CTL_LANES == 2) & + (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & + (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | + ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & + (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | + ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & + (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | + ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & + (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | + ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & + (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? + 8'b00_00_11_01 : + ((N_CTL_LANES == 2) & + (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & + (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | + ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & + (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | + ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & + (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | + ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & + (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | + ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & + (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ? + 8'b00_00_10_00 : 8'b11_10_01_00; + + localparam PI_DIV2_INCDEC = (DRAM_TYPE == "DDR2") ? "FALSE" : (((FPGA_VOLT_TYPE == "L") && (nCK_PER_CLK == 4)) ? "TRUE" : "FALSE"); + + wire [HIGHEST_LANE*80-1:0] phy_din; + wire [HIGHEST_LANE*80-1:0] phy_dout; + wire [(HIGHEST_LANE*12)-1:0] ddr_cmd_ctl_data; + wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out; + wire [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk; + wire phy_mc_go; + wire phy_ctl_full; + wire phy_cmd_full; + wire phy_data_full; + wire phy_pre_data_a_full; + wire if_empty /* synthesis syn_maxfan = 3 */; + wire phy_write_calib; + wire phy_read_calib; + wire [HIGHEST_BANK-1:0] rst_stg1_cal; + wire [5:0] calib_sel; + wire calib_in_common /* synthesis syn_maxfan = 10 */; + wire [HIGHEST_BANK-1:0] calib_zero_inputs; + wire [HIGHEST_BANK-1:0] calib_zero_ctrl; + wire pi_phase_locked; + wire pi_phase_locked_all; + wire pi_found_dqs; + wire pi_dqs_found_all; + wire pi_dqs_out_of_range; + wire pi_enstg2_f; + wire pi_stg2_fincdec; + wire pi_stg2_load; + wire [5:0] pi_stg2_reg_l; + wire idelay_ce; + wire idelay_inc; + wire idelay_ld; + wire [2:0] po_sel_stg2stg3; + wire [2:0] po_stg2_cincdec; + wire [2:0] po_enstg2_c; + wire [2:0] po_stg2_fincdec; + wire [2:0] po_enstg2_f; + wire [8:0] po_counter_read_val; + wire [5:0] pi_counter_read_val; + wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata; + reg [nCK_PER_CLK-1:0] parity; + wire [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address; + wire [nCK_PER_CLK*BANK_WIDTH-1:0] phy_bank; + wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n; + wire [nCK_PER_CLK-1:0] phy_ras_n; + wire [nCK_PER_CLK-1:0] phy_cas_n; + wire [nCK_PER_CLK-1:0] phy_we_n; + wire phy_reset_n; + wire [3:0] calib_aux_out; + wire [nCK_PER_CLK-1:0] calib_cke; + wire [1:0] calib_odt; + wire calib_ctl_wren; + wire calib_cmd_wren; + wire calib_wrdata_en; + wire [2:0] calib_cmd; + wire [1:0] calib_seq; + wire [5:0] calib_data_offset_0; + wire [5:0] calib_data_offset_1; + wire [5:0] calib_data_offset_2; + wire [1:0] calib_rank_cnt; + wire [1:0] calib_cas_slot; + wire [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address; + wire [3:0] mux_aux_out; + wire [3:0] aux_out_map; + wire [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank; + wire [2:0] mux_cmd; + wire mux_cmd_wren; + wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n; + wire mux_ctl_wren; + wire [1:0] mux_cas_slot; + wire [5:0] mux_data_offset; + wire [5:0] mux_data_offset_1; + wire [5:0] mux_data_offset_2; + wire [nCK_PER_CLK-1:0] mux_ras_n; + wire [nCK_PER_CLK-1:0] mux_cas_n; + wire [1:0] mux_rank_cnt; + wire mux_reset_n; + wire [nCK_PER_CLK-1:0] mux_we_n; + wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata; + wire [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask; + wire mux_wrdata_en; + wire [nCK_PER_CLK-1:0] mux_cke ; + wire [1:0] mux_odt ; + wire phy_if_empty_def; + wire phy_if_reset; + wire phy_init_data_sel; + wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_map; + wire phy_rddata_valid_w; + reg rddata_valid_reg; + reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_reg; + wire [4:0] idelaye2_init_val; + wire [5:0] oclkdelay_init_val; + wire po_counter_load_en; + wire [DQS_CNT_WIDTH:0] byte_sel_cnt; + wire [DRAM_WIDTH-1:0] fine_delay_incdec_pb; + wire fine_delay_sel; + wire pd_out; + + //*************************************************************************** + + assign dbg_rddata_valid = rddata_valid_reg; + assign dbg_rddata = rd_data_reg; + + assign dbg_rd_data_offset = calib_rd_data_offset_0; + assign dbg_pi_phaselocked_done = pi_phase_locked_all; + + assign dbg_po_counter_read_val = po_counter_read_val; + assign dbg_pi_counter_read_val = pi_counter_read_val; + + //*************************************************************************** + + //*************************************************************************** + // Clock domain crossing from DIV4 to DIV2 for Phaser_In stage2 incdec + //*************************************************************************** + //localparam PI_DIV2_INCDEC = "TRUE"; + + wire pi_fine_enable; + wire pi_fine_inc; + wire pi_counter_load_en; + wire [5:0] pi_counter_load_val; + wire [HIGHEST_BANK-1:0] pi_rst_dqs_find; + + generate + if (PI_DIV2_INCDEC == "TRUE") begin: div2_incdec + // 3-stage synchronizer registers + (* ASYNC_REG = "TRUE" *) reg pi_enstg2_f_div2r1; + (* ASYNC_REG = "TRUE" *) reg pi_enstg2_f_div2r2; + (* ASYNC_REG = "TRUE" *) reg pi_enstg2_f_div2r3; + (* ASYNC_REG = "TRUE" *) reg pi_stg2_fincdec_div2r1; + (* ASYNC_REG = "TRUE" *) reg pi_stg2_fincdec_div2r2; + (* ASYNC_REG = "TRUE" *) reg pi_stg2_fincdec_div2r3; + (* ASYNC_REG = "TRUE" *) reg pi_stg2_load_div2r1; + (* ASYNC_REG = "TRUE" *) reg pi_stg2_load_div2r2; + (* ASYNC_REG = "TRUE" *) reg pi_stg2_load_div2r3; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_BANK-1:0] rst_stg1_cal_div2r1; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_BANK-1:0] rst_stg1_cal_div2r2; + (* ASYNC_REG = "TRUE" *) reg [5:0] pi_stg2_reg_l_div2r1; + (* ASYNC_REG = "TRUE" *) reg [5:0] pi_stg2_reg_l_div2r2; + (* ASYNC_REG = "TRUE" *) reg [5:0] pi_stg2_reg_l_div2r3; + + reg pi_stg2_fine_enable, pi_stg2_fine_enable_r1; + reg pi_stg2_fine_inc, pi_stg2_fine_inc_r1; + reg pi_stg2_load_en, pi_stg2_load_en_r1; + reg [5:0] pi_stg2_load_val; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_BANK-1:0] pi_dqs_find_rst; + + // 3-stage synchronizer + always @(posedge clk_div2) begin + //Phaser_In fine enable + pi_enstg2_f_div2r1 <= #TCQ pi_enstg2_f; + pi_enstg2_f_div2r2 <= #TCQ pi_enstg2_f_div2r1; + pi_enstg2_f_div2r3 <= #TCQ pi_enstg2_f_div2r2; + //Phaser_In fine incdec + pi_stg2_fincdec_div2r1 <= #TCQ pi_stg2_fincdec; + pi_stg2_fincdec_div2r2 <= #TCQ pi_stg2_fincdec_div2r1; + pi_stg2_fincdec_div2r3 <= #TCQ pi_stg2_fincdec_div2r2; + //Phaser_In stage2 load + pi_stg2_load_div2r1 <= #TCQ pi_stg2_load; + pi_stg2_load_div2r2 <= #TCQ pi_stg2_load_div2r1; + pi_stg2_load_div2r3 <= #TCQ pi_stg2_load_div2r2; + //Phaser_In stage2 load value + pi_stg2_reg_l_div2r1 <= #TCQ pi_stg2_reg_l; + pi_stg2_reg_l_div2r2 <= #TCQ pi_stg2_reg_l_div2r1; + pi_stg2_reg_l_div2r3 <= #TCQ pi_stg2_reg_l_div2r2; + //Phaser_In reset DQSFOUND + rst_stg1_cal_div2r1 <= #TCQ rst_stg1_cal; + rst_stg1_cal_div2r2 <= #TCQ rst_stg1_cal_div2r1; + pi_dqs_find_rst <= #TCQ rst_stg1_cal_div2r2; + end + + always @(posedge clk_div2) begin + pi_stg2_fine_enable_r1 <= #TCQ pi_stg2_fine_enable; + pi_stg2_fine_inc_r1 <= #TCQ pi_stg2_fine_inc; + pi_stg2_load_en_r1 <= #TCQ pi_stg2_load_en; + end + + always @(posedge clk_div2) begin + if (rst_div2 || pi_stg2_fine_enable || pi_stg2_fine_enable_r1) + pi_stg2_fine_enable <= #TCQ 1'b0; + else if (pi_enstg2_f_div2r3) + pi_stg2_fine_enable <= #TCQ 1'b1; + end + + always @(posedge clk_div2) begin + if (rst_div2 || pi_stg2_fine_inc || pi_stg2_fine_inc_r1) + pi_stg2_fine_inc <= #TCQ 1'b0; + else if (pi_stg2_fincdec_div2r3) + pi_stg2_fine_inc <= #TCQ 1'b1; + end + + always @(posedge clk_div2) begin + if (rst_div2 || pi_stg2_load_en || pi_stg2_load_en_r1) + pi_stg2_load_en <= #TCQ 1'b0; + else if (pi_stg2_load_div2r3) + pi_stg2_load_en <= #TCQ 1'b1; + end + + always @(posedge clk_div2) begin + if (rst_div2 || pi_stg2_load_en || pi_stg2_load_en_r1) + pi_stg2_load_val <= #TCQ 6'd0; + else if (pi_stg2_load_div2r3) + pi_stg2_load_val <= #TCQ pi_stg2_reg_l_div2r3; + end + + + assign pi_fine_enable = pi_stg2_fine_enable; + assign pi_fine_inc = pi_stg2_fine_inc; + assign pi_counter_load_en = pi_stg2_load_en; + assign pi_counter_load_val = pi_stg2_load_val; + assign pi_rst_dqs_find = pi_dqs_find_rst; + + end else begin: div4_incdec + assign pi_fine_enable = pi_enstg2_f; + assign pi_fine_inc = pi_stg2_fincdec; + assign pi_counter_load_en = pi_stg2_load; + assign pi_counter_load_val = pi_stg2_reg_l; + assign pi_rst_dqs_find = rst_stg1_cal; + + end + endgenerate + + genvar i; + generate + for (i = 0; i < CK_WIDTH; i = i+1) begin: clock_gen + assign ddr_ck[i] = ddr_clk[LP_DDR_CK_WIDTH * i]; + assign ddr_ck_n[i] = ddr_clk[(LP_DDR_CK_WIDTH * i) + 1]; + end + endgenerate + + //*************************************************************************** + // During memory initialization and calibration the calibration logic drives + // the memory signals. After calibration is complete the memory controller + // drives the memory signals. + // Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps + //*************************************************************************** + + wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_temp ; + genvar v ; + + generate + if((REG_CTRL == "ON") && (DRAM_TYPE == "DDR3") && (RANKS == 1) && (nCS_PER_RANK ==2)) begin : cs_rdimm + for(v = 0 ; v < CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK ; v = v+1 ) begin + if((v%(CS_WIDTH*nCS_PER_RANK)) == 0) begin + assign mc_cs_n_temp[v] = mc_cs_n[v] ; + end else begin + assign mc_cs_n_temp[v] = 'b1 ; + end + end + end else begin + assign mc_cs_n_temp = mc_cs_n ; + end + endgenerate + + assign mux_wrdata = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata : phy_wrdata; + assign mux_wrdata_mask = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_mask : 'b0; + assign mux_address = (phy_init_data_sel | init_wrcal_complete) ? mc_address : phy_address; + assign mux_bank = (phy_init_data_sel | init_wrcal_complete) ? mc_bank : phy_bank; + assign mux_cs_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cs_n_temp : phy_cs_n; + assign mux_ras_n = (phy_init_data_sel | init_wrcal_complete) ? mc_ras_n : phy_ras_n; + assign mux_cas_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_n : phy_cas_n; + assign mux_we_n = (phy_init_data_sel | init_wrcal_complete) ? mc_we_n : phy_we_n; + assign mux_reset_n = (phy_init_data_sel | init_wrcal_complete) ? mc_reset_n : phy_reset_n; + assign mux_aux_out = (phy_init_data_sel | init_wrcal_complete) ? mc_aux_out0 : calib_aux_out; + assign mux_odt = (phy_init_data_sel | init_wrcal_complete) ? mc_odt : calib_odt ; + assign mux_cke = (phy_init_data_sel | init_wrcal_complete) ? mc_cke : calib_cke ; + assign mux_cmd_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd_wren : + calib_cmd_wren; + assign mux_ctl_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_ctl_wren : + calib_ctl_wren; + assign mux_wrdata_en = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_en : + calib_wrdata_en; + assign mux_cmd = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd : calib_cmd; + assign mux_cas_slot = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_slot : calib_cas_slot; + assign mux_data_offset = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset : + calib_data_offset_0; + assign mux_data_offset_1 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_1 : + calib_data_offset_1; + assign mux_data_offset_2 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_2 : + calib_data_offset_2; + // Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601 + assign mux_rank_cnt = 2'b00; + + + // Assigning cke & odt for DDR2 & DDR3 + // No changes for DDR3 & DDR2 dual rank + // DDR2 single rank systems might potentially need 3 odt signals. + // Aux_out[2] will have the odt toggled by phy and controller + // wiring aux_out[2] to 0 & 3. Depending upon the odt parameter + // all of the three odt bits or some of them might be used. + // mapping done in mc_phy_wrapper module + generate + if(CKE_ODT_AUX == "TRUE") begin + assign aux_out_map = ((DRAM_TYPE == "DDR2") && (RANKS == 1)) ? + {mux_aux_out[1],mux_aux_out[1],mux_aux_out[1],mux_aux_out[0]} : + mux_aux_out; + end else begin + assign aux_out_map = 4'b0000 ; + end + endgenerate + + assign init_calib_complete = phy_init_data_sel; + + assign phy_mc_ctl_full = phy_ctl_full; + assign phy_mc_cmd_full = phy_cmd_full; + assign phy_mc_data_full = phy_pre_data_a_full; + + //*************************************************************************** + // Generate parity for DDR3 RDIMM. + //*************************************************************************** + + generate + if ((DRAM_TYPE == "DDR3") && (REG_CTRL == "ON")) begin: gen_ddr3_parity + if (nCK_PER_CLK == 4) begin + always @(posedge clk) begin + parity[0] <= #TCQ (^{mux_address[(ROW_WIDTH*4)-1:ROW_WIDTH*3], + mux_bank[(BANK_WIDTH*4)-1:BANK_WIDTH*3], + mux_cas_n[3], mux_ras_n[3], mux_we_n[3]}); + end + always @(*) begin + parity[1] = (^{mux_address[ROW_WIDTH-1:0], mux_bank[BANK_WIDTH-1:0], + mux_cas_n[0],mux_ras_n[0], mux_we_n[0]}); + parity[2] = (^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH], + mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH], + mux_cas_n[1], mux_ras_n[1], mux_we_n[1]}); + parity[3] = (^{mux_address[(ROW_WIDTH*3)-1:ROW_WIDTH*2], + mux_bank[(BANK_WIDTH*3)-1:BANK_WIDTH*2], + mux_cas_n[2],mux_ras_n[2], mux_we_n[2]}); + end + end else begin + always @(posedge clk) begin + parity[0] <= #TCQ(^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH], + mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH], + mux_cas_n[1], mux_ras_n[1], mux_we_n[1]}); + end + always @(*) begin + parity[1] = (^{mux_address[ROW_WIDTH-1:0], + mux_bank[BANK_WIDTH-1:0], + mux_cas_n[0], mux_ras_n[0], mux_we_n[0]}); + end + end + end else begin: gen_ddr3_noparity + if (nCK_PER_CLK == 4) begin + always @(posedge clk) begin + parity[0] <= #TCQ 1'b0; + parity[1] <= #TCQ 1'b0; + parity[2] <= #TCQ 1'b0; + parity[3] <= #TCQ 1'b0; + end + end else begin + always @(posedge clk) begin + parity[0] <= #TCQ 1'b0; + parity[1] <= #TCQ 1'b0; + end + end + end + endgenerate + + //*************************************************************************** + // Code for optional register stage in read path to MC for timing + //*************************************************************************** + generate + if(RD_PATH_REG == 1)begin:RD_REG_TIMING + always @(posedge clk)begin + rddata_valid_reg <= #TCQ phy_rddata_valid_w; + rd_data_reg <= #TCQ rd_data_map; + end // always @ (posedge clk) + end else begin : RD_REG_NO_TIMING // block: RD_REG_TIMING + always @(phy_rddata_valid_w or rd_data_map)begin + rddata_valid_reg = phy_rddata_valid_w; + rd_data_reg = rd_data_map; + end + end + endgenerate + + assign phy_rddata_valid = rddata_valid_reg; + assign phy_rd_data = rd_data_reg; + + //*************************************************************************** + // Hard PHY and accompanying bit mapping logic + //*************************************************************************** + + mig_7series_v4_0_ddr_mc_phy_wrapper # + ( + .TCQ (TCQ), + .tCK (tCK), + .BANK_TYPE (BANK_TYPE), + .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), + .DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .nCK_PER_CLK (nCK_PER_CLK), + .nCS_PER_RANK (nCS_PER_RANK), + .BANK_WIDTH (BANK_WIDTH), + .CKE_WIDTH (CKE_WIDTH), + .CS_WIDTH (CS_WIDTH), + .CK_WIDTH (CK_WIDTH), + .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH), + .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), + .CWL (CWL), + .DM_WIDTH (DM_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_TYPE (DRAM_TYPE), + .RANKS (RANKS), + .ODT_WIDTH (ODT_WIDTH), + .REG_CTRL (REG_CTRL), + .ROW_WIDTH (ROW_WIDTH), + .USE_CS_PORT (USE_CS_PORT), + .USE_DM_PORT (USE_DM_PORT), + .USE_ODT_PORT (USE_ODT_PORT), + .IBUF_LPWR_MODE (IBUF_LPWR_MODE), + .PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4), + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .PHY_0_BITLANES (PHY_0_BITLANES), + .PHY_1_BITLANES (PHY_1_BITLANES), + .PHY_2_BITLANES (PHY_2_BITLANES), + .HIGHEST_BANK (HIGHEST_BANK), + .HIGHEST_LANE (HIGHEST_LANE), + .CK_BYTE_MAP (CK_BYTE_MAP), + .ADDR_MAP (ADDR_MAP), + .BANK_MAP (BANK_MAP), + .CAS_MAP (CAS_MAP), + .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), + .CKE_MAP (CKE_MAP), + .ODT_MAP (ODT_MAP), + .CKE_ODT_AUX (CKE_ODT_AUX), + .CS_MAP (CS_MAP), + .PARITY_MAP (PARITY_MAP), + .RAS_MAP (RAS_MAP), + .WE_MAP (WE_MAP), + .DQS_BYTE_MAP (DQS_BYTE_MAP), + .DATA0_MAP (DATA0_MAP), + .DATA1_MAP (DATA1_MAP), + .DATA2_MAP (DATA2_MAP), + .DATA3_MAP (DATA3_MAP), + .DATA4_MAP (DATA4_MAP), + .DATA5_MAP (DATA5_MAP), + .DATA6_MAP (DATA6_MAP), + .DATA7_MAP (DATA7_MAP), + .DATA8_MAP (DATA8_MAP), + .DATA9_MAP (DATA9_MAP), + .DATA10_MAP (DATA10_MAP), + .DATA11_MAP (DATA11_MAP), + .DATA12_MAP (DATA12_MAP), + .DATA13_MAP (DATA13_MAP), + .DATA14_MAP (DATA14_MAP), + .DATA15_MAP (DATA15_MAP), + .DATA16_MAP (DATA16_MAP), + .DATA17_MAP (DATA17_MAP), + .MASK0_MAP (MASK0_MAP), + .MASK1_MAP (MASK1_MAP), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .MASTER_PHY_CTL (MASTER_PHY_CTL), + .DRAM_WIDTH (DRAM_WIDTH), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), + .PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + u_ddr_mc_phy_wrapper + ( + .rst (rst), + .iddr_rst (iddr_rst), + .clk (clk), + .clk_div2 (clk_div2), + // For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk + // For memory frequencies below 400 MHz mem_refclk = mem_refclk and + // freq_refclk = 2x or 4x mem_refclk such that it remains in the + // 400~1066 MHz range + .freq_refclk (freq_refclk), + .mem_refclk (mem_refclk), + .mmcm_ps_clk (mmcm_ps_clk), + .pll_lock (pll_lock), + .sync_pulse (sync_pulse), + .idelayctrl_refclk (clk_ref), + .phy_cmd_wr_en (mux_cmd_wren), + .phy_data_wr_en (mux_wrdata_en), + // phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23], + // DataOffset[22:17],HiIndex[16:15],LowIndex[14:12], + // AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]} + // The fields ACTPRE, and BankCount are only used + // when the hard PHY counters are used by the MC. + .phy_ctl_wd ({5'd0, mux_cas_slot, calib_seq, mux_data_offset, + mux_rank_cnt, 3'd0, aux_out_map, + 5'd0, mux_cmd}), + .phy_ctl_wr (mux_ctl_wren), + .phy_if_empty_def (phy_if_empty_def), + .phy_if_reset (phy_if_reset), + .data_offset_1 (mux_data_offset_1), + .data_offset_2 (mux_data_offset_2), + .aux_in_1 (aux_out_map), + .aux_in_2 (aux_out_map), + .idelaye2_init_val (idelaye2_init_val), + .oclkdelay_init_val (oclkdelay_init_val), + .if_empty (if_empty), + .phy_ctl_full (phy_ctl_full), + .phy_cmd_full (phy_cmd_full), + .phy_data_full (phy_data_full), + .phy_pre_data_a_full (phy_pre_data_a_full), + .ddr_clk (ddr_clk), + .phy_mc_go (phy_mc_go), + .phy_write_calib (phy_write_calib), + .phy_read_calib (phy_read_calib), + .po_fine_enable (po_enstg2_f), + .po_coarse_enable (po_enstg2_c), + .po_fine_inc (po_stg2_fincdec), + .po_coarse_inc (po_stg2_cincdec), + .po_counter_load_en (po_counter_load_en), + .po_counter_read_en (1'b1), + .po_sel_fine_oclk_delay (po_sel_stg2stg3), + .po_counter_load_val (), + .po_counter_read_val (po_counter_read_val), + .pi_rst_dqs_find (pi_rst_dqs_find), + .pi_fine_enable (pi_fine_enable), + .pi_fine_inc (pi_fine_inc), + .pi_counter_load_en (pi_counter_load_en), + .pi_counter_load_val (pi_counter_load_val), + .pi_counter_read_val (pi_counter_read_val), + .idelay_ce (idelay_ce), + .idelay_inc (idelay_inc), + .idelay_ld (idelay_ld), + .pi_phase_locked (pi_phase_locked), + .pi_phase_locked_all (pi_phase_locked_all), + .pi_dqs_found (pi_found_dqs), + .pi_dqs_found_all (pi_dqs_found_all), + // Currently not being used. May be used in future if periodic reads + // become a requirement. This output could also be used to signal a + // catastrophic failure in read capture and the need for re-cal + .pi_dqs_out_of_range (pi_dqs_out_of_range), + .phy_init_data_sel (phy_init_data_sel), + .calib_sel (calib_sel), + .calib_in_common (calib_in_common), + .calib_zero_inputs (calib_zero_inputs), + .calib_zero_ctrl (calib_zero_ctrl), + .mux_address (mux_address), + .mux_bank (mux_bank), + .mux_cs_n (mux_cs_n), + .mux_ras_n (mux_ras_n), + .mux_cas_n (mux_cas_n), + .mux_we_n (mux_we_n), + .mux_reset_n (mux_reset_n), + .parity_in (parity), + .mux_wrdata (mux_wrdata), + .mux_wrdata_mask (mux_wrdata_mask), + .mux_odt (mux_odt), + .mux_cke (mux_cke), + .idle (idle), + .rd_data (rd_data_map), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_odt (ddr_odt), + .ddr_parity (ddr_parity), + .ddr_ras_n (ddr_ras_n), + .ddr_we_n (ddr_we_n), + .ddr_dq (ddr_dq), + .ddr_dqs (ddr_dqs), + .ddr_dqs_n (ddr_dqs_n), + .ddr_reset_n (ddr_reset_n), + .dbg_pi_counter_read_en (1'b1), + .ref_dll_lock (ref_dll_lock), + .rst_phaser_ref (rst_phaser_ref), + .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes), + .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes), + .byte_sel_cnt (byte_sel_cnt), + .pd_out (pd_out), + .fine_delay_incdec_pb (fine_delay_incdec_pb), + .fine_delay_sel (fine_delay_sel) + ); + + //*************************************************************************** + // Soft memory initialization and calibration logic + //*************************************************************************** + + mig_7series_v4_0_ddr_calib_top # + ( + .TCQ (TCQ), + .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), + .nCK_PER_CLK (nCK_PER_CLK), + .PRE_REV3ES (PRE_REV3ES), + .tCK (tCK), + .CLK_PERIOD (CLK_PERIOD), + .N_CTL_LANES (N_CTL_LANES), + .CTL_BYTE_LANE (CTL_BYTE_LANE), + .CTL_BANK (CTL_BANK), + .DRAM_TYPE (DRAM_TYPE), + .PRBS_WIDTH (8), + .DQS_BYTE_MAP (DQS_BYTE_MAP), + .HIGHEST_BANK (HIGHEST_BANK), + .BANK_TYPE (BANK_TYPE), + .HIGHEST_LANE (HIGHEST_LANE), + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4), + .SLOT_1_CONFIG (SLOT_1_CONFIG), + .BANK_WIDTH (BANK_WIDTH), + .CA_MIRROR (CA_MIRROR), + .COL_WIDTH (COL_WIDTH), + .CKE_ODT_AUX (CKE_ODT_AUX), + .nCS_PER_RANK (nCS_PER_RANK), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .ROW_WIDTH (ROW_WIDTH), + .RANKS (RANKS), + .CS_WIDTH (CS_WIDTH), + .CKE_WIDTH (CKE_WIDTH), + .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), + .PER_BIT_DESKEW ("OFF"), + .CALIB_ROW_ADD (CALIB_ROW_ADD), + .CALIB_COL_ADD (CALIB_COL_ADD), + .CALIB_BA_ADD (CALIB_BA_ADD), + .AL (AL), + .BURST_MODE (BURST_MODE), + .BURST_TYPE (BURST_TYPE), + .nCL (CL), + .nCWL (CWL), + .tRFC (tRFC), + .tREFI (tREFI), + .OUTPUT_DRV (OUTPUT_DRV), + .REG_CTRL (REG_CTRL), + .ADDR_CMD_MODE (ADDR_CMD_MODE), + .RTT_NOM (RTT_NOM), + .RTT_WR (RTT_WR), + .WRLVL (WRLVL_W), + .USE_ODT_PORT (USE_ODT_PORT), + .SIM_INIT_OPTION (SIM_INIT_OPTION), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .DEBUG_PORT (DEBUG_PORT), + .IDELAY_ADJ (IDELAY_ADJ), + .FINE_PER_BIT (FINE_PER_BIT), + .CENTER_COMP_MODE (CENTER_COMP_MODE), + .PI_VAL_ADJ (PI_VAL_ADJ), + .TAPSPERKCLK (TAPSPERKCLK), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), + .SKIP_CALIB (SKIP_CALIB), + .PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + u_ddr_calib_top + ( + .clk (clk), + .rst (rst), + + .tg_err (error), + .rst_tg_mc (rst_tg_mc), + + .slot_0_present (slot_0_present), + .slot_1_present (slot_1_present), + // PHY Control Block and IN_FIFO status + .phy_ctl_ready (phy_mc_go), + .phy_ctl_full (1'b0), + .phy_cmd_full (1'b0), + .phy_data_full (1'b0), + .phy_if_empty (if_empty), + .idelaye2_init_val (idelaye2_init_val), + .oclkdelay_init_val (oclkdelay_init_val), + // From calib logic To data IN_FIFO + // DQ IDELAY tap value from Calib logic + // port to be added to mc_phy by Gary + .dlyval_dq (), + // hard PHY calibration modes + .write_calib (phy_write_calib), + .read_calib (phy_read_calib), + // DQS count and ck/addr/cmd to be mapped to calib_sel + // based on parameter that defines placement of ctl lanes + // and DQS byte groups in each bank. When phy_write_calib + // is de-asserted calib_sel should select CK/addr/cmd/ctl. + .calib_sel (calib_sel), + .calib_in_common (calib_in_common), + .calib_zero_inputs (calib_zero_inputs), + .calib_zero_ctrl (calib_zero_ctrl), + .phy_if_empty_def (phy_if_empty_def), + .phy_if_reset (phy_if_reset), + // Signals from calib logic to be MUXED with MC + // signals before sending to hard PHY + .calib_ctl_wren (calib_ctl_wren), + .calib_cmd_wren (calib_cmd_wren), + .calib_seq (calib_seq), + .calib_aux_out (calib_aux_out), + .calib_odt (calib_odt), + .calib_cke (calib_cke), + .calib_cmd (calib_cmd), + .calib_wrdata_en (calib_wrdata_en), + .calib_rank_cnt (calib_rank_cnt), + .calib_cas_slot (calib_cas_slot), + .calib_data_offset_0 (calib_data_offset_0), + .calib_data_offset_1 (calib_data_offset_1), + .calib_data_offset_2 (calib_data_offset_2), + .phy_reset_n (phy_reset_n), + .phy_address (phy_address), + .phy_bank (phy_bank), + .phy_cs_n (phy_cs_n), + .phy_ras_n (phy_ras_n), + .phy_cas_n (phy_cas_n), + .phy_we_n (phy_we_n), + .phy_wrdata (phy_wrdata), + // DQS Phaser_IN calibration/status signals + .pi_phaselocked (pi_phase_locked), + .pi_phase_locked_all (pi_phase_locked_all), + .pi_found_dqs (pi_found_dqs), + .pi_dqs_found_all (pi_dqs_found_all), + .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes), + .pi_rst_stg1_cal (rst_stg1_cal), + .pi_en_stg2_f (pi_enstg2_f), + .pi_stg2_f_incdec (pi_stg2_fincdec), + .pi_stg2_load (pi_stg2_load), + .pi_stg2_reg_l (pi_stg2_reg_l), + .pi_counter_read_val (pi_counter_read_val), + .device_temp (device_temp), + .tempmon_sample_en (tempmon_sample_en), + // IDELAY tap enable and inc signals + .idelay_ce (idelay_ce), + .idelay_inc (idelay_inc), + .idelay_ld (idelay_ld), + // DQS Phaser_OUT calibration/status signals + .po_sel_stg2stg3 (po_sel_stg2stg3), + .po_stg2_c_incdec (po_stg2_cincdec), + .po_en_stg2_c (po_enstg2_c), + .po_stg2_f_incdec (po_stg2_fincdec), + .po_en_stg2_f (po_enstg2_f), + .po_counter_load_en (po_counter_load_en), + .po_counter_read_val (po_counter_read_val), + // From data IN_FIFO To Calib logic and MC/UI + .phy_rddata (rd_data_map), + // From calib logic To MC + .phy_rddata_valid (phy_rddata_valid_w), + .calib_rd_data_offset_0 (calib_rd_data_offset_0), + .calib_rd_data_offset_1 (calib_rd_data_offset_1), + .calib_rd_data_offset_2 (calib_rd_data_offset_2), + .calib_writes (), + // Mem Init and Calibration status To MC + .init_calib_complete (phy_init_data_sel), + .init_wrcal_complete (init_wrcal_complete), + // Debug Error signals + .pi_phase_locked_err (dbg_pi_phaselock_err), + .pi_dqsfound_err (dbg_pi_dqsfound_err), + .wrcal_err (dbg_wrcal_err), + //used for oclk stg3 centering + .pd_out (pd_out), + .psen (psen), + .psincdec (psincdec), + .psdone (psdone), + .poc_sample_pd (poc_sample_pd), + .calib_tap_req (calib_tap_req), + .calib_tap_addr (calib_tap_addr), + .calib_tap_load (calib_tap_load), + .calib_tap_val (calib_tap_val), + .calib_tap_load_done (calib_tap_load_done), + // Debug Signals + .dbg_pi_phaselock_start (dbg_pi_phaselock_start), + .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start), + .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done), + .dbg_wrlvl_start (dbg_wrlvl_start), + .dbg_wrlvl_done (dbg_wrlvl_done), + .dbg_wrlvl_err (dbg_wrlvl_err), + .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), + .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), + .dbg_phy_wrlvl (dbg_phy_wrlvl), + .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl), + .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), + .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), + .dbg_wrcal_start (dbg_wrcal_start), + .dbg_wrcal_done (dbg_wrcal_done), + .dbg_phy_wrcal (dbg_phy_wrcal), + .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), + .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt), + .dbg_rdlvl_start (dbg_rdlvl_start), + .dbg_rdlvl_done (dbg_rdlvl_done), + .dbg_rdlvl_err (dbg_rdlvl_err), + .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), + .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), + .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), + .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), + .dbg_sel_pi_incdec (dbg_sel_pi_incdec), + .dbg_sel_po_incdec (dbg_sel_po_incdec), + .dbg_byte_sel (dbg_byte_sel), + .dbg_pi_f_inc (dbg_pi_f_inc), + .dbg_pi_f_dec (dbg_pi_f_dec), + .dbg_po_f_inc (dbg_po_f_inc), + .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel), + .dbg_po_f_dec (dbg_po_f_dec), + .dbg_idel_up_all (dbg_idel_up_all), + .dbg_idel_down_all (dbg_idel_down_all), + .dbg_idel_up_cpt (dbg_idel_up_cpt), + .dbg_idel_down_cpt (dbg_idel_down_cpt), + .dbg_sel_idel_cpt (dbg_sel_idel_cpt), + .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), + .dbg_phy_rdlvl (dbg_phy_rdlvl), + .dbg_calib_top (dbg_calib_top), + .dbg_phy_init (dbg_phy_init), + .dbg_prbs_rdlvl (dbg_prbs_rdlvl), + .dbg_dqs_found_cal (dbg_dqs_found_cal), + .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal), + .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data), + .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start), + .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done), + .dbg_poc (dbg_poc[1023:0]), + .prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r), + .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps), + .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps), + .byte_sel_cnt (byte_sel_cnt), + .fine_delay_incdec_pb (fine_delay_incdec_pb), + .fine_delay_sel (fine_delay_sel) + ); + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_wrcal.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_wrcal.v new file mode 100644 index 0000000..4a7560c --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_wrcal.v @@ -0,0 +1,1316 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: +// \ \ Application: MIG +// / / Filename: ddr_phy_wrcal.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// Write calibration logic to align DQS to correct CK edge +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ +**$Date: 2011/06/02 08:35:09 $ +**$Author: +**$Revision: +**$Source: +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_wrcal # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter nCK_PER_CLK = 2, // # of memory clocks per CLK + parameter CLK_PERIOD = 2500, + parameter DQ_WIDTH = 64, // # of DQ (data) + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly + parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps + ) + ( + input clk, + input rst, + // Calibration status, control signals + input wrcal_start, + input wrcal_rd_wait, + input wrcal_sanity_chk, + input dqsfound_retry_done, + input phy_rddata_en, + output dqsfound_retry, + output wrcal_read_req, + output reg wrcal_act_req, + output reg wrcal_done, + output reg wrcal_pat_err, + output reg wrcal_prech_req, + output reg temp_wrcal_done, + output reg wrcal_sanity_chk_done, + input prech_done, + // Captured data in resync clock domain + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, + // Write level values of Phaser_Out coarse and fine + // delay taps required to load Phaser_Out register + input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt, + input [6*DQS_WIDTH-1:0] wl_po_fine_cnt, + input wrlvl_byte_done, + output reg wrlvl_byte_redo, + output reg early1_data, + output reg early2_data, + // DQ IDELAY + output reg idelay_ld, + output reg wrcal_pat_resume, // to phy_init for write + output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt, + output phy_if_reset, + + // Debug Port + output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, + output [99:0] dbg_phy_wrcal + ); + + // Length of calibration sequence (in # of words) + //localparam CAL_PAT_LEN = 8; + + // Read data shift register length + localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2; + + // # of reads for reliable read capture + localparam NUM_READS = 2; + + // # of cycles to wait after changing RDEN count value + localparam RDEN_WAIT_CNT = 12; + + localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6; + localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44; + + + localparam CAL2_IDLE = 4'h0; + localparam CAL2_READ_WAIT = 4'h1; + localparam CAL2_NEXT_DQS = 4'h2; + localparam CAL2_WRLVL_WAIT = 4'h3; + localparam CAL2_IFIFO_RESET = 4'h4; + localparam CAL2_DQ_IDEL_DEC = 4'h5; + localparam CAL2_DONE = 4'h6; + localparam CAL2_SANITY_WAIT = 4'h7; + localparam CAL2_ERR = 4'h8; + + integer i,j,k,l,m,p,q,d; + + reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1]; + reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w; + reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1]; + reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w; + reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */; + reg [4:0] not_empty_wait_cnt; + reg [3:0] tap_inc_wait_cnt; + reg cal2_done_r; + reg cal2_done_r1; + reg cal2_prech_req_r; + reg [3:0] cal2_state_r; + reg [3:0] cal2_state_r1; + reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1]; + reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1]; + reg cal2_if_reset; + reg wrcal_pat_resume_r; + reg wrcal_pat_resume_r1; + reg wrcal_pat_resume_r2; + reg wrcal_pat_resume_r3; + reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; + reg pat_data_match_r; + reg pat1_data_match_r; + reg pat1_data_match_r1; + reg pat2_data_match_r; + reg pat_data_match_valid_r; + wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0]; + wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0]; + reg [DRAM_WIDTH-1:0] pat_match_fall0_r; + reg pat_match_fall0_and_r; + reg [DRAM_WIDTH-1:0] pat_match_fall1_r; + reg pat_match_fall1_and_r; + reg [DRAM_WIDTH-1:0] pat_match_fall2_r; + reg pat_match_fall2_and_r; + reg [DRAM_WIDTH-1:0] pat_match_fall3_r; + reg pat_match_fall3_and_r; + reg [DRAM_WIDTH-1:0] pat_match_rise0_r; + reg pat_match_rise0_and_r; + reg [DRAM_WIDTH-1:0] pat_match_rise1_r; + reg pat_match_rise1_and_r; + reg [DRAM_WIDTH-1:0] pat_match_rise2_r; + reg pat_match_rise2_and_r; + reg [DRAM_WIDTH-1:0] pat_match_rise3_r; + reg pat_match_rise3_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; + reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; + reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; + reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; + reg [DRAM_WIDTH-1:0] pat2_match_rise0_r; + reg [DRAM_WIDTH-1:0] pat2_match_rise1_r; + reg [DRAM_WIDTH-1:0] pat2_match_fall0_r; + reg [DRAM_WIDTH-1:0] pat2_match_fall1_r; + reg pat1_match_rise0_and_r; + reg pat1_match_rise1_and_r; + reg pat1_match_fall0_and_r; + reg pat1_match_fall1_and_r; + reg pat2_match_rise0_and_r; + reg pat2_match_rise1_and_r; + reg pat2_match_fall0_and_r; + reg pat2_match_fall1_and_r; + reg early1_data_match_r; + reg early1_data_match_r1; + reg [DRAM_WIDTH-1:0] early1_match_fall0_r; + reg early1_match_fall0_and_r; + reg [DRAM_WIDTH-1:0] early1_match_fall1_r; + reg early1_match_fall1_and_r; + reg [DRAM_WIDTH-1:0] early1_match_fall2_r; + reg early1_match_fall2_and_r; + reg [DRAM_WIDTH-1:0] early1_match_fall3_r; + reg early1_match_fall3_and_r; + reg [DRAM_WIDTH-1:0] early1_match_rise0_r; + reg early1_match_rise0_and_r; + reg [DRAM_WIDTH-1:0] early1_match_rise1_r; + reg early1_match_rise1_and_r; + reg [DRAM_WIDTH-1:0] early1_match_rise2_r; + reg early1_match_rise2_and_r; + reg [DRAM_WIDTH-1:0] early1_match_rise3_r; + reg early1_match_rise3_and_r; + reg early2_data_match_r; + reg [DRAM_WIDTH-1:0] early2_match_fall0_r; + reg early2_match_fall0_and_r; + reg [DRAM_WIDTH-1:0] early2_match_fall1_r; + reg early2_match_fall1_and_r; + reg [DRAM_WIDTH-1:0] early2_match_fall2_r; + reg early2_match_fall2_and_r; + reg [DRAM_WIDTH-1:0] early2_match_fall3_r; + reg early2_match_fall3_and_r; + reg [DRAM_WIDTH-1:0] early2_match_rise0_r; + reg early2_match_rise0_and_r; + reg [DRAM_WIDTH-1:0] early2_match_rise1_r; + reg early2_match_rise1_and_r; + reg [DRAM_WIDTH-1:0] early2_match_rise2_r; + reg early2_match_rise2_and_r; + reg [DRAM_WIDTH-1:0] early2_match_rise3_r; + reg early2_match_rise3_and_r; + wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0]; + wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0]; + wire [DQ_WIDTH-1:0] rd_data_rise0; + wire [DQ_WIDTH-1:0] rd_data_fall0; + wire [DQ_WIDTH-1:0] rd_data_rise1; + wire [DQ_WIDTH-1:0] rd_data_fall1; + wire [DQ_WIDTH-1:0] rd_data_rise2; + wire [DQ_WIDTH-1:0] rd_data_fall2; + wire [DQ_WIDTH-1:0] rd_data_rise3; + wire [DQ_WIDTH-1:0] rd_data_fall3; + reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; + reg rd_active_posedge_r; + reg rd_active_r; + reg rd_active_r1; + reg rd_active_r2; + reg rd_active_r3; + reg rd_active_r4; + reg rd_active_r5; + reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; + reg wrlvl_byte_done_r; + reg idelay_ld_done; + reg pat1_detect; + reg early1_detect; + reg wrcal_sanity_chk_r; + reg wrcal_sanity_chk_err; + + + //*************************************************************************** + // Debug + //*************************************************************************** + + always @(*) begin + for (d = 0; d < DQS_WIDTH; d = d + 1) begin + po_fine_tap_cnt_w[(6*d)+:6] = po_fine_tap_cnt[d]; + po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d]; + end + end + + assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w; + assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w; + + assign dbg_phy_wrcal[0] = pat_data_match_r; + assign dbg_phy_wrcal[4:1] = cal2_state_r1[3:0]; + assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err; + assign dbg_phy_wrcal[6] = wrcal_start; + assign dbg_phy_wrcal[7] = wrcal_done; + assign dbg_phy_wrcal[8] = pat_data_match_valid_r; + assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r; + assign dbg_phy_wrcal[17+:5] = not_empty_wait_cnt; + assign dbg_phy_wrcal[22] = early1_data; + assign dbg_phy_wrcal[23] = early2_data; + assign dbg_phy_wrcal[24+:8] = mux_rd_rise0_r; + assign dbg_phy_wrcal[32+:8] = mux_rd_fall0_r; + assign dbg_phy_wrcal[40+:8] = mux_rd_rise1_r; + assign dbg_phy_wrcal[48+:8] = mux_rd_fall1_r; + assign dbg_phy_wrcal[56+:8] = mux_rd_rise2_r; + assign dbg_phy_wrcal[64+:8] = mux_rd_fall2_r; + assign dbg_phy_wrcal[72+:8] = mux_rd_rise3_r; + assign dbg_phy_wrcal[80+:8] = mux_rd_fall3_r; + assign dbg_phy_wrcal[88] = early1_data_match_r; + assign dbg_phy_wrcal[89] = early2_data_match_r; + assign dbg_phy_wrcal[90] = wrcal_sanity_chk_r & pat_data_match_valid_r; + assign dbg_phy_wrcal[91] = wrcal_sanity_chk_r; + assign dbg_phy_wrcal[92] = wrcal_sanity_chk_done; + + assign dqsfound_retry = 1'b0; + assign wrcal_read_req = 1'b0; + assign phy_if_reset = cal2_if_reset; + + //************************************************************************** + // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 + // coarse delay + //************************************************************************** + + always @(posedge clk) begin + po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r; + wrlvl_byte_done_r <= #TCQ wrlvl_byte_done; + wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk; + end + + //*************************************************************************** + // Data mux to route appropriate byte to calibration logic - i.e. calibration + // is done sequentially, one byte (or DQS group) at a time + //*************************************************************************** + + generate + if (nCK_PER_CLK == 4) begin: gen_rd_data_div4 + assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; + assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; + assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; + assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; + assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; + end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2 + assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; + assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + end + endgenerate + + //************************************************************************** + // Final Phaser OUT coarse and fine delay taps after write calibration + // Sum of taps used during write leveling taps and write calibration + //************************************************************************** + + always @(*) begin + for (m = 0; m < DQS_WIDTH; m = m + 1) begin + wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3]; + wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6]; + end + end + + always @(posedge clk) begin + if (rst) begin + for (p = 0; p < DQS_WIDTH; p = p + 1) begin + po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}}; + po_fine_tap_cnt[p] <= #TCQ {6{1'b0}}; + end + end else if (cal2_done_r && ~cal2_done_r1) begin + for (q = 0; q < DQS_WIDTH; q = q + 1) begin + po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i]; + po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i]; + end + end + end + + always @(posedge clk) begin + rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r; + end + + // Register outputs for improved timing. + // NOTE: Will need to change when per-bit DQ deskew is supported. + // Currenly all bits in DQS group are checked in aggregate + generate + genvar mux_i; + if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4 + for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd + always @(posedge clk) begin + mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + end + end + end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2 + for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd + always @(posedge clk) begin + mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + end + end + end + endgenerate + + //*************************************************************************** + // generate request to PHY_INIT logic to issue precharged. Required when + // calibration can take a long time (during which there are only constant + // reads present on this bus). In this case need to issue perioidic + // precharges to avoid tRAS violation. This signal must meet the following + // requirements: (1) only transition from 0->1 when prech is first needed, + // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted + //*************************************************************************** + + always @(posedge clk) + if (rst) + wrcal_prech_req <= #TCQ 1'b0; + else + // Combine requests from all stages here + wrcal_prech_req <= #TCQ cal2_prech_req_r; + + //*************************************************************************** + // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES + // NOTE: Written using discrete flops, but SRL can be used if the matching + // logic does the comparison sequentially, rather than parallel + //*************************************************************************** + + generate + genvar rd_i; + if (nCK_PER_CLK == 4) begin: gen_sr_div4 + for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr + always @(posedge clk) begin + sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; + sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; + sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; + sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; + sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; + sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; + sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; + sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; + end + end + end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 + for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr + always @(posedge clk) begin + sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; + sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; + sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; + sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; + end + end + end + endgenerate + + //*************************************************************************** + // Write calibration: + // During write leveling DQS is aligned to the nearest CK edge that may not + // be the correct CK edge. Write calibration is required to align the DQS to + // the correct CK edge that clocks the write command. + // The Phaser_Out coarse delay line is adjusted if required to add a memory + // clock cycle of delay in order to read back the expected pattern. + //*************************************************************************** + + always @(posedge clk) begin + rd_active_r <= #TCQ phy_rddata_en; + rd_active_r1 <= #TCQ rd_active_r; + rd_active_r2 <= #TCQ rd_active_r1; + rd_active_r3 <= #TCQ rd_active_r2; + rd_active_r4 <= #TCQ rd_active_r3; + rd_active_r5 <= #TCQ rd_active_r4; + end + + //***************************************************************** + // Expected data pattern when properly received by read capture + // logic: + // Based on pattern of ({rise,fall}) = + // 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 + // Each nibble will look like: + // bit3: 1, 0, 1, 0, 0, 1, 1, 0 + // bit2: 1, 0, 0, 1, 1, 0, 0, 1 + // bit1: 1, 0, 1, 0, 0, 1, 0, 1 + // bit0: 1, 0, 0, 1, 1, 0, 1, 0 + // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN + // and the actual training pattern contents change + //***************************************************************** + + generate + if (nCK_PER_CLK == 4) begin: gen_pat_div4 + // FF00AA5555AA9966 + assign pat_rise0[3] = 1'b1; + assign pat_fall0[3] = 1'b0; + assign pat_rise1[3] = 1'b1; + assign pat_fall1[3] = 1'b0; + assign pat_rise2[3] = 1'b0; + assign pat_fall2[3] = 1'b1; + assign pat_rise3[3] = 1'b1; + assign pat_fall3[3] = 1'b0; + + assign pat_rise0[2] = 1'b1; + assign pat_fall0[2] = 1'b0; + assign pat_rise1[2] = 1'b0; + assign pat_fall1[2] = 1'b1; + assign pat_rise2[2] = 1'b1; + assign pat_fall2[2] = 1'b0; + assign pat_rise3[2] = 1'b0; + assign pat_fall3[2] = 1'b1; + + assign pat_rise0[1] = 1'b1; + assign pat_fall0[1] = 1'b0; + assign pat_rise1[1] = 1'b1; + assign pat_fall1[1] = 1'b0; + assign pat_rise2[1] = 1'b0; + assign pat_fall2[1] = 1'b1; + assign pat_rise3[1] = 1'b0; + assign pat_fall3[1] = 1'b1; + + assign pat_rise0[0] = 1'b1; + assign pat_fall0[0] = 1'b0; + assign pat_rise1[0] = 1'b0; + assign pat_fall1[0] = 1'b1; + assign pat_rise2[0] = 1'b1; + assign pat_fall2[0] = 1'b0; + assign pat_rise3[0] = 1'b1; + assign pat_fall3[0] = 1'b0; + + // Pattern to distinguish between early write and incorrect read + // BB11EE4444EEDD88 + assign early_rise0[3] = 1'b1; + assign early_fall0[3] = 1'b0; + assign early_rise1[3] = 1'b1; + assign early_fall1[3] = 1'b0; + assign early_rise2[3] = 1'b0; + assign early_fall2[3] = 1'b1; + assign early_rise3[3] = 1'b1; + assign early_fall3[3] = 1'b1; + + assign early_rise0[2] = 1'b0; + assign early_fall0[2] = 1'b0; + assign early_rise1[2] = 1'b1; + assign early_fall1[2] = 1'b1; + assign early_rise2[2] = 1'b1; + assign early_fall2[2] = 1'b1; + assign early_rise3[2] = 1'b1; + assign early_fall3[2] = 1'b0; + + assign early_rise0[1] = 1'b1; + assign early_fall0[1] = 1'b0; + assign early_rise1[1] = 1'b1; + assign early_fall1[1] = 1'b0; + assign early_rise2[1] = 1'b0; + assign early_fall2[1] = 1'b1; + assign early_rise3[1] = 1'b0; + assign early_fall3[1] = 1'b0; + + assign early_rise0[0] = 1'b1; + assign early_fall0[0] = 1'b1; + assign early_rise1[0] = 1'b0; + assign early_fall1[0] = 1'b0; + assign early_rise2[0] = 1'b0; + assign early_fall2[0] = 1'b0; + assign early_rise3[0] = 1'b1; + assign early_fall3[0] = 1'b0; + + end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 + // First cycle pattern FF00AA55 + assign pat1_rise0[3] = 1'b1; + assign pat1_fall0[3] = 1'b0; + assign pat1_rise1[3] = 1'b1; + assign pat1_fall1[3] = 1'b0; + + assign pat1_rise0[2] = 1'b1; + assign pat1_fall0[2] = 1'b0; + assign pat1_rise1[2] = 1'b0; + assign pat1_fall1[2] = 1'b1; + + assign pat1_rise0[1] = 1'b1; + assign pat1_fall0[1] = 1'b0; + assign pat1_rise1[1] = 1'b1; + assign pat1_fall1[1] = 1'b0; + + assign pat1_rise0[0] = 1'b1; + assign pat1_fall0[0] = 1'b0; + assign pat1_rise1[0] = 1'b0; + assign pat1_fall1[0] = 1'b1; + + // Second cycle pattern 55AA9966 + assign pat2_rise0[3] = 1'b0; + assign pat2_fall0[3] = 1'b1; + assign pat2_rise1[3] = 1'b1; + assign pat2_fall1[3] = 1'b0; + + assign pat2_rise0[2] = 1'b1; + assign pat2_fall0[2] = 1'b0; + assign pat2_rise1[2] = 1'b0; + assign pat2_fall1[2] = 1'b1; + + assign pat2_rise0[1] = 1'b0; + assign pat2_fall0[1] = 1'b1; + assign pat2_rise1[1] = 1'b0; + assign pat2_fall1[1] = 1'b1; + + assign pat2_rise0[0] = 1'b1; + assign pat2_fall0[0] = 1'b0; + assign pat2_rise1[0] = 1'b1; + assign pat2_fall1[0] = 1'b0; + + //Pattern to distinguish between early write and incorrect read + // First cycle pattern AA5555AA + assign early1_rise0[3] = 2'b1; + assign early1_fall0[3] = 2'b0; + assign early1_rise1[3] = 2'b0; + assign early1_fall1[3] = 2'b1; + + assign early1_rise0[2] = 2'b0; + assign early1_fall0[2] = 2'b1; + assign early1_rise1[2] = 2'b1; + assign early1_fall1[2] = 2'b0; + + assign early1_rise0[1] = 2'b1; + assign early1_fall0[1] = 2'b0; + assign early1_rise1[1] = 2'b0; + assign early1_fall1[1] = 2'b1; + + assign early1_rise0[0] = 2'b0; + assign early1_fall0[0] = 2'b1; + assign early1_rise1[0] = 2'b1; + assign early1_fall1[0] = 2'b0; + + // Second cycle pattern 9966BB11 + assign early2_rise0[3] = 2'b1; + assign early2_fall0[3] = 2'b0; + assign early2_rise1[3] = 2'b1; + assign early2_fall1[3] = 2'b0; + + assign early2_rise0[2] = 2'b0; + assign early2_fall0[2] = 2'b1; + assign early2_rise1[2] = 2'b0; + assign early2_fall1[2] = 2'b0; + + assign early2_rise0[1] = 2'b0; + assign early2_fall0[1] = 2'b1; + assign early2_rise1[1] = 2'b1; + assign early2_fall1[1] = 2'b0; + + assign early2_rise0[0] = 2'b1; + assign early2_fall0[0] = 2'b0; + assign early2_rise1[0] = 2'b1; + assign early2_fall1[0] = 2'b1; + end + endgenerate + + // Each bit of each byte is compared to expected pattern. + // This was done to prevent (and "drastically decrease") the chance that + // invalid data clocked in when the DQ bus is tri-state (along with a + // combination of the correct data) will resemble the expected data + // pattern. A better fix for this is to change the training pattern and/or + // make the pattern longer. + generate + genvar pt_i; + if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 + for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4]) + pat_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4]) + pat_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4]) + pat_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4]) + pat_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4]) + pat_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + pat_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4]) + pat_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + pat_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4]) + pat_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + pat_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4]) + pat_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + pat_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4]) + early1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + early1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4]) + early1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + early1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4]) + early1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + early1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4]) + early1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + early1_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4]) + early1_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + early1_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4]) + early1_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + early1_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == early_rise0[pt_i%4]) + early1_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + early1_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == early_fall0[pt_i%4]) + early1_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + early1_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4]) + early2_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + early2_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4]) + early2_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + early2_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4]) + early2_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + early2_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4]) + early2_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + early2_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == early_rise0[pt_i%4]) + early2_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + early2_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == early_fall0[pt_i%4]) + early2_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + early2_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == early_rise1[pt_i%4]) + early2_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + early2_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == early_fall1[pt_i%4]) + early2_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + early2_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + end + + + always @(posedge clk) begin + pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r; + pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r; + pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r; + pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r; + pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r; + pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r; + pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r; + pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r; + pat_data_match_r <= #TCQ (pat_match_rise0_and_r && + pat_match_fall0_and_r && + pat_match_rise1_and_r && + pat_match_fall1_and_r && + pat_match_rise2_and_r && + pat_match_fall2_and_r && + pat_match_rise3_and_r && + pat_match_fall3_and_r); + pat_data_match_valid_r <= #TCQ rd_active_r3; + end + + always @(posedge clk) begin + early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; + early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; + early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; + early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; + early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r; + early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r; + early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r; + early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r; + early1_data_match_r <= #TCQ (early1_match_rise0_and_r && + early1_match_fall0_and_r && + early1_match_rise1_and_r && + early1_match_fall1_and_r && + early1_match_rise2_and_r && + early1_match_fall2_and_r && + early1_match_rise3_and_r && + early1_match_fall3_and_r); + end + + always @(posedge clk) begin + early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r; + early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r; + early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r; + early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r; + early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r; + early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r; + early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r; + early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r; + early2_data_match_r <= #TCQ (early2_match_rise0_and_r && + early2_match_fall0_and_r && + early2_match_rise1_and_r && + early2_match_fall1_and_r && + early2_match_rise2_and_r && + early2_match_fall2_and_r && + early2_match_rise3_and_r && + early2_match_fall3_and_r); + end + + end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 + + for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) + pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) + pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) + pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) + pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4]) + pat2_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat2_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4]) + pat2_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat2_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4]) + pat2_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat2_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4]) + pat2_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat2_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4]) + early1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + early1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4]) + early1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + early1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4]) + early1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + early1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4]) + early1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + early1_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + // early2 in this case does not mean 2 cycles early but + // the second cycle of read data in 2:1 mode + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4]) + early2_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + early2_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4]) + early2_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + early2_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4]) + early2_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + early2_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4]) + early2_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + early2_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + end + + always @(posedge clk) begin + pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; + pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; + pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; + pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; + pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && + pat1_match_fall0_and_r && + pat1_match_rise1_and_r && + pat1_match_fall1_and_r); + pat1_data_match_r1 <= #TCQ pat1_data_match_r; + + pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3; + pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3; + pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3; + pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3; + pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r && + pat2_match_fall0_and_r && + pat2_match_rise1_and_r && + pat2_match_fall1_and_r); + + // For 2:1 mode, read valid is asserted for 2 clock cycles - + // here we generate a "match valid" pulse that is only 1 clock + // cycle wide that is simulatenous when the match calculation + // is complete + pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5; + end + + always @(posedge clk) begin + early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; + early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; + early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; + early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; + early1_data_match_r <= #TCQ (early1_match_rise0_and_r && + early1_match_fall0_and_r && + early1_match_rise1_and_r && + early1_match_fall1_and_r); + early1_data_match_r1 <= #TCQ early1_data_match_r; + + early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3; + early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3; + early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3; + early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3; + early2_data_match_r <= #TCQ (early2_match_rise0_and_r && + early2_match_fall0_and_r && + early2_match_rise1_and_r && + early2_match_fall1_and_r); + end + + end + endgenerate + + // Need to delay it by 3 cycles in order to wait for Phaser_Out + // coarse delay to take effect before issuing a write command + always @(posedge clk) begin + wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r; + wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1; + wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2; + end + + always @(posedge clk) begin + if (rst) + tap_inc_wait_cnt <= #TCQ 'd0; + else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) || + (cal2_state_r == CAL2_IFIFO_RESET) || + (cal2_state_r == CAL2_SANITY_WAIT)) + tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1; + else + tap_inc_wait_cnt <= #TCQ 'd0; + end + + always @(posedge clk) begin + if (rst) + not_empty_wait_cnt <= #TCQ 'd0; + else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait) + not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1; + else + not_empty_wait_cnt <= #TCQ 'd0; + end + + always @(posedge clk) + cal2_state_r1 <= #TCQ cal2_state_r; + + //***************************************************************** + // Write Calibration state machine + //***************************************************************** + + // when calibrating, check to see if the expected pattern is received. + // Otherwise delay DQS to align to correct CK edge. + // NOTES: + // 1. An error condition can occur due to two reasons: + // a. If the matching logic does not receive the expected data + // pattern. However, the error may be "recoverable" because + // the write calibration is still in progress. If an error is + // found the write calibration logic delays DQS by an additional + // clock cycle and restarts the pattern detection process. + // By design, if the write path timing is incorrect, the correct + // data pattern will never be detected. + // b. Valid data not found even after incrementing Phaser_Out + // coarse delay line. + + + always @(posedge clk) begin + if (rst) begin + wrcal_dqs_cnt_r <= #TCQ 'b0; + cal2_done_r <= #TCQ 1'b0; + cal2_prech_req_r <= #TCQ 1'b0; + cal2_state_r <= #TCQ CAL2_IDLE; + wrcal_pat_err <= #TCQ 1'b0; + wrcal_pat_resume_r <= #TCQ 1'b0; + wrcal_act_req <= #TCQ 1'b0; + cal2_if_reset <= #TCQ 1'b0; + temp_wrcal_done <= #TCQ 1'b0; + wrlvl_byte_redo <= #TCQ 1'b0; + early1_data <= #TCQ 1'b0; + early2_data <= #TCQ 1'b0; + idelay_ld <= #TCQ 1'b0; + idelay_ld_done <= #TCQ 1'b0; + pat1_detect <= #TCQ 1'b0; + early1_detect <= #TCQ 1'b0; + wrcal_sanity_chk_done <= #TCQ 1'b0; + wrcal_sanity_chk_err <= #TCQ 1'b0; + end else begin + cal2_prech_req_r <= #TCQ 1'b0; + case (cal2_state_r) + CAL2_IDLE: begin + wrcal_pat_err <= #TCQ 1'b0; + if (wrcal_start) begin + cal2_if_reset <= #TCQ 1'b0; + if (SIM_CAL_OPTION == "SKIP_CAL") + // If skip write calibration, then proceed to end. + cal2_state_r <= #TCQ CAL2_DONE; + else + cal2_state_r <= #TCQ CAL2_READ_WAIT; + end + end + + // General wait state to wait for read data to be output by the + // IN_FIFO + CAL2_READ_WAIT: begin + wrcal_pat_resume_r <= #TCQ 1'b0; + cal2_if_reset <= #TCQ 1'b0; + // Wait until read data is received, and pattern matching + // calculation is complete. NOTE: Need to add a timeout here + // in case for some reason data is never received (or rather + // the PHASER_IN and IN_FIFO think they never receives data) + if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin + if (pat_data_match_r) + // If found data match, then move on to next DQS group + cal2_state_r <= #TCQ CAL2_NEXT_DQS; + else begin + if (wrcal_sanity_chk_r) + cal2_state_r <= #TCQ CAL2_ERR; + // If writes are one or two cycles early then redo + // write leveling for the byte + else if (early1_data_match_r) begin + early1_data <= #TCQ 1'b1; + early2_data <= #TCQ 1'b0; + wrlvl_byte_redo <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; + end else if (early2_data_match_r) begin + early1_data <= #TCQ 1'b0; + early2_data <= #TCQ 1'b1; + wrlvl_byte_redo <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; + // Read late due to incorrect MPR idelay value + // Decrement Idelay to '0'for the current byte + end else if (~idelay_ld_done) begin + cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; + idelay_ld <= #TCQ 1'b1; + end else + cal2_state_r <= #TCQ CAL2_ERR; + end + end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin + if ((pat1_data_match_r1 && pat2_data_match_r) || + (pat1_detect && pat2_data_match_r)) + // If found data match, then move on to next DQS group + cal2_state_r <= #TCQ CAL2_NEXT_DQS; + else if (pat1_data_match_r1 && ~pat2_data_match_r) begin + cal2_state_r <= #TCQ CAL2_READ_WAIT; + pat1_detect <= #TCQ 1'b1; + end else begin + // If writes are one or two cycles early then redo + // write leveling for the byte + if (wrcal_sanity_chk_r) + cal2_state_r <= #TCQ CAL2_ERR; + else if ((early1_data_match_r1 && early2_data_match_r) || + (early1_detect && early2_data_match_r)) begin + early1_data <= #TCQ 1'b1; + early2_data <= #TCQ 1'b0; + wrlvl_byte_redo <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; + end else if (early1_data_match_r1 && ~early2_data_match_r) begin + early1_detect <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_READ_WAIT; + // Read late due to incorrect MPR idelay value + // Decrement Idelay to '0'for the current byte + end else if (~idelay_ld_done) begin + cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; + idelay_ld <= #TCQ 1'b1; + end else + cal2_state_r <= #TCQ CAL2_ERR; + end + end else if (not_empty_wait_cnt == 'd31) + cal2_state_r <= #TCQ CAL2_ERR; + end + + CAL2_WRLVL_WAIT: begin + early1_detect <= #TCQ 1'b0; + if (wrlvl_byte_done && ~wrlvl_byte_done_r) + wrlvl_byte_redo <= #TCQ 1'b0; + if (wrlvl_byte_done) begin + if (rd_active_r1 && ~rd_active_r) begin + cal2_state_r <= #TCQ CAL2_IFIFO_RESET; + cal2_if_reset <= #TCQ 1'b1; + early1_data <= #TCQ 1'b0; + early2_data <= #TCQ 1'b0; + end + end + end + + CAL2_DQ_IDEL_DEC: begin + if (tap_inc_wait_cnt == 'd4) begin + idelay_ld <= #TCQ 1'b0; + cal2_state_r <= #TCQ CAL2_IFIFO_RESET; + cal2_if_reset <= #TCQ 1'b1; + idelay_ld_done <= #TCQ 1'b1; + end + end + + CAL2_IFIFO_RESET: begin + if (tap_inc_wait_cnt == 'd15) begin + cal2_if_reset <= #TCQ 1'b0; + if (wrcal_sanity_chk_r) + cal2_state_r <= #TCQ CAL2_DONE; + else if (idelay_ld_done) begin + wrcal_pat_resume_r <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_READ_WAIT; + end else + cal2_state_r <= #TCQ CAL2_IDLE; + end + end + + // Final processing for current DQS group. Move on to next group + CAL2_NEXT_DQS: begin + // At this point, we've just found the correct pattern for the + // current DQS group. + + // Request bank/row precharge, and wait for its completion. Always + // precharge after each DQS group to avoid tRAS(max) violation + //verilint STARC-2.2.3.3 off + if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin + cal2_prech_req_r <= #TCQ 1'b0; + wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; + cal2_state_r <= #TCQ CAL2_SANITY_WAIT; + end else + cal2_prech_req_r <= #TCQ 1'b1; + idelay_ld_done <= #TCQ 1'b0; + pat1_detect <= #TCQ 1'b0; + if (prech_done) + if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) || + (wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin + // If either FAST_CAL is enabled and first DQS group is + // finished, or if the last DQS group was just finished, + // then end of write calibration + if (wrcal_sanity_chk_r) begin + cal2_if_reset <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_IFIFO_RESET; + end else + cal2_state_r <= #TCQ CAL2_DONE; + end else begin + // Continue to next DQS group + wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; + cal2_state_r <= #TCQ CAL2_READ_WAIT; + end + end + //verilint STARC-2.2.3.3 on + CAL2_SANITY_WAIT: begin + if (tap_inc_wait_cnt == 'd15) begin + cal2_state_r <= #TCQ CAL2_READ_WAIT; + wrcal_pat_resume_r <= #TCQ 1'b1; + end + end + + // Finished with read enable calibration + CAL2_DONE: begin + if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin + cal2_done_r <= #TCQ 1'b0; + wrcal_dqs_cnt_r <= #TCQ 'd0; + cal2_state_r <= #TCQ CAL2_IDLE; + end else + cal2_done_r <= #TCQ 1'b1; + cal2_prech_req_r <= #TCQ 1'b0; + cal2_if_reset <= #TCQ 1'b0; + if (wrcal_sanity_chk_r) + wrcal_sanity_chk_done <= #TCQ 1'b1; + end + + // Assert error signal indicating that writes timing is incorrect + CAL2_ERR: begin + wrcal_pat_resume_r <= #TCQ 1'b0; + if (wrcal_sanity_chk_r) + wrcal_sanity_chk_err <= #TCQ 1'b1; + else + wrcal_pat_err <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_ERR; + end + endcase + end + end + + // Delay assertion of wrcal_done for write calibration by a few cycles after + // we've reached CAL2_DONE + always @(posedge clk) + if (rst) + cal2_done_r1 <= #TCQ 1'b0; + else + cal2_done_r1 <= #TCQ cal2_done_r; + + always @(posedge clk) + if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r)) + wrcal_done <= #TCQ 1'b0; + else if (cal2_done_r) + wrcal_done <= #TCQ 1'b1; + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_wrlvl.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_wrlvl.v new file mode 100644 index 0000000..9f3a811 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_wrlvl.v @@ -0,0 +1,1218 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_wrlvl.v +// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ +// \ \ / \ Date Created: Mon Jun 23 2008 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// Memory initialization and overall master state control during +// initialization and calibration. Specifically, the following functions +// are performed: +// 1. Memory initialization (initial AR, mode register programming, etc.) +// 2. Initiating write leveling +// 3. Generate training pattern writes for read leveling. Generate +// memory readback for read leveling. +// This module has a DFI interface for providing control/address and write +// data to the rest of the PHY datapath during initialization/calibration. +// Once initialization is complete, control is passed to the MC. +// NOTES: +// 1. Multiple CS (multi-rank) not supported +// 2. DDR2 not supported +// 3. ODT not supported +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_wrlvl.v,v 1.3 2011/06/24 14:49:00 mgeorge Exp $ +**$Date: 2011/06/24 14:49:00 $ +**$Author: mgeorge $ +**$Revision: 1.3 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_wrlvl.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_wrlvl # + ( + parameter TCQ = 100, + parameter DQS_CNT_WIDTH = 3, + parameter DQ_WIDTH = 64, + parameter DQS_WIDTH = 2, + parameter DRAM_WIDTH = 8, + parameter RANKS = 1, + parameter nCK_PER_CLK = 4, + parameter CLK_PERIOD = 4, + parameter SIM_CAL_OPTION = "NONE" + ) + ( + input clk, + input rst, + input phy_ctl_ready, + input wr_level_start, + input wl_sm_start, + input wrlvl_final, + input wrlvl_byte_redo, + input [DQS_CNT_WIDTH:0] wrcal_cnt, + input early1_data, + input early2_data, + input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt, + input oclkdelay_calib_done, + input [(DQ_WIDTH)-1:0] rd_data_rise0, + output reg wrlvl_byte_done, + output reg dqs_po_dec_done /* synthesis syn_maxfan = 2 */, + output phy_ctl_rdy_dly, + output reg wr_level_done /* synthesis syn_maxfan = 2 */, + // to phy_init for cs logic + output wrlvl_rank_done, + output done_dqs_tap_inc, + output [DQS_CNT_WIDTH:0] po_stg2_wl_cnt, + // Fine delay line used only during write leveling + // Inc/dec Phaser_Out fine delay line + output reg dqs_po_stg2_f_incdec, + // Enable Phaser_Out fine delay inc/dec + output reg dqs_po_en_stg2_f, + // Coarse delay line used during write leveling + // only if 64 taps of fine delay line were not + // sufficient to detect a 0->1 transition + // Inc Phaser_Out coarse delay line + output reg dqs_wl_po_stg2_c_incdec, + // Enable Phaser_Out coarse delay inc/dec + output reg dqs_wl_po_en_stg2_c, + // Read Phaser_Out delay value + input [8:0] po_counter_read_val, +// output reg dqs_wl_po_stg2_load, +// output reg [8:0] dqs_wl_po_stg2_reg_l, + // CK edge undetected + output reg wrlvl_err, + output reg [3*DQS_WIDTH-1:0] wl_po_coarse_cnt, + output reg [6*DQS_WIDTH-1:0] wl_po_fine_cnt, + // Debug ports + output [5:0] dbg_wl_tap_cnt, + output dbg_wl_edge_detect_valid, + output [(DQS_WIDTH)-1:0] dbg_rd_data_edge_detect, + output [DQS_CNT_WIDTH:0] dbg_dqs_count, + output [4:0] dbg_wl_state, + output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, + output [255:0] dbg_phy_wrlvl + ); + + + localparam WL_IDLE = 5'h0; + localparam WL_INIT = 5'h1; + localparam WL_INIT_FINE_INC = 5'h2; + localparam WL_INIT_FINE_INC_WAIT1= 5'h3; + localparam WL_INIT_FINE_INC_WAIT = 5'h4; + localparam WL_INIT_FINE_DEC = 5'h5; + localparam WL_INIT_FINE_DEC_WAIT = 5'h6; + localparam WL_FINE_INC = 5'h7; + localparam WL_WAIT = 5'h8; + localparam WL_EDGE_CHECK = 5'h9; + localparam WL_DQS_CHECK = 5'hA; + localparam WL_DQS_CNT = 5'hB; + localparam WL_2RANK_TAP_DEC = 5'hC; + localparam WL_2RANK_DQS_CNT = 5'hD; + localparam WL_FINE_DEC = 5'hE; + localparam WL_FINE_DEC_WAIT = 5'hF; + localparam WL_CORSE_INC = 5'h10; + localparam WL_CORSE_INC_WAIT = 5'h11; + localparam WL_CORSE_INC_WAIT1 = 5'h12; + localparam WL_CORSE_INC_WAIT2 = 5'h13; + localparam WL_CORSE_DEC = 5'h14; + localparam WL_CORSE_DEC_WAIT = 5'h15; + localparam WL_CORSE_DEC_WAIT1 = 5'h16; + localparam WL_FINE_INC_WAIT = 5'h17; + localparam WL_2RANK_FINAL_TAP = 5'h18; + localparam WL_INIT_FINE_DEC_WAIT1= 5'h19; + localparam WL_FINE_DEC_WAIT1 = 5'h1A; + localparam WL_CORSE_INC_WAIT_TMP = 5'h1B; + + localparam COARSE_TAPS = 7; + + localparam FAST_CAL_FINE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 45 : 48; + localparam FAST_CAL_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 1 : 2; + localparam REDO_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 2 : 5; + + + integer i, j, k, l, p, q, r, s, t, m, n, u, v, w, x,y; + + reg phy_ctl_ready_r1; + reg phy_ctl_ready_r2; + reg phy_ctl_ready_r3; + reg phy_ctl_ready_r4; + reg phy_ctl_ready_r5; + reg phy_ctl_ready_r6; + (* max_fanout = 50 *) reg [DQS_CNT_WIDTH:0] dqs_count_r; + reg [1:0] rank_cnt_r; + reg [DQS_WIDTH-1:0] rd_data_rise_wl_r; + reg [DQS_WIDTH-1:0] rd_data_previous_r; + reg [DQS_WIDTH-1:0] rd_data_edge_detect_r; + reg wr_level_done_r; + reg wrlvl_rank_done_r; + reg wr_level_start_r; + reg [4:0] wl_state_r, wl_state_r1; + reg inhibit_edge_detect_r; + reg wl_edge_detect_valid_r; + reg [5:0] wl_tap_count_r; + reg [5:0] fine_dec_cnt; + reg [5:0] fine_inc[0:DQS_WIDTH-1]; // DQS_WIDTH number of counters 6-bit each + reg [2:0] corse_dec[0:DQS_WIDTH-1]; + reg [2:0] corse_inc[0:DQS_WIDTH-1]; + reg dq_cnt_inc; + reg [3:0] stable_cnt; + reg flag_ck_negedge; + //reg past_negedge; + reg flag_init; + reg [2:0] corse_cnt[0:DQS_WIDTH-1]; + reg [3*DQS_WIDTH-1:0] corse_cnt_dbg; + reg [2:0] wl_corse_cnt[0:RANKS-1][0:DQS_WIDTH-1]; + //reg [3*DQS_WIDTH-1:0] coarse_tap_inc; + reg [2:0] final_coarse_tap[0:DQS_WIDTH-1]; + reg [5:0] add_smallest[0:DQS_WIDTH-1]; + reg [5:0] add_largest[0:DQS_WIDTH-1]; + //reg [6*DQS_WIDTH-1:0] fine_tap_inc; + //reg [6*DQS_WIDTH-1:0] fine_tap_dec; + reg wr_level_done_r1; + reg wr_level_done_r2; + reg wr_level_done_r3; + reg wr_level_done_r4; + reg wr_level_done_r5; + reg [5:0] wl_dqs_tap_count_r[0:RANKS-1][0:DQS_WIDTH-1]; + reg [5:0] smallest[0:DQS_WIDTH-1]; + reg [5:0] largest[0:DQS_WIDTH-1]; + reg [5:0] final_val[0:DQS_WIDTH-1]; + reg [5:0] po_dec_cnt[0:DQS_WIDTH-1]; + reg done_dqs_dec; + reg [8:0] po_rdval_cnt; + reg po_cnt_dec; + reg po_dec_done; + reg dual_rnk_dec; + wire [DQS_CNT_WIDTH+2:0] dqs_count_w; + reg [5:0] fast_cal_fine_cnt; + reg [2:0] fast_cal_coarse_cnt; + reg wrlvl_byte_redo_r; + reg [2:0] wrlvl_redo_corse_inc; + reg wrlvl_final_r; + reg final_corse_dec; + wire [DQS_CNT_WIDTH+2:0] oclk_count_w; + reg wrlvl_tap_done_r ; + reg [3:0] wait_cnt; + reg [3:0] incdec_wait_cnt; + + + + // Debug ports + assign dbg_wl_edge_detect_valid = wl_edge_detect_valid_r; + assign dbg_rd_data_edge_detect = rd_data_edge_detect_r; + assign dbg_wl_tap_cnt = wl_tap_count_r; + assign dbg_dqs_count = dqs_count_r; + assign dbg_wl_state = wl_state_r; + assign dbg_wrlvl_fine_tap_cnt = wl_po_fine_cnt; + assign dbg_wrlvl_coarse_tap_cnt = wl_po_coarse_cnt; + + always @(*) begin + for (v = 0; v < DQS_WIDTH; v = v + 1) + corse_cnt_dbg[3*v+:3] = corse_cnt[v]; + end + + assign dbg_phy_wrlvl[0+:27] = corse_cnt_dbg; + assign dbg_phy_wrlvl[27+:5] = wl_state_r; + assign dbg_phy_wrlvl[32+:4] = dqs_count_r; + assign dbg_phy_wrlvl[36+:9] = rd_data_rise_wl_r; + assign dbg_phy_wrlvl[45+:9] = rd_data_previous_r; + assign dbg_phy_wrlvl[54+:4] = stable_cnt; + assign dbg_phy_wrlvl[58] = 'd0; + assign dbg_phy_wrlvl[59] = flag_ck_negedge; + + assign dbg_phy_wrlvl [60] = wl_edge_detect_valid_r; + assign dbg_phy_wrlvl [61+:6] = wl_tap_count_r; + assign dbg_phy_wrlvl [67+:9] = rd_data_edge_detect_r; + assign dbg_phy_wrlvl [76+:54] = wl_po_fine_cnt; + assign dbg_phy_wrlvl [130+:27] = wl_po_coarse_cnt; + + + + //************************************************************************** + // DQS count to hard PHY during write leveling using Phaser_OUT Stage2 delay + //************************************************************************** + assign po_stg2_wl_cnt = dqs_count_r; + + assign wrlvl_rank_done = wrlvl_rank_done_r; + + assign done_dqs_tap_inc = done_dqs_dec; + + assign phy_ctl_rdy_dly = phy_ctl_ready_r6; + + always @(posedge clk) begin + phy_ctl_ready_r1 <= #TCQ phy_ctl_ready; + phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1; + phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2; + phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3; + phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4; + phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5; + wrlvl_byte_redo_r <= #TCQ wrlvl_byte_redo; + wrlvl_final_r <= #TCQ wrlvl_final; + if ((wrlvl_byte_redo && ~wrlvl_byte_redo_r) || + (wrlvl_final && ~wrlvl_final_r)) + wr_level_done <= #TCQ 1'b0; + else + wr_level_done <= #TCQ done_dqs_dec; + end + +// Status signal that will be asserted once the first +// pass of write leveling is done. + always @(posedge clk) begin + if(rst) begin + wrlvl_tap_done_r <= #TCQ 1'b0 ; + end else begin + if(wrlvl_tap_done_r == 1'b0) begin + if(oclkdelay_calib_done) begin + wrlvl_tap_done_r <= #TCQ 1'b1 ; + end + end + end + end + + always @(posedge clk) begin + if (rst || po_cnt_dec) + wait_cnt <= #TCQ 'd8; + else if (phy_ctl_ready_r6 && (wait_cnt > 'd0)) + wait_cnt <= #TCQ wait_cnt - 1; + end + + always @(posedge clk) begin + if (rst) begin + po_rdval_cnt <= #TCQ 'd0; + end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin + po_rdval_cnt <= #TCQ po_counter_read_val; + end else if (po_rdval_cnt > 'd0) begin + if (po_cnt_dec) + po_rdval_cnt <= #TCQ po_rdval_cnt - 1; + else + po_rdval_cnt <= #TCQ po_rdval_cnt; + end else if (po_rdval_cnt == 'd0) begin + po_rdval_cnt <= #TCQ po_rdval_cnt; + end + end + + always @(posedge clk) begin + if (rst || (po_rdval_cnt == 'd0)) + po_cnt_dec <= #TCQ 1'b0; + else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (wait_cnt == 'd1)) + po_cnt_dec <= #TCQ 1'b1; + else + po_cnt_dec <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst) + po_dec_done <= #TCQ 1'b0; + else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) || + (phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin + po_dec_done <= #TCQ 1'b1; + end + end + + + always @(posedge clk) begin + dqs_po_dec_done <= #TCQ po_dec_done; + wr_level_done_r1 <= #TCQ wr_level_done_r; + wr_level_done_r2 <= #TCQ wr_level_done_r1; + wr_level_done_r3 <= #TCQ wr_level_done_r2; + wr_level_done_r4 <= #TCQ wr_level_done_r3; + wr_level_done_r5 <= #TCQ wr_level_done_r4; + for (l = 0; l < DQS_WIDTH; l = l + 1) begin + wl_po_coarse_cnt[3*l+:3] <= #TCQ final_coarse_tap[l]; + if ((RANKS == 1) || ~oclkdelay_calib_done) + wl_po_fine_cnt[6*l+:6] <= #TCQ smallest[l]; + else + wl_po_fine_cnt[6*l+:6] <= #TCQ final_val[l]; + end + end + + generate + if (RANKS == 2) begin: dual_rank + always @(posedge clk) begin + if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) || + (wrlvl_final && ~wrlvl_final_r)) + done_dqs_dec <= #TCQ 1'b0; + else if ((SIM_CAL_OPTION == "FAST_CAL") || ~oclkdelay_calib_done) + done_dqs_dec <= #TCQ wr_level_done_r; + else if (wr_level_done_r5 && (wl_state_r == WL_IDLE)) + done_dqs_dec <= #TCQ 1'b1; + end + end else begin: single_rank + always @(posedge clk) begin + if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) || + (wrlvl_final && ~wrlvl_final_r)) + done_dqs_dec <= #TCQ 1'b0; + else if (~oclkdelay_calib_done) + done_dqs_dec <= #TCQ wr_level_done_r; + else if (wr_level_done_r3 && ~wr_level_done_r4) + done_dqs_dec <= #TCQ 1'b1; + end + end + endgenerate + + always @(posedge clk) + if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r)) + wrlvl_byte_done <= #TCQ 1'b0; + else if (wrlvl_byte_redo && wr_level_done_r3 && ~wr_level_done_r4) + wrlvl_byte_done <= #TCQ 1'b1; + + // Storing DQS tap values at the end of each DQS write leveling + always @(posedge clk) begin + if (rst) begin + for (k = 0; k < RANKS; k = k + 1) begin: rst_wl_dqs_tap_count_loop + for (n = 0; n < DQS_WIDTH; n = n + 1) begin + wl_corse_cnt[k][n] <= #TCQ 'b0; + wl_dqs_tap_count_r[k][n] <= #TCQ 'b0; + end + end + end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_WAIT) | + (wl_state_r == WL_FINE_DEC_WAIT1) | + (wl_state_r == WL_2RANK_TAP_DEC)) begin + wl_dqs_tap_count_r[rank_cnt_r][dqs_count_r] <= #TCQ wl_tap_count_r; + wl_corse_cnt[rank_cnt_r][dqs_count_r] <= #TCQ corse_cnt[dqs_count_r]; + end else if ((SIM_CAL_OPTION == "FAST_CAL") & (wl_state_r == WL_DQS_CHECK)) begin + for (p = 0; p < RANKS; p = p +1) begin: dqs_tap_rank_cnt + for(q = 0; q < DQS_WIDTH; q = q +1) begin: dqs_tap_dqs_cnt + wl_dqs_tap_count_r[p][q] <= #TCQ wl_tap_count_r; + wl_corse_cnt[p][q] <= #TCQ corse_cnt[0]; + end + end + end + end + + // Convert coarse delay to fine taps in case of unequal number of coarse + // taps between ranks. Assuming a difference of 1 coarse tap counts + // between ranks. A common fine and coarse tap value must be used for both ranks + // because Phaser_Out has only one rank register. + // Coarse tap1 = period(ps)*93/360 = 34 fine taps + // Other coarse taps = period(ps)*103/360 = 38 fine taps + + generate + genvar cnt; + if (RANKS == 2) begin // Dual rank + for(cnt = 0; cnt < DQS_WIDTH; cnt = cnt +1) begin: coarse_dqs_cnt + always @(posedge clk) begin + if (rst) begin + //coarse_tap_inc[3*cnt+:3] <= #TCQ 'b0; + add_smallest[cnt] <= #TCQ 'd0; + add_largest[cnt] <= #TCQ 'd0; + final_coarse_tap[cnt] <= #TCQ 'd0; + end else if (wr_level_done_r1 & ~wr_level_done_r2) begin + if (~oclkdelay_calib_done) begin + for(y = 0 ; y < DQS_WIDTH; y = y+1) begin + final_coarse_tap[y] <= #TCQ wl_corse_cnt[0][y]; + add_smallest[y] <= #TCQ 'd0; + add_largest[y] <= #TCQ 'd0; + end + end else + if (wl_corse_cnt[0][cnt] == wl_corse_cnt[1][cnt]) begin + // Both ranks have use the same number of coarse delay taps. + // No conversion of coarse tap to fine taps required. + //coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3]; + final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt]; + add_smallest[cnt] <= #TCQ 'd0; + add_largest[cnt] <= #TCQ 'd0; + end else if (wl_corse_cnt[0][cnt] < wl_corse_cnt[1][cnt]) begin + // Rank 0 uses fewer coarse delay taps than rank1. + // conversion of coarse tap to fine taps required for rank1. + // The final coarse count will the smaller value. + //coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3] - 1; + final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt] - 1; + if (|wl_corse_cnt[0][cnt]) + // Coarse tap 2 or higher being converted to fine taps + // This will be added to 'largest' value in final_val + // computation + add_largest[cnt] <= #TCQ 'd38; + else + // Coarse tap 1 being converted to fine taps + // This will be added to 'largest' value in final_val + // computation + add_largest[cnt] <= #TCQ 'd34; + end else if (wl_corse_cnt[0][cnt] > wl_corse_cnt[1][cnt]) begin + // This may be an unlikely scenario in a real system. + // Rank 0 uses more coarse delay taps than rank1. + // conversion of coarse tap to fine taps required. + //coarse_tap_inc[3*cnt+:3] <= #TCQ 'd0; + final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt]; + if (|wl_corse_cnt[1][cnt]) + // Coarse tap 2 or higher being converted to fine taps + // This will be added to 'smallest' value in final_val + // computation + add_smallest[cnt] <= #TCQ 'd38; + else + // Coarse tap 1 being converted to fine taps + // This will be added to 'smallest' value in + // final_val computation + add_smallest[cnt] <= #TCQ 'd34; + end + end + end + end + end else begin + // Single rank + always @(posedge clk) begin + //coarse_tap_inc <= #TCQ 'd0; + for(w = 0; w < DQS_WIDTH; w = w + 1) begin + final_coarse_tap[w] <= #TCQ wl_corse_cnt[0][w]; + add_smallest[w] <= #TCQ 'd0; + add_largest[w] <= #TCQ 'd0; + end + end + end + endgenerate + + + // Determine delay value for DQS in multirank system + // Assuming delay value is the smallest for rank 0 DQS + // and largest delay value for rank 4 DQS + // Set to smallest + ((largest-smallest)/2) + always @(posedge clk) begin + if (rst) begin + for(x = 0; x < DQS_WIDTH; x = x +1) begin + smallest[x] <= #TCQ 'b0; + largest[x] <= #TCQ 'b0; + end + end else if ((wl_state_r == WL_DQS_CNT) & wrlvl_byte_redo) begin + smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; + largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; + end else if ((wl_state_r == WL_DQS_CNT) | + (wl_state_r == WL_2RANK_TAP_DEC)) begin + smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; + largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[RANKS-1][dqs_count_r]; + end else if (((SIM_CAL_OPTION == "FAST_CAL") | + (~oclkdelay_calib_done & ~wrlvl_byte_redo)) & + wr_level_done_r1 & ~wr_level_done_r2) begin + for(i = 0; i < DQS_WIDTH; i = i +1) begin: smallest_dqs + smallest[i] <= #TCQ wl_dqs_tap_count_r[0][i]; + largest[i] <= #TCQ wl_dqs_tap_count_r[0][i]; + end + end + end + + +// final_val to be used for all DQSs in all ranks + genvar wr_i; + generate + for (wr_i = 0; wr_i < DQS_WIDTH; wr_i = wr_i +1) begin: gen_final_tap + always @(posedge clk) begin + if (rst) + final_val[wr_i] <= #TCQ 'b0; + else if (wr_level_done_r2 && ~wr_level_done_r3) begin + if (~oclkdelay_calib_done) + final_val[wr_i] <= #TCQ (smallest[wr_i] + add_smallest[wr_i]); + else if ((smallest[wr_i] + add_smallest[wr_i]) < + (largest[wr_i] + add_largest[wr_i])) + final_val[wr_i] <= #TCQ ((smallest[wr_i] + add_smallest[wr_i]) + + (((largest[wr_i] + add_largest[wr_i]) - + (smallest[wr_i] + add_smallest[wr_i]))/2)); + else if ((smallest[wr_i] + add_smallest[wr_i]) > + (largest[wr_i] + add_largest[wr_i])) + final_val[wr_i] <= #TCQ ((largest[wr_i] + add_largest[wr_i]) + + (((smallest[wr_i] + add_smallest[wr_i]) - + (largest[wr_i] + add_largest[wr_i]))/2)); + else if ((smallest[wr_i] + add_smallest[wr_i]) == + (largest[wr_i] + add_largest[wr_i])) + final_val[wr_i] <= #TCQ (largest[wr_i] + add_largest[wr_i]); + end + end + end + endgenerate + +// // fine tap inc/dec value for all DQSs in all ranks +// genvar dqs_i; +// generate +// for (dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i +1) begin: gen_fine_tap +// always @(posedge clk) begin +// if (rst) +// fine_tap_inc[6*dqs_i+:6] <= #TCQ 'd0; +// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0; +// else if (wr_level_done_r3 && ~wr_level_done_r4) begin +// fine_tap_inc[6*dqs_i+:6] <= #TCQ final_val[6*dqs_i+:6]; +// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0; +// end +// end +// endgenerate + + + // Inc/Dec Phaser_Out stage 2 fine delay line + always @(posedge clk) begin + if (rst) begin + // Fine delay line used only during write leveling + dqs_po_stg2_f_incdec <= #TCQ 1'b0; + dqs_po_en_stg2_f <= #TCQ 1'b0; + // Dec Phaser_Out fine delay (1)before write leveling, + // (2)if no 0 to 1 transition detected with 63 fine delay taps, or + // (3)dual rank case where fine taps for the first rank need to be 0 + end else if (po_cnt_dec || (wl_state_r == WL_INIT_FINE_DEC) || + (wl_state_r == WL_FINE_DEC)) begin + dqs_po_stg2_f_incdec <= #TCQ 1'b0; + dqs_po_en_stg2_f <= #TCQ 1'b1; + // Inc Phaser_Out fine delay during write leveling + end else if ((wl_state_r == WL_INIT_FINE_INC) || + (wl_state_r == WL_FINE_INC)) begin + dqs_po_stg2_f_incdec <= #TCQ 1'b1; + dqs_po_en_stg2_f <= #TCQ 1'b1; + end else begin + dqs_po_stg2_f_incdec <= #TCQ 1'b0; + dqs_po_en_stg2_f <= #TCQ 1'b0; + end + end + + + // Inc Phaser_Out stage 2 Coarse delay line + always @(posedge clk) begin + if (rst) begin + // Coarse delay line used during write leveling + // only if no 0->1 transition undetected with 64 + // fine delay line taps + dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0; + dqs_wl_po_en_stg2_c <= #TCQ 1'b0; + end else if (wl_state_r == WL_CORSE_INC) begin + // Inc Phaser_Out coarse delay during write leveling + dqs_wl_po_stg2_c_incdec <= #TCQ 1'b1; + dqs_wl_po_en_stg2_c <= #TCQ 1'b1; + end else begin + dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0; + dqs_wl_po_en_stg2_c <= #TCQ 1'b0; + end + end + + + // only storing the rise data for checking. The data comming back during + // write leveling will be a static value. Just checking for rise data is + // enough. + +genvar rd_i; +generate + for(rd_i = 0; rd_i < DQS_WIDTH; rd_i = rd_i +1)begin: gen_rd + always @(posedge clk) + rd_data_rise_wl_r[rd_i] <= + #TCQ |rd_data_rise0[(rd_i*DRAM_WIDTH)+DRAM_WIDTH-1:rd_i*DRAM_WIDTH]; + end +endgenerate + + + // storing the previous data for checking later. + always @(posedge clk)begin + if ((wl_state_r == WL_INIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT) || + //(wl_state_r == WL_INIT_FINE_INC_WAIT1) || + ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)) || + (wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_FINE_DEC_WAIT) || + (wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) || + (wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2) || + ((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r))) + rd_data_previous_r <= #TCQ rd_data_rise_wl_r; + end + + // changed stable count from 3 to 7 because of fine tap resolution + always @(posedge clk)begin + if (rst | (wl_state_r == WL_DQS_CNT) | + (wl_state_r == WL_2RANK_TAP_DEC) | + (wl_state_r == WL_FINE_DEC) | + (rd_data_previous_r[dqs_count_r] != rd_data_rise_wl_r[dqs_count_r]) | + (wl_state_r1 == WL_INIT_FINE_DEC)) + stable_cnt <= #TCQ 'd0; + else if ((wl_tap_count_r > 6'd0) & + (((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)) | + ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)))) begin + if ((rd_data_previous_r[dqs_count_r] == rd_data_rise_wl_r[dqs_count_r]) + & (stable_cnt < 'd14)) + stable_cnt <= #TCQ stable_cnt + 1; + end + end + + // Signal to ensure that flag_ck_negedge does not incorrectly assert + // when DQS is very close to CK rising edge + //always @(posedge clk) begin + // if (rst | (wl_state_r == WL_DQS_CNT) | + // (wl_state_r == WL_DQS_CHECK) | wr_level_done_r) + // past_negedge <= #TCQ 1'b0; + // else if (~flag_ck_negedge && ~rd_data_previous_r[dqs_count_r] && + // (stable_cnt == 'd0) && ((wl_state_r == WL_CORSE_INC_WAIT1) | + // (wl_state_r == WL_CORSE_INC_WAIT2))) + // past_negedge <= #TCQ 1'b1; + //end + + // Flag to indicate negedge of CK detected and ignore 0->1 transitions + // in this region + always @(posedge clk)begin + if (rst | (wl_state_r == WL_DQS_CNT) | + (wl_state_r == WL_DQS_CHECK) | wr_level_done_r | + (wl_state_r1 == WL_INIT_FINE_DEC)) + flag_ck_negedge <= #TCQ 1'd0; + else if ((rd_data_previous_r[dqs_count_r] && ((stable_cnt > 'd0) | + (wl_state_r == WL_FINE_DEC) | (wl_state_r == WL_FINE_DEC_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1))) | + (wl_state_r == WL_CORSE_INC)) + flag_ck_negedge <= #TCQ 1'd1; + else if (~rd_data_previous_r[dqs_count_r] && (stable_cnt == 'd14)) + //&& flag_ck_negedge) + flag_ck_negedge <= #TCQ 1'd0; + end + + // Flag to inhibit rd_data_edge_detect_r before stable DQ + always @(posedge clk) begin + if (rst) + flag_init <= #TCQ 1'b1; + else if ((wl_state_r == WL_WAIT) && ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) || + (wl_state_r1 == WL_INIT_FINE_DEC_WAIT))) + flag_init <= #TCQ 1'b0; + end + + //checking for transition from 0 to 1 + always @(posedge clk)begin + if (rst | flag_ck_negedge | flag_init | (wl_tap_count_r < 'd1) | + inhibit_edge_detect_r) + rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; + else if (rd_data_edge_detect_r[dqs_count_r] == 1'b1) begin + if ((wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT) || (wl_state_r == WL_FINE_DEC_WAIT1) || + (wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) || + (wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2)) + rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; + else + rd_data_edge_detect_r <= #TCQ rd_data_edge_detect_r; + end else if (rd_data_previous_r[dqs_count_r] && (stable_cnt < 'd14)) + rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; + else + rd_data_edge_detect_r <= #TCQ (~rd_data_previous_r & rd_data_rise_wl_r); + end + + + + // registring the write level start signal + always@(posedge clk) begin + wr_level_start_r <= #TCQ wr_level_start; + end + + // Assign dqs_count_r to dqs_count_w to perform the shift operation + // instead of multiply operation + assign dqs_count_w = {2'b00, dqs_count_r}; + + assign oclk_count_w = {2'b00, oclkdelay_calib_cnt}; + + always @(posedge clk) begin + if (rst) + incdec_wait_cnt <= #TCQ 'd0; + else if ((wl_state_r == WL_FINE_DEC_WAIT1) || + (wl_state_r == WL_INIT_FINE_DEC_WAIT1) || + (wl_state_r == WL_CORSE_INC_WAIT_TMP)) + incdec_wait_cnt <= #TCQ incdec_wait_cnt + 1; + else + incdec_wait_cnt <= #TCQ 'd0; + end + + + // state machine to initiate the write leveling sequence + // The state machine operates on one byte at a time. + // It will increment the delays to the DQS OSERDES + // and sample the DQ from the memory. When it detects + // a transition from 1 to 0 then the write leveling is considered + // done. + always @(posedge clk) begin + if(rst)begin + wrlvl_err <= #TCQ 1'b0; + wr_level_done_r <= #TCQ 1'b0; + wrlvl_rank_done_r <= #TCQ 1'b0; + dqs_count_r <= #TCQ {DQS_CNT_WIDTH+1{1'b0}}; + dq_cnt_inc <= #TCQ 1'b1; + rank_cnt_r <= #TCQ 2'b00; + wl_state_r <= #TCQ WL_IDLE; + wl_state_r1 <= #TCQ WL_IDLE; + inhibit_edge_detect_r <= #TCQ 1'b1; + wl_edge_detect_valid_r <= #TCQ 1'b0; + wl_tap_count_r <= #TCQ 6'd0; + fine_dec_cnt <= #TCQ 6'd0; + for (r = 0; r < DQS_WIDTH; r = r + 1) begin + fine_inc[r] <= #TCQ 6'b0; + corse_dec[r] <= #TCQ 3'b0; + corse_inc[r] <= #TCQ 3'b0; + corse_cnt[r] <= #TCQ 3'b0; + end + dual_rnk_dec <= #TCQ 1'b0; + fast_cal_fine_cnt <= #TCQ FAST_CAL_FINE; + fast_cal_coarse_cnt <= #TCQ FAST_CAL_COARSE; + final_corse_dec <= #TCQ 1'b0; + //zero_tran_r <= #TCQ 1'b0; + wrlvl_redo_corse_inc <= #TCQ 'd0; + end else begin + wl_state_r1 <= #TCQ wl_state_r; + case (wl_state_r) + + WL_IDLE: begin + wrlvl_rank_done_r <= #TCQ 1'd0; + inhibit_edge_detect_r <= #TCQ 1'b1; + if (wrlvl_byte_redo && ~wrlvl_byte_redo_r) begin + wr_level_done_r <= #TCQ 1'b0; + dqs_count_r <= #TCQ wrcal_cnt; + corse_cnt[wrcal_cnt] <= #TCQ final_coarse_tap[wrcal_cnt]; + wl_tap_count_r <= #TCQ smallest[wrcal_cnt]; + if (early1_data && + (((final_coarse_tap[wrcal_cnt] < 'd6) && (CLK_PERIOD/nCK_PER_CLK <= 2500)) || + ((final_coarse_tap[wrcal_cnt] < 'd3) && (CLK_PERIOD/nCK_PER_CLK > 2500)))) + wrlvl_redo_corse_inc <= #TCQ REDO_COARSE; + else if (early2_data && (final_coarse_tap[wrcal_cnt] < 'd2)) + wrlvl_redo_corse_inc <= #TCQ 3'd6; + else begin + wl_state_r <= #TCQ WL_IDLE; + wrlvl_err <= #TCQ 1'b1; + end + end else if (wrlvl_final && ~wrlvl_final_r) begin + wr_level_done_r <= #TCQ 1'b0; + dqs_count_r <= #TCQ 'd0; + end + // verilint STARC-2.2.3.3 off + if(!wr_level_done_r & wr_level_start_r & wl_sm_start) begin + if (SIM_CAL_OPTION == "FAST_CAL") + wl_state_r <= #TCQ WL_FINE_INC; + else + wl_state_r <= #TCQ WL_INIT; + end + end + // verilint STARC-2.2.3.3 on + WL_INIT: begin + wl_edge_detect_valid_r <= #TCQ 1'b0; + inhibit_edge_detect_r <= #TCQ 1'b1; + wrlvl_rank_done_r <= #TCQ 1'd0; + //zero_tran_r <= #TCQ 1'b0; + if (wrlvl_final) + corse_cnt[dqs_count_w ] <= #TCQ final_coarse_tap[dqs_count_w ]; + if (wrlvl_byte_redo) begin + if (|wl_tap_count_r) begin + wl_state_r <= #TCQ WL_FINE_DEC; + fine_dec_cnt <= #TCQ wl_tap_count_r; + end else if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7) + wl_state_r <= #TCQ WL_CORSE_INC; + else begin + wl_state_r <= #TCQ WL_IDLE; + wrlvl_err <= #TCQ 1'b1; + end + end else if(wl_sm_start) + wl_state_r <= #TCQ WL_INIT_FINE_INC; + end + + // Initially Phaser_Out fine delay taps incremented + // until stable_cnt=14. A stable_cnt of 14 indicates + // that rd_data_rise_wl_r=rd_data_previous_r for 14 fine + // tap increments. This is done to inhibit false 0->1 + // edge detection when DQS is initially aligned to the + // negedge of CK + WL_INIT_FINE_INC: begin + wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT1; + wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1; + final_corse_dec <= #TCQ 1'b0; + end + + WL_INIT_FINE_INC_WAIT1: begin + if (wl_sm_start) + wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT; + end + + // Case1: stable value of rd_data_previous_r=0 then + // proceed to 0->1 edge detection. + // Case2: stable value of rd_data_previous_r=1 then + // decrement fine taps to '0' and proceed to 0->1 + // edge detection. Need to decrement in this case to + // make sure a valid 0->1 transition was not left + // undetected. + WL_INIT_FINE_INC_WAIT: begin + if (wl_sm_start) begin + if (stable_cnt < 'd14) + wl_state_r <= #TCQ WL_INIT_FINE_INC; + else if (~rd_data_previous_r[dqs_count_r]) begin + wl_state_r <= #TCQ WL_WAIT; + inhibit_edge_detect_r <= #TCQ 1'b0; + end else begin + wl_state_r <= #TCQ WL_INIT_FINE_DEC; + fine_dec_cnt <= #TCQ wl_tap_count_r; + end + end + end + + // Case2: stable value of rd_data_previous_r=1 then + // decrement fine taps to '0' and proceed to 0->1 + // edge detection. Need to decrement in this case to + // make sure a valid 0->1 transition was not left + // undetected. + WL_INIT_FINE_DEC: begin + wl_tap_count_r <= #TCQ 'd0; + wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT1; + if (fine_dec_cnt > 6'd0) + fine_dec_cnt <= #TCQ fine_dec_cnt - 1; + else + fine_dec_cnt <= #TCQ fine_dec_cnt; + end + + WL_INIT_FINE_DEC_WAIT1: begin + if (incdec_wait_cnt == 'd8) + wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT; + end + + WL_INIT_FINE_DEC_WAIT: begin + if (fine_dec_cnt > 6'd0) begin + wl_state_r <= #TCQ WL_INIT_FINE_DEC; + inhibit_edge_detect_r <= #TCQ 1'b1; + end else begin + wl_state_r <= #TCQ WL_WAIT; + inhibit_edge_detect_r <= #TCQ 1'b0; + end + end + + // Inc DQS Phaser_Out Stage2 Fine Delay line + WL_FINE_INC: begin + wl_edge_detect_valid_r <= #TCQ 1'b0; + if (SIM_CAL_OPTION == "FAST_CAL") begin + wl_state_r <= #TCQ WL_FINE_INC_WAIT; + if (fast_cal_fine_cnt > 'd0) + fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt - 1; + else + fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt; + end else if (wr_level_done_r5) begin + wl_tap_count_r <= #TCQ 'd0; + wl_state_r <= #TCQ WL_FINE_INC_WAIT; + if (|fine_inc[dqs_count_w]) + fine_inc[dqs_count_w] <= #TCQ fine_inc[dqs_count_w] - 1; + end else begin + wl_state_r <= #TCQ WL_WAIT; + wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1; + end + end + + WL_FINE_INC_WAIT: begin + if (SIM_CAL_OPTION == "FAST_CAL") begin + if (fast_cal_fine_cnt > 'd0) + wl_state_r <= #TCQ WL_FINE_INC; + else if (fast_cal_coarse_cnt > 'd0) + wl_state_r <= #TCQ WL_CORSE_INC; + else + wl_state_r <= #TCQ WL_DQS_CNT; + end else if (|fine_inc[dqs_count_w]) + wl_state_r <= #TCQ WL_FINE_INC; + else if (dqs_count_r == (DQS_WIDTH-1)) + wl_state_r <= #TCQ WL_IDLE; + else begin + wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; + dqs_count_r <= #TCQ dqs_count_r + 1; + end + end + + WL_FINE_DEC: begin + wl_edge_detect_valid_r <= #TCQ 1'b0; + wl_tap_count_r <= #TCQ 'd0; + wl_state_r <= #TCQ WL_FINE_DEC_WAIT1; + if (fine_dec_cnt > 6'd0) + fine_dec_cnt <= #TCQ fine_dec_cnt - 1; + else + fine_dec_cnt <= #TCQ fine_dec_cnt; + end + + WL_FINE_DEC_WAIT1: begin + if (incdec_wait_cnt == 'd8) + wl_state_r <= #TCQ WL_FINE_DEC_WAIT; + end + + WL_FINE_DEC_WAIT: begin + if (fine_dec_cnt > 6'd0) + wl_state_r <= #TCQ WL_FINE_DEC; + //else if (zero_tran_r) + // wl_state_r <= #TCQ WL_DQS_CNT; + else if (dual_rnk_dec) begin + if (|corse_dec[dqs_count_r]) + wl_state_r <= #TCQ WL_CORSE_DEC; + else + wl_state_r <= #TCQ WL_2RANK_DQS_CNT; + end else if (wrlvl_byte_redo) begin + if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7) + wl_state_r <= #TCQ WL_CORSE_INC; + else begin + wl_state_r <= #TCQ WL_IDLE; + wrlvl_err <= #TCQ 1'b1; + end + end else + wl_state_r <= #TCQ WL_CORSE_INC; + end + + WL_CORSE_DEC: begin + wl_state_r <= #TCQ WL_CORSE_DEC_WAIT; + dual_rnk_dec <= #TCQ 1'b0; + if (|corse_dec[dqs_count_r]) + corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r] - 1; + else + corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r]; + end + + WL_CORSE_DEC_WAIT: begin + if (wl_sm_start) begin + //if (|corse_dec[dqs_count_r]) + // wl_state_r <= #TCQ WL_CORSE_DEC; + if (|corse_dec[dqs_count_r]) + wl_state_r <= #TCQ WL_CORSE_DEC_WAIT1; + else + wl_state_r <= #TCQ WL_2RANK_DQS_CNT; + end + end + + WL_CORSE_DEC_WAIT1: begin + if (wl_sm_start) + wl_state_r <= #TCQ WL_CORSE_DEC; + end + + WL_CORSE_INC: begin + wl_state_r <= #TCQ WL_CORSE_INC_WAIT_TMP; + if (SIM_CAL_OPTION == "FAST_CAL") begin + if (fast_cal_coarse_cnt > 'd0) + fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt - 1; + else + fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt; + end else if (wrlvl_byte_redo) begin + corse_cnt[dqs_count_w] <= #TCQ corse_cnt[dqs_count_w] + 1; + if (|wrlvl_redo_corse_inc) + wrlvl_redo_corse_inc <= #TCQ wrlvl_redo_corse_inc - 1; + end else if (~wr_level_done_r5) + corse_cnt[dqs_count_r] <= #TCQ corse_cnt[dqs_count_r] + 1; + else if (|corse_inc[dqs_count_w]) + corse_inc[dqs_count_w] <= #TCQ corse_inc[dqs_count_w] - 1; + end + + WL_CORSE_INC_WAIT_TMP: begin + if (incdec_wait_cnt == 'd8) + wl_state_r <= #TCQ WL_CORSE_INC_WAIT; + end + + WL_CORSE_INC_WAIT: begin + if (SIM_CAL_OPTION == "FAST_CAL") begin + if (fast_cal_coarse_cnt > 'd0) + wl_state_r <= #TCQ WL_CORSE_INC; + else + wl_state_r <= #TCQ WL_DQS_CNT; + end else if (wrlvl_byte_redo) begin + if (|wrlvl_redo_corse_inc) + wl_state_r <= #TCQ WL_CORSE_INC; + else begin + wl_state_r <= #TCQ WL_INIT_FINE_INC; + inhibit_edge_detect_r <= #TCQ 1'b1; + end + end else if (~wr_level_done_r5 && wl_sm_start) + wl_state_r <= #TCQ WL_CORSE_INC_WAIT1; + else if (wr_level_done_r5) begin + if (|corse_inc[dqs_count_r]) + wl_state_r <= #TCQ WL_CORSE_INC; + else if (|fine_inc[dqs_count_w]) + wl_state_r <= #TCQ WL_FINE_INC; + else if (dqs_count_r == (DQS_WIDTH-1)) + wl_state_r <= #TCQ WL_IDLE; + else begin + wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; + dqs_count_r <= #TCQ dqs_count_r + 1; + end + end + end + + WL_CORSE_INC_WAIT1: begin + if (wl_sm_start) + wl_state_r <= #TCQ WL_CORSE_INC_WAIT2; + end + + WL_CORSE_INC_WAIT2: begin + if (wl_sm_start) + wl_state_r <= #TCQ WL_WAIT; + end + + WL_WAIT: begin + if (wl_sm_start) + wl_state_r <= #TCQ WL_EDGE_CHECK; + end + + WL_EDGE_CHECK: begin // Look for the edge + if (wl_edge_detect_valid_r == 1'b0) begin + wl_state_r <= #TCQ WL_WAIT; + wl_edge_detect_valid_r <= #TCQ 1'b1; + end + // 0->1 transition detected with DQS + else if(rd_data_edge_detect_r[dqs_count_r] && + wl_edge_detect_valid_r) + begin + wl_tap_count_r <= #TCQ wl_tap_count_r; + if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || + ~oclkdelay_calib_done) + wl_state_r <= #TCQ WL_DQS_CNT; + else + wl_state_r <= #TCQ WL_2RANK_TAP_DEC; + end + // For initial writes check only upto 56 taps. Reserving the + // remaining taps for OCLK calibration. + else if((~wrlvl_tap_done_r) && (wl_tap_count_r > 6'd55)) begin + if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin + wl_state_r <= #TCQ WL_FINE_DEC; + fine_dec_cnt <= #TCQ wl_tap_count_r; + end else begin + wrlvl_err <= #TCQ 1'b1; + wl_state_r <= #TCQ WL_IDLE; + end + end else begin + if (wl_tap_count_r < 6'd56) //for reuse wrlvl for complex ocal + wl_state_r <= #TCQ WL_FINE_INC; + else if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin + wl_state_r <= #TCQ WL_FINE_DEC; + fine_dec_cnt <= #TCQ wl_tap_count_r; + end else begin + wrlvl_err <= #TCQ 1'b1; + wl_state_r <= #TCQ WL_IDLE; + end + end + end + + WL_2RANK_TAP_DEC: begin + wl_state_r <= #TCQ WL_FINE_DEC; + fine_dec_cnt <= #TCQ wl_tap_count_r; + for (m = 0; m < DQS_WIDTH; m = m + 1) + corse_dec[m] <= #TCQ corse_cnt[m]; + wl_edge_detect_valid_r <= #TCQ 1'b0; + dual_rnk_dec <= #TCQ 1'b1; + end + + WL_DQS_CNT: begin + if ((SIM_CAL_OPTION == "FAST_CAL") || + (dqs_count_r == (DQS_WIDTH-1)) || + wrlvl_byte_redo) begin + dqs_count_r <= #TCQ dqs_count_r; + dq_cnt_inc <= #TCQ 1'b0; + end else begin + dqs_count_r <= #TCQ dqs_count_r + 1'b1; + dq_cnt_inc <= #TCQ 1'b1; + end + wl_state_r <= #TCQ WL_DQS_CHECK; + wl_edge_detect_valid_r <= #TCQ 1'b0; + end + + WL_2RANK_DQS_CNT: begin + if ((SIM_CAL_OPTION == "FAST_CAL") || + (dqs_count_r == (DQS_WIDTH-1))) begin + dqs_count_r <= #TCQ dqs_count_r; + dq_cnt_inc <= #TCQ 1'b0; + end else begin + dqs_count_r <= #TCQ dqs_count_r + 1'b1; + dq_cnt_inc <= #TCQ 1'b1; + end + wl_state_r <= #TCQ WL_DQS_CHECK; + wl_edge_detect_valid_r <= #TCQ 1'b0; + dual_rnk_dec <= #TCQ 1'b0; + end + + WL_DQS_CHECK: begin // check if all DQS have been calibrated + wl_tap_count_r <= #TCQ 'd0; + if (dq_cnt_inc == 1'b0)begin + wrlvl_rank_done_r <= #TCQ 1'd1; + for (t = 0; t < DQS_WIDTH; t = t + 1) + corse_cnt[t] <= #TCQ 3'b0; + if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || ~oclkdelay_calib_done) begin + wl_state_r <= #TCQ WL_IDLE; + if (wrlvl_byte_redo) + dqs_count_r <= #TCQ dqs_count_r; + else + dqs_count_r <= #TCQ 'd0; + end else if (rank_cnt_r == RANKS-1) begin + dqs_count_r <= #TCQ dqs_count_r; + if (RANKS > 1) + wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; + else + wl_state_r <= #TCQ WL_IDLE; + end else begin + wl_state_r <= #TCQ WL_INIT; + dqs_count_r <= #TCQ 'd0; + end + if ((SIM_CAL_OPTION == "FAST_CAL") || + (rank_cnt_r == RANKS-1)) begin + wr_level_done_r <= #TCQ 1'd1; + rank_cnt_r <= #TCQ 2'b00; + end else begin + wr_level_done_r <= #TCQ 1'd0; + rank_cnt_r <= #TCQ rank_cnt_r + 1'b1; + end + end else + wl_state_r <= #TCQ WL_INIT; + end + + WL_2RANK_FINAL_TAP: begin + if (wr_level_done_r4 && ~wr_level_done_r5) begin + for(u = 0; u < DQS_WIDTH; u = u + 1) begin + corse_inc[u] <= #TCQ final_coarse_tap[u]; + fine_inc[u] <= #TCQ final_val[u]; + end + dqs_count_r <= #TCQ 'd0; + end else if (wr_level_done_r5) begin + if (|corse_inc[dqs_count_r]) + wl_state_r <= #TCQ WL_CORSE_INC; + else if (|fine_inc[dqs_count_w]) + wl_state_r <= #TCQ WL_FINE_INC; + end + end + endcase + end + end // always @ (posedge clk) + +endmodule + + + + + + + diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v new file mode 100644 index 0000000..5c2a599 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v @@ -0,0 +1,246 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_ck_addr_cmd_delay.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Module to decrement initial PO delay to 0 and add 1/4 tck for tdqss +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_phy_wrlvl_off_delay # + ( + parameter TCQ = 100, + parameter tCK = 3636, + parameter nCK_PER_CLK = 2, + parameter CLK_PERIOD = 4, + parameter PO_INITIAL_DLY= 46, + parameter DQS_CNT_WIDTH = 3, + parameter DQS_WIDTH = 8, + parameter N_CTL_LANES = 3 + ) + ( + input clk, + input rst, + input pi_fine_dly_dec_done, + input cmd_delay_start, + // Control lane being shifted using Phaser_Out fine delay taps + output reg [DQS_CNT_WIDTH:0] ctl_lane_cnt, + // Inc/dec Phaser_Out fine delay line + output reg po_s2_incdec_f, + output reg po_en_s2_f, + // Inc/dec Phaser_Out coarse delay line + output reg po_s2_incdec_c, + output reg po_en_s2_c, + // Completed adjusting delays for dq, dqs for tdqss + output po_ck_addr_cmd_delay_done, + // completed decrementing initialPO delays + output po_dec_done, + output phy_ctl_rdy_dly + ); + + + localparam TAP_LIMIT = 63; + + + +// PO fine delay tap resolution change by frequency. tCK > 2500, need +// twice the amount of taps +// localparam D_DLY_F = (tCK > 2500 ) ? D_DLY * 2 : D_DLY; + + // coarse delay tap is added DQ/DQS to meet the TDQSS specification. + localparam TDQSS_DLY = (tCK > 2500 )? 2: 1; + + reg delay_done; + reg delay_done_r1; + reg delay_done_r2; + reg delay_done_r3; + reg delay_done_r4; + reg [5:0] po_delay_cnt_r; + reg po_cnt_inc; + reg cmd_delay_start_r1; + reg cmd_delay_start_r2; + reg cmd_delay_start_r3; + reg cmd_delay_start_r4; + reg cmd_delay_start_r5; + reg cmd_delay_start_r6; + reg po_delay_done; + reg po_delay_done_r1; + reg po_delay_done_r2; + reg po_delay_done_r3; + reg po_delay_done_r4; + reg pi_fine_dly_dec_done_r; + reg po_en_stg2_c; + reg po_en_stg2_f; + reg po_stg2_incdec_c; + reg po_stg2_f_incdec; + reg [DQS_CNT_WIDTH:0] lane_cnt_dqs_c_r; + reg [DQS_CNT_WIDTH:0] lane_cnt_po_r; + reg [5:0] delay_cnt_r; + + always @(posedge clk) begin + cmd_delay_start_r1 <= #TCQ cmd_delay_start; + cmd_delay_start_r2 <= #TCQ cmd_delay_start_r1; + cmd_delay_start_r3 <= #TCQ cmd_delay_start_r2; + cmd_delay_start_r4 <= #TCQ cmd_delay_start_r3; + cmd_delay_start_r5 <= #TCQ cmd_delay_start_r4; + cmd_delay_start_r6 <= #TCQ cmd_delay_start_r5; + pi_fine_dly_dec_done_r <= #TCQ pi_fine_dly_dec_done; + end + + assign phy_ctl_rdy_dly = cmd_delay_start_r6; + + + // logic for decrementing initial fine delay taps for all PO + // Decrement done for add, ctrl and data phaser outs + + assign po_dec_done = (PO_INITIAL_DLY == 0) ? 1 : po_delay_done_r4; + + + always @(posedge clk) + if (rst || ~cmd_delay_start_r6 || po_delay_done) begin + po_stg2_f_incdec <= #TCQ 1'b0; + po_en_stg2_f <= #TCQ 1'b0; + end else if (po_delay_cnt_r > 6'd0) begin + po_en_stg2_f <= #TCQ ~po_en_stg2_f; + end + + always @(posedge clk) + if (rst || ~cmd_delay_start_r6 || (po_delay_cnt_r == 6'd0)) + // set all the PO delays to 31. Decrement from 46 to 31. + // Requirement comes from dqs_found logic + po_delay_cnt_r <= #TCQ (PO_INITIAL_DLY - 31); + else if ( po_en_stg2_f && (po_delay_cnt_r > 6'd0)) + po_delay_cnt_r <= #TCQ po_delay_cnt_r - 1; + + always @(posedge clk) + if (rst) + lane_cnt_po_r <= #TCQ 'd0; + else if ( po_en_stg2_f && (po_delay_cnt_r == 6'd1)) + lane_cnt_po_r <= #TCQ lane_cnt_po_r + 1; + + always @(posedge clk) + if (rst || ~cmd_delay_start_r6 ) + po_delay_done <= #TCQ 1'b0; + else if ((po_delay_cnt_r == 6'd1) && (lane_cnt_po_r ==1'b0)) + po_delay_done <= #TCQ 1'b1; + + always @(posedge clk) begin + po_delay_done_r1 <= #TCQ po_delay_done; + po_delay_done_r2 <= #TCQ po_delay_done_r1; + po_delay_done_r3 <= #TCQ po_delay_done_r2; + po_delay_done_r4 <= #TCQ po_delay_done_r3; + end + + // logic to select between all PO delays and data path delay. + always @(posedge clk) begin + po_s2_incdec_f <= #TCQ po_stg2_f_incdec; + po_en_s2_f <= #TCQ po_en_stg2_f; + end + +// Logic to add 1/4 taps amount of delay to data path for tdqss. +// After all the initial PO delays are decremented the 1/4 delay will +// be added. Coarse delay taps will be added here . +// Delay added only to data path + + assign po_ck_addr_cmd_delay_done = (TDQSS_DLY == 0) ? pi_fine_dly_dec_done_r + : delay_done_r4; + + always @(posedge clk) + if (rst || ~pi_fine_dly_dec_done_r || delay_done) begin + po_stg2_incdec_c <= #TCQ 1'b1; + po_en_stg2_c <= #TCQ 1'b0; + end else if (delay_cnt_r > 6'd0) begin + po_en_stg2_c <= #TCQ ~po_en_stg2_c; + end + + always @(posedge clk) + if (rst || ~pi_fine_dly_dec_done_r || (delay_cnt_r == 6'd0)) + delay_cnt_r <= #TCQ TDQSS_DLY; + else if ( po_en_stg2_c && (delay_cnt_r > 6'd0)) + delay_cnt_r <= #TCQ delay_cnt_r - 1; + + always @(posedge clk) + if (rst) + lane_cnt_dqs_c_r <= #TCQ 'd0; + else if ( po_en_stg2_c && (delay_cnt_r == 6'd1)) + lane_cnt_dqs_c_r <= #TCQ lane_cnt_dqs_c_r + 1; + + always @(posedge clk) + if (rst || ~pi_fine_dly_dec_done_r) + delay_done <= #TCQ 1'b0; + else if ((delay_cnt_r == 6'd1) && (lane_cnt_dqs_c_r == 1'b0)) + delay_done <= #TCQ 1'b1; + + + always @(posedge clk) begin + delay_done_r1 <= #TCQ delay_done; + delay_done_r2 <= #TCQ delay_done_r1; + delay_done_r3 <= #TCQ delay_done_r2; + delay_done_r4 <= #TCQ delay_done_r3; + end + + always @(posedge clk) begin + po_s2_incdec_c <= #TCQ po_stg2_incdec_c; + po_en_s2_c <= #TCQ po_en_stg2_c; + ctl_lane_cnt <= #TCQ lane_cnt_dqs_c_r; + end + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_prbs_gen.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_prbs_gen.v new file mode 100644 index 0000000..9222b07 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_prbs_gen.v @@ -0,0 +1,580 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_prbs_gen.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:10 $ +// \ \ / \ Date Created: 05/12/10 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: ddr_prbs_gen +// Overview: +// Implements a "pseudo-PRBS" generator. Basically this is a standard +// PRBS generator (using an linear feedback shift register) along with +// logic to force the repetition of the sequence after 2^PRBS_WIDTH +// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design +// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains +// are supported in this code +// Parameter Requirements: +// 1. PRBS_WIDTH = 8 or 10 +// 2. PRBS_WIDTH >= 2*nCK_PER_CLK +// Output notes: +// The output of this module consists of 2*nCK_PER_CLK bits, these contain +// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note +// that prbs_o[0] contains the bit value for the "earliest" bit time. +// +//Reference: +//Revision History: +// +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_prbs_gen.v,v 1.1 2011/06/02 08:35:10 mishra Exp $ +**$Date: 2011/06/02 08:35:10 $ +**$Author: mishra $ +**$Revision: 1.1 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_prbs_gen.v,v $ +******************************************************************************/ + + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_prbs_gen # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter PRBS_WIDTH = 64, // LFSR shift register length + parameter DQS_CNT_WIDTH = 5, + parameter DQ_WIDTH = 72, + parameter VCCO_PAT_EN = 1, + parameter VCCAUX_PAT_EN = 1, + parameter ISI_PAT_EN = 1, + parameter FIXED_VICTIM = "TRUE" + ) + ( + input clk_i, // input clock + input clk_en_i, // clock enable + input rst_i, // synchronous reset + input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed + input phy_if_empty, // IN_FIFO empty flag + input prbs_rdlvl_start, // PRBS read lveling start + input prbs_rdlvl_done, + input complex_wr_done, + input [2:0] victim_sel, + input [DQS_CNT_WIDTH:0] byte_cnt, + //output [PRBS_WIDTH-1:0] prbs_o // generated pseudo random data + output [8*DQ_WIDTH-1:0] prbs_o, + output [9:0] dbg_prbs_gen, + input reset_rd_addr, + output prbs_ignore_first_byte, + output prbs_ignore_last_bytes + ); + + //*************************************************************************** + + function integer clogb2 (input integer size); + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction + + // Number of internal clock cycles before the PRBS sequence will repeat + localparam PRBS_SEQ_LEN_CYCLES = 128; + localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES); + + reg phy_if_empty_r; + reg reseed_prbs_r; + reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r; + reg [PRBS_WIDTH - 1 :0] prbs; + reg [PRBS_WIDTH :1] lfsr_q; + + + //*************************************************************************** + always @(posedge clk_i) begin + phy_if_empty_r <= #TCQ phy_if_empty; + end + + //*************************************************************************** + // Generate PRBS reset signal to ensure that PRBS sequence repeats after + // every 2**PRBS_WIDTH samples. Basically what happens is that we let the + // LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1 + // samples have past. Once that extra cycle is finished, we reseed the LFSR + always @(posedge clk_i) + begin + if (rst_i || ~clk_en_i) begin + sample_cnt_r <= #TCQ 'b0; + reseed_prbs_r <= #TCQ 1'b0; + end else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin + // The rollver count should always be [(power of 2) - 1] + sample_cnt_r <= #TCQ sample_cnt_r + 1; + // Assert PRBS reset signal so that it is simultaneously with the + // last sample of the sequence + if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2) + reseed_prbs_r <= #TCQ 1'b1; + else + reseed_prbs_r <= #TCQ 1'b0; + end + end + + always @ (posedge clk_i) + begin +//reset it to a known good state to prevent it locks up + if ((reseed_prbs_r && clk_en_i) || rst_i || ~clk_en_i) begin + lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5; + lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4]; + end + else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin + lfsr_q[PRBS_WIDTH:31] <= #TCQ lfsr_q[PRBS_WIDTH-1:30]; + lfsr_q[30] <= #TCQ lfsr_q[16] ^ lfsr_q[13] ^ lfsr_q[5] ^ lfsr_q[1]; + lfsr_q[29:9] <= #TCQ lfsr_q[28:8]; + lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; + lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; + lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; + lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; + lfsr_q[2] <= #TCQ lfsr_q[1] ; + lfsr_q[1] <= #TCQ lfsr_q[32]; + end + end + + always @ (lfsr_q[PRBS_WIDTH:1]) begin + prbs = lfsr_q[PRBS_WIDTH:1]; + end + +//****************************************************************************** +// Complex pattern BRAM +//****************************************************************************** + +localparam BRAM_ADDR_WIDTH = 8; +localparam BRAM_DATA_WIDTH = 18; +localparam BRAM_DEPTH = 256; + +integer i,j; +(* RAM_STYLE = "distributed" *) reg [BRAM_ADDR_WIDTH - 1:0] rd_addr; +//reg [BRAM_DATA_WIDTH - 1:0] mem[0:BRAM_DEPTH - 1]; +(* RAM_STYLE = "distributed" *) reg [BRAM_DATA_WIDTH - 1:0] mem_out; +reg [BRAM_DATA_WIDTH - 3:0] dout_o; +reg [DQ_WIDTH-1:0] sel; +reg [DQ_WIDTH-1:0] dout_rise0; +reg [DQ_WIDTH-1:0] dout_fall0; +reg [DQ_WIDTH-1:0] dout_rise1; +reg [DQ_WIDTH-1:0] dout_fall1; +reg [DQ_WIDTH-1:0] dout_rise2; +reg [DQ_WIDTH-1:0] dout_fall2; +reg [DQ_WIDTH-1:0] dout_rise3; +reg [DQ_WIDTH-1:0] dout_fall3; + +// VCCO noise injection pattern with matching victim (reads with gaps) +// content format +// {aggressor pattern, victim pattern} +always @ (rd_addr) begin + case (rd_addr) + 8'd0 : mem_out = {2'b11, 8'b10101010,8'b10101010}; //1 read + 8'd1 : mem_out = {2'b01, 8'b11001100,8'b11001100}; //2 reads + 8'd2 : mem_out = {2'b10, 8'b11001100,8'b11001100}; //2 reads + 8'd3 : mem_out = {2'b01, 8'b11100011,8'b11100011}; //3 reads + 8'd4 : mem_out = {2'b00, 8'b10001110,8'b10001110}; //3 reads + 8'd5 : mem_out = {2'b10, 8'b00111000,8'b00111000}; //3 reads + 8'd6 : mem_out = {2'b01, 8'b11110000,8'b11110000}; //4 reads + 8'd7 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads + 8'd8 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads + 8'd9 : mem_out = {2'b10, 8'b11110000,8'b11110000}; //4 reads + 8'd10 : mem_out = {2'b01, 8'b11111000,8'b11111000}; //5 reads + 8'd11 : mem_out = {2'b00, 8'b00111110,8'b00111110}; //5 reads + 8'd12 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //5 reads + 8'd13 : mem_out = {2'b00, 8'b10000011,8'b10000011}; //5 reads + 8'd14 : mem_out = {2'b10, 8'b11100000,8'b11100000}; //5 reads + 8'd15 : mem_out = {2'b01, 8'b11111100,8'b11111100}; //6 reads + 8'd16 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads + 8'd17 : mem_out = {2'b00, 8'b11000000,8'b11000000}; //6 reads + 8'd18 : mem_out = {2'b00, 8'b11111100,8'b11111100}; //6 reads + 8'd19 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads + 8'd20 : mem_out = {2'b10, 8'b11000000,8'b11000000}; //6 reads + // VCCO noise injection pattern with non-matching victim (reads with gaps) + // content format + // {aggressor pattern, victim pattern} + 8'd21 : mem_out = {2'b11, 8'b10101010,8'b01010101}; //1 read + 8'd22 : mem_out = {2'b01, 8'b11001100,8'b00110011}; //2 reads + 8'd23 : mem_out = {2'b10, 8'b11001100,8'b00110011}; //2 reads + 8'd24 : mem_out = {2'b01, 8'b11100011,8'b00011100}; //3 reads + 8'd25 : mem_out = {2'b00, 8'b10001110,8'b01110001}; //3 reads + 8'd26 : mem_out = {2'b10, 8'b00111000,8'b11000111}; //3 reads + 8'd27 : mem_out = {2'b01, 8'b11110000,8'b00001111}; //4 reads + 8'd28 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads + 8'd29 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads + 8'd30 : mem_out = {2'b10, 8'b11110000,8'b00001111}; //4 reads + 8'd31 : mem_out = {2'b01, 8'b11111000,8'b00000111}; //5 reads + 8'd32 : mem_out = {2'b00, 8'b00111110,8'b11000001}; //5 reads + 8'd33 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //5 reads + 8'd34 : mem_out = {2'b00, 8'b10000011,8'b01111100}; //5 reads + 8'd35 : mem_out = {2'b10, 8'b11100000,8'b00011111}; //5 reads + 8'd36 : mem_out = {2'b01, 8'b11111100,8'b00000011}; //6 reads + 8'd37 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads + 8'd38 : mem_out = {2'b00, 8'b11000000,8'b00111111}; //6 reads + 8'd39 : mem_out = {2'b00, 8'b11111100,8'b00000011}; //6 reads + 8'd40 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads + 8'd41 : mem_out = {2'b10, 8'b11000000,8'b00111111}; //6 reads + // VCCAUX noise injection pattern with ISI pattern on victim (reads with gaps) + // content format + // {aggressor pattern, victim pattern} + 8'd42 : mem_out = {2'b01, 8'b10110100,8'b01010111}; //3 reads + 8'd43 : mem_out = {2'b00, 8'b10110100,8'b01101111}; //3 reads + 8'd44 : mem_out = {2'b10, 8'b10110100,8'b11000000}; //3 reads + 8'd45 : mem_out = {2'b01, 8'b10100010,8'b10000100}; //4 reads + 8'd46 : mem_out = {2'b00, 8'b10001010,8'b00110001}; //4 reads + 8'd47 : mem_out = {2'b00, 8'b00101000,8'b01000111}; //4 reads + 8'd48 : mem_out = {2'b10, 8'b10100010,8'b00100101}; //4 reads + 8'd49 : mem_out = {2'b01, 8'b10101111,8'b10011010}; //5 reads + 8'd50 : mem_out = {2'b00, 8'b01010000,8'b01111010}; //5 reads + 8'd51 : mem_out = {2'b00, 8'b10101111,8'b10010101}; //5 reads + 8'd52 : mem_out = {2'b00, 8'b01010000,8'b11011011}; //5 reads + 8'd53 : mem_out = {2'b10, 8'b10101111,8'b11110000}; //5 reads + 8'd54 : mem_out = {2'b01, 8'b10101000,8'b00100001}; //7 reads + 8'd55 : mem_out = {2'b00, 8'b00101010,8'b10001010}; //7 reads + 8'd56 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //7 reads + 8'd57 : mem_out = {2'b00, 8'b10000010,8'b10011010}; //7 reads + 8'd58 : mem_out = {2'b00, 8'b10100000,8'b01111010}; //7 reads + 8'd59 : mem_out = {2'b00, 8'b10101000,8'b10111111}; //7 reads + 8'd60 : mem_out = {2'b10, 8'b00101010,8'b01010111}; //7 reads + 8'd61 : mem_out = {2'b01, 8'b10101011,8'b01101111}; //8 reads + 8'd62 : mem_out = {2'b00, 8'b11110101,8'b11000000}; //8 reads + 8'd63 : mem_out = {2'b00, 8'b01000000,8'b10000100}; //8 reads + 8'd64 : mem_out = {2'b00, 8'b10101011,8'b00110001}; //8 reads + 8'd65 : mem_out = {2'b00, 8'b11110101,8'b01000111}; //8 reads + 8'd66 : mem_out = {2'b00, 8'b01000000,8'b00100101}; //8 reads + 8'd67 : mem_out = {2'b00, 8'b10101011,8'b10011010}; //8 reads + 8'd68 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //8 reads + 8'd69 : mem_out = {2'b01, 8'b10101010,8'b10010101}; //9 reads + 8'd70 : mem_out = {2'b00, 8'b00000010,8'b11011011}; //9 reads + 8'd71 : mem_out = {2'b00, 8'b10101000,8'b11110000}; //9 reads + 8'd72 : mem_out = {2'b00, 8'b00001010,8'b00100001}; //9 reads + 8'd73 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //9 reads + 8'd74 : mem_out = {2'b00, 8'b00101010,8'b00100101}; //9 reads + 8'd75 : mem_out = {2'b00, 8'b10000000,8'b10011010}; //9 reads + 8'd76 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //9 reads + 8'd77 : mem_out = {2'b10, 8'b00000010,8'b10111111}; //9 reads + 8'd78 : mem_out = {2'b01, 8'b10101010,8'b01010111}; //10 reads + 8'd79 : mem_out = {2'b00, 8'b11111111,8'b01101111}; //10 reads + 8'd80 : mem_out = {2'b00, 8'b01010101,8'b11000000}; //10 reads + 8'd81 : mem_out = {2'b00, 8'b00000000,8'b10000100}; //10 reads + 8'd82 : mem_out = {2'b00, 8'b10101010,8'b00110001}; //10 reads + 8'd83 : mem_out = {2'b00, 8'b11111111,8'b01000111}; //10 reads + 8'd84 : mem_out = {2'b00, 8'b01010101,8'b00100101}; //10 reads + 8'd85 : mem_out = {2'b00, 8'b00000000,8'b10011010}; //10 reads + 8'd86 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //10 reads + 8'd87 : mem_out = {2'b10, 8'b11111111,8'b10010101}; //10 reads + 8'd88 : mem_out = {2'b01, 8'b10101010,8'b11011011}; //12 reads + 8'd89 : mem_out = {2'b00, 8'b10000000,8'b11110000}; //12 reads + 8'd90 : mem_out = {2'b00, 8'b00101010,8'b00100001}; //12 reads + 8'd91 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //12 reads + 8'd92 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //12 reads + 8'd93 : mem_out = {2'b00, 8'b10101000,8'b10011010}; //12 reads + 8'd94 : mem_out = {2'b00, 8'b00000010,8'b01111010}; //12 reads + 8'd95 : mem_out = {2'b00, 8'b10101010,8'b10111111}; //12 reads + 8'd96 : mem_out = {2'b00, 8'b00000000,8'b01010111}; //12 reads + 8'd97 : mem_out = {2'b00, 8'b10101010,8'b01101111}; //12 reads + 8'd98 : mem_out = {2'b00, 8'b10000000,8'b11000000}; //12 reads + 8'd99 : mem_out = {2'b10, 8'b00101010,8'b10000100}; //12 reads + 8'd100 : mem_out = {2'b01, 8'b10101010,8'b00110001}; //13 reads + 8'd101 : mem_out = {2'b00, 8'b10111111,8'b01000111}; //13 reads + 8'd102 : mem_out = {2'b00, 8'b11110101,8'b00100101}; //13 reads + 8'd103 : mem_out = {2'b00, 8'b01010100,8'b10011010}; //13 reads + 8'd104 : mem_out = {2'b00, 8'b00000000,8'b01111010}; //13 reads + 8'd105 : mem_out = {2'b00, 8'b10101010,8'b10010101}; //13 reads + 8'd106 : mem_out = {2'b00, 8'b10111111,8'b11011011}; //13 reads + 8'd107 : mem_out = {2'b00, 8'b11110101,8'b11110000}; //13 reads + 8'd108 : mem_out = {2'b00, 8'b01010100,8'b00100001}; //13 reads + 8'd109 : mem_out = {2'b00, 8'b00000000,8'b10001010}; //13 reads + 8'd110 : mem_out = {2'b00, 8'b10101010,8'b00100101}; //13 reads + 8'd111 : mem_out = {2'b00, 8'b10111111,8'b10011010}; //13 reads + 8'd112 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //13 reads + 8'd113 : mem_out = {2'b01, 8'b10101010,8'b10111111}; //14 reads + 8'd114 : mem_out = {2'b00, 8'b10100000,8'b01010111}; //14 reads + 8'd115 : mem_out = {2'b00, 8'b00000010,8'b01101111}; //14 reads + 8'd116 : mem_out = {2'b00, 8'b10101010,8'b11000000}; //14 reads + 8'd117 : mem_out = {2'b00, 8'b10000000,8'b10000100}; //14 reads + 8'd118 : mem_out = {2'b00, 8'b00001010,8'b00110001}; //14 reads + 8'd119 : mem_out = {2'b00, 8'b10101010,8'b01000111}; //14 reads + 8'd120 : mem_out = {2'b00, 8'b00000000,8'b00100101}; //14 reads + 8'd121 : mem_out = {2'b00, 8'b00101010,8'b10011010}; //14 reads + 8'd122 : mem_out = {2'b00, 8'b10101000,8'b01111010}; //14 reads + 8'd123 : mem_out = {2'b00, 8'b00000000,8'b10010101}; //14 reads + 8'd124 : mem_out = {2'b00, 8'b10101010,8'b11011011}; //14 reads + 8'd125 : mem_out = {2'b00, 8'b10100000,8'b11110000}; //14 reads + 8'd126 : mem_out = {2'b10, 8'b00000010,8'b00100001}; //14 reads + // ISI pattern (Back-to-back reads) + // content format + // {aggressor pattern, victim pattern} + 8'd127 : mem_out = {2'b01, 8'b01010111,8'b01010111}; + 8'd128 : mem_out = {2'b00, 8'b01101111,8'b01101111}; + 8'd129 : mem_out = {2'b00, 8'b11000000,8'b11000000}; + 8'd130 : mem_out = {2'b00, 8'b10000110,8'b10000100}; + 8'd131 : mem_out = {2'b00, 8'b00101000,8'b00110001}; + 8'd132 : mem_out = {2'b00, 8'b11100100,8'b01000111}; + 8'd133 : mem_out = {2'b00, 8'b10110011,8'b00100101}; + 8'd134 : mem_out = {2'b00, 8'b01001111,8'b10011011}; + 8'd135 : mem_out = {2'b00, 8'b10110101,8'b01010101}; + 8'd136 : mem_out = {2'b00, 8'b10110101,8'b01010101}; + 8'd137 : mem_out = {2'b00, 8'b10000111,8'b10011000}; + 8'd138 : mem_out = {2'b00, 8'b11100011,8'b00011100}; + 8'd139 : mem_out = {2'b00, 8'b00001010,8'b11110101}; + 8'd140 : mem_out = {2'b00, 8'b11010100,8'b00101011}; + 8'd141 : mem_out = {2'b00, 8'b01001000,8'b10110111}; + 8'd142 : mem_out = {2'b00, 8'b00011111,8'b11100000}; + 8'd143 : mem_out = {2'b00, 8'b10111100,8'b01000011}; + 8'd144 : mem_out = {2'b00, 8'b10001111,8'b00010100}; + 8'd145 : mem_out = {2'b00, 8'b10110100,8'b01001011}; + 8'd146 : mem_out = {2'b00, 8'b11001011,8'b00110100}; + 8'd147 : mem_out = {2'b00, 8'b00001010,8'b11110101}; + 8'd148 : mem_out = {2'b00, 8'b10000000,8'b00000000}; + //Additional for ISI + 8'd149 : mem_out = {2'b00, 8'b00000000,8'b00000000}; + 8'd150 : mem_out = {2'b00, 8'b01010101,8'b01010101}; + 8'd151 : mem_out = {2'b00, 8'b01010101,8'b01010101}; + 8'd152 : mem_out = {2'b00, 8'b00000000,8'b00000000}; + 8'd153 : mem_out = {2'b00, 8'b00000000,8'b00000000}; + 8'd154 : mem_out = {2'b00, 8'b01010101,8'b00101010}; + 8'd155 : mem_out = {2'b00, 8'b01010101,8'b10101010}; + 8'd156 : mem_out = {2'b10, 8'b00000000,8'b10000000}; + //Available + 8'd157 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd158 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd159 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd160 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd161 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd162 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd163 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd164 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd165 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd166 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd167 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd168 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd169 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd170 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd171 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd172 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd173 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd174 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd175 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd176 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd177 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd178 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd179 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd180 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd181 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd182 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd183 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd184 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd185 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd186 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd187 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd188 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd189 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd190 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd191 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd192 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd193 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd194 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd195 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd196 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd197 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd198 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd199 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd200 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd201 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd202 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd203 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd204 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd205 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd206 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd207 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd208 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd209 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd210 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd211 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd212 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd213 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd214 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd215 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd216 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd217 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd218 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd219 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd220 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd221 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd222 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd223 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd224 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd225 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd226 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd227 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd228 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd229 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd230 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd231 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd232 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd233 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd234 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd235 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd236 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd237 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd238 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd239 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd240 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd241 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd242 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd243 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd244 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd245 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd246 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd247 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd248 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd249 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd250 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd251 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd252 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd253 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd254 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd255 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + endcase +end + + + +always @ (posedge clk_i) begin + if (rst_i | reset_rd_addr) + rd_addr <= #TCQ 'b0; + //rd_addr for complex oclkdelay calib + else if (clk_en_i && prbs_rdlvl_done && (~phy_if_empty_r || ~complex_wr_done)) begin + if (rd_addr == 'd156) rd_addr <= #TCQ 'b0; + else rd_addr <= #TCQ rd_addr + 1; + end + //rd_addr for complex rdlvl + else if (clk_en_i && (~phy_if_empty_r || (~prbs_rdlvl_start && ~complex_wr_done))) begin + if (rd_addr == 'd148) rd_addr <= #TCQ 'b0; + else rd_addr <= #TCQ rd_addr+1; + end + +end + +// Each pattern can be disabled independently +// When disabled zeros are written to and read from the DRAM +always @ (posedge clk_i) begin + if ((rd_addr < 42) && VCCO_PAT_EN) + dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0]; + else if ((rd_addr < 127) && VCCAUX_PAT_EN) + dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0]; + else if (ISI_PAT_EN && (rd_addr > 126)) + dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0]; + else + dout_o <= #TCQ 'd0; +end + +reg prbs_ignore_first_byte_r; +always @(posedge clk_i) prbs_ignore_first_byte_r <= #TCQ mem_out[16]; +assign prbs_ignore_first_byte = prbs_ignore_first_byte_r; + +reg prbs_ignore_last_bytes_r; +always @(posedge clk_i) prbs_ignore_last_bytes_r <= #TCQ mem_out[17]; +assign prbs_ignore_last_bytes = prbs_ignore_last_bytes_r; + + + +generate + if (FIXED_VICTIM == "TRUE") begin: victim_sel_fixed + // Fixed victim bit 3 + always @(posedge clk_i) + sel <= #TCQ {DQ_WIDTH/8{8'h08}}; + end else begin: victim_sel_rotate + // One-hot victim select + always @(posedge clk_i) + if (rst_i) + sel <= #TCQ 'd0; + else begin + for (i = 0; i < DQ_WIDTH/8; i = i+1) begin + for (j=0; j <8 ; j = j+1) begin + if (j == victim_sel) + sel[i*8+j] <= #TCQ 1'b1; + else + sel[i*8+j] <= #TCQ 1'b0; + end + end + end + end +endgenerate + + + +// construct 8 X DATA_WIDTH output bus +always @(*) + for (i = 0; i < DQ_WIDTH; i = i+1) begin + dout_rise0[i] = (dout_o[7]&&sel[i] || dout_o[15]&&~sel[i]); + dout_fall0[i] = (dout_o[6]&&sel[i] || dout_o[14]&&~sel[i]); + dout_rise1[i] = (dout_o[5]&&sel[i] || dout_o[13]&&~sel[i]); + dout_fall1[i] = (dout_o[4]&&sel[i] || dout_o[12]&&~sel[i]); + dout_rise2[i] = (dout_o[3]&&sel[i] || dout_o[11]&&~sel[i]); + dout_fall2[i] = (dout_o[2]&&sel[i] || dout_o[10]&&~sel[i]); + dout_rise3[i] = (dout_o[1]&&sel[i] || dout_o[9]&&~sel[i]); + dout_fall3[i] = (dout_o[0]&&sel[i] || dout_o[8]&&~sel[i]); + end + + + assign prbs_o = {dout_fall3, dout_rise3, dout_fall2, dout_rise2, dout_fall1, dout_rise1, dout_fall0, dout_rise0}; + + assign dbg_prbs_gen[9] = phy_if_empty_r; + assign dbg_prbs_gen[8] = clk_en_i; + assign dbg_prbs_gen[7:0] = rd_addr[7:0]; + +endmodule + + diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_skip_calib_tap.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_skip_calib_tap.v new file mode 100644 index 0000000..cba1878 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_skip_calib_tap.v @@ -0,0 +1,837 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_skip_calib_tap.v +// /___/ /\ Date Last Modified: $Date: 2015/05/06 02:07:40 $ +// \ \ / \ Date Created: May 06 2015 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Phaser_Out, Phaser_In, and IDELAY tap adjustments to match +// calibration values when SKIP_CALIB=="TRUE" +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_0_ddr_skip_calib_tap # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter DQS_WIDTH = 8 // number of bytes + ) + ( + input clk, + input rst, + input phy_ctl_ready, + // Completed loading calib tap values into registers + input load_done, + // Tap adjustment status + input calib_tap_inc_start, + output calib_tap_inc_done, + // Calibration tap values + input [6*DQS_WIDTH-1:0] calib_po_stage2_tap_cnt, + input [6*DQS_WIDTH-1:0] calib_po_stage3_tap_cnt, + input [3*DQS_WIDTH-1:0] calib_po_coarse_tap_cnt, + input [6*DQS_WIDTH-1:0] calib_pi_stage2_tap_cnt, + input [5*DQS_WIDTH-1:0] calib_idelay_tap_cnt, + // Phaser_Out and Phaser_In tap count + input [8:0] po_counter_read_val, + input [5:0] pi_counter_read_val, + // Phaser_Out and Phaser_In tap inc/dec control signals + output [5:0] calib_tap_inc_byte_cnt, + output calib_po_f_en, + output calib_po_f_incdec, + output calib_po_sel_stg2stg3, + output calib_po_c_en, + output calib_po_c_inc, + output calib_pi_f_en, + output calib_pi_f_incdec, + output calib_idelay_ce, + output calib_idelay_inc, + output skip_cal_po_pi_dec_done, + output reg coarse_dec_err, + output [127:0] dbg_skip_cal + ); + + //*************************************************************************** + // Decrement initial Phaser_OUT fine delay value before proceeding with + // calibration + //*************************************************************************** + + + reg phy_ctl_ready_r1, phy_ctl_ready_r2, phy_ctl_ready_r3, phy_ctl_ready_r4, phy_ctl_ready_r5, phy_ctl_ready_r6; + reg po_cnt_dec; + reg [3:0] dec_wait_cnt; + reg [8:0] po_rdval_cnt; + reg po_dec_done; + reg dec_po_f_en_r; + reg dec_po_f_incdec_r; + reg dqs_po_dec_done_r1, dqs_po_dec_done_r2; + reg fine_dly_dec_done_r1, fine_dly_dec_done_r2, fine_dly_dec_done_r3; + reg [5:0] pi_rdval_cnt; + reg pi_cnt_dec; + reg dec_pi_f_en_r; + reg dec_pi_f_incdec_r; + + always @(posedge clk) begin + phy_ctl_ready_r1 <= #TCQ phy_ctl_ready; + phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1; + phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2; + phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3; + phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4; + phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5; + end + + always @(posedge clk) begin + if (rst || po_cnt_dec || pi_cnt_dec) + dec_wait_cnt <= #TCQ 'd8; + else if (phy_ctl_ready_r6 && (dec_wait_cnt > 'd0)) + dec_wait_cnt <= #TCQ dec_wait_cnt - 1; + end + + always @(posedge clk) begin + if (rst) begin + po_rdval_cnt <= #TCQ 'd0; + end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin + po_rdval_cnt <= #TCQ po_counter_read_val; + end else if (po_rdval_cnt > 'd0) begin + if (po_cnt_dec) + po_rdval_cnt <= #TCQ po_rdval_cnt - 1; + else + po_rdval_cnt <= #TCQ po_rdval_cnt; + end else if (po_rdval_cnt == 'd0) begin + po_rdval_cnt <= #TCQ po_rdval_cnt; + end + end + + always @(posedge clk) begin + if (rst || (po_rdval_cnt == 'd0)) + po_cnt_dec <= #TCQ 1'b0; + else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (dec_wait_cnt == 'd1)) + po_cnt_dec <= #TCQ 1'b1; + else + po_cnt_dec <= #TCQ 1'b0; + end + + // Inc/Dec Phaser_Out stage 2 fine delay line + always @(posedge clk) begin + if (rst) begin + dec_po_f_incdec_r <= #TCQ 1'b0; + dec_po_f_en_r <= #TCQ 1'b0; + end else if (po_cnt_dec) begin + dec_po_f_incdec_r <= #TCQ 1'b0; + dec_po_f_en_r <= #TCQ 1'b1; + end else begin + dec_po_f_incdec_r <= #TCQ 1'b0; + dec_po_f_en_r <= #TCQ 1'b0; + end + end + + always @(posedge clk) begin + if (rst) + po_dec_done <= #TCQ 1'b0; + else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) || + (phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin + po_dec_done <= #TCQ 1'b1; + end + end + + //*************************************************************************** + // Decrement initial Phaser_IN fine delay value before proceeding with + // calibration + //*************************************************************************** + + always @(posedge clk) begin + dqs_po_dec_done_r1 <= #TCQ po_dec_done; + dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1; + fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1; + fine_dly_dec_done_r3 <= #TCQ fine_dly_dec_done_r2; + end + + always @(posedge clk) begin + if (rst) begin + pi_rdval_cnt <= #TCQ 'd0; + end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin + pi_rdval_cnt <= #TCQ pi_counter_read_val; + end else if (pi_rdval_cnt > 'd0) begin + if (pi_cnt_dec) + pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1; + else + pi_rdval_cnt <= #TCQ pi_rdval_cnt; + end else if (pi_rdval_cnt == 'd0) begin + pi_rdval_cnt <= #TCQ pi_rdval_cnt; + end + end + + always @(posedge clk) begin + if (rst || (pi_rdval_cnt == 'd0)) + pi_cnt_dec <= #TCQ 1'b0; + else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0) + && (dec_wait_cnt == 'd1)) + pi_cnt_dec <= #TCQ 1'b1; + else + pi_cnt_dec <= #TCQ 1'b0; + end + + // Inc/Dec Phaser_In stage 2 fine delay line + always @(posedge clk) begin + if (rst) begin + dec_pi_f_incdec_r <= #TCQ 1'b0; + dec_pi_f_en_r <= #TCQ 1'b0; + end else if (pi_cnt_dec) begin + dec_pi_f_incdec_r <= #TCQ 1'b0; + dec_pi_f_en_r <= #TCQ 1'b1; + end else begin + dec_pi_f_incdec_r <= #TCQ 1'b0; + dec_pi_f_en_r <= #TCQ 1'b0; + end + end + + always @(posedge clk) begin + if (rst) begin + fine_dly_dec_done_r1 <= #TCQ 1'b0; + end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) || + (dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin + fine_dly_dec_done_r1 <= #TCQ 1'b1; + end + end + + assign skip_cal_po_pi_dec_done = fine_dly_dec_done_r3; + +//*************************end Phaser_Out and Phaser_In decrement to zero******* + + + + localparam WAIT_CNT = 15; + + // State Machine + localparam [4:0] IDLE = 5'h00; + localparam [4:0] READ_PO_PI_COUNTER_VAL = 5'h01; + localparam [4:0] CALC_INC_DEC_CNT_VAL = 5'h02; + localparam [4:0] WAIT_STG3_SEL = 5'h03; + localparam [4:0] PO_COARSE_CNT_CHECK = 5'h04; + localparam [4:0] PO_COARSE_INC = 5'h05; + localparam [4:0] PO_STG3_SEL = 5'h06; + localparam [4:0] PO_STG3_INC_CNT_CHECK = 5'h07; + localparam [4:0] PO_STG3_INC = 5'h08; + localparam [4:0] PO_STG3_DEC_CNT_CHECK = 5'h09; + localparam [4:0] PO_STG3_DEC = 5'h0A; + localparam [4:0] PO_STG2_INC_CNT_CHECK = 5'h0B; + localparam [4:0] PO_STG2_INC = 5'h0C; + localparam [4:0] PO_STG2_DEC_CNT_CHECK = 5'h0D; + localparam [4:0] PO_STG2_DEC = 5'h0E; + localparam [4:0] PI_STG2_INC_CNT_CHECK = 5'h0F; + localparam [4:0] PI_STG2_INC = 5'h10; + localparam [4:0] PI_STG2_DEC_CNT_CHECK = 5'h11; + localparam [4:0] PI_STG2_DEC = 5'h12; + localparam [4:0] IDELAY_CNT_CHECK = 5'h13; + localparam [4:0] IDELAY_TAP_INC = 5'h14; + localparam [4:0] WAIT_TAP_INC_DEC = 5'h15; + localparam [4:0] NEXT_BYTE = 5'h16; + localparam [4:0] WAIT_PO_PI_COUNTER_VAL = 5'h17; + localparam [4:0] PO_PI_TAP_ADJ_DONE = 5'h18; + + + reg calib_tap_inc_start_r; + reg [4:0] skip_state_r; + reg wait_cnt_en_r; + reg wait_cnt_done; + reg [3:0] wait_cnt_r; + reg po_sel_stg23_r; + reg po_f_en_r; + reg po_f_incdec_r; + reg po_c_en_r; + reg po_c_inc_r; + reg pi_f_en_r; + reg pi_f_incdec_r; + reg idelay_ce_r; + reg idelay_inc_r; + reg [2:0] po_c_inc_cnt; + reg [5:0] po_stg3_inc_cnt; + reg [5:0] po_stg3_dec_cnt; + reg [5:0] po_stg2_inc_cnt; + reg [5:0] po_stg2_dec_cnt; + reg [5:0] pi_stg2_inc_cnt; + reg [5:0] pi_stg2_dec_cnt; + reg [4:0] idelay_inc_cnt; + reg po_stg3_cnt_load_r; + reg po_c_inc_active_r; + reg po_stg3_inc_active_r; + reg po_stg3_dec_active_r; + reg po_stg2_inc_active_r; + reg po_stg2_dec_active_r; + reg pi_stg2_inc_active_r; + reg pi_stg2_dec_active_r; + reg idelay_inc_active_r; + reg [5:0] byte_cnt_r; + reg tap_adj_done_r; + reg [2:0] calib_byte_po_c_cnt; + reg [5:0] calib_byte_po_stg2_cnt; + reg [5:0] calib_byte_po_stg3_cnt; + reg [5:0] calib_byte_pi_stg2_cnt; + reg [4:0] calib_byte_idelay_cnt; + + reg [4:0] skip_next_state; + reg [5:0] byte_cnt; + reg tap_adj_done; + reg po_sel_stg23; + reg po_f_en; + reg po_f_incdec; + reg po_c_en; + reg po_c_inc; + reg pi_f_en; + reg pi_f_incdec; + reg idelay_ce; + reg idelay_inc; + reg po_stg3_cnt_load; + reg po_c_inc_active; + reg po_stg3_inc_active; + reg po_stg3_dec_active; + reg po_stg2_inc_active; + reg po_stg2_dec_active; + reg pi_stg2_inc_active; + reg pi_stg2_dec_active; + reg idelay_inc_active; + + + +// Output assignments + assign calib_tap_inc_byte_cnt = byte_cnt_r; + assign calib_po_f_en = fine_dly_dec_done_r3 ? po_f_en_r : dec_po_f_en_r; + assign calib_po_f_incdec = fine_dly_dec_done_r3 ? po_f_incdec_r : dec_po_f_incdec_r; + assign calib_po_sel_stg2stg3 = po_sel_stg23_r; + assign calib_po_c_en = po_c_en_r; + assign calib_po_c_inc = po_c_inc_r; + assign calib_pi_f_en = fine_dly_dec_done_r3 ? pi_f_en_r : dec_pi_f_en_r; + assign calib_pi_f_incdec = fine_dly_dec_done_r3 ? pi_f_incdec_r : dec_pi_f_incdec_r; + assign calib_idelay_ce = idelay_ce_r; + assign calib_idelay_inc = idelay_inc_r; + assign calib_tap_inc_done = tap_adj_done_r; + +// Register input calib_tap_inc_start + always @(posedge clk) + calib_tap_inc_start_r <= #TCQ calib_tap_inc_start; + + +/**************************Wait Counter Start*********************************/ +// Wait counter enable for wait states WAIT_STG3_SEL, WAIT_TAP_INC_DEC, and +// WAIT_PO_PI_COUNTER_VAL + always @(posedge clk) begin + if ((skip_state_r == WAIT_STG3_SEL) || + (skip_state_r == WAIT_TAP_INC_DEC) || + (skip_state_r == WAIT_PO_PI_COUNTER_VAL)) + wait_cnt_en_r <= #TCQ 1'b1; + else + wait_cnt_en_r <= #TCQ 1'b0; + end + +// Wait counter enable for wait states WAIT_STG3_SEL, WAIT_TAP_INC_DEC, and +// WAIT_PO_PI_COUNTER_VAL + always @(posedge clk) begin + if (!wait_cnt_en_r) begin + wait_cnt_r <= #TCQ 'b0; + wait_cnt_done <= #TCQ 1'b0; + end else begin + if (wait_cnt_r != WAIT_CNT - 1) begin + wait_cnt_r <= #TCQ wait_cnt_r + 1; + wait_cnt_done <= #TCQ 1'b0; + end else begin + wait_cnt_r <= #TCQ 'b0; + wait_cnt_done <= #TCQ 1'b1; + end + end + end +/**************************Wait Counter End***********************************/ + +// Calibration tap values for current byte being adjusted + always @(posedge clk) begin + if (rst) begin + calib_byte_po_c_cnt <= #TCQ 'd0; + calib_byte_po_stg2_cnt <= #TCQ 'd0; + calib_byte_po_stg3_cnt <= #TCQ 'd0; + calib_byte_pi_stg2_cnt <= #TCQ 'd0; + calib_byte_idelay_cnt <= #TCQ 'd0; + end else begin + calib_byte_po_c_cnt <= #TCQ calib_po_coarse_tap_cnt[3*byte_cnt_r+:3]; + calib_byte_po_stg2_cnt <= #TCQ calib_po_stage2_tap_cnt[6*byte_cnt_r+:6]; + calib_byte_po_stg3_cnt <= #TCQ calib_po_stage3_tap_cnt[6*byte_cnt_r+:6]; + calib_byte_pi_stg2_cnt <= #TCQ calib_pi_stage2_tap_cnt[6*byte_cnt_r+:6]; + calib_byte_idelay_cnt <= #TCQ calib_idelay_tap_cnt[5*byte_cnt_r+:5]; + end + end + +// Phaser_Out, Phaser_In, and IDELAY inc/dec counters + always @(posedge clk) begin + if (rst) begin + po_c_inc_cnt <= #TCQ 'd0; + po_stg2_inc_cnt <= #TCQ 'd0; + po_stg2_dec_cnt <= #TCQ 'd0; + pi_stg2_inc_cnt <= #TCQ 'd0; + pi_stg2_dec_cnt <= #TCQ 'd0; + idelay_inc_cnt <= #TCQ 'd0; + end else if (skip_state_r == READ_PO_PI_COUNTER_VAL) begin + // IDELAY tap count setting + idelay_inc_cnt <= #TCQ calib_byte_idelay_cnt; + // Phaser_Out coarse tap setting + if (po_counter_read_val[8:6] == 'd0) begin + coarse_dec_err <= #TCQ 1'b0; + po_c_inc_cnt <= #TCQ calib_byte_po_c_cnt; + end else if (po_counter_read_val[8:6] < calib_byte_po_c_cnt) begin + coarse_dec_err <= #TCQ 1'b0; + po_c_inc_cnt <= #TCQ calib_byte_po_c_cnt - po_counter_read_val[8:6]; + end else begin + // Phaser_Out coarse taps cannot be decremented + coarse_dec_err <= #TCQ 1'b1; + po_c_inc_cnt <= #TCQ 'd0; + end + // Phaser_Out stage2 tap count setting when po_sel_stg23_r=0 + if (po_counter_read_val[5:0] == 'd0) begin + po_stg2_inc_cnt <= #TCQ calib_byte_po_stg2_cnt; + po_stg2_dec_cnt <= #TCQ 'd0; + end else if (po_counter_read_val[5:0] > calib_byte_po_stg2_cnt) begin + po_stg2_inc_cnt <= #TCQ 'd0; + po_stg2_dec_cnt <= #TCQ po_counter_read_val[5:0] - calib_byte_po_stg2_cnt; + end else if (po_counter_read_val[5:0] < calib_byte_po_stg2_cnt) begin + po_stg2_inc_cnt <= #TCQ calib_byte_po_stg2_cnt - po_counter_read_val[5:0]; + po_stg2_dec_cnt <= #TCQ 'd0; + end else if (po_counter_read_val[5:0] == calib_byte_po_stg2_cnt) begin + po_stg2_inc_cnt <= #TCQ 'd0; + po_stg2_dec_cnt <= #TCQ 'd0; + end + //Phaser_In stgae2 tap count setting + if (pi_counter_read_val == 'd0) begin + pi_stg2_inc_cnt <= #TCQ calib_byte_pi_stg2_cnt; + pi_stg2_dec_cnt <= #TCQ 'd0; + end else if (pi_counter_read_val > calib_byte_pi_stg2_cnt) begin + pi_stg2_inc_cnt <= #TCQ 'd0; + pi_stg2_dec_cnt <= #TCQ pi_counter_read_val - calib_byte_pi_stg2_cnt; + end else if (pi_counter_read_val < calib_byte_pi_stg2_cnt) begin + pi_stg2_inc_cnt <= #TCQ calib_byte_pi_stg2_cnt - pi_counter_read_val; + pi_stg2_dec_cnt <= #TCQ 'd0; + end else if (pi_counter_read_val == calib_byte_pi_stg2_cnt) begin + pi_stg2_inc_cnt <= #TCQ 'd0; + pi_stg2_dec_cnt <= #TCQ 'd0; + end + end else begin + if (skip_state_r == IDELAY_TAP_INC) + idelay_inc_cnt <= #TCQ idelay_inc_cnt - 1; + if (skip_state_r == PO_COARSE_INC) + po_c_inc_cnt <= #TCQ po_c_inc_cnt - 1; + if (skip_state_r == PO_STG2_INC) + po_stg2_inc_cnt <= #TCQ po_stg2_inc_cnt - 1; + if (skip_state_r == PO_STG2_DEC) + po_stg2_dec_cnt <= #TCQ po_stg2_dec_cnt - 1; + if (skip_state_r == PI_STG2_INC) + pi_stg2_inc_cnt <= #TCQ pi_stg2_inc_cnt - 1; + if (skip_state_r == PI_STG2_DEC) + pi_stg2_dec_cnt <= #TCQ pi_stg2_dec_cnt - 1; + end + end + + // Phaser_Out stage 3 tap count setting when po_sel_stg23_r=1 + always @(posedge clk) begin + if (rst) begin + po_stg3_inc_cnt <= #TCQ 'd0; + po_stg3_dec_cnt <= #TCQ 'd0; + end else if ((skip_state_r == WAIT_STG3_SEL) && wait_cnt_done && po_stg3_cnt_load_r) begin + if (po_counter_read_val[5:0] == 'd0) begin + po_stg3_inc_cnt <= #TCQ calib_byte_po_stg3_cnt; + po_stg3_dec_cnt <= #TCQ 'd0; + end else if (po_counter_read_val[5:0] > calib_byte_po_stg3_cnt) begin + po_stg3_inc_cnt <= #TCQ 'd0; + po_stg3_dec_cnt <= #TCQ po_counter_read_val[5:0] - calib_byte_po_stg3_cnt; + end else if (po_counter_read_val[5:0] < calib_byte_po_stg3_cnt) begin + po_stg3_inc_cnt <= #TCQ calib_byte_po_stg3_cnt - po_counter_read_val[5:0]; + po_stg3_dec_cnt <= #TCQ 'd0; + end else if (po_counter_read_val[5:0] == calib_byte_po_stg3_cnt) begin + po_stg3_inc_cnt <= #TCQ 'd0; + po_stg3_dec_cnt <= #TCQ 'd0; + end + end else begin + if (skip_state_r == PO_STG3_INC) + po_stg3_inc_cnt <= #TCQ po_stg3_inc_cnt - 1; + if (skip_state_r == PO_STG3_DEC) + po_stg3_dec_cnt <= #TCQ po_stg3_dec_cnt - 1; + end + end + + always @(posedge clk) begin + if (rst) begin + skip_state_r <= #TCQ IDLE; + byte_cnt_r <= #TCQ 'd0; + tap_adj_done_r <= #TCQ 1'b0; + po_sel_stg23_r <= #TCQ 1'b0; + po_f_en_r <= #TCQ 1'b0; + po_f_incdec_r <= #TCQ 1'b0; + po_c_en_r <= #TCQ 1'b0; + po_c_inc_r <= #TCQ 1'b0; + pi_f_en_r <= #TCQ 1'b0; + pi_f_incdec_r <= #TCQ 1'b0; + idelay_ce_r <= #TCQ 1'b0; + idelay_inc_r <= #TCQ 1'b0; + po_stg3_cnt_load_r <= #TCQ 1'b0; + po_c_inc_active_r <= #TCQ 1'b0; + po_stg3_inc_active_r <= #TCQ 1'b0; + po_stg3_dec_active_r <= #TCQ 1'b0; + po_stg2_inc_active_r <= #TCQ 1'b0; + po_stg2_dec_active_r <= #TCQ 1'b0; + pi_stg2_inc_active_r <= #TCQ 1'b0; + pi_stg2_dec_active_r <= #TCQ 1'b0; + idelay_inc_active_r <= #TCQ 1'b0; + end else begin + skip_state_r <= #TCQ skip_next_state; + byte_cnt_r <= #TCQ byte_cnt; + tap_adj_done_r <= #TCQ tap_adj_done; + po_sel_stg23_r <= #TCQ po_sel_stg23; + po_f_en_r <= #TCQ po_f_en; + po_f_incdec_r <= #TCQ po_f_incdec; + po_c_en_r <= #TCQ po_c_en; + po_c_inc_r <= #TCQ po_c_inc; + pi_f_en_r <= #TCQ pi_f_en; + pi_f_incdec_r <= #TCQ pi_f_incdec; + idelay_ce_r <= #TCQ idelay_ce; + idelay_inc_r <= #TCQ idelay_inc; + po_stg3_cnt_load_r <= #TCQ po_stg3_cnt_load; + po_c_inc_active_r <= #TCQ po_c_inc_active; + po_stg3_inc_active_r <= #TCQ po_stg3_inc_active; + po_stg3_dec_active_r <= #TCQ po_stg3_dec_active; + po_stg2_inc_active_r <= #TCQ po_stg2_inc_active; + po_stg2_dec_active_r <= #TCQ po_stg2_dec_active; + pi_stg2_inc_active_r <= #TCQ pi_stg2_inc_active; + pi_stg2_dec_active_r <= #TCQ pi_stg2_dec_active; + idelay_inc_active_r <= #TCQ idelay_inc_active; + end + end + +// State Machine + always @(*) begin + skip_next_state = skip_state_r; + byte_cnt = byte_cnt_r; + tap_adj_done = tap_adj_done_r; + po_sel_stg23 = po_sel_stg23_r; + po_f_en = po_f_en_r; + po_f_incdec = po_f_incdec_r; + po_c_en = po_c_en_r; + po_c_inc = po_c_inc_r; + pi_f_en = pi_f_en_r; + pi_f_incdec = pi_f_incdec_r; + idelay_ce = idelay_ce_r; + idelay_inc = idelay_inc_r; + po_stg3_cnt_load = po_stg3_cnt_load_r; + po_c_inc_active = po_c_inc_active_r; + po_stg3_inc_active = po_stg3_inc_active_r; + po_stg3_dec_active = po_stg3_dec_active_r; + po_stg2_inc_active = po_stg2_inc_active_r; + po_stg2_dec_active = po_stg2_dec_active_r; + pi_stg2_inc_active = pi_stg2_inc_active_r; + pi_stg2_dec_active = pi_stg2_dec_active_r; + idelay_inc_active = idelay_inc_active_r; + + + case(skip_state_r) + IDLE: begin + // Begin tap adjustment on the rising edge of calib_tap_inc_start + // This logic assumes that load_done is asserted before calib_tap_inc_start + // If this is not the case this logic will have to change + if (calib_tap_inc_start && ~calib_tap_inc_start_r && load_done) begin + skip_next_state = READ_PO_PI_COUNTER_VAL; + end + end + + READ_PO_PI_COUNTER_VAL: begin + skip_next_state = CALC_INC_DEC_CNT_VAL; + end + + CALC_INC_DEC_CNT_VAL: begin + skip_next_state = WAIT_STG3_SEL; + po_sel_stg23 = 1'b1; + po_stg3_cnt_load = 1'b1; + end + + WAIT_STG3_SEL: begin + if (wait_cnt_done) begin + if (po_stg3_cnt_load) + skip_next_state = PO_STG3_SEL; + else + skip_next_state = PO_COARSE_CNT_CHECK; + end + end + + PO_COARSE_CNT_CHECK: begin + if (po_c_inc_cnt > 'd0) begin + po_c_inc_active = 1'b1; + skip_next_state = PO_COARSE_INC; + end else begin + po_c_inc_active = 1'b0; + skip_next_state = PO_STG2_DEC_CNT_CHECK; + end + end + + PO_COARSE_INC: begin + po_c_en = 1'b1; + po_c_inc = 1'b1; + skip_next_state = WAIT_TAP_INC_DEC; + end + + PO_STG3_SEL: begin + po_stg3_cnt_load = 1'b0; + if (po_stg3_inc_cnt > 'd0) begin + po_stg3_inc_active = 1'b1; + skip_next_state = PO_STG3_INC; + end else if (po_stg3_dec_cnt > 'd0) begin + po_stg3_dec_active = 1'b1; + skip_next_state = PO_STG3_DEC; + end else begin + po_sel_stg23 = 1'b0; + skip_next_state = WAIT_STG3_SEL; + + end + end + + PO_STG3_INC_CNT_CHECK: begin + if (po_stg3_inc_cnt > 'd0) begin + po_stg3_inc_active = 1'b1; + skip_next_state = PO_STG3_INC; + end else begin + po_stg3_inc_active = 1'b0; + po_sel_stg23 = 1'b0; + skip_next_state = WAIT_STG3_SEL; + end + end + + PO_STG3_INC: begin + po_f_en = 1'b1; + po_f_incdec = 1'b1; + skip_next_state = WAIT_TAP_INC_DEC; + end + + PO_STG3_DEC_CNT_CHECK: begin + if (po_stg3_dec_cnt > 'd0) begin + po_stg3_dec_active = 1'b1; + skip_next_state = PO_STG3_DEC; + end else begin + po_stg3_dec_active = 1'b0; + po_sel_stg23 = 1'b0; + skip_next_state = WAIT_STG3_SEL; + end + end + + PO_STG3_DEC: begin + po_f_en = 1'b1; + po_f_incdec = 1'b0; + skip_next_state = WAIT_TAP_INC_DEC; + end + + PO_STG2_DEC_CNT_CHECK: begin + if (po_stg2_dec_cnt > 'd0) begin + po_stg2_dec_active = 1'b1; + skip_next_state = PO_STG2_DEC; + end else if (po_stg2_inc_cnt > 'd0) begin + po_stg2_dec_active = 1'b0; + skip_next_state = PO_STG2_INC_CNT_CHECK; + end else begin + po_stg2_dec_active = 1'b0; + skip_next_state = PI_STG2_DEC_CNT_CHECK; + end + end + + PO_STG2_DEC: begin + po_f_en = 1'b1; + po_f_incdec = 1'b0; + skip_next_state = WAIT_TAP_INC_DEC; + end + + PO_STG2_INC_CNT_CHECK: begin + if (po_stg2_inc_cnt > 'd0) begin + po_stg2_inc_active = 1'b1; + skip_next_state = PO_STG2_INC; + end else begin + po_stg2_inc_active = 1'b0; + skip_next_state = PI_STG2_DEC_CNT_CHECK; + end + end + + PO_STG2_INC: begin + po_f_en = 1'b1; + po_f_incdec = 1'b1; + skip_next_state = WAIT_TAP_INC_DEC; + end + + PI_STG2_DEC_CNT_CHECK: begin + if (pi_stg2_dec_cnt > 'd0) begin + pi_stg2_dec_active = 1'b1; + skip_next_state = PI_STG2_DEC; + end else if (pi_stg2_inc_cnt > 'd0) begin + pi_stg2_dec_active = 1'b0; + skip_next_state = PI_STG2_INC_CNT_CHECK; + end else begin + pi_stg2_dec_active = 1'b0; + skip_next_state = IDELAY_CNT_CHECK; + end + end + + PI_STG2_DEC: begin + pi_f_en = 1'b1; + pi_f_incdec = 1'b0; + skip_next_state = WAIT_TAP_INC_DEC; + end + + PI_STG2_INC_CNT_CHECK: begin + if (pi_stg2_inc_cnt > 'd0) begin + pi_stg2_inc_active = 1'b1; + skip_next_state = PI_STG2_INC; + end else begin + pi_stg2_inc_active = 1'b0; + skip_next_state = IDELAY_CNT_CHECK; + end + end + + PI_STG2_INC: begin + pi_f_en = 1'b1; + pi_f_incdec = 1'b1; + skip_next_state = WAIT_TAP_INC_DEC; + end + + IDELAY_CNT_CHECK: begin + if (idelay_inc_cnt > 'd0) begin + idelay_inc_active = 1'b1; + skip_next_state = IDELAY_TAP_INC; + end else begin + idelay_inc_active = 1'b0; + skip_next_state = NEXT_BYTE; + end + end + + IDELAY_TAP_INC: begin + idelay_ce = 1'b1; + idelay_inc = 1'b1; + skip_next_state = WAIT_TAP_INC_DEC; + end + + WAIT_TAP_INC_DEC: begin + po_c_en = 1'b0; + po_c_inc = 1'b0; + po_f_en = 1'b0; + po_f_incdec = 1'b0; + pi_f_en = 1'b0; + pi_f_incdec = 1'b0; + idelay_ce = 1'b0; + idelay_inc = 1'b0; + if (wait_cnt_done) begin + if (po_c_inc_active_r) + skip_next_state = PO_COARSE_CNT_CHECK; + else if (po_stg3_inc_active_r) + skip_next_state = PO_STG3_INC_CNT_CHECK; + else if (po_stg3_dec_active_r) + skip_next_state = PO_STG3_DEC_CNT_CHECK; + else if (po_stg2_dec_active_r) + skip_next_state = PO_STG2_DEC_CNT_CHECK; + else if (po_stg2_inc_active_r) + skip_next_state = PO_STG2_INC_CNT_CHECK; + else if (pi_stg2_dec_active_r) + skip_next_state = PI_STG2_DEC_CNT_CHECK; + else if (pi_stg2_inc_active_r) + skip_next_state = PI_STG2_INC_CNT_CHECK; + else if (idelay_inc_active_r) + skip_next_state = IDELAY_CNT_CHECK; + end + end + + NEXT_BYTE: begin + if (byte_cnt_r >= DQS_WIDTH-1) begin + skip_next_state = PO_PI_TAP_ADJ_DONE; + end else begin + byte_cnt = byte_cnt + 1; + skip_next_state = WAIT_PO_PI_COUNTER_VAL; + end + end + + WAIT_PO_PI_COUNTER_VAL: begin + if (wait_cnt_done) + skip_next_state = READ_PO_PI_COUNTER_VAL; + end + + PO_PI_TAP_ADJ_DONE: begin + tap_adj_done = 1'b1; + end + + default: begin + skip_next_state = IDLE; + end + + endcase + end + + //Debug + assign dbg_skip_cal[4:0] = skip_state_r; + assign dbg_skip_cal[7:5] = po_c_inc_cnt; + assign dbg_skip_cal[13:8] = po_stg3_inc_cnt; + assign dbg_skip_cal[19:14] = po_stg3_dec_cnt; + assign dbg_skip_cal[25:20] = po_stg2_inc_cnt; + assign dbg_skip_cal[31:26] = po_stg2_dec_cnt; + assign dbg_skip_cal[37:32] = pi_stg2_inc_cnt; + assign dbg_skip_cal[43:38] = pi_stg2_dec_cnt; + assign dbg_skip_cal[48:44] = idelay_inc_cnt; + assign dbg_skip_cal[54:49] = byte_cnt_r; + assign dbg_skip_cal[55] = po_c_inc_active; + assign dbg_skip_cal[56] = po_stg3_inc_active; + assign dbg_skip_cal[57] = po_stg3_dec_active; + assign dbg_skip_cal[58] = po_stg2_inc_active; + assign dbg_skip_cal[59] = po_stg2_dec_active; + assign dbg_skip_cal[60] = pi_stg2_inc_active; + assign dbg_skip_cal[61] = pi_stg2_dec_active; + assign dbg_skip_cal[62] = idelay_inc_active; + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_infrastructure.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_infrastructure.v new file mode 100644 index 0000000..02d85aa --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_infrastructure.v @@ -0,0 +1,767 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: infrastructure.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ +// \ \ / \ Date Created:Tue Jun 30 2009 +// \___\/\___\ +// +//Device: Virtex-6 +//Design Name: DDR3 SDRAM +//Purpose: +// Clock generation/distribution and reset synchronization +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: infrastructure.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ +**$Date: 2011/06/02 08:34:56 $ +**$Author: mishra $ +**$Revision: 1.1 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/infrastructure.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + + +module mig_7series_v4_0_infrastructure # + ( + parameter SIMULATION = "FALSE", // Should be TRUE during design simulations and + // FALSE during implementations + parameter TCQ = 100, // clk->out delay (sim only) + parameter CLKIN_PERIOD = 3000, // Memory clock period + parameter nCK_PER_CLK = 2, // Fabric clk period:Memory clk period + parameter SYSCLK_TYPE = "DIFFERENTIAL", + // input clock type + // "DIFFERENTIAL","SINGLE_ENDED" + parameter UI_EXTRA_CLOCKS = "FALSE", + // Generates extra clocks as + // 1/2, 1/4 and 1/8 of fabrick clock. + // Valid for DDR2/DDR3 AXI interfaces + // based on GUI selection + parameter CLKFBOUT_MULT = 4, // write PLL VCO multiplier + parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor + parameter CLKOUT0_PHASE = 45.0, // VCO output divisor for clkout0 + parameter CLKOUT0_DIVIDE = 16, // VCO output divisor for PLL clkout0 + parameter CLKOUT1_DIVIDE = 4, // VCO output divisor for PLL clkout1 + parameter CLKOUT2_DIVIDE = 64, // VCO output divisor for PLL clkout2 + parameter CLKOUT3_DIVIDE = 16, // VCO output divisor for PLL clkout3 + parameter MMCM_VCO = 1200, // Max Freq (MHz) of MMCM VCO + parameter MMCM_MULT_F = 4, // write MMCM VCO multiplier + parameter MMCM_DIVCLK_DIVIDE = 1, // write MMCM VCO divisor + parameter MMCM_CLKOUT0_EN = "FALSE", // Enabled (or) Disable MMCM clkout0 + parameter MMCM_CLKOUT1_EN = "FALSE", // Enabled (or) Disable MMCM clkout1 + parameter MMCM_CLKOUT2_EN = "FALSE", // Enabled (or) Disable MMCM clkout2 + parameter MMCM_CLKOUT3_EN = "FALSE", // Enabled (or) Disable MMCM clkout3 + parameter MMCM_CLKOUT4_EN = "FALSE", // Enabled (or) Disable MMCM clkout4 + parameter MMCM_CLKOUT0_DIVIDE = 1, // VCO output divisor for MMCM clkout0 + parameter MMCM_CLKOUT1_DIVIDE = 1, // VCO output divisor for MMCM clkout1 + parameter MMCM_CLKOUT2_DIVIDE = 1, // VCO output divisor for MMCM clkout2 + parameter MMCM_CLKOUT3_DIVIDE = 1, // VCO output divisor for MMCM clkout3 + parameter MMCM_CLKOUT4_DIVIDE = 1, // VCO output divisor for MMCM clkout4 + parameter RST_ACT_LOW = 1, + parameter tCK = 1250, + // memory tCK paramter. + // # = Clock Period in pS. + parameter MEM_TYPE = "DDR3" + ) + ( + // Clock inputs + input mmcm_clk, // System clock diff input + // System reset input + input sys_rst, // core reset from user application + // PLLE2/IDELAYCTRL Lock status + input [1:0] iodelay_ctrl_rdy, // IDELAYCTRL lock status + // Clock outputs + + output clk, // fabric clock freq ; either half rate or quarter rate and is + // determined by PLL parameters settings. + output clk_div2, // mem_refclk divided by 2 for PI incdec + output rst_div2, // reset in clk_div2 domain + output mem_refclk, // equal to memory clock + output freq_refclk, // freq above 400 MHz: set freq_refclk = mem_refclk + // freq below 400 MHz: set freq_refclk = 2* mem_refclk or 4* mem_refclk; + // to hard PHY for phaser + output sync_pulse, // exactly 1/16 of mem_refclk and the sync pulse is exactly 1 memref_clk wide +// output auxout_clk, // IO clk used to clock out Aux_Out ports + output mmcm_ps_clk, // Phase shift clock + output poc_sample_pd, // Tell POC when to sample phase detector output. + output ui_addn_clk_0, // MMCM out0 clk + output ui_addn_clk_1, // MMCM out1 clk + output ui_addn_clk_2, // MMCM out2 clk + output ui_addn_clk_3, // MMCM out3 clk + output ui_addn_clk_4, // MMCM out4 clk + output pll_locked, // locked output from PLLE2_ADV + output mmcm_locked, // locked output from MMCME2_ADV + // Reset outputs + output rstdiv0, // Reset CLK and CLKDIV logic (incl I/O), + output iddr_rst + + ,output rst_phaser_ref + ,input ref_dll_lock + ,input psen + ,input psincdec + ,output psdone + ); + + // # of clock cycles to delay deassertion of reset. Needs to be a fairly + // high number not so much for metastability protection, but to give time + // for reset (i.e. stable clock cycles) to propagate through all state + // machines and to all control signals (i.e. not all control signals have + // resets, instead they rely on base state logic being reset, and the effect + // of that reset propagating through the logic). Need this because we may not + // be getting stable clock cycles while reset asserted (i.e. since reset + // depends on DCM lock status) + localparam RST_SYNC_NUM = 25; + + // Round up for clk reset delay to ensure that CLKDIV reset deassertion + // occurs at same time or after CLK reset deassertion (still need to + // consider route delay - add one or two extra cycles to be sure!) + localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2; + + // Input clock is assumed to be equal to the memory clock frequency + // User should change the parameter as necessary if a different input + // clock frequency is used + localparam real CLKIN1_PERIOD_NS = CLKIN_PERIOD / 1000.0; + localparam CLKOUT4_DIVIDE = 2 * CLKOUT1_DIVIDE; + + localparam integer VCO_PERIOD + = (CLKIN1_PERIOD_NS * DIVCLK_DIVIDE * 1000) / CLKFBOUT_MULT; + + localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE; + localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE; + localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE; + localparam CLKOUT3_PERIOD = VCO_PERIOD * CLKOUT3_DIVIDE; + localparam CLKOUT4_PERIOD = VCO_PERIOD * CLKOUT4_DIVIDE; + + localparam CLKOUT4_PHASE = (SIMULATION == "TRUE") ? 22.5 : 168.75; + + localparam real CLKOUT3_PERIOD_NS = CLKOUT3_PERIOD / 1000.0; + localparam real CLKOUT4_PERIOD_NS = CLKOUT4_PERIOD / 1000.0; + + //synthesis translate_off + initial begin + $display("############# Write Clocks PLLE2_ADV Parameters #############\n"); + $display("nCK_PER_CLK = %7d", nCK_PER_CLK ); + $display("CLK_PERIOD = %7d", CLKIN_PERIOD ); + $display("CLKIN1_PERIOD = %7.3f", CLKIN1_PERIOD_NS); + $display("DIVCLK_DIVIDE = %7d", DIVCLK_DIVIDE ); + $display("CLKFBOUT_MULT = %7d", CLKFBOUT_MULT ); + $display("VCO_PERIOD = %7.1f", VCO_PERIOD ); + $display("CLKOUT0_DIVIDE_F = %7d", CLKOUT0_DIVIDE ); + $display("CLKOUT1_DIVIDE = %7d", CLKOUT1_DIVIDE ); + $display("CLKOUT2_DIVIDE = %7d", CLKOUT2_DIVIDE ); + $display("CLKOUT3_DIVIDE = %7d", CLKOUT3_DIVIDE ); + $display("CLKOUT0_PERIOD = %7d", CLKOUT0_PERIOD ); + $display("CLKOUT1_PERIOD = %7d", CLKOUT1_PERIOD ); + $display("CLKOUT2_PERIOD = %7d", CLKOUT2_PERIOD ); + $display("CLKOUT3_PERIOD = %7d", CLKOUT3_PERIOD ); + $display("CLKOUT4_PERIOD = %7d", CLKOUT4_PERIOD ); + $display("############################################################\n"); + end + //synthesis translate_on + + wire clk_bufg; + wire clk_pll; + wire clkfbout_pll; + wire mmcm_clkfbout; + wire pll_locked_i + /* synthesis syn_maxfan = 10 */; + (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-2:0] rstdiv0_sync_r; + wire rst_tmp; + (* max_fanout = 50 *) reg rstdiv0_sync_r1 + /* synthesis syn_maxfan = 50 */; + reg [RST_DIV_SYNC_NUM-2:0] rst_sync_r; + (* max_fanout = 10 *) reg rst_sync_r1 + /* synthesis syn_maxfan = 10 */; + reg [RST_DIV_SYNC_NUM-2:0] rstdiv2_sync_r; + (* max_fanout = 10 *) reg rstdiv2_sync_r1 + /* synthesis syn_maxfan = 10 */; + wire sys_rst_act_hi; + + wire rst_tmp_phaser_ref; + (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-1:0] rst_phaser_ref_sync_r + /* synthesis syn_maxfan = 10 */; + + // Instantiation of the MMCM primitive + wire clkfbout; + wire MMCM_Locked_i; + + wire mmcm_clkout0; + wire mmcm_clkout1; + wire mmcm_clkout2; + wire mmcm_clkout3; + wire mmcm_clkout4; + wire mmcm_ps_clk_bufg_in; + wire clk_div2_bufg_in; + + wire pll_clk3_out; + wire pll_clk3; + + assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst; + + //*************************************************************************** + // Assign global clocks: + // 2. clk : Half rate / Quarter rate(used for majority of internal logic) + //*************************************************************************** + + assign clk = clk_bufg; + assign pll_locked = pll_locked_i & MMCM_Locked_i; + assign mmcm_locked = MMCM_Locked_i; + + + //*************************************************************************** + // Global base clock generation and distribution + //*************************************************************************** + + //***************************************************************** + // NOTES ON CALCULTING PROPER VCO FREQUENCY + // 1. VCO frequency = + // 1/((DIVCLK_DIVIDE * CLKIN_PERIOD)/(CLKFBOUT_MULT * nCK_PER_CLK)) + // 2. VCO frequency must be in the range [TBD, TBD] + //***************************************************************** + + PLLE2_ADV # + ( + .BANDWIDTH ("OPTIMIZED"), + .COMPENSATION ("INTERNAL"), + .STARTUP_WAIT ("FALSE"), + .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), // 4 freq_ref + .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), // 4 mem_ref + .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), // 16 sync + .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), // 16 sysclk + .CLKOUT4_DIVIDE (CLKOUT4_DIVIDE), + .CLKOUT5_DIVIDE (), + .DIVCLK_DIVIDE (DIVCLK_DIVIDE), + .CLKFBOUT_MULT (CLKFBOUT_MULT), + .CLKFBOUT_PHASE (0.000), + .CLKIN1_PERIOD (CLKIN1_PERIOD_NS), + .CLKIN2_PERIOD (), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_PHASE (CLKOUT0_PHASE), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (1.0/16.0), + .CLKOUT2_PHASE (9.84375), // PHASE shift is required for sync pulse generation. + .CLKOUT3_DUTY_CYCLE (0.500), + .CLKOUT3_PHASE (0.000), + .CLKOUT4_DUTY_CYCLE (0.500), + .CLKOUT4_PHASE (CLKOUT4_PHASE), + .CLKOUT5_DUTY_CYCLE (0.500), + .CLKOUT5_PHASE (0.000), + .REF_JITTER1 (0.010), + .REF_JITTER2 (0.010) + ) + plle2_i + ( + .CLKFBOUT (pll_clkfbout), + .CLKOUT0 (freq_refclk), + .CLKOUT1 (mem_refclk), + .CLKOUT2 (sync_pulse), // always 1/16 of mem_ref_clk + .CLKOUT3 (pll_clk3_out), +// .CLKOUT4 (auxout_clk_i), + .CLKOUT4 (), + .CLKOUT5 (), + .DO (), + .DRDY (), + .LOCKED (pll_locked_i), + .CLKFBIN (pll_clkfbout), + .CLKIN1 (mmcm_clk), + .CLKIN2 (), + .CLKINSEL (1'b1), + .DADDR (7'b0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'b0), + .DWE (1'b0), + .PWRDWN (1'b0), + .RST ( sys_rst_act_hi) + ); + + +// BUFH u_bufh_auxout_clk +// ( +// .O (auxout_clk), +// .I (auxout_clk_i) +// ); + + BUFG u_bufg_clkdiv0 + ( + .O (clk_bufg), + .I (clk_pll_i) + ); + + BUFH u_bufh_pll_clk3 + ( + .O (pll_clk3), + .I (pll_clk3_out) + ); + + localparam real MMCM_VCO_PERIOD = 1000000.0/MMCM_VCO; + + //synthesis translate_off + initial begin + $display("############# MMCME2_ADV Parameters #############\n"); + $display("MMCM_MULT_F = %d", MMCM_MULT_F); +// $display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO*1000.0); + $display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO*1.000); + $display("MMCM_VCO_PERIOD = %7.3f", MMCM_VCO_PERIOD); + $display("#################################################\n"); + end + //synthesis translate_on + + generate + if (UI_EXTRA_CLOCKS == "TRUE") begin: gen_ui_extra_clocks + + localparam MMCM_CLKOUT0_DIVIDE_CAL = (MMCM_CLKOUT0_EN == "TRUE") ? MMCM_CLKOUT0_DIVIDE : MMCM_MULT_F; + localparam MMCM_CLKOUT1_DIVIDE_CAL = (MMCM_CLKOUT1_EN == "TRUE") ? MMCM_CLKOUT1_DIVIDE : MMCM_MULT_F; + localparam MMCM_CLKOUT2_DIVIDE_CAL = (MMCM_CLKOUT2_EN == "TRUE") ? MMCM_CLKOUT2_DIVIDE : MMCM_MULT_F; + localparam MMCM_CLKOUT3_DIVIDE_CAL = (MMCM_CLKOUT3_EN == "TRUE") ? MMCM_CLKOUT3_DIVIDE : MMCM_MULT_F; + localparam MMCM_CLKOUT4_DIVIDE_CAL = (MMCM_CLKOUT4_EN == "TRUE") ? MMCM_CLKOUT4_DIVIDE : MMCM_MULT_F; + + MMCME2_ADV + #(.BANDWIDTH ("HIGH"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("BUF_IN"), + .STARTUP_WAIT ("FALSE"), +// .DIVCLK_DIVIDE (1), + .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), + .CLKFBOUT_MULT_F (MMCM_MULT_F), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (MMCM_CLKOUT0_DIVIDE_CAL), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (MMCM_CLKOUT1_DIVIDE_CAL), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (MMCM_CLKOUT2_DIVIDE_CAL), + .CLKOUT2_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKOUT3_DIVIDE (MMCM_CLKOUT3_DIVIDE_CAL), + .CLKOUT3_PHASE (0.000), + .CLKOUT3_DUTY_CYCLE (0.500), + .CLKOUT3_USE_FINE_PS ("FALSE"), + .CLKOUT4_DIVIDE (MMCM_CLKOUT4_DIVIDE_CAL), + .CLKOUT4_PHASE (0.000), + .CLKOUT4_DUTY_CYCLE (0.500), + .CLKOUT4_USE_FINE_PS ("FALSE"), + .CLKOUT5_DIVIDE (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), + .CLKOUT5_PHASE (0.000), + .CLKOUT5_DUTY_CYCLE (0.500), + .CLKOUT5_USE_FINE_PS ("TRUE"), + .CLKOUT6_DIVIDE (MMCM_MULT_F/2), + .CLKOUT6_PHASE (0.000), + .CLKOUT6_DUTY_CYCLE (0.500), + .CLKOUT6_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), + .REF_JITTER1 (0.000)) + mmcm_i + // Output clocks + (.CLKFBOUT (clk_pll_i), + .CLKFBOUTB (), + .CLKOUT0 (mmcm_clkout0), + .CLKOUT0B (), + .CLKOUT1 (mmcm_clkout1), + .CLKOUT1B (), + .CLKOUT2 (mmcm_clkout2), + .CLKOUT2B (), + .CLKOUT3 (mmcm_clkout3), + .CLKOUT3B (), + .CLKOUT4 (mmcm_clkout4), + .CLKOUT5 (mmcm_ps_clk_bufg_in), + .CLKOUT6 (clk_div2_bufg_in), + // Input clock control + .CLKFBIN (clk_bufg), // From BUFH network + .CLKIN1 (pll_clk3), // From PLL + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (clk), + .PSEN (psen), + .PSINCDEC (psincdec), + .PSDONE (psdone), + // Other control and status signals + .LOCKED (MMCM_Locked_i), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (~pll_locked_i)); + + BUFG u_bufg_ui_addn_clk_0 + ( + .O (ui_addn_clk_0), + .I (mmcm_clkout0) + ); + + BUFG u_bufg_ui_addn_clk_1 + ( + .O (ui_addn_clk_1), + .I (mmcm_clkout1) + ); + + BUFG u_bufg_ui_addn_clk_2 + ( + .O (ui_addn_clk_2), + .I (mmcm_clkout2) + ); + + BUFG u_bufg_ui_addn_clk_3 + ( + .O (ui_addn_clk_3), + .I (mmcm_clkout3) + ); + + BUFG u_bufg_ui_addn_clk_4 + ( + .O (ui_addn_clk_4), + .I (mmcm_clkout4) + ); + + BUFG u_bufg_mmcm_ps_clk + ( + .O (mmcm_ps_clk), + .I (mmcm_ps_clk_bufg_in) + ); + + BUFG u_bufg_clk_div2 + ( + .O (clk_div2), + .I (clk_div2_bufg_in) + ); + end else begin: gen_mmcm + + MMCME2_ADV + #(.BANDWIDTH ("HIGH"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("BUF_IN"), + .STARTUP_WAIT ("FALSE"), +// .DIVCLK_DIVIDE (1), + .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), + .CLKFBOUT_MULT_F (MMCM_MULT_F), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("TRUE"), + .CLKOUT1_DIVIDE (MMCM_MULT_F/2), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), + .REF_JITTER1 (0.000)) + mmcm_i + // Output clocks + (.CLKFBOUT (clk_pll_i), + .CLKFBOUTB (), + .CLKOUT0 (mmcm_ps_clk_bufg_in), + .CLKOUT0B (), + .CLKOUT1 (clk_div2_bufg_in), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (clk_bufg), // From BUFH network + .CLKIN1 (pll_clk3), // From PLL + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (clk), + .PSEN (psen), + .PSINCDEC (psincdec), + .PSDONE (psdone), + // Other control and status signals + .LOCKED (MMCM_Locked_i), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (~pll_locked_i)); + + BUFG u_bufg_mmcm_ps_clk + ( + .O (mmcm_ps_clk), + .I (mmcm_ps_clk_bufg_in) + ); + + BUFG u_bufg_clk_div2 + ( + .O (clk_div2), + .I (clk_div2_bufg_in) + ); + + end // block: gen_mmcm + endgenerate + + //*************************************************************************** + // Generate poc_sample_pd. + // + // As the phase shift clocks precesses around kclk, it also precesses + // around the fabric clock. Noise may be generated as output of the + // IDDR is registered into the fabric clock domain. + // + // The mmcm_ps_clk signal runs at half the rate of the fabric clock. + // This means that there are two rising edges of fabric clock per mmcm_ps_clk. + // If we can guarantee that the POC uses the data sampled on the second + // fabric clock, then we are certain that the setup time to the second + // fabric clock is greater than 1 fabric clock cycle. + // + // To predict when the phase detctor output is from this second edge, we + // need to know two things. The initial phase of fabric clock and mmcm_ps_clk + // and the number of phase offsets set into the mmcm. The later is a + // trivial count of the PSEN signal. + // + // The former is a bit tricky because latching a clock with a clock is + // not well defined. This problem is solved by generating a signal + // the goes high on the first rising edge of mmcm_ps_clk. Logic in + // the fabric domain can look at this signal and then develop an analog + // the mmcm_ps_clk with zero offset. + // + // This all depends on the timing tools making the timing work when + // when the mmcm phase offset is zero. + // + // poc_sample_pd tells the POC when to sample the phase detector output. + // Setup from the IDDR to the fabric clock is always one plus some + // fraction of the fabric clock. + //*************************************************************************** + + localparam ONE = 1; + localparam integer TAPSPERFCLK = 56 * MMCM_MULT_F; + localparam TAPSPERFCLK_MINUS_ONE = TAPSPERFCLK - 1; + localparam QCNTR_WIDTH = clogb2(TAPSPERFCLK); + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + reg [QCNTR_WIDTH-1:0] qcntr_ns, qcntr_r; + always @(posedge clk) qcntr_r <= #TCQ qcntr_ns; + + reg inv_poc_sample_ns, inv_poc_sample_r; + always @(posedge clk) inv_poc_sample_r <= #TCQ inv_poc_sample_ns; + + always @(*) begin + qcntr_ns = qcntr_r; + inv_poc_sample_ns = inv_poc_sample_r; + if (rstdiv0) begin + qcntr_ns = 'b0; + inv_poc_sample_ns = 'b0; + end else if (psen) begin + if (qcntr_r < TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0]) + qcntr_ns = (qcntr_r + ONE[QCNTR_WIDTH-1:0]); + else begin + qcntr_ns = {QCNTR_WIDTH{1'b0}}; + inv_poc_sample_ns = ~inv_poc_sample_r; + end + end + end + + // Be vewy vewy careful to make sure this path is aligned with the + // phase detector out pipeline. + reg first_rising_ps_clk_ns, first_rising_ps_clk_r; + always @(posedge mmcm_ps_clk) first_rising_ps_clk_r <= #TCQ first_rising_ps_clk_ns; + always @(*) first_rising_ps_clk_ns = ~rstdiv0; + + reg mmcm_hi0_ns, mmcm_hi0_r; + always @(posedge clk) mmcm_hi0_r <= #TCQ mmcm_hi0_ns; + always @(*) mmcm_hi0_ns = ~first_rising_ps_clk_r || ~mmcm_hi0_r; + + reg poc_sample_pd_ns, poc_sample_pd_r; + always @(*) poc_sample_pd_ns = inv_poc_sample_ns ^ mmcm_hi0_r; + always @(posedge clk) poc_sample_pd_r <= #TCQ poc_sample_pd_ns; + assign poc_sample_pd = poc_sample_pd_r; + + //*************************************************************************** + // Make sure logic acheives 90 degree setup time from rising mmcm_ps_clk + // to the appropriate edge of fabric clock + //*************************************************************************** + + //synthesis translate_off + generate + if ( tCK <= 2500 ) begin : check_ocal_timing + localparam CLK_PERIOD_PS = MMCM_VCO_PERIOD * MMCM_MULT_F; + localparam integer CLK_PERIOD_PS_DIV4 = CLK_PERIOD_PS/4; + + time rising_mmcm_ps_clk; + always @(posedge mmcm_ps_clk) rising_mmcm_ps_clk = $time(); + + time pdiff; // Not used, except in waveform plots. + always @(posedge clk) pdiff = $time() - rising_mmcm_ps_clk; + end + endgenerate + + //synthesis translate_on + + //*************************************************************************** + // RESET SYNCHRONIZATION DESCRIPTION: + // Various resets are generated to ensure that: + // 1. All resets are synchronously deasserted with respect to the clock + // domain they are interfacing to. There are several different clock + // domains - each one will receive a synchronized reset. + // 2. The reset deassertion order starts with deassertion of SYS_RST, + // followed by deassertion of resets for various parts of the design + // (see "RESET ORDER" below) based on the lock status of PLLE2s. + // RESET ORDER: + // 1. User deasserts SYS_RST + // 2. Reset PLLE2 and IDELAYCTRL + // 3. Wait for PLLE2 and IDELAYCTRL to lock + // 4. Release reset for all I/O primitives and internal logic + // OTHER NOTES: + // 1. Asynchronously assert reset. This way we can assert reset even if + // there is no clock (needed for things like 3-stating output buffers + // to prevent initial bus contention). Reset deassertion is synchronous. + //*************************************************************************** + + //***************************************************************** + // CLKDIV logic reset + //***************************************************************** + + // Wait for PLLE2 and IDELAYCTRL to lock before releasing reset + + // current O,25.0 unisim phaser_ref never locks. Need to find out why . + generate + if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_300_400 + assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[1] | + ~ref_dll_lock | ~MMCM_Locked_i; + end else begin: rst_tmp_200 + assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[0] | + ~ref_dll_lock | ~MMCM_Locked_i; + end + endgenerate + + always @(posedge clk_bufg or posedge rst_tmp) begin + if (rst_tmp) begin + rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; + rstdiv0_sync_r1 <= #TCQ 1'b1 ; + end else begin + rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1; + rstdiv0_sync_r1 <= #TCQ rstdiv0_sync_r[RST_DIV_SYNC_NUM-2]; + end + end + + assign rstdiv0 = rstdiv0_sync_r1 ; + +//IDDR rest + always @(posedge mmcm_ps_clk or posedge rst_tmp) begin + if (rst_tmp) begin + rst_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; + rst_sync_r1 <= #TCQ 1'b1 ; + end else begin + rst_sync_r <= #TCQ rst_sync_r << 1; + rst_sync_r1 <= #TCQ rst_sync_r[RST_DIV_SYNC_NUM-2]; + end + end + + assign iddr_rst = rst_sync_r1 ; + +// Sync reset in the clk_div2 domain + always @(posedge clk_div2 or posedge rst_tmp) begin + if (rst_tmp) begin + rstdiv2_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; + rstdiv2_sync_r1 <= #TCQ 1'b1 ; + end else begin + rstdiv2_sync_r <= #TCQ rstdiv2_sync_r << 1; + rstdiv2_sync_r1 <= #TCQ rstdiv2_sync_r[RST_DIV_SYNC_NUM-2]; + end + end + + assign rst_div2 = rstdiv2_sync_r1 ; + + generate + if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_phaser_ref_300_400 + assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[1]; + end else begin: rst_tmp_phaser_ref_200 + assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[0]; + end + endgenerate + + always @(posedge clk_bufg or posedge rst_tmp_phaser_ref) + if (rst_tmp_phaser_ref) + rst_phaser_ref_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}}; + else + rst_phaser_ref_sync_r <= #TCQ rst_phaser_ref_sync_r << 1; + + assign rst_phaser_ref = rst_phaser_ref_sync_r[RST_DIV_SYNC_NUM-1]; + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_iodelay_ctrl.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_iodelay_ctrl.v new file mode 100644 index 0000000..ec50367 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_iodelay_ctrl.v @@ -0,0 +1,355 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: iodelay_ctrl.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ +// \ \ / \ Date Created: Wed Aug 16 2006 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// This module instantiates the IDELAYCTRL primitive, which continously +// calibrates the IODELAY elements in the region to account for varying +// environmental conditions. A 200MHz or 300MHz reference clock (depending +// on the desired IODELAY tap resolution) must be supplied +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ +**$Date: 2011/06/02 08:34:56 $ +**$Author: mishra $ +**$Revision: 1.1 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_0_iodelay_ctrl # + ( + parameter TCQ = 100, + // clk->out delay (sim only) + parameter IODELAY_GRP0 = "IODELAY_MIG0", + // May be assigned unique name when + // multiple IP cores used in design + parameter IODELAY_GRP1 = "IODELAY_MIG1", + // May be assigned unique name when + // multiple IP cores used in design + parameter REFCLK_TYPE = "DIFFERENTIAL", + // Reference clock type + // "DIFFERENTIAL","SINGLE_ENDED" + // NO_BUFFER, USE_SYSTEM_CLOCK + parameter SYSCLK_TYPE = "DIFFERENTIAL", + // input clock type + // DIFFERENTIAL, SINGLE_ENDED, + // NO_BUFFER + parameter SYS_RST_PORT = "FALSE", + // "TRUE" - if pin is selected for sys_rst + // and IBUF will be instantiated. + // "FALSE" - if pin is not selected for sys_rst + parameter RST_ACT_LOW = 1, + // Reset input polarity + // (0 = active high, 1 = active low) + parameter DIFF_TERM_REFCLK = "TRUE", + // Differential Termination + parameter FPGA_SPEED_GRADE = 1, + // FPGA speed grade + parameter REF_CLK_MMCM_IODELAY_CTRL = "FALSE" + ) + ( + input clk_ref_p, + input clk_ref_n, + input clk_ref_i, + input sys_rst, + output [1:0] clk_ref, + output sys_rst_o, + output [1:0] iodelay_ctrl_rdy + ); + + // # of clock cycles to delay deassertion of reset. Needs to be a fairly + // high number not so much for metastability protection, but to give time + // for reset (i.e. stable clock cycles) to propagate through all state + // machines and to all control signals (i.e. not all control signals have + // resets, instead they rely on base state logic being reset, and the effect + // of that reset propagating through the logic). Need this because we may not + // be getting stable clock cycles while reset asserted (i.e. since reset + // depends on DCM lock status) + // COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger # + localparam RST_SYNC_NUM = 15; + // localparam RST_SYNC_NUM = 25; + + wire clk_ref_ibufg; + wire clk_ref_mmcm_300; + wire clk_ref_mmcm_400; + wire mmcm_clkfbout; + wire mmcm_Locked; + wire [1:0] rst_ref; + reg [RST_SYNC_NUM-1:0] rst_ref_sync_r [1:0] /* synthesis syn_maxfan = 10 */; + wire rst_tmp_idelay; + wire sys_rst_act_hi; + + //*************************************************************************** + + // If the pin is selected for sys_rst in GUI, IBUF will be instantiated. + // If the pin is not selected in GUI, sys_rst signal is expected to be + // driven internally. + generate + if (SYS_RST_PORT == "TRUE") + IBUF u_sys_rst_ibuf + ( + .I (sys_rst), + .O (sys_rst_o) + ); + else + assign sys_rst_o = sys_rst; + endgenerate + + // Possible inversion of system reset as appropriate + assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o; + + //*************************************************************************** + // 1) Input buffer for IDELAYCTRL reference clock - handle either a + // differential or single-ended input. Global clock buffer is used to + // drive the rest of FPGA logic. + // 2) For NO_BUFFER option, Reference clock will be driven from internal + // clock i.e., clock is driven from fabric. Input buffers and Global + // clock buffers will not be instaitaed. + // 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used + // as the input reference clock. Global clock buffer is used to drive + // the rest of FPGA logic. + //*************************************************************************** + + generate + if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref + IBUFGDS # + ( + .DIFF_TERM (DIFF_TERM_REFCLK), + .IBUF_LOW_PWR ("FALSE") + ) + u_ibufg_clk_ref + ( + .I (clk_ref_p), + .IB (clk_ref_n), + .O (clk_ref_ibufg) + ); + + end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref + IBUFG # + ( + .IBUF_LOW_PWR ("FALSE") + ) + u_ibufg_clk_ref + ( + .I (clk_ref_i), + .O (clk_ref_ibufg) + ); + + end else if ((REFCLK_TYPE == "NO_BUFFER") || + (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf + assign clk_ref_ibufg = clk_ref_i; + end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf + assign clk_ref_ibufg = clk_ref_i; + end + endgenerate + + // reference clock 300MHz and 400MHz generation with MMCM + generate + if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: clk_ref_mmcm_gen + + MMCME2_ADV + #(.BANDWIDTH ("HIGH"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("INTERNAL"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (6), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (4), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (3), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (5), + .REF_JITTER1 (0.000)) + mmcm_i + // Output clocks + (.CLKFBOUT (mmcm_clkfbout), + .CLKFBOUTB (), + .CLKOUT0 (clk_ref_mmcm_300), + .CLKOUT0B (), + .CLKOUT1 (clk_ref_mmcm_400), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (mmcm_clkfbout), + .CLKIN1 (clk_ref_ibufg), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (mmcm_Locked), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (sys_rst_act_hi)); + end + endgenerate + + generate + if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin : clk_ref_300_400_en + if(FPGA_SPEED_GRADE == 1) begin: clk_ref_300 + BUFG u_bufg_clk_ref_300 + ( + .O (clk_ref[1]), + .I (clk_ref_mmcm_300) + ); + end else if (FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) begin: clk_ref_400 + BUFG u_bufg_clk_ref_400 + ( + .O (clk_ref[1]), + .I (clk_ref_mmcm_400) + ); + end + end + endgenerate + + generate + if ((REFCLK_TYPE == "DIFFERENTIAL") || + (REFCLK_TYPE == "SINGLE_ENDED") || + (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER")) begin: clk_ref_200 + BUFG u_bufg_clk_ref + ( + .O (clk_ref[0]), + .I (clk_ref_ibufg) + ); + end else begin: clk_ref_200_no_buffer + assign clk_ref[0] = clk_ref_i; + end + endgenerate + + //***************************************************************** + // IDELAYCTRL reset + // This assumes an external clock signal driving the IDELAYCTRL + // blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL + // lock signal will need to be incorporated in this. + //***************************************************************** + + // Add PLL lock if PLL drives IDELAYCTRL in user design + assign rst_tmp_idelay = sys_rst_act_hi; + + generate + if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: rst_ref_gen_1 + always @(posedge clk_ref[1] or posedge rst_tmp_idelay) + if (rst_tmp_idelay) + rst_ref_sync_r[1] <= #TCQ {RST_SYNC_NUM{1'b1}}; + else + rst_ref_sync_r[1] <= #TCQ rst_ref_sync_r[1] << 1; + + assign rst_ref[1] = rst_ref_sync_r[1][RST_SYNC_NUM-1]; + end + endgenerate + + always @(posedge clk_ref[0] or posedge rst_tmp_idelay) + if (rst_tmp_idelay) + rst_ref_sync_r[0] <= #TCQ {RST_SYNC_NUM{1'b1}}; + else + rst_ref_sync_r[0] <= #TCQ rst_ref_sync_r[0] << 1; + + assign rst_ref[0] = rst_ref_sync_r[0][RST_SYNC_NUM-1]; + + //***************************************************************** + + generate + if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: idelayctrl_gen_1 + (* IODELAY_GROUP = IODELAY_GRP1 *) IDELAYCTRL u_idelayctrl_300_400 + ( + .RDY (iodelay_ctrl_rdy[1]), + .REFCLK (clk_ref[1]), + .RST (rst_ref[1]) + ); + end + endgenerate + + (* IODELAY_GROUP = IODELAY_GRP0 *) IDELAYCTRL u_idelayctrl_200 + ( + .RDY (iodelay_ctrl_rdy[0]), + .REFCLK (clk_ref[0]), + .RST (rst_ref[0]) + ); + +endmodule diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_cc.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_cc.v new file mode 100644 index 0000000..cac0016 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_cc.v @@ -0,0 +1,203 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: mig_7series_v4_0_poc_cc.v +// /___/ /\ Date Last Modified: $$ +// \ \ / \ Date Created:Tue 20 Jan 2014 +// \___\/\___\ +// +//Device: Virtex-7 +//Design Name: DDR3 SDRAM +//Purpose: Phaser out characterization and control. Logic to interface with +// Chipscope and control. Intended to support real time observation. Largely +// not generated for production implementations. +// +// Also generates debug bus. Concept is a dynamic portion that can be used +// to examine the POC while it is operating, and a logging portion that +// stores per lane results. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_0_poc_cc # + (parameter TCQ = 100, + parameter CCENABLE = 0, + parameter LANE_CNT_WIDTH = 2, + parameter PCT_SAMPS_SOLID = 95, + parameter SAMPCNTRWIDTH = 8, + parameter SAMPLES = 128, + parameter SMWIDTH = 2, + parameter TAPCNTRWIDTH = 7) + (/*AUTOARG*/ + // Outputs + samples, samps_solid_thresh, poc_error, dbg_poc, + // Inputs + psen, clk, rst, ktap_at_right_edge, ktap_at_left_edge, + mmcm_lbclk_edge_aligned, mmcm_edge_detect_done, fall_lead_right, + fall_trail_right, rise_lead_right, rise_trail_right, fall_lead_left, + fall_trail_left, rise_lead_left, rise_trail_left, fall_lead_center, + fall_trail_center, rise_lead_center, rise_trail_center, lane, + mmcm_edge_detect_rdy, poc_backup, sm, tap, run, run_end, + run_polarity, run_too_small, samp_cntr, samps_hi, samps_hi_held, + samps_zero, samps_one, run_ends, diff, left, right, window_center, + edge_center + ); + + // Remember SAMPLES is whole number counting. Zero corresponds to one sample. + localparam integer SAMPS_SOLID_THRESH = (SAMPLES+1) * PCT_SAMPS_SOLID * 0.01; + + output [SAMPCNTRWIDTH:0] samples, samps_solid_thresh; + input psen; + + input clk, rst; + input ktap_at_right_edge, ktap_at_left_edge; + + input mmcm_lbclk_edge_aligned; + wire reset_aligned_cnt = rst || ktap_at_right_edge || ktap_at_left_edge || mmcm_lbclk_edge_aligned; + + input mmcm_edge_detect_done; + reg mmcm_edge_detect_done_r; + always @(posedge clk) mmcm_edge_detect_done_r <= #TCQ mmcm_edge_detect_done; + wire done = mmcm_edge_detect_done && ~mmcm_edge_detect_done_r; + + + reg [6:0] aligned_cnt_r; + wire [6:0] aligned_cnt_ns = reset_aligned_cnt ? 7'b0 : aligned_cnt_r + {6'b0, done}; + always @(posedge clk) aligned_cnt_r <= #TCQ aligned_cnt_ns; + + reg poc_error_r; + wire poc_error_ns = ~rst && (aligned_cnt_r[6] || poc_error_r); + always @(posedge clk) poc_error_r <= #TCQ poc_error_ns; + output poc_error; + assign poc_error = poc_error_r; + + input [TAPCNTRWIDTH-1:0] fall_lead_right, fall_trail_right, rise_lead_right, rise_trail_right; + input [TAPCNTRWIDTH-1:0] fall_lead_left, fall_trail_left, rise_lead_left, rise_trail_left; + input [TAPCNTRWIDTH-1:0] fall_lead_center, fall_trail_center, rise_lead_center, rise_trail_center; + + + generate if (CCENABLE == 0) begin : no_characterization + assign samples = SAMPLES[SAMPCNTRWIDTH:0]; + assign samps_solid_thresh = SAMPS_SOLID_THRESH[SAMPCNTRWIDTH:0]; + end else begin : characterization + end endgenerate + + reg [1023:0] dbg_poc_r; + output [1023:0] dbg_poc; + assign dbg_poc = dbg_poc_r; + input [LANE_CNT_WIDTH-1:0] lane; + + input mmcm_edge_detect_rdy; + input poc_backup; + input [SMWIDTH-1:0] sm; + input [TAPCNTRWIDTH-1:0] tap; + input [TAPCNTRWIDTH-1:0] run; + input run_end; + input run_polarity; + input run_too_small; + input [SAMPCNTRWIDTH-1:0] samp_cntr; + input [SAMPCNTRWIDTH:0] samps_hi; + input [SAMPCNTRWIDTH:0] samps_hi_held; + input samps_zero, samps_one; + input [1:0] run_ends; + input [TAPCNTRWIDTH+1:0] diff; + + always @(*) begin + dbg_poc_r[99:0] = 'b0; + dbg_poc_r[1023:900] = 'b0; + dbg_poc_r[0] = mmcm_edge_detect_rdy; + dbg_poc_r[1] = mmcm_edge_detect_done; + dbg_poc_r[2] = ktap_at_right_edge; + dbg_poc_r[3] = ktap_at_left_edge; + dbg_poc_r[4] = mmcm_lbclk_edge_aligned; + dbg_poc_r[5] = poc_backup; + dbg_poc_r[6+:SMWIDTH] = sm; + dbg_poc_r[10+:TAPCNTRWIDTH] = tap; + dbg_poc_r[20+:TAPCNTRWIDTH] = run; + dbg_poc_r[30] = run_end; + dbg_poc_r[31] = run_polarity; + dbg_poc_r[32] = run_too_small; + dbg_poc_r[33+:SAMPCNTRWIDTH] = samp_cntr; + dbg_poc_r[49+:SAMPCNTRWIDTH+1] = samps_hi; + dbg_poc_r[66+:SAMPCNTRWIDTH+1] = samps_hi_held; + dbg_poc_r[83] = samps_zero; + dbg_poc_r[84] = samps_one; + dbg_poc_r[86:85] = run_ends; + dbg_poc_r[87+:TAPCNTRWIDTH+2] = diff; + end // always @ (*) + + input [TAPCNTRWIDTH-1:0] left, right; + input [TAPCNTRWIDTH:0] window_center, edge_center; + + reg [899:100] dbg_poc_ns; + always @(posedge clk) dbg_poc_r[899:100] <= #TCQ dbg_poc_ns; + + always @(*) begin + if (rst) dbg_poc_ns = 'b0; + else begin + dbg_poc_ns = dbg_poc_r[899:100]; + if (mmcm_edge_detect_rdy && lane < 8) begin + dbg_poc_ns[(lane+1)*100] = poc_backup; + dbg_poc_ns[(lane+1)*100+1] = dbg_poc_ns[(lane+1)*100+1] || run_too_small; + dbg_poc_ns[(lane+1)*100+10+:TAPCNTRWIDTH] = left; + dbg_poc_ns[(lane+1)*100+20+:TAPCNTRWIDTH] = right; + dbg_poc_ns[(lane+1)*100+30+:TAPCNTRWIDTH+1] = window_center; + dbg_poc_ns[(lane+1)*100+41+:TAPCNTRWIDTH+1] = edge_center; + end + end + end + +endmodule // mig_7series_v4_0_poc_cc diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_edge_store.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_edge_store.v new file mode 100644 index 0000000..2f25193 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_edge_store.v @@ -0,0 +1,117 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: mig_7series_v4_0_poc_meta.v +// /___/ /\ Date Last Modified: $$ +// \ \ / \ Date Created:Fri 24 Jan 2014 +// \___\/\___\ +// +//Device: Virtex-7 +//Design Name: DDR3 SDRAM +//Purpose: Phaser output calibration edge store. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_0_poc_edge_store # + (parameter TCQ = 100, + parameter TAPCNTRWIDTH = 7, + parameter TAPSPERKCLK = 112) + (/*AUTOARG*/ + // Outputs + fall_lead, fall_trail, rise_lead, rise_trail, + // Inputs + clk, run_polarity, run_end, select0, select1, tap, run + ); + + input clk; + + input run_polarity; + input run_end; + input select0; + input select1; + input [TAPCNTRWIDTH-1:0] tap; + input [TAPCNTRWIDTH-1:0] run; + + wire [TAPCNTRWIDTH:0] trailing_edge = run > tap ? tap + TAPSPERKCLK[TAPCNTRWIDTH-1:0] - run + : tap - run; + + wire run_end_this = run_end && select0 && select1; + + reg [TAPCNTRWIDTH-1:0] fall_lead_r, fall_trail_r, rise_lead_r, rise_trail_r; + output [TAPCNTRWIDTH-1:0] fall_lead, fall_trail, rise_lead, rise_trail; + assign fall_lead = fall_lead_r; + assign fall_trail = fall_trail_r; + assign rise_lead = rise_lead_r; + assign rise_trail = rise_trail_r; + + wire [TAPCNTRWIDTH-1:0] fall_lead_ns = run_end_this & run_polarity ? tap : fall_lead_r; + wire [TAPCNTRWIDTH-1:0] rise_trail_ns = run_end_this & run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0] + : rise_trail_r; + wire [TAPCNTRWIDTH-1:0] rise_lead_ns = run_end_this & ~run_polarity ? tap : rise_lead_r; + wire [TAPCNTRWIDTH-1:0] fall_trail_ns = run_end_this & ~run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0] + : fall_trail_r; + + always @(posedge clk) fall_lead_r <= #TCQ fall_lead_ns; + always @(posedge clk) fall_trail_r <= #TCQ fall_trail_ns; + always @(posedge clk) rise_lead_r <= #TCQ rise_lead_ns; + always @(posedge clk) rise_trail_r <= #TCQ rise_trail_ns; + +endmodule // mig_7series_v4_0_poc_edge_store + +// Local Variables: +// verilog-library-directories:(".") +// verilog-library-extensions:(".v") +// End: diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_meta.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_meta.v new file mode 100644 index 0000000..6e3490c --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_meta.v @@ -0,0 +1,302 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: mig_7series_v4_0_poc_meta.v +// /___/ /\ Date Last Modified: $$ +// \ \ / \ Date Created:Tue 15 Jan 2014 +// \___\/\___\ +// +//Device: Virtex-7 +//Design Name: DDR3 SDRAM +//Purpose: Phaser output calibration meta controller. +// +// Compute center of the window set up with with the ktap_left, +// ktap_right dance (hereafter "the window"). Also compute center of the +// edge (hereafter "the edge") to be aligned in the center +// of this window. +// +// Following the ktap_left/right dance, the to be centered edge is +// always left at the right edge of the window +// if SCANFROMRIGHT == 1, and the left edge otherwise. +// +// An assumption is the rise(0) case has a window wider than the noise on the +// edge. The noise case with the possibly narrow window +// will always be shifted by 90. And the fall(180) case is shifted by +// 90 twice. Hence when we start, we can assume the center of the +// edge is to the right/left of the the window center. +// +// The actual hardware does not necessarily monotonically appear to +// move the window centers. Because of noise, it is possible for the +// centered edge to move opposite the expected direction with a tap increment. +// +// This problem is solved by computing the absolute difference between +// the centers and the circular distance between the centers. These will +// be the same until the difference transits through zero. Then the circular +// difference will jump to almost the value of TAPSPERKCLK. +// +// The window center computation is done at 1/2 tap increments to maintain +// resolution through the divide by 2 for centering. +// +// There is a corner case of when the shift is greater than 180 degress. In +// this case the absolute difference and the circular difference will be +// unequal at the beginning of the alignment. This is solved by latching +// if they are equal at the end of each cycle. The completion must see +// that they were equal in the previous cycle, but are not equal in this cycle. +// +// Since the phaser out steps are of unknown size, it is possible to overshoot +// the center. The previous difference is recorded and if its less than the current +// difference, poc_backup is driven high. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_0_poc_meta # + (parameter SCANFROMRIGHT = 0, + parameter TCQ = 100, + parameter TAPCNTRWIDTH = 7, + parameter TAPSPERKCLK = 112) + (/*AUTOARG*/ + // Outputs + run_ends, mmcm_edge_detect_done, edge_center, left, right, + window_center, diff, poc_backup, mmcm_lbclk_edge_aligned, + // Inputs + rst, clk, mmcm_edge_detect_rdy, run_too_small, run, run_end, + run_polarity, rise_lead_right, rise_trail_left, rise_lead_center, + rise_trail_center, rise_trail_right, rise_lead_left, ninety_offsets, + use_noise_window, ktap_at_right_edge, ktap_at_left_edge + ); + + localparam NINETY = TAPSPERKCLK/4; + + function [TAPCNTRWIDTH-1:0] offset (input [TAPCNTRWIDTH-1:0] a, + input [1:0] b, + input integer base); + integer offset_ii; + begin + offset_ii = (a + b * NINETY) < base + ? (a + b * NINETY) + : (a + b * NINETY - base); + offset = offset_ii[TAPCNTRWIDTH-1:0]; + end + endfunction // offset + + function [TAPCNTRWIDTH-1:0] mod_sub (input [TAPCNTRWIDTH-1:0] a, + input [TAPCNTRWIDTH-1:0] b, + input integer base); + begin + mod_sub = (a>=b) ? a-b : a+base-b; + end + endfunction // mod_sub + + function [TAPCNTRWIDTH:0] center (input [TAPCNTRWIDTH-1:0] left, + input [TAPCNTRWIDTH-1:0] diff, + input integer base); + integer center_ii; + begin + center_ii = ({left, 1'b0} + diff < base * 2) + ? {left, 1'b0} + diff + 32'h0 + : {left, 1'b0} + diff - base * 2; + center = center_ii[TAPCNTRWIDTH:0]; + end + endfunction // center + + input rst; + input clk; + + + input mmcm_edge_detect_rdy; + + reg [1:0] run_ends_r; + + input run_too_small; + reg run_too_small_r1, run_too_small_r2, run_too_small_r3; + + always @ (posedge clk) run_too_small_r1 <= #TCQ run_too_small & (run_ends_r == 'd1); //align with run_end_r1; + always @ (posedge clk) run_too_small_r2 <= #TCQ run_too_small_r1; + always @ (posedge clk) run_too_small_r3 <= #TCQ run_too_small_r2; + + wire reset_run_ends = rst || ~mmcm_edge_detect_rdy || run_too_small_r3 ; + + // This input used only for the SVA. + input [TAPCNTRWIDTH-1:0] run; + + input run_end; + reg run_end_r, run_end_r1, run_end_r2, run_end_r3; + always @(posedge clk) run_end_r <= #TCQ run_end; + always @(posedge clk) run_end_r1 <= #TCQ run_end_r; + always @(posedge clk) run_end_r2 <= #TCQ run_end_r1; + always @(posedge clk) run_end_r3 <= #TCQ run_end_r2; + + input run_polarity; + reg run_polarity_held_ns, run_polarity_held_r; + always @(posedge clk) run_polarity_held_r <= #TCQ run_polarity_held_ns; + always @(*) run_polarity_held_ns = run_end ? run_polarity : run_polarity_held_r; + + reg [1:0] run_ends_ns; + always @(posedge clk) run_ends_r <= #TCQ run_ends_ns; + always @(*) begin + run_ends_ns = run_ends_r; + if (reset_run_ends) run_ends_ns = 2'b0; + else case (run_ends_r) + 2'b00 : run_ends_ns = run_ends_r + {1'b0, run_end_r3 && run_polarity_held_r}; + 2'b01, 2'b10 : run_ends_ns = run_ends_r + {1'b0, run_end_r3}; + endcase // case (run_ends_r) + end // always @ begin + output [1:0] run_ends; + assign run_ends = run_ends_r; + + reg done_r; + wire done_ns = mmcm_edge_detect_rdy && &run_ends_r; + always @(posedge clk) done_r <= #TCQ done_ns; + output mmcm_edge_detect_done; + assign mmcm_edge_detect_done = done_r; + + input [TAPCNTRWIDTH-1:0] rise_lead_right; + input [TAPCNTRWIDTH-1:0] rise_trail_left; + input [TAPCNTRWIDTH-1:0] rise_lead_center; + input [TAPCNTRWIDTH-1:0] rise_trail_center; + input [TAPCNTRWIDTH-1:0] rise_trail_right; + input [TAPCNTRWIDTH-1:0] rise_lead_left; + + input [1:0] ninety_offsets; + wire [1:0] offsets = SCANFROMRIGHT == 1 ? ninety_offsets : 2'b00 - ninety_offsets; + + wire [TAPCNTRWIDTH-1:0] rise_lead_center_offset_ns = offset(rise_lead_center, offsets, TAPSPERKCLK); + wire [TAPCNTRWIDTH-1:0] rise_trail_center_offset_ns = offset(rise_trail_center, offsets, TAPSPERKCLK); + reg [TAPCNTRWIDTH-1:0] rise_lead_center_offset_r, rise_trail_center_offset_r; + always @(posedge clk) rise_lead_center_offset_r <= #TCQ rise_lead_center_offset_ns; + always @(posedge clk) rise_trail_center_offset_r <= #TCQ rise_trail_center_offset_ns; + + wire [TAPCNTRWIDTH-1:0] edge_diff_ns = mod_sub(rise_trail_center_offset_r, rise_lead_center_offset_r, TAPSPERKCLK); + reg [TAPCNTRWIDTH-1:0] edge_diff_r; + always @(posedge clk) edge_diff_r <= #TCQ edge_diff_ns; + + wire [TAPCNTRWIDTH:0] edge_center_ns = center(rise_lead_center_offset_r, edge_diff_r, TAPSPERKCLK); + reg [TAPCNTRWIDTH:0] edge_center_r; + always @(posedge clk) edge_center_r <= #TCQ edge_center_ns; + output [TAPCNTRWIDTH:0] edge_center; + assign edge_center = edge_center_r; + + input use_noise_window; + output [TAPCNTRWIDTH-1:0] left, right; + assign left = use_noise_window ? rise_lead_left : rise_trail_left; + assign right = use_noise_window ? rise_trail_right : rise_lead_right; + + wire [TAPCNTRWIDTH-1:0] center_diff_ns = mod_sub(right, left, TAPSPERKCLK); + reg [TAPCNTRWIDTH-1:0] center_diff_r; + always @(posedge clk) center_diff_r <= #TCQ center_diff_ns; + + wire [TAPCNTRWIDTH:0] window_center_ns = center(left, center_diff_r, TAPSPERKCLK); + reg [TAPCNTRWIDTH:0] window_center_r; + always @(posedge clk) window_center_r <= #TCQ window_center_ns; + output [TAPCNTRWIDTH:0] window_center; + assign window_center = window_center_r; + + localparam TAPSPERKCLKX2 = TAPSPERKCLK * 2; + + wire [TAPCNTRWIDTH+1:0] left_center = {1'b0, SCANFROMRIGHT == 1 ? window_center_r : edge_center_r}; + wire [TAPCNTRWIDTH+1:0] right_center = {1'b0, SCANFROMRIGHT == 1 ? edge_center_r : window_center_r}; + + wire [TAPCNTRWIDTH+1:0] diff_ns = right_center >= left_center + ? right_center - left_center + : right_center + TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - left_center; + + reg [TAPCNTRWIDTH+1:0] diff_r; + always @(posedge clk) diff_r <= #TCQ diff_ns; + output [TAPCNTRWIDTH+1:0] diff; + assign diff = diff_r; + + wire [TAPCNTRWIDTH+1:0] abs_diff = diff_r > TAPSPERKCLKX2[TAPCNTRWIDTH+1:0]/2 + ? TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - diff_r + : diff_r; + + reg [TAPCNTRWIDTH+1:0] prev_ns, prev_r; + always @(posedge clk) prev_r <= #TCQ prev_ns; + always @(*) prev_ns = done_ns ? diff_r : prev_r; + + input ktap_at_right_edge; + input ktap_at_left_edge; + + wire centering = !(ktap_at_right_edge || ktap_at_left_edge); + wire diffs_eq = abs_diff == diff_r; + reg diffs_eq_ns, diffs_eq_r; + always @(*) diffs_eq_ns = centering && ((done_r && done_ns) ? diffs_eq : diffs_eq_r); + always @(posedge clk) diffs_eq_r <= #TCQ diffs_eq_ns; + + reg edge_aligned_r; + reg prev_valid_ns, prev_valid_r; + always @(posedge clk) prev_valid_r <= #TCQ prev_valid_ns; + always @(*) prev_valid_ns = (~rst && ~ktap_at_right_edge && ~ktap_at_left_edge && ~edge_aligned_r) && prev_valid_r | done_ns; + + wire indicate_alignment = ~rst && centering && done_ns; + wire edge_aligned_ns = indicate_alignment && (~|diff_r || ~diffs_eq & diffs_eq_r); + always @(posedge clk) edge_aligned_r <= #TCQ edge_aligned_ns; + + reg poc_backup_r; + wire poc_backup_ns = edge_aligned_ns && abs_diff > prev_r; + always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns; + output poc_backup; + assign poc_backup = poc_backup_r; + + output mmcm_lbclk_edge_aligned; + assign mmcm_lbclk_edge_aligned = edge_aligned_r; + +endmodule // mig_7series_v4_0_poc_meta + +// Local Variables: +// verilog-library-directories:(".") +// verilog-library-extensions:(".v") +// End: diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_pd.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_pd.v new file mode 100644 index 0000000..6fd4667 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_pd.v @@ -0,0 +1,131 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: mig_7series_v4_0_poc_pd.v +// /___/ /\ Date Last Modified: $$ +// \ \ / \ Date Created:Tue 15 Jan 2014 +// \___\/\___\ +// +//Device: Virtex-7 +//Design Name: DDR3 SDRAM +//Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff +// prevents any noise that could happen when the phase shift clock is very +// nearly aligned to the fabric clock. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_0_poc_pd # + (parameter POC_USE_METASTABLE_SAMP = "FALSE", + parameter SIM_CAL_OPTION = "NONE", + parameter TCQ = 100) + (/*AUTOARG*/ + // Outputs + pd_out, + // Inputs + iddr_rst, clk, kclk, mmcm_ps_clk + ); + + input iddr_rst; + input clk; + input kclk; + input mmcm_ps_clk; + + wire q1; + IDDR # + (.DDR_CLK_EDGE ("OPPOSITE_EDGE"), + .INIT_Q1 (1'b0), + .INIT_Q2 (1'b0), + .SRTYPE ("SYNC")) + u_phase_detector + (.Q1 (q1), + .Q2 (), + .C (mmcm_ps_clk), + .CE (1'b1), + .D (kclk), + .R (iddr_rst), + .S (1'b0)); + + // Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME + + reg pos_edge_samp; + + generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes + always @(posedge clk) pos_edge_samp <= #TCQ q1; + end else begin : eXes + reg q1_delayed; + reg rising_clk_seen; + always @(posedge mmcm_ps_clk) begin + rising_clk_seen <= 1'b0; + q1_delayed <= 1'bx; + end + always @(posedge clk) begin + rising_clk_seen = 1'b1; + if (rising_clk_seen) q1_delayed <= q1; + end + always @(posedge clk) begin + pos_edge_samp <= q1_delayed; + end + end endgenerate + + reg pd_out_r; + always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp; + + output pd_out; + assign pd_out = pd_out_r; + + +endmodule // mic_7series_v4_0_poc_pd + diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_tap_base.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_tap_base.v new file mode 100644 index 0000000..56146db --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_tap_base.v @@ -0,0 +1,301 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: mig_7series_v4_0_poc_tap_base.v +// /___/ /\ Date Last Modified: $$ +// \ \ / \ Date Created:Tue 15 Jan 2014 +// \___\/\___\ +// +//Device: Virtex-7 +//Design Name: DDR3 SDRAM +//Purpose: All your taps are belong to us. +// +//In general, this block should be able to start up with a random initialization of +//the various counters. But its probably easier, more normative and quicker time to solution +//to just initialize to zero with rst. +// +// Following deassertion of reset, endlessly increments the MMCM delay with PSEN. For +// each MMCM tap it samples the phase detector output a programmable number of times. +// When the sampling count is achieved, PSEN is pulsed and sampling of the next MMCM +// tap begins. +// +// Following a PSEN, sampling pauses for MMCM_SAMP_WAIT clocks. This is workaround +// for a bug in the MMCM where its output may have noise for a period following +// the PSEN. +// +// Samples are taken every other fabric clock. This is because the MMCM phase shift +// clock operates at half the fabric clock. The reason for this is unknown. +// +// At the end of the sampling period, a filtering step is implemented. samps_solid_thresh +// is the minumum number of samples that must be seen to declare a solid zero or one. If +// neithr the one and zero samples cross this threshold, then the sampple is declared fuzz. +// +// A "run_polarity" bit is maintained. It is set appropriately whenever a solid sample +// is observed. +// +// A "run" counter is maintained. If the current sample is fuzz, or opposite polarity +// from a previous sample, then the run counter is reset. If the current sample is the +// same polarity run_polarity, then the run counter is incremented. +// +// If a run_polarity reversal or fuzz is observed and the run counter is not zero +// then the run_end strobe is pulsed. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_0_poc_tap_base # + (parameter MMCM_SAMP_WAIT = 10, + parameter POC_USE_METASTABLE_SAMP = "FALSE", + parameter TCQ = 100, + parameter SAMPCNTRWIDTH = 8, + parameter SMWIDTH = 2, + parameter TAPCNTRWIDTH = 7, + parameter TAPSPERKCLK = 112) + (/*AUTOARG*/ + // Outputs + psincdec, psen, run, run_end, run_too_small, run_polarity, + samp_cntr, samps_hi, samps_hi_held, tap, sm, samps_zero, samps_one, + // Inputs + pd_out, clk, samples, samps_solid_thresh, psdone, rst, + poc_sample_pd + ); + + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + input pd_out; + input clk; + input [SAMPCNTRWIDTH:0] samples, samps_solid_thresh; + input psdone; + input rst; + + localparam ONE = 1; + + localparam SAMP_WAIT_WIDTH = clogb2(MMCM_SAMP_WAIT); + reg [SAMP_WAIT_WIDTH-1:0] samp_wait_ns, samp_wait_r; + always @(posedge clk) samp_wait_r <= #TCQ samp_wait_ns; + + reg pd_out_r; + always @(posedge clk) pd_out_r <= #TCQ pd_out; + wire pd_out_sel = POC_USE_METASTABLE_SAMP == "TRUE" ? pd_out_r : pd_out; + + output psincdec; + assign psincdec = 1'b1; + output psen; + reg psen_int; + assign psen = psen_int; + + reg [TAPCNTRWIDTH-1:0] run_r; + reg [TAPCNTRWIDTH-1:0] run_ns; + always @(posedge clk) run_r <= #TCQ run_ns; + output [TAPCNTRWIDTH-1:0] run; + assign run = run_r; + + output run_end; + reg run_end_int; + assign run_end = run_end_int; + + output run_too_small; + reg run_too_small_r, run_too_small_ns; + always @(*) run_too_small_ns = run_end && (run < TAPSPERKCLK/4); + always @(posedge clk) run_too_small_r <= #TCQ run_too_small_ns; + assign run_too_small = run_too_small_r; + + reg run_polarity_r; + reg run_polarity_ns; + always @(posedge clk) run_polarity_r <= #TCQ run_polarity_ns; + output run_polarity; + assign run_polarity = run_polarity_r; + + reg [SAMPCNTRWIDTH-1:0] samp_cntr_r; + reg [SAMPCNTRWIDTH-1:0] samp_cntr_ns; + always @(posedge clk) samp_cntr_r <= #TCQ samp_cntr_ns; + output [SAMPCNTRWIDTH-1:0] samp_cntr; + assign samp_cntr = samp_cntr_r; + + reg [SAMPCNTRWIDTH:0] samps_hi_r; + reg [SAMPCNTRWIDTH:0] samps_hi_ns; + always @(posedge clk) samps_hi_r <= #TCQ samps_hi_ns; + output [SAMPCNTRWIDTH:0] samps_hi; + assign samps_hi = samps_hi_r; + + reg [SAMPCNTRWIDTH:0] samps_hi_held_r; + reg [SAMPCNTRWIDTH:0] samps_hi_held_ns; + always @(posedge clk) samps_hi_held_r <= #TCQ samps_hi_held_ns; + output [SAMPCNTRWIDTH:0] samps_hi_held; + assign samps_hi_held = samps_hi_held_r; + + reg [TAPCNTRWIDTH-1:0] tap_ns, tap_r; + always @(posedge clk) tap_r <= #TCQ tap_ns; + output [TAPCNTRWIDTH-1:0] tap; + assign tap = tap_r; + + reg [SMWIDTH-1:0] sm_ns; + reg [SMWIDTH-1:0] sm_r; + always @(posedge clk) sm_r <= #TCQ sm_ns; + output [SMWIDTH-1:0] sm; + assign sm = sm_r; + + reg samps_zero_ns, samps_zero_r, samps_one_ns, samps_one_r; + always @(posedge clk) samps_zero_r <= #TCQ samps_zero_ns; + always @(posedge clk) samps_one_r <= #TCQ samps_one_ns; + output samps_zero, samps_one; + assign samps_zero = samps_zero_r; + assign samps_one = samps_one_r; + + // Interesting corner case... what if both samps_zero and samps_one are + // hi? Could happen for small sample counts and reasonable values of + // PCT_SAMPS_SOLID. Doesn't affect samps_solid. run_polarity assignment + // consistently breaks tie with samps_one_r. + wire [SAMPCNTRWIDTH:0] samps_lo = samples + ONE[SAMPCNTRWIDTH:0] - samps_hi_r; + always @(*) begin + samps_zero_ns = samps_zero_r; + samps_one_ns = samps_one_r; + samps_zero_ns = samps_lo >= samps_solid_thresh; + samps_one_ns = samps_hi_r >= samps_solid_thresh; + end // always @ begin + wire new_polarity = run_polarity_ns ^ run_polarity_r; + + input poc_sample_pd; + + always @(*) begin + + if (rst == 1'b1) begin + + // RESET next states + psen_int = 1'b0; + sm_ns = /*AUTOLINK("SAMPLE")*/2'd0; + run_polarity_ns = 1'b0; + run_ns = {TAPCNTRWIDTH{1'b0}}; + run_end_int = 1'b0; + samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}}; + samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}}; + tap_ns = {TAPCNTRWIDTH{1'b0}}; + samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0]; + samps_hi_held_ns = {SAMPCNTRWIDTH+1{1'b0}}; + end else begin + + // Default next states; + psen_int = 1'b0; + sm_ns = sm_r; + run_polarity_ns = run_polarity_r; + run_ns = run_r; + run_end_int = 1'b0; + samp_cntr_ns = samp_cntr_r; + samps_hi_ns = samps_hi_r; + tap_ns = tap_r; + samp_wait_ns = samp_wait_r; + if (|samp_wait_r) samp_wait_ns = samp_wait_r - ONE[SAMP_WAIT_WIDTH-1:0]; + samps_hi_held_ns = samps_hi_held_r; + +// State based actions and next states. + case (sm_r) + /*AL("SAMPLE")*/2'd0: begin + if (~|samp_wait_r && poc_sample_pd | POC_USE_METASTABLE_SAMP == "TRUE") begin + if (POC_USE_METASTABLE_SAMP == "TRUE") samp_wait_ns = ONE[SAMP_WAIT_WIDTH-1:0]; + if ({1'b0, samp_cntr_r} == samples) sm_ns = /*AK("COMPUTE")*/2'd1; + samps_hi_ns = samps_hi_r + {{SAMPCNTRWIDTH{1'b0}}, pd_out_sel}; + samp_cntr_ns = samp_cntr_r + ONE[SAMPCNTRWIDTH-1:0]; + end + end + + /*AL("COMPUTE")*/2'd1:begin + sm_ns = /*AK("PSEN")*/2'd2; + end + + /*AL("PSEN")*/2'd2:begin + sm_ns = /*AK("PSDONE_WAIT")*/2'd3; + psen_int = 1'b1; + samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}}; + samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}}; + samps_hi_held_ns = samps_hi_r; + tap_ns = (tap_r < TAPSPERKCLK[TAPCNTRWIDTH-1:0] - ONE[TAPCNTRWIDTH-1:0]) + ? tap_r + ONE[TAPCNTRWIDTH-1:0] + : {TAPCNTRWIDTH{1'b0}}; + + if (run_polarity_r) begin + if (samps_zero_r) run_polarity_ns = 1'b0; + end else begin + if (samps_one_r) run_polarity_ns = 1'b1; + end + if (new_polarity) begin + run_ns ={TAPCNTRWIDTH{1'b0}}; + run_end_int = 1'b1; + end else run_ns = run_r + ONE[TAPCNTRWIDTH-1:0]; + end + + /*AL("PSDONE_WAIT")*/2'd3:begin + samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0] - ONE[SAMP_WAIT_WIDTH-1:0]; + if (psdone) sm_ns = /*AK("SAMPLE")*/2'd0; + end + + endcase // case (sm_r) + end // else: !if(rst == 1'b1) + end // always @ (*) + +endmodule // mig_7series_v4_0_poc_tap_base + +// Local Variables: +// verilog-library-directories:(".") +// verilog-library-extensions:(".v") +// verilog-autolabel-prefix: "2'd" +// End: diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_top.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_top.v new file mode 100644 index 0000000..ab75547 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_poc_top.v @@ -0,0 +1,370 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: mig_7series_v4_0_poc_top.v +// /___/ /\ Date Last Modified: $$ +// \ \ / \ Date Created:Tue 15 Jan 2014 +// \___\/\___\ +// +//Device: Virtex-7 +//Design Name: DDR3 SDRAM +//Purpose: Phaser out calibration top. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_0_poc_top # + (parameter LANE_CNT_WIDTH = 2, + parameter MMCM_SAMP_WAIT = 10, + parameter PCT_SAMPS_SOLID = 95, + parameter POC_USE_METASTABLE_SAMP = "FALSE", + parameter TCQ = 100, + parameter CCENABLE = 0, + parameter SCANFROMRIGHT = 0, + parameter SAMPCNTRWIDTH = 8, + parameter SAMPLES = 128, + parameter TAPCNTRWIDTH = 7, + parameter TAPSPERKCLK =112) + (/*AUTOARG*/ + // Outputs + psincdec, poc_error, dbg_poc, psen, rise_lead_right, + rise_trail_right, mmcm_edge_detect_done, mmcm_lbclk_edge_aligned, + poc_backup, + // Inputs + use_noise_window, rst, psdone, poc_sample_pd, pd_out, + ninety_offsets, mmcm_edge_detect_rdy, lane, ktap_at_right_edge, + ktap_at_left_edge, clk + ); + + localparam SMWIDTH = 2; + + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input clk; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v, ... + input ktap_at_left_edge; // To u_poc_meta of mig_7series_v4_0_poc_meta.v, ... + input ktap_at_right_edge; // To u_poc_meta of mig_7series_v4_0_poc_meta.v, ... + input [LANE_CNT_WIDTH-1:0] lane; // To u_poc_cc of mig_7series_v4_0_poc_cc.v + input mmcm_edge_detect_rdy; // To u_poc_meta of mig_7series_v4_0_poc_meta.v, ... + input [1:0] ninety_offsets; // To u_poc_meta of mig_7series_v4_0_poc_meta.v + input pd_out; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + input poc_sample_pd; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + input psdone; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + input rst; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v, ... + input use_noise_window; // To u_poc_meta of mig_7series_v4_0_poc_meta.v + // End of automatics + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [1023:0] dbg_poc; // From u_poc_cc of mig_7series_v4_0_poc_cc.v + output poc_error; // From u_poc_cc of mig_7series_v4_0_poc_cc.v + output psincdec; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + // End of automatics + /*AUTOwire*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [TAPCNTRWIDTH+1:0] diff; // From u_poc_meta of mig_7series_v4_0_poc_meta.v + wire [TAPCNTRWIDTH:0] edge_center; // From u_poc_meta of mig_7series_v4_0_poc_meta.v + wire [TAPCNTRWIDTH-1:0] fall_lead_center; // From u_edge_center of mig_7series_v4_0_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] fall_lead_left; // From u_edge_left of mig_7series_v4_0_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] fall_lead_right; // From u_edge_right of mig_7series_v4_0_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] fall_trail_center; // From u_edge_center of mig_7series_v4_0_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] fall_trail_left; // From u_edge_left of mig_7series_v4_0_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] fall_trail_right; // From u_edge_right of mig_7series_v4_0_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] left; // From u_poc_meta of mig_7series_v4_0_poc_meta.v + wire [TAPCNTRWIDTH-1:0] right; // From u_poc_meta of mig_7series_v4_0_poc_meta.v + wire [TAPCNTRWIDTH-1:0] rise_lead_center; // From u_edge_center of mig_7series_v4_0_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] rise_lead_left; // From u_edge_left of mig_7series_v4_0_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] rise_trail_center; // From u_edge_center of mig_7series_v4_0_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] rise_trail_left; // From u_edge_left of mig_7series_v4_0_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] run; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + wire run_end; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + wire [1:0] run_ends; // From u_poc_meta of mig_7series_v4_0_poc_meta.v + wire run_polarity; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + wire run_too_small; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + wire [SAMPCNTRWIDTH-1:0] samp_cntr; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + wire [SAMPCNTRWIDTH:0] samples; // From u_poc_cc of mig_7series_v4_0_poc_cc.v + wire [SAMPCNTRWIDTH:0] samps_hi; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + wire [SAMPCNTRWIDTH:0] samps_hi_held; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + wire samps_one; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + wire [SAMPCNTRWIDTH:0] samps_solid_thresh; // From u_poc_cc of mig_7series_v4_0_poc_cc.v + wire samps_zero; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + wire [SMWIDTH-1:0] sm; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + wire [TAPCNTRWIDTH-1:0] tap; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v + wire [TAPCNTRWIDTH:0] window_center; // From u_poc_meta of mig_7series_v4_0_poc_meta.v + // End of automatics + + output psen; + output [TAPCNTRWIDTH-1:0] rise_lead_right; + output [TAPCNTRWIDTH-1:0] rise_trail_right; + output mmcm_edge_detect_done; + output mmcm_lbclk_edge_aligned; + output poc_backup; + + mig_7series_v4_0_poc_tap_base # + (/*AUTOINSTPARAM*/ + // Parameters + .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), + .SAMPCNTRWIDTH (SAMPCNTRWIDTH), + .SMWIDTH (SMWIDTH), + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ)) + u_poc_tap_base + (/*AUTOINST*/ + // Outputs + .psen (psen), + .psincdec (psincdec), + .run (run[TAPCNTRWIDTH-1:0]), + .run_end (run_end), + .run_polarity (run_polarity), + .run_too_small (run_too_small), + .samp_cntr (samp_cntr[SAMPCNTRWIDTH-1:0]), + .samps_hi (samps_hi[SAMPCNTRWIDTH:0]), + .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), + .samps_one (samps_one), + .samps_zero (samps_zero), + .sm (sm[SMWIDTH-1:0]), + .tap (tap[TAPCNTRWIDTH-1:0]), + // Inputs + .clk (clk), + .pd_out (pd_out), + .poc_sample_pd (poc_sample_pd), + .psdone (psdone), + .rst (rst), + .samples (samples[SAMPCNTRWIDTH:0]), + .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0])); + + mig_7series_v4_0_poc_meta # + (/*AUTOINSTPARAM*/ + // Parameters + .SCANFROMRIGHT (SCANFROMRIGHT), + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ)) + u_poc_meta + (/*AUTOINST*/ + // Outputs + .diff (diff[TAPCNTRWIDTH+1:0]), + .edge_center (edge_center[TAPCNTRWIDTH:0]), + .left (left[TAPCNTRWIDTH-1:0]), + .mmcm_edge_detect_done (mmcm_edge_detect_done), + .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), + .poc_backup (poc_backup), + .right (right[TAPCNTRWIDTH-1:0]), + .run_ends (run_ends[1:0]), + .window_center (window_center[TAPCNTRWIDTH:0]), + // Inputs + .clk (clk), + .ktap_at_left_edge (ktap_at_left_edge), + .ktap_at_right_edge (ktap_at_right_edge), + .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), + .ninety_offsets (ninety_offsets[1:0]), + .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), + .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), + .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), + .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), + .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), + .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), + .rst (rst), + .run (run[TAPCNTRWIDTH-1:0]), + .run_end (run_end), + .run_polarity (run_polarity), + .run_too_small (run_too_small), + .use_noise_window (use_noise_window)); + + /*mig_7series_v4_0_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( + .\(.*\)lead (\1lead_@@"vl-bits"), + .\(.*\)trail (\1trail_@@"vl-bits"), + .select0 (ktap_at_@_edge), + .select1 (1'b1),)*/ + + mig_7series_v4_0_poc_edge_store # + (/*AUTOINSTPARAM*/ + // Parameters + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ)) + u_edge_right + (/*AUTOINST*/ + // Outputs + .fall_lead (fall_lead_right[TAPCNTRWIDTH-1:0]), // Templated + .fall_trail (fall_trail_right[TAPCNTRWIDTH-1:0]), // Templated + .rise_lead (rise_lead_right[TAPCNTRWIDTH-1:0]), // Templated + .rise_trail (rise_trail_right[TAPCNTRWIDTH-1:0]), // Templated + // Inputs + .clk (clk), + .run (run[TAPCNTRWIDTH-1:0]), + .run_end (run_end), + .run_polarity (run_polarity), + .select0 (ktap_at_right_edge), // Templated + .select1 (1'b1), // Templated + .tap (tap[TAPCNTRWIDTH-1:0])); + + mig_7series_v4_0_poc_edge_store # + (/*AUTOINSTPARAM*/ + // Parameters + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ)) + u_edge_left + (/*AUTOINST*/ + // Outputs + .fall_lead (fall_lead_left[TAPCNTRWIDTH-1:0]), // Templated + .fall_trail (fall_trail_left[TAPCNTRWIDTH-1:0]), // Templated + .rise_lead (rise_lead_left[TAPCNTRWIDTH-1:0]), // Templated + .rise_trail (rise_trail_left[TAPCNTRWIDTH-1:0]), // Templated + // Inputs + .clk (clk), + .run (run[TAPCNTRWIDTH-1:0]), + .run_end (run_end), + .run_polarity (run_polarity), + .select0 (ktap_at_left_edge), // Templated + .select1 (1'b1), // Templated + .tap (tap[TAPCNTRWIDTH-1:0])); + + wire not_ktap_at_right_edge = ~ktap_at_right_edge; + wire not_ktap_at_left_edge = ~ktap_at_left_edge; + /*mig_7series_v4_0_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( + .\(.*\)lead (\1lead_@@"vl-bits"), + .\(.*\)trail (\1trail_@@"vl-bits"), + .select0 (not_ktap_at_right_edge), + .select1 (not_ktap_at_left_edge),)*/ + + mig_7series_v4_0_poc_edge_store # + (/*AUTOINSTPARAM*/ + // Parameters + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ)) + u_edge_center + (/*AUTOINST*/ + // Outputs + .fall_lead (fall_lead_center[TAPCNTRWIDTH-1:0]), // Templated + .fall_trail (fall_trail_center[TAPCNTRWIDTH-1:0]), // Templated + .rise_lead (rise_lead_center[TAPCNTRWIDTH-1:0]), // Templated + .rise_trail (rise_trail_center[TAPCNTRWIDTH-1:0]), // Templated + // Inputs + .clk (clk), + .run (run[TAPCNTRWIDTH-1:0]), + .run_end (run_end), + .run_polarity (run_polarity), + .select0 (not_ktap_at_right_edge), // Templated + .select1 (not_ktap_at_left_edge), // Templated + .tap (tap[TAPCNTRWIDTH-1:0])); + + mig_7series_v4_0_poc_cc # + (/*AUTOINSTPARAM*/ + // Parameters + .CCENABLE (CCENABLE), + .LANE_CNT_WIDTH (LANE_CNT_WIDTH), + .PCT_SAMPS_SOLID (PCT_SAMPS_SOLID), + .SAMPCNTRWIDTH (SAMPCNTRWIDTH), + .SAMPLES (SAMPLES), + .SMWIDTH (SMWIDTH), + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TCQ (TCQ)) + u_poc_cc + (/*AUTOINST*/ + // Outputs + .dbg_poc (dbg_poc[1023:0]), + .poc_error (poc_error), + .samples (samples[SAMPCNTRWIDTH:0]), + .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0]), + // Inputs + .clk (clk), + .diff (diff[TAPCNTRWIDTH+1:0]), + .edge_center (edge_center[TAPCNTRWIDTH:0]), + .fall_lead_center (fall_lead_center[TAPCNTRWIDTH-1:0]), + .fall_lead_left (fall_lead_left[TAPCNTRWIDTH-1:0]), + .fall_lead_right (fall_lead_right[TAPCNTRWIDTH-1:0]), + .fall_trail_center (fall_trail_center[TAPCNTRWIDTH-1:0]), + .fall_trail_left (fall_trail_left[TAPCNTRWIDTH-1:0]), + .fall_trail_right (fall_trail_right[TAPCNTRWIDTH-1:0]), + .ktap_at_left_edge (ktap_at_left_edge), + .ktap_at_right_edge (ktap_at_right_edge), + .lane (lane[LANE_CNT_WIDTH-1:0]), + .left (left[TAPCNTRWIDTH-1:0]), + .mmcm_edge_detect_done (mmcm_edge_detect_done), + .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), + .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), + .poc_backup (poc_backup), + .psen (psen), + .right (right[TAPCNTRWIDTH-1:0]), + .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), + .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), + .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), + .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), + .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), + .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), + .rst (rst), + .run (run[TAPCNTRWIDTH-1:0]), + .run_end (run_end), + .run_ends (run_ends[1:0]), + .run_polarity (run_polarity), + .run_too_small (run_too_small), + .samp_cntr (samp_cntr[SAMPCNTRWIDTH-1:0]), + .samps_hi (samps_hi[SAMPCNTRWIDTH:0]), + .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), + .samps_one (samps_one), + .samps_zero (samps_zero), + .sm (sm[SMWIDTH-1:0]), + .tap (tap[TAPCNTRWIDTH-1:0]), + .window_center (window_center[TAPCNTRWIDTH:0])); + +endmodule // mig_7series_v4_0_poc_top + +// Local Variables: +// verilog-library-directories:(".") +// verilog-library-extensions:(".v") +// End: diff --git a/projects/ZC706/verilog/phy/mig_7series_v4_0_tempmon.v b/projects/ZC706/verilog/phy/mig_7series_v4_0_tempmon.v new file mode 100644 index 0000000..51340b8 --- /dev/null +++ b/projects/ZC706/verilog/phy/mig_7series_v4_0_tempmon.v @@ -0,0 +1,381 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : mig_7series_v4_0_tempmon.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Jul 25 2012 +// \___\/\___\ +// +//Device : 7 Series +//Design Name : DDR3 SDRAM +//Purpose : Monitors chip temperature via the XADC and adjusts the +// stage 2 tap values as appropriate. +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_0_tempmon # +( + parameter TCQ = 100, // Register delay (sim only) + parameter TEMP_MON_CONTROL = "INTERNAL", // XADC or user temperature source + parameter XADC_CLK_PERIOD = 5000, // pS (default to 200 MHz refclk) + parameter tTEMPSAMPLE = 10000000 // ps (10 us) +) +( + input clk, // Fabric clock + input xadc_clk, + input rst, // System reset + input [11:0] device_temp_i, // User device temperature + output [11:0] device_temp // Sampled temperature +); + + //*************************************************************************** + // Function cdiv + // Description: + // This function performs ceiling division (divide and round-up) + // Inputs: + // num: integer to be divided + // div: divisor + // Outputs: + // cdiv: result of ceiling division (num/div, rounded up) + //*************************************************************************** + + function integer cdiv (input integer num, input integer div); + begin + // perform division, then add 1 if and only if remainder is non-zero + cdiv = (num/div) + (((num%div)>0) ? 1 : 0); + end + endfunction // cdiv + + //*************************************************************************** + // Function clogb2 + // Description: + // This function performs binary logarithm and rounds up + // Inputs: + // size: integer to perform binary log upon + // Outputs: + // clogb2: result of binary logarithm, rounded up + //*************************************************************************** + + function integer clogb2 (input integer size); + begin + + size = size - 1; + + // increment clogb2 from 1 for each bit in size + for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) + size = size >> 1; + + end + + endfunction // clogb2 + + // Synchronization registers + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r1; + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r2; + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r3 /* synthesis syn_srlstyle="registers" */; + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r4; + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r5; + + // Output register + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_r; + + wire [11:0] device_temp_lcl; + reg [3:0] sync_cntr = 4'b0000; + reg device_temp_sync_r4_neq_r3; + + // (* ASYNC_REG = "TRUE" *) reg rst_r1; + // (* ASYNC_REG = "TRUE" *) reg rst_r2; + + // // Synchronization rst to XADC clock domain + // always @(posedge xadc_clk) begin + // rst_r1 <= rst; + // rst_r2 <= rst_r1; + // end + + // Synchronization counter + always @(posedge clk) begin + + device_temp_sync_r1 <= #TCQ device_temp_lcl; + device_temp_sync_r2 <= #TCQ device_temp_sync_r1; + device_temp_sync_r3 <= #TCQ device_temp_sync_r2; + device_temp_sync_r4 <= #TCQ device_temp_sync_r3; + device_temp_sync_r5 <= #TCQ device_temp_sync_r4; + + device_temp_sync_r4_neq_r3 <= #TCQ (device_temp_sync_r4 != device_temp_sync_r3) ? 1'b1 : 1'b0; + + end + + always @(posedge clk) + if(rst || (device_temp_sync_r4_neq_r3)) + sync_cntr <= #TCQ 4'b0000; + else if(~&sync_cntr) + sync_cntr <= #TCQ sync_cntr + 4'b0001; + + always @(posedge clk) + if(&sync_cntr) + device_temp_r <= #TCQ device_temp_sync_r5; + + assign device_temp = device_temp_r; + + generate + + if(TEMP_MON_CONTROL == "EXTERNAL") begin : user_supplied_temperature + + assign device_temp_lcl = device_temp_i; + + end else begin : xadc_supplied_temperature + + // calculate polling timer width and limit + localparam nTEMPSAMP = cdiv(tTEMPSAMPLE, XADC_CLK_PERIOD); + localparam nTEMPSAMP_CLKS = nTEMPSAMP; + localparam nTEMPSAMP_CLKS_M6 = nTEMPSAMP - 6; + localparam nTEMPSAMP_CNTR_WIDTH = clogb2(nTEMPSAMP_CLKS); + + // Temperature sampler FSM encoding + localparam INIT_IDLE = 2'b00; + localparam REQUEST_READ_TEMP = 2'b01; + localparam WAIT_FOR_READ = 2'b10; + localparam READ = 2'b11; + + // polling timer and tick + reg [nTEMPSAMP_CNTR_WIDTH-1:0] sample_timer = {nTEMPSAMP_CNTR_WIDTH{1'b0}}; + reg sample_timer_en = 1'b0; + reg sample_timer_clr = 1'b0; + reg sample_en = 1'b0; + + // Temperature sampler state + reg [2:0] tempmon_state = INIT_IDLE; + reg [2:0] tempmon_next_state = INIT_IDLE; + + // XADC interfacing + reg xadc_den = 1'b0; + wire xadc_drdy; + wire [15:0] xadc_do; + reg xadc_drdy_r = 1'b0; + reg [15:0] xadc_do_r = 1'b0; + + // Temperature storage + reg [11:0] temperature = 12'b0; + + // Reset sync + (* ASYNC_REG = "TRUE" *) reg rst_r1; + (* ASYNC_REG = "TRUE" *) reg rst_r2; + + // Synchronization rst to XADC clock domain + always @(posedge xadc_clk) begin + rst_r1 <= rst; + rst_r2 <= rst_r1; + end + + // XADC polling interval timer + always @ (posedge xadc_clk) + if(rst_r2 || sample_timer_clr) + sample_timer <= #TCQ {nTEMPSAMP_CNTR_WIDTH{1'b0}}; + else if(sample_timer_en) + sample_timer <= #TCQ sample_timer + 1'b1; + + // XADC sampler state transition + always @(posedge xadc_clk) + if(rst_r2) + tempmon_state <= #TCQ INIT_IDLE; + else + tempmon_state <= #TCQ tempmon_next_state; + + // Sample enable + always @(posedge xadc_clk) + sample_en <= #TCQ (sample_timer == nTEMPSAMP_CLKS_M6) ? 1'b1 : 1'b0; + + // XADC sampler next state transition + always @(tempmon_state or sample_en or xadc_drdy_r) begin + + tempmon_next_state = tempmon_state; + + case(tempmon_state) + + INIT_IDLE: + if(sample_en) + tempmon_next_state = REQUEST_READ_TEMP; + + REQUEST_READ_TEMP: + tempmon_next_state = WAIT_FOR_READ; + + WAIT_FOR_READ: + if(xadc_drdy_r) + tempmon_next_state = READ; + + READ: + tempmon_next_state = INIT_IDLE; + + default: + tempmon_next_state = INIT_IDLE; + + endcase + + end + + // Sample timer clear + always @(posedge xadc_clk) + if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) + sample_timer_clr <= #TCQ 1'b0; + else if(tempmon_state == REQUEST_READ_TEMP) + sample_timer_clr <= #TCQ 1'b1; + + // Sample timer enable + always @(posedge xadc_clk) + if(rst_r2 || (tempmon_state == REQUEST_READ_TEMP)) + sample_timer_en <= #TCQ 1'b0; + else if((tempmon_state == INIT_IDLE) || (tempmon_state == READ)) + sample_timer_en <= #TCQ 1'b1; + + // XADC enable + always @(posedge xadc_clk) + if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) + xadc_den <= #TCQ 1'b0; + else if(tempmon_state == REQUEST_READ_TEMP) + xadc_den <= #TCQ 1'b1; + + // Register XADC outputs + always @(posedge xadc_clk) + if(rst_r2) begin + xadc_drdy_r <= #TCQ 1'b0; + xadc_do_r <= #TCQ 16'b0; + end + else begin + xadc_drdy_r <= #TCQ xadc_drdy; + xadc_do_r <= #TCQ xadc_do; + end + + // Store current read value + always @(posedge xadc_clk) + if(rst_r2) + temperature <= #TCQ 12'b0; + else if(tempmon_state == READ) + temperature <= #TCQ xadc_do_r[15:4]; + + assign device_temp_lcl = temperature; + + // XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter + // 7 Series + // Xilinx HDL Libraries Guide, version 14.1 + XADC #( + // INIT_40 - INIT_42: XADC configuration registers + .INIT_40(16'h1000), // config reg 0 + .INIT_41(16'h2fff), // config reg 1 + .INIT_42(16'h0800), // config reg 2 + // INIT_48 - INIT_4F: Sequence Registers + .INIT_48(16'h0101), // Sequencer channel selection + .INIT_49(16'h0000), // Sequencer channel selection + .INIT_4A(16'h0100), // Sequencer Average selection + .INIT_4B(16'h0000), // Sequencer Average selection + .INIT_4C(16'h0000), // Sequencer Bipolar selection + .INIT_4D(16'h0000), // Sequencer Bipolar selection + .INIT_4E(16'h0000), // Sequencer Acq time selection + .INIT_4F(16'h0000), // Sequencer Acq time selection + // INIT_50 - INIT_58, INIT5C: Alarm Limit Registers + .INIT_50(16'hb5ed), // Temp alarm trigger + .INIT_51(16'h57e4), // Vccint upper alarm limit + .INIT_52(16'ha147), // Vccaux upper alarm limit + .INIT_53(16'hca33), // Temp alarm OT upper + .INIT_54(16'ha93a), // Temp alarm reset + .INIT_55(16'h52c6), // Vccint lower alarm limit + .INIT_56(16'h9555), // Vccaux lower alarm limit + .INIT_57(16'hae4e), // Temp alarm OT reset + .INIT_58(16'h5999), // VBRAM upper alarm limit + .INIT_5C(16'h5111), // VBRAM lower alarm limit + // Simulation attributes: Set for proepr simulation behavior + .SIM_DEVICE("7SERIES") // Select target device (values) + ) + XADC_inst ( + // ALARMS: 8-bit (each) output: ALM, OT + .ALM(), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram + .OT(), // 1-bit output: Over-Temperature alarm + // Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports + .DO(xadc_do), // 16-bit output: DRP output data bus + .DRDY(xadc_drdy), // 1-bit output: DRP data ready + // STATUS: 1-bit (each) output: XADC status ports + .BUSY(), // 1-bit output: ADC busy output + .CHANNEL(), // 5-bit output: Channel selection outputs + .EOC(), // 1-bit output: End of Conversion + .EOS(), // 1-bit output: End of Sequence + .JTAGBUSY(), // 1-bit output: JTAG DRP transaction in progress output + .JTAGLOCKED(), // 1-bit output: JTAG requested DRP port lock + .JTAGMODIFIED(), // 1-bit output: JTAG Write to the DRP has occurred + .MUXADDR(), // 5-bit output: External MUX channel decode + // Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0] + .VAUXN(16'b0), // 16-bit input: N-side auxiliary analog input + .VAUXP(16'b0), // 16-bit input: P-side auxiliary analog input + // CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs + .CONVST(1'b0), // 1-bit input: Convert start input + .CONVSTCLK(1'b0), // 1-bit input: Convert start input + .RESET(1'b0), // 1-bit input: Active-high reset + // Dedicated Analog Input Pair: 1-bit (each) input: VP/VN + .VN(1'b0), // 1-bit input: N-side analog input + .VP(1'b0), // 1-bit input: P-side analog input + // Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports + .DADDR(7'b0), // 7-bit input: DRP address bus + .DCLK(xadc_clk), // 1-bit input: DRP clock + .DEN(xadc_den), // 1-bit input: DRP enable signal + .DI(16'b0), // 16-bit input: DRP input data bus + .DWE(1'b0) // 1-bit input: DRP write enable + ); + + // End of XADC_inst instantiation + + end + + endgenerate + +endmodule diff --git a/projects/ZC706/verilog/project.vh b/projects/ZC706/verilog/project.vh new file mode 100644 index 0000000..d9f67e2 --- /dev/null +++ b/projects/ZC706/verilog/project.vh @@ -0,0 +1,14 @@ +//`define SIMULATION + +`define SOFTMC_STREAM_WIDTH 256 +`define SOFTMC_STREAM_KEEP 32 + +`define DQ_WIDTH 64 +`define ODT_WIDTH 1 +`define CS_WIDTH 1 +`define CKE_WIDTH 1 +`define CK_WIDTH 1 +`define ROW_ADDR_WIDTH 14 + +`define BANK_WIDTH 3 +`define ROW_WIDTH 16 \ No newline at end of file diff --git a/projects/ZC706/verilog/softmc_top.v b/projects/ZC706/verilog/softmc_top.v new file mode 100644 index 0000000..6360122 --- /dev/null +++ b/projects/ZC706/verilog/softmc_top.v @@ -0,0 +1,511 @@ +`include "parameters.vh" +`include "project.vh" + + +module softmc_top #(parameter tCK = 1500, SIM = "false") + ( +`ifdef SIMULATION + input clk, + input rst, +`else + // common signals + input c0_sys_clk_p, + input c0_sys_clk_n, + input sys_rst, +`endif + + // iob <> ddr4 sdram ip signals + output [13:0] ddr3_addr, + output [2:0] ddr3_ba, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + output [`CKE_WIDTH-1:0] ddr3_cke, + output [`ODT_WIDTH-1:0] ddr3_odt, + output [`CS_WIDTH-1:0] ddr3_cs_n, + output [`CK_WIDTH-1:0] ddr3_ck_p, + output [`CK_WIDTH-1:0] ddr3_ck_n, + output ddr3_reset_n, + + inout [7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [7:0] ddr3_dqs_p, + inout [7:0] ddr3_dqs_n + //output init_calib_complete + +`ifndef SIMULATION + , + // xdma signals + input clk_ref_p, + input clk_ref_n, + output [3:0] pci_exp_txp, + output [3:0] pci_exp_txn, + input [3:0] pci_exp_rxp, + input [3:0] pci_exp_rxn, + input pcie_rst_n +`endif + ); + + wire ui_rst_n; + wire ui_clk, ui_rst; + +`ifdef SIMULATION + // Generate differantial clock from single edge input clock and assign resets. + wire c0_sys_clk_p; + wire c0_sys_clk_n; + wire sys_rst; + reg [6:0] sim_rst_r; + + assign c0_sys_clk_p = clk; + assign c0_sys_clk_n = ~clk; + assign sys_rst = rst; + assign ui_rst = ~ui_rst_n || (|sim_rst_r); + + always @(posedge clk) begin + if (rst) begin + sim_rst_r <= 'hFFFFFFFF; + end + else if (sim_rst_r > 0) begin + sim_rst_r <= sim_rst_r - 1; + end + end +`else + assign ui_rst = ~ui_rst_n; +`endif + + + // Frontend control signals + wire softmc_fin; + wire user_rst; + + // Frontend <-> Fetch signals + wire [`IMEM_ADDR_WIDTH-1:0] fr_addr_in; + wire fr_valid_in; + wire [`INSTR_WIDTH-1:0] fr_data_out; + wire fr_valid_out; + wire [`IMEM_ADDR_WIDTH-1:0] fr_addr_out; + wire fr_ready_out; + + // Frontend <-> misc. control signals + wire per_rd_init; + wire per_zq_init; + wire per_ref_init; + wire rbe_switch_mode; + wire toggle_dll; + + // AXI streaming ports + wire [`XDMA_AXI_DATA_WIDTH-1:0] m_axis_h2c_tdata_0,xdma_h2c_tdata_0; + wire m_axis_h2c_tlast_0, xdma_h2c_tlast_0; + wire m_axis_h2c_tvalid_0, xdma_h2c_tvalid_0; + wire m_axis_h2c_tready_0, xdma_h2c_tready_0; + wire [`XDMA_AXI_DATA_WIDTH/8-1:0] m_axis_h2c_tkeep_0, xdma_h2c_tkeep_0; + wire [`XDMA_AXI_DATA_WIDTH-1:0] s_axis_c2h_tdata_0, xdma_c2h_tdata_0; + wire s_axis_c2h_tlast_0, xdma_c2h_tlast_0; + wire s_axis_c2h_tvalid_0, xdma_c2h_tvalid_0; + wire s_axis_c2h_tready_0, xdma_c2h_tready_0; + wire [`XDMA_AXI_DATA_WIDTH/8-1:0] s_axis_c2h_tkeep_0, xdma_c2h_tkeep_0; + + // ddr_pipeline <-> outer module if + wire [3:0] ddr_write; + wire [3:0] ddr_read; + wire [3:0] ddr_pre; + wire [3:0] ddr_act; + wire [3:0] ddr_ref; + wire [3:0] ddr_sre; + wire [3:0] ddr_srx; + wire [3:0] ddr_zq; + wire [3:0] ddr_nop; + wire [3:0] ddr_ap; + wire [3:0] ddr_pall; + wire [3:0] ddr_half_bl; + wire [4*`BG_WIDTH-1:0] ddr_bg; + wire [4*`BANK_WIDTH-1:0] ddr_bank; + wire [4*`COL_WIDTH-1:0] ddr_col; + wire [4*`ROW_WIDTH-1:0] ddr_row; + wire [511:0] ddr_wdata; + + // periodic maintenance signals + wire ddr_maint_read; + + + // ddr adapter + // MC <-> PHY Interface + wire [3:0] mc_ras_n; // DDR Row access strobe + wire [3:0] mc_cas_n; // DDR Column access strobe + wire [3:0] mc_we_n; // DDR Write enable + wire [55:0] mc_address; // row address for activates / column address for read&writes + wire [11:0] mc_bank; // bank address + wire [3:0] mc_cs_n; // chip select, probably used to deselect in NOP cycles + wire mc_reset_n; // Have no idea, probably need to keep HIGH + wire [1:0] mc_odt; // Need some logic to drive this + wire [3:0] mc_cke; // This should be HIGH all the time + wire [3:0] mc_aux_out0; + wire [3:0] mc_aux_out1; + wire mc_cmd_wren; // Enqueue new command + wire mc_ctl_wren; // Enqueue new control singal + wire [2:0] mc_cmd; // The command to enqueue + wire [1:0] mc_cas_slot; // Which CAS slot we issued this command from 0-2 + wire [5:0] mc_data_offset; + wire [5:0] mc_data_offset_1; + wire [5:0] mc_data_offset_2; + wire [1:0] mc_rank_cnt; + // Write + wire mc_wrdata_en; // Asserted for DDR-WRITEs + wire [511:0] mc_wrdata; + wire [63:0] mc_wrdata_mask; // Should be 0xff if we don't want to mask out bits + wire idle; + wire phy_mc_ctl_full; // CTL interface is full + wire phy_mc_cmd_full; // CMD interface is full + wire phy_mc_data_full; // ????????? + (*dont_touch = "true"*) reg pmcctlf; + (*dont_touch = "true"*) reg pmccmdf; + (*dont_touch = "true"*) reg pmcdf; + wire [5:0] calib_rd_data_offset_0; + wire [5:0] calib_rd_data_offset_1; + wire [5:0] calib_rd_data_offset_2; + wire phy_rddata_valid; // Next cycle will have a valid read + wire [511:0] phy_rd_data; + + wire read_seq_incoming; // next few instructions will read from DRAM + wire [11:0] incoming_reads; // how many reads next few instructions will issue + wire [11:0] buffer_space; // remaining buffer size + + wire c0_init_calib_complete; + + // There is a possibility that these signals are on + // the critical path as observed in + // the previous iteration of SoftMC + reg c0_init_calib_complete_r, sys_rst_r; + wire iq_full, processing_iseq, rdback_fifo_empty; + + //assign init_calib_complete = c0_init_calib_complete_r; + + always @(posedge ui_clk) begin + c0_init_calib_complete_r <= c0_init_calib_complete; + sys_rst_r <= sys_rst; + end + + memctl_mig phy_ddr3_i( + // DDR Interface + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_cke (ddr3_cke), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + + // MC <-> PHY Interface + .mc_ras_n (mc_ras_n), + .mc_cas_n (mc_cas_n), + .mc_we_n (mc_we_n), + .mc_address (mc_address), + .mc_bank (mc_bank), + .mc_cs_n (mc_cs_n), + .mc_reset_n (mc_reset_n), + .mc_odt (mc_odt), + .mc_cke (mc_cke), + // AUX - For ODT and CKE assertion during reads and writes + .mc_aux_out0 (mc_aux_out0), + .mc_aux_out1 (mc_aux_out1), + .mc_cmd_wren (mc_cmd_wren), + .mc_ctl_wren (mc_ctl_wren), + .mc_cmd (mc_cmd), + .mc_cas_slot (mc_cas_slot), + .mc_data_offset (mc_data_offset), + .mc_data_offset_1 (mc_data_offset_1), + .mc_data_offset_2 (mc_data_offset_2), + .mc_rank_cnt (mc_rank_cnt), + + .mc_wrdata_en (mc_wrdata_en), + .mc_wrdata (mc_wrdata), + .mc_wrdata_mask (mc_wrdata_mask), + .idle (idle), + .phy_mc_ctl_full (phy_mc_ctl_full), + .phy_mc_cmd_full (phy_mc_cmd_full), + .phy_mc_data_full (phy_mc_data_full), + .calib_rd_data_offset_0 (calib_rd_data_offset_0), + .calib_rd_data_offset_1 (calib_rd_data_offset_1), + .calib_rd_data_offset_2 (calib_rd_data_offset_2), + .phy_rddata_valid (phy_rddata_valid), + .phy_rd_data (phy_rd_data), + + + .sys_clk_p (c0_sys_clk_p), + .sys_clk_n (c0_sys_clk_n), + + .ui_clk (ui_clk), + .ui_clk_sync_rst (ui_rst_n), + + .init_calib_complete (c0_init_calib_complete), + + // System reset - Default polarity of sys_rst pin is Active Low. + // System reset polarity will change based on the option + // selected in GUI. + .sys_rst (sys_rst) + ); + + softmc_pipeline pipeline( + .clk(ui_clk), + .rst(ui_rst || user_rst), + + .softmc_end(softmc_fin), + .read_size(incoming_reads), + .read_seq_incoming(read_seq_incoming), + .buffer_space(buffer_space), + + .addr_out(fr_addr_in), + .valid_out(fr_valid_in), + .data_in(fr_data_out), + .valid_in(fr_valid_out), + .addr_in(fr_addr_out), + .ready_out(fr_ready_out), + + .ddr_write(ddr_write), + .ddr_read(ddr_read), + .ddr_pre(ddr_pre), + .ddr_act(ddr_act), + .ddr_ref(ddr_ref), + .ddr_sre(ddr_sre), + .ddr_srx(ddr_srx), + .ddr_zq(ddr_zq), + .ddr_nop(ddr_nop), + .ddr_ap(ddr_ap), + .ddr_pall(ddr_pall), + .ddr_half_bl(ddr_half_bl), + .ddr_bg(ddr_bg), + .ddr_bank(ddr_bank), + .ddr_col(ddr_col), + .ddr_row(ddr_row), + .ddr_wdata(ddr_wdata) + ); + + wire frontend_ready; + + frontend #(.SIM_MEM(SIM)) frontend( + .clk(ui_clk), + .rst(ui_rst), + + .init_calib_complete(c0_init_calib_complete_r), + .softmc_fin(softmc_fin), + .user_rst(user_rst), + + .dllt_begin(toggle_dll), + + // indicates read_back unit is ready for the next iseq + .frontend_ready(frontend_ready), + + // frontend <-> fetch stage if + .addr_in(fr_addr_in), + .valid_in(fr_valid_in), + .data_out(fr_data_out), + .valid_out(fr_valid_out), + .addr_out(fr_addr_out), + .ready_in(fr_ready_out), + + // frontend <-> xdma interface + .h2c_tdata_0(m_axis_h2c_tdata_0), + .h2c_tlast_0(m_axis_h2c_tlast_0), + .h2c_tvalid_0(m_axis_h2c_tvalid_0), + .h2c_tready_0(m_axis_h2c_tready_0), + .h2c_tkeep_0(m_axis_h2c_tkeep_0), + + .per_rd_init(per_rd_init), + .per_zq_init(per_zq_init), + .per_ref_init(per_ref_init), + .rbe_switch_mode(rbe_switch_mode) + ); + + ddr3_adapter ddr3_adapter + ( + .clk(ui_clk), + .rst(ui_rst || user_rst), + .init_calib_complete(c0_init_calib_complete_r), + //.io_config_strobe, + //.io_config, + // MC <-> PHY Interface + .mc_ras_n (mc_ras_n), + .mc_cas_n (mc_cas_n), + .mc_we_n (mc_we_n), + .mc_address (mc_address), + .mc_bank (mc_bank), + .mc_cs_n (mc_cs_n), + .mc_reset_n (mc_reset_n), + .mc_odt (mc_odt), + .mc_cke (mc_cke), + // AUX - For ODT and CKE assertion during reads and writes + .mc_aux_out0 (mc_aux_out0), + .mc_aux_out1 (mc_aux_out1), + .mc_cmd_wren (mc_cmd_wren), + .mc_ctl_wren (mc_ctl_wren), + .mc_cmd (mc_cmd), + .mc_cas_slot (mc_cas_slot), + .mc_data_offset (mc_data_offset), + .mc_data_offset_1 (mc_data_offset_1), + .mc_data_offset_2 (mc_data_offset_2), + .mc_rank_cnt (mc_rank_cnt), + + .mc_wrdata_en (mc_wrdata_en), + .mc_wrdata (mc_wrdata), + .mc_wrdata_mask (mc_wrdata_mask), + .idle (idle), + .phy_mc_ctl_full (phy_mc_ctl_full), + .phy_mc_cmd_full (phy_mc_cmd_full), + .phy_mc_data_full (phy_mc_data_full), + .calib_rd_data_offset_0 (calib_rd_data_offset_0), + .calib_rd_data_offset_1 (calib_rd_data_offset_1), + .calib_rd_data_offset_2 (calib_rd_data_offset_2), + + .ddr_write(ddr_write), + .ddr_read(ddr_read), + .ddr_pre(ddr_pre), + .ddr_act(ddr_act), + .ddr_ref(ddr_ref), + .ddr_zq(ddr_zq), + .ddr_nop(ddr_nop), + .ddr_ap(ddr_ap), + .ddr_pall(ddr_pall), + .ddr_half_bl(ddr_half_bl), + .ddr_bg(ddr_bg), + .ddr_bank(ddr_bank), + .ddr_col(ddr_col), + .ddr_row(ddr_row), + .ddr_wdata(ddr_wdata), + + .ddr_maint_read(per_rd_init) + ); + +`ifndef SIMULATION + wire sys_clk, sys_clk_gt; + wire [2:0] msi_vector_width; + wire msi_enable; + wire user_lnk_up, usr_irq_req, usr_irq_ack; + wire pci_user_clk, pci_user_reset; + + pcie_top zc706_pcie ( + .pci_exp_txn ( pci_exp_txn ), + .pci_exp_txp ( pci_exp_txp ), + .pci_exp_rxn ( pci_exp_rxn ), + .pci_exp_rxp ( pci_exp_rxp ), + + .sys_rst_n ( pcie_rst_n ), + + .sys_clk_p ( clk_ref_p ), + .sys_clk_n ( clk_ref_n ), + + .softmc_c2h_tdata(xdma_c2h_tdata_0), + .softmc_c2h_tlast(xdma_c2h_tlast_0), + .softmc_c2h_tvalid(xdma_c2h_tvalid_0), + .softmc_c2h_tready(xdma_c2h_tready_0), + .softmc_c2h_tkeep(xdma_c2h_tkeep_0), + + .softmc_h2c_tdata(xdma_h2c_tdata_0), + .softmc_h2c_tlast(xdma_h2c_tlast_0), + .softmc_h2c_tvalid(xdma_h2c_tvalid_0), + .softmc_h2c_tready(xdma_h2c_tready_0), + .softmc_h2c_tkeep(xdma_h2c_tkeep_0), + + .user_clk_o ( pci_user_clk ), + .user_reset_o ( pci_user_reset ) + ); + + assign clk_200mhz = pci_user_clk; + + // Clock converter for the c2h interface + axis_clock_converter axis_clk_conv_i0 + ( + .s_axis_tvalid(s_axis_c2h_tvalid_0), + .s_axis_tlast(s_axis_c2h_tlast_0), + .s_axis_tdata(s_axis_c2h_tdata_0), + .s_axis_tkeep(s_axis_c2h_tkeep_0), + .s_axis_tready(s_axis_c2h_tready_0), + .m_axis_tvalid(xdma_c2h_tvalid_0), + .m_axis_tlast(xdma_c2h_tlast_0), + .m_axis_tdata(xdma_c2h_tdata_0), + .m_axis_tkeep(xdma_c2h_tkeep_0), + .m_axis_tready(xdma_c2h_tready_0), + .s_axis_aresetn(~ui_rst), + .s_axis_aclk(ui_clk), + .m_axis_aresetn(~pci_user_reset), + .m_axis_aclk(pci_user_clk) + ); + + // Clock converter for the h2c interface + axis_clock_converter axis_clk_conv_i1 + ( + .m_axis_tvalid(m_axis_h2c_tvalid_0), + .m_axis_tlast(m_axis_h2c_tlast_0), + .m_axis_tdata(m_axis_h2c_tdata_0), + .m_axis_tkeep(m_axis_h2c_tkeep_0), + .m_axis_tready(m_axis_h2c_tready_0), + .s_axis_tvalid(xdma_h2c_tvalid_0), + .s_axis_tlast(xdma_h2c_tlast_0), + .s_axis_tdata(xdma_h2c_tdata_0), + .s_axis_tkeep(xdma_h2c_tkeep_0), + .s_axis_tready(xdma_h2c_tready_0), + .m_axis_aresetn(~ui_rst), + .m_axis_aclk(ui_clk), + .s_axis_aresetn(~pci_user_reset), + .s_axis_aclk(pci_user_clk) + ); + + // ila_hc debug_c2h_ui_clk ( + // .clk ( ui_clk ), + // .probe0 ( s_axis_c2h_tdata_0 ), + // .probe1 ( s_axis_c2h_tkeep_0 ), + // .probe2 ( s_axis_c2h_tvalid_0 ), + // .probe3 ( c0_init_calib_complete_r ), + // .probe4 ( s_axis_c2h_tlast_0 ) + // ); + + // ila_hc debug_h2c_ui_clk ( + // .clk ( ui_clk ), + // .probe0 ( m_axis_h2c_tdata_0 ), + // .probe1 ( m_axis_h2c_tkeep_0 ), + // .probe2 ( m_axis_h2c_tvalid_0 ), + // .probe3 ( m_axis_h2c_tready_0 ), + // .probe4 ( m_axis_h2c_tlast_0 ) + // ); +`endif + + readback_engine rbe( + + // common signals + .clk(ui_clk), + .rst(ui_rst || user_rst), + + // other ctrl signals + .flush(frontend_ready), + .switch_mode(rbe_switch_mode), + .read_seq_incoming(read_seq_incoming), // next few instructions will read from DRAM + .incoming_reads(incoming_reads), // how many reads next few instructions will issue + .buffer_space(buffer_space), // remaining buffer size + // DRAM <-> engine if + .rd_data(phy_rd_data), + .rd_valid(phy_rddata_valid), + + // rbe <-> rf interface + .ddr_wdata(ddr_wdata), + + .per_rd_init(per_rd_init), + .per_zq_init(per_zq_init), + .per_ref_init(per_ref_init), + + // rbe <-> xdma if + .c2h_tdata_0(s_axis_c2h_tdata_0), + .c2h_tlast_0(s_axis_c2h_tlast_0), + .c2h_tvalid_0(s_axis_c2h_tvalid_0), + .c2h_tready_0(s_axis_c2h_tready_0), + .c2h_tkeep_0(s_axis_c2h_tkeep_0) + + ); + +endmodule diff --git a/projects/ZC706/verilog/zc706_pcie_4x_gen2.v b/projects/ZC706/verilog/zc706_pcie_4x_gen2.v new file mode 100644 index 0000000..e0609d3 --- /dev/null +++ b/projects/ZC706/verilog/zc706_pcie_4x_gen2.v @@ -0,0 +1,582 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : zc706_pcie_x4_gen2_support.v +// Version : 3.2 +//-- +//-- Description: PCI Express Endpoint Shared Logic Wrapper +//-- +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module zc706_pcie_x4_gen2_support # ( + parameter LINK_CAP_MAX_LINK_WIDTH = 8, // PCIe Lane Width + parameter CLK_SHARING_EN = "FALSE", // Enable Clock Sharing + parameter C_DATA_WIDTH = 256, // AXI interface data width + parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width + parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency + parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency + parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency + parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device + parameter PCIE_USE_MODE = "2.1" // PCIe use mode +) +( + + //----------------------------------------------------------------------------------------------------------------// + // PCI Express (pci_exp) Interface // + //----------------------------------------------------------------------------------------------------------------// + + // Tx + output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn, + output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp, + + // Rx + input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn, + input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp, + + //----------------------------------------------------------------------------------------------------------------// + // Clocking Sharing Interface // + //----------------------------------------------------------------------------------------------------------------// + output pipe_pclk_out_slave, + output pipe_rxusrclk_out, + output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_out, + output pipe_dclk_out, + output pipe_userclk1_out, + output pipe_userclk2_out, + output pipe_oobclk_out, + output pipe_mmcm_lock_out, + input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_pclk_sel_slave, + input pipe_mmcm_rst_n, + + //----------------------------------------------------------------------------------------------------------------// + // AXI-S Interface // + //----------------------------------------------------------------------------------------------------------------// + + // Common + output user_clk_out, + output user_reset_out, + output user_lnk_up, + output user_app_rdy, + + input tx_cfg_gnt, + input rx_np_ok, + input rx_np_req, + input cfg_turnoff_ok, + input cfg_trn_pending, + input cfg_pm_halt_aspm_l0s, + input cfg_pm_halt_aspm_l1, + input cfg_pm_force_state_en, + input [1:0] cfg_pm_force_state, + input [63:0] cfg_dsn, + input cfg_pm_send_pme_to, + input [7:0] cfg_ds_bus_number, + input [4:0] cfg_ds_device_number, + input [2:0] cfg_ds_function_number, + input cfg_pm_wake, + + // AXI TX + //----------- + input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, + input s_axis_tx_tvalid, + output s_axis_tx_tready, + input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, + input s_axis_tx_tlast, + input [3:0] s_axis_tx_tuser, + + // AXI RX + //----------- + output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, + output m_axis_rx_tvalid, + input m_axis_rx_tready, + output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, + output m_axis_rx_tlast, + output [21:0] m_axis_rx_tuser, + + // Flow Control + output [11:0] fc_cpld, + output [7:0] fc_cplh, + output [11:0] fc_npd, + output [7:0] fc_nph, + output [11:0] fc_pd, + output [7:0] fc_ph, + input [2:0] fc_sel, + + //----------------------------------------------------------------------------------------------------------------// + // Configuration (CFG) Interface // + //----------------------------------------------------------------------------------------------------------------// + //------------------------------------------------// + // EP and RP // + //------------------------------------------------// + output tx_err_drop, + output tx_cfg_req, + output [5:0] tx_buf_av, + output [15:0] cfg_status, + output [15:0] cfg_command, + output [15:0] cfg_dstatus, + output [15:0] cfg_dcommand, + output [15:0] cfg_lstatus, + output [15:0] cfg_lcommand, + output [15:0] cfg_dcommand2, + output [2:0] cfg_pcie_link_state, + output cfg_to_turnoff, + output [7:0] cfg_bus_number, + output [4:0] cfg_device_number, + output [2:0] cfg_function_number, + + output cfg_pmcsr_pme_en, + output [1:0] cfg_pmcsr_powerstate, + output cfg_pmcsr_pme_status, + output cfg_received_func_lvl_rst, + + //------------------------------------------------// + // RP Only // + //------------------------------------------------// + output cfg_bridge_serr_en, + output cfg_slot_control_electromech_il_ctl_pulse, + output cfg_root_control_syserr_corr_err_en, + output cfg_root_control_syserr_non_fatal_err_en, + output cfg_root_control_syserr_fatal_err_en, + output cfg_root_control_pme_int_en, + output cfg_aer_rooterr_corr_err_reporting_en, + output cfg_aer_rooterr_non_fatal_err_reporting_en, + output cfg_aer_rooterr_fatal_err_reporting_en, + output cfg_aer_rooterr_corr_err_received, + output cfg_aer_rooterr_non_fatal_err_received, + output cfg_aer_rooterr_fatal_err_received, + //----------------------------------------------------------------------------------------------------------------// + // VC interface // + //----------------------------------------------------------------------------------------------------------------// + + output [6:0] cfg_vc_tcvc_map, + + // Management Interface + output [31:0] cfg_mgmt_do, + output cfg_mgmt_rd_wr_done, + input [31:0] cfg_mgmt_di, + input [3:0] cfg_mgmt_byte_en, + input [9:0] cfg_mgmt_dwaddr, + input cfg_mgmt_wr_en, + input cfg_mgmt_rd_en, + input cfg_mgmt_wr_readonly, + input cfg_mgmt_wr_rw1c_as_rw, + + // Error Reporting Interface + input cfg_err_ecrc, + input cfg_err_ur, + input cfg_err_cpl_timeout, + input cfg_err_cpl_unexpect, + input cfg_err_cpl_abort, + input cfg_err_posted, + input cfg_err_cor, + input cfg_err_atomic_egress_blocked, + input cfg_err_internal_cor, + input cfg_err_malformed, + input cfg_err_mc_blocked, + input cfg_err_poisoned, + input cfg_err_norecovery, + input [47:0] cfg_err_tlp_cpl_header, + output cfg_err_cpl_rdy, + input cfg_err_locked, + input cfg_err_acs, + input cfg_err_internal_uncor, + //----------------------------------------------------------------------------------------------------------------// + // AER interface // + //----------------------------------------------------------------------------------------------------------------// + input [127:0] cfg_err_aer_headerlog, + input [4:0] cfg_aer_interrupt_msgnum, + output cfg_err_aer_headerlog_set, + output cfg_aer_ecrc_check_en, + output cfg_aer_ecrc_gen_en, + + output cfg_msg_received, + output [15:0] cfg_msg_data, + output cfg_msg_received_pm_as_nak, + output cfg_msg_received_setslotpowerlimit, + output cfg_msg_received_err_cor, + output cfg_msg_received_err_non_fatal, + output cfg_msg_received_err_fatal, + output cfg_msg_received_pm_pme, + output cfg_msg_received_pme_to_ack, + output cfg_msg_received_assert_int_a, + output cfg_msg_received_assert_int_b, + output cfg_msg_received_assert_int_c, + output cfg_msg_received_assert_int_d, + output cfg_msg_received_deassert_int_a, + output cfg_msg_received_deassert_int_b, + output cfg_msg_received_deassert_int_c, + output cfg_msg_received_deassert_int_d, + + //------------------------------------------------// + // EP Only // + //------------------------------------------------// + // Interrupt Interface Signals + input cfg_interrupt, + output cfg_interrupt_rdy, + input cfg_interrupt_assert, + input [7:0] cfg_interrupt_di, + output [7:0] cfg_interrupt_do, + output [2:0] cfg_interrupt_mmenable, + output cfg_interrupt_msienable, + output cfg_interrupt_msixenable, + output cfg_interrupt_msixfm, + input cfg_interrupt_stat, + input [4:0] cfg_pciecap_interrupt_msgnum, + + //----------------------------------------------------------------------------------------------------------------// + // Physical Layer Control and Status (PL) Interface // + //----------------------------------------------------------------------------------------------------------------// + //------------------------------------------------// + // EP and RP // + //------------------------------------------------// + input [1:0] pl_directed_link_change, + input [1:0] pl_directed_link_width, + input pl_directed_link_speed, + input pl_directed_link_auton, + input pl_upstream_prefer_deemph, + + output pl_sel_lnk_rate, + output [1:0] pl_sel_lnk_width, + output [5:0] pl_ltssm_state, + output [1:0] pl_lane_reversal_mode, + output pl_phy_lnk_up, + output [2:0] pl_tx_pm_state, + output [1:0] pl_rx_pm_state, + output pl_link_upcfg_cap, + output pl_link_gen2_cap, + output pl_link_partner_gen2_supported, + output [2:0] pl_initial_link_width, + output pl_directed_change_done, + + //------------------------------------------------// + // EP Only // + //------------------------------------------------// + output pl_received_hot_rst, + + //------------------------------------------------// + // RP Only // + //------------------------------------------------// + input pl_transmit_hot_rst, + input pl_downstream_deemph_source, + + //----------------------------------------------------------------------------------------------------------------// + // PCIe DRP (PCIe DRP) Interface // + //----------------------------------------------------------------------------------------------------------------// + input pcie_drp_clk, + input pcie_drp_en, + input pcie_drp_we, + input [8:0] pcie_drp_addr, + input [15:0] pcie_drp_di, + output pcie_drp_rdy, + output [15:0] pcie_drp_do, + + input sys_clk, + input sys_rst_n + +); + // Wires used for external clocking connectivity + wire pipe_pclk_out; + wire pipe_txoutclk_in; + wire [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_in; + wire [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_pclk_sel_in; + wire pipe_gen3_in; + + + // Wires used for external GT COMMON connectivity + wire [11:0] qpll_drp_crscode; + wire [17:0] qpll_drp_fsm; + wire [1:0] qpll_drp_done; + wire [1:0] qpll_drp_reset; + wire qpll_qplld; + wire [1:0] qpll_qpllreset; + wire qpll_drp_clk; + wire qpll_drp_rst_n; + wire qpll_drp_ovrd; + wire qpll_drp_gen3; + wire qpll_drp_start; + + + //---------- PIPE Clock Shared Mode ------------------------------// + +zc706_pcie_x4_gen2_pipe_clock # + ( + .PCIE_ASYNC_EN ( "FALSE" ), // PCIe async enable + .PCIE_TXBUF_EN ( "FALSE" ), // PCIe TX buffer enable for Gen1/Gen2 only + .PCIE_LANE ( LINK_CAP_MAX_LINK_WIDTH ), // PCIe number of lanes + // synthesis translate_off + .PCIE_LINK_SPEED ( 2 ), + // synthesis translate_on + .PCIE_REFCLK_FREQ ( PCIE_REFCLK_FREQ ), // PCIe reference clock frequency + .PCIE_USERCLK1_FREQ ( PCIE_USERCLK1_FREQ ), // PCIe user clock 1 frequency + .PCIE_USERCLK2_FREQ ( PCIE_USERCLK2_FREQ ), // PCIe user clock 2 frequency + .PCIE_DEBUG_MODE ( 0 ) + ) + pipe_clock_i + ( + + //---------- Input ------------------------------------- + .CLK_CLK ( sys_clk ), + .CLK_TXOUTCLK ( pipe_txoutclk_in ), // Reference clock from lane 0 + .CLK_RXOUTCLK_IN ( pipe_rxoutclk_in ), + .CLK_RST_N ( pipe_mmcm_rst_n ), // Allow system reset for error_recovery + .CLK_PCLK_SEL ( pipe_pclk_sel_in ), + .CLK_PCLK_SEL_SLAVE ( pipe_pclk_sel_slave), + .CLK_GEN3 ( pipe_gen3_in ), + + //---------- Output ------------------------------------ + .CLK_PCLK ( pipe_pclk_out), + .CLK_PCLK_SLAVE ( pipe_pclk_out_slave), + .CLK_RXUSRCLK ( pipe_rxusrclk_out), + .CLK_RXOUTCLK_OUT ( pipe_rxoutclk_out), + .CLK_DCLK ( pipe_dclk_out), + .CLK_OOBCLK ( pipe_oobclk_out), + .CLK_USERCLK1 ( pipe_userclk1_out), + .CLK_USERCLK2 ( pipe_userclk2_out), + .CLK_MMCM_LOCK ( pipe_mmcm_lock_out) + + ); + + + + + //---------- GT COMMON Internal Mode--------------------------------------- + + assign qpll_drp_done = 2'd0; + assign qpll_drp_reset = 2'd0; + assign qpll_drp_crscode = 12'd0; + assign qpll_drp_fsm = 18'd0; + assign qpll_qplloutclk = 2'd0; + assign qpll_qplloutrefclk = 2'd0; + assign qpll_qplllock = 2'd0; + + + +pcie_7x_0 zc706_pcie_x4_gen2_i +( + .pci_exp_txn(pci_exp_txn), + .pci_exp_txp(pci_exp_txp), + .pci_exp_rxn(pci_exp_rxn), + .pci_exp_rxp(pci_exp_rxp), + .pipe_pclk_in(pipe_pclk_out), + .pipe_rxusrclk_in(pipe_rxusrclk_out), + .pipe_rxoutclk_in(pipe_rxoutclk_out), + .pipe_mmcm_rst_n(pipe_mmcm_rst_n), + .pipe_dclk_in(pipe_dclk_out), + .pipe_userclk1_in(pipe_userclk1_out), + .pipe_userclk2_in(pipe_userclk2_out), + .pipe_oobclk_in( pipe_oobclk_out ), + .pipe_mmcm_lock_in(pipe_mmcm_lock_out), + .pipe_txoutclk_out(pipe_txoutclk_in), + .pipe_rxoutclk_out(pipe_rxoutclk_in), + .pipe_pclk_sel_out(pipe_pclk_sel_in), + .pipe_gen3_out(pipe_gen3_in), + .user_clk_out(user_clk_out), + .user_reset_out(user_reset_out), + .user_lnk_up(user_lnk_up), + .user_app_rdy(user_app_rdy), + .s_axis_tx_tdata(s_axis_tx_tdata), + .s_axis_tx_tvalid(s_axis_tx_tvalid), + .s_axis_tx_tready(s_axis_tx_tready), + .s_axis_tx_tkeep(s_axis_tx_tkeep), + .s_axis_tx_tlast(s_axis_tx_tlast), + .s_axis_tx_tuser(s_axis_tx_tuser), + .m_axis_rx_tdata(m_axis_rx_tdata), + .m_axis_rx_tvalid(m_axis_rx_tvalid), + .m_axis_rx_tready(m_axis_rx_tready), + .m_axis_rx_tkeep(m_axis_rx_tkeep), + .m_axis_rx_tlast(m_axis_rx_tlast), + .m_axis_rx_tuser(m_axis_rx_tuser), + .tx_cfg_gnt(tx_cfg_gnt), + .rx_np_ok(rx_np_ok), + .rx_np_req(rx_np_req), + .cfg_trn_pending(cfg_trn_pending), + .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s), + .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1), + .cfg_pm_force_state_en(cfg_pm_force_state_en), + .cfg_pm_force_state(cfg_pm_force_state), + .cfg_dsn(cfg_dsn), + .cfg_turnoff_ok(cfg_turnoff_ok), + .cfg_pm_wake(cfg_pm_wake), + .cfg_pm_send_pme_to(cfg_pm_send_pme_to), + .cfg_ds_bus_number(cfg_ds_bus_number), + .cfg_ds_device_number(cfg_ds_device_number), + .cfg_ds_function_number(cfg_ds_function_number), + .fc_cpld(fc_cpld), + .fc_cplh(fc_cplh), + .fc_npd(fc_npd), + .fc_nph(fc_nph), + .fc_pd(fc_pd), + .fc_ph(fc_ph), + .fc_sel(fc_sel), + .cfg_mgmt_do(cfg_mgmt_do), + .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done), + .cfg_mgmt_di(cfg_mgmt_di), + .cfg_mgmt_byte_en(cfg_mgmt_byte_en), + .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr), + .cfg_mgmt_wr_en(cfg_mgmt_wr_en), + .cfg_mgmt_rd_en(cfg_mgmt_rd_en), + .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly), + .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw), + .tx_buf_av(tx_buf_av), + .tx_err_drop(tx_err_drop), + .tx_cfg_req(tx_cfg_req), + .cfg_status(cfg_status), + .cfg_command(cfg_command), + .cfg_dstatus(cfg_dstatus), + .cfg_dcommand(cfg_dcommand), + .cfg_lstatus(cfg_lstatus), + .cfg_lcommand(cfg_lcommand), + .cfg_dcommand2(cfg_dcommand2), + .cfg_pcie_link_state(cfg_pcie_link_state), + .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en), + .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate), + .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status), + .cfg_vc_tcvc_map(cfg_vc_tcvc_map), + .cfg_to_turnoff(cfg_to_turnoff), + .cfg_bus_number(cfg_bus_number), + .cfg_device_number(cfg_device_number), + .cfg_function_number(cfg_function_number), + .cfg_bridge_serr_en(cfg_bridge_serr_en), + .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse), + .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en), + .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en), + .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en), + .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en), + .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en), + .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en), + .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en), + .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received), + .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received), + .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received), + .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst), + .cfg_err_ecrc(cfg_err_ecrc), + .cfg_err_ur(cfg_err_ur), + .cfg_err_cpl_timeout(cfg_err_cpl_timeout), + .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect), + .cfg_err_cpl_abort(cfg_err_cpl_abort), + .cfg_err_posted(cfg_err_posted), + .cfg_err_cor(cfg_err_cor), + .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked), + .cfg_err_internal_cor(cfg_err_internal_cor), + .cfg_err_malformed(cfg_err_malformed), + .cfg_err_mc_blocked(cfg_err_mc_blocked), + .cfg_err_poisoned(cfg_err_poisoned), + .cfg_err_norecovery(cfg_err_norecovery), + .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header), + .cfg_err_cpl_rdy(cfg_err_cpl_rdy), + .cfg_err_locked(cfg_err_locked), + .cfg_err_acs(cfg_err_acs), + .cfg_err_internal_uncor(cfg_err_internal_uncor), + .cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en), + .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en), + .cfg_err_aer_headerlog(cfg_err_aer_headerlog), + .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set), + .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum), + .cfg_interrupt(cfg_interrupt), + .cfg_interrupt_rdy(cfg_interrupt_rdy), + .cfg_interrupt_assert(cfg_interrupt_assert), + .cfg_interrupt_di(cfg_interrupt_di), + .cfg_interrupt_do(cfg_interrupt_do), + .cfg_interrupt_mmenable(cfg_interrupt_mmenable), + .cfg_interrupt_msienable(cfg_interrupt_msienable), + .cfg_interrupt_msixenable(cfg_interrupt_msixenable), + .cfg_interrupt_msixfm(cfg_interrupt_msixfm), + .cfg_interrupt_stat(cfg_interrupt_stat), + .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum), + .cfg_msg_received(cfg_msg_received), + .cfg_msg_data(cfg_msg_data), + .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak), + .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit), + .cfg_msg_received_err_cor(cfg_msg_received_err_cor), + .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal), + .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal), + .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme), + .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack), + .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a), + .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b), + .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c), + .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d), + .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a), + .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b), + .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c), + .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d), + .pl_directed_link_change(pl_directed_link_change), + .pl_directed_link_width(pl_directed_link_width), + .pl_directed_link_speed(pl_directed_link_speed), + .pl_directed_link_auton(pl_directed_link_auton), + .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph), + .pl_sel_lnk_rate(pl_sel_lnk_rate), + .pl_sel_lnk_width(pl_sel_lnk_width), + .pl_ltssm_state(pl_ltssm_state), + .pl_lane_reversal_mode(pl_lane_reversal_mode), + .pl_phy_lnk_up(pl_phy_lnk_up), + .pl_tx_pm_state(pl_tx_pm_state), + .pl_rx_pm_state(pl_rx_pm_state), + .pl_link_upcfg_cap(pl_link_upcfg_cap), + .pl_link_gen2_cap(pl_link_gen2_cap), + .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported), + .pl_initial_link_width(pl_initial_link_width), + .pl_directed_change_done(pl_directed_change_done), + .pl_received_hot_rst(pl_received_hot_rst), + .pl_transmit_hot_rst(pl_transmit_hot_rst), + .pl_downstream_deemph_source(pl_downstream_deemph_source), + .pcie_drp_clk(pcie_drp_clk), + .pcie_drp_en(pcie_drp_en), + .pcie_drp_we(pcie_drp_we), + .pcie_drp_addr(pcie_drp_addr), + .pcie_drp_di(pcie_drp_di), + .pcie_drp_rdy(pcie_drp_rdy), + .pcie_drp_do(pcie_drp_do), + .sys_clk(sys_clk), + .sys_rst_n(sys_rst_n) + ); + +endmodule diff --git a/projects/ZC706/verilog/zc706_pcie_4x_gen2_pipe_clock.v b/projects/ZC706/verilog/zc706_pcie_4x_gen2_pipe_clock.v new file mode 100644 index 0000000..ff37b25 --- /dev/null +++ b/projects/ZC706/verilog/zc706_pcie_4x_gen2_pipe_clock.v @@ -0,0 +1,578 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Series-7 Integrated Block for PCI Express +// File : zc706_pcie_x4_gen2_pipe_clock.v +// Version : 3.2 +//------------------------------------------------------------------------------ +// Filename : pipe_clock.v +// Description : PIPE Clock Module for 7 Series Transceiver +// Version : 15.3 +//------------------------------------------------------------------------------ +`timescale 1ns / 1ps +//---------- PIPE Clock Module ------------------------------------------------- +(* DowngradeIPIdentifiedWarnings = "yes" *) +module zc706_pcie_x4_gen2_pipe_clock # +( + parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable + parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only + parameter PCIE_CLK_SHARING_EN= "FALSE", // Enable Clock Sharing + parameter PCIE_LANE = 1, // PCIe number of lanes + parameter PCIE_LINK_SPEED = 3, // PCIe link speed + parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency + parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency + parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency + parameter PCIE_OOBCLK_MODE = 1, // PCIe oob clock mode + parameter PCIE_DEBUG_MODE = 0 // PCIe Debug mode + +) +( + + //---------- Input ------------------------------------- + input CLK_CLK, + input CLK_TXOUTCLK, + input [PCIE_LANE-1:0] CLK_RXOUTCLK_IN, + input CLK_RST_N, + input [PCIE_LANE-1:0] CLK_PCLK_SEL, + input [PCIE_LANE-1:0] CLK_PCLK_SEL_SLAVE, + input CLK_GEN3, + + //---------- Output ------------------------------------ + output CLK_PCLK, + output CLK_PCLK_SLAVE, + output CLK_RXUSRCLK, + output [PCIE_LANE-1:0] CLK_RXOUTCLK_OUT, + output CLK_DCLK, + output CLK_OOBCLK, + output CLK_USERCLK1, + output CLK_USERCLK2, + output CLK_MMCM_LOCK + +); + + //---------- Select Clock Divider ---------------------- + localparam DIVCLK_DIVIDE = (PCIE_REFCLK_FREQ == 2) ? 1 : + (PCIE_REFCLK_FREQ == 1) ? 1 : 1; + + localparam CLKFBOUT_MULT_F = (PCIE_REFCLK_FREQ == 2) ? 4 : + (PCIE_REFCLK_FREQ == 1) ? 8 : 10; + + localparam CLKIN1_PERIOD = (PCIE_REFCLK_FREQ == 2) ? 4 : + (PCIE_REFCLK_FREQ == 1) ? 8 : 10; + + localparam CLKOUT0_DIVIDE_F = 8; + + localparam CLKOUT1_DIVIDE = 4; + + localparam CLKOUT2_DIVIDE = (PCIE_USERCLK1_FREQ == 5) ? 2 : + (PCIE_USERCLK1_FREQ == 4) ? 4 : + (PCIE_USERCLK1_FREQ == 3) ? 8 : + (PCIE_USERCLK1_FREQ == 1) ? 32 : 16; + + localparam CLKOUT3_DIVIDE = (PCIE_USERCLK2_FREQ == 5) ? 2 : + (PCIE_USERCLK2_FREQ == 4) ? 4 : + (PCIE_USERCLK2_FREQ == 3) ? 8 : + (PCIE_USERCLK2_FREQ == 1) ? 32 : 16; + + localparam CLKOUT4_DIVIDE = 20; + + localparam PCIE_GEN1_MODE = 1'b0; // PCIe link speed is GEN1 only + + //---------- Input Registers --------------------------- +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}}; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_slave_reg1 = {PCIE_LANE{1'd0}}; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1 = 1'd0; + +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}}; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_slave_reg2 = {PCIE_LANE{1'd0}}; +(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2 = 1'd0; + + //---------- Internal Signals -------------------------- + wire refclk; + wire mmcm_fb; + wire clk_125mhz; + wire clk_125mhz_buf; + wire clk_250mhz; + wire userclk1; + wire userclk2; + wire oobclk; + reg pclk_sel = 1'd0; + reg pclk_sel_slave = 1'd0; + + //---------- Output Registers -------------------------- + wire pclk_1; + wire pclk; + wire userclk1_1; + wire userclk2_1; + wire mmcm_lock; + + //---------- Generate Per-Lane Signals ----------------- + genvar i; // Index for per-lane signals + +//---------- Input FF ---------------------------------------------------------- +always @ (posedge pclk) +begin + + if (!CLK_RST_N) + begin + //---------- 1st Stage FF -------------------------- + pclk_sel_reg1 <= {PCIE_LANE{1'd0}}; + pclk_sel_slave_reg1 <= {PCIE_LANE{1'd0}}; + gen3_reg1 <= 1'd0; + //---------- 2nd Stage FF -------------------------- + pclk_sel_reg2 <= {PCIE_LANE{1'd0}}; + pclk_sel_slave_reg2 <= {PCIE_LANE{1'd0}}; + gen3_reg2 <= 1'd0; + end + else + begin + //---------- 1st Stage FF -------------------------- + pclk_sel_reg1 <= CLK_PCLK_SEL; + pclk_sel_slave_reg1 <= CLK_PCLK_SEL_SLAVE; + gen3_reg1 <= CLK_GEN3; + //---------- 2nd Stage FF -------------------------- + pclk_sel_reg2 <= pclk_sel_reg1; + pclk_sel_slave_reg2 <= pclk_sel_slave_reg1; + gen3_reg2 <= gen3_reg1; + end + +end + +//---------- Select Reference clock or TXOUTCLK -------------------------------- +generate if ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3)) + + begin : refclk_i + + //---------- Select Reference Clock ---------------------------------------- + BUFG refclk_i + ( + + //---------- Input ------------------------------------- + .I (CLK_CLK), + //---------- Output ------------------------------------ + .O (refclk) + + ); + + end + +else + + begin : txoutclk_i + + //---------- Select TXOUTCLK ----------------------------------------------- + BUFG txoutclk_i + ( + + //---------- Input ------------------------------------- + .I (CLK_TXOUTCLK), + //---------- Output ------------------------------------ + .O (refclk) + + ); + + end + +endgenerate + +//---------- MMCM -------------------------------------------------------------- +MMCME2_ADV # +( + + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (DIVCLK_DIVIDE), + .CLKFBOUT_MULT_F (CLKFBOUT_MULT_F), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (CLKOUT0_DIVIDE_F), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), + .CLKOUT2_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), + .CLKOUT3_PHASE (0.000), + .CLKOUT3_DUTY_CYCLE (0.500), + .CLKOUT3_USE_FINE_PS ("FALSE"), + .CLKOUT4_DIVIDE (CLKOUT4_DIVIDE), + .CLKOUT4_PHASE (0.000), + .CLKOUT4_DUTY_CYCLE (0.500), + .CLKOUT4_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (CLKIN1_PERIOD), + .REF_JITTER1 (0.010) + +) +mmcm_i +( + + //---------- Input ------------------------------------ + .CLKIN1 (refclk), + .CLKIN2 (1'd0), // not used, comment out CLKIN2 if it cause implementation issues + //.CLKIN2 (refclk), // not used, comment out CLKIN2 if it cause implementation issues + .CLKINSEL (1'd1), + .CLKFBIN (mmcm_fb), + .RST (!CLK_RST_N), + .PWRDWN (1'd0), + + //---------- Output ------------------------------------ + .CLKFBOUT (mmcm_fb), + .CLKFBOUTB (), + .CLKOUT0 (clk_125mhz), + .CLKOUT0B (), + .CLKOUT1 (clk_250mhz), + .CLKOUT1B (), + .CLKOUT2 (userclk1), + .CLKOUT2B (), + .CLKOUT3 (userclk2), + .CLKOUT3B (), + .CLKOUT4 (oobclk), + .CLKOUT5 (), + .CLKOUT6 (), + .LOCKED (mmcm_lock), + + //---------- Dynamic Reconfiguration ------------------- + .DCLK ( 1'd0), + .DADDR ( 7'd0), + .DEN ( 1'd0), + .DWE ( 1'd0), + .DI (16'd0), + .DO (), + .DRDY (), + + //---------- Dynamic Phase Shift ----------------------- + .PSCLK (1'd0), + .PSEN (1'd0), + .PSINCDEC (1'd0), + .PSDONE (), + + //---------- Status ------------------------------------ + .CLKINSTOPPED (), + .CLKFBSTOPPED () + +); + +//---------- Select PCLK MUX --------------------------------------------------- +generate if (PCIE_LINK_SPEED != 1) + + begin : pclk_i1_bufgctrl + //---------- PCLK Mux ---------------------------------- + BUFGCTRL pclk_i1 + ( + //---------- Input --------------------------------- + .CE0 (1'd1), + .CE1 (1'd1), + .I0 (clk_125mhz), + .I1 (clk_250mhz), + .IGNORE0 (1'd0), + .IGNORE1 (1'd0), + .S0 (~pclk_sel), + .S1 ( pclk_sel), + //---------- Output -------------------------------- + .O (pclk_1) + ); + end + +else + + //---------- Select PCLK Buffer ------------------------ + begin : pclk_i1_bufg + //---------- PCLK Buffer ------------------------------- + BUFG pclk_i1 + ( + //---------- Input --------------------------------- + .I (clk_125mhz), + //---------- Output -------------------------------- + .O (clk_125mhz_buf) + ); + assign pclk_1 = clk_125mhz_buf; + end + +endgenerate + +//---------- Select PCLK MUX for Slave--------------------------------------------------- +generate if(PCIE_CLK_SHARING_EN == "FALSE") + //---------- PCLK MUX for Slave------------------// + begin : pclk_slave_disable + assign CLK_PCLK_SLAVE = 1'b0; + end + +else if (PCIE_LINK_SPEED != 1) + + begin : pclk_slave_bufgctrl + //---------- PCLK Mux ---------------------------------- + BUFGCTRL pclk_slave + ( + //---------- Input --------------------------------- + .CE0 (1'd1), + .CE1 (1'd1), + .I0 (clk_125mhz), + .I1 (clk_250mhz), + .IGNORE0 (1'd0), + .IGNORE1 (1'd0), + .S0 (~pclk_sel_slave), + .S1 ( pclk_sel_slave), + //---------- Output -------------------------------- + .O (CLK_PCLK_SLAVE) + ); + end + +else + + //---------- Select PCLK Buffer ------------------------ + begin : pclk_slave_bufg + //---------- PCLK Buffer ------------------------------- + BUFG pclk_slave + ( + //---------- Input --------------------------------- + .I (clk_125mhz), + //---------- Output -------------------------------- + .O (CLK_PCLK_SLAVE) + ); + end + +endgenerate + +//---------- Generate RXOUTCLK Buffer for Debug -------------------------------- +generate if ((PCIE_DEBUG_MODE == 1) || (PCIE_ASYNC_EN == "TRUE")) + + begin : rxoutclk_per_lane + //---------- Generate per Lane ------------------------- + for (i=0; i Date: Tue, 23 May 2023 20:55:44 +0300 Subject: [PATCH 2/5] Add ZC706 PCIe Driver --- sources/zc706_driver/Makefile | 13 ++ sources/zc706_driver/cdev.c | 97 ++++++++++++++ sources/zc706_driver/cdev.h | 38 ++++++ sources/zc706_driver/softmc_dma.c | 207 ++++++++++++++++++++++++++++++ sources/zc706_driver/softmc_dma.h | 67 ++++++++++ sources/zc706_driver/test/test.c | 43 +++++++ 6 files changed, 465 insertions(+) create mode 100644 sources/zc706_driver/Makefile create mode 100644 sources/zc706_driver/cdev.c create mode 100644 sources/zc706_driver/cdev.h create mode 100644 sources/zc706_driver/softmc_dma.c create mode 100644 sources/zc706_driver/softmc_dma.h create mode 100644 sources/zc706_driver/test/test.c diff --git a/sources/zc706_driver/Makefile b/sources/zc706_driver/Makefile new file mode 100644 index 0000000..3bfa404 --- /dev/null +++ b/sources/zc706_driver/Makefile @@ -0,0 +1,13 @@ +CONFIG_MODULE_SIG=n +CONFIG_MODULE_SIG_ALL=n + +TARGET_MODULE := dma_softmc + +$(TARGET_MODULE)-objs += softmc_dma.o cdev.o +obj-m += $(TARGET_MODULE).o + +all: + make -C /usr/src/linux-headers-$(shell uname -r)/ M=$(shell pwd) modules + +clean: + make -C /usr/src/linux-headers-$(shell uname -r)/ M=$(shell pwd) clean \ No newline at end of file diff --git a/sources/zc706_driver/cdev.c b/sources/zc706_driver/cdev.c new file mode 100644 index 0000000..32c3209 --- /dev/null +++ b/sources/zc706_driver/cdev.c @@ -0,0 +1,97 @@ +#include "cdev.h" +#include "softmc_dma.h" + +static int read_offset = 0; + +static int softmc_uevent(struct device *dev, struct kobj_uevent_env *env) { + add_uevent_var(env, "DEVMODE=%#o", 0666); + return 0; +} + +void softmc_cdev_init(void) { + int err; + dev_t dev; + softmc_class = NULL; + err = alloc_chrdev_region(&dev, 0, 1, "softmc_cdev"); + dev_major = MAJOR(dev); + softmc_class = class_create(THIS_MODULE, "softmc_cdev"); + softmc_class->dev_uevent = softmc_uevent; + cdev_init(&driver_data.cdev, &softmc_fops); + driver_data.cdev.owner = THIS_MODULE; + cdev_add(&driver_data.cdev, MKDEV(dev_major, 0), 1); + device_create(softmc_class, NULL, MKDEV(dev_major, 0), NULL, "softmc_cdev", 0); +} + +void softmc_cdev_exit(void) { + device_destroy(softmc_class, MKDEV(dev_major, 0)); + class_unregister(softmc_class); + class_destroy(softmc_class); + unregister_chrdev_region(MKDEV(dev_major, 0), 1); +} + +int softmc_open(struct inode *inode, struct file *file) { + printk("SOFTMC: Device open\n"); + return 0; +} + +int softmc_release(struct inode *inode, struct file *file) { + printk("SOFTMC: Device close\n"); + return 0; +} + +long softmc_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { + printk("SOFTMC: Device ioctl\n"); + return 0; +} + +ssize_t softmc_read(struct file *file, char __user *buf, size_t count, loff_t *offset) { + int i; + int n; + size_t remaining_bytes = count; + int read_bytes = 0; + char cdev_buf[CDEV_BUF_LEN]; + #ifdef DEBUG + printk("READ CALL with count %d.\n", count); + #endif + while (remaining_bytes > 0) { + size_t step_size = remaining_bytes < CDEV_BUF_LEN ? remaining_bytes : CDEV_BUF_LEN; + n = read_dma_buffer(cdev_buf, step_size); + copy_to_user((buf + read_bytes), cdev_buf, n); + if (n < step_size) { + DBG("Requesting data.\n"); + n = load_recv_buffer(remaining_bytes); + } + read_bytes += n; + remaining_bytes -= n; + } + #ifdef DEBUG + printk("READ CALL completed with %d reads.\n", read_bytes); + #endif + return read_bytes; +} + +ssize_t softmc_write(struct file *file, const char __user *buf, size_t count, loff_t *offset) { + int n; + size_t remaining_bytes = count; + int sent_bytes = 0; + char cdev_buf[CDEV_BUF_LEN]; + #ifdef DEBUG + printk("WRITE CALL with count %d.\n", count); + #endif + while (remaining_bytes > 0) { + size_t step_size = remaining_bytes < CDEV_BUF_LEN ? remaining_bytes : CDEV_BUF_LEN; + copy_from_user(cdev_buf, (buf + sent_bytes), step_size); + n = write_dma_buffer(cdev_buf, step_size); + if (n < step_size) { + DBG("Flushing buffer.\n"); + flush_send_buffer(); + } + sent_bytes += n; + remaining_bytes -= n; + } + #ifdef DEBUG + printk("WRITE CALL completed with %d sent bytes.\n", sent_bytes); + #endif + flush_send_buffer(); + return sent_bytes; +} \ No newline at end of file diff --git a/sources/zc706_driver/cdev.h b/sources/zc706_driver/cdev.h new file mode 100644 index 0000000..43724dc --- /dev/null +++ b/sources/zc706_driver/cdev.h @@ -0,0 +1,38 @@ +#ifndef CDEV_H +#define CDEV_H + +#include +#include +#include +#include +#include +#include + +#define CDEV_BUF_LEN 256 + +struct softmc_data { + struct cdev cdev; +}; + +void softmc_cdev_init(void); +void softmc_cdev_exit(void); +int softmc_open(struct inode *inode, struct file *file); +int softmc_release(struct inode *inode, struct file *file); +long softmc_ioctl(struct file *file, unsigned int cmd, unsigned long arg); +ssize_t softmc_read(struct file *file, char __user *buf, size_t count, loff_t *offset); +ssize_t softmc_write(struct file *file, const char __user *buf, size_t count, loff_t *offset); + +static const struct file_operations softmc_fops = { + .owner = THIS_MODULE, + .open = softmc_open, + .release = softmc_release, + .unlocked_ioctl = softmc_ioctl, + .read = softmc_read, + .write = softmc_write +}; + +static int dev_major; +static struct class *softmc_class; +static struct softmc_data driver_data; + +#endif //CDEV_H \ No newline at end of file diff --git a/sources/zc706_driver/softmc_dma.c b/sources/zc706_driver/softmc_dma.c new file mode 100644 index 0000000..8579740 --- /dev/null +++ b/sources/zc706_driver/softmc_dma.c @@ -0,0 +1,207 @@ +#include "softmc_dma.h" +#include "cdev.h" + +static irqreturn_t irq_handler(int irq, void *dev_id) { + int i; + disable_interrupt(); + DBG("Interrupt received.\n"); + printk("IRQ: %d DEV_ID:%4x\n", irq, *((int *)dev_id)); + last_cmd_done = TRUE; + DBG("Waking up devices.\n"); + wake_up_all(&softmc_wq); + enable_interrupt(); + return IRQ_HANDLED; +} + +static int __init init_softmc_dma(void) { + printk(KERN_INFO "Loading DMA Module.\n"); + printk("---------------------------\n\n\n"); + int nvec; + int err; + device_id = (int *) kmalloc(sizeof(int), GFP_KERNEL); + dev = pci_get_device(VENDOR_ID, DEVICE_ID, dev); + if (dev == NULL) { + printk("pci_softmc - device not available\n"); + return -1; + } + if (pci_enable_device(dev) < 0) { + printk("pci_softmc - can not enable device\n"); + return -1; + } + u16 val = 0; + pci_read_config_word(dev, PCI_VENDOR_ID, &val); + printk("pci_softmc - VENDOR ID: 0x%x\n", val); + pci_read_config_word(dev, PCI_DEVICE_ID, &val); + *device_id = val; + printk("pci_softmc - DEVICE ID: 0x%x\n", val); + pci_read_config_word(dev, PCI_COMMAND, &val); + printk("pci_softmc - COMMAND: 0x%x\n", val); + pci_release_region(dev, 0); + if (pci_request_region(dev, 0, "pci_softmc_bar0")) { + printk("pci_softmc - could not request BAR0\n"); + return -1; + } + softmc_bar0 = pci_iomap(dev, 0, pci_resource_len(dev, 0)); + printk("pci_softmc - bar size is %lld\n", pci_resource_len(dev, 0)); + printk("pci_softmc - current_state: %d\n", dev->current_state); + printk("pci_softmc - pci_msi_vec_count: %d\n", pci_msi_vec_count(dev)); + printk("pci_softmc - msi_enabled: %d\n", dev->msi_enabled); + printk("pci_softmc - msix_enabled: %d\n", dev->msix_enabled); + printk("pci_softmc - dev->irq: %d\n", dev->irq); + err = request_irq(dev->irq, irq_handler, 0, "PCI_FPGA_SOFTMC", device_id); + printk("pci_softmc - request IRQ: %d\n", err); + send_buff = create_buffer(DMA_BUF_SIZE); + recv_buff = create_buffer(DMA_BUF_SIZE); + init_waitqueue_head(&softmc_wq); + softmc_cdev_init(); + txn_reg = (int *) kmalloc(sizeof(int), GFP_DMA); + uint64_t txn_reg_addr = virt_to_phys(txn_reg); + iowrite32((u32) (txn_reg_addr >> 32), softmc_bar0 + OFFSET_TXN_REG_LO_ADDR); + iowrite32((u32) (txn_reg_addr & 0xFFFFFFFF), softmc_bar0 + OFFSET_TXN_REG_HI_ADDR); + printk(KERN_INFO "Loaded DMA Module.\n"); + enable_interrupt(); + return 0; +} + +static void __exit exit_softmc_dma(void) { + printk(KERN_INFO "Unloading DMA Module.\n"); + free_irq(dev->irq, device_id); + printk("pci_softmc - freed IRQ\n"); + pci_release_region(dev, 0); + printk("pci_softmc - released BARs\n"); + softmc_cdev_exit(); + destroy_buffer(send_buff); + destroy_buffer(recv_buff); + printk(KERN_INFO "Unloaded DMA Module.\n"); +} + +int write_dma_buffer(void *from, int size) { + dma_buffer_t *buf = send_buff; + if (!buf) { + printk("Invalid dma buffer.\n"); + } + if (!from) { + printk("Invalid target buffer.\n"); + } + const char *src = from; + int write_count = 0; + int available_bytes = buf->capacity - buf->data_count; + if (size > available_bytes) { + size = available_bytes; + } +#ifdef DEBUG + printk("size: %d\tavailable_bytes: %d\n", size, available_bytes); +#endif + while (write_count < size) { + writeb(*(src + write_count), (buf->buffer + ((buf->start_off + write_count) % buf->capacity))); + write_count++; + } + buf->data_count += write_count; +#ifdef DEBUG + printk("WRITING DMA BUFFER:\n"); + printk("start_off: %d\tdata_count: %d\n", buf->start_off, buf->data_count); +#endif + return write_count; +} + +int read_dma_buffer(void *to, int size) { + dma_buffer_t *buf = recv_buff; + if (!buf) { + printk("Invalid dma buffer.\n"); + } + if (!to) { + printk("Invalid target buffer.\n"); + } + int read_count = 0; + int available_bytes = buf->data_count; + char *dst = to; + if (size > available_bytes) { + size = available_bytes; + } +#ifdef DEBUG + printk("size: %d\tavailable_bytes: %d\n", size, available_bytes); +#endif + while (read_count < size) { + writeb(*(buf->buffer + ((buf->start_off + read_count) % buf->capacity)), (dst + read_count)); + read_count++; + } + buf->start_off = (buf->start_off + read_count) % buf->capacity; + buf->data_count -= read_count; +#ifdef DEBUG + printk("READ DMA BUFFER:\n"); + printk("start_off: %d\tdata_count: %d\n", buf->start_off, buf->data_count); +#endif + return read_count; +} + +dma_buffer_t *create_buffer(unsigned long size) { + dma_buffer_t *buf = (dma_buffer_t *) kmalloc(sizeof(dma_buffer_t), GFP_KERNEL); + if (!buf) { + printk("Could not create dma_buffer_t\n"); + return NULL; + } + buf->buffer = (void *) kmalloc(size, GFP_DMA); + if (!buf->buffer) { + printk("Could not create buffer\n"); + return NULL; + } + buf->capacity = size; + buf->data_count = 0; + buf->start_off = 0; + return buf; +} + +void destroy_buffer(dma_buffer_t *buf) { + kfree(buf->buffer); + kfree(buf); +} + +int load_recv_buffer(int size) { + int i; + int available_size = recv_buff->capacity - recv_buff->data_count; + if (size > available_size) { + size = available_size; + } + last_cmd = CMD_WRITE; + last_cmd_done = FALSE; + uint64_t send_phy_addr = virt_to_phys(recv_buff->buffer); + iowrite32((u32) (send_phy_addr >> 32), softmc_bar0 + 4); + iowrite32((u32) (send_phy_addr & 0xFFFFFFFF), softmc_bar0 + 8); + iowrite32((u32) ((sizeof(char) * available_size) << CMD_LEN_OFFSET | CMD_WRITE), softmc_bar0); + recv_buff->start_off = 0; + recv_buff->data_count = size; + DBG("Waiting for DMA load\n"); + wait_event_interruptible(softmc_wq, last_cmd_done); + DBG("DMA loaded\n"); + return size; +} + +void flush_send_buffer(void) { + last_cmd = CMD_READ; + last_cmd_done = FALSE; + uint64_t send_phy_addr = virt_to_phys(send_buff->buffer); + iowrite32((u32) (send_phy_addr >> 32), softmc_bar0 + 4); + iowrite32((u32) (send_phy_addr & 0xFFFFFFFF), softmc_bar0 + 8); + iowrite32((u32) ((sizeof(char) * send_buff->data_count) << CMD_LEN_OFFSET | CMD_READ), softmc_bar0); + send_buff->data_count = 0; + DBG("Waiting for DMA write\n"); + wait_event_interruptible(softmc_wq, last_cmd_done); + DBG("DMA written\n"); +} + +void disable_interrupt(void) { + u16 reg; + pci_read_config_word(dev, PCI_COMMAND, ®); + reg = reg | (1ULL << INTR_BIT_OFFSET); + pci_write_config_word(dev, PCI_COMMAND, reg); +} + +void enable_interrupt(void) { + u16 reg; + pci_read_config_word(dev, PCI_COMMAND, ®); + reg = reg & ~(1ULL << INTR_BIT_OFFSET); + pci_write_config_word(dev, PCI_COMMAND, reg); +} + +module_init(init_softmc_dma); +module_exit(exit_softmc_dma); \ No newline at end of file diff --git a/sources/zc706_driver/softmc_dma.h b/sources/zc706_driver/softmc_dma.h new file mode 100644 index 0000000..b78f12f --- /dev/null +++ b/sources/zc706_driver/softmc_dma.h @@ -0,0 +1,67 @@ +#ifndef SOFTMC_DMA_H +#define SOFTMC_DMA_H + +#include +#include +#include +#include +#include +#include +#include +#include + +#define TRUE (1 == 1) +#define FALSE (1 != 1) + +#define VENDOR_ID 0x10EE +#define DEVICE_ID 0x7024 +#define BUF_LEN 64 +#define CMD_LEN_OFFSET 16 +#define CMD_WRITE 0x0003 +#define CMD_READ 0x0001 +#define DMA_BUF_SIZE 4096 +#define INTR_BIT_OFFSET 10 +#define BUS_BIT_OFFSET 2 + +#define OFFSET_TXN_REG_LO_ADDR 5 +#define OFFSET_TXN_REG_HI_ADDR 4 + +#define DEBUG + +#ifdef DEBUG +#define DBG(msg) printk("%s", msg) +#else +#define DBG(msg) while(false) +#endif + +MODULE_AUTHOR("Oguzhan Canpolat"); +MODULE_LICENSE("GPL"); + +typedef struct { + char *buffer; + int data_count; + int start_off; + int capacity; +} dma_buffer_t; + +static dma_buffer_t *send_buff; +static dma_buffer_t *recv_buff; +static int *txn_reg; +static int last_cmd; +static int last_cmd_done; +static struct pci_dev *dev; +static int *device_id; +static void __iomem *softmc_bar0; +static wait_queue_head_t softmc_wq; + +static irqreturn_t irq_handler(int irq, void *dev_id); +int load_recv_buffer(int bytes); +void flush_send_buffer(void); +int write_dma_buffer(void *from, int size); +int read_dma_buffer(void *to, int size); +dma_buffer_t *create_buffer(unsigned long size); +void destroy_buffer(dma_buffer_t *buf); +void disable_interrupt(void); +void enable_interrupt(void); + +#endif //SOFTMC_DMA_H \ No newline at end of file diff --git a/sources/zc706_driver/test/test.c b/sources/zc706_driver/test/test.c new file mode 100644 index 0000000..9ae4126 --- /dev/null +++ b/sources/zc706_driver/test/test.c @@ -0,0 +1,43 @@ +#include +#include + +#define BUF_LEN 4096*4 + +void read_test() { + char buf[BUF_LEN]; + for (int i = 0; i < BUF_LEN; i++) { + buf[i] = i; + } + FILE *fp = fopen("/dev/softmc_cdev", "r"); + if (!fp) { + printf("No file\n"); + return; + } + printf("Reading once\n"); + fread(buf, sizeof(char), BUF_LEN, fp); + printf("%s", buf); + printf("\n--------\n"); + fread(buf, sizeof(char), BUF_LEN, fp); + printf("%s", buf); + printf("\n--------\n"); + fclose(fp); +} + +void write_test() { + char buf[BUF_LEN]; + for (int i = 0; i < BUF_LEN; i++) { + buf[i] = i; + } + FILE *fp = fopen("/dev/softmc_cdev", "w"); + if (!fp) { + printf("No file\n"); + return; + } + fwrite(buf, sizeof(char), BUF_LEN, fp); + fclose(fp); +} + +int main() { + write_test(); + return 0; +} \ No newline at end of file From 1554bd5bd10a362de9504605e421d7859a58a6d9 Mon Sep 17 00:00:00 2001 From: kirbyydoge Date: Sat, 31 Aug 2024 17:46:10 +0200 Subject: [PATCH 3/5] Add ZC706 to platform api and create ZC706 driver README --- projects/ZC706/verilog/pcie_top.v | 1211 +++++++++++++++-------------- sources/api/board.cpp | 31 + sources/api/board.h | 3 +- sources/zc706_driver/README.md | 13 + 4 files changed, 653 insertions(+), 605 deletions(-) create mode 100644 sources/zc706_driver/README.md diff --git a/projects/ZC706/verilog/pcie_top.v b/projects/ZC706/verilog/pcie_top.v index 2e5d55a..3c15765 100644 --- a/projects/ZC706/verilog/pcie_top.v +++ b/projects/ZC706/verilog/pcie_top.v @@ -57,650 +57,653 @@ `include "project.vh" // `define DEBUG +// `define ILA_CORES `timescale 1ns / 1ps (* DowngradeIPIdentifiedWarnings = "yes" *) module pcie_top # ( - parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup - parameter EXT_PIPE_SIM = "FALSE", // This Parameter has effect on selecting Enable External PIPE Interface in GUI. - parameter PCIE_EXT_CLK = "TRUE", // Use External Clocking Module - parameter PCIE_EXT_GT_COMMON = "FALSE", - parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz - parameter C_DATA_WIDTH = 64, // RX/TX interface data width - parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // TSTRB width + parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup + parameter EXT_PIPE_SIM = "FALSE", // This Parameter has effect on selecting Enable External PIPE Interface in GUI. + parameter PCIE_EXT_CLK = "TRUE", // Use External Clocking Module + parameter PCIE_EXT_GT_COMMON = "FALSE", + parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz + parameter C_DATA_WIDTH = 64, // RX/TX interface data width + parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // TSTRB width ) ( - output [3:0] pci_exp_txp, - output [3:0] pci_exp_txn, - input [3:0] pci_exp_rxp, - input [3:0] pci_exp_rxn, + output [3:0] pci_exp_txp, + output [3:0] pci_exp_txn, + input [3:0] pci_exp_rxp, + input [3:0] pci_exp_rxn, - output led_0, - output led_2, - output led_3, + output led_0, + output led_2, + output led_3, `ifndef DEBUG - output [`SOFTMC_STREAM_WIDTH-1:0] softmc_h2c_tdata, - output [`SOFTMC_STREAM_KEEP-1:0] softmc_h2c_tkeep, - output softmc_h2c_tvalid, - input softmc_h2c_tready, - output softmc_h2c_tlast, - - input [`SOFTMC_STREAM_WIDTH-1:0] softmc_c2h_tdata, - input [`SOFTMC_STREAM_KEEP-1:0] softmc_c2h_tkeep, - input softmc_c2h_tvalid, - output softmc_c2h_tready, - input softmc_c2h_tlast, - - output user_clk_o, - output user_reset_o, + output [`SOFTMC_STREAM_WIDTH-1:0] softmc_h2c_tdata, + output [`SOFTMC_STREAM_KEEP-1:0] softmc_h2c_tkeep, + output softmc_h2c_tvalid, + input softmc_h2c_tready, + output softmc_h2c_tlast, + + input [`SOFTMC_STREAM_WIDTH-1:0] softmc_c2h_tdata, + input [`SOFTMC_STREAM_KEEP-1:0] softmc_c2h_tkeep, + input softmc_c2h_tvalid, + output softmc_c2h_tready, + input softmc_c2h_tlast, + + output user_clk_o, + output user_reset_o, `endif - input sys_clk_p, - input sys_clk_n, - input sys_rst_n + input sys_clk_p, + input sys_clk_n, + input sys_rst_n ); // Wire Declarations - wire pipe_mmcm_rst_n; - - wire user_clk; - wire user_reset; - wire user_lnk_up; - - assign user_clk_o = user_clk; - assign user_reset_o = user_reset; - - // Tx - wire s_axis_tx_tready; - wire [3:0] s_axis_tx_tuser; - wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata; - wire [KEEP_WIDTH-1:0] s_axis_tx_tkeep; - wire s_axis_tx_tlast; - wire s_axis_tx_tvalid; - - // Rx - wire [C_DATA_WIDTH-1:0] m_axis_rx_tdata; - wire [KEEP_WIDTH-1:0] m_axis_rx_tkeep; - wire m_axis_rx_tlast; - wire m_axis_rx_tvalid; - wire m_axis_rx_tready; - wire [21:0] m_axis_rx_tuser; - - wire tx_cfg_gnt; - wire rx_np_ok; - wire rx_np_req; - wire cfg_turnoff_ok; - wire cfg_trn_pending; - wire cfg_pm_halt_aspm_l0s; - wire cfg_pm_halt_aspm_l1; - wire cfg_pm_force_state_en; - wire [1:0] cfg_pm_force_state; - wire cfg_pm_wake; - wire [63:0] cfg_dsn; - - // Flow Control - wire [2:0] fc_sel; - - //------------------------------------------------------- - // Configuration (CFG) Interface - //------------------------------------------------------- - wire cfg_err_ecrc; - wire cfg_err_cor; - wire cfg_err_ur; - wire cfg_err_cpl_timeout; - wire cfg_err_cpl_abort; - wire cfg_err_cpl_unexpect; - wire cfg_err_posted; - wire cfg_err_locked; - wire [47:0] cfg_err_tlp_cpl_header; - wire [127:0] cfg_err_aer_headerlog; - wire [4:0] cfg_aer_interrupt_msgnum; - - wire cfg_interrupt; - wire cfg_interrupt_rdy; - wire cfg_interrupt_assert; - wire [7:0] cfg_interrupt_di; - wire cfg_interrupt_stat; - wire [4:0] cfg_pciecap_interrupt_msgnum; - wire cfg_interrupt_msienable; - - wire cfg_to_turnoff; - wire [7:0] cfg_bus_number; - wire [4:0] cfg_device_number; - wire [2:0] cfg_function_number; - - wire [31:0] cfg_mgmt_di; - wire [31:0] cfg_mgmt_do; - wire [3:0] cfg_mgmt_byte_en; - wire [9:0] cfg_mgmt_dwaddr; - wire cfg_mgmt_wr_en; - wire cfg_mgmt_rd_en; - wire cfg_mgmt_rd_wr_done; - wire cfg_mgmt_wr_readonly; - - wire [15:0] cfg_dcommand; - wire [15:0] cfg_command; - - //------------------------------------------------------- - // Physical Layer Control and Status (PL) Interface - //------------------------------------------------------- - wire pl_directed_link_auton; - wire [1:0] pl_directed_link_change; - wire pl_directed_link_speed; - wire [1:0] pl_directed_link_width; - wire pl_upstream_prefer_deemph; - - wire sys_rst_n_c; + wire pipe_mmcm_rst_n; + + wire user_clk; + wire user_reset; + wire user_lnk_up; + + assign user_clk_o = user_clk; + assign user_reset_o = user_reset; + + // Tx + wire s_axis_tx_tready; + wire [3:0] s_axis_tx_tuser; + wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata; + wire [KEEP_WIDTH-1:0] s_axis_tx_tkeep; + wire s_axis_tx_tlast; + wire s_axis_tx_tvalid; + + // Rx + wire [C_DATA_WIDTH-1:0] m_axis_rx_tdata; + wire [KEEP_WIDTH-1:0] m_axis_rx_tkeep; + wire m_axis_rx_tlast; + wire m_axis_rx_tvalid; + wire m_axis_rx_tready; + wire [21:0] m_axis_rx_tuser; + + wire tx_cfg_gnt; + wire rx_np_ok; + wire rx_np_req; + wire cfg_turnoff_ok; + wire cfg_trn_pending; + wire cfg_pm_halt_aspm_l0s; + wire cfg_pm_halt_aspm_l1; + wire cfg_pm_force_state_en; + wire [1:0] cfg_pm_force_state; + wire cfg_pm_wake; + wire [63:0] cfg_dsn; + + // Flow Control + wire [2:0] fc_sel; + + //------------------------------------------------------- + // Configuration (CFG) Interface + //------------------------------------------------------- + wire cfg_err_ecrc; + wire cfg_err_cor; + wire cfg_err_ur; + wire cfg_err_cpl_timeout; + wire cfg_err_cpl_abort; + wire cfg_err_cpl_unexpect; + wire cfg_err_posted; + wire cfg_err_locked; + wire [47:0] cfg_err_tlp_cpl_header; + wire [127:0] cfg_err_aer_headerlog; + wire [4:0] cfg_aer_interrupt_msgnum; + + wire cfg_interrupt; + wire cfg_interrupt_rdy; + wire cfg_interrupt_assert; + wire [7:0] cfg_interrupt_di; + wire cfg_interrupt_stat; + wire [4:0] cfg_pciecap_interrupt_msgnum; + wire cfg_interrupt_msienable; + + wire cfg_to_turnoff; + wire [7:0] cfg_bus_number; + wire [4:0] cfg_device_number; + wire [2:0] cfg_function_number; + + wire [31:0] cfg_mgmt_di; + wire [31:0] cfg_mgmt_do; + wire [3:0] cfg_mgmt_byte_en; + wire [9:0] cfg_mgmt_dwaddr; + wire cfg_mgmt_wr_en; + wire cfg_mgmt_rd_en; + wire cfg_mgmt_rd_wr_done; + wire cfg_mgmt_wr_readonly; + + wire [15:0] cfg_dcommand; + wire [15:0] cfg_command; + + //------------------------------------------------------- + // Physical Layer Control and Status (PL) Interface + //------------------------------------------------------- + wire pl_directed_link_auton; + wire [1:0] pl_directed_link_change; + wire pl_directed_link_speed; + wire [1:0] pl_directed_link_width; + wire pl_upstream_prefer_deemph; + + wire sys_rst_n_c; // Register Declaration - reg user_reset_q; - reg user_lnk_up_q; - reg [25:0] user_clk_heartbeat = 'h0; + reg user_reset_q; + reg user_lnk_up_q; + reg [25:0] user_clk_heartbeat = 'h0; // Local Parameters - localparam TCQ = 1; - localparam USER_CLK_FREQ = 3; - localparam USER_CLK2_DIV2 = "FALSE"; - localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "TRUE") ? (USER_CLK_FREQ == 4) ? 3 : (USER_CLK_FREQ == 3) ? 2 : USER_CLK_FREQ: USER_CLK_FREQ; + localparam TCQ = 1; + localparam USER_CLK_FREQ = 3; + localparam USER_CLK2_DIV2 = "FALSE"; + localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "TRUE") ? (USER_CLK_FREQ == 4) ? 3 : (USER_CLK_FREQ == 3) ? 2 : USER_CLK_FREQ: USER_CLK_FREQ; //-----------------------------I/O BUFFERS------------------------// - IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_rst_n)); + IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_rst_n)); - IBUFDS_GTE2 refclk_ibuf (.O(sys_clk), .ODIV2(), .I(sys_clk_p), .CEB(1'b0), .IB(sys_clk_n)); + IBUFDS_GTE2 refclk_ibuf (.O(sys_clk), .ODIV2(), .I(sys_clk_p), .CEB(1'b0), .IB(sys_clk_n)); - OBUF led_0_obuf (.O(led_0), .I(!user_reset)); - OBUF led_2_obuf (.O(led_2), .I(user_lnk_up)); - OBUF led_3_obuf (.O(led_3), .I(user_clk_heartbeat[25])); + OBUF led_0_obuf (.O(led_0), .I(!user_reset)); + OBUF led_2_obuf (.O(led_2), .I(user_lnk_up)); + OBUF led_3_obuf (.O(led_3), .I(user_clk_heartbeat[25])); - always @(posedge user_clk) begin - user_reset_q <= user_reset; - user_lnk_up_q <= user_lnk_up; - end + always @(posedge user_clk) begin + user_reset_q <= user_reset; + user_lnk_up_q <= user_lnk_up; + end - // Create a Clock Heartbeat on LED #3 - always @(posedge user_clk) begin - user_clk_heartbeat <= #TCQ user_clk_heartbeat + 1'b1; - end + // Create a Clock Heartbeat on LED #3 + always @(posedge user_clk) begin + user_clk_heartbeat <= #TCQ user_clk_heartbeat + 1'b1; + end - assign pipe_mmcm_rst_n = 1'b1; + assign pipe_mmcm_rst_n = 1'b1; `ifdef DEBUG - localparam DATA_LIMIT = 'd1024; - wire [`SOFTMC_STREAM_WIDTH-1:0] softmc_h2c_tdata; - wire [`SOFTMC_STREAM_KEEP-1:0] softmc_h2c_tkeep; - wire softmc_h2c_tvalid; - reg softmc_h2c_tready; - wire softmc_h2c_tlast; - - reg [`SOFTMC_STREAM_WIDTH-1:0] softmc_c2h_tdata; - reg [`SOFTMC_STREAM_KEEP-1:0] softmc_c2h_tkeep; - reg softmc_c2h_tvalid; - wire softmc_c2h_tready; - reg softmc_c2h_tlast; - - reg [15:0] data_count; - reg [7:0] data_base; - - integer data_loop_i; - always @(posedge user_clk) begin - if (user_reset_q) begin - softmc_c2h_tdata <= 0; - softmc_c2h_tkeep <= 0; - softmc_c2h_tvalid <= 0; - softmc_c2h_tlast <= 0; - softmc_h2c_tready <= 0; - data_count <= 0; - data_base <= 0; - end - else begin - softmc_c2h_tkeep <= {`SOFTMC_STREAM_KEEP{1'b1}}; - softmc_c2h_tlast <= data_count == (DATA_LIMIT - 1); - softmc_h2c_tready <= 1; - if (softmc_c2h_tready && softmc_c2h_tvalid) begin - for (data_loop_i = 0; data_loop_i < `SOFTMC_STREAM_KEEP; data_loop_i = data_loop_i + 1) begin - softmc_c2h_tdata[(`SOFTMC_STREAM_KEEP - data_loop_i - 1) * 8 +: 8] <= (data_base + `SOFTMC_STREAM_KEEP) + data_loop_i; - end - softmc_c2h_tvalid <= data_count < (DATA_LIMIT - 1); - data_count <= data_count + (`SOFTMC_STREAM_WIDTH / 32); // each data is 32 bits long - data_base <= data_base + `SOFTMC_STREAM_KEEP; - end - else begin - for (data_loop_i = 0; data_loop_i < `SOFTMC_STREAM_KEEP; data_loop_i = data_loop_i + 1) begin - softmc_c2h_tdata[(`SOFTMC_STREAM_KEEP - data_loop_i - 1) * 8 +: 8] <= data_base + data_loop_i; - end - softmc_c2h_tvalid <= data_count < DATA_LIMIT; - end - end - end + localparam DATA_LIMIT = 'd1024; + wire [`SOFTMC_STREAM_WIDTH-1:0] softmc_h2c_tdata; + wire [`SOFTMC_STREAM_KEEP-1:0] softmc_h2c_tkeep; + wire softmc_h2c_tvalid; + reg softmc_h2c_tready; + wire softmc_h2c_tlast; + + reg [`SOFTMC_STREAM_WIDTH-1:0] softmc_c2h_tdata; + reg [`SOFTMC_STREAM_KEEP-1:0] softmc_c2h_tkeep; + reg softmc_c2h_tvalid; + wire softmc_c2h_tready; + reg softmc_c2h_tlast; + + reg [15:0] data_count; + reg [7:0] data_base; + + integer data_loop_i; + always @(posedge user_clk) begin + if (user_reset_q) begin + softmc_c2h_tdata <= 0; + softmc_c2h_tkeep <= 0; + softmc_c2h_tvalid <= 0; + softmc_c2h_tlast <= 0; + softmc_h2c_tready <= 0; + data_count <= 0; + data_base <= 0; + end + else begin + softmc_c2h_tkeep <= {`SOFTMC_STREAM_KEEP{1'b1}}; + softmc_c2h_tlast <= data_count == (DATA_LIMIT - 1); + softmc_h2c_tready <= 1; + if (softmc_c2h_tready && softmc_c2h_tvalid) begin + for (data_loop_i = 0; data_loop_i < `SOFTMC_STREAM_KEEP; data_loop_i = data_loop_i + 1) begin + softmc_c2h_tdata[(`SOFTMC_STREAM_KEEP - data_loop_i - 1) * 8 +: 8] <= (data_base + `SOFTMC_STREAM_KEEP) + data_loop_i; + end + softmc_c2h_tvalid <= data_count < (DATA_LIMIT - 1); + data_count <= data_count + (`SOFTMC_STREAM_WIDTH / 32); // each data is 32 bits long + data_base <= data_base + `SOFTMC_STREAM_KEEP; + end + else begin + for (data_loop_i = 0; data_loop_i < `SOFTMC_STREAM_KEEP; data_loop_i = data_loop_i + 1) begin + softmc_c2h_tdata[(`SOFTMC_STREAM_KEEP - data_loop_i - 1) * 8 +: 8] <= data_base + data_loop_i; + end + softmc_c2h_tvalid <= data_count < DATA_LIMIT; + end + end + end `endif zc706_pcie_x4_gen2_support # - ( - .LINK_CAP_MAX_LINK_WIDTH ( 4 ), // PCIe Lane Width - .C_DATA_WIDTH ( C_DATA_WIDTH ), // RX/TX interface data width - .KEEP_WIDTH ( KEEP_WIDTH ), // TSTRB width - .PCIE_REFCLK_FREQ ( REF_CLK_FREQ ), // PCIe reference clock frequency - .PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ), // PCIe user clock 1 frequency - .PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 ), // PCIe user clock 2 frequency - .PCIE_USE_MODE ("3.0"), // PCIe use mode - .PCIE_GT_DEVICE ("GTX") // PCIe GT device - ) + ( + .LINK_CAP_MAX_LINK_WIDTH ( 4 ), // PCIe Lane Width + .C_DATA_WIDTH ( C_DATA_WIDTH ), // RX/TX interface data width + .KEEP_WIDTH ( KEEP_WIDTH ), // TSTRB width + .PCIE_REFCLK_FREQ ( REF_CLK_FREQ ), // PCIe reference clock frequency + .PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ), // PCIe user clock 1 frequency + .PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 ), // PCIe user clock 2 frequency + .PCIE_USE_MODE ("3.0"), // PCIe use mode + .PCIE_GT_DEVICE ("GTX") // PCIe GT device + ) zc706_pcie_x4_gen2_support_i - ( - - //----------------------------------------------------------------------------------------------------------------// - // PCI Express (pci_exp) Interface // - //----------------------------------------------------------------------------------------------------------------// - // Tx - .pci_exp_txn ( pci_exp_txn ), - .pci_exp_txp ( pci_exp_txp ), - - // Rx - .pci_exp_rxn ( pci_exp_rxn ), - .pci_exp_rxp ( pci_exp_rxp ), - - //----------------------------------------------------------------------------------------------------------------// - // Clocking Sharing Interface // - //----------------------------------------------------------------------------------------------------------------// - .pipe_pclk_out_slave ( ), - .pipe_rxusrclk_out ( ), - .pipe_rxoutclk_out ( ), - .pipe_dclk_out ( ), - .pipe_userclk1_out ( ), - .pipe_oobclk_out ( ), - .pipe_userclk2_out ( ), - .pipe_mmcm_lock_out ( ), - .pipe_pclk_sel_slave ( 4'b0), - .pipe_mmcm_rst_n ( pipe_mmcm_rst_n ), // Async | Async - - - //----------------------------------------------------------------------------------------------------------------// - // AXI-S Interface // - //----------------------------------------------------------------------------------------------------------------// - - // Common - .user_clk_out ( user_clk ), - .user_reset_out ( user_reset ), - .user_lnk_up ( user_lnk_up ), - .user_app_rdy ( ), - - // TX - .s_axis_tx_tready ( s_axis_tx_tready ), - .s_axis_tx_tdata ( s_axis_tx_tdata ), - .s_axis_tx_tkeep ( s_axis_tx_tkeep ), - .s_axis_tx_tuser ( s_axis_tx_tuser ), - .s_axis_tx_tlast ( s_axis_tx_tlast ), - .s_axis_tx_tvalid ( s_axis_tx_tvalid ), - - // Rx - .m_axis_rx_tdata ( m_axis_rx_tdata ), - .m_axis_rx_tkeep ( m_axis_rx_tkeep ), - .m_axis_rx_tlast ( m_axis_rx_tlast ), - .m_axis_rx_tvalid ( m_axis_rx_tvalid ), - .m_axis_rx_tready ( m_axis_rx_tready ), - .m_axis_rx_tuser ( m_axis_rx_tuser ), - - // Flow Control - .fc_cpld ( ), - .fc_cplh ( ), - .fc_npd ( ), - .fc_nph ( ), - .fc_pd ( ), - .fc_ph ( ), - .fc_sel ( fc_sel ), - - // Management Interface - .cfg_mgmt_di ( cfg_mgmt_di ), - .cfg_mgmt_byte_en ( cfg_mgmt_byte_en ), - .cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ), - .cfg_mgmt_wr_en ( cfg_mgmt_wr_en ), - .cfg_mgmt_rd_en ( cfg_mgmt_rd_en ), - .cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ), - - //------------------------------------------------// - // EP and RP // - //------------------------------------------------// - .cfg_mgmt_do ( cfg_mgmt_do ), - .cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ), - .cfg_mgmt_wr_rw1c_as_rw ( 1'b0 ), - - // Error Reporting Interface - .cfg_err_ecrc ( cfg_err_ecrc ), - .cfg_err_ur ( cfg_err_ur ), - .cfg_err_cpl_timeout ( cfg_err_cpl_timeout ), - .cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ), - .cfg_err_cpl_abort ( cfg_err_cpl_abort ), - .cfg_err_posted ( cfg_err_posted ), - .cfg_err_cor ( cfg_err_cor ), - .cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ), - .cfg_err_internal_cor ( cfg_err_internal_cor ), - .cfg_err_malformed ( cfg_err_malformed ), - .cfg_err_mc_blocked ( cfg_err_mc_blocked ), - .cfg_err_poisoned ( cfg_err_poisoned ), - .cfg_err_norecovery ( cfg_err_norecovery ), - .cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ), - .cfg_err_cpl_rdy ( ), - .cfg_err_locked ( cfg_err_locked ), - .cfg_err_acs ( cfg_err_acs ), - .cfg_err_internal_uncor ( cfg_err_internal_uncor ), - - //----------------------------------------------------------------------------------------------------------------// - // AER Interface // - //----------------------------------------------------------------------------------------------------------------// - .cfg_err_aer_headerlog ( cfg_err_aer_headerlog ), - .cfg_err_aer_headerlog_set ( ), - .cfg_aer_ecrc_check_en ( ), - .cfg_aer_ecrc_gen_en ( ), - .cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ), - - .tx_cfg_gnt ( tx_cfg_gnt ), - .rx_np_ok ( rx_np_ok ), - .rx_np_req ( rx_np_req ), - .cfg_trn_pending ( cfg_trn_pending ), - .cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ), - .cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ), - .cfg_pm_force_state_en ( cfg_pm_force_state_en ), - .cfg_pm_force_state ( cfg_pm_force_state ), - .cfg_dsn ( cfg_dsn ), - .cfg_turnoff_ok ( cfg_turnoff_ok ), - .cfg_pm_wake ( cfg_pm_wake ), - //------------------------------------------------// - // RP Only // - //------------------------------------------------// - .cfg_pm_send_pme_to ( 1'b0 ), - .cfg_ds_bus_number ( 8'b0 ), - .cfg_ds_device_number ( 5'b0 ), - .cfg_ds_function_number ( 3'b0 ), - - //------------------------------------------------// - // EP Only // - //------------------------------------------------// - .cfg_interrupt ( cfg_interrupt ), - .cfg_interrupt_rdy ( cfg_interrupt_rdy ), - .cfg_interrupt_assert ( cfg_interrupt_assert ), - .cfg_interrupt_di ( cfg_interrupt_di ), - .cfg_interrupt_do ( ), - .cfg_interrupt_mmenable ( ), - .cfg_interrupt_msienable ( cfg_interrupt_msienable ), - .cfg_interrupt_msixenable ( ), - .cfg_interrupt_msixfm ( ), - .cfg_interrupt_stat ( cfg_interrupt_stat ), - .cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ), - - //----------------------------------------------------------------------------------------------------------------// - // Configuration (CFG) Interface // - //----------------------------------------------------------------------------------------------------------------// - .cfg_status ( ), - .cfg_command ( cfg_command ), - .cfg_dstatus ( ), - .cfg_lstatus ( ), - .cfg_pcie_link_state ( ), - .cfg_dcommand ( cfg_dcommand ), - .cfg_lcommand ( ), - .cfg_dcommand2 ( ), - - .cfg_pmcsr_pme_en ( ), - .cfg_pmcsr_powerstate ( ), - .cfg_pmcsr_pme_status ( ), - .cfg_received_func_lvl_rst ( ), - .tx_buf_av ( ), - .tx_err_drop ( ), - .tx_cfg_req ( ), - .cfg_to_turnoff ( cfg_to_turnoff ), - .cfg_bus_number ( cfg_bus_number ), - .cfg_device_number ( cfg_device_number ), - .cfg_function_number ( cfg_function_number ), - .cfg_bridge_serr_en ( ), - .cfg_slot_control_electromech_il_ctl_pulse ( ), - .cfg_root_control_syserr_corr_err_en ( ), - .cfg_root_control_syserr_non_fatal_err_en ( ), - .cfg_root_control_syserr_fatal_err_en ( ), - .cfg_root_control_pme_int_en ( ), - .cfg_aer_rooterr_corr_err_reporting_en ( ), - .cfg_aer_rooterr_non_fatal_err_reporting_en( ), - .cfg_aer_rooterr_fatal_err_reporting_en ( ), - .cfg_aer_rooterr_corr_err_received ( ), - .cfg_aer_rooterr_non_fatal_err_received ( ), - .cfg_aer_rooterr_fatal_err_received ( ), - //----------------------------------------------------------------------------------------------------------------// - // VC interface // - //---------------------------------------------------------------------------------------------------------------// - .cfg_vc_tcvc_map ( ), - - .cfg_msg_received ( ), - .cfg_msg_data ( ), - .cfg_msg_received_err_cor ( ), - .cfg_msg_received_err_non_fatal ( ), - .cfg_msg_received_err_fatal ( ), - .cfg_msg_received_pm_as_nak ( ), - .cfg_msg_received_pme_to_ack ( ), - .cfg_msg_received_assert_int_a ( ), - .cfg_msg_received_assert_int_b ( ), - .cfg_msg_received_assert_int_c ( ), - .cfg_msg_received_assert_int_d ( ), - .cfg_msg_received_deassert_int_a ( ), - .cfg_msg_received_deassert_int_b ( ), - .cfg_msg_received_deassert_int_c ( ), - .cfg_msg_received_deassert_int_d ( ), - .cfg_msg_received_pm_pme ( ), - .cfg_msg_received_setslotpowerlimit ( ), - - //----------------------------------------------------------------------------------------------------------------// - // Physical Layer Control and Status (PL) Interface // - //----------------------------------------------------------------------------------------------------------------// - .pl_directed_link_change ( pl_directed_link_change ), - .pl_directed_link_width ( pl_directed_link_width ), - .pl_directed_link_speed ( pl_directed_link_speed ), - .pl_directed_link_auton ( pl_directed_link_auton ), - .pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ), - - .pl_sel_lnk_rate ( ), - .pl_sel_lnk_width ( ), - .pl_ltssm_state ( ), - .pl_lane_reversal_mode ( ), - - .pl_phy_lnk_up ( ), - .pl_tx_pm_state ( ), - .pl_rx_pm_state ( ), - - .pl_link_upcfg_cap ( ), - .pl_link_gen2_cap ( ), - .pl_link_partner_gen2_supported ( ), - .pl_initial_link_width ( ), - - .pl_directed_change_done ( ), - - //------------------------------------------------// - // EP Only // - //------------------------------------------------// - .pl_received_hot_rst ( ), - - //------------------------------------------------// - // RP Only // - //------------------------------------------------// - .pl_transmit_hot_rst ( 1'b0 ), - .pl_downstream_deemph_source ( 1'b0 ), - - //----------------------------------------------------------------------------------------------------------------// - // PCIe DRP (PCIe DRP) Interface // - //----------------------------------------------------------------------------------------------------------------// - .pcie_drp_clk ( 1'b1 ), - .pcie_drp_en ( 1'b0 ), - .pcie_drp_we ( 1'b0 ), - .pcie_drp_addr ( 9'h0 ), - .pcie_drp_di ( 16'h0 ), - .pcie_drp_rdy ( ), - .pcie_drp_do ( ), - - - - //----------------------------------------------------------------------------------------------------------------// - // System (SYS) Interface // - //----------------------------------------------------------------------------------------------------------------// - .sys_clk ( sys_clk ), - .sys_rst_n ( sys_rst_n_c ) + ( + + //----------------------------------------------------------------------------------------------------------------// + // PCI Express (pci_exp) Interface // + //----------------------------------------------------------------------------------------------------------------// + // Tx + .pci_exp_txn ( pci_exp_txn ), + .pci_exp_txp ( pci_exp_txp ), + + // Rx + .pci_exp_rxn ( pci_exp_rxn ), + .pci_exp_rxp ( pci_exp_rxp ), + + //----------------------------------------------------------------------------------------------------------------// + // Clocking Sharing Interface // + //----------------------------------------------------------------------------------------------------------------// + .pipe_pclk_out_slave ( ), + .pipe_rxusrclk_out ( ), + .pipe_rxoutclk_out ( ), + .pipe_dclk_out ( ), + .pipe_userclk1_out ( ), + .pipe_oobclk_out ( ), + .pipe_userclk2_out ( ), + .pipe_mmcm_lock_out ( ), + .pipe_pclk_sel_slave ( 4'b0), + .pipe_mmcm_rst_n ( pipe_mmcm_rst_n ), // Async | Async + + + //----------------------------------------------------------------------------------------------------------------// + // AXI-S Interface // + //----------------------------------------------------------------------------------------------------------------// + + // Common + .user_clk_out ( user_clk ), + .user_reset_out ( user_reset ), + .user_lnk_up ( user_lnk_up ), + .user_app_rdy ( ), + + // TX + .s_axis_tx_tready ( s_axis_tx_tready ), + .s_axis_tx_tdata ( s_axis_tx_tdata ), + .s_axis_tx_tkeep ( s_axis_tx_tkeep ), + .s_axis_tx_tuser ( s_axis_tx_tuser ), + .s_axis_tx_tlast ( s_axis_tx_tlast ), + .s_axis_tx_tvalid ( s_axis_tx_tvalid ), + + // Rx + .m_axis_rx_tdata ( m_axis_rx_tdata ), + .m_axis_rx_tkeep ( m_axis_rx_tkeep ), + .m_axis_rx_tlast ( m_axis_rx_tlast ), + .m_axis_rx_tvalid ( m_axis_rx_tvalid ), + .m_axis_rx_tready ( m_axis_rx_tready ), + .m_axis_rx_tuser ( m_axis_rx_tuser ), + + // Flow Control + .fc_cpld ( ), + .fc_cplh ( ), + .fc_npd ( ), + .fc_nph ( ), + .fc_pd ( ), + .fc_ph ( ), + .fc_sel ( fc_sel ), + + // Management Interface + .cfg_mgmt_di ( cfg_mgmt_di ), + .cfg_mgmt_byte_en ( cfg_mgmt_byte_en ), + .cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ), + .cfg_mgmt_wr_en ( cfg_mgmt_wr_en ), + .cfg_mgmt_rd_en ( cfg_mgmt_rd_en ), + .cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ), + + //------------------------------------------------// + // EP and RP // + //------------------------------------------------// + .cfg_mgmt_do ( cfg_mgmt_do ), + .cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ), + .cfg_mgmt_wr_rw1c_as_rw ( 1'b0 ), + + // Error Reporting Interface + .cfg_err_ecrc ( cfg_err_ecrc ), + .cfg_err_ur ( cfg_err_ur ), + .cfg_err_cpl_timeout ( cfg_err_cpl_timeout ), + .cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ), + .cfg_err_cpl_abort ( cfg_err_cpl_abort ), + .cfg_err_posted ( cfg_err_posted ), + .cfg_err_cor ( cfg_err_cor ), + .cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ), + .cfg_err_internal_cor ( cfg_err_internal_cor ), + .cfg_err_malformed ( cfg_err_malformed ), + .cfg_err_mc_blocked ( cfg_err_mc_blocked ), + .cfg_err_poisoned ( cfg_err_poisoned ), + .cfg_err_norecovery ( cfg_err_norecovery ), + .cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ), + .cfg_err_cpl_rdy ( ), + .cfg_err_locked ( cfg_err_locked ), + .cfg_err_acs ( cfg_err_acs ), + .cfg_err_internal_uncor ( cfg_err_internal_uncor ), + + //----------------------------------------------------------------------------------------------------------------// + // AER Interface // + //----------------------------------------------------------------------------------------------------------------// + .cfg_err_aer_headerlog ( cfg_err_aer_headerlog ), + .cfg_err_aer_headerlog_set ( ), + .cfg_aer_ecrc_check_en ( ), + .cfg_aer_ecrc_gen_en ( ), + .cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ), + + .tx_cfg_gnt ( tx_cfg_gnt ), + .rx_np_ok ( rx_np_ok ), + .rx_np_req ( rx_np_req ), + .cfg_trn_pending ( cfg_trn_pending ), + .cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ), + .cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ), + .cfg_pm_force_state_en ( cfg_pm_force_state_en ), + .cfg_pm_force_state ( cfg_pm_force_state ), + .cfg_dsn ( cfg_dsn ), + .cfg_turnoff_ok ( cfg_turnoff_ok ), + .cfg_pm_wake ( cfg_pm_wake ), + //------------------------------------------------// + // RP Only // + //------------------------------------------------// + .cfg_pm_send_pme_to ( 1'b0 ), + .cfg_ds_bus_number ( 8'b0 ), + .cfg_ds_device_number ( 5'b0 ), + .cfg_ds_function_number ( 3'b0 ), + + //------------------------------------------------// + // EP Only // + //------------------------------------------------// + .cfg_interrupt ( cfg_interrupt ), + .cfg_interrupt_rdy ( cfg_interrupt_rdy ), + .cfg_interrupt_assert ( cfg_interrupt_assert ), + .cfg_interrupt_di ( cfg_interrupt_di ), + .cfg_interrupt_do ( ), + .cfg_interrupt_mmenable ( ), + .cfg_interrupt_msienable ( cfg_interrupt_msienable ), + .cfg_interrupt_msixenable ( ), + .cfg_interrupt_msixfm ( ), + .cfg_interrupt_stat ( cfg_interrupt_stat ), + .cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ), + + //----------------------------------------------------------------------------------------------------------------// + // Configuration (CFG) Interface // + //----------------------------------------------------------------------------------------------------------------// + .cfg_status ( ), + .cfg_command ( cfg_command ), + .cfg_dstatus ( ), + .cfg_lstatus ( ), + .cfg_pcie_link_state ( ), + .cfg_dcommand ( cfg_dcommand ), + .cfg_lcommand ( ), + .cfg_dcommand2 ( ), + + .cfg_pmcsr_pme_en ( ), + .cfg_pmcsr_powerstate ( ), + .cfg_pmcsr_pme_status ( ), + .cfg_received_func_lvl_rst ( ), + .tx_buf_av ( ), + .tx_err_drop ( ), + .tx_cfg_req ( ), + .cfg_to_turnoff ( cfg_to_turnoff ), + .cfg_bus_number ( cfg_bus_number ), + .cfg_device_number ( cfg_device_number ), + .cfg_function_number ( cfg_function_number ), + .cfg_bridge_serr_en ( ), + .cfg_slot_control_electromech_il_ctl_pulse ( ), + .cfg_root_control_syserr_corr_err_en ( ), + .cfg_root_control_syserr_non_fatal_err_en ( ), + .cfg_root_control_syserr_fatal_err_en ( ), + .cfg_root_control_pme_int_en ( ), + .cfg_aer_rooterr_corr_err_reporting_en ( ), + .cfg_aer_rooterr_non_fatal_err_reporting_en( ), + .cfg_aer_rooterr_fatal_err_reporting_en ( ), + .cfg_aer_rooterr_corr_err_received ( ), + .cfg_aer_rooterr_non_fatal_err_received ( ), + .cfg_aer_rooterr_fatal_err_received ( ), + //----------------------------------------------------------------------------------------------------------------// + // VC interface // + //---------------------------------------------------------------------------------------------------------------// + .cfg_vc_tcvc_map ( ), + + .cfg_msg_received ( ), + .cfg_msg_data ( ), + .cfg_msg_received_err_cor ( ), + .cfg_msg_received_err_non_fatal ( ), + .cfg_msg_received_err_fatal ( ), + .cfg_msg_received_pm_as_nak ( ), + .cfg_msg_received_pme_to_ack ( ), + .cfg_msg_received_assert_int_a ( ), + .cfg_msg_received_assert_int_b ( ), + .cfg_msg_received_assert_int_c ( ), + .cfg_msg_received_assert_int_d ( ), + .cfg_msg_received_deassert_int_a ( ), + .cfg_msg_received_deassert_int_b ( ), + .cfg_msg_received_deassert_int_c ( ), + .cfg_msg_received_deassert_int_d ( ), + .cfg_msg_received_pm_pme ( ), + .cfg_msg_received_setslotpowerlimit ( ), + + //----------------------------------------------------------------------------------------------------------------// + // Physical Layer Control and Status (PL) Interface // + //----------------------------------------------------------------------------------------------------------------// + .pl_directed_link_change ( pl_directed_link_change ), + .pl_directed_link_width ( pl_directed_link_width ), + .pl_directed_link_speed ( pl_directed_link_speed ), + .pl_directed_link_auton ( pl_directed_link_auton ), + .pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ), + + .pl_sel_lnk_rate ( ), + .pl_sel_lnk_width ( ), + .pl_ltssm_state ( ), + .pl_lane_reversal_mode ( ), + + .pl_phy_lnk_up ( ), + .pl_tx_pm_state ( ), + .pl_rx_pm_state ( ), + + .pl_link_upcfg_cap ( ), + .pl_link_gen2_cap ( ), + .pl_link_partner_gen2_supported ( ), + .pl_initial_link_width ( ), + + .pl_directed_change_done ( ), + + //------------------------------------------------// + // EP Only // + //------------------------------------------------// + .pl_received_hot_rst ( ), + + //------------------------------------------------// + // RP Only // + //------------------------------------------------// + .pl_transmit_hot_rst ( 1'b0 ), + .pl_downstream_deemph_source ( 1'b0 ), + + //----------------------------------------------------------------------------------------------------------------// + // PCIe DRP (PCIe DRP) Interface // + //----------------------------------------------------------------------------------------------------------------// + .pcie_drp_clk ( 1'b1 ), + .pcie_drp_en ( 1'b0 ), + .pcie_drp_we ( 1'b0 ), + .pcie_drp_addr ( 9'h0 ), + .pcie_drp_di ( 16'h0 ), + .pcie_drp_rdy ( ), + .pcie_drp_do ( ), + + + + //----------------------------------------------------------------------------------------------------------------// + // System (SYS) Interface // + //----------------------------------------------------------------------------------------------------------------// + .sys_clk ( sys_clk ), + .sys_rst_n ( sys_rst_n_c ) ); pcie_app_7x #( - .C_DATA_WIDTH( C_DATA_WIDTH ) + .C_DATA_WIDTH( C_DATA_WIDTH ) ) app ( - //----------------------------------------------------------------------------------------------------------------// - // AXI-S Interface // - //----------------------------------------------------------------------------------------------------------------// - - // Common - .user_clk ( user_clk ), - .user_reset ( user_reset_q ), - .user_lnk_up ( user_lnk_up_q ), - - // Tx - .s_axis_tx_tready ( s_axis_tx_tready ), - .s_axis_tx_tdata ( s_axis_tx_tdata ), - .s_axis_tx_tkeep ( s_axis_tx_tkeep ), - .s_axis_tx_tuser ( s_axis_tx_tuser ), - .s_axis_tx_tlast ( s_axis_tx_tlast ), - .s_axis_tx_tvalid ( s_axis_tx_tvalid ), - - // Rx - .m_axis_rx_tdata ( m_axis_rx_tdata ), - .m_axis_rx_tkeep ( m_axis_rx_tkeep ), - .m_axis_rx_tlast ( m_axis_rx_tlast ), - .m_axis_rx_tvalid ( m_axis_rx_tvalid ), - .m_axis_rx_tready ( m_axis_rx_tready ), - .m_axis_rx_tuser ( m_axis_rx_tuser ), - - .tx_cfg_gnt ( tx_cfg_gnt ), - .rx_np_ok ( rx_np_ok ), - .rx_np_req ( rx_np_req ), - .cfg_turnoff_ok ( cfg_turnoff_ok ), - .cfg_trn_pending ( cfg_trn_pending ), - .cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ), - .cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ), - .cfg_pm_force_state_en ( cfg_pm_force_state_en ), - .cfg_pm_force_state ( cfg_pm_force_state ), - .cfg_pm_wake ( cfg_pm_wake ), - .cfg_dsn ( cfg_dsn ), - .cfg_dcommand ( cfg_dcommand ), - .cfg_command ( cfg_command ), - - // Flow Control - .fc_sel ( fc_sel ), - - //----------------------------------------------------------------------------------------------------------------// - // Configuration (CFG) Interface // - //----------------------------------------------------------------------------------------------------------------// - .cfg_err_cor ( cfg_err_cor ), - .cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ), - .cfg_err_internal_cor ( cfg_err_internal_cor ), - .cfg_err_malformed ( cfg_err_malformed ), - .cfg_err_mc_blocked ( cfg_err_mc_blocked ), - .cfg_err_poisoned ( cfg_err_poisoned ), - .cfg_err_norecovery ( cfg_err_norecovery ), - .cfg_err_ur ( cfg_err_ur ), - .cfg_err_ecrc ( cfg_err_ecrc ), - .cfg_err_cpl_timeout ( cfg_err_cpl_timeout ), - .cfg_err_cpl_abort ( cfg_err_cpl_abort ), - .cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ), - .cfg_err_posted ( cfg_err_posted ), - .cfg_err_locked ( cfg_err_locked ), - .cfg_err_acs ( cfg_err_acs ), //1'b0 ), - .cfg_err_internal_uncor ( cfg_err_internal_uncor ), //1'b0 ), - .cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ), - //----------------------------------------------------------------------------------------------------------------// - // Advanced Error Reporting (AER) Interface // - //----------------------------------------------------------------------------------------------------------------// - .cfg_err_aer_headerlog ( cfg_err_aer_headerlog ), - .cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ), - - .cfg_to_turnoff ( cfg_to_turnoff ), - .cfg_bus_number ( cfg_bus_number ), - .cfg_device_number ( cfg_device_number ), - .cfg_function_number ( cfg_function_number ), - - //----------------------------------------------------------------------------------------------------------------// - // Management (MGMT) Interface // - //----------------------------------------------------------------------------------------------------------------// - .cfg_mgmt_di ( cfg_mgmt_di ), - .cfg_mgmt_do ( cfg_mgmt_do ), - .cfg_mgmt_byte_en ( cfg_mgmt_byte_en ), - .cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ), - .cfg_mgmt_wr_en ( cfg_mgmt_wr_en ), - .cfg_mgmt_rd_en ( cfg_mgmt_rd_en ), - .cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ), - .cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ), - - //----------------------------------------------------------------------------------------------------------------// - // Physical Layer Control and Status (PL) Interface // - //----------------------------------------------------------------------------------------------------------------// - .pl_directed_link_auton ( pl_directed_link_auton ), - .pl_directed_link_change ( pl_directed_link_change ), - .pl_directed_link_speed ( pl_directed_link_speed ), - .pl_directed_link_width ( pl_directed_link_width ), - .pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ), - - .cfg_interrupt ( cfg_interrupt ), - .cfg_interrupt_rdy ( cfg_interrupt_rdy ), - .cfg_interrupt_assert ( cfg_interrupt_assert ), - .cfg_interrupt_di ( cfg_interrupt_di ), - .cfg_interrupt_stat ( cfg_interrupt_stat ), - .cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ), - .cfg_interrupt_msienable ( cfg_interrupt_msienable ), - - //--------------------------------------------------------------------------------------------------------------// - // Streaming Data Transfer Interface // - //--------------------------------------------------------------------------------------------------------------// - .softmc_h2c_tdata ( softmc_h2c_tdata ), - .softmc_h2c_tkeep ( softmc_h2c_tkeep ), - .softmc_h2c_tvalid ( softmc_h2c_tvalid ), - .softmc_h2c_tready ( softmc_h2c_tready ), - .softmc_h2c_tlast ( softmc_h2c_tlast ), - - .softmc_c2h_tdata ( softmc_c2h_tdata ), - .softmc_c2h_tkeep ( softmc_c2h_tkeep ), - .softmc_c2h_tvalid ( softmc_c2h_tvalid ), - .softmc_c2h_tready ( softmc_c2h_tready ), - .softmc_c2h_tlast ( softmc_c2h_tlast ) + //----------------------------------------------------------------------------------------------------------------// + // AXI-S Interface // + //----------------------------------------------------------------------------------------------------------------// + + // Common + .user_clk ( user_clk ), + .user_reset ( user_reset_q ), + .user_lnk_up ( user_lnk_up_q ), + + // Tx + .s_axis_tx_tready ( s_axis_tx_tready ), + .s_axis_tx_tdata ( s_axis_tx_tdata ), + .s_axis_tx_tkeep ( s_axis_tx_tkeep ), + .s_axis_tx_tuser ( s_axis_tx_tuser ), + .s_axis_tx_tlast ( s_axis_tx_tlast ), + .s_axis_tx_tvalid ( s_axis_tx_tvalid ), + + // Rx + .m_axis_rx_tdata ( m_axis_rx_tdata ), + .m_axis_rx_tkeep ( m_axis_rx_tkeep ), + .m_axis_rx_tlast ( m_axis_rx_tlast ), + .m_axis_rx_tvalid ( m_axis_rx_tvalid ), + .m_axis_rx_tready ( m_axis_rx_tready ), + .m_axis_rx_tuser ( m_axis_rx_tuser ), + + .tx_cfg_gnt ( tx_cfg_gnt ), + .rx_np_ok ( rx_np_ok ), + .rx_np_req ( rx_np_req ), + .cfg_turnoff_ok ( cfg_turnoff_ok ), + .cfg_trn_pending ( cfg_trn_pending ), + .cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ), + .cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ), + .cfg_pm_force_state_en ( cfg_pm_force_state_en ), + .cfg_pm_force_state ( cfg_pm_force_state ), + .cfg_pm_wake ( cfg_pm_wake ), + .cfg_dsn ( cfg_dsn ), + .cfg_dcommand ( cfg_dcommand ), + .cfg_command ( cfg_command ), + + // Flow Control + .fc_sel ( fc_sel ), + + //----------------------------------------------------------------------------------------------------------------// + // Configuration (CFG) Interface // + //----------------------------------------------------------------------------------------------------------------// + .cfg_err_cor ( cfg_err_cor ), + .cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ), + .cfg_err_internal_cor ( cfg_err_internal_cor ), + .cfg_err_malformed ( cfg_err_malformed ), + .cfg_err_mc_blocked ( cfg_err_mc_blocked ), + .cfg_err_poisoned ( cfg_err_poisoned ), + .cfg_err_norecovery ( cfg_err_norecovery ), + .cfg_err_ur ( cfg_err_ur ), + .cfg_err_ecrc ( cfg_err_ecrc ), + .cfg_err_cpl_timeout ( cfg_err_cpl_timeout ), + .cfg_err_cpl_abort ( cfg_err_cpl_abort ), + .cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ), + .cfg_err_posted ( cfg_err_posted ), + .cfg_err_locked ( cfg_err_locked ), + .cfg_err_acs ( cfg_err_acs ), //1'b0 ), + .cfg_err_internal_uncor ( cfg_err_internal_uncor ), //1'b0 ), + .cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ), + //----------------------------------------------------------------------------------------------------------------// + // Advanced Error Reporting (AER) Interface // + //----------------------------------------------------------------------------------------------------------------// + .cfg_err_aer_headerlog ( cfg_err_aer_headerlog ), + .cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ), + + .cfg_to_turnoff ( cfg_to_turnoff ), + .cfg_bus_number ( cfg_bus_number ), + .cfg_device_number ( cfg_device_number ), + .cfg_function_number ( cfg_function_number ), + + //----------------------------------------------------------------------------------------------------------------// + // Management (MGMT) Interface // + //----------------------------------------------------------------------------------------------------------------// + .cfg_mgmt_di ( cfg_mgmt_di ), + .cfg_mgmt_do ( cfg_mgmt_do ), + .cfg_mgmt_byte_en ( cfg_mgmt_byte_en ), + .cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ), + .cfg_mgmt_wr_en ( cfg_mgmt_wr_en ), + .cfg_mgmt_rd_en ( cfg_mgmt_rd_en ), + .cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ), + .cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ), + + //----------------------------------------------------------------------------------------------------------------// + // Physical Layer Control and Status (PL) Interface // + //----------------------------------------------------------------------------------------------------------------// + .pl_directed_link_auton ( pl_directed_link_auton ), + .pl_directed_link_change ( pl_directed_link_change ), + .pl_directed_link_speed ( pl_directed_link_speed ), + .pl_directed_link_width ( pl_directed_link_width ), + .pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ), + + .cfg_interrupt ( cfg_interrupt ), + .cfg_interrupt_rdy ( cfg_interrupt_rdy ), + .cfg_interrupt_assert ( cfg_interrupt_assert ), + .cfg_interrupt_di ( cfg_interrupt_di ), + .cfg_interrupt_stat ( cfg_interrupt_stat ), + .cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ), + .cfg_interrupt_msienable ( cfg_interrupt_msienable ), + + //--------------------------------------------------------------------------------------------------------------// + // Streaming Data Transfer Interface // + //--------------------------------------------------------------------------------------------------------------// + .softmc_h2c_tdata ( softmc_h2c_tdata ), + .softmc_h2c_tkeep ( softmc_h2c_tkeep ), + .softmc_h2c_tvalid ( softmc_h2c_tvalid ), + .softmc_h2c_tready ( softmc_h2c_tready ), + .softmc_h2c_tlast ( softmc_h2c_tlast ), + + .softmc_c2h_tdata ( softmc_c2h_tdata ), + .softmc_c2h_tkeep ( softmc_c2h_tkeep ), + .softmc_c2h_tvalid ( softmc_c2h_tvalid ), + .softmc_c2h_tready ( softmc_c2h_tready ), + .softmc_c2h_tlast ( softmc_c2h_tlast ) ); -// ila_ms debug_maxis ( -// .clk ( user_clk ), -// .probe0 ( m_axis_rx_tdata ), -// .probe1 ( m_axis_rx_tkeep ), -// .probe2 ( m_axis_rx_tvalid ), -// .probe3 ( m_axis_rx_tready ), -// .probe4 ( m_axis_rx_tlast ) -// ); - -// ila_ms debug_saxis ( -// .clk ( user_clk ), -// .probe0 ( s_axis_tx_tdata ), -// .probe1 ( s_axis_tx_tkeep ), -// .probe2 ( s_axis_tx_tvalid ), -// .probe3 ( s_axis_tx_tready ), -// .probe4 ( s_axis_tx_tlast ) -// ); - -// ila_hc debug_c2h ( -// .clk ( user_clk ), -// .probe0 ( softmc_c2h_tdata ), -// .probe1 ( softmc_c2h_tkeep ), -// .probe2 ( softmc_c2h_tvalid ), -// .probe3 ( softmc_c2h_tready ), -// .probe4 ( softmc_c2h_tlast ) -// ); - -// ila_hc debug_h2c ( -// .clk ( user_clk ), -// .probe0 ( softmc_h2c_tdata ), -// .probe1 ( softmc_h2c_tkeep ), -// .probe2 ( softmc_h2c_tvalid ), -// .probe3 ( softmc_h2c_tready ), -// .probe4 ( softmc_h2c_tlast ) -// ); +`ifdef ILA_CORES + ila_ms debug_maxis ( + .clk ( user_clk ), + .probe0 ( m_axis_rx_tdata ), + .probe1 ( m_axis_rx_tkeep ), + .probe2 ( m_axis_rx_tvalid ), + .probe3 ( m_axis_rx_tready ), + .probe4 ( m_axis_rx_tlast ) + ); + + ila_ms debug_saxis ( + .clk ( user_clk ), + .probe0 ( s_axis_tx_tdata ), + .probe1 ( s_axis_tx_tkeep ), + .probe2 ( s_axis_tx_tvalid ), + .probe3 ( s_axis_tx_tready ), + .probe4 ( s_axis_tx_tlast ) + ); + + ila_hc debug_c2h ( + .clk ( user_clk ), + .probe0 ( softmc_c2h_tdata ), + .probe1 ( softmc_c2h_tkeep ), + .probe2 ( softmc_c2h_tvalid ), + .probe3 ( softmc_c2h_tready ), + .probe4 ( softmc_c2h_tlast ) + ); + + ila_hc debug_h2c ( + .clk ( user_clk ), + .probe0 ( softmc_h2c_tdata ), + .probe1 ( softmc_h2c_tkeep ), + .probe2 ( softmc_h2c_tvalid ), + .probe3 ( softmc_h2c_tready ), + .probe4 ( softmc_h2c_tlast ) + ); +`endif endmodule \ No newline at end of file diff --git a/sources/api/board.cpp b/sources/api/board.cpp index db990ca..61753c5 100644 --- a/sources/api/board.cpp +++ b/sources/api/board.cpp @@ -60,6 +60,21 @@ int BoardInterface::init() } return 0; } + case IFACE::ZC706: + { + to_card = fopen("/dev/softmc_cdev", "r"); + if (to_card < 0) + { + std::cerr << "Open to host failed!" << std::endl; + return 1; + } + from_card = fopen("/dev/softmc_cdev", "w"); + if (from_card < 0) + { + std::cerr << "Open to card failed!" << std::endl; + return 1; + } + } default: std::cerr << "Unknown iface_type!" << std::endl; return 1; @@ -73,6 +88,9 @@ int BoardInterface::sendData(void* data, const uint size) case IFACE::XDMA: return xdma_send(data,size); break; + case IFACE::ZC706: + return zc706_send(data,size); + break; default: std::cerr << "Unknown iface_type!" << std::endl; return 1; @@ -86,6 +104,9 @@ int BoardInterface::recvData(void* buf, const uint size) case IFACE::XDMA: return xdma_recv(buf,size); break; + case IFACE::ZC706: + return zc706_recv(data,size); + break; default: std::cerr << "Unknown iface_type!" << std::endl; return 1; @@ -130,3 +151,13 @@ int BoardInterface::xdma_recv(void* buf, const uint size) memcpy(buf, (char*) recv_buf, count); return count; } + +int BoardInterface::zc706_recv(void* buf, const uint size) +{ + return fread(buf, sizeof(char), size, fp); +} + +int BoardInterface::zc706_send(void* buf, const uint size) +{ + return fwrite(buf, sizeof(char), size, fp); +} \ No newline at end of file diff --git a/sources/api/board.h b/sources/api/board.h index 0935392..357fb3b 100644 --- a/sources/api/board.h +++ b/sources/api/board.h @@ -13,7 +13,8 @@ class BoardInterface{ const std::string FROM_FPGA_DEFAULT = "/dev/xdma0_c2h_0"; public: enum class IFACE { - XDMA = 0 + XDMA = 0, + ZC706 }; BoardInterface(IFACE); ~BoardInterface(); diff --git a/sources/zc706_driver/README.md b/sources/zc706_driver/README.md new file mode 100644 index 0000000..9378e43 --- /dev/null +++ b/sources/zc706_driver/README.md @@ -0,0 +1,13 @@ +### Testing and Verifying the ZC706 PCIe Driver + +1. Define ILA_CORES flag in `/projects/ZC706/verilog/pcie_top.v` and synthesize / implement the project (see line 60) +2. Compile the ZC706 PCIe Driver with `$ make all` +3. Insert ZC706 Driver with `$ insmod dma_softmc` +4. Compile the driver test with `$ g++ test/*.c -o test/test` +5. Setup ILA cores to trigger when `softmc_c2h_tvalid` or `softmc_h2c_tvalid` is asserted +6. Run the driver test with `./test/test` and verify data transfers using ILA core waveforms + +### Using ZC706 PCIe Driver Instead of XDMA + +1. Replace the default *BoardInterface* to `BoardInterface::IFACE::XDMA` in `/sources/api/platform.cpp` (line 69) +2. Include the DRAM-Bender platform to applications and execute as before (e.g., `/sources/apps/Smalltest`) \ No newline at end of file From a6d879a665d12b4a2e1fcfc93a7fe94c7392bd1f Mon Sep 17 00:00:00 2001 From: kirbyydoge <60625692+kirbyydoge@users.noreply.github.com> Date: Sat, 31 Aug 2024 17:59:22 +0200 Subject: [PATCH 4/5] Update README.md --- sources/zc706_driver/README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sources/zc706_driver/README.md b/sources/zc706_driver/README.md index 9378e43..a2c8c5e 100644 --- a/sources/zc706_driver/README.md +++ b/sources/zc706_driver/README.md @@ -1,6 +1,6 @@ ### Testing and Verifying the ZC706 PCIe Driver -1. Define ILA_CORES flag in `/projects/ZC706/verilog/pcie_top.v` and synthesize / implement the project (see line 60) +1. Define ILA_CORES flag in `/projects/ZC706/verilog/pcie_top.v` (see line 60) and synthesize / implement the project 2. Compile the ZC706 PCIe Driver with `$ make all` 3. Insert ZC706 Driver with `$ insmod dma_softmc` 4. Compile the driver test with `$ g++ test/*.c -o test/test` @@ -9,5 +9,5 @@ ### Using ZC706 PCIe Driver Instead of XDMA -1. Replace the default *BoardInterface* to `BoardInterface::IFACE::XDMA` in `/sources/api/platform.cpp` (line 69) -2. Include the DRAM-Bender platform to applications and execute as before (e.g., `/sources/apps/Smalltest`) \ No newline at end of file +1. Replace the default *BoardInterface* to `BoardInterface::IFACE::XDMA` in `/sources/api/platform.cpp` (see line 69) +2. Include the DRAM-Bender platform to applications and execute as before (e.g., `/sources/apps/Smalltest`) From dfc5d64630ae2db838cc9443e3481201a8e421af Mon Sep 17 00:00:00 2001 From: kirbyydoge Date: Sun, 1 Sep 2024 13:18:19 +0200 Subject: [PATCH 5/5] Change standard file functions of ZC706 driver to match XDMA driver --- sources/api/board.cpp | 21 +++++++++++++-------- sources/api/board.h | 2 ++ 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/sources/api/board.cpp b/sources/api/board.cpp index 61753c5..b0c474c 100644 --- a/sources/api/board.cpp +++ b/sources/api/board.cpp @@ -62,13 +62,13 @@ int BoardInterface::init() } case IFACE::ZC706: { - to_card = fopen("/dev/softmc_cdev", "r"); + to_card = open("/dev/softmc_cdev", O_RDWR); if (to_card < 0) { std::cerr << "Open to host failed!" << std::endl; return 1; } - from_card = fopen("/dev/softmc_cdev", "w"); + from_card = open("/dev/softmc_cdev", O_RDWR); if (from_card < 0) { std::cerr << "Open to card failed!" << std::endl; @@ -105,7 +105,7 @@ int BoardInterface::recvData(void* buf, const uint size) return xdma_recv(buf,size); break; case IFACE::ZC706: - return zc706_recv(data,size); + return zc706_recv(buf,size); break; default: std::cerr << "Unknown iface_type!" << std::endl; @@ -152,12 +152,17 @@ int BoardInterface::xdma_recv(void* buf, const uint size) return count; } -int BoardInterface::zc706_recv(void* buf, const uint size) +int BoardInterface::zc706_send(void* data, const uint size) { - return fread(buf, sizeof(char), size, fp); + uint64_t count = 0; + while (count < size) { + auto rc = write(to_card, (char*) data, size); + count += rc; + } + return count; } -int BoardInterface::zc706_send(void* buf, const uint size) +int BoardInterface::zc706_recv(void* buf, const uint size) { - return fwrite(buf, sizeof(char), size, fp); -} \ No newline at end of file + return read(from_card, (char*) buf, size); +} diff --git a/sources/api/board.h b/sources/api/board.h index 357fb3b..7f0fe3a 100644 --- a/sources/api/board.h +++ b/sources/api/board.h @@ -30,6 +30,8 @@ class BoardInterface{ void* recv_buf; int xdma_send(void* data, const uint size); int xdma_recv(void* buf, const uint size); + int zc706_send(void* data, const uint size); + int zc706_recv(void* buf, const uint size); // end XDMA related constructs };

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