diff --git a/projects/ZC706/ZC706.srcs/sim_1/tb_instr_mem.v b/projects/ZC706/ZC706.srcs/sim_1/tb_instr_mem.v
new file mode 100644
index 0000000..8417af0
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sim_1/tb_instr_mem.v
@@ -0,0 +1,80 @@
+`timescale 1ns / 1ps
+
+module tb_instr_mem();
+
+localparam FIFO_SCALE = 4;
+localparam DATA_WIDTH = 64;
+localparam KEEP_WIDTH = DATA_WIDTH / 8;
+
+reg clk;
+reg reset;
+
+reg [DATA_WIDTH-1:0] s_axis_tdata;
+reg s_axis_tvalid;
+reg [KEEP_WIDTH-1:0] s_axis_tkeep;
+wire s_axis_tready;
+
+wire [DATA_WIDTH*FIFO_SCALE-1:0] m_axis_tdata;
+wire m_axis_tvalid;
+reg m_axis_tready;
+
+instruction_buffer #(
+ .C_DATA_WIDTH(DATA_WIDTH),
+ .FIFO_WIDTH(FIFO_SCALE * DATA_WIDTH)
+) uut(
+ .clk(clk),
+ .reset(reset),
+ .s_axis_tdata(s_axis_tdata),
+ .s_axis_tready(s_axis_tready),
+ .s_axis_tkeep(s_axis_tkeep),
+ .s_axis_tvalid(s_axis_tvalid),
+ .m_axis_tdata(m_axis_tdata),
+ .m_axis_tready(m_axis_tready),
+ .m_axis_tvalid(m_axis_tvalid)
+);
+
+always begin
+ clk = 0;
+ #5;
+ clk = 1;
+ #5;
+end
+
+localparam TEST_LEN = 16;
+reg [DATA_WIDTH-1:0] data [0:TEST_LEN-1];
+reg [KEEP_WIDTH-1:0] data_keep [0:TEST_LEN-1];
+
+integer i;
+integer j;
+initial begin
+ for (i = 0; i < TEST_LEN; i = i+1) begin
+ for (j = 0; j < 8; j = j+1) begin
+ data[i][(KEEP_WIDTH - j - 1) * 8 +: 8] = (8 * i + j) & 'hFF;
+ end
+ /*
+ data_keep[i] = i % 4 == 0 ? 'h0F :
+ i % 4 == 1 ? 'hF0 :
+ i % 4 == 2 ? 'h0F : 'hFF ;
+ */
+ data_keep[i] = i == 0 ? 'h0F : 'hFF ;
+ end
+ reset = 1;
+ s_axis_tdata = 0;
+ s_axis_tvalid = 0;
+ m_axis_tready = 0;
+ repeat(10) begin @(posedge clk); end #1;
+ reset = 0;
+ for (i = 0; i < TEST_LEN;) begin
+ s_axis_tdata = data[i];
+ s_axis_tkeep = data_keep[i];
+ s_axis_tvalid = 1;
+ if (s_axis_tready && s_axis_tvalid) begin
+ i = i+1;
+ end
+ @(posedge clk) #1;
+ end
+ s_axis_tvalid = 0;
+ m_axis_tready = 1;
+end
+
+endmodule
diff --git a/projects/ZC706/ZC706.srcs/sim_1/tb_pcie_top.sv b/projects/ZC706/ZC706.srcs/sim_1/tb_pcie_top.sv
new file mode 100644
index 0000000..6a406a2
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sim_1/tb_pcie_top.sv
@@ -0,0 +1,349 @@
+`timescale 1ns / 1ps
+
+module tb_pcie_top();
+
+localparam SOFTMC_STREAM_WIDTH = 256;
+localparam C_DATA_WIDTH = 64;
+localparam C_ADDR_WIDTH = 64;
+localparam KEEP_WIDTH = C_DATA_WIDTH / 8;
+
+reg user_clk;
+reg user_reset;
+reg user_lnk_up;
+
+reg [7:0] cfg_bus_number;
+reg [4:0] cfg_device_number;
+reg [2:0] cfg_function_number;
+wire cfg_interrupt;
+wire cfg_interrupt_assert;
+reg cfg_interrupt_rdy;
+wire [7:0] cfg_interrupt_di;
+reg cfg_interrupt_msienable;
+
+wire m_axis_rx_tready;
+reg [C_DATA_WIDTH-1:0] m_axis_rx_tdata;
+reg [KEEP_WIDTH-1:0] m_axis_rx_tkeep;
+reg m_axis_rx_tlast;
+reg m_axis_rx_tvalid;
+reg [21:0] m_axis_rx_tuser;
+reg tx_src_dsc;
+
+wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata;
+wire [KEEP_WIDTH-1:0] s_axis_tx_tkeep;
+wire s_axis_tx_tlast;
+wire s_axis_tx_tvalid;
+reg s_axis_tx_tready;
+
+reg cfg_to_turnoff;
+wire cfg_turnoff_ok;
+reg [15:0] cfg_completer_id;
+
+wire [9:0] pci_cfg_dwaddr;
+wire pci_cfg_rd_en;
+wire [31:0] pci_cfg_dout;
+wire pci_cfg_rd_wr_done;
+
+wire [15:0] cfg_dcommand;
+reg [15:0] cfg_command;
+
+wire [SOFTMC_STREAM_WIDTH-1:0] softmc_h2c_tdata;
+wire softmc_h2c_tvalid;
+reg softmc_h2c_tready;
+wire softmc_h2c_tlast;
+
+reg [SOFTMC_STREAM_WIDTH-1:0] softmc_c2h_tdata;
+reg softmc_c2h_tvalid;
+wire softmc_c2h_tready;
+reg softmc_c2h_tlast;
+
+pcie_app_softmc uut(
+ .user_clk(user_clk),
+ .user_reset(user_reset),
+ .user_lnk_up(user_lnk_up),
+
+ .softmc_h2c_tdata(softmc_h2c_tdata),
+ .softmc_h2c_tvalid(softmc_h2c_tvalid),
+ .softmc_h2c_tready(softmc_h2c_tready),
+ .softmc_h2c_tlast(softmc_h2c_tlast),
+
+ .softmc_c2h_tdata(softmc_c2h_tdata),
+ .softmc_c2h_tvalid(softmc_c2h_tvalid),
+ .softmc_c2h_tready(softmc_c2h_tready),
+ .softmc_c2h_tlast(softmc_c2h_tlast),
+
+ .cfg_bus_number(cfg_bus_number),
+ .cfg_device_number(cfg_device_number),
+ .cfg_function_number(cfg_function_number),
+ .cfg_interrupt(cfg_interrupt),
+ .cfg_interrupt_assert(cfg_interrupt_assert),
+ .cfg_interrupt_rdy(cfg_interrupt_rdy),
+ .cfg_interrupt_di(cfg_interrupt_di),
+ .cfg_interrupt_msienable(cfg_interrupt_msienable),
+
+ .cfg_dcommand(cfg_dcommand),
+ .cfg_command(cfg_command),
+
+ .pci_cfg_dwaddr(pci_cfg_dwaddr),
+ .pci_cfg_rd_en(pci_cfg_rd_en),
+ .pci_cfg_dout(pci_cfg_dout),
+ .pci_cfg_rd_wr_done(pci_cfg_rd_wr_done),
+
+ .m_axis_rx_tready(m_axis_rx_tready),
+ .m_axis_rx_tdata(m_axis_rx_tdata),
+ .m_axis_rx_tkeep(m_axis_rx_tkeep),
+ .m_axis_rx_tlast(m_axis_rx_tlast),
+ .m_axis_rx_tvalid(m_axis_rx_tvalid),
+ .m_axis_rx_tuser(m_axis_rx_tuser),
+
+ .tx_src_dsc(tx_src_dsc),
+
+ .s_axis_tx_tdata(s_axis_tx_tdata),
+ .s_axis_tx_tkeep(s_axis_tx_tkeep),
+ .s_axis_tx_tlast(s_axis_tx_tlast),
+ .s_axis_tx_tvalid(s_axis_tx_tvalid),
+ .s_axis_tx_tready(s_axis_tx_tready),
+
+ .cfg_to_turnoff(cfg_to_turnoff),
+ .cfg_turnoff_ok(cfg_turnoff_ok),
+ .cfg_completer_id(cfg_completer_id)
+);
+
+always begin
+ user_clk = 0;
+ #5;
+ user_clk = 1;
+ #5;
+end
+
+
+// PCIe IP CFG Channel Simulation
+localparam READ_LATENCY = 'd3;
+
+reg cfg_read_en;
+reg cfg_read_en_prev;
+wire cfg_read_en_spike;
+
+reg [31:0] cfg_dout [0:READ_LATENCY-1];
+reg cfg_rd_done [0:READ_LATENCY-1];
+
+assign cfg_read_en_spike = cfg_read_en && !cfg_read_en_prev;
+assign pci_cfg_dout = cfg_dout[0];
+assign pci_cfg_rd_wr_done = cfg_rd_done[0];
+assign cfg_dcommand = 'b0000_0000_0000_0000;
+
+integer j;
+always @(posedge user_clk) begin
+ cfg_read_en <= pci_cfg_rd_en;
+ cfg_read_en_prev <= cfg_read_en;
+ cfg_dout[READ_LATENCY-1] <= pci_cfg_dwaddr == 'h04 ? 'hf0100000 :
+ pci_cfg_dwaddr == 'h05 ? 'hf0900000 : 'hffffffff;
+ cfg_rd_done[READ_LATENCY-1] <= cfg_read_en_spike;
+ for(j = 0; j < READ_LATENCY - 1; j = j + 1) begin
+ cfg_dout[j] <= cfg_dout[j+1];
+ cfg_rd_done[j] <= cfg_rd_done[j+1];
+ end
+end
+
+// c2h data generator
+localparam c2h_cap = 1024 * 8 * 8 / SOFTMC_STREAM_WIDTH;
+reg [31:0] c2h_count;
+reg [15:0] c2h_repeat;
+always @(posedge user_clk) begin
+ if (user_reset) begin
+ softmc_c2h_tdata <= 0;
+ softmc_c2h_tvalid <= 0;
+ softmc_c2h_tlast <= 0;
+ c2h_repeat <= 0;
+ c2h_count <= 0;
+ end
+ else if (softmc_c2h_tready && softmc_c2h_tvalid) begin
+ softmc_c2h_tdata <= {(SOFTMC_STREAM_WIDTH/16){c2h_repeat}};
+ softmc_c2h_tvalid <= c2h_count < (c2h_cap - 1);
+ softmc_c2h_tlast <= c2h_count == (c2h_cap - 2);
+ c2h_repeat <= c2h_repeat + (c2h_count < (c2h_cap - 1) ? 1 : 0);
+ c2h_count <= c2h_count + 1;
+ end
+ else if (!softmc_c2h_tvalid) begin
+ softmc_c2h_tdata <= {(SOFTMC_STREAM_WIDTH/16){c2h_repeat}};
+ softmc_c2h_tvalid <= c2h_count < (c2h_cap);
+ softmc_c2h_tlast <= c2h_count == (c2h_cap - 1);
+ c2h_repeat <= c2h_repeat + (c2h_count < (c2h_cap) ? 1 : 0);
+ end
+end
+
+always @(posedge user_clk) begin
+ if (cfg_interrupt) begin
+ cfg_command <= 'b0000_0100_0000_0100;
+ end
+ else begin
+ cfg_command <= 'b0000_0000_0000_0100;
+ end
+end
+
+// TLPs
+localparam CMD_LEN = 8;
+localparam TEST_DATA_LEN = 10 + 2; // 20 Data + 3 Header -> 12 in DW pacets
+
+reg [C_DATA_WIDTH-1:0] tb_dw_queue [0:CMD_LEN-1];
+reg [KEEP_WIDTH-1:0] tb_keep_queue [0:CMD_LEN-1];
+reg tb_tlast_queue [0:CMD_LEN-1];
+reg [21:0] tb_user_queue [0:CMD_LEN-1];
+
+reg [C_DATA_WIDTH-1:0] tb_cmp_queue [0:TEST_DATA_LEN-1];
+reg [KEEP_WIDTH-1:0] tb_cmp_keep_queue [0:TEST_DATA_LEN-1];
+reg tb_cmp_tlast_queue [0:TEST_DATA_LEN-1];
+reg [21:0] tb_cmp_user_queue [0:TEST_DATA_LEN-1];
+
+integer i;
+reg [7:0] data_repeat;
+initial begin
+ softmc_h2c_tready = 0;
+
+ tb_cmp_queue ['h00] = 'h0000000f_4a000014;
+ tb_cmp_keep_queue ['h00] = 'hff;
+ tb_cmp_tlast_queue ['h00] = 'h0;
+ tb_cmp_user_queue ['h00] = 'b00000000;
+ tb_cmp_queue ['h01] = 'h01010101_00000100;
+ tb_cmp_keep_queue ['h01] = 'hff;
+ tb_cmp_tlast_queue ['h01] = 'h0;
+ tb_cmp_user_queue ['h01] = 'b00000000;
+ for (i = 0; i < 9; i = i + 1) begin
+ data_repeat = 2 * i + 3;
+ tb_cmp_queue ['h02 + i][63:32] = {4{data_repeat}};
+ data_repeat = 2 * i + 2;
+ tb_cmp_queue ['h02 + i][31:0] = {4{data_repeat}};
+ tb_cmp_keep_queue ['h02 + i] = 'hff;
+ tb_cmp_tlast_queue ['h02 + i] = 'h0;
+ tb_cmp_user_queue ['h02 + i] = 'b00000000;
+ end
+ tb_cmp_queue ['h0b] = 'h00000000_14141414;
+ tb_cmp_keep_queue ['h0b] = 'h0f;
+ tb_cmp_tlast_queue ['h0b] = 'h1;
+ tb_cmp_user_queue ['h0b] = 'b00000000;
+
+ tb_dw_queue ['h00] = 'h0000000f_40000001;
+ tb_keep_queue ['h00] = 'hff;
+ tb_tlast_queue ['h00] = 'h0;
+ tb_user_queue ['h00] = 'b00000100;
+ tb_dw_queue ['h01] = 'h000001f8_f0100008;
+ tb_keep_queue ['h01] = 'hff;
+ tb_tlast_queue ['h01] = 'h1;
+ tb_user_queue ['h01] = 'b00000100;
+ tb_dw_queue ['h02] = 'h0000000f_40000001;
+ tb_keep_queue ['h02] = 'hff;
+ tb_tlast_queue ['h02] = 'h0;
+ tb_user_queue ['h02] = 'b00000100;
+ tb_dw_queue ['h03] = 'h01000000_f0100004;
+ tb_keep_queue ['h03] = 'hff;
+ tb_tlast_queue ['h03] = 'h1;
+ tb_user_queue ['h03] = 'b00000100;
+ tb_dw_queue ['h04] = 'h0000000f_40000001;
+ tb_keep_queue ['h04] = 'hff;
+ tb_tlast_queue ['h04] = 'h0;
+ tb_user_queue ['h04] = 'b00000100;
+ tb_dw_queue ['h05] = 'h09005000_f0100000;
+ tb_keep_queue ['h05] = 'hff;
+ tb_tlast_queue ['h05] = 'h1;
+ tb_user_queue ['h05] = 'b00000100;
+ tb_dw_queue ['h06] = 'h0000000f_40000001;
+ tb_keep_queue ['h06] = 'hff;
+ tb_tlast_queue ['h06] = 'h0;
+ tb_user_queue ['h06] = 'b00000100;
+ tb_dw_queue ['h07] = 'h000002f8_f0100014;
+ tb_keep_queue ['h07] = 'hff;
+ tb_tlast_queue ['h07] = 'h1;
+ tb_user_queue ['h07] = 'b00000100;
+
+ cfg_interrupt_msienable = 0;
+
+ cfg_bus_number = 0;
+ cfg_device_number = 1;
+ cfg_function_number = 0;
+ cfg_interrupt_rdy = 0;
+ user_reset = 1;
+ user_lnk_up = 0;
+ m_axis_rx_tvalid = 0;
+ s_axis_tx_tready = 0;
+ #100;
+ @(posedge user_clk) #1;
+ user_reset = 0;
+ user_lnk_up = 1;
+ cfg_interrupt_rdy = 1;
+ s_axis_tx_tready = 1;
+ softmc_h2c_tready = 1;
+
+ for (i = 0; i < CMD_LEN; ) begin
+ m_axis_rx_tdata = tb_dw_queue[i];
+ m_axis_rx_tkeep = tb_keep_queue[i];
+ m_axis_rx_tlast = tb_tlast_queue[i];
+ m_axis_rx_tuser = tb_user_queue[i];
+ m_axis_rx_tvalid = 1;
+ if (m_axis_rx_tready && m_axis_rx_tvalid) begin
+ i = i + 1;
+ end
+ @(posedge user_clk) #1;
+ end
+ m_axis_rx_tvalid = 0;
+ m_axis_rx_tlast = 0;
+ m_axis_rx_tkeep = 0;
+
+ wait(s_axis_tx_tlast);
+ @(posedge user_clk) #1;
+ for (i = 0; i < TEST_DATA_LEN; ) begin
+ m_axis_rx_tdata = tb_cmp_queue[i];
+ m_axis_rx_tkeep = tb_cmp_keep_queue[i];
+ m_axis_rx_tlast = tb_cmp_tlast_queue[i];
+ m_axis_rx_tuser = tb_cmp_user_queue[i];
+ m_axis_rx_tvalid = 1;
+ if (m_axis_rx_tready && m_axis_rx_tvalid) begin
+ i = i + 1;
+ end
+ @(posedge user_clk) #1;
+ end
+ m_axis_rx_tvalid = 0;
+ m_axis_rx_tlast = 0;
+ m_axis_rx_tkeep = 0;
+
+ wait(c2h_count == c2h_cap);
+ tb_dw_queue ['h00] = 'h0000000f_40000001;
+ tb_keep_queue ['h00] = 'hff;
+ tb_tlast_queue ['h00] = 'h0;
+ tb_user_queue ['h00] = 'b00000100;
+ tb_dw_queue ['h01] = 'h000002f8_f0100008;
+ tb_keep_queue ['h01] = 'hff;
+ tb_tlast_queue ['h01] = 'h1;
+ tb_user_queue ['h01] = 'b00000100;
+ tb_dw_queue ['h02] = 'h0000000f_40000001;
+ tb_keep_queue ['h02] = 'hff;
+ tb_tlast_queue ['h02] = 'h0;
+ tb_user_queue ['h02] = 'b00000100;
+ tb_dw_queue ['h03] = 'h01000000_f0100004;
+ tb_keep_queue ['h03] = 'hff;
+ tb_tlast_queue ['h03] = 'h1;
+ tb_user_queue ['h03] = 'b00000100;
+ tb_dw_queue ['h04] = 'h0000000f_40000001;
+ tb_keep_queue ['h04] = 'hff;
+ tb_tlast_queue ['h04] = 'h0;
+ tb_user_queue ['h04] = 'b00000100;
+ tb_dw_queue ['h05] = 'h03000020_f0100000;
+ tb_keep_queue ['h05] = 'hff;
+ tb_tlast_queue ['h05] = 'h1;
+ tb_user_queue ['h05] = 'b00000100;
+
+ for (i = 0; i < CMD_LEN; ) begin
+ m_axis_rx_tdata = tb_dw_queue[i];
+ m_axis_rx_tkeep = tb_keep_queue[i];
+ m_axis_rx_tlast = tb_tlast_queue[i];
+ m_axis_rx_tuser = tb_user_queue[i];
+ m_axis_rx_tvalid = 1;
+ if (m_axis_rx_tready && m_axis_rx_tvalid) begin
+ i = i + 1;
+ end
+ @(posedge user_clk) #1;
+ end
+ m_axis_rx_tvalid = 0;
+ m_axis_rx_tlast = 0;
+ m_axis_rx_tkeep = 0;
+end
+
+endmodule
diff --git a/projects/ZC706/ZC706.srcs/sim_1/tb_pcie_txn_buffer.v b/projects/ZC706/ZC706.srcs/sim_1/tb_pcie_txn_buffer.v
new file mode 100644
index 0000000..8fc4050
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sim_1/tb_pcie_txn_buffer.v
@@ -0,0 +1,101 @@
+`timescale 1ns / 1ps
+
+module tb_pcie_txn_buffer();
+
+localparam C_IN_DATA_WIDTH = 128;
+localparam C_OUT_DATA_WIDTH = 64;
+localparam C_IN_KEEP = C_IN_DATA_WIDTH / 8;
+localparam C_OUT_KEEP = C_OUT_DATA_WIDTH / 8;
+localparam DATA_COUNT_WIDTH = 32;
+
+reg clk;
+reg reset;
+reg [C_IN_DATA_WIDTH-1:0] s_axis_tdata;
+reg [C_IN_KEEP-1:0] s_axis_tkeep;
+reg s_axis_tvalid;
+wire s_axis_tready;
+reg s_axis_tlast;
+wire [C_OUT_DATA_WIDTH-1:0] m_axis_tdata;
+wire [C_OUT_DATA_WIDTH/2-1:0] m_axis_upper_half_data;
+wire [C_OUT_KEEP-1:0] m_axis_tkeep;
+wire [C_OUT_KEEP/2-1:0] m_axis_upper_half_keep;
+wire m_axis_tvalid;
+wire m_axis_upper_half_valid;
+reg m_axis_tready;
+reg m_axis_upper_half_ready;
+wire [DATA_COUNT_WIDTH-1:0] data_count;
+wire programmed_stop;
+
+pcie_txn_buffer #(
+ .C_IN_DATA_WIDTH(C_IN_DATA_WIDTH),
+ .C_OUT_DATA_WIDTH(C_OUT_DATA_WIDTH)
+) uut (
+ .clk(clk),
+ .reset(reset),
+ .s_axis_tdata(s_axis_tdata),
+ .s_axis_tkeep(s_axis_tkeep),
+ .s_axis_tvalid(s_axis_tvalid),
+ .s_axis_tready(s_axis_tready),
+ .s_axis_tlast(s_axis_tlast),
+ .m_axis_tdata(m_axis_tdata),
+ .m_axis_upper_half_data(m_axis_upper_half_data),
+ .m_axis_tkeep(m_axis_tkeep),
+ .m_axis_upper_half_keep(m_axis_upper_half_keep),
+ .m_axis_tvalid(m_axis_tvalid),
+ .m_axis_upper_half_valid(m_axis_upper_half_valid),
+ .m_axis_tready(m_axis_tready),
+ .m_axis_upper_half_ready(m_axis_upper_half_ready),
+ .data_count(data_count),
+ .programmed_stop(programmed_stop)
+);
+
+always begin
+ clk = 0;
+ #5;
+ clk = 1;
+ #5;
+end
+
+integer i;
+
+localparam WRITE_LENGTH = 16;
+
+initial begin
+ s_axis_tdata = 0;
+ s_axis_tkeep = 0;
+ s_axis_tvalid = 0;
+ s_axis_tlast = 0;
+ m_axis_tready = 0;
+ m_axis_upper_half_ready = 0;
+ reset = 1;
+ repeat (10) @(posedge clk) #1;
+ reset = 0;
+ for (i = 0; i < WRITE_LENGTH;) begin
+ s_axis_tdata = {C_IN_KEEP{i[C_IN_KEEP-1:0]}};
+ s_axis_tkeep = {C_IN_KEEP{1'b1}};
+ s_axis_tvalid = 1;
+ if (s_axis_tready && s_axis_tvalid) begin
+ i = i + 1;
+ end
+ @(posedge clk) #2;
+ end
+ s_axis_tvalid = 0;
+ m_axis_tready = 0;
+ m_axis_upper_half_ready = 0;
+ wait(m_axis_tvalid);
+ @(posedge clk) #2;
+ m_axis_tready = 0;
+ m_axis_upper_half_ready = 1;
+ @(posedge clk) #2;
+ m_axis_tready = 1;
+ m_axis_upper_half_ready = 0;
+ wait(!m_axis_tvalid);
+ @(posedge clk) #2;
+ m_axis_tready = 1;
+ m_axis_upper_half_ready = 1;
+ repeat(5) @(posedge clk) #2;
+ m_axis_tready = 0;
+ m_axis_upper_half_ready = 0;
+end
+
+endmodule
diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci
new file mode 100644
index 0000000..0a1221f
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter.xci
@@ -0,0 +1,133 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ axis_clock_converter
+
+
+
+ 100000000
+ 1
+ 1
+ 1
+ 0
+ 0
+ undef
+ 0.000
+ 32
+ 0
+ 0
+ 0
+ ACTIVE_LOW
+
+
+
+ 100000000
+ 0
+ 0
+ 0.000
+ 0
+ ACTIVE_LOW
+
+ 100000000
+ 1
+ 1
+ 1
+ 0
+ 0
+ undef
+ 0.000
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+ ACTIVE_LOW
+
+
+
+ 100000000
+ 0
+ 0
+ 0.000
+ 0
+ ACTIVE_LOW
+ 0
+ 0b00000000000000000000000000011011
+ 256
+ 1
+ 1
+ 1
+ zynq
+ 1
+ 2
+ 2
+ 1
+ 0
+ 1:2
+ axis_clock_converter
+ 1
+ 1
+ 0
+ 1
+ 2
+ 32
+ 0
+ 0
+ 0
+ zynq
+ xilinx.com:zc706:part0:1.4
+
+ xc7z045
+ ffg900
+ VERILOG
+
+ MIXED
+ -2
+
+
+ TRUE
+ TRUE
+ IP_Flow
+ 23
+ TRUE
+ ../../../../ZC706.gen/sources_1/ip/axis_clock_converter
+
+ .
+ 2020.2
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/data_fifo/data_fifo.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/data_fifo/data_fifo.xci
new file mode 100644
index 0000000..488039f
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sources_1/ip/data_fifo/data_fifo.xci
@@ -0,0 +1,594 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ data_fifo
+
+
+
+
+
+ 100000000
+ 0
+ 0
+ 0.000
+
+
+ 100000000
+ 0
+ 0
+ 0.000
+ 1
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+ 0
+
+ 1
+ 100000000
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+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
+ 0
+ 0
+ 0
+ 0
+
+ 100000000
+ 1
+ 0
+ 1
+ 0
+ 0
+ undef
+ 0.000
+ 32
+ 0
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+ 0
+
+
+
+ 100000000
+ 0
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+
+ 100000000
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+ 100000000
+ 0
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+ 0
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+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
+ 0
+ 0
+ 0
+ 0
+
+ 100000000
+ 1
+ 0
+ 1
+ 0
+ 0
+ undef
+ 0.000
+ 32
+ 0
+ 0
+ 0
+
+
+
+ 100000000
+ 0
+ 0
+ 0.000
+ 0
+ 0
+ 0
+ 0
+ 0
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+ 256
+ 1
+ 1
+ 32
+ 32
+ 1
+ 0
+ 32
+ 1
+ 1
+ 1
+ 64
+ 1
+ 8
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 10
+ BlankString
+ 18
+ 288
+ 32
+ 64
+ 32
+ 64
+ 2
+ 0
+ 18
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ zynq
+ 1
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+ 1
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+ 1
+ 0
+ 0
+ 0
+ 1
+ 0
+ 4kx4
+ 512x72
+ 512x36
+ 1kx36
+ 512x36
+ 1kx36
+ 512x36
+ 2
+ 62
+ 14
+ 1022
+ 14
+ 1022
+ 14
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1022
+ 63
+ 15
+ 1023
+ 15
+ 1023
+ 15
+ 1021
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 10
+ 1024
+ 1
+ 10
+ 0
+ 0
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+ 0
+ 0
+ 0
+ 2
+ 0
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+ 0
+ 0
+ 1
+ 0
+ 0
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+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 10
+ 1024
+ 64
+ 16
+ 1024
+ 16
+ 1024
+ 16
+ 1
+ 10
+ 6
+ 4
+ 10
+ 4
+ 10
+ 4
+ 1
+ 32
+ 0
+ 0
+ false
+ false
+ false
+ 0
+ 0
+ Slave_Interface_Clock_Enable
+ Common_Clock
+ data_fifo
+ 64
+ false
+ 10
+ false
+ false
+ 0
+ 2
+ 62
+ 14
+ 1022
+ 14
+ 1022
+ 14
+ 3
+ false
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ false
+ Hard_ECC
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ true
+ false
+ true
+ Data_FIFO
+ Data_FIFO
+ Data_FIFO
+ Data_FIFO
+ Data_FIFO
+ Data_FIFO
+ Common_Clock_Block_RAM
+ Common_Clock_Distributed_RAM
+ Common_Clock_Block_RAM
+ Common_Clock_Distributed_RAM
+ Common_Clock_Block_RAM
+ Common_Clock_Distributed_RAM
+ Common_Clock_Block_RAM
+ 1
+ 1022
+ 63
+ 15
+ 1023
+ 15
+ 1023
+ 15
+ 1021
+ false
+ true
+ false
+ 0
+ AXI_STREAM
+ false
+ false
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+ false
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+ false
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+ false
+ false
+ false
+ false
+ 18
+ 1024
+ 64
+ 16
+ 1024
+ 16
+ 1024
+ 16
+ false
+ 18
+ 1024
+ Embedded_Reg
+ false
+ false
+ Active_High
+ Active_High
+ AXI4
+ Standard_FIFO
+ No_Programmable_Empty_Threshold
+ No_Programmable_Empty_Threshold
+ No_Programmable_Empty_Threshold
+ No_Programmable_Empty_Threshold
+ No_Programmable_Empty_Threshold
+ No_Programmable_Empty_Threshold
+ No_Programmable_Empty_Threshold
+ No_Programmable_Full_Threshold
+ No_Programmable_Full_Threshold
+ No_Programmable_Full_Threshold
+ No_Programmable_Full_Threshold
+ No_Programmable_Full_Threshold
+ No_Programmable_Full_Threshold
+ No_Programmable_Full_Threshold
+ READ_WRITE
+ 0
+ 1
+ false
+ 10
+ Fully_Registered
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+ Fully_Registered
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+ Fully_Registered
+ true
+ Asynchronous_Reset
+ false
+ 32
+ 0
+ 0
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+ 32
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+ false
+ Active_High
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+ true
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+ false
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+ 0
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+ Active_High
+ 1
+ false
+ 10
+ false
+ FIFO
+ false
+ false
+ false
+ false
+ FIFO
+ FIFO
+ 2
+ 2
+ false
+ FIFO
+ FIFO
+ FIFO
+ zynq
+ xilinx.com:zc706:part0:1.4
+
+ xc7z045
+ ffg900
+ VERILOG
+
+ MIXED
+ -2
+
+
+ TRUE
+ TRUE
+ IP_Flow
+ 5
+ TRUE
+ ../../../../ZC706.gen/sources_1/ip/data_fifo
+
+ .
+ 2020.2
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci
new file mode 100644
index 0000000..bf2af3a
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci
@@ -0,0 +1,316 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ instr_blk_mem
+
+
+ 4096
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 100000000
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 100000000
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
+ 0
+ 0
+ 0
+ 0
+ OTHER
+ NONE
+ 8192
+ 32
+ 1
+
+ OTHER
+ NONE
+ 8192
+ 32
+ 1
+
+
+ 100000000
+ 0
+ 0
+ 0.000
+ 0
+ 11
+ 11
+ 1
+ 4
+ 0
+ 1
+ 9
+ 0
+ 0
+ 4
+ NONE
+ 0
+ 0
+ 0
+ ./
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ Estimated Power for IP : 10.698001 mW
+ zynq
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ instr_blk_mem.mem
+ no_coe_file_loaded
+ 0
+ 0
+ 0
+ 0
+ 1
+ 2048
+ 2048
+ 1
+ 1
+ 64
+ 64
+ 0
+ 0
+ CE
+ CE
+ ALL
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 2048
+ 2048
+ WRITE_FIRST
+ WRITE_FIRST
+ 64
+ 64
+ zynq
+ 4
+ Memory_Slave
+ AXI4_Full
+ false
+ Minimum_Area
+ false
+ 9
+ NONE
+ no_coe_file_loaded
+ ALL
+ instr_blk_mem
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ Use_ENA_Pin
+ Always_Enabled
+ Single_Bit_Error_Injection
+ false
+ Native
+ false
+ no_mem_loaded
+ Single_Port_RAM
+ WRITE_FIRST
+ WRITE_FIRST
+ 0
+ 0
+ BRAM
+ 0
+ 100
+ 100
+ 50
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+ 0
+ 0
+ 8kx2
+ false
+ false
+ 1
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+ false
+ false
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+ false
+ 0
+ false
+ false
+ CE
+ CE
+ SYNC
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ 2048
+ 64
+ 64
+ No_ECC
+ false
+ false
+ false
+ Stand_Alone
+ zynq
+ xilinx.com:zc706:part0:1.4
+
+ xc7z045
+ ffg900
+ VERILOG
+
+ MIXED
+ -2
+
+
+ TRUE
+ TRUE
+ IP_Flow
+ 4
+ TRUE
+ ../../../../ZC706.gen/sources_1/ip/instr_blk_mem
+
+ .
+ 2020.2
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xci
new file mode 100644
index 0000000..7b74ab8
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sources_1/ip/instr_blk_mem_sim/instr_blk_mem_sim.xci
@@ -0,0 +1,319 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ instr_blk_mem_sim
+
+
+ 4096
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 100000000
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 100000000
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
+ 0
+ 0
+ 0
+ 0
+ OTHER
+ NONE
+ 8192
+ 32
+ 1
+
+ OTHER
+ NONE
+ 8192
+ 32
+ 1
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+
+ 100000000
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+ 0
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+ 1
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+ 0
+ 0
+ 2
+ NONE
+ 0
+ 0
+ 0
+ ./
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ Estimated Power for IP : 5.9043 mW
+ zynq
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
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+ instr_blk_mem_sim.mem
+ instr_blk_mem_sim.mif
+ 0
+ 1
+ 0
+ 0
+ 1
+ 1024
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+ 1
+ 1
+ 64
+ 64
+ 0
+ 0
+ CE
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+ ALL
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+ 0
+ 0
+ 0
+ 1
+ 1
+ 1024
+ 1024
+ WRITE_FIRST
+ WRITE_FIRST
+ 64
+ 64
+ zynq
+ 4
+ Memory_Slave
+ AXI4_Full
+ false
+ Minimum_Area
+ false
+ 9
+ NONE
+ ../../../../coe/simmem.coe
+ ALL
+ instr_blk_mem_sim
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ Use_ENA_Pin
+ Always_Enabled
+ Single_Bit_Error_Injection
+ true
+ Native
+ true
+ no_mem_loaded
+ Single_Port_RAM
+ WRITE_FIRST
+ WRITE_FIRST
+ 0
+ 0
+ BRAM
+ 0
+ 100
+ 100
+ 50
+ 0
+ 0
+ 0
+ 8kx2
+ false
+ false
+ 1
+ 1
+ 64
+ 64
+ false
+ false
+ false
+ false
+ 0
+ false
+ false
+ CE
+ CE
+ SYNC
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ 1024
+ 64
+ 64
+ No_ECC
+ false
+ false
+ false
+ Stand_Alone
+ zynq
+ xilinx.com:zc706:part0:1.4
+
+ xc7z045
+ ffg900
+ VERILOG
+
+ MIXED
+ -2
+
+
+ TRUE
+ TRUE
+ IP_Flow
+ 4
+ TRUE
+ ../../../../ZC706.gen/sources_1/ip/instr_blk_mem_sim
+
+ .
+ 2020.2
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/instr_fifo/instr_fifo.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/instr_fifo/instr_fifo.xci
new file mode 100644
index 0000000..83e0abc
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sources_1/ip/instr_fifo/instr_fifo.xci
@@ -0,0 +1,593 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ instr_fifo
+
+
+
+
+
+ 100000000
+ 0
+ 0
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+
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+ 100000000
+ 0
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+ 1
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+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
+ 0
+ 0
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+ 0
+
+ 100000000
+ 0
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+ 0
+ 0
+ undef
+ 0.000
+ 32
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+
+
+ 100000000
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+
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+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
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+ BlankString
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+ Slave_Interface_Clock_Enable
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+ instr_fifo
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+ true
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+ Data_FIFO
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+ Common_Clock_Block_RAM
+ Common_Clock_Distributed_RAM
+ Common_Clock_Block_RAM
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+ false
+ false
+ false
+ false
+ false
+ false
+ 18
+ 1024
+ 2048
+ 16
+ 1024
+ 16
+ 1024
+ 16
+ false
+ 18
+ 1024
+ Embedded_Reg
+ false
+ false
+ Active_High
+ Active_High
+ AXI4
+ Standard_FIFO
+ No_Programmable_Empty_Threshold
+ No_Programmable_Empty_Threshold
+ No_Programmable_Empty_Threshold
+ No_Programmable_Empty_Threshold
+ No_Programmable_Empty_Threshold
+ No_Programmable_Empty_Threshold
+ No_Programmable_Empty_Threshold
+ No_Programmable_Full_Threshold
+ No_Programmable_Full_Threshold
+ No_Programmable_Full_Threshold
+ No_Programmable_Full_Threshold
+ No_Programmable_Full_Threshold
+ No_Programmable_Full_Threshold
+ No_Programmable_Full_Threshold
+ READ_WRITE
+ 0
+ 1
+ false
+ 10
+ Fully_Registered
+ Fully_Registered
+ Fully_Registered
+ Fully_Registered
+ Fully_Registered
+ Fully_Registered
+ true
+ Asynchronous_Reset
+ false
+ 32
+ 0
+ 0
+ 32
+ 32
+ 0
+ false
+ false
+ Active_High
+ Active_High
+ true
+ false
+ false
+ false
+ false
+ Active_High
+ 0
+ false
+ Active_High
+ 1
+ false
+ 10
+ false
+ FIFO
+ false
+ false
+ false
+ false
+ FIFO
+ FIFO
+ 2
+ 2
+ false
+ FIFO
+ FIFO
+ FIFO
+ zynq
+ xilinx.com:zc706:part0:1.4
+
+ xc7z045
+ ffg900
+ VERILOG
+
+ MIXED
+ -2
+
+
+ TRUE
+ TRUE
+ IP_Flow
+ 5
+ TRUE
+ ../../../../ZC706.gen/sources_1/ip/instr_fifo
+
+ .
+ 2020.2
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/doc/pcie_7x_v3_3_changelog.txt b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/doc/pcie_7x_v3_3_changelog.txt
new file mode 100644
index 0000000..32c4ed5
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/doc/pcie_7x_v3_3_changelog.txt
@@ -0,0 +1,280 @@
+2020.2:
+ * Version 3.3 (Rev. 14)
+ * General: Added Zynq 7z030i,7z035i,7z045i and 7z100i device support
+
+2020.1.1:
+ * Version 3.3 (Rev. 13)
+ * No changes
+
+2020.1:
+ * Version 3.3 (Rev. 13)
+ * Revision change in one or more subcores
+
+2019.2.2:
+ * Version 3.3 (Rev. 12)
+ * No changes
+
+2019.2.1:
+ * Version 3.3 (Rev. 12)
+ * No changes
+
+2019.2:
+ * Version 3.3 (Rev. 12)
+ * Revision change in one or more subcores
+
+2019.1.3:
+ * Version 3.3 (Rev. 11)
+ * No changes
+
+2019.1.2:
+ * Version 3.3 (Rev. 11)
+ * No changes
+
+2019.1.1:
+ * Version 3.3 (Rev. 11)
+ * No changes
+
+2019.1:
+ * Version 3.3 (Rev. 11)
+ * General: Added new device xa7k160t.
+ * Revision change in one or more subcores
+
+2018.3.1:
+ * Version 3.3 (Rev. 10)
+ * No changes
+
+2018.3:
+ * Version 3.3 (Rev. 10)
+ * Bug Fix: Fixed JTAG debugger Issue.
+ * Bug Fix: Added waviers for lint errors.
+ * Revision change in one or more subcores
+
+2018.2:
+ * Version 3.3 (Rev. 9)
+ * Bug Fix: Updated MSIX TABLE & PBA OFFSET parameters. Which effects MSI-X functionality
+ * Revision change in one or more subcores
+
+2018.1:
+ * Version 3.3 (Rev. 8)
+ * General: Added support for xa7a12t(cpg238,csg325) and xa7a25t(cpg238,csg325) devices
+ * Revision change in one or more subcores
+
+2017.4:
+ * Version 3.3 (Rev. 7)
+ * General: Removed 'xx' in the Interface values
+ * Revision change in one or more subcores
+
+2017.3:
+ * Version 3.3 (Rev. 6)
+ * Bug Fix: Updated arrow colors for JTAG debugger LTSSM graph
+ * Feature Enhancement: Enabled support for cpg238 package for devices - xc7a12t,xc7a12ti,xc7a12tl,xc7a25t,xc7z25ti and xc7a25tl
+ * Revision change in one or more subcores
+
+2017.2:
+ * Version 3.3 (Rev. 5)
+ * Revision change in one or more subcores
+
+2017.1:
+ * Version 3.3 (Rev. 4)
+ * Bug Fix: Removed unwanted display messages
+ * Bug Fix: Removed option to select 250Mhz of UserClk_freq (AXI Interface Frequency) for the devices xc7z015,xc7z15i and xc7z12s since the timing does not meet
+ * Feature Enhancement: Added JTAG debugger support to debug LTSSM, Reset sequence and Rx detect sequence.User option is added in the 'Add.Debug Options' GUI page
+ * Revision change in one or more subcores
+
+2016.4:
+ * Version 3.3 (Rev. 3)
+ * General: Added support for xc7a12tl and xc7a25tl devices
+ * Revision change in one or more subcores
+
+2016.3:
+ * Version 3.3 (Rev. 2)
+ * Bug Fix: Updated text in core configuration GUI to display Capabilities Register value as 0x0142 when Slot Implemented option is selected for Rootport Mode
+ * Other: Added support for xc7a12t,xc7a12t,xc7a25t,xc7a25ti and xc7z012s devices
+ * Revision change in one or more subcores
+
+2016.2:
+ * Version 3.3 (Rev. 1)
+ * Reduced the number of characters on a single line by making a multi-line attribute assignment.
+ * Added CDC registers to the pl_phy_lnk_up and pl_received_hot_rst PCIe outputs.
+ * Revision change in one or more subcores
+
+2016.1:
+ * Version 3.3
+ * Modified the width of pipe_tx_*_sigs, common_commands_in and common_commands_out
+ * Added Tandem support for xc7z035
+ * Modified the mapping of logical and physical external pipe interface ports for End Point configurations so that it can be connected to Root Port instance directly
+ * Fixed issue with the default values of 'Base Class Menu' and 'Sub Class Interface Menu' and 'Class Code' update when Lookup Assistant option is used
+ * Removed the dependency of 'Include Shared Logic(clocking)in example design' on 'External PIPE Interface' pipe mode simulation option.No changes made to the 'Enable Pipe mode Simulation' option
+ * Revision change in one or more subcores
+
+2015.4.2:
+ * Version 3.2 (Rev. 1)
+ * No changes
+
+2015.4.1:
+ * Version 3.2 (Rev. 1)
+ * No changes
+
+2015.4:
+ * Version 3.2 (Rev. 1)
+ * Fixed unresolved instances of sys_clk_gen used in pipe mode simulations. This module is now delivered in 'source' directory
+
+2015.3:
+ * Version 3.2
+ * For EXTERNAL PIPE INTERFACE mode, a new file xil_sig2pipe.v is delivered in the simulation directory and it replaces the phy_sig_gen.v. BFM/VIP’s should interface with the xil_sig2pipe instance in board.v
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * Revision change in one or more subcores
+
+2015.2.1:
+ * Version 3.1 (Rev. 1)
+ * No changes
+
+2015.2:
+ * Version 3.1 (Rev. 1)
+ * Fixed GTP DRP write issue - (Xilinx Answer 62770)
+ * Added support for xq7z100 device
+ * Added support for Post Synthesis/Implementation netlist simulation for EP/Verilog mode, for non-PIPE mode only
+
+2015.1:
+ * Version 3.1
+ * Added support for xc7a35ti,xc7a50ti,xc7a75ti,xc7a100ti and xc7a200ti devices.
+ * Added non-default input port pipe_txinhibit.
+ * Fixed issue with invalid link width and speeds for -1 speed grade for devices xc7z030i and xc7z015i devices (x8 is not supported and incase of xc7z015i only Gen1 speeds are supported when speedgrade -1 is selected).
+ * Added support for new packages: fbv484,fbv676,ffv1156,ffv900,fbv900 and ffv901
+ * Added shared logic support for RP configuration.
+ * Modified the External Pipe Interface as Master for Rootport configuration and Slave for Endpoint and Legacy Endpoint configurations.
+ * Update to generate a 100MHz icap_clk for tandem configurations rather than using the ref_clk input.
+ * Removed 250Mhz User clock frequency option for all -1,-1I,-1M,-1Q,-1L speedgrades of Artix7 family.
+
+2014.4.1:
+ * Version 3.0 (Rev. 4)
+ * No changes
+
+2014.4:
+ * Version 3.0 (Rev. 4)
+ * Enhancement to allow debug cores to work better within Tandem designs. Build_stage1.tcl now runs befor place_design and handles bscan primitives.
+ * Added support for Artix7 xc7a15t, xc7a15tl and xa7a15t devices
+ * Added support for Zynq xc7z035 device
+ * Changed the pipe mode simulation options in GUI to radio buttons (No change in the functionality)
+
+2014.3:
+ * Version 3.0 (Rev. 3)
+ * Enabled PIPE Sim support for Root Port configuration
+ * Added support for Kintex7 Low voltage (0.9v) variants, for only Gen1 speed
+ * Added support for Kintex7 Defense grade Low voltage (0.9v) variants, for only Gen1 speed
+ * Fixed CPLL Power spike on power up issue (AR59294)
+
+2014.2:
+ * Version 3.0 (Rev. 2)
+ * Added AZynq7030 device support
+ * Added QArtix 50t device support
+ * Enabled PIPE simulation and External PIPE interface support only when shared logic option Shared Logic (clocking) in example design is selected
+
+2014.1:
+ * Version 3.0 (Rev. 1)
+ * Added Zynq7015 device support
+ * Added 35t,50t and 75t support for Artix7l and Aartix7 devices
+ * Added cpg236 and csg325 packages support for Artix7 devices
+ * Enabled Tandem PROM configuration support for Zynq 7030 and for Zynq7045 devices
+ * Enabled Tandem Configuration support for Kintex 420T device
+ * Changed the directory structure of the core without affecting the design hierarchy
+
+2013.4:
+ * Version 3.0
+ * Added XC7Z200TSBG484 device support
+ * Added support Artix7 35t, 50t and 75t devices
+ * Added port level enablement for icap and startup signal interfaces
+ * Added 3 new ports - pipe_rxstatus, pipe_eyescandataerror and pipe_dmonitordout to the transceiver debug interface
+ * Added logic to power down CPLL until it is required during the PCIe link bring-up
+
+2013.3:
+ * Version 2.2
+ * Reduced Warnings in Simulations
+ * Reduced Warnings in Synthesis
+ * Implemented Shared Logic for Clocking and Transeciver GT Common blocks to include either in core or example design
+ * Implemented Tarnsceiver Core Debug interface. Brought the debug signals to the port level
+ * Brought the Ext GT DRP signals upto the core top port level
+ * Added support for IPI integrator
+ * Updated xdc to match IP hierarchy
+ * Added support for Cadence IES and Synopsys VCS Simulators
+ * Added support for upgrade from previous versions
+ * Added support for Zynq 7100 device
+ * Added new pages Shared Logic and Core interface Parameters in GUI in Advanced mode
+ * Added Enablement of PCIe DRP interface and made the option true by default
+ * PCIe Sideband interface is broken into several smaller interfaces to connect with DMA IP in IPI
+ * Added support for External PIPE interface mode
+
+2013.2:
+ * Version 2.1
+ * Enhancements in the Tandem Logic - added STARTUP Premitive and new ports related to this premitive (static ports)
+ * Removed the redundant blocks related to Tandem configuration logic
+ * Added AER_CAP_ECRC_GEN_CAPABLE parameter in XGUI
+ * Added option to select the Internal or external clocking module (Parameter PCIE_EXT_CLK)
+ * Marked Artix7 (fgg484 and fbg484) and Zynq devices as production. Added GES_and_Production option for Silicon_Rev parameter. Updated the Auto-Upgrade Script
+ * Added support for Artix7 and Kintex7 Lowvoltage family
+ * Shortened the example design xdc file name (PG updated)
+ * IPI Level 0 Support
+ * Added OOC flow support
+ * Fixed CDC issues with GT wrappers
+ * Removed the BETA tag for Tandem PROM and Tandem PCIe options
+ * For x8g1, 128-bit interface width configuration, Removed the optional 250MHz. Updated the Auto-upgrade script
+
+2013.1:
+ * Version 2.0
+ * Lower case ports for Verilog
+ * Added Zynq Support
+ * Fixed Reset Sequence issue with GTPs
+ * Fixed TXOUTCLK flatline issue
+ * Fixed the issue with GUI to select the optional frequency for g2x4, 128-bit configuration. Now the selection for 250Mhz optional frequency is removed as it is not supported configuration
+ * Fixed XSIM issues with VHDL version of the core
+ * Changed upper case portlevel signals to lower case (clocking interface for partial re-configuration and ICAP interface)
+ * Added pipe_mmcm_rst_n signal at the port level as input in the core top file.
+ * All Kintex devices, Virtex 2000T, Artix 100t/ffg676, 200T/fbg676,ffg1156 are marked as Production. Option is added in GUI to select GES_and_Production
+ * Tandem Configuration - The option is enabled independent of the Dev board selection for Kintex 325/ffg900 and Virtex 485/ffg1761/PCIe Block X1Y0
+ * Tandem Confguration - Create Bin files for stage 2, Back Up & restore of bitstream generation settings
+
+(c) Copyright 2002 - 2020 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.dcp b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.dcp
new file mode 100644
index 0000000..34352e3
Binary files /dev/null and b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.dcp differ
diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.veo b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.veo
new file mode 100644
index 0000000..c844b63
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.veo
@@ -0,0 +1,240 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:pcie_7x:3.3
+// IP Revision: 14
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+pcie_7x_0 your_instance_name (
+ .pci_exp_txp(pci_exp_txp), // output wire [3 : 0] pci_exp_txp
+ .pci_exp_txn(pci_exp_txn), // output wire [3 : 0] pci_exp_txn
+ .pci_exp_rxp(pci_exp_rxp), // input wire [3 : 0] pci_exp_rxp
+ .pci_exp_rxn(pci_exp_rxn), // input wire [3 : 0] pci_exp_rxn
+ .pipe_pclk_in(pipe_pclk_in), // input wire pipe_pclk_in
+ .pipe_rxusrclk_in(pipe_rxusrclk_in), // input wire pipe_rxusrclk_in
+ .pipe_rxoutclk_in(pipe_rxoutclk_in), // input wire [3 : 0] pipe_rxoutclk_in
+ .pipe_dclk_in(pipe_dclk_in), // input wire pipe_dclk_in
+ .pipe_userclk1_in(pipe_userclk1_in), // input wire pipe_userclk1_in
+ .pipe_userclk2_in(pipe_userclk2_in), // input wire pipe_userclk2_in
+ .pipe_oobclk_in(pipe_oobclk_in), // input wire pipe_oobclk_in
+ .pipe_mmcm_lock_in(pipe_mmcm_lock_in), // input wire pipe_mmcm_lock_in
+ .pipe_txoutclk_out(pipe_txoutclk_out), // output wire pipe_txoutclk_out
+ .pipe_rxoutclk_out(pipe_rxoutclk_out), // output wire [3 : 0] pipe_rxoutclk_out
+ .pipe_pclk_sel_out(pipe_pclk_sel_out), // output wire [3 : 0] pipe_pclk_sel_out
+ .pipe_gen3_out(pipe_gen3_out), // output wire pipe_gen3_out
+ .user_clk_out(user_clk_out), // output wire user_clk_out
+ .user_reset_out(user_reset_out), // output wire user_reset_out
+ .user_lnk_up(user_lnk_up), // output wire user_lnk_up
+ .user_app_rdy(user_app_rdy), // output wire user_app_rdy
+ .tx_buf_av(tx_buf_av), // output wire [5 : 0] tx_buf_av
+ .tx_cfg_req(tx_cfg_req), // output wire tx_cfg_req
+ .tx_err_drop(tx_err_drop), // output wire tx_err_drop
+ .s_axis_tx_tready(s_axis_tx_tready), // output wire s_axis_tx_tready
+ .s_axis_tx_tdata(s_axis_tx_tdata), // input wire [63 : 0] s_axis_tx_tdata
+ .s_axis_tx_tkeep(s_axis_tx_tkeep), // input wire [7 : 0] s_axis_tx_tkeep
+ .s_axis_tx_tlast(s_axis_tx_tlast), // input wire s_axis_tx_tlast
+ .s_axis_tx_tvalid(s_axis_tx_tvalid), // input wire s_axis_tx_tvalid
+ .s_axis_tx_tuser(s_axis_tx_tuser), // input wire [3 : 0] s_axis_tx_tuser
+ .tx_cfg_gnt(tx_cfg_gnt), // input wire tx_cfg_gnt
+ .m_axis_rx_tdata(m_axis_rx_tdata), // output wire [63 : 0] m_axis_rx_tdata
+ .m_axis_rx_tkeep(m_axis_rx_tkeep), // output wire [7 : 0] m_axis_rx_tkeep
+ .m_axis_rx_tlast(m_axis_rx_tlast), // output wire m_axis_rx_tlast
+ .m_axis_rx_tvalid(m_axis_rx_tvalid), // output wire m_axis_rx_tvalid
+ .m_axis_rx_tready(m_axis_rx_tready), // input wire m_axis_rx_tready
+ .m_axis_rx_tuser(m_axis_rx_tuser), // output wire [21 : 0] m_axis_rx_tuser
+ .rx_np_ok(rx_np_ok), // input wire rx_np_ok
+ .rx_np_req(rx_np_req), // input wire rx_np_req
+ .fc_cpld(fc_cpld), // output wire [11 : 0] fc_cpld
+ .fc_cplh(fc_cplh), // output wire [7 : 0] fc_cplh
+ .fc_npd(fc_npd), // output wire [11 : 0] fc_npd
+ .fc_nph(fc_nph), // output wire [7 : 0] fc_nph
+ .fc_pd(fc_pd), // output wire [11 : 0] fc_pd
+ .fc_ph(fc_ph), // output wire [7 : 0] fc_ph
+ .fc_sel(fc_sel), // input wire [2 : 0] fc_sel
+ .cfg_mgmt_do(cfg_mgmt_do), // output wire [31 : 0] cfg_mgmt_do
+ .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done), // output wire cfg_mgmt_rd_wr_done
+ .cfg_status(cfg_status), // output wire [15 : 0] cfg_status
+ .cfg_command(cfg_command), // output wire [15 : 0] cfg_command
+ .cfg_dstatus(cfg_dstatus), // output wire [15 : 0] cfg_dstatus
+ .cfg_dcommand(cfg_dcommand), // output wire [15 : 0] cfg_dcommand
+ .cfg_lstatus(cfg_lstatus), // output wire [15 : 0] cfg_lstatus
+ .cfg_lcommand(cfg_lcommand), // output wire [15 : 0] cfg_lcommand
+ .cfg_dcommand2(cfg_dcommand2), // output wire [15 : 0] cfg_dcommand2
+ .cfg_pcie_link_state(cfg_pcie_link_state), // output wire [2 : 0] cfg_pcie_link_state
+ .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en), // output wire cfg_pmcsr_pme_en
+ .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate), // output wire [1 : 0] cfg_pmcsr_powerstate
+ .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status), // output wire cfg_pmcsr_pme_status
+ .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst), // output wire cfg_received_func_lvl_rst
+ .cfg_mgmt_di(cfg_mgmt_di), // input wire [31 : 0] cfg_mgmt_di
+ .cfg_mgmt_byte_en(cfg_mgmt_byte_en), // input wire [3 : 0] cfg_mgmt_byte_en
+ .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr), // input wire [9 : 0] cfg_mgmt_dwaddr
+ .cfg_mgmt_wr_en(cfg_mgmt_wr_en), // input wire cfg_mgmt_wr_en
+ .cfg_mgmt_rd_en(cfg_mgmt_rd_en), // input wire cfg_mgmt_rd_en
+ .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly), // input wire cfg_mgmt_wr_readonly
+ .cfg_err_ecrc(cfg_err_ecrc), // input wire cfg_err_ecrc
+ .cfg_err_ur(cfg_err_ur), // input wire cfg_err_ur
+ .cfg_err_cpl_timeout(cfg_err_cpl_timeout), // input wire cfg_err_cpl_timeout
+ .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect), // input wire cfg_err_cpl_unexpect
+ .cfg_err_cpl_abort(cfg_err_cpl_abort), // input wire cfg_err_cpl_abort
+ .cfg_err_posted(cfg_err_posted), // input wire cfg_err_posted
+ .cfg_err_cor(cfg_err_cor), // input wire cfg_err_cor
+ .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked), // input wire cfg_err_atomic_egress_blocked
+ .cfg_err_internal_cor(cfg_err_internal_cor), // input wire cfg_err_internal_cor
+ .cfg_err_malformed(cfg_err_malformed), // input wire cfg_err_malformed
+ .cfg_err_mc_blocked(cfg_err_mc_blocked), // input wire cfg_err_mc_blocked
+ .cfg_err_poisoned(cfg_err_poisoned), // input wire cfg_err_poisoned
+ .cfg_err_norecovery(cfg_err_norecovery), // input wire cfg_err_norecovery
+ .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header), // input wire [47 : 0] cfg_err_tlp_cpl_header
+ .cfg_err_cpl_rdy(cfg_err_cpl_rdy), // output wire cfg_err_cpl_rdy
+ .cfg_err_locked(cfg_err_locked), // input wire cfg_err_locked
+ .cfg_err_acs(cfg_err_acs), // input wire cfg_err_acs
+ .cfg_err_internal_uncor(cfg_err_internal_uncor), // input wire cfg_err_internal_uncor
+ .cfg_trn_pending(cfg_trn_pending), // input wire cfg_trn_pending
+ .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s), // input wire cfg_pm_halt_aspm_l0s
+ .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1), // input wire cfg_pm_halt_aspm_l1
+ .cfg_pm_force_state_en(cfg_pm_force_state_en), // input wire cfg_pm_force_state_en
+ .cfg_pm_force_state(cfg_pm_force_state), // input wire [1 : 0] cfg_pm_force_state
+ .cfg_dsn(cfg_dsn), // input wire [63 : 0] cfg_dsn
+ .cfg_interrupt(cfg_interrupt), // input wire cfg_interrupt
+ .cfg_interrupt_rdy(cfg_interrupt_rdy), // output wire cfg_interrupt_rdy
+ .cfg_interrupt_assert(cfg_interrupt_assert), // input wire cfg_interrupt_assert
+ .cfg_interrupt_di(cfg_interrupt_di), // input wire [7 : 0] cfg_interrupt_di
+ .cfg_interrupt_do(cfg_interrupt_do), // output wire [7 : 0] cfg_interrupt_do
+ .cfg_interrupt_mmenable(cfg_interrupt_mmenable), // output wire [2 : 0] cfg_interrupt_mmenable
+ .cfg_interrupt_msienable(cfg_interrupt_msienable), // output wire cfg_interrupt_msienable
+ .cfg_interrupt_msixenable(cfg_interrupt_msixenable), // output wire cfg_interrupt_msixenable
+ .cfg_interrupt_msixfm(cfg_interrupt_msixfm), // output wire cfg_interrupt_msixfm
+ .cfg_interrupt_stat(cfg_interrupt_stat), // input wire cfg_interrupt_stat
+ .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum), // input wire [4 : 0] cfg_pciecap_interrupt_msgnum
+ .cfg_to_turnoff(cfg_to_turnoff), // output wire cfg_to_turnoff
+ .cfg_turnoff_ok(cfg_turnoff_ok), // input wire cfg_turnoff_ok
+ .cfg_bus_number(cfg_bus_number), // output wire [7 : 0] cfg_bus_number
+ .cfg_device_number(cfg_device_number), // output wire [4 : 0] cfg_device_number
+ .cfg_function_number(cfg_function_number), // output wire [2 : 0] cfg_function_number
+ .cfg_pm_wake(cfg_pm_wake), // input wire cfg_pm_wake
+ .cfg_pm_send_pme_to(cfg_pm_send_pme_to), // input wire cfg_pm_send_pme_to
+ .cfg_ds_bus_number(cfg_ds_bus_number), // input wire [7 : 0] cfg_ds_bus_number
+ .cfg_ds_device_number(cfg_ds_device_number), // input wire [4 : 0] cfg_ds_device_number
+ .cfg_ds_function_number(cfg_ds_function_number), // input wire [2 : 0] cfg_ds_function_number
+ .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw), // input wire cfg_mgmt_wr_rw1c_as_rw
+ .cfg_msg_received(cfg_msg_received), // output wire cfg_msg_received
+ .cfg_msg_data(cfg_msg_data), // output wire [15 : 0] cfg_msg_data
+ .cfg_bridge_serr_en(cfg_bridge_serr_en), // output wire cfg_bridge_serr_en
+ .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse), // output wire cfg_slot_control_electromech_il_ctl_pulse
+ .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en), // output wire cfg_root_control_syserr_corr_err_en
+ .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en), // output wire cfg_root_control_syserr_non_fatal_err_en
+ .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en), // output wire cfg_root_control_syserr_fatal_err_en
+ .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en), // output wire cfg_root_control_pme_int_en
+ .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en), // output wire cfg_aer_rooterr_corr_err_reporting_en
+ .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en), // output wire cfg_aer_rooterr_non_fatal_err_reporting_en
+ .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en), // output wire cfg_aer_rooterr_fatal_err_reporting_en
+ .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received), // output wire cfg_aer_rooterr_corr_err_received
+ .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received), // output wire cfg_aer_rooterr_non_fatal_err_received
+ .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received), // output wire cfg_aer_rooterr_fatal_err_received
+ .cfg_msg_received_err_cor(cfg_msg_received_err_cor), // output wire cfg_msg_received_err_cor
+ .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal), // output wire cfg_msg_received_err_non_fatal
+ .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal), // output wire cfg_msg_received_err_fatal
+ .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak), // output wire cfg_msg_received_pm_as_nak
+ .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme), // output wire cfg_msg_received_pm_pme
+ .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack), // output wire cfg_msg_received_pme_to_ack
+ .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a), // output wire cfg_msg_received_assert_int_a
+ .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b), // output wire cfg_msg_received_assert_int_b
+ .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c), // output wire cfg_msg_received_assert_int_c
+ .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d), // output wire cfg_msg_received_assert_int_d
+ .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a), // output wire cfg_msg_received_deassert_int_a
+ .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b), // output wire cfg_msg_received_deassert_int_b
+ .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c), // output wire cfg_msg_received_deassert_int_c
+ .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d), // output wire cfg_msg_received_deassert_int_d
+ .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit), // output wire cfg_msg_received_setslotpowerlimit
+ .pl_directed_link_change(pl_directed_link_change), // input wire [1 : 0] pl_directed_link_change
+ .pl_directed_link_width(pl_directed_link_width), // input wire [1 : 0] pl_directed_link_width
+ .pl_directed_link_speed(pl_directed_link_speed), // input wire pl_directed_link_speed
+ .pl_directed_link_auton(pl_directed_link_auton), // input wire pl_directed_link_auton
+ .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph), // input wire pl_upstream_prefer_deemph
+ .pl_sel_lnk_rate(pl_sel_lnk_rate), // output wire pl_sel_lnk_rate
+ .pl_sel_lnk_width(pl_sel_lnk_width), // output wire [1 : 0] pl_sel_lnk_width
+ .pl_ltssm_state(pl_ltssm_state), // output wire [5 : 0] pl_ltssm_state
+ .pl_lane_reversal_mode(pl_lane_reversal_mode), // output wire [1 : 0] pl_lane_reversal_mode
+ .pl_phy_lnk_up(pl_phy_lnk_up), // output wire pl_phy_lnk_up
+ .pl_tx_pm_state(pl_tx_pm_state), // output wire [2 : 0] pl_tx_pm_state
+ .pl_rx_pm_state(pl_rx_pm_state), // output wire [1 : 0] pl_rx_pm_state
+ .pl_link_upcfg_cap(pl_link_upcfg_cap), // output wire pl_link_upcfg_cap
+ .pl_link_gen2_cap(pl_link_gen2_cap), // output wire pl_link_gen2_cap
+ .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported), // output wire pl_link_partner_gen2_supported
+ .pl_initial_link_width(pl_initial_link_width), // output wire [2 : 0] pl_initial_link_width
+ .pl_directed_change_done(pl_directed_change_done), // output wire pl_directed_change_done
+ .pl_received_hot_rst(pl_received_hot_rst), // output wire pl_received_hot_rst
+ .pl_transmit_hot_rst(pl_transmit_hot_rst), // input wire pl_transmit_hot_rst
+ .pl_downstream_deemph_source(pl_downstream_deemph_source), // input wire pl_downstream_deemph_source
+ .cfg_err_aer_headerlog(cfg_err_aer_headerlog), // input wire [127 : 0] cfg_err_aer_headerlog
+ .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum), // input wire [4 : 0] cfg_aer_interrupt_msgnum
+ .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set), // output wire cfg_err_aer_headerlog_set
+ .cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en), // output wire cfg_aer_ecrc_check_en
+ .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en), // output wire cfg_aer_ecrc_gen_en
+ .cfg_vc_tcvc_map(cfg_vc_tcvc_map), // output wire [6 : 0] cfg_vc_tcvc_map
+ .sys_clk(sys_clk), // input wire sys_clk
+ .sys_rst_n(sys_rst_n), // input wire sys_rst_n
+ .pipe_mmcm_rst_n(pipe_mmcm_rst_n), // input wire pipe_mmcm_rst_n
+ .pcie_drp_clk(pcie_drp_clk), // input wire pcie_drp_clk
+ .pcie_drp_en(pcie_drp_en), // input wire pcie_drp_en
+ .pcie_drp_we(pcie_drp_we), // input wire pcie_drp_we
+ .pcie_drp_addr(pcie_drp_addr), // input wire [8 : 0] pcie_drp_addr
+ .pcie_drp_di(pcie_drp_di), // input wire [15 : 0] pcie_drp_di
+ .pcie_drp_do(pcie_drp_do), // output wire [15 : 0] pcie_drp_do
+ .pcie_drp_rdy(pcie_drp_rdy) // output wire pcie_drp_rdy
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file pcie_7x_0.v when simulating
+// the core, pcie_7x_0. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.vho b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.vho
new file mode 100644
index 0000000..0236294
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.vho
@@ -0,0 +1,425 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:pcie_7x:3.3
+-- IP Revision: 14
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT pcie_7x_0
+ PORT (
+ pci_exp_txp : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ pci_exp_txn : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ pci_exp_rxp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ pci_exp_rxn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ pipe_pclk_in : IN STD_LOGIC;
+ pipe_rxusrclk_in : IN STD_LOGIC;
+ pipe_rxoutclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ pipe_dclk_in : IN STD_LOGIC;
+ pipe_userclk1_in : IN STD_LOGIC;
+ pipe_userclk2_in : IN STD_LOGIC;
+ pipe_oobclk_in : IN STD_LOGIC;
+ pipe_mmcm_lock_in : IN STD_LOGIC;
+ pipe_txoutclk_out : OUT STD_LOGIC;
+ pipe_rxoutclk_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ pipe_pclk_sel_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ pipe_gen3_out : OUT STD_LOGIC;
+ user_clk_out : OUT STD_LOGIC;
+ user_reset_out : OUT STD_LOGIC;
+ user_lnk_up : OUT STD_LOGIC;
+ user_app_rdy : OUT STD_LOGIC;
+ tx_buf_av : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+ tx_cfg_req : OUT STD_LOGIC;
+ tx_err_drop : OUT STD_LOGIC;
+ s_axis_tx_tready : OUT STD_LOGIC;
+ s_axis_tx_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+ s_axis_tx_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ s_axis_tx_tlast : IN STD_LOGIC;
+ s_axis_tx_tvalid : IN STD_LOGIC;
+ s_axis_tx_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ tx_cfg_gnt : IN STD_LOGIC;
+ m_axis_rx_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
+ m_axis_rx_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ m_axis_rx_tlast : OUT STD_LOGIC;
+ m_axis_rx_tvalid : OUT STD_LOGIC;
+ m_axis_rx_tready : IN STD_LOGIC;
+ m_axis_rx_tuser : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
+ rx_np_ok : IN STD_LOGIC;
+ rx_np_req : IN STD_LOGIC;
+ fc_cpld : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+ fc_cplh : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ fc_npd : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+ fc_nph : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ fc_pd : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+ fc_ph : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ fc_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ cfg_mgmt_do : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ cfg_mgmt_rd_wr_done : OUT STD_LOGIC;
+ cfg_status : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ cfg_command : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ cfg_dstatus : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ cfg_dcommand : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ cfg_lstatus : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ cfg_lcommand : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ cfg_dcommand2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ cfg_pcie_link_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+ cfg_pmcsr_pme_en : OUT STD_LOGIC;
+ cfg_pmcsr_powerstate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ cfg_pmcsr_pme_status : OUT STD_LOGIC;
+ cfg_received_func_lvl_rst : OUT STD_LOGIC;
+ cfg_mgmt_di : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ cfg_mgmt_byte_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ cfg_mgmt_dwaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+ cfg_mgmt_wr_en : IN STD_LOGIC;
+ cfg_mgmt_rd_en : IN STD_LOGIC;
+ cfg_mgmt_wr_readonly : IN STD_LOGIC;
+ cfg_err_ecrc : IN STD_LOGIC;
+ cfg_err_ur : IN STD_LOGIC;
+ cfg_err_cpl_timeout : IN STD_LOGIC;
+ cfg_err_cpl_unexpect : IN STD_LOGIC;
+ cfg_err_cpl_abort : IN STD_LOGIC;
+ cfg_err_posted : IN STD_LOGIC;
+ cfg_err_cor : IN STD_LOGIC;
+ cfg_err_atomic_egress_blocked : IN STD_LOGIC;
+ cfg_err_internal_cor : IN STD_LOGIC;
+ cfg_err_malformed : IN STD_LOGIC;
+ cfg_err_mc_blocked : IN STD_LOGIC;
+ cfg_err_poisoned : IN STD_LOGIC;
+ cfg_err_norecovery : IN STD_LOGIC;
+ cfg_err_tlp_cpl_header : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+ cfg_err_cpl_rdy : OUT STD_LOGIC;
+ cfg_err_locked : IN STD_LOGIC;
+ cfg_err_acs : IN STD_LOGIC;
+ cfg_err_internal_uncor : IN STD_LOGIC;
+ cfg_trn_pending : IN STD_LOGIC;
+ cfg_pm_halt_aspm_l0s : IN STD_LOGIC;
+ cfg_pm_halt_aspm_l1 : IN STD_LOGIC;
+ cfg_pm_force_state_en : IN STD_LOGIC;
+ cfg_pm_force_state : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ cfg_dsn : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+ cfg_interrupt : IN STD_LOGIC;
+ cfg_interrupt_rdy : OUT STD_LOGIC;
+ cfg_interrupt_assert : IN STD_LOGIC;
+ cfg_interrupt_di : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ cfg_interrupt_do : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ cfg_interrupt_mmenable : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+ cfg_interrupt_msienable : OUT STD_LOGIC;
+ cfg_interrupt_msixenable : OUT STD_LOGIC;
+ cfg_interrupt_msixfm : OUT STD_LOGIC;
+ cfg_interrupt_stat : IN STD_LOGIC;
+ cfg_pciecap_interrupt_msgnum : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+ cfg_to_turnoff : OUT STD_LOGIC;
+ cfg_turnoff_ok : IN STD_LOGIC;
+ cfg_bus_number : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ cfg_device_number : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+ cfg_function_number : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+ cfg_pm_wake : IN STD_LOGIC;
+ cfg_pm_send_pme_to : IN STD_LOGIC;
+ cfg_ds_bus_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ cfg_ds_device_number : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+ cfg_ds_function_number : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ cfg_mgmt_wr_rw1c_as_rw : IN STD_LOGIC;
+ cfg_msg_received : OUT STD_LOGIC;
+ cfg_msg_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ cfg_bridge_serr_en : OUT STD_LOGIC;
+ cfg_slot_control_electromech_il_ctl_pulse : OUT STD_LOGIC;
+ cfg_root_control_syserr_corr_err_en : OUT STD_LOGIC;
+ cfg_root_control_syserr_non_fatal_err_en : OUT STD_LOGIC;
+ cfg_root_control_syserr_fatal_err_en : OUT STD_LOGIC;
+ cfg_root_control_pme_int_en : OUT STD_LOGIC;
+ cfg_aer_rooterr_corr_err_reporting_en : OUT STD_LOGIC;
+ cfg_aer_rooterr_non_fatal_err_reporting_en : OUT STD_LOGIC;
+ cfg_aer_rooterr_fatal_err_reporting_en : OUT STD_LOGIC;
+ cfg_aer_rooterr_corr_err_received : OUT STD_LOGIC;
+ cfg_aer_rooterr_non_fatal_err_received : OUT STD_LOGIC;
+ cfg_aer_rooterr_fatal_err_received : OUT STD_LOGIC;
+ cfg_msg_received_err_cor : OUT STD_LOGIC;
+ cfg_msg_received_err_non_fatal : OUT STD_LOGIC;
+ cfg_msg_received_err_fatal : OUT STD_LOGIC;
+ cfg_msg_received_pm_as_nak : OUT STD_LOGIC;
+ cfg_msg_received_pm_pme : OUT STD_LOGIC;
+ cfg_msg_received_pme_to_ack : OUT STD_LOGIC;
+ cfg_msg_received_assert_int_a : OUT STD_LOGIC;
+ cfg_msg_received_assert_int_b : OUT STD_LOGIC;
+ cfg_msg_received_assert_int_c : OUT STD_LOGIC;
+ cfg_msg_received_assert_int_d : OUT STD_LOGIC;
+ cfg_msg_received_deassert_int_a : OUT STD_LOGIC;
+ cfg_msg_received_deassert_int_b : OUT STD_LOGIC;
+ cfg_msg_received_deassert_int_c : OUT STD_LOGIC;
+ cfg_msg_received_deassert_int_d : OUT STD_LOGIC;
+ cfg_msg_received_setslotpowerlimit : OUT STD_LOGIC;
+ pl_directed_link_change : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ pl_directed_link_width : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ pl_directed_link_speed : IN STD_LOGIC;
+ pl_directed_link_auton : IN STD_LOGIC;
+ pl_upstream_prefer_deemph : IN STD_LOGIC;
+ pl_sel_lnk_rate : OUT STD_LOGIC;
+ pl_sel_lnk_width : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ pl_ltssm_state : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+ pl_lane_reversal_mode : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ pl_phy_lnk_up : OUT STD_LOGIC;
+ pl_tx_pm_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+ pl_rx_pm_state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ pl_link_upcfg_cap : OUT STD_LOGIC;
+ pl_link_gen2_cap : OUT STD_LOGIC;
+ pl_link_partner_gen2_supported : OUT STD_LOGIC;
+ pl_initial_link_width : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+ pl_directed_change_done : OUT STD_LOGIC;
+ pl_received_hot_rst : OUT STD_LOGIC;
+ pl_transmit_hot_rst : IN STD_LOGIC;
+ pl_downstream_deemph_source : IN STD_LOGIC;
+ cfg_err_aer_headerlog : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+ cfg_aer_interrupt_msgnum : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+ cfg_err_aer_headerlog_set : OUT STD_LOGIC;
+ cfg_aer_ecrc_check_en : OUT STD_LOGIC;
+ cfg_aer_ecrc_gen_en : OUT STD_LOGIC;
+ cfg_vc_tcvc_map : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
+ sys_clk : IN STD_LOGIC;
+ sys_rst_n : IN STD_LOGIC;
+ pipe_mmcm_rst_n : IN STD_LOGIC;
+ pcie_drp_clk : IN STD_LOGIC;
+ pcie_drp_en : IN STD_LOGIC;
+ pcie_drp_we : IN STD_LOGIC;
+ pcie_drp_addr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+ pcie_drp_di : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+ pcie_drp_do : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ pcie_drp_rdy : OUT STD_LOGIC
+ );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : pcie_7x_0
+ PORT MAP (
+ pci_exp_txp => pci_exp_txp,
+ pci_exp_txn => pci_exp_txn,
+ pci_exp_rxp => pci_exp_rxp,
+ pci_exp_rxn => pci_exp_rxn,
+ pipe_pclk_in => pipe_pclk_in,
+ pipe_rxusrclk_in => pipe_rxusrclk_in,
+ pipe_rxoutclk_in => pipe_rxoutclk_in,
+ pipe_dclk_in => pipe_dclk_in,
+ pipe_userclk1_in => pipe_userclk1_in,
+ pipe_userclk2_in => pipe_userclk2_in,
+ pipe_oobclk_in => pipe_oobclk_in,
+ pipe_mmcm_lock_in => pipe_mmcm_lock_in,
+ pipe_txoutclk_out => pipe_txoutclk_out,
+ pipe_rxoutclk_out => pipe_rxoutclk_out,
+ pipe_pclk_sel_out => pipe_pclk_sel_out,
+ pipe_gen3_out => pipe_gen3_out,
+ user_clk_out => user_clk_out,
+ user_reset_out => user_reset_out,
+ user_lnk_up => user_lnk_up,
+ user_app_rdy => user_app_rdy,
+ tx_buf_av => tx_buf_av,
+ tx_cfg_req => tx_cfg_req,
+ tx_err_drop => tx_err_drop,
+ s_axis_tx_tready => s_axis_tx_tready,
+ s_axis_tx_tdata => s_axis_tx_tdata,
+ s_axis_tx_tkeep => s_axis_tx_tkeep,
+ s_axis_tx_tlast => s_axis_tx_tlast,
+ s_axis_tx_tvalid => s_axis_tx_tvalid,
+ s_axis_tx_tuser => s_axis_tx_tuser,
+ tx_cfg_gnt => tx_cfg_gnt,
+ m_axis_rx_tdata => m_axis_rx_tdata,
+ m_axis_rx_tkeep => m_axis_rx_tkeep,
+ m_axis_rx_tlast => m_axis_rx_tlast,
+ m_axis_rx_tvalid => m_axis_rx_tvalid,
+ m_axis_rx_tready => m_axis_rx_tready,
+ m_axis_rx_tuser => m_axis_rx_tuser,
+ rx_np_ok => rx_np_ok,
+ rx_np_req => rx_np_req,
+ fc_cpld => fc_cpld,
+ fc_cplh => fc_cplh,
+ fc_npd => fc_npd,
+ fc_nph => fc_nph,
+ fc_pd => fc_pd,
+ fc_ph => fc_ph,
+ fc_sel => fc_sel,
+ cfg_mgmt_do => cfg_mgmt_do,
+ cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done,
+ cfg_status => cfg_status,
+ cfg_command => cfg_command,
+ cfg_dstatus => cfg_dstatus,
+ cfg_dcommand => cfg_dcommand,
+ cfg_lstatus => cfg_lstatus,
+ cfg_lcommand => cfg_lcommand,
+ cfg_dcommand2 => cfg_dcommand2,
+ cfg_pcie_link_state => cfg_pcie_link_state,
+ cfg_pmcsr_pme_en => cfg_pmcsr_pme_en,
+ cfg_pmcsr_powerstate => cfg_pmcsr_powerstate,
+ cfg_pmcsr_pme_status => cfg_pmcsr_pme_status,
+ cfg_received_func_lvl_rst => cfg_received_func_lvl_rst,
+ cfg_mgmt_di => cfg_mgmt_di,
+ cfg_mgmt_byte_en => cfg_mgmt_byte_en,
+ cfg_mgmt_dwaddr => cfg_mgmt_dwaddr,
+ cfg_mgmt_wr_en => cfg_mgmt_wr_en,
+ cfg_mgmt_rd_en => cfg_mgmt_rd_en,
+ cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly,
+ cfg_err_ecrc => cfg_err_ecrc,
+ cfg_err_ur => cfg_err_ur,
+ cfg_err_cpl_timeout => cfg_err_cpl_timeout,
+ cfg_err_cpl_unexpect => cfg_err_cpl_unexpect,
+ cfg_err_cpl_abort => cfg_err_cpl_abort,
+ cfg_err_posted => cfg_err_posted,
+ cfg_err_cor => cfg_err_cor,
+ cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked,
+ cfg_err_internal_cor => cfg_err_internal_cor,
+ cfg_err_malformed => cfg_err_malformed,
+ cfg_err_mc_blocked => cfg_err_mc_blocked,
+ cfg_err_poisoned => cfg_err_poisoned,
+ cfg_err_norecovery => cfg_err_norecovery,
+ cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header,
+ cfg_err_cpl_rdy => cfg_err_cpl_rdy,
+ cfg_err_locked => cfg_err_locked,
+ cfg_err_acs => cfg_err_acs,
+ cfg_err_internal_uncor => cfg_err_internal_uncor,
+ cfg_trn_pending => cfg_trn_pending,
+ cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s,
+ cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1,
+ cfg_pm_force_state_en => cfg_pm_force_state_en,
+ cfg_pm_force_state => cfg_pm_force_state,
+ cfg_dsn => cfg_dsn,
+ cfg_interrupt => cfg_interrupt,
+ cfg_interrupt_rdy => cfg_interrupt_rdy,
+ cfg_interrupt_assert => cfg_interrupt_assert,
+ cfg_interrupt_di => cfg_interrupt_di,
+ cfg_interrupt_do => cfg_interrupt_do,
+ cfg_interrupt_mmenable => cfg_interrupt_mmenable,
+ cfg_interrupt_msienable => cfg_interrupt_msienable,
+ cfg_interrupt_msixenable => cfg_interrupt_msixenable,
+ cfg_interrupt_msixfm => cfg_interrupt_msixfm,
+ cfg_interrupt_stat => cfg_interrupt_stat,
+ cfg_pciecap_interrupt_msgnum => cfg_pciecap_interrupt_msgnum,
+ cfg_to_turnoff => cfg_to_turnoff,
+ cfg_turnoff_ok => cfg_turnoff_ok,
+ cfg_bus_number => cfg_bus_number,
+ cfg_device_number => cfg_device_number,
+ cfg_function_number => cfg_function_number,
+ cfg_pm_wake => cfg_pm_wake,
+ cfg_pm_send_pme_to => cfg_pm_send_pme_to,
+ cfg_ds_bus_number => cfg_ds_bus_number,
+ cfg_ds_device_number => cfg_ds_device_number,
+ cfg_ds_function_number => cfg_ds_function_number,
+ cfg_mgmt_wr_rw1c_as_rw => cfg_mgmt_wr_rw1c_as_rw,
+ cfg_msg_received => cfg_msg_received,
+ cfg_msg_data => cfg_msg_data,
+ cfg_bridge_serr_en => cfg_bridge_serr_en,
+ cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse,
+ cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en,
+ cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en,
+ cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en,
+ cfg_root_control_pme_int_en => cfg_root_control_pme_int_en,
+ cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en,
+ cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en,
+ cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en,
+ cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received,
+ cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received,
+ cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received,
+ cfg_msg_received_err_cor => cfg_msg_received_err_cor,
+ cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal,
+ cfg_msg_received_err_fatal => cfg_msg_received_err_fatal,
+ cfg_msg_received_pm_as_nak => cfg_msg_received_pm_as_nak,
+ cfg_msg_received_pm_pme => cfg_msg_received_pm_pme,
+ cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack,
+ cfg_msg_received_assert_int_a => cfg_msg_received_assert_int_a,
+ cfg_msg_received_assert_int_b => cfg_msg_received_assert_int_b,
+ cfg_msg_received_assert_int_c => cfg_msg_received_assert_int_c,
+ cfg_msg_received_assert_int_d => cfg_msg_received_assert_int_d,
+ cfg_msg_received_deassert_int_a => cfg_msg_received_deassert_int_a,
+ cfg_msg_received_deassert_int_b => cfg_msg_received_deassert_int_b,
+ cfg_msg_received_deassert_int_c => cfg_msg_received_deassert_int_c,
+ cfg_msg_received_deassert_int_d => cfg_msg_received_deassert_int_d,
+ cfg_msg_received_setslotpowerlimit => cfg_msg_received_setslotpowerlimit,
+ pl_directed_link_change => pl_directed_link_change,
+ pl_directed_link_width => pl_directed_link_width,
+ pl_directed_link_speed => pl_directed_link_speed,
+ pl_directed_link_auton => pl_directed_link_auton,
+ pl_upstream_prefer_deemph => pl_upstream_prefer_deemph,
+ pl_sel_lnk_rate => pl_sel_lnk_rate,
+ pl_sel_lnk_width => pl_sel_lnk_width,
+ pl_ltssm_state => pl_ltssm_state,
+ pl_lane_reversal_mode => pl_lane_reversal_mode,
+ pl_phy_lnk_up => pl_phy_lnk_up,
+ pl_tx_pm_state => pl_tx_pm_state,
+ pl_rx_pm_state => pl_rx_pm_state,
+ pl_link_upcfg_cap => pl_link_upcfg_cap,
+ pl_link_gen2_cap => pl_link_gen2_cap,
+ pl_link_partner_gen2_supported => pl_link_partner_gen2_supported,
+ pl_initial_link_width => pl_initial_link_width,
+ pl_directed_change_done => pl_directed_change_done,
+ pl_received_hot_rst => pl_received_hot_rst,
+ pl_transmit_hot_rst => pl_transmit_hot_rst,
+ pl_downstream_deemph_source => pl_downstream_deemph_source,
+ cfg_err_aer_headerlog => cfg_err_aer_headerlog,
+ cfg_aer_interrupt_msgnum => cfg_aer_interrupt_msgnum,
+ cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set,
+ cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en,
+ cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en,
+ cfg_vc_tcvc_map => cfg_vc_tcvc_map,
+ sys_clk => sys_clk,
+ sys_rst_n => sys_rst_n,
+ pipe_mmcm_rst_n => pipe_mmcm_rst_n,
+ pcie_drp_clk => pcie_drp_clk,
+ pcie_drp_en => pcie_drp_en,
+ pcie_drp_we => pcie_drp_we,
+ pcie_drp_addr => pcie_drp_addr,
+ pcie_drp_di => pcie_drp_di,
+ pcie_drp_do => pcie_drp_do,
+ pcie_drp_rdy => pcie_drp_rdy
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file pcie_7x_0.vhd when simulating
+-- the core, pcie_7x_0. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.xci b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.xci
new file mode 100644
index 0000000..c708fa2
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.xci
@@ -0,0 +1,631 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ pcie_7x_0
+
+
+
+
+
+ 100000000
+ 0
+ 0
+ 0.000
+
+ 0
+ 0
+ 0.000
+
+ 100000000
+ 1
+ 1
+ 1
+ 0
+ 0
+ undef
+ 0.000
+ 8
+ 0
+ 0
+ 22
+ 0
+ 0
+
+ 100000000
+ 1
+ 1
+ 1
+ 0
+ 0
+ undef
+ 0.000
+ 8
+ 0
+ 0
+ 4
+ TRUE
+ TRUE
+ TRUE
+ TRUE
+ 64
+ FALSE
+ TRUE
+ FALSE
+ FALSE
+ FALSE
+ 4
+ FALSE
+ TRUE
+ FALSE
+ FALSE
+ TRUE
+ TRUE
+ FALSE
+ FALSE
+ FALSE
+ FFFF0000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 0
+ 000
+ FALSE
+ FALSE
+ FALSE
+ 000
+ FALSE
+ 000000
+ FALSE
+ TRUE
+ pcie_7x_0
+ TRUE
+ TRUE
+ FALSE
+ 0010
+ 2
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ 00
+ FALSE
+ 0
+ TRUE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ 100
+ TRUE
+ 000
+ 00000000000
+ 0
+ 7
+ 3FF
+ 973
+ 36
+ 24
+ 12
+ 949
+ 32
+ true
+ 00
+ FALSE
+ 10C
+ FALSE
+ 0000
+ FALSE
+ 0
+ 0000
+ FALSE
+ 1
+ 0
+ TRUE
+ FALSE
+ 0
+ FALSE
+ FALSE
+ 00
+ 0
+ 0
+ 0
+ 0
+ 000
+ 3F
+ 0
+ 00
+ FALSE
+ TRUE
+ 0
+ TRUE
+ 0
+ 60
+ 0F
+ 000
+ 00
+ 00
+ 00
+ 00
+ 00
+ 00
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 000
+ FALSE
+ 00001
+ 00001
+ 00001
+ 00001
+ 00001
+ 00001
+ 0
+ 0
+ 0
+ FALSE
+ FALSE
+ 0
+ FFF
+ 2
+ 0
+ 2
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ FALSE
+ 0
+ FALSE
+ FALSE
+ 0
+ 0
+ 2
+ TRUE
+ 30
+ 0
+ 2
+ 0
+ TRUE
+ TRUE
+ FALSE
+ TRUE
+ TRUE
+ 000
+ FALSE
+ FALSE
+ 000
+ 000
+ FALSE
+ 000
+ ZC706
+ 2
+ 00000000
+ 050000
+ 3
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 7024
+ 0000
+ 0
+ 0
+ 0
+ 0
+ 0
+ 000
+ 111
+ FALSE
+ 1
+ TRUE
+ 2
+ 000100
+ 011
+ TRUE
+ 3
+ 0
+ 00
+ 0F
+ 00
+ 00
+ 00
+ 00
+ 00
+ 00
+ 00
+ 00
+ 00
+ TRUE
+ 0007
+ 10EE
+ 10EE
+ 00000000
+ Absolute
+ 0000
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ Maximum_of_64_ns
+ No_limit
+ false
+ 1M
+ 1M
+ 1M
+ 1M
+ 1M
+ 1M
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ false
+ true
+ false
+ Kilobytes
+ 64
+ Memory
+ false
+ false
+ false
+ Megabytes
+ 1
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ false
+ false
+ Kilobytes
+ 2
+ N/A
+ Memory_controller
+ false
+ false
+ 00000000
+ 05
+ 00
+ 00
+ pcie_7x_0
+ 1
+ false
+ false
+ Range_B
+ true
+ 0
+ 0
+ 0
+ 0
+ true
+ 0
+ 0
+ 0
+ 0
+ false
+ true
+ 0
+ 0
+ 0
+ 0
+ false
+ 0
+ 0
+ 0
+ 0
+ false
+ true
+ true
+ -3.5
+ 7024
+ PCI_Express_Endpoint_device
+ false
+ false
+ false
+ false
+ 00
+ false
+ 3FF
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ true
+ false
+ Kilobytes
+ 2
+ false
+ false
+ false
+ false
+ Disabled
+ true
+ 64_bit
+ INTA
+ 5.0_GT/s
+ true
+ false
+ false
+ false
+ BAR_0
+ 0
+ BAR_0
+ 0
+ 1
+ 1024_bytes
+ X4
+ 1_vector
+ true
+ 000000
+ false
+ 3F
+ X0Y0
+ false
+ true
+ None
+ High
+ No_function_number_bits_used
+ Disabled
+ false
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 64_byte
+ 0
+ false
+ Custom
+ true
+ 100_MHz
+ Add
+ 0000
+ 00
+ false
+ GES_and_Production
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ 0
+ false
+ false
+ 0
+ 0
+ RAM
+ 0007
+ 10EE
+ 00
+ None
+ 4'h2
+ false
+ true
+ true
+ false
+ true
+ false
+ 250
+ false
+ false
+ false
+ 10EE
+ ZC706
+ true
+ true
+ true
+ true
+ false
+ true
+ false
+ false
+ false
+ false
+ false
+ true
+ Basic
+ None
+ false
+ true
+ true
+ false
+ false
+ zynq
+ xilinx.com:zc706:part0:1.2
+
+ xc7z045
+ ffg900
+ VERILOG
+
+ MIXED
+ -2
+
+
+ TRUE
+ TRUE
+ IP_Flow
+ 14
+ TRUE
+ .
+
+ .
+ 2020.2
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.xml b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.xml
new file mode 100644
index 0000000..0e2f8e2
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.xml
@@ -0,0 +1,12604 @@
+
+
+ xilinx.com
+ customized_ip
+ pcie_7x_0
+ 1.0
+
+
+ m_axis_rx
+
+
+
+
+
+
+ TDATA
+
+
+ m_axis_rx_tdata
+
+
+
+
+ TKEEP
+
+
+ m_axis_rx_tkeep
+
+
+
+
+ TLAST
+
+
+ m_axis_rx_tlast
+
+
+
+
+ TREADY
+
+
+ m_axis_rx_tready
+
+
+
+
+ TUSER
+
+
+ m_axis_rx_tuser
+
+
+
+
+ TVALID
+
+
+ m_axis_rx_tvalid
+
+
+
+
+
+ TDATA_NUM_BYTES
+ 8
+
+
+ none
+
+
+
+
+ TDEST_WIDTH
+ 0
+
+
+ none
+
+
+
+
+ TID_WIDTH
+ 0
+
+
+ none
+
+
+
+
+ TUSER_WIDTH
+ 22
+
+
+ none
+
+
+
+
+ HAS_TREADY
+ 1
+
+
+ none
+
+
+
+
+ HAS_TSTRB
+ 0
+
+
+ none
+
+
+
+
+ HAS_TKEEP
+ 1
+
+
+ none
+
+
+
+
+ HAS_TLAST
+ 1
+
+
+ none
+
+
+
+
+ FREQ_HZ
+ 100000000
+
+
+ none
+
+
+
+
+ PHASE
+ 0.000
+
+
+ none
+
+
+
+
+ CLK_DOMAIN
+
+
+
+ none
+
+
+
+
+ LAYERED_METADATA
+ undef
+
+
+ none
+
+
+
+
+ INSERT_VIP
+ 0
+
+
+ simulation.rtl
+
+
+
+
+
+
+ s_axis_tx
+
+
+
+
+
+
+ TDATA
+
+
+ s_axis_tx_tdata
+
+
+
+
+ TKEEP
+
+
+ s_axis_tx_tkeep
+
+
+
+
+ TLAST
+
+
+ s_axis_tx_tlast
+
+
+
+
+ TREADY
+
+
+ s_axis_tx_tready
+
+
+
+
+ TUSER
+
+
+ s_axis_tx_tuser
+
+
+
+
+ TVALID
+
+
+ s_axis_tx_tvalid
+
+
+
+
+
+ TDATA_NUM_BYTES
+ 8
+
+
+ none
+
+
+
+
+ TDEST_WIDTH
+ 0
+
+
+ none
+
+
+
+
+ TID_WIDTH
+ 0
+
+
+ none
+
+
+
+
+ TUSER_WIDTH
+ 4
+
+
+ none
+
+
+
+
+ HAS_TREADY
+ 1
+
+
+ none
+
+
+
+
+ HAS_TSTRB
+ 0
+
+
+ none
+
+
+
+
+ HAS_TKEEP
+ 1
+
+
+ none
+
+
+
+
+ HAS_TLAST
+ 1
+
+
+ none
+
+
+
+
+ FREQ_HZ
+ 100000000
+
+
+ none
+
+
+
+
+ PHASE
+ 0.000
+
+
+ none
+
+
+
+
+ CLK_DOMAIN
+
+
+
+ none
+
+
+
+
+ LAYERED_METADATA
+ undef
+
+
+ none
+
+
+
+
+ INSERT_VIP
+ 0
+
+
+ simulation.rtl
+
+
+
+
+
+
+ icap
+ icap
+ ICAP Interface
+
+
+
+
+
+
+ clk
+
+
+ icap_clk
+
+
+
+
+ csib
+
+
+ icap_csib
+
+
+
+
+ i
+
+
+ icap_i
+
+
+
+
+ o
+
+
+ icap_o
+
+
+
+
+ rdwrb
+
+
+ icap_rdwrb
+
+
+
+
+
+
+ false
+
+
+
+
+
+ startup
+ startup
+ STARTUP Interface
+
+
+
+
+
+
+ cfgclk
+
+
+ startup_cfgclk
+
+
+
+
+ cfgmclk
+
+
+ startup_cfgmclk
+
+
+
+
+ clk
+
+
+ startup_clk
+
+
+
+
+ eos
+
+
+ startup_eos
+
+
+
+
+ gsr
+
+
+ startup_gsr
+
+
+
+
+ gts
+
+
+ startup_gts
+
+
+
+
+ keyclearb
+
+
+ startup_keyclearb
+
+
+
+
+ pack
+
+
+ startup_pack
+
+
+
+
+ preq
+
+
+ startup_preq
+
+
+
+
+ userdoneo
+
+
+ startup_usrdoneo
+
+
+
+
+ usrcclko
+
+
+ startup_usrcclko
+
+
+
+
+ usrclkts
+
+
+ startup_usrcclkts
+
+
+
+
+ usrdonets
+
+
+ startup_usrdonets
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pcie_7x_mgt
+ pcie_7x_mgt
+ PCI Express Serial Link
+
+
+
+
+
+
+ rxn
+
+
+ pci_exp_rxn
+
+
+
+
+ rxp
+
+
+ pci_exp_rxp
+
+
+
+
+ txn
+
+
+ pci_exp_txn
+
+
+
+
+ txp
+
+
+ pci_exp_txp
+
+
+
+
+
+ pipe_clock
+ pipe_clock
+ PCIe External Pipe Clock
+
+
+
+
+
+
+ dclk_in
+
+
+ pipe_dclk_in
+
+
+
+
+ gen3_out
+
+
+ pipe_gen3_out
+
+
+
+
+ mmcm_lock_in
+
+
+ pipe_mmcm_lock_in
+
+
+
+
+ mmcm_rst_n
+
+
+ pipe_mmcm_rst_n
+
+
+
+
+ oobclk_in
+
+
+ pipe_oobclk_in
+
+
+
+
+ pclk_in
+
+
+ pipe_pclk_in
+
+
+
+
+ pclk_sel_out
+
+
+ pipe_pclk_sel_out
+
+
+
+
+ rxoutclk_in
+
+
+ pipe_rxoutclk_in
+
+
+
+
+ rxoutclk_out
+
+
+ pipe_rxoutclk_out
+
+
+
+
+ rxusrclk_in
+
+
+ pipe_rxusrclk_in
+
+
+
+
+ txoutclk_out
+
+
+ pipe_txoutclk_out
+
+
+
+
+ userclk1_in
+
+
+ pipe_userclk1_in
+
+
+
+
+ userclk2_in
+
+
+ pipe_userclk2_in
+
+
+
+
+
+
+ true
+
+
+
+
+
+ drp
+ drp
+ DRP interface
+
+
+
+
+
+
+ DADDR
+
+
+ pcie_drp_addr
+
+
+
+
+ DEN
+
+
+ pcie_drp_en
+
+
+
+
+ DI
+
+
+ pcie_drp_di
+
+
+
+
+ DO
+
+
+ pcie_drp_do
+
+
+
+
+ DRDY
+
+
+ pcie_drp_rdy
+
+
+
+
+ DWE
+
+
+ pcie_drp_we
+
+
+
+
+
+
+ true
+
+
+
+
+
+ CLK.sys_clk
+ CLK.sys_clk
+ sys_clk interface
+
+
+
+
+
+
+ CLK
+
+
+ sys_clk
+
+
+
+
+
+ FREQ_HZ
+ 100000000
+
+
+ none
+
+
+
+
+ FREQ_TOLERANCE_HZ
+ 0
+
+
+ none
+
+
+
+
+ PHASE
+ 0.000
+
+
+ none
+
+
+
+
+ CLK_DOMAIN
+
+
+
+ none
+
+
+
+
+ ASSOCIATED_BUSIF
+
+
+
+ none
+
+
+
+
+ ASSOCIATED_RESET
+
+
+
+ none
+
+
+
+
+ INSERT_VIP
+ 0
+
+
+ simulation.rtl
+
+
+
+
+
+
+ CLK.user_clk_out
+ CLK.user_clk_out
+ user_clk_out interface
+
+
+
+
+
+
+ CLK
+
+
+ user_clk_out
+
+
+
+
+
+ ASSOCIATED_BUSIF
+ m_axis_rx:s_axis_tx
+
+
+ FREQ_HZ
+ 125000000
+
+
+ ASSOCIATED_RESET
+ user_reset_out
+
+
+ FREQ_TOLERANCE_HZ
+ 0
+
+
+ none
+
+
+
+
+ PHASE
+ 0.000
+
+
+ none
+
+
+
+
+ CLK_DOMAIN
+
+
+
+ none
+
+
+
+
+ INSERT_VIP
+ 0
+
+
+ simulation.rtl
+
+
+
+
+
+
+ RST.sys_rst_n
+ RST.sys_rst_n
+ sys_rst_n interface
+
+
+
+
+
+
+ RST
+
+
+ sys_rst_n
+
+
+
+
+
+ POLARITY
+ ACTIVE_LOW
+
+
+ INSERT_VIP
+ 0
+
+
+ simulation.rtl
+
+
+
+
+
+
+ RST.user_reset_out
+ RST.user_reset_out
+ user_reset_out Interface
+
+
+
+
+
+
+ RST
+
+
+ user_reset_out
+
+
+
+
+
+ POLARITY
+ ACTIVE_HIGH
+
+
+ INSERT_VIP
+ 0
+
+
+ simulation.rtl
+
+
+
+
+
+
+ pcie2_cfg_err
+ pcie2_cfg_err
+ pcie config error for gen2
+
+
+
+
+
+
+ acs
+
+
+ cfg_err_acs
+
+
+
+
+ aer_ecrc_check_en
+
+
+ cfg_aer_ecrc_check_en
+
+
+
+
+ aer_ecrc_gen_en
+
+
+ cfg_aer_ecrc_gen_en
+
+
+
+
+ aer_interrupt_msgnum
+
+
+ cfg_aer_interrupt_msgnum
+
+
+
+
+ atomic_egress_blocked
+
+
+ cfg_err_atomic_egress_blocked
+
+
+
+
+ cor
+
+
+ cfg_err_cor
+
+
+
+
+ cpl_abort
+
+
+ cfg_err_cpl_abort
+
+
+
+
+ cpl_rdy
+
+
+ cfg_err_cpl_rdy
+
+
+
+
+ cpl_timeout
+
+
+ cfg_err_cpl_timeout
+
+
+
+
+ cpl_unexpect
+
+
+ cfg_err_cpl_unexpect
+
+
+
+
+ ecrc
+
+
+ cfg_err_ecrc
+
+
+
+
+ err_aer_headerlog
+
+
+ cfg_err_aer_headerlog
+
+
+
+
+ err_aer_headerlog_set
+
+
+ cfg_err_aer_headerlog_set
+
+
+
+
+ internal_cor
+
+
+ cfg_err_internal_cor
+
+
+
+
+ internal_uncor
+
+
+ cfg_err_internal_uncor
+
+
+
+
+ locked
+
+
+ cfg_err_locked
+
+
+
+
+ malformed
+
+
+ cfg_err_malformed
+
+
+
+
+ mc_blocked
+
+
+ cfg_err_mc_blocked
+
+
+
+
+ norecovery
+
+
+ cfg_err_norecovery
+
+
+
+
+ poisoned
+
+
+ cfg_err_poisoned
+
+
+
+
+ posted
+
+
+ cfg_err_posted
+
+
+
+
+ tlp_cpl_header
+
+
+ cfg_err_tlp_cpl_header
+
+
+
+
+ ur
+
+
+ cfg_err_ur
+
+
+
+
+
+
+ true
+
+
+
+
+
+ pcie2_cfg_interrupt
+ pcie2_cfg_interrupt
+ pcie config interrupt for gen2
+
+
+
+
+
+
+ assert
+
+
+ cfg_interrupt_assert
+
+
+
+
+ interrupt
+
+
+ cfg_interrupt
+
+
+
+
+ mmenable
+
+
+ cfg_interrupt_mmenable
+
+
+
+
+ msienable
+
+
+ cfg_interrupt_msienable
+
+
+
+
+ msixenable
+
+
+ cfg_interrupt_msixenable
+
+
+
+
+ msixfm
+
+
+ cfg_interrupt_msixfm
+
+
+
+
+ pciecap_interrupt_msgnum
+
+
+ cfg_pciecap_interrupt_msgnum
+
+
+
+
+ rdy
+
+
+ cfg_interrupt_rdy
+
+
+
+
+ read_data
+
+
+ cfg_interrupt_do
+
+
+
+
+ stat
+
+
+ cfg_interrupt_stat
+
+
+
+
+ write_data
+
+
+ cfg_interrupt_di
+
+
+
+
+
+ pcie2_cfg_status
+ pcie2_cfg_status
+ pcie config status for gen2
+
+
+
+
+
+
+ aer_rooterr_corr_err_received
+
+
+ cfg_aer_rooterr_corr_err_received
+
+
+
+
+ aer_rooterr_corr_err_reporting_en
+
+
+ cfg_aer_rooterr_corr_err_reporting_en
+
+
+
+
+ aer_rooterr_fatal_err_received
+
+
+ cfg_aer_rooterr_fatal_err_received
+
+
+
+
+ aer_rooterr_fatal_err_reporting_en
+
+
+ cfg_aer_rooterr_fatal_err_reporting_en
+
+
+
+
+ aer_rooterr_non_fatal_err_received
+
+
+ cfg_aer_rooterr_non_fatal_err_received
+
+
+
+
+ aer_rooterr_non_fatal_err_reporting_en
+
+
+ cfg_aer_rooterr_non_fatal_err_reporting_en
+
+
+
+
+ bridge_serr_en
+
+
+ cfg_bridge_serr_en
+
+
+
+
+ bus_number
+
+
+ cfg_bus_number
+
+
+
+
+ command
+
+
+ cfg_command
+
+
+
+
+ dcommand
+
+
+ cfg_dcommand
+
+
+
+
+ dcommand2
+
+
+ cfg_dcommand2
+
+
+
+
+ device_number
+
+
+ cfg_device_number
+
+
+
+
+ dstatus
+
+
+ cfg_dstatus
+
+
+
+
+ function_number
+
+
+ cfg_function_number
+
+
+
+
+ lcommand
+
+
+ cfg_lcommand
+
+
+
+
+ lstatus
+
+
+ cfg_lstatus
+
+
+
+
+ pcie_link_state
+
+
+ cfg_pcie_link_state
+
+
+
+
+ pmcsr_pme_en
+
+
+ cfg_pmcsr_pme_en
+
+
+
+
+ pmcsr_pme_status
+
+
+ cfg_pmcsr_pme_status
+
+
+
+
+ pmcsr_powerstate
+
+
+ cfg_pmcsr_powerstate
+
+
+
+
+ received_func_lvl_rst
+
+
+ cfg_received_func_lvl_rst
+
+
+
+
+ root_control_pme_int_en
+
+
+ cfg_root_control_pme_int_en
+
+
+
+
+ root_control_syserr_corr_err_en
+
+
+ cfg_root_control_syserr_corr_err_en
+
+
+
+
+ root_control_syserr_fatal_err_en
+
+
+ cfg_root_control_syserr_fatal_err_en
+
+
+
+
+ root_control_syserr_non_fatal_err_en
+
+
+ cfg_root_control_syserr_non_fatal_err_en
+
+
+
+
+ slot_control_electromech_il_ctl_pulse
+
+
+ cfg_slot_control_electromech_il_ctl_pulse
+
+
+
+
+ status
+
+
+ cfg_status
+
+
+
+
+ turnoff
+
+
+ cfg_to_turnoff
+
+
+
+
+ tx_buf_av
+
+
+ tx_buf_av
+
+
+
+
+ tx_cfg_req
+
+
+ tx_cfg_req
+
+
+
+
+ tx_err_drop
+
+
+ tx_err_drop
+
+
+
+
+ vc_tcvc_map
+
+
+ cfg_vc_tcvc_map
+
+
+
+
+
+
+ true
+
+
+
+
+
+ pcie_cfg_fc
+ pcie_cfg_fc
+ pcie config flowcontrol
+
+
+
+
+
+
+ CPLD
+
+
+ fc_cpld
+
+
+
+
+ CPLH
+
+
+ fc_cplh
+
+
+
+
+ NPD
+
+
+ fc_npd
+
+
+
+
+ NPH
+
+
+ fc_nph
+
+
+
+
+ PD
+
+
+ fc_pd
+
+
+
+
+ PH
+
+
+ fc_ph
+
+
+
+
+ SEL
+
+
+ fc_sel
+
+
+
+
+
+
+ true
+
+
+
+
+
+ pcie2_cfg_control
+ pcie2_cfg_control
+ pcie config control for gen2
+
+
+
+
+
+
+ ds_bus_number
+
+
+ cfg_ds_bus_number
+
+
+
+
+ ds_device_number
+
+
+ cfg_ds_device_number
+
+
+
+
+ ds_function_number
+
+
+ cfg_ds_function_number
+
+
+
+
+ dsn
+
+
+ cfg_dsn
+
+
+
+
+ pm_force_state
+
+
+ cfg_pm_force_state
+
+
+
+
+ pm_force_state_en
+
+
+ cfg_pm_force_state_en
+
+
+
+
+ pm_halt_aspm_l0s
+
+
+ cfg_pm_halt_aspm_l0s
+
+
+
+
+ pm_halt_aspm_l1
+
+
+ cfg_pm_halt_aspm_l1
+
+
+
+
+ pm_send_pme_to
+
+
+ cfg_pm_send_pme_to
+
+
+
+
+ pm_wake
+
+
+ cfg_pm_wake
+
+
+
+
+ rx_np_ok
+
+
+ rx_np_ok
+
+
+
+
+ rx_np_req
+
+
+ rx_np_req
+
+
+
+
+ trn_pending
+
+
+ cfg_trn_pending
+
+
+
+
+ turnoff_ok
+
+
+ cfg_turnoff_ok
+
+
+
+
+ tx_cfg_gnt
+
+
+ tx_cfg_gnt
+
+
+
+
+
+
+ true
+
+
+
+
+
+ pcie2_cfg_msg_rcvd
+ pcie2_cfg_msg_rcvd
+ pcie config message received for gen2
+
+
+
+
+
+
+ assert_int_a
+
+
+ cfg_msg_received_assert_int_a
+
+
+
+
+ assert_int_b
+
+
+ cfg_msg_received_assert_int_b
+
+
+
+
+ assert_int_c
+
+
+ cfg_msg_received_assert_int_c
+
+
+
+
+ assert_int_d
+
+
+ cfg_msg_received_assert_int_d
+
+
+
+
+ data
+
+
+ cfg_msg_data
+
+
+
+
+ deassert_int_a
+
+
+ cfg_msg_received_deassert_int_a
+
+
+
+
+ deassert_int_b
+
+
+ cfg_msg_received_deassert_int_b
+
+
+
+
+ deassert_int_c
+
+
+ cfg_msg_received_deassert_int_c
+
+
+
+
+ deassert_int_d
+
+
+ cfg_msg_received_deassert_int_d
+
+
+
+
+ err_cor
+
+
+ cfg_msg_received_err_cor
+
+
+
+
+ err_fatal
+
+
+ cfg_msg_received_err_fatal
+
+
+
+
+ err_non_fatal
+
+
+ cfg_msg_received_err_non_fatal
+
+
+
+
+ pm_pme
+
+
+ cfg_msg_received_pm_pme
+
+
+
+
+ pme_to_ack
+
+
+ cfg_msg_received_pme_to_ack
+
+
+
+
+ received
+
+
+ cfg_msg_received
+
+
+
+
+ received_pm_as_nak
+
+
+ cfg_msg_received_pm_as_nak
+
+
+
+
+ received_setslotpowerlimit
+
+
+ cfg_msg_received_setslotpowerlimit
+
+
+
+
+
+
+ true
+
+
+
+
+
+ pcie_cfg_mgmt
+ pcie_cfg_mgmt
+ pcie config management for gen2
+
+
+
+
+
+
+ ADDR
+
+
+ cfg_mgmt_dwaddr
+
+
+
+
+ BYTE_EN
+
+
+ cfg_mgmt_byte_en
+
+
+
+
+ READ_DATA
+
+
+ cfg_mgmt_do
+
+
+
+
+ READ_EN
+
+
+ cfg_mgmt_rd_en
+
+
+
+
+ READ_WRITE_DONE
+
+
+ cfg_mgmt_rd_wr_done
+
+
+
+
+ READONLY
+
+
+ cfg_mgmt_wr_readonly
+
+
+
+
+ TYPE1_CFG_REG_ACCESS
+
+
+ cfg_mgmt_wr_rw1c_as_rw
+
+
+
+
+ WRITE_DATA
+
+
+ cfg_mgmt_di
+
+
+
+
+ WRITE_EN
+
+
+ cfg_mgmt_wr_en
+
+
+
+
+
+
+ true
+
+
+
+
+
+ pcie_qpll_drp
+ pcie_qpll_drp
+ pcie qpll drp for gen2
+
+
+
+
+
+
+ clk
+
+
+ qpll_drp_clk
+
+
+
+
+ crscode
+
+
+ qpll_drp_crscode
+
+
+
+
+ done
+
+
+ qpll_drp_done
+
+
+
+
+ fsm
+
+
+ qpll_drp_fsm
+
+
+
+
+ gen3
+
+
+ qpll_drp_gen3
+
+
+
+
+ ovrd
+
+
+ qpll_drp_ovrd
+
+
+
+
+ qplld
+
+
+ qpll_qplld
+
+
+
+
+ qplllock
+
+
+ qpll_qplllock
+
+
+
+
+ qplloutclk
+
+
+ qpll_qplloutclk
+
+
+
+
+ qplloutrefclk
+
+
+ qpll_qplloutrefclk
+
+
+
+
+ qpllreset
+
+
+ qpll_qpllreset
+
+
+
+
+ reset
+
+
+ qpll_drp_reset
+
+
+
+
+ rst_n
+
+
+ qpll_drp_rst_n
+
+
+
+
+ start
+
+
+ qpll_drp_start
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pcie_sharedlogic_int_clk
+ pcie_sharedlogic_int_clk
+ pcie sharedlogic internal clock for gen2
+
+
+
+
+
+
+ dclk
+
+
+ int_dclk_out
+
+
+
+
+ mmcm_lock
+
+
+ int_mmcm_lock_out
+
+
+
+
+ oobclk
+
+
+ int_oobclk_out
+
+
+
+
+ pclk_sel_slave
+
+
+ int_pclk_sel_slave
+
+
+
+
+ pclk_slave
+
+
+ int_pclk_out_slave
+
+
+
+
+ pipe_rxusrclk
+
+
+ int_pipe_rxusrclk_out
+
+
+
+
+ qplllock
+
+
+ int_qplllock_out
+
+
+
+
+ qplloutclk
+
+
+ int_qplloutclk_out
+
+
+
+
+ qplloutrefclk
+
+
+ int_qplloutrefclk_out
+
+
+
+
+ rxoutclk
+
+
+ int_rxoutclk_out
+
+
+
+
+ usrclk1
+
+
+ int_userclk1_out
+
+
+
+
+ usrclk2
+
+
+ int_userclk2_out
+
+
+
+
+
+
+ false
+
+
+
+
+
+ transceiver_debug
+ transceiver_debug
+ Transceiver Debug Interface
+
+
+
+
+
+
+ cpll_lock
+
+
+ pipe_cpll_lock
+
+
+
+
+ debug
+
+
+ pipe_debug
+
+
+
+
+ debug_0
+
+
+ pipe_debug_0
+
+
+
+
+ debug_1
+
+
+ pipe_debug_1
+
+
+
+
+ debug_2
+
+
+ pipe_debug_2
+
+
+
+
+ debug_3
+
+
+ pipe_debug_3
+
+
+
+
+ debug_4
+
+
+ pipe_debug_4
+
+
+
+
+ debug_5
+
+
+ pipe_debug_5
+
+
+
+
+ debug_6
+
+
+ pipe_debug_6
+
+
+
+
+ debug_7
+
+
+ pipe_debug_7
+
+
+
+
+ debug_8
+
+
+ pipe_debug_8
+
+
+
+
+ debug_9
+
+
+ pipe_debug_9
+
+
+
+
+ dmonitorout
+
+
+ pipe_dmonitorout
+
+
+
+
+ drp_fsm
+
+
+ pipe_drp_fsm
+
+
+
+
+ eyescandataerror
+
+
+ pipe_eyescandataerror
+
+
+
+
+ gt_ch_drp_rdy
+
+
+ gt_ch_drp_rdy
+
+
+
+
+ loopback
+
+
+ pipe_loopback
+
+
+
+
+ qpll_lock
+
+
+ pipe_qpll_lock
+
+
+
+
+ qrst_fsm
+
+
+ pipe_qrst_fsm
+
+
+
+
+ qrst_idle
+
+
+ pipe_qrst_idle
+
+
+
+
+ rate_fsm
+
+
+ pipe_rate_fsm
+
+
+
+
+ rate_idle
+
+
+ pipe_rate_idle
+
+
+
+
+ rst_fsm
+
+
+ pipe_rst_fsm
+
+
+
+
+ rst_idle
+
+
+ pipe_rst_idle
+
+
+
+
+ rxbufstatus
+
+
+ pipe_rxbufstatus
+
+
+
+
+ rxcommadet
+
+
+ pipe_rxcommadet
+
+
+
+
+ rxdisperr
+
+
+ pipe_rxdisperr
+
+
+
+
+ rxdlysresetdone
+
+
+ pipe_rxdlysresetdone
+
+
+
+
+ rxnotintable
+
+
+ pipe_rxnotintable
+
+
+
+
+ rxphaligndone
+
+
+ pipe_rxphaligndone
+
+
+
+
+ rxpmaresetdone
+
+
+ pipe_rxpmaresetdone
+
+
+
+
+ rxprbscntreset
+
+
+ pipe_rxprbscntreset
+
+
+
+
+ rxprbserr
+
+
+ pipe_rxprbserr
+
+
+
+
+ rxprbssel
+
+
+ pipe_rxprbssel
+
+
+
+
+ rxstatus
+
+
+ pipe_rxstatus
+
+
+
+
+ rxsyncdone
+
+
+ pipe_rxsyncdone
+
+
+
+
+ sync_fsm_rx
+
+
+ pipe_sync_fsm_rx
+
+
+
+
+ sync_fsm_tx
+
+
+ pipe_sync_fsm_tx
+
+
+
+
+ txdlysresetdone
+
+
+ pipe_txdlysresetdone
+
+
+
+
+ txinhibit
+
+
+ pipe_txinhibit
+
+
+
+
+ txphaligndone
+
+
+ pipe_txphaligndone
+
+
+
+
+ txphinitdone
+
+
+ pipe_txphinitdone
+
+
+
+
+ txprbsforceerr
+
+
+ pipe_txprbsforceerr
+
+
+
+
+ txprbssel
+
+
+ pipe_txprbssel
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pcie2_pl
+ pcie2_pl
+ pcie pl for gen2
+
+
+
+
+
+
+ directed_change_done
+
+
+ pl_directed_change_done
+
+
+
+
+ directed_link_auton
+
+
+ pl_directed_link_auton
+
+
+
+
+ directed_link_change
+
+
+ pl_directed_link_change
+
+
+
+
+ directed_link_speed
+
+
+ pl_directed_link_speed
+
+
+
+
+ directed_link_width
+
+
+ pl_directed_link_width
+
+
+
+
+ downstream_deemph_source
+
+
+ pl_downstream_deemph_source
+
+
+
+
+ initial_link_width
+
+
+ pl_initial_link_width
+
+
+
+
+ lane_reversal_mode
+
+
+ pl_lane_reversal_mode
+
+
+
+
+ link_gen2_cap
+
+
+ pl_link_gen2_cap
+
+
+
+
+ link_partner_gen2_supported
+
+
+ pl_link_partner_gen2_supported
+
+
+
+
+ link_upcfg_cap
+
+
+ pl_link_upcfg_cap
+
+
+
+
+ ltssm_state
+
+
+ pl_ltssm_state
+
+
+
+
+ phy_lnk_up
+
+
+ pl_phy_lnk_up
+
+
+
+
+ received_hot_rst
+
+
+ pl_received_hot_rst
+
+
+
+
+ rx_pm_state
+
+
+ pl_rx_pm_state
+
+
+
+
+ sel_lnk_rate
+
+
+ pl_sel_lnk_rate
+
+
+
+
+ sel_lnk_width
+
+
+ pl_sel_lnk_width
+
+
+
+
+ transmit_hot_rst
+
+
+ pl_transmit_hot_rst
+
+
+
+
+ tx_pm_state
+
+
+ pl_tx_pm_state
+
+
+
+
+ upstream_prefer_deemph
+
+
+ pl_upstream_prefer_deemph
+
+
+
+
+
+
+ true
+
+
+
+
+
+ pcie_ext_ch_gt
+ pcie_ext_ch_gt
+ pcie ext ch gt for gen2
+
+
+
+
+
+
+ DADDR
+
+
+ ext_ch_gt_drpaddr
+
+
+
+
+ DEN
+
+
+ ext_ch_gt_drpen
+
+
+
+
+ DI
+
+
+ ext_ch_gt_drpdi
+
+
+
+
+ DO
+
+
+ ext_ch_gt_drpdo
+
+
+
+
+ DRDY
+
+
+ ext_ch_gt_drprdy
+
+
+
+
+ DWE
+
+
+ ext_ch_gt_drpwe
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pcie2_ext_pipe_rp
+ pcie_ext_pipe_rp
+ External PIPE Interface
+
+
+
+
+
+
+ COMMANDS_IN
+
+
+ common_commands_in
+
+
+
+
+ COMMANDS_OUT
+
+
+ common_commands_out
+
+
+
+
+ RX_0
+
+
+ pipe_rx_0_sigs
+
+
+
+
+ RX_1
+
+
+ pipe_rx_1_sigs
+
+
+
+
+ RX_2
+
+
+ pipe_rx_2_sigs
+
+
+
+
+ RX_3
+
+
+ pipe_rx_3_sigs
+
+
+
+
+ RX_4
+
+
+ pipe_rx_4_sigs
+
+
+
+
+ RX_5
+
+
+ pipe_rx_5_sigs
+
+
+
+
+ RX_6
+
+
+ pipe_rx_6_sigs
+
+
+
+
+ RX_7
+
+
+ pipe_rx_7_sigs
+
+
+
+
+ TX_0
+
+
+ pipe_tx_0_sigs
+
+
+
+
+ TX_1
+
+
+ pipe_tx_1_sigs
+
+
+
+
+ TX_2
+
+
+ pipe_tx_2_sigs
+
+
+
+
+ TX_3
+
+
+ pipe_tx_3_sigs
+
+
+
+
+ TX_4
+
+
+ pipe_tx_4_sigs
+
+
+
+
+ TX_5
+
+
+ pipe_tx_5_sigs
+
+
+
+
+ TX_6
+
+
+ pipe_tx_6_sigs
+
+
+
+
+ TX_7
+
+
+ pipe_tx_7_sigs
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pcie2_ext_pipe_ep
+ pcie_ext_pipe_ep
+ External PIPE Interface
+
+
+
+
+
+
+ COMMANDS_IN
+
+
+ common_commands_out
+
+
+
+
+ COMMANDS_OUT
+
+
+ common_commands_in
+
+
+
+
+ RX_0
+
+
+ pipe_tx_0_sigs
+
+
+
+
+ RX_1
+
+
+ pipe_tx_1_sigs
+
+
+
+
+ RX_2
+
+
+ pipe_tx_2_sigs
+
+
+
+
+ RX_3
+
+
+ pipe_tx_3_sigs
+
+
+
+
+ RX_4
+
+
+ pipe_tx_4_sigs
+
+
+
+
+ RX_5
+
+
+ pipe_tx_5_sigs
+
+
+
+
+ RX_6
+
+
+ pipe_tx_6_sigs
+
+
+
+
+ RX_7
+
+
+ pipe_tx_7_sigs
+
+
+
+
+ TX_0
+
+
+ pipe_rx_0_sigs
+
+
+
+
+ TX_1
+
+
+ pipe_rx_1_sigs
+
+
+
+
+ TX_2
+
+
+ pipe_rx_2_sigs
+
+
+
+
+ TX_3
+
+
+ pipe_rx_3_sigs
+
+
+
+
+ TX_4
+
+
+ pipe_rx_4_sigs
+
+
+
+
+ TX_5
+
+
+ pipe_rx_5_sigs
+
+
+
+
+ TX_6
+
+
+ pipe_rx_6_sigs
+
+
+
+
+ TX_7
+
+
+ pipe_rx_7_sigs
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pcie2_ext_pipe_ep_legacy
+ pcie_ext_pipe_ep_legacy
+ External PIPE Interface
+
+
+
+
+
+
+ COMMANDS_IN
+
+
+ common_commands_out
+
+
+
+
+ COMMANDS_OUT
+
+
+ common_commands_in
+
+
+
+
+ RX_0
+
+
+ pipe_tx_0_sigs
+
+
+
+
+ RX_1
+
+
+ pipe_tx_1_sigs
+
+
+
+
+ RX_2
+
+
+ pipe_tx_2_sigs
+
+
+
+
+ RX_3
+
+
+ pipe_tx_3_sigs
+
+
+
+
+ RX_4
+
+
+ pipe_tx_4_sigs
+
+
+
+
+ RX_5
+
+
+ pipe_tx_5_sigs
+
+
+
+
+ RX_6
+
+
+ pipe_tx_6_sigs
+
+
+
+
+ RX_7
+
+
+ pipe_tx_7_sigs
+
+
+
+
+ TX_0
+
+
+ pipe_rx_0_sigs
+
+
+
+
+ TX_1
+
+
+ pipe_rx_1_sigs
+
+
+
+
+ TX_2
+
+
+ pipe_rx_2_sigs
+
+
+
+
+ TX_3
+
+
+ pipe_rx_3_sigs
+
+
+
+
+ TX_4
+
+
+ pipe_rx_4_sigs
+
+
+
+
+ TX_5
+
+
+ pipe_rx_5_sigs
+
+
+
+
+ TX_6
+
+
+ pipe_rx_6_sigs
+
+
+
+
+ TX_7
+
+
+ pipe_rx_7_sigs
+
+
+
+
+
+
+ false
+
+
+
+
+
+
+
+
+ xilinx_elaboratesubcores
+ Elaborate Sub-Cores
+ :vivado.xilinx.com:elaborate.subcores
+
+
+ outputProductCRC
+ 9:a59ead8b
+
+
+
+
+ xilinx_veriloginstantiationtemplate
+ Verilog Instantiation Template
+ verilogSource:vivado.xilinx.com:synthesis.template
+ verilog
+
+ xilinx_veriloginstantiationtemplate_view_fileset
+
+
+
+ GENtimestamp
+ Mon Jul 11 16:39:34 UTC 2022
+
+
+ outputProductCRC
+ 9:203c374d
+
+
+
+
+ xilinx_verilogbehavioralsimulation
+ Verilog Simulation
+ verilogSource:vivado.xilinx.com:simulation
+ verilog
+ pcie_7x_0_pcie2_top
+
+ xilinx_verilogbehavioralsimulation_view_fileset
+
+
+
+ GENtimestamp
+ Mon Jul 11 16:39:36 UTC 2022
+
+
+ outputProductCRC
+ 9:df3b5035
+
+
+
+
+ xilinx_verilogsimulationwrapper
+ Verilog Simulation Wrapper
+ verilogSource:vivado.xilinx.com:simulation.wrapper
+ verilog
+ pcie_7x_0
+
+ xilinx_verilogsimulationwrapper_view_fileset
+
+
+
+ GENtimestamp
+ Mon Jul 11 16:39:37 UTC 2022
+
+
+ outputProductCRC
+ 9:df3b5035
+
+
+
+
+ xilinx_versioninformation
+ Version Information
+ :vivado.xilinx.com:docs.versioninfo
+
+ xilinx_versioninformation_view_fileset
+
+
+
+ GENtimestamp
+ Mon Jul 11 16:39:37 UTC 2022
+
+
+ outputProductCRC
+ 9:203c374d
+
+
+
+
+ xilinx_verilogsynthesis
+ Verilog Synthesis
+ verilogSource:vivado.xilinx.com:synthesis
+ verilog
+ pcie_7x_0_pcie2_top
+
+ xilinx_verilogsynthesis_view_fileset
+
+
+
+ GENtimestamp
+ Wed Jul 20 10:37:04 UTC 2022
+
+
+ outputProductCRC
+ 9:203c374d
+
+
+
+
+ xilinx_synthesisconstraints
+ Synthesis Constraints
+ :vivado.xilinx.com:synthesis.constraints
+
+
+ outputProductCRC
+ 9:203c374d
+
+
+
+
+ xilinx_verilogsynthesiswrapper
+ Verilog Synthesis Wrapper
+ verilogSource:vivado.xilinx.com:synthesis.wrapper
+ verilog
+ pcie_7x_0
+
+ xilinx_verilogsynthesiswrapper_view_fileset
+
+
+
+ GENtimestamp
+ Wed Jul 20 10:37:04 UTC 2022
+
+
+ outputProductCRC
+ 9:203c374d
+
+
+
+
+ xilinx_externalfiles
+ External Files
+ :vivado.xilinx.com:external.files
+
+ xilinx_externalfiles_view_fileset
+
+
+
+ GENtimestamp
+ Tue May 23 16:05:53 UTC 2023
+
+
+ outputProductCRC
+ 9:203c374d
+
+
+
+
+
+
+ pci_exp_txp
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+ pci_exp_txn
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+ pci_exp_rxp
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+ pci_exp_rxn
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+ int_pclk_out_slave
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ int_pipe_rxusrclk_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ int_rxoutclk_out
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ int_dclk_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ int_mmcm_lock_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ int_userclk1_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ int_userclk2_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ int_oobclk_out
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ int_qplllock_out
+
+ out
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ int_qplloutclk_out
+
+ out
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ int_qplloutrefclk_out
+
+ out
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ int_pclk_sel_slave
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_pclk_in
+
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+
+ false
+
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+
+ startup_preq
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ startup_clk
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
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+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ startup_gsr
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ startup_gts
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ startup_keyclearb
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 1
+
+
+
+
+
+ false
+
+
+
+
+
+ startup_pack
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ startup_usrcclko
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 1
+
+
+
+
+
+ false
+
+
+
+
+
+ startup_usrcclkts
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ startup_usrdoneo
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ startup_usrdonets
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 1
+
+
+
+
+
+ false
+
+
+
+
+
+ icap_clk
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ icap_csib
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ icap_rdwrb
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ icap_i
+
+ in
+
+ 31
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+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+ 0
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+
+
+
+
+ false
+
+
+
+
+
+ icap_o
+
+ out
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+ 31
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+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_drp_crscode
+
+ in
+
+ 11
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_drp_fsm
+
+ in
+
+ 17
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+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_drp_done
+
+ in
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_drp_reset
+
+ in
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_qplllock
+
+ in
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_qplloutclk
+
+ in
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_qplloutrefclk
+
+ in
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_qplld
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_qpllreset
+
+ out
+
+ 1
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_drp_clk
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_drp_rst_n
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_drp_ovrd
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_drp_gen3
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ qpll_drp_start
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_txprbssel
+
+ in
+
+ 2
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rxprbssel
+
+ in
+
+ 2
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_txprbsforceerr
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rxprbscntreset
+
+ in
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_loopback
+
+ in
+
+ 2
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rxprbserr
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_txinhibit
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rst_fsm
+
+ out
+
+ 4
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_qrst_fsm
+
+ out
+
+ 11
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rate_fsm
+
+ out
+
+ 19
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_sync_fsm_tx
+
+ out
+
+ 23
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_sync_fsm_rx
+
+ out
+
+ 27
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_drp_fsm
+
+ out
+
+ 27
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rst_idle
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_qrst_idle
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rate_idle
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_eyescandataerror
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rxstatus
+
+ out
+
+ 11
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_dmonitorout
+
+ out
+
+ 59
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
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+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_cpll_lock
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_qpll_lock
+
+ out
+
+ 0
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rxpmaresetdone
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rxbufstatus
+
+ out
+
+ 11
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_txphaligndone
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_txphinitdone
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_txdlysresetdone
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rxphaligndone
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rxdlysresetdone
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rxsyncdone
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rxdisperr
+
+ out
+
+ 31
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rxnotintable
+
+ out
+
+ 31
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_rxcommadet
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ gt_ch_drp_rdy
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_debug_1
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_debug_2
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_debug_3
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_debug_4
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_debug_5
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_debug_6
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_debug_7
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_debug_8
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_debug_9
+
+ out
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ pipe_debug
+
+ out
+
+ 31
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ ext_ch_gt_drpclk
+
+ out
+
+
+ std_logic
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+
+
+
+ false
+
+
+
+
+
+ ext_ch_gt_drpaddr
+
+ in
+
+ 35
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ ext_ch_gt_drpen
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ ext_ch_gt_drpdi
+
+ in
+
+ 63
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ ext_ch_gt_drpwe
+
+ in
+
+ 3
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+ false
+
+
+
+
+
+ ext_ch_gt_drpdo
+
+ out
+
+ 63
+ 0
+
+
+
+ std_logic_vector
+ xilinx_verilogsynthesis
+ xilinx_verilogbehavioralsimulation
+
+
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+ 00
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+ true
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+ 3
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+ 00000000
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+ 10EE
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+ 0007
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+ 00000000
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+ FALSE
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+ 011
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+ 0010
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+ FALSE
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+ FALSE
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+ 00001
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+ Keep Width
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+
+
+ choice_list_f5f941aa
+ 2
+ 4
+ 8
+ 16
+ 32
+ 64
+ 128
+ 256
+ 512
+
+
+ choice_pairs_0332e24c
+ 100_MHz
+ 250_MHz
+
+
+ choice_pairs_067d6dc7
+ 4'h1
+ 4'h2
+
+
+ choice_pairs_0db949eb
+ Reserved
+ Wireless_controller
+ Satellite_communication_controllers
+ Data_acquisition_and_signal_processing_controllers
+ Intelligent_I/O_controllers
+ Docking_stations
+ Device_was_built_before_Class_Code_definitions_were_finalized
+ Memory_controller
+ Simple_communication_controllers
+ Serial_bus_controllers
+ Encryption/Decryption_controllers
+ Display_controller
+ Multimedia_device
+ Input_devices
+ Mass_storage_controller
+ Processors
+ Device_does_not_fit_in_any_defined_classes
+ Bridge_device
+ Network_controller
+ Base_system_peripherals
+
+
+ choice_pairs_26a64edf
+ 1_vector
+ 2_vectors
+ 4_vectors
+ 8_vectors
+ 16_vectors
+ 32_vectors
+ 256_vectors
+
+
+ choice_pairs_307ee298
+ Maximum_of_64_ns
+ Maximum_of_128_ns
+ Maximum_of_256_ns
+ Maximum_of_512_ns
+ Maximum_of_1_us
+ Maximum_of_2_us
+ Maximum_of_4_us
+ No_limit
+
+
+ choice_pairs_395c7aad
+ 64_bit
+ 128_bit
+
+
+ choice_pairs_3f2631bf
+ 128_bytes
+ 256_bytes
+ 512_bytes
+ 1024_bytes
+
+
+ choice_pairs_49d248fb
+ BAR_0
+
+
+ choice_pairs_4da2f4f7
+ No_function_number_bits_used
+ First_MSB_of_function_number_used
+ First_2_MSBs_of_function_number_used
+ All_3_bits_of_function_number_used
+
+
+ choice_pairs_5a23eaa1
+ None
+ Buffer_Write
+ Buffer_Write_and_Read
+
+
+ choice_pairs_6f377f25
+ None
+ Enable_Pipe_Simulation
+ Enable_External_PIPE_Interface
+
+
+ choice_pairs_77d6f5f3
+ dB:
+ -3.5
+ 1
+
+
+ choice_pairs_7b4ddf8d
+ Disabled
+ 16-bit_I/O_Addressing
+ 32-bit_I/O_Addressing
+
+
+ choice_pairs_817775ab
+ Disabled
+ 32-bit_Addressing
+ 64-bit_Addressing
+
+
+ choice_pairs_8d857fe8
+ 64_byte
+ 128_byte
+
+
+ choice_pairs_b03f0655
+ None
+ Tandem_PROM (Refer PG054)
+
+
+ choice_pairs_c7407e77
+ Range_A
+ Range_B
+ Ranges_A_&_B
+ Ranges_B_&_C
+ Ranges_A,_B_&_C
+ Ranges_B,_C_&_D
+ Ranges_A,_B,_C_&_D
+
+
+ choice_pairs_c98117c0
+ RAM
+ Other_memory_controller
+ Flash
+
+
+ choice_pairs_d06c0498
+ 2.5_GT/s
+ 5.0_GT/s
+
+
+ choice_pairs_db58a2b2
+ Initial_ES
+ GES_and_Production
+
+
+ choice_pairs_dbee2759
+ Maximum_of_1_us
+ Maximum_of_2_us
+ Maximum_of_4_us
+ Maximum_of_8_us
+ Maximum_of_16_us
+ Maximum_of_32_us
+ Maximum_of_64_us
+ No_limit
+
+
+ choice_pairs_dc66c043
+ PCI_Express_Endpoint_device
+ Legacy_PCI_Express_Endpoint_device
+ Root_Port_of_PCI_Express_Root_Complex
+
+
+
+
+ xilinx_veriloginstantiationtemplate_view_fileset
+
+ pcie_7x_0.vho
+ vhdlTemplate
+
+
+ pcie_7x_0.veo
+ verilogTemplate
+
+
+
+ xilinx_verilogbehavioralsimulation_view_fileset
+
+ source/pcie_7x_0_pipe_eq.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pipe_drp.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pipe_rate.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pipe_reset.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pipe_sync.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gtp_pipe_rate.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gtp_pipe_drp.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gtp_pipe_reset.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pipe_user.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pipe_wrapper.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_qpll_drp.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_qpll_reset.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_qpll_wrapper.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_rxeq_scan.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_top.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ sys_clk_gen_ps_v.txt
+ text
+
+
+ source/pcie_7x_0_core_top.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_rx_null_gen.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_rx_pipeline.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_rx.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_top.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_tx_pipeline.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_tx_thrtl_ctl.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_tx.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_7x.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_bram_7x.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_bram_top_7x.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_brams_7x.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_pipe_lane.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_pipe_misc.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_pipe_pipeline.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gt_top.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gt_common.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gtp_cpllpd_ovrd.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gtx_cpllpd_ovrd.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gt_rx_valid_filter_7x.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gt_wrapper.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie2_top.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+
+ xilinx_verilogsimulationwrapper_view_fileset
+
+ sim/pcie_7x_0.v
+ verilogSource
+ xil_defaultlib
+
+
+
+ xilinx_versioninformation_view_fileset
+
+ doc/pcie_7x_v3_3_changelog.txt
+ text
+
+
+
+ xilinx_verilogsynthesis_view_fileset
+
+ source/pcie_7x_0_pipe_eq.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pipe_drp.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pipe_rate.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pipe_reset.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pipe_sync.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gtp_pipe_rate.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gtp_pipe_drp.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gtp_pipe_reset.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pipe_user.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pipe_wrapper.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_qpll_drp.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_qpll_reset.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_qpll_wrapper.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_rxeq_scan.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_top.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ sys_clk_gen_ps_v.txt
+ text
+
+
+ source/pcie_7x_0_core_top.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_rx_null_gen.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_rx_pipeline.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_rx.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_top.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_tx_pipeline.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_tx_thrtl_ctl.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_axi_basic_tx.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_7x.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_bram_7x.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_bram_top_7x.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_brams_7x.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_pipe_lane.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_pipe_misc.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie_pipe_pipeline.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gt_top.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gt_common.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gtp_cpllpd_ovrd.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gtx_cpllpd_ovrd.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gt_rx_valid_filter_7x.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_gt_wrapper.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0-PCIE_X0Y0.xdc
+ xdc
+ pcie_7x_0_pcie2_top
+
+
+ synth/pcie_7x_0_ooc.xdc
+ xdc
+ USED_IN_implementation
+ USED_IN_out_of_context
+ USED_IN_synthesis
+ pcie_7x_0_pcie2_top
+
+
+ source/pcie_7x_0_pcie2_top.v
+ verilogSource
+ pcie_7x_0_pcie2_top
+
+
+
+ xilinx_verilogsynthesiswrapper_view_fileset
+
+ synth/pcie_7x_0.v
+ verilogSource
+ xil_defaultlib
+
+
+
+ xilinx_externalfiles_view_fileset
+
+ pcie_7x_0.dcp
+ dcp
+ USED_IN_implementation
+ USED_IN_synthesis
+ xil_defaultlib
+
+
+ pcie_7x_0_stub.v
+ verilogSource
+ USED_IN_synth_blackbox_stub
+ xil_defaultlib
+
+
+ pcie_7x_0_stub.vhdl
+ vhdlSource
+ USED_IN_synth_blackbox_stub
+ xil_defaultlib
+
+
+ pcie_7x_0_sim_netlist.v
+ verilogSource
+ USED_IN_simulation
+ USED_IN_single_language
+ xil_defaultlib
+
+
+ pcie_7x_0_sim_netlist.vhdl
+ vhdlSource
+ USED_IN_simulation
+ USED_IN_single_language
+ xil_defaultlib
+
+
+
+ The Xilinx 7 Series Integrated Block for PCI Express (1-lane, 2-lane, 4-lane, and 8-lane) uses the 7-Series Integrated Hard IP Block for PCI Express in conjunction with flexible 7-Series architectural features to implement a PCI Express Base Specification v2.1 compliant PCI Express Endpoint or Root Port. Unique features of the LogiCORE Block for PCI Express are the high performance AXI Interface, optimal buffering for high bandwidth applications, and BAR checking and filtering.
+
+
+ mode_selection
+ Mode
+ Basic
+
+
+ Use_Class_Code_Lookup_Assistant
+ false
+
+
+ Component_Name
+ pcie_7x_0
+
+
+ Device_Port_Type
+ PCI_Express_Endpoint_device
+
+
+ Maximum_Link_Width
+ X4
+
+
+ Link_Speed
+ 5.0_GT/s
+
+
+ Interface_Width
+ 64_bit
+
+
+ User_Clk_Freq
+ 250
+
+
+ Bar0_Enabled
+ true
+
+
+ Bar0_Type
+ Memory
+
+
+ Bar0_64bit
+ false
+
+
+ Bar0_Prefetchable
+ false
+
+
+ Bar0_Scale
+ Kilobytes
+
+
+ Bar0_Size
+ 64
+
+
+ Bar1_Enabled
+ false
+
+
+ Bar1_Type
+ N/A
+
+
+ Bar1_64bit
+ false
+
+
+ Bar1_Prefetchable
+ false
+
+
+ Bar1_Scale
+ Megabytes
+
+
+ Bar1_Size
+ 1
+
+
+ Bar2_Enabled
+ false
+
+
+ Bar2_Type
+ N/A
+
+
+ Bar2_64bit
+ false
+
+
+ Bar2_Prefetchable
+ false
+
+
+ Bar2_Scale
+ Kilobytes
+
+
+ Bar2_Size
+ 2
+
+
+ Bar3_Enabled
+ false
+
+
+ Bar3_Type
+ N/A
+
+
+ Bar3_64bit
+ false
+
+
+ Bar3_Prefetchable
+ false
+
+
+ Bar3_Scale
+ Kilobytes
+
+
+ Bar3_Size
+ 2
+
+
+ Bar4_Enabled
+ false
+
+
+ Bar4_Type
+ N/A
+
+
+ Bar4_64bit
+ false
+
+
+ Bar4_Prefetchable
+ false
+
+
+ Bar4_Scale
+ Kilobytes
+
+
+ Bar4_Size
+ 2
+
+
+ Bar5_Enabled
+ false
+
+
+ Bar5_Type
+ N/A
+
+
+ Bar5_Prefetchable
+ false
+
+
+ Bar5_Scale
+ Kilobytes
+
+
+ Bar5_Size
+ 2
+
+
+ Expansion_Rom_Enabled
+ false
+
+
+ Expansion_Rom_Scale
+ Kilobytes
+
+
+ Expansion_Rom_Size
+ 2
+
+
+ IO_Base_Limit_Registers
+ Disabled
+
+
+ Prefetchable_Memory_Base_Limit_Registers
+ Disabled
+
+
+ Vendor_ID
+ 10EE
+
+
+ Device_ID
+ 7024
+
+
+ Revision_ID
+ 00
+
+
+ Subsystem_Vendor_ID
+ 10EE
+
+
+ Subsystem_ID
+ 0007
+
+
+ Class_Code_Base
+ 05
+
+
+ Class_Code_Sub
+ 00
+
+
+ Class_Code_Interface
+ 00
+
+
+ Base_Class_Menu
+ Memory_controller
+
+
+ Sub_Class_Interface_Menu
+ RAM
+
+
+ Cardbus_CIS_Pointer
+ 00000000
+
+
+ PCIe_Cap_Slot_Implemented
+ false
+
+
+ Max_Payload_Size
+ 1024_bytes
+
+
+ Extended_Tag_Field
+ false
+
+
+ Extended_Tag_Default
+ false
+
+
+ Phantom_Functions
+ No_function_number_bits_used
+
+
+ Acceptable_L0s_Latency
+ Maximum_of_64_ns
+
+
+ Acceptable_L1_Latency
+ No_limit
+
+
+ Cpl_Finite
+ false
+
+
+ Cpl_Timeout_Disable_Sup
+ false
+
+
+ Cpl_Timeout_Range
+ Range_B
+
+
+ Buf_Opt_BMA
+ false
+
+
+ Perf_Level
+ High
+
+
+ Dll_Link_Active_Cap
+ false
+
+
+ RCB
+ 64_byte
+
+
+ Trgt_Link_Speed
+ 4'h2
+
+
+ Hw_Auton_Spd_Disable
+ false
+
+
+ De_emph
+ -3.5
+
+
+ Enable_Slot_Clock_Cfg
+ true
+
+
+ Root_Cap_CRS
+ false
+
+
+ Slot_Cap_Attn_Butn
+ false
+
+
+ Slot_Cap_Pwr_Ctrl
+ false
+
+
+ Slot_Cap_MRL
+ false
+
+
+ Slot_Cap_Attn_Ind
+ false
+
+
+ Slot_Cap_Pwr_Ind
+ false
+
+
+ Slot_Cap_HotPlug_Surprise
+ false
+
+
+ Slot_Cap_HotPlug_Cap
+ false
+
+
+ Slot_Cap_Elec_Interlock
+ false
+
+
+ Slot_Cap_No_Cmd_Comp_Sup
+ false
+
+
+ Slot_Cap_Pwr_Limit_Value
+ 0
+
+
+ Slot_Cap_Pwr_Limit_Scale
+ 0
+
+
+ Slot_Cap_Physical_Slot_Num
+ 0
+
+
+ IntX_Generation
+ true
+
+
+ Legacy_Interrupt
+ INTA
+
+
+ MSI_Enabled
+ false
+
+
+ MSI_64b
+ true
+
+
+ Multiple_Message_Capable
+ 1_vector
+
+
+ MSI_Vec_Mask
+ false
+
+
+ MSIx_Enabled
+ false
+
+
+ MSIx_Table_Size
+ 1
+
+
+ MSIx_Table_Offset
+ 0
+
+
+ MSIx_Table_BIR
+ BAR_0
+
+
+ MSIx_PBA_Offset
+ 0
+
+
+ MSIx_PBA_BIR
+ BAR_0
+
+
+ Device_Specific_Initialization
+ false
+
+
+ D1_Support
+ false
+
+
+ D2_Support
+ false
+
+
+ D0_PME_Support
+ true
+
+
+ D1_PME_Support
+ true
+
+
+ D2_PME_Support
+ true
+
+
+ D3hot_PME_Support
+ true
+
+
+ D3cold_PME_Support
+ false
+
+
+ No_Soft_Reset
+ true
+
+
+ D0_Power_Consumed
+ 0
+
+
+ D0_Power_Consumed_Factor
+ 0
+
+
+ D1_Power_Consumed
+ 0
+
+
+ D1_Power_Consumed_Factor
+ 0
+
+
+ D2_Power_Consumed
+ 0
+
+
+ D2_Power_Consumed_Factor
+ 0
+
+
+ D3_Power_Consumed
+ 0
+
+
+ D3_Power_Consumed_Factor
+ 0
+
+
+ D0_Power_Dissipated
+ 0
+
+
+ D0_Power_Dissipated_Factor
+ 0
+
+
+ D1_Power_Dissipated
+ 0
+
+
+ D1_Power_Dissipated_Factor
+ 0
+
+
+ D2_Power_Dissipated
+ 0
+
+
+ D2_Power_Dissipated_Factor
+ 0
+
+
+ D3_Power_Dissipated
+ 0
+
+
+ D3_Power_Dissipated_Factor
+ 0
+
+
+ DSN_Enabled
+ true
+
+
+ VC_Cap_Enabled
+ false
+
+
+ VC_Cap_Reject_Snoop
+ false
+
+
+ VSEC_Enabled
+ false
+
+
+ PCI_CFG_Space
+ false
+
+
+ PCI_CFG_Space_Addr
+ 3F
+
+
+ EXT_PCI_CFG_Space
+ false
+
+
+ EXT_PCI_CFG_Space_Addr
+ 3FF
+
+
+ Xlnx_Ref_Board
+ ZC706
+
+
+ PCIe_Blk_Locn
+ X0Y0
+
+
+ Trans_Buf_Pipeline
+ None
+
+
+ En_route_unlock
+ false
+
+
+ En_route_pme_to
+ false
+
+
+ En_route_err_cor
+ false
+
+
+ En_route_err_nfl
+ false
+
+
+ En_route_err_ftl
+ false
+
+
+ En_route_inta
+ false
+
+
+ En_route_intb
+ false
+
+
+ En_route_intc
+ false
+
+
+ En_route_intd
+ false
+
+
+ En_route_pm_pme
+ false
+
+
+ En_route_pme_to_ack
+ false
+
+
+ Receive_NP_Request
+ true
+
+
+ Enable_ACK_NAK_Timer
+ false
+
+
+ ACK_NAK_Timeout_Func
+ Absolute
+
+
+ ACK_NAK_Timeout_Value
+ 0000
+
+
+ Enable_Replay_Timer
+ false
+
+
+ Replay_Timeout_Func
+ Add
+
+
+ Replay_Timeout_Value
+ 0000
+
+
+ Enable_Lane_Reversal
+ false
+
+
+ Upconfigure_Capable
+ true
+
+
+ Force_No_Scrambling
+ false
+
+
+ Disable_Tx_ASPM_L0s
+ false
+
+
+ Downstream_Link_Num
+ 00
+
+
+ UR_INV_REQ
+ true
+
+
+ UR_PRS_RESPONSE
+ true
+
+
+ Silicon_Rev
+ GES_and_Production
+
+
+ Pcie_fast_config
+ None
+
+
+ PCIe_Debug_Ports
+ true
+
+
+ Ref_Clk_Freq
+ 100_MHz
+
+
+ Cost_Table
+ 1
+
+
+ UR_Atomic
+ false
+
+
+ ATOMICOP32_Completer_Supported
+ false
+
+
+ ATOMICOP64_Completer_Supported
+ false
+
+
+ CAS128_Completer_Supported
+ false
+
+
+ TPH_Completer_Supported
+ 00
+
+
+ ARI_Forwarding_Supported
+ false
+
+
+ AtomicOp_Routing_Supported
+ false
+
+
+ ASPM_Optionality
+ false
+
+
+ AER_Enabled
+ false
+
+
+ AER_ECRC_Check_Capable
+ false
+
+
+ AER_ECRC_Gen_Capable
+ false
+
+
+ AER_Multiheader
+ false
+
+
+ AER_Permit_Root_Error_Update
+ false
+
+
+ AER_Correctable_Internal_Error
+ false
+
+
+ AER_Header_Log_Overflow
+ false
+
+
+ AER_Receiver_Error
+ false
+
+
+ AER_Surprise_Down
+ false
+
+
+ AER_Flow_Control_Protocol_Error
+ false
+
+
+ AER_Completion_Timeout
+ false
+
+
+ AER_Completer_Abort
+ false
+
+
+ AER_Receiver_Overflow
+ false
+
+
+ AER_ECRC_Error
+ false
+
+
+ AER_ACS_Violation
+ false
+
+
+ AER_Uncorrectable_Internal_Error
+ false
+
+
+ AER_MC_Blocked_TLP
+ false
+
+
+ AER_AtomicOp_Egress_Blocked
+ false
+
+
+ AER_TLP_Prefix_Blocked
+ false
+
+
+ Optional_Error_Support
+ 000000
+
+
+ RBAR_Enabled
+ false
+
+
+ RBAR_Num
+ 0
+
+
+ BAR_Index_Value0
+ 0
+
+
+ BAR0_Size_Vector
+ 1M
+
+
+ RBAR_Initial_Value0
+ 0
+
+
+ BAR_Index_Value1
+ 0
+
+
+ BAR1_Size_Vector
+ 1M
+
+
+ RBAR_Initial_Value1
+ 0
+
+
+ BAR_Index_Value2
+ 0
+
+
+ BAR2_Size_Vector
+ 1M
+
+
+ RBAR_Initial_Value2
+ 0
+
+
+ BAR_Index_Value3
+ 0
+
+
+ BAR3_Size_Vector
+ 1M
+
+
+ RBAR_Initial_Value3
+ 0
+
+
+ BAR_Index_Value4
+ 0
+
+
+ BAR4_Size_Vector
+ 1M
+
+
+ RBAR_Initial_Value4
+ 0
+
+
+ BAR_Index_Value5
+ 0
+
+
+ BAR5_Size_Vector
+ 1M
+
+
+ RBAR_Initial_Value5
+ 0
+
+
+ RECRC_Check
+ 0
+
+
+ RECRC_Check_Trim
+ false
+
+
+ Disable_Rx_Poisoned_Resp
+ false
+
+
+ pipe_sim
+ false
+
+
+ en_ext_clk
+ true
+
+
+ en_ext_gt_common
+ false
+
+
+ en_ext_ch_gt_drp
+ false
+
+
+ en_transceiver_status_ports
+ false
+
+
+ shared_logic_in_core
+ false
+
+
+ pl_interface
+ true
+
+
+ cfg_mgmt_if
+ true
+
+
+ cfg_ctl_if
+ true
+
+
+ cfg_status_if
+ true
+
+
+ rcv_msg_if
+ true
+
+
+ cfg_fc_if
+ true
+
+
+ err_reporting_if
+ true
+
+
+ USE_BOARD_FLOW
+ Generate Board based IO Constraints
+ false
+
+
+ RESET_BOARD_INTERFACE
+ Custom
+
+
+ en_ext_pipe_interface
+ false
+
+
+ en_ext_startup
+ false
+
+
+ pipe_mode_sim
+ None
+
+
+ enable_jtag_dbg
+ false
+
+
+ reduce_oob_freq
+ false
+
+
+
+
+ 7 Series Integrated Block for PCI Express
+
+ XPM_CDC
+ XPM_MEMORY
+
+ 14
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2020.2
+
+
+
+
+
+
+
+
diff --git a/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_sim_netlist.v b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_sim_netlist.v
new file mode 100644
index 0000000..9d1d801
--- /dev/null
+++ b/projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0_sim_netlist.v
@@ -0,0 +1,66137 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+// Date : Wed Jul 20 13:38:01 2022
+// Host : DESKTOP-4NLVFC8 running 64-bit major release (build 9200)
+// Command : write_verilog -force -mode funcsim -rename_top pcie_7x_0 -prefix
+// pcie_7x_0_ pcie_7x_0_sim_netlist.v
+// Design : pcie_7x_0
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7z045ffg900-2
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module pcie_7x_0_BRAM_TDP_MACRO_viv_
+ (rdata,
+ pipe_userclk1_in,
+ mim_tx_wen,
+ mim_tx_ren,
+ MIMTXWADDR,
+ MIMTXRADDR,
+ wdata);
+ output [5:0]rdata;
+ input pipe_userclk1_in;
+ input mim_tx_wen;
+ input mim_tx_ren;
+ input [11:0]MIMTXWADDR;
+ input [11:0]MIMTXRADDR;
+ input [5:0]wdata;
+
+ wire [11:0]MIMTXRADDR;
+ wire [11:0]MIMTXWADDR;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_60 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_61 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_75 ;
+ wire mim_tx_ren;
+ wire mim_tx_wen;
+ wire pipe_userclk1_in;
+ wire [5:0]rdata;
+ wire [5:0]wdata;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],1'b0,1'b0,wdata}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_60 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_61 ,rdata}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_75 }),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_tx_wen),
+ .ENBWREN(mim_tx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_11
+ (rdata,
+ pipe_userclk1_in,
+ mim_tx_wen,
+ mim_tx_ren,
+ MIMTXWADDR,
+ MIMTXRADDR,
+ wdata);
+ output [8:0]rdata;
+ input pipe_userclk1_in;
+ input mim_tx_wen;
+ input mim_tx_ren;
+ input [11:0]MIMTXWADDR;
+ input [11:0]MIMTXRADDR;
+ input [8:0]wdata;
+
+ wire [11:0]MIMTXRADDR;
+ wire [11:0]MIMTXWADDR;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_tx_ren;
+ wire mim_tx_wen;
+ wire pipe_userclk1_in;
+ wire [8:0]rdata;
+ wire [8:0]wdata;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_tx_wen),
+ .ENBWREN(mim_tx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_12
+ (rdata,
+ pipe_userclk1_in,
+ mim_tx_wen,
+ mim_tx_ren,
+ MIMTXWADDR,
+ MIMTXRADDR,
+ wdata);
+ output [8:0]rdata;
+ input pipe_userclk1_in;
+ input mim_tx_wen;
+ input mim_tx_ren;
+ input [11:0]MIMTXWADDR;
+ input [11:0]MIMTXRADDR;
+ input [8:0]wdata;
+
+ wire [11:0]MIMTXRADDR;
+ wire [11:0]MIMTXWADDR;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_tx_ren;
+ wire mim_tx_wen;
+ wire pipe_userclk1_in;
+ wire [8:0]rdata;
+ wire [8:0]wdata;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_tx_wen),
+ .ENBWREN(mim_tx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_13
+ (rdata,
+ pipe_userclk1_in,
+ mim_tx_wen,
+ mim_tx_ren,
+ MIMTXWADDR,
+ MIMTXRADDR,
+ wdata);
+ output [8:0]rdata;
+ input pipe_userclk1_in;
+ input mim_tx_wen;
+ input mim_tx_ren;
+ input [11:0]MIMTXWADDR;
+ input [11:0]MIMTXRADDR;
+ input [8:0]wdata;
+
+ wire [11:0]MIMTXRADDR;
+ wire [11:0]MIMTXWADDR;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_tx_ren;
+ wire mim_tx_wen;
+ wire pipe_userclk1_in;
+ wire [8:0]rdata;
+ wire [8:0]wdata;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_tx_wen),
+ .ENBWREN(mim_tx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_14
+ (rdata,
+ pipe_userclk1_in,
+ mim_tx_wen,
+ mim_tx_ren,
+ MIMTXWADDR,
+ MIMTXRADDR,
+ wdata);
+ output [8:0]rdata;
+ input pipe_userclk1_in;
+ input mim_tx_wen;
+ input mim_tx_ren;
+ input [11:0]MIMTXWADDR;
+ input [11:0]MIMTXRADDR;
+ input [8:0]wdata;
+
+ wire [11:0]MIMTXRADDR;
+ wire [11:0]MIMTXWADDR;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_tx_ren;
+ wire mim_tx_wen;
+ wire pipe_userclk1_in;
+ wire [8:0]rdata;
+ wire [8:0]wdata;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_tx_wen),
+ .ENBWREN(mim_tx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_15
+ (rdata,
+ pipe_userclk1_in,
+ mim_tx_wen,
+ mim_tx_ren,
+ MIMTXWADDR,
+ MIMTXRADDR,
+ wdata);
+ output [8:0]rdata;
+ input pipe_userclk1_in;
+ input mim_tx_wen;
+ input mim_tx_ren;
+ input [11:0]MIMTXWADDR;
+ input [11:0]MIMTXRADDR;
+ input [8:0]wdata;
+
+ wire [11:0]MIMTXRADDR;
+ wire [11:0]MIMTXWADDR;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_tx_ren;
+ wire mim_tx_wen;
+ wire pipe_userclk1_in;
+ wire [8:0]rdata;
+ wire [8:0]wdata;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_tx_wen),
+ .ENBWREN(mim_tx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_16
+ (rdata,
+ pipe_userclk1_in,
+ mim_tx_wen,
+ mim_tx_ren,
+ MIMTXWADDR,
+ MIMTXRADDR,
+ wdata);
+ output [8:0]rdata;
+ input pipe_userclk1_in;
+ input mim_tx_wen;
+ input mim_tx_ren;
+ input [11:0]MIMTXWADDR;
+ input [11:0]MIMTXRADDR;
+ input [8:0]wdata;
+
+ wire [11:0]MIMTXRADDR;
+ wire [11:0]MIMTXWADDR;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_tx_ren;
+ wire mim_tx_wen;
+ wire pipe_userclk1_in;
+ wire [8:0]rdata;
+ wire [8:0]wdata;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_tx_wen),
+ .ENBWREN(mim_tx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_17
+ (rdata,
+ pipe_userclk1_in,
+ mim_tx_wen,
+ mim_tx_ren,
+ MIMTXWADDR,
+ MIMTXRADDR,
+ wdata);
+ output [8:0]rdata;
+ input pipe_userclk1_in;
+ input mim_tx_wen;
+ input mim_tx_ren;
+ input [11:0]MIMTXWADDR;
+ input [11:0]MIMTXRADDR;
+ input [8:0]wdata;
+
+ wire [11:0]MIMTXRADDR;
+ wire [11:0]MIMTXWADDR;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_tx_ren;
+ wire mim_tx_wen;
+ wire pipe_userclk1_in;
+ wire [8:0]rdata;
+ wire [8:0]wdata;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],wdata[7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],rdata[7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],rdata[8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_tx_wen),
+ .ENBWREN(mim_tx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_26
+ (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ,
+ pipe_userclk1_in,
+ mim_rx_wen,
+ mim_rx_ren,
+ MIMRXWADDR,
+ MIMRXRADDR,
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 );
+ output [4:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ input pipe_userclk1_in;
+ input mim_rx_wen;
+ input mim_rx_ren;
+ input [11:0]MIMRXWADDR;
+ input [11:0]MIMRXRADDR;
+ input [4:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+
+ wire [11:0]MIMRXRADDR;
+ wire [11:0]MIMRXWADDR;
+ wire [4:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ wire [4:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_60 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_61 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_62 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_75 ;
+ wire mim_rx_ren;
+ wire mim_rx_wen;
+ wire pipe_userclk1_in;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 }),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_60 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_61 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_62 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 }),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_75 }),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_rx_wen),
+ .ENBWREN(mim_rx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_27
+ (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ,
+ pipe_userclk1_in,
+ mim_rx_wen,
+ mim_rx_ren,
+ MIMRXWADDR,
+ MIMRXRADDR,
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 );
+ output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ input pipe_userclk1_in;
+ input mim_rx_wen;
+ input mim_rx_ren;
+ input [11:0]MIMRXWADDR;
+ input [11:0]MIMRXRADDR;
+ input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+
+ wire [11:0]MIMRXRADDR;
+ wire [11:0]MIMRXWADDR;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_rx_ren;
+ wire mim_rx_wen;
+ wire pipe_userclk1_in;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_rx_wen),
+ .ENBWREN(mim_rx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_28
+ (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ,
+ pipe_userclk1_in,
+ mim_rx_wen,
+ mim_rx_ren,
+ MIMRXWADDR,
+ MIMRXRADDR,
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 );
+ output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ input pipe_userclk1_in;
+ input mim_rx_wen;
+ input mim_rx_ren;
+ input [11:0]MIMRXWADDR;
+ input [11:0]MIMRXRADDR;
+ input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+
+ wire [11:0]MIMRXRADDR;
+ wire [11:0]MIMRXWADDR;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_rx_ren;
+ wire mim_rx_wen;
+ wire pipe_userclk1_in;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_rx_wen),
+ .ENBWREN(mim_rx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_29
+ (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ,
+ pipe_userclk1_in,
+ mim_rx_wen,
+ mim_rx_ren,
+ MIMRXWADDR,
+ MIMRXRADDR,
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 );
+ output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ input pipe_userclk1_in;
+ input mim_rx_wen;
+ input mim_rx_ren;
+ input [11:0]MIMRXWADDR;
+ input [11:0]MIMRXRADDR;
+ input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+
+ wire [11:0]MIMRXRADDR;
+ wire [11:0]MIMRXWADDR;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_rx_ren;
+ wire mim_rx_wen;
+ wire pipe_userclk1_in;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_rx_wen),
+ .ENBWREN(mim_rx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_30
+ (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ,
+ pipe_userclk1_in,
+ mim_rx_wen,
+ mim_rx_ren,
+ MIMRXWADDR,
+ MIMRXRADDR,
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 );
+ output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ input pipe_userclk1_in;
+ input mim_rx_wen;
+ input mim_rx_ren;
+ input [11:0]MIMRXWADDR;
+ input [11:0]MIMRXRADDR;
+ input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+
+ wire [11:0]MIMRXRADDR;
+ wire [11:0]MIMRXWADDR;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_rx_ren;
+ wire mim_rx_wen;
+ wire pipe_userclk1_in;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_rx_wen),
+ .ENBWREN(mim_rx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_31
+ (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ,
+ pipe_userclk1_in,
+ mim_rx_wen,
+ mim_rx_ren,
+ MIMRXWADDR,
+ MIMRXRADDR,
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 );
+ output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ input pipe_userclk1_in;
+ input mim_rx_wen;
+ input mim_rx_ren;
+ input [11:0]MIMRXWADDR;
+ input [11:0]MIMRXRADDR;
+ input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+
+ wire [11:0]MIMRXRADDR;
+ wire [11:0]MIMRXWADDR;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_rx_ren;
+ wire mim_rx_wen;
+ wire pipe_userclk1_in;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_rx_wen),
+ .ENBWREN(mim_rx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_32
+ (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ,
+ pipe_userclk1_in,
+ mim_rx_wen,
+ mim_rx_ren,
+ MIMRXWADDR,
+ MIMRXRADDR,
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 );
+ output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ input pipe_userclk1_in;
+ input mim_rx_wen;
+ input mim_rx_ren;
+ input [11:0]MIMRXWADDR;
+ input [11:0]MIMRXRADDR;
+ input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+
+ wire [11:0]MIMRXRADDR;
+ wire [11:0]MIMRXWADDR;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_rx_ren;
+ wire mim_rx_wen;
+ wire pipe_userclk1_in;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_rx_wen),
+ .ENBWREN(mim_rx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "BRAM_TDP_MACRO" *)
+module pcie_7x_0_BRAM_TDP_MACRO_33
+ (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ,
+ pipe_userclk1_in,
+ mim_rx_wen,
+ mim_rx_ren,
+ MIMRXWADDR,
+ MIMRXRADDR,
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 );
+ output [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ input pipe_userclk1_in;
+ input mim_rx_wen;
+ input mim_rx_ren;
+ input [11:0]MIMRXWADDR;
+ input [11:0]MIMRXRADDR;
+ input [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+
+ wire [11:0]MIMRXRADDR;
+ wire [11:0]MIMRXWADDR;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
+ wire [8:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
+ wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
+ wire mim_rx_ren;
+ wire mim_rx_wen;
+ wire pipe_userclk1_in;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
+ wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
+ wire [31:8]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
+ wire [3:1]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
+ wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
+ wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ RAMB36E1 #(
+ .DOA_REG(0),
+ .DOB_REG(1),
+ .EN_ECC_READ("FALSE"),
+ .EN_ECC_WRITE("FALSE"),
+ .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+ .INIT_A(36'h000000000),
+ .INIT_B(36'h000000000),
+ .INIT_FILE("NONE"),
+ .IS_CLKARDCLK_INVERTED(1'b0),
+ .IS_CLKBWRCLK_INVERTED(1'b0),
+ .IS_ENARDEN_INVERTED(1'b0),
+ .IS_ENBWREN_INVERTED(1'b0),
+ .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+ .IS_RSTRAMB_INVERTED(1'b0),
+ .IS_RSTREGARSTREG_INVERTED(1'b0),
+ .IS_RSTREGB_INVERTED(1'b0),
+ .RAM_EXTENSION_A("NONE"),
+ .RAM_EXTENSION_B("NONE"),
+ .RAM_MODE("TDP"),
+ .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
+ .READ_WIDTH_A(9),
+ .READ_WIDTH_B(9),
+ .RSTREG_PRIORITY_A("RSTREG"),
+ .RSTREG_PRIORITY_B("RSTREG"),
+ .SIM_COLLISION_CHECK("ALL"),
+ .SIM_DEVICE("7SERIES"),
+ .SRVAL_A(36'h000000000),
+ .SRVAL_B(36'h000000000),
+ .WRITE_MODE_A("NO_CHANGE"),
+ .WRITE_MODE_B("WRITE_FIRST"),
+ .WRITE_WIDTH_A(9),
+ .WRITE_WIDTH_B(9))
+ \genblk5_0.bram36_tdp_bl.bram36_tdp_bl
+ (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1}),
+ .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1}),
+ .CASCADEINA(1'b0),
+ .CASCADEINB(1'b0),
+ .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
+ .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
+ .CLKARDCLK(pipe_userclk1_in),
+ .CLKBWRCLK(pipe_userclk1_in),
+ .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
+ .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}),
+ .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}),
+ .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
+ .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
+ .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:8],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}),
+ .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
+ .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:1],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}),
+ .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
+ .ENARDEN(mim_rx_wen),
+ .ENBWREN(mim_rx_ren),
+ .INJECTDBITERR(1'b0),
+ .INJECTSBITERR(1'b0),
+ .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
+ .REGCEAREGCE(1'b0),
+ .REGCEB(1'b1),
+ .RSTRAMARSTRAM(1'b0),
+ .RSTRAMB(1'b0),
+ .RSTREGARSTREG(1'b0),
+ .RSTREGB(1'b0),
+ .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
+ .WEA({1'b1,1'b1,1'b1,1'b1}),
+ .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* CHECK_LICENSE_TYPE = "pcie_7x_0,pcie_7x_0_pcie2_top,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "pcie_7x_0_pcie2_top,Vivado 2020.2" *)
+(* NotValidForBitStream *)
+module pcie_7x_0
+ (pci_exp_txp,
+ pci_exp_txn,
+ pci_exp_rxp,
+ pci_exp_rxn,
+ pipe_pclk_in,
+ pipe_rxusrclk_in,
+ pipe_rxoutclk_in,
+ pipe_dclk_in,
+ pipe_userclk1_in,
+ pipe_userclk2_in,
+ pipe_oobclk_in,
+ pipe_mmcm_lock_in,
+ pipe_txoutclk_out,
+ pipe_rxoutclk_out,
+ pipe_pclk_sel_out,
+ pipe_gen3_out,
+ user_clk_out,
+ user_reset_out,
+ user_lnk_up,
+ user_app_rdy,
+ tx_buf_av,
+ tx_cfg_req,
+ tx_err_drop,
+ s_axis_tx_tready,
+ s_axis_tx_tdata,
+ s_axis_tx_tkeep,
+ s_axis_tx_tlast,
+ s_axis_tx_tvalid,
+ s_axis_tx_tuser,
+ tx_cfg_gnt,
+ m_axis_rx_tdata,
+ m_axis_rx_tkeep,
+ m_axis_rx_tlast,
+ m_axis_rx_tvalid,
+ m_axis_rx_tready,
+ m_axis_rx_tuser,
+ rx_np_ok,
+ rx_np_req,
+ fc_cpld,
+ fc_cplh,
+ fc_npd,
+ fc_nph,
+ fc_pd,
+ fc_ph,
+ fc_sel,
+ cfg_mgmt_do,
+ cfg_mgmt_rd_wr_done,
+ cfg_status,
+ cfg_command,
+ cfg_dstatus,
+ cfg_dcommand,
+ cfg_lstatus,
+ cfg_lcommand,
+ cfg_dcommand2,
+ cfg_pcie_link_state,
+ cfg_pmcsr_pme_en,
+ cfg_pmcsr_powerstate,
+ cfg_pmcsr_pme_status,
+ cfg_received_func_lvl_rst,
+ cfg_mgmt_di,
+ cfg_mgmt_byte_en,
+ cfg_mgmt_dwaddr,
+ cfg_mgmt_wr_en,
+ cfg_mgmt_rd_en,
+ cfg_mgmt_wr_readonly,
+ cfg_err_ecrc,
+ cfg_err_ur,
+ cfg_err_cpl_timeout,
+ cfg_err_cpl_unexpect,
+ cfg_err_cpl_abort,
+ cfg_err_posted,
+ cfg_err_cor,
+ cfg_err_atomic_egress_blocked,
+ cfg_err_internal_cor,
+ cfg_err_malformed,
+ cfg_err_mc_blocked,
+ cfg_err_poisoned,
+ cfg_err_norecovery,
+ cfg_err_tlp_cpl_header,
+ cfg_err_cpl_rdy,
+ cfg_err_locked,
+ cfg_err_acs,
+ cfg_err_internal_uncor,
+ cfg_trn_pending,
+ cfg_pm_halt_aspm_l0s,
+ cfg_pm_halt_aspm_l1,
+ cfg_pm_force_state_en,
+ cfg_pm_force_state,
+ cfg_dsn,
+ cfg_interrupt,
+ cfg_interrupt_rdy,
+ cfg_interrupt_assert,
+ cfg_interrupt_di,
+ cfg_interrupt_do,
+ cfg_interrupt_mmenable,
+ cfg_interrupt_msienable,
+ cfg_interrupt_msixenable,
+ cfg_interrupt_msixfm,
+ cfg_interrupt_stat,
+ cfg_pciecap_interrupt_msgnum,
+ cfg_to_turnoff,
+ cfg_turnoff_ok,
+ cfg_bus_number,
+ cfg_device_number,
+ cfg_function_number,
+ cfg_pm_wake,
+ cfg_pm_send_pme_to,
+ cfg_ds_bus_number,
+ cfg_ds_device_number,
+ cfg_ds_function_number,
+ cfg_mgmt_wr_rw1c_as_rw,
+ cfg_msg_received,
+ cfg_msg_data,
+ cfg_bridge_serr_en,
+ cfg_slot_control_electromech_il_ctl_pulse,
+ cfg_root_control_syserr_corr_err_en,
+ cfg_root_control_syserr_non_fatal_err_en,
+ cfg_root_control_syserr_fatal_err_en,
+ cfg_root_control_pme_int_en,
+ cfg_aer_rooterr_corr_err_reporting_en,
+ cfg_aer_rooterr_non_fatal_err_reporting_en,
+ cfg_aer_rooterr_fatal_err_reporting_en,
+ cfg_aer_rooterr_corr_err_received,
+ cfg_aer_rooterr_non_fatal_err_received,
+ cfg_aer_rooterr_fatal_err_received,
+ cfg_msg_received_err_cor,
+ cfg_msg_received_err_non_fatal,
+ cfg_msg_received_err_fatal,
+ cfg_msg_received_pm_as_nak,
+ cfg_msg_received_pm_pme,
+ cfg_msg_received_pme_to_ack,
+ cfg_msg_received_assert_int_a,
+ cfg_msg_received_assert_int_b,
+ cfg_msg_received_assert_int_c,
+ cfg_msg_received_assert_int_d,
+ cfg_msg_received_deassert_int_a,
+ cfg_msg_received_deassert_int_b,
+ cfg_msg_received_deassert_int_c,
+ cfg_msg_received_deassert_int_d,
+ cfg_msg_received_setslotpowerlimit,
+ pl_directed_link_change,
+ pl_directed_link_width,
+ pl_directed_link_speed,
+ pl_directed_link_auton,
+ pl_upstream_prefer_deemph,
+ pl_sel_lnk_rate,
+ pl_sel_lnk_width,
+ pl_ltssm_state,
+ pl_lane_reversal_mode,
+ pl_phy_lnk_up,
+ pl_tx_pm_state,
+ pl_rx_pm_state,
+ pl_link_upcfg_cap,
+ pl_link_gen2_cap,
+ pl_link_partner_gen2_supported,
+ pl_initial_link_width,
+ pl_directed_change_done,
+ pl_received_hot_rst,
+ pl_transmit_hot_rst,
+ pl_downstream_deemph_source,
+ cfg_err_aer_headerlog,
+ cfg_aer_interrupt_msgnum,
+ cfg_err_aer_headerlog_set,
+ cfg_aer_ecrc_check_en,
+ cfg_aer_ecrc_gen_en,
+ cfg_vc_tcvc_map,
+ sys_clk,
+ sys_rst_n,
+ pipe_mmcm_rst_n,
+ pcie_drp_clk,
+ pcie_drp_en,
+ pcie_drp_we,
+ pcie_drp_addr,
+ pcie_drp_di,
+ pcie_drp_do,
+ pcie_drp_rdy);
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txp" *) output [3:0]pci_exp_txp;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txn" *) output [3:0]pci_exp_txn;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxp" *) input [3:0]pci_exp_rxp;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxn" *) input [3:0]pci_exp_rxn;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock pclk_in" *) input pipe_pclk_in;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxusrclk_in" *) input pipe_rxusrclk_in;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxoutclk_in" *) input [3:0]pipe_rxoutclk_in;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock dclk_in" *) input pipe_dclk_in;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock userclk1_in" *) input pipe_userclk1_in;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock userclk2_in" *) input pipe_userclk2_in;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock oobclk_in" *) input pipe_oobclk_in;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock mmcm_lock_in" *) input pipe_mmcm_lock_in;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock txoutclk_out" *) output pipe_txoutclk_out;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock rxoutclk_out" *) output [3:0]pipe_rxoutclk_out;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock pclk_sel_out" *) output [3:0]pipe_pclk_sel_out;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock gen3_out" *) output pipe_gen3_out;
+ (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.user_clk_out CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.user_clk_out, ASSOCIATED_BUSIF m_axis_rx:s_axis_tx, FREQ_HZ 125000000, ASSOCIATED_RESET user_reset_out, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) output user_clk_out;
+ (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.user_reset_out RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.user_reset_out, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) output user_reset_out;
+ output user_lnk_up;
+ output user_app_rdy;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_buf_av" *) output [5:0]tx_buf_av;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_cfg_req" *) output tx_cfg_req;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_err_drop" *) output tx_err_drop;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TREADY" *) output s_axis_tx_tready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TDATA" *) input [63:0]s_axis_tx_tdata;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TKEEP" *) input [7:0]s_axis_tx_tkeep;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TLAST" *) input s_axis_tx_tlast;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TVALID" *) input s_axis_tx_tvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TUSER" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axis_tx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) input [3:0]s_axis_tx_tuser;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control tx_cfg_gnt" *) input tx_cfg_gnt;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TDATA" *) output [63:0]m_axis_rx_tdata;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TKEEP" *) output [7:0]m_axis_rx_tkeep;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TLAST" *) output m_axis_rx_tlast;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TVALID" *) output m_axis_rx_tvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TREADY" *) input m_axis_rx_tready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TUSER" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis_rx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) output [21:0]m_axis_rx_tuser;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_ok" *) input rx_np_ok;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_req" *) input rx_np_req;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLD" *) output [11:0]fc_cpld;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLH" *) output [7:0]fc_cplh;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPD" *) output [11:0]fc_npd;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPH" *) output [7:0]fc_nph;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PD" *) output [11:0]fc_pd;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PH" *) output [7:0]fc_ph;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc SEL" *) input [2:0]fc_sel;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_DATA" *) output [31:0]cfg_mgmt_do;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_WRITE_DONE" *) output cfg_mgmt_rd_wr_done;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status status" *) output [15:0]cfg_status;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status command" *) output [15:0]cfg_command;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dstatus" *) output [15:0]cfg_dstatus;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand" *) output [15:0]cfg_dcommand;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lstatus" *) output [15:0]cfg_lstatus;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lcommand" *) output [15:0]cfg_lcommand;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand2" *) output [15:0]cfg_dcommand2;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pcie_link_state" *) output [2:0]cfg_pcie_link_state;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_en" *) output cfg_pmcsr_pme_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_powerstate" *) output [1:0]cfg_pmcsr_powerstate;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_status" *) output cfg_pmcsr_pme_status;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status received_func_lvl_rst" *) output cfg_received_func_lvl_rst;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_DATA" *) input [31:0]cfg_mgmt_di;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt BYTE_EN" *) input [3:0]cfg_mgmt_byte_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt ADDR" *) input [9:0]cfg_mgmt_dwaddr;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_EN" *) input cfg_mgmt_wr_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_EN" *) input cfg_mgmt_rd_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READONLY" *) input cfg_mgmt_wr_readonly;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ecrc" *) input cfg_err_ecrc;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ur" *) input cfg_err_ur;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_timeout" *) input cfg_err_cpl_timeout;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_unexpect" *) input cfg_err_cpl_unexpect;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_abort" *) input cfg_err_cpl_abort;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err posted" *) input cfg_err_posted;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cor" *) input cfg_err_cor;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err atomic_egress_blocked" *) input cfg_err_atomic_egress_blocked;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_cor" *) input cfg_err_internal_cor;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err malformed" *) input cfg_err_malformed;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err mc_blocked" *) input cfg_err_mc_blocked;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err poisoned" *) input cfg_err_poisoned;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err norecovery" *) input cfg_err_norecovery;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err tlp_cpl_header" *) input [47:0]cfg_err_tlp_cpl_header;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_rdy" *) output cfg_err_cpl_rdy;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err locked" *) input cfg_err_locked;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err acs" *) input cfg_err_acs;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_uncor" *) input cfg_err_internal_uncor;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control trn_pending" *) input cfg_trn_pending;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l0s" *) input cfg_pm_halt_aspm_l0s;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l1" *) input cfg_pm_halt_aspm_l1;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state_en" *) input cfg_pm_force_state_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state" *) input [1:0]cfg_pm_force_state;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control dsn" *) input [63:0]cfg_dsn;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt interrupt" *) input cfg_interrupt;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt rdy" *) output cfg_interrupt_rdy;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt assert" *) input cfg_interrupt_assert;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt write_data" *) input [7:0]cfg_interrupt_di;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt read_data" *) output [7:0]cfg_interrupt_do;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt mmenable" *) output [2:0]cfg_interrupt_mmenable;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msienable" *) output cfg_interrupt_msienable;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixenable" *) output cfg_interrupt_msixenable;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixfm" *) output cfg_interrupt_msixfm;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt stat" *) input cfg_interrupt_stat;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt pciecap_interrupt_msgnum" *) input [4:0]cfg_pciecap_interrupt_msgnum;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status turnoff" *) output cfg_to_turnoff;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control turnoff_ok" *) input cfg_turnoff_ok;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bus_number" *) output [7:0]cfg_bus_number;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status device_number" *) output [4:0]cfg_device_number;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status function_number" *) output [2:0]cfg_function_number;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_wake" *) input cfg_pm_wake;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_send_pme_to" *) input cfg_pm_send_pme_to;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_bus_number" *) input [7:0]cfg_ds_bus_number;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_device_number" *) input [4:0]cfg_ds_device_number;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_function_number" *) input [2:0]cfg_ds_function_number;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt TYPE1_CFG_REG_ACCESS" *) input cfg_mgmt_wr_rw1c_as_rw;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received" *) output cfg_msg_received;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd data" *) output [15:0]cfg_msg_data;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bridge_serr_en" *) output cfg_bridge_serr_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status slot_control_electromech_il_ctl_pulse" *) output cfg_slot_control_electromech_il_ctl_pulse;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_corr_err_en" *) output cfg_root_control_syserr_corr_err_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_non_fatal_err_en" *) output cfg_root_control_syserr_non_fatal_err_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_fatal_err_en" *) output cfg_root_control_syserr_fatal_err_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_pme_int_en" *) output cfg_root_control_pme_int_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_reporting_en" *) output cfg_aer_rooterr_corr_err_reporting_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_reporting_en" *) output cfg_aer_rooterr_non_fatal_err_reporting_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_reporting_en" *) output cfg_aer_rooterr_fatal_err_reporting_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_received" *) output cfg_aer_rooterr_corr_err_received;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_received" *) output cfg_aer_rooterr_non_fatal_err_received;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_received" *) output cfg_aer_rooterr_fatal_err_received;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_cor" *) output cfg_msg_received_err_cor;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_non_fatal" *) output cfg_msg_received_err_non_fatal;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_fatal" *) output cfg_msg_received_err_fatal;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_pm_as_nak" *) output cfg_msg_received_pm_as_nak;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pm_pme" *) output cfg_msg_received_pm_pme;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pme_to_ack" *) output cfg_msg_received_pme_to_ack;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_a" *) output cfg_msg_received_assert_int_a;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_b" *) output cfg_msg_received_assert_int_b;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_c" *) output cfg_msg_received_assert_int_c;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_d" *) output cfg_msg_received_assert_int_d;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_a" *) output cfg_msg_received_deassert_int_a;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_b" *) output cfg_msg_received_deassert_int_b;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_c" *) output cfg_msg_received_deassert_int_c;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_d" *) output cfg_msg_received_deassert_int_d;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_setslotpowerlimit" *) output cfg_msg_received_setslotpowerlimit;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_change" *) input [1:0]pl_directed_link_change;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_width" *) input [1:0]pl_directed_link_width;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_speed" *) input pl_directed_link_speed;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_auton" *) input pl_directed_link_auton;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl upstream_prefer_deemph" *) input pl_upstream_prefer_deemph;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_rate" *) output pl_sel_lnk_rate;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_width" *) output [1:0]pl_sel_lnk_width;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl ltssm_state" *) output [5:0]pl_ltssm_state;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl lane_reversal_mode" *) output [1:0]pl_lane_reversal_mode;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl phy_lnk_up" *) output pl_phy_lnk_up;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl tx_pm_state" *) output [2:0]pl_tx_pm_state;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl rx_pm_state" *) output [1:0]pl_rx_pm_state;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_upcfg_cap" *) output pl_link_upcfg_cap;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_gen2_cap" *) output pl_link_gen2_cap;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_partner_gen2_supported" *) output pl_link_partner_gen2_supported;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl initial_link_width" *) output [2:0]pl_initial_link_width;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_change_done" *) output pl_directed_change_done;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl received_hot_rst" *) output pl_received_hot_rst;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl transmit_hot_rst" *) input pl_transmit_hot_rst;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl downstream_deemph_source" *) input pl_downstream_deemph_source;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog" *) input [127:0]cfg_err_aer_headerlog;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_interrupt_msgnum" *) input [4:0]cfg_aer_interrupt_msgnum;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog_set" *) output cfg_err_aer_headerlog_set;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_check_en" *) output cfg_aer_ecrc_check_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_gen_en" *) output cfg_aer_ecrc_gen_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status vc_tcvc_map" *) output [6:0]cfg_vc_tcvc_map;
+ (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.sys_clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.sys_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) input sys_clk;
+ (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.sys_rst_n RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.sys_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input sys_rst_n;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:pipe_clock:1.0 pipe_clock mmcm_rst_n" *) input pipe_mmcm_rst_n;
+ input pcie_drp_clk;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DEN" *) input pcie_drp_en;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DWE" *) input pcie_drp_we;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DADDR" *) input [8:0]pcie_drp_addr;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DI" *) input [15:0]pcie_drp_di;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DO" *) output [15:0]pcie_drp_do;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DRDY" *) output pcie_drp_rdy;
+
+ wire \ ;
+ wire \ ;
+ wire cfg_aer_ecrc_check_en;
+ wire cfg_aer_ecrc_gen_en;
+ wire [4:0]cfg_aer_interrupt_msgnum;
+ wire cfg_aer_rooterr_corr_err_received;
+ wire cfg_aer_rooterr_corr_err_reporting_en;
+ wire cfg_aer_rooterr_fatal_err_received;
+ wire cfg_aer_rooterr_fatal_err_reporting_en;
+ wire cfg_aer_rooterr_non_fatal_err_received;
+ wire cfg_aer_rooterr_non_fatal_err_reporting_en;
+ wire cfg_bridge_serr_en;
+ wire [7:0]cfg_bus_number;
+ wire [10:0]\^cfg_command ;
+ wire [14:0]\^cfg_dcommand ;
+ wire [11:0]\^cfg_dcommand2 ;
+ wire [4:0]cfg_device_number;
+ wire [7:0]cfg_ds_bus_number;
+ wire [4:0]cfg_ds_device_number;
+ wire [2:0]cfg_ds_function_number;
+ wire [63:0]cfg_dsn;
+ wire [5:0]\^cfg_dstatus ;
+ wire [127:0]cfg_err_aer_headerlog;
+ wire cfg_err_aer_headerlog_set;
+ wire cfg_err_atomic_egress_blocked;
+ wire cfg_err_cor;
+ wire cfg_err_cpl_abort;
+ wire cfg_err_cpl_rdy;
+ wire cfg_err_cpl_timeout;
+ wire cfg_err_cpl_unexpect;
+ wire cfg_err_ecrc;
+ wire cfg_err_internal_cor;
+ wire cfg_err_internal_uncor;
+ wire cfg_err_locked;
+ wire cfg_err_malformed;
+ wire cfg_err_mc_blocked;
+ wire cfg_err_norecovery;
+ wire cfg_err_poisoned;
+ wire cfg_err_posted;
+ wire [47:0]cfg_err_tlp_cpl_header;
+ wire cfg_err_ur;
+ wire [2:0]cfg_function_number;
+ wire cfg_interrupt;
+ wire cfg_interrupt_assert;
+ wire [7:0]cfg_interrupt_di;
+ wire [7:0]cfg_interrupt_do;
+ wire [2:0]cfg_interrupt_mmenable;
+ wire cfg_interrupt_msienable;
+ wire cfg_interrupt_msixenable;
+ wire cfg_interrupt_msixfm;
+ wire cfg_interrupt_rdy;
+ wire cfg_interrupt_stat;
+ wire [11:0]\^cfg_lcommand ;
+ wire [15:0]\^cfg_lstatus ;
+ wire [3:0]cfg_mgmt_byte_en;
+ wire [31:0]cfg_mgmt_di;
+ wire [31:0]cfg_mgmt_do;
+ wire [9:0]cfg_mgmt_dwaddr;
+ wire cfg_mgmt_rd_en;
+ wire cfg_mgmt_rd_wr_done;
+ wire cfg_mgmt_wr_en;
+ wire cfg_mgmt_wr_readonly;
+ wire cfg_mgmt_wr_rw1c_as_rw;
+ wire [15:0]cfg_msg_data;
+ wire cfg_msg_received;
+ wire cfg_msg_received_assert_int_a;
+ wire cfg_msg_received_assert_int_b;
+ wire cfg_msg_received_assert_int_c;
+ wire cfg_msg_received_assert_int_d;
+ wire cfg_msg_received_deassert_int_a;
+ wire cfg_msg_received_deassert_int_b;
+ wire cfg_msg_received_deassert_int_c;
+ wire cfg_msg_received_deassert_int_d;
+ wire cfg_msg_received_err_cor;
+ wire cfg_msg_received_err_fatal;
+ wire cfg_msg_received_err_non_fatal;
+ wire cfg_msg_received_pm_as_nak;
+ wire cfg_msg_received_pm_pme;
+ wire cfg_msg_received_pme_to_ack;
+ wire cfg_msg_received_setslotpowerlimit;
+ wire [2:0]cfg_pcie_link_state;
+ wire [4:0]cfg_pciecap_interrupt_msgnum;
+ wire [1:0]cfg_pm_force_state;
+ wire cfg_pm_force_state_en;
+ wire cfg_pm_halt_aspm_l0s;
+ wire cfg_pm_halt_aspm_l1;
+ wire cfg_pm_wake;
+ wire cfg_pmcsr_pme_en;
+ wire cfg_pmcsr_pme_status;
+ wire [1:0]cfg_pmcsr_powerstate;
+ wire cfg_received_func_lvl_rst;
+ wire cfg_root_control_pme_int_en;
+ wire cfg_root_control_syserr_corr_err_en;
+ wire cfg_root_control_syserr_fatal_err_en;
+ wire cfg_root_control_syserr_non_fatal_err_en;
+ wire cfg_slot_control_electromech_il_ctl_pulse;
+ wire cfg_to_turnoff;
+ wire cfg_trn_pending;
+ wire cfg_turnoff_ok;
+ wire [6:0]cfg_vc_tcvc_map;
+ wire [11:0]fc_cpld;
+ wire [7:0]fc_cplh;
+ wire [11:0]fc_npd;
+ wire [7:0]fc_nph;
+ wire [11:0]fc_pd;
+ wire [7:0]fc_ph;
+ wire [2:0]fc_sel;
+ wire [63:0]m_axis_rx_tdata;
+ wire [7:4]\^m_axis_rx_tkeep ;
+ wire m_axis_rx_tlast;
+ wire m_axis_rx_tready;
+ wire [21:0]\^m_axis_rx_tuser ;
+ wire m_axis_rx_tvalid;
+ wire [3:0]pci_exp_rxn;
+ wire [3:0]pci_exp_rxp;
+ wire [3:0]pci_exp_txn;
+ wire [3:0]pci_exp_txp;
+ wire [8:0]pcie_drp_addr;
+ wire pcie_drp_clk;
+ wire [15:0]pcie_drp_di;
+ wire [15:0]pcie_drp_do;
+ wire pcie_drp_en;
+ wire pcie_drp_rdy;
+ wire pcie_drp_we;
+ wire pipe_dclk_in;
+ wire pipe_gen3_out;
+ wire pipe_mmcm_lock_in;
+ wire pipe_oobclk_in;
+ wire pipe_pclk_in;
+ wire [3:0]pipe_pclk_sel_out;
+ wire [3:0]pipe_rxoutclk_out;
+ wire pipe_rxusrclk_in;
+ wire pipe_txoutclk_out;
+ wire pipe_userclk1_in;
+ wire pipe_userclk2_in;
+ wire pl_directed_change_done;
+ wire pl_directed_link_auton;
+ wire [1:0]pl_directed_link_change;
+ wire pl_directed_link_speed;
+ wire [1:0]pl_directed_link_width;
+ wire pl_downstream_deemph_source;
+ wire [2:0]pl_initial_link_width;
+ wire [1:0]pl_lane_reversal_mode;
+ wire pl_link_gen2_cap;
+ wire pl_link_partner_gen2_supported;
+ wire pl_link_upcfg_cap;
+ wire [5:0]pl_ltssm_state;
+ wire pl_phy_lnk_up;
+ wire pl_received_hot_rst;
+ wire [1:0]pl_rx_pm_state;
+ wire pl_sel_lnk_rate;
+ wire [1:0]pl_sel_lnk_width;
+ wire pl_transmit_hot_rst;
+ wire [2:0]pl_tx_pm_state;
+ wire pl_upstream_prefer_deemph;
+ wire rx_np_ok;
+ wire rx_np_req;
+ wire [63:0]s_axis_tx_tdata;
+ wire [7:0]s_axis_tx_tkeep;
+ wire s_axis_tx_tlast;
+ wire s_axis_tx_tready;
+ wire [3:0]s_axis_tx_tuser;
+ wire s_axis_tx_tvalid;
+ wire sys_clk;
+ wire sys_rst_n;
+ wire [5:0]tx_buf_av;
+ wire tx_cfg_gnt;
+ wire tx_cfg_req;
+ wire tx_err_drop;
+ wire user_clk_out;
+ wire user_lnk_up;
+ wire user_reset_out;
+ wire NLW_inst_ext_ch_gt_drpclk_UNCONNECTED;
+ wire NLW_inst_int_dclk_out_UNCONNECTED;
+ wire NLW_inst_int_mmcm_lock_out_UNCONNECTED;
+ wire NLW_inst_int_oobclk_out_UNCONNECTED;
+ wire NLW_inst_int_pclk_out_slave_UNCONNECTED;
+ wire NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED;
+ wire NLW_inst_int_userclk1_out_UNCONNECTED;
+ wire NLW_inst_int_userclk2_out_UNCONNECTED;
+ wire NLW_inst_pipe_qrst_idle_UNCONNECTED;
+ wire NLW_inst_pipe_rate_idle_UNCONNECTED;
+ wire NLW_inst_pipe_rst_idle_UNCONNECTED;
+ wire NLW_inst_qpll_drp_clk_UNCONNECTED;
+ wire NLW_inst_qpll_drp_gen3_UNCONNECTED;
+ wire NLW_inst_qpll_drp_ovrd_UNCONNECTED;
+ wire NLW_inst_qpll_drp_rst_n_UNCONNECTED;
+ wire NLW_inst_qpll_drp_start_UNCONNECTED;
+ wire NLW_inst_qpll_qplld_UNCONNECTED;
+ wire NLW_inst_startup_cfgclk_UNCONNECTED;
+ wire NLW_inst_startup_cfgmclk_UNCONNECTED;
+ wire NLW_inst_startup_eos_UNCONNECTED;
+ wire NLW_inst_startup_preq_UNCONNECTED;
+ wire NLW_inst_user_app_rdy_UNCONNECTED;
+ wire [15:3]NLW_inst_cfg_command_UNCONNECTED;
+ wire [15:15]NLW_inst_cfg_dcommand_UNCONNECTED;
+ wire [15:12]NLW_inst_cfg_dcommand2_UNCONNECTED;
+ wire [15:4]NLW_inst_cfg_dstatus_UNCONNECTED;
+ wire [15:2]NLW_inst_cfg_lcommand_UNCONNECTED;
+ wire [12:2]NLW_inst_cfg_lstatus_UNCONNECTED;
+ wire [15:0]NLW_inst_cfg_status_UNCONNECTED;
+ wire [11:0]NLW_inst_common_commands_out_UNCONNECTED;
+ wire [63:0]NLW_inst_ext_ch_gt_drpdo_UNCONNECTED;
+ wire [3:0]NLW_inst_ext_ch_gt_drprdy_UNCONNECTED;
+ wire [3:0]NLW_inst_gt_ch_drp_rdy_UNCONNECTED;
+ wire [31:0]NLW_inst_icap_o_UNCONNECTED;
+ wire [1:0]NLW_inst_int_qplllock_out_UNCONNECTED;
+ wire [1:0]NLW_inst_int_qplloutclk_out_UNCONNECTED;
+ wire [1:0]NLW_inst_int_qplloutrefclk_out_UNCONNECTED;
+ wire [3:0]NLW_inst_int_rxoutclk_out_UNCONNECTED;
+ wire [3:0]NLW_inst_m_axis_rx_tkeep_UNCONNECTED;
+ wire [20:9]NLW_inst_m_axis_rx_tuser_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_cpll_lock_UNCONNECTED;
+ wire [31:0]NLW_inst_pipe_debug_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_debug_0_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_debug_1_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_debug_2_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_debug_3_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_debug_4_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_debug_5_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_debug_6_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_debug_7_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_debug_8_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_debug_9_UNCONNECTED;
+ wire [59:0]NLW_inst_pipe_dmonitorout_UNCONNECTED;
+ wire [27:0]NLW_inst_pipe_drp_fsm_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_eyescandataerror_UNCONNECTED;
+ wire [0:0]NLW_inst_pipe_qpll_lock_UNCONNECTED;
+ wire [11:0]NLW_inst_pipe_qrst_fsm_UNCONNECTED;
+ wire [19:0]NLW_inst_pipe_rate_fsm_UNCONNECTED;
+ wire [4:0]NLW_inst_pipe_rst_fsm_UNCONNECTED;
+ wire [11:0]NLW_inst_pipe_rxbufstatus_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_rxcommadet_UNCONNECTED;
+ wire [31:0]NLW_inst_pipe_rxdisperr_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_rxdlysresetdone_UNCONNECTED;
+ wire [31:0]NLW_inst_pipe_rxnotintable_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_rxphaligndone_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_rxpmaresetdone_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_rxprbserr_UNCONNECTED;
+ wire [11:0]NLW_inst_pipe_rxstatus_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_rxsyncdone_UNCONNECTED;
+ wire [27:0]NLW_inst_pipe_sync_fsm_rx_UNCONNECTED;
+ wire [23:0]NLW_inst_pipe_sync_fsm_tx_UNCONNECTED;
+ wire [24:0]NLW_inst_pipe_tx_0_sigs_UNCONNECTED;
+ wire [24:0]NLW_inst_pipe_tx_1_sigs_UNCONNECTED;
+ wire [24:0]NLW_inst_pipe_tx_2_sigs_UNCONNECTED;
+ wire [24:0]NLW_inst_pipe_tx_3_sigs_UNCONNECTED;
+ wire [24:0]NLW_inst_pipe_tx_4_sigs_UNCONNECTED;
+ wire [24:0]NLW_inst_pipe_tx_5_sigs_UNCONNECTED;
+ wire [24:0]NLW_inst_pipe_tx_6_sigs_UNCONNECTED;
+ wire [24:0]NLW_inst_pipe_tx_7_sigs_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_txdlysresetdone_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_txphaligndone_UNCONNECTED;
+ wire [3:0]NLW_inst_pipe_txphinitdone_UNCONNECTED;
+ wire [1:0]NLW_inst_qpll_qpllreset_UNCONNECTED;
+
+ assign cfg_command[15] = \ ;
+ assign cfg_command[14] = \ ;
+ assign cfg_command[13] = \ ;
+ assign cfg_command[12] = \ ;
+ assign cfg_command[11] = \ ;
+ assign cfg_command[10] = \^cfg_command [10];
+ assign cfg_command[9] = \ ;
+ assign cfg_command[8] = \^cfg_command [8];
+ assign cfg_command[7] = \ ;
+ assign cfg_command[6] = \ ;
+ assign cfg_command[5] = \ ;
+ assign cfg_command[4] = \ ;
+ assign cfg_command[3] = \ ;
+ assign cfg_command[2:0] = \^cfg_command [2:0];
+ assign cfg_dcommand[15] = \ ;
+ assign cfg_dcommand[14:0] = \^cfg_dcommand [14:0];
+ assign cfg_dcommand2[15] = \ ;
+ assign cfg_dcommand2[14] = \ ;
+ assign cfg_dcommand2[13] = \ ;
+ assign cfg_dcommand2[12] = \ ;
+ assign cfg_dcommand2[11:0] = \^cfg_dcommand2 [11:0];
+ assign cfg_dstatus[15] = \ ;
+ assign cfg_dstatus[14] = \ ;
+ assign cfg_dstatus[13] = \ ;
+ assign cfg_dstatus[12] = \ ;
+ assign cfg_dstatus[11] = \ ;
+ assign cfg_dstatus[10] = \ ;
+ assign cfg_dstatus[9] = \ ;
+ assign cfg_dstatus[8] = \ ;
+ assign cfg_dstatus[7] = \ ;
+ assign cfg_dstatus[6] = \ ;
+ assign cfg_dstatus[5] = \^cfg_dstatus [5];
+ assign cfg_dstatus[4] = \ ;
+ assign cfg_dstatus[3:0] = \^cfg_dstatus [3:0];
+ assign cfg_lcommand[15] = \ ;
+ assign cfg_lcommand[14] = \ ;
+ assign cfg_lcommand[13] = \ ;
+ assign cfg_lcommand[12] = \ ;
+ assign cfg_lcommand[11:3] = \^cfg_lcommand [11:3];
+ assign cfg_lcommand[2] = \ ;
+ assign cfg_lcommand[1:0] = \^cfg_lcommand [1:0];
+ assign cfg_lstatus[15:13] = \^cfg_lstatus [15:13];
+ assign cfg_lstatus[12] = \ ;
+ assign cfg_lstatus[11] = \^cfg_lstatus [11];
+ assign cfg_lstatus[10] = \ ;
+ assign cfg_lstatus[9] = \ ;
+ assign cfg_lstatus[8] = \ ;
+ assign cfg_lstatus[7:4] = \^cfg_lstatus [7:4];
+ assign cfg_lstatus[3] = \ ;
+ assign cfg_lstatus[2] = \ ;
+ assign cfg_lstatus[1:0] = \^cfg_lstatus [1:0];
+ assign cfg_status[15] = \ ;
+ assign cfg_status[14] = \ ;
+ assign cfg_status[13] = \ ;
+ assign cfg_status[12] = \ ;
+ assign cfg_status[11] = \ ;
+ assign cfg_status[10] = \ ;
+ assign cfg_status[9] = \ ;
+ assign cfg_status[8] = \ ;
+ assign cfg_status[7] = \ ;
+ assign cfg_status[6] = \ ;
+ assign cfg_status[5] = \ ;
+ assign cfg_status[4] = \ ;
+ assign cfg_status[3] = \ ;
+ assign cfg_status[2] = \ ;
+ assign cfg_status[1] = \ ;
+ assign cfg_status[0] = \ ;
+ assign m_axis_rx_tkeep[7:4] = \^m_axis_rx_tkeep [7:4];
+ assign m_axis_rx_tkeep[3] = \ ;
+ assign m_axis_rx_tkeep[2] = \ ;
+ assign m_axis_rx_tkeep[1] = \ ;
+ assign m_axis_rx_tkeep[0] = \ ;
+ assign m_axis_rx_tuser[21] = \^m_axis_rx_tuser [21];
+ assign m_axis_rx_tuser[20] = \ ;
+ assign m_axis_rx_tuser[19:17] = \^m_axis_rx_tuser [19:17];
+ assign m_axis_rx_tuser[16] = \ ;
+ assign m_axis_rx_tuser[15] = \ ;
+ assign m_axis_rx_tuser[14] = \^m_axis_rx_tuser [14];
+ assign m_axis_rx_tuser[13] = \ ;
+ assign m_axis_rx_tuser[12] = \ ;
+ assign m_axis_rx_tuser[11] = \ ;
+ assign m_axis_rx_tuser[10] = \ ;
+ assign m_axis_rx_tuser[9] = \ ;
+ assign m_axis_rx_tuser[8:0] = \^m_axis_rx_tuser [8:0];
+ assign user_app_rdy = \ ;
+ GND GND
+ (.G(\ ));
+ VCC VCC
+ (.P(\ ));
+ (* CFG_CTL_IF = "TRUE" *)
+ (* CFG_FC_IF = "TRUE" *)
+ (* CFG_MGMT_IF = "TRUE" *)
+ (* CFG_STATUS_IF = "TRUE" *)
+ (* CLASS_CODE = "050000" *)
+ (* C_DATA_WIDTH = "64" *)
+ (* DowngradeIPIdentifiedWarnings = "yes" *)
+ (* ENABLE_JTAG_DBG = "FALSE" *)
+ (* ERR_REPORTING_IF = "TRUE" *)
+ (* EXT_CH_GT_DRP = "FALSE" *)
+ (* EXT_PIPE_INTERFACE = "FALSE" *)
+ (* EXT_STARTUP_PRIMITIVE = "FALSE" *)
+ (* KEEP_WIDTH = "8" *)
+ (* LINK_CAP_MAX_LINK_WIDTH = "4" *)
+ (* PCIE_ASYNC_EN = "FALSE" *)
+ (* PCIE_EXT_CLK = "TRUE" *)
+ (* PCIE_EXT_GT_COMMON = "FALSE" *)
+ (* PIPE_SIM = "FALSE" *)
+ (* PL_INTERFACE = "TRUE" *)
+ (* RCV_MSG_IF = "TRUE" *)
+ (* REDUCE_OOB_FREQ = "FALSE" *)
+ (* SHARED_LOGIC_IN_CORE = "FALSE" *)
+ (* TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE" *)
+ (* bar_0 = "FFFF0000" *)
+ (* bar_1 = "00000000" *)
+ (* bar_2 = "00000000" *)
+ (* bar_3 = "00000000" *)
+ (* bar_4 = "00000000" *)
+ (* bar_5 = "00000000" *)
+ (* bram_lat = "0" *)
+ (* c_aer_base_ptr = "000" *)
+ (* c_aer_cap_ecrc_check_capable = "FALSE" *)
+ (* c_aer_cap_ecrc_gen_capable = "FALSE" *)
+ (* c_aer_cap_multiheader = "FALSE" *)
+ (* c_aer_cap_nextptr = "000" *)
+ (* c_aer_cap_on = "FALSE" *)
+ (* c_aer_cap_optional_err_support = "000000" *)
+ (* c_aer_cap_permit_rooterr_update = "FALSE" *)
+ (* c_buf_opt_bma = "TRUE" *)
+ (* c_component_name = "pcie_7x_0" *)
+ (* c_cpl_inf = "TRUE" *)
+ (* c_cpl_infinite = "TRUE" *)
+ (* c_cpl_timeout_disable_sup = "FALSE" *)
+ (* c_cpl_timeout_range = "0010" *)
+ (* c_cpl_timeout_ranges_sup = "2" *)
+ (* c_d1_support = "FALSE" *)
+ (* c_d2_support = "FALSE" *)
+ (* c_de_emph = "FALSE" *)
+ (* c_dev_cap2_ari_forwarding_supported = "FALSE" *)
+ (* c_dev_cap2_atomicop32_completer_supported = "FALSE" *)
+ (* c_dev_cap2_atomicop64_completer_supported = "FALSE" *)
+ (* c_dev_cap2_atomicop_routing_supported = "FALSE" *)
+ (* c_dev_cap2_cas128_completer_supported = "FALSE" *)
+ (* c_dev_cap2_tph_completer_supported = "00" *)
+ (* c_dev_control_ext_tag_default = "FALSE" *)
+ (* c_dev_port_type = "0" *)
+ (* c_dis_lane_reverse = "TRUE" *)
+ (* c_disable_rx_poisoned_resp = "FALSE" *)
+ (* c_disable_scrambling = "FALSE" *)
+ (* c_disable_tx_aspm_l0s = "FALSE" *)
+ (* c_dll_lnk_actv_cap = "FALSE" *)
+ (* c_dsi_bool = "FALSE" *)
+ (* c_dsn_base_ptr = "100" *)
+ (* c_dsn_cap_enabled = "TRUE" *)
+ (* c_dsn_next_ptr = "000" *)
+ (* c_enable_msg_route = "00000000000" *)
+ (* c_ep_l0s_accpt_lat = "0" *)
+ (* c_ep_l1_accpt_lat = "7" *)
+ (* c_ext_pci_cfg_space_addr = "3FF" *)
+ (* c_external_clocking = "TRUE" *)
+ (* c_fc_cpld = "973" *)
+ (* c_fc_cplh = "36" *)
+ (* c_fc_npd = "24" *)
+ (* c_fc_nph = "12" *)
+ (* c_fc_pd = "949" *)
+ (* c_fc_ph = "32" *)
+ (* c_gen1 = "1'b1" *)
+ (* c_header_type = "00" *)
+ (* c_hw_auton_spd_disable = "FALSE" *)
+ (* c_int_width = "64" *)
+ (* c_last_cfg_dw = "10C" *)
+ (* c_link_cap_aspm_optionality = "FALSE" *)
+ (* c_ll_ack_timeout = "0000" *)
+ (* c_ll_ack_timeout_enable = "FALSE" *)
+ (* c_ll_ack_timeout_function = "0" *)
+ (* c_ll_replay_timeout = "0000" *)
+ (* c_ll_replay_timeout_enable = "FALSE" *)
+ (* c_ll_replay_timeout_func = "1" *)
+ (* c_lnk_bndwdt_notif = "FALSE" *)
+ (* c_msi = "0" *)
+ (* c_msi_64b_addr = "TRUE" *)
+ (* c_msi_cap_on = "FALSE" *)
+ (* c_msi_mult_msg_extn = "0" *)
+ (* c_msi_per_vctr_mask_cap = "FALSE" *)
+ (* c_msix_cap_on = "FALSE" *)
+ (* c_msix_next_ptr = "00" *)
+ (* c_msix_pba_bir = "0" *)
+ (* c_msix_pba_offset = "0" *)
+ (* c_msix_table_bir = "0" *)
+ (* c_msix_table_offset = "0" *)
+ (* c_msix_table_size = "000" *)
+ (* c_pci_cfg_space_addr = "3F" *)
+ (* c_pcie_blk_locn = "0" *)
+ (* c_pcie_cap_next_ptr = "00" *)
+ (* c_pcie_cap_slot_implemented = "FALSE" *)
+ (* c_pcie_dbg_ports = "TRUE" *)
+ (* c_pcie_fast_config = "0" *)
+ (* c_perf_level_high = "TRUE" *)
+ (* c_phantom_functions = "0" *)
+ (* c_pm_cap_next_ptr = "60" *)
+ (* c_pme_support = "0F" *)
+ (* c_rbar_base_ptr = "000" *)
+ (* c_rbar_cap_control_encodedbar0 = "00" *)
+ (* c_rbar_cap_control_encodedbar1 = "00" *)
+ (* c_rbar_cap_control_encodedbar2 = "00" *)
+ (* c_rbar_cap_control_encodedbar3 = "00" *)
+ (* c_rbar_cap_control_encodedbar4 = "00" *)
+ (* c_rbar_cap_control_encodedbar5 = "00" *)
+ (* c_rbar_cap_index0 = "0" *)
+ (* c_rbar_cap_index1 = "0" *)
+ (* c_rbar_cap_index2 = "0" *)
+ (* c_rbar_cap_index3 = "0" *)
+ (* c_rbar_cap_index4 = "0" *)
+ (* c_rbar_cap_index5 = "0" *)
+ (* c_rbar_cap_nextptr = "000" *)
+ (* c_rbar_cap_on = "FALSE" *)
+ (* c_rbar_cap_sup0 = "00001" *)
+ (* c_rbar_cap_sup1 = "00001" *)
+ (* c_rbar_cap_sup2 = "00001" *)
+ (* c_rbar_cap_sup3 = "00001" *)
+ (* c_rbar_cap_sup4 = "00001" *)
+ (* c_rbar_cap_sup5 = "00001" *)
+ (* c_rbar_num = "0" *)
+ (* c_rcb = "0" *)
+ (* c_recrc_check = "0" *)
+ (* c_recrc_check_trim = "FALSE" *)
+ (* c_rev_gt_order = "FALSE" *)
+ (* c_root_cap_crs = "FALSE" *)
+ (* c_rx_raddr_lat = "0" *)
+ (* c_rx_ram_limit = "FFF" *)
+ (* c_rx_rdata_lat = "2" *)
+ (* c_rx_write_lat = "0" *)
+ (* c_silicon_rev = "2" *)
+ (* c_slot_cap_attn_butn = "FALSE" *)
+ (* c_slot_cap_attn_ind = "FALSE" *)
+ (* c_slot_cap_elec_interlock = "FALSE" *)
+ (* c_slot_cap_hotplug_cap = "FALSE" *)
+ (* c_slot_cap_hotplug_surprise = "FALSE" *)
+ (* c_slot_cap_mrl = "FALSE" *)
+ (* c_slot_cap_no_cmd_comp_sup = "FALSE" *)
+ (* c_slot_cap_physical_slot_num = "0" *)
+ (* c_slot_cap_pwr_ctrl = "FALSE" *)
+ (* c_slot_cap_pwr_ind = "FALSE" *)
+ (* c_slot_cap_pwr_limit_scale = "0" *)
+ (* c_slot_cap_pwr_limit_value = "0" *)
+ (* c_surprise_dn_err_cap = "FALSE" *)
+ (* c_trgt_lnk_spd = "2" *)
+ (* c_trn_np_fc = "TRUE" *)
+ (* c_tx_last_tlp = "30" *)
+ (* c_tx_raddr_lat = "0" *)
+ (* c_tx_rdata_lat = "2" *)
+ (* c_tx_write_lat = "0" *)
+ (* c_upconfig_capable = "TRUE" *)
+ (* c_upstream_facing = "TRUE" *)
+ (* c_ur_atomic = "FALSE" *)
+ (* c_ur_inv_req = "TRUE" *)
+ (* c_ur_prs_response = "TRUE" *)
+ (* c_vc_base_ptr = "000" *)
+ (* c_vc_cap_enabled = "FALSE" *)
+ (* c_vc_cap_reject_snoop = "FALSE" *)
+ (* c_vc_next_ptr = "000" *)
+ (* c_vsec_base_ptr = "000" *)
+ (* c_vsec_cap_enabled = "FALSE" *)
+ (* c_vsec_next_ptr = "000" *)
+ (* c_xlnx_ref_board = "ZC706" *)
+ (* cap_ver = "2" *)
+ (* cardbus_cis_ptr = "00000000" *)
+ (* cmps = "3" *)
+ (* con_scl_fctr_d0_state = "0" *)
+ (* con_scl_fctr_d1_state = "0" *)
+ (* con_scl_fctr_d2_state = "0" *)
+ (* con_scl_fctr_d3_state = "0" *)
+ (* cost_table = "1" *)
+ (* d1_sup = "0" *)
+ (* d2_sup = "0" *)
+ (* dev_id = "7024" *)
+ (* dev_port_type = "0000" *)
+ (* dis_scl_fctr_d0_state = "0" *)
+ (* dis_scl_fctr_d1_state = "0" *)
+ (* dis_scl_fctr_d2_state = "0" *)
+ (* dis_scl_fctr_d3_state = "0" *)
+ (* dsi = "0" *)
+ (* ep_l0s_accpt_lat = "000" *)
+ (* ep_l1_accpt_lat = "111" *)
+ (* ext_tag_fld_sup = "FALSE" *)
+ (* int_pin = "1" *)
+ (* intx = "TRUE" *)
+ (* max_lnk_spd = "2" *)
+ (* max_lnk_wdt = "000100" *)
+ (* mps = "011" *)
+ (* no_soft_rst = "TRUE" *)
+ (* pci_exp_int_freq = "3" *)
+ (* pci_exp_ref_freq = "0" *)
+ (* phantm_func_sup = "00" *)
+ (* pme_sup = "0F" *)
+ (* pwr_con_d0_state = "00" *)
+ (* pwr_con_d1_state = "00" *)
+ (* pwr_con_d2_state = "00" *)
+ (* pwr_con_d3_state = "00" *)
+ (* pwr_dis_d0_state = "00" *)
+ (* pwr_dis_d1_state = "00" *)
+ (* pwr_dis_d2_state = "00" *)
+ (* pwr_dis_d3_state = "00" *)
+ (* rev_id = "00" *)
+ (* slot_clk = "TRUE" *)
+ (* subsys_id = "0007" *)
+ (* subsys_ven_id = "10EE" *)
+ (* ven_id = "10EE" *)
+ (* xrom_bar = "00000000" *)
+ pcie_7x_0_pcie_7x_0_pcie2_top inst
+ (.cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en),
+ .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en),
+ .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum),
+ .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received),
+ .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en),
+ .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received),
+ .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en),
+ .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received),
+ .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en),
+ .cfg_bridge_serr_en(cfg_bridge_serr_en),
+ .cfg_bus_number(cfg_bus_number),
+ .cfg_command({NLW_inst_cfg_command_UNCONNECTED[15:11],\^cfg_command }),
+ .cfg_dcommand({NLW_inst_cfg_dcommand_UNCONNECTED[15],\^cfg_dcommand }),
+ .cfg_dcommand2({NLW_inst_cfg_dcommand2_UNCONNECTED[15:12],\^cfg_dcommand2 }),
+ .cfg_device_number(cfg_device_number),
+ .cfg_ds_bus_number(cfg_ds_bus_number),
+ .cfg_ds_device_number(cfg_ds_device_number),
+ .cfg_ds_function_number(cfg_ds_function_number),
+ .cfg_dsn(cfg_dsn),
+ .cfg_dstatus({NLW_inst_cfg_dstatus_UNCONNECTED[15:6],\^cfg_dstatus }),
+ .cfg_err_acs(1'b0),
+ .cfg_err_aer_headerlog(cfg_err_aer_headerlog),
+ .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set),
+ .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked),
+ .cfg_err_cor(cfg_err_cor),
+ .cfg_err_cpl_abort(cfg_err_cpl_abort),
+ .cfg_err_cpl_rdy(cfg_err_cpl_rdy),
+ .cfg_err_cpl_timeout(cfg_err_cpl_timeout),
+ .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect),
+ .cfg_err_ecrc(cfg_err_ecrc),
+ .cfg_err_internal_cor(cfg_err_internal_cor),
+ .cfg_err_internal_uncor(cfg_err_internal_uncor),
+ .cfg_err_locked(cfg_err_locked),
+ .cfg_err_malformed(cfg_err_malformed),
+ .cfg_err_mc_blocked(cfg_err_mc_blocked),
+ .cfg_err_norecovery(cfg_err_norecovery),
+ .cfg_err_poisoned(cfg_err_poisoned),
+ .cfg_err_posted(cfg_err_posted),
+ .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header),
+ .cfg_err_ur(cfg_err_ur),
+ .cfg_function_number(cfg_function_number),
+ .cfg_interrupt(cfg_interrupt),
+ .cfg_interrupt_assert(cfg_interrupt_assert),
+ .cfg_interrupt_di(cfg_interrupt_di),
+ .cfg_interrupt_do(cfg_interrupt_do),
+ .cfg_interrupt_mmenable(cfg_interrupt_mmenable),
+ .cfg_interrupt_msienable(cfg_interrupt_msienable),
+ .cfg_interrupt_msixenable(cfg_interrupt_msixenable),
+ .cfg_interrupt_msixfm(cfg_interrupt_msixfm),
+ .cfg_interrupt_rdy(cfg_interrupt_rdy),
+ .cfg_interrupt_stat(cfg_interrupt_stat),
+ .cfg_lcommand({NLW_inst_cfg_lcommand_UNCONNECTED[15:12],\^cfg_lcommand }),
+ .cfg_lstatus(\^cfg_lstatus ),
+ .cfg_mgmt_byte_en(cfg_mgmt_byte_en),
+ .cfg_mgmt_di(cfg_mgmt_di),
+ .cfg_mgmt_do(cfg_mgmt_do),
+ .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr),
+ .cfg_mgmt_rd_en(cfg_mgmt_rd_en),
+ .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done),
+ .cfg_mgmt_wr_en(cfg_mgmt_wr_en),
+ .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly),
+ .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw),
+ .cfg_msg_data(cfg_msg_data),
+ .cfg_msg_received(cfg_msg_received),
+ .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a),
+ .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b),
+ .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c),
+ .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d),
+ .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a),
+ .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b),
+ .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c),
+ .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d),
+ .cfg_msg_received_err_cor(cfg_msg_received_err_cor),
+ .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal),
+ .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal),
+ .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak),
+ .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme),
+ .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack),
+ .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit),
+ .cfg_pcie_link_state(cfg_pcie_link_state),
+ .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum),
+ .cfg_pm_force_state(cfg_pm_force_state),
+ .cfg_pm_force_state_en(cfg_pm_force_state_en),
+ .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s),
+ .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1),
+ .cfg_pm_send_pme_to(1'b0),
+ .cfg_pm_wake(cfg_pm_wake),
+ .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en),
+ .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status),
+ .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate),
+ .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst),
+ .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en),
+ .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en),
+ .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en),
+ .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en),
+ .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse),
+ .cfg_status(NLW_inst_cfg_status_UNCONNECTED[15:0]),
+ .cfg_to_turnoff(cfg_to_turnoff),
+ .cfg_trn_pending(cfg_trn_pending),
+ .cfg_turnoff_ok(cfg_turnoff_ok),
+ .cfg_vc_tcvc_map(cfg_vc_tcvc_map),
+ .common_commands_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .common_commands_out(NLW_inst_common_commands_out_UNCONNECTED[11:0]),
+ .ext_ch_gt_drpaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .ext_ch_gt_drpclk(NLW_inst_ext_ch_gt_drpclk_UNCONNECTED),
+ .ext_ch_gt_drpdi({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .ext_ch_gt_drpdo(NLW_inst_ext_ch_gt_drpdo_UNCONNECTED[63:0]),
+ .ext_ch_gt_drpen({1'b0,1'b0,1'b0,1'b0}),
+ .ext_ch_gt_drprdy(NLW_inst_ext_ch_gt_drprdy_UNCONNECTED[3:0]),
+ .ext_ch_gt_drpwe({1'b0,1'b0,1'b0,1'b0}),
+ .fc_cpld(fc_cpld),
+ .fc_cplh(fc_cplh),
+ .fc_npd(fc_npd),
+ .fc_nph(fc_nph),
+ .fc_pd(fc_pd),
+ .fc_ph(fc_ph),
+ .fc_sel(fc_sel),
+ .gt_ch_drp_rdy(NLW_inst_gt_ch_drp_rdy_UNCONNECTED[3:0]),
+ .icap_clk(1'b0),
+ .icap_csib(1'b0),
+ .icap_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .icap_o(NLW_inst_icap_o_UNCONNECTED[31:0]),
+ .icap_rdwrb(1'b0),
+ .int_dclk_out(NLW_inst_int_dclk_out_UNCONNECTED),
+ .int_mmcm_lock_out(NLW_inst_int_mmcm_lock_out_UNCONNECTED),
+ .int_oobclk_out(NLW_inst_int_oobclk_out_UNCONNECTED),
+ .int_pclk_out_slave(NLW_inst_int_pclk_out_slave_UNCONNECTED),
+ .int_pclk_sel_slave({1'b0,1'b0,1'b0,1'b0}),
+ .int_pipe_rxusrclk_out(NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED),
+ .int_qplllock_out(NLW_inst_int_qplllock_out_UNCONNECTED[1:0]),
+ .int_qplloutclk_out(NLW_inst_int_qplloutclk_out_UNCONNECTED[1:0]),
+ .int_qplloutrefclk_out(NLW_inst_int_qplloutrefclk_out_UNCONNECTED[1:0]),
+ .int_rxoutclk_out(NLW_inst_int_rxoutclk_out_UNCONNECTED[3:0]),
+ .int_userclk1_out(NLW_inst_int_userclk1_out_UNCONNECTED),
+ .int_userclk2_out(NLW_inst_int_userclk2_out_UNCONNECTED),
+ .m_axis_rx_tdata(m_axis_rx_tdata),
+ .m_axis_rx_tkeep({\^m_axis_rx_tkeep ,NLW_inst_m_axis_rx_tkeep_UNCONNECTED[3:0]}),
+ .m_axis_rx_tlast(m_axis_rx_tlast),
+ .m_axis_rx_tready(m_axis_rx_tready),
+ .m_axis_rx_tuser(\^m_axis_rx_tuser ),
+ .m_axis_rx_tvalid(m_axis_rx_tvalid),
+ .pci_exp_rxn(pci_exp_rxn),
+ .pci_exp_rxp(pci_exp_rxp),
+ .pci_exp_txn(pci_exp_txn),
+ .pci_exp_txp(pci_exp_txp),
+ .pcie_drp_addr(pcie_drp_addr),
+ .pcie_drp_clk(pcie_drp_clk),
+ .pcie_drp_di(pcie_drp_di),
+ .pcie_drp_do(pcie_drp_do),
+ .pcie_drp_en(pcie_drp_en),
+ .pcie_drp_rdy(pcie_drp_rdy),
+ .pcie_drp_we(pcie_drp_we),
+ .pipe_cpll_lock(NLW_inst_pipe_cpll_lock_UNCONNECTED[3:0]),
+ .pipe_dclk_in(pipe_dclk_in),
+ .pipe_debug(NLW_inst_pipe_debug_UNCONNECTED[31:0]),
+ .pipe_debug_0(NLW_inst_pipe_debug_0_UNCONNECTED[3:0]),
+ .pipe_debug_1(NLW_inst_pipe_debug_1_UNCONNECTED[3:0]),
+ .pipe_debug_2(NLW_inst_pipe_debug_2_UNCONNECTED[3:0]),
+ .pipe_debug_3(NLW_inst_pipe_debug_3_UNCONNECTED[3:0]),
+ .pipe_debug_4(NLW_inst_pipe_debug_4_UNCONNECTED[3:0]),
+ .pipe_debug_5(NLW_inst_pipe_debug_5_UNCONNECTED[3:0]),
+ .pipe_debug_6(NLW_inst_pipe_debug_6_UNCONNECTED[3:0]),
+ .pipe_debug_7(NLW_inst_pipe_debug_7_UNCONNECTED[3:0]),
+ .pipe_debug_8(NLW_inst_pipe_debug_8_UNCONNECTED[3:0]),
+ .pipe_debug_9(NLW_inst_pipe_debug_9_UNCONNECTED[3:0]),
+ .pipe_dmonitorout(NLW_inst_pipe_dmonitorout_UNCONNECTED[59:0]),
+ .pipe_drp_fsm(NLW_inst_pipe_drp_fsm_UNCONNECTED[27:0]),
+ .pipe_eyescandataerror(NLW_inst_pipe_eyescandataerror_UNCONNECTED[3:0]),
+ .pipe_gen3_out(pipe_gen3_out),
+ .pipe_loopback({1'b0,1'b0,1'b0}),
+ .pipe_mmcm_lock_in(pipe_mmcm_lock_in),
+ .pipe_mmcm_rst_n(1'b0),
+ .pipe_oobclk_in(pipe_oobclk_in),
+ .pipe_pclk_in(pipe_pclk_in),
+ .pipe_pclk_sel_out(pipe_pclk_sel_out),
+ .pipe_qpll_lock(NLW_inst_pipe_qpll_lock_UNCONNECTED[0]),
+ .pipe_qrst_fsm(NLW_inst_pipe_qrst_fsm_UNCONNECTED[11:0]),
+ .pipe_qrst_idle(NLW_inst_pipe_qrst_idle_UNCONNECTED),
+ .pipe_rate_fsm(NLW_inst_pipe_rate_fsm_UNCONNECTED[19:0]),
+ .pipe_rate_idle(NLW_inst_pipe_rate_idle_UNCONNECTED),
+ .pipe_rst_fsm(NLW_inst_pipe_rst_fsm_UNCONNECTED[4:0]),
+ .pipe_rst_idle(NLW_inst_pipe_rst_idle_UNCONNECTED),
+ .pipe_rx_0_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .pipe_rx_1_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .pipe_rx_2_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .pipe_rx_3_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .pipe_rx_4_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .pipe_rx_5_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .pipe_rx_6_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .pipe_rx_7_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .pipe_rxbufstatus(NLW_inst_pipe_rxbufstatus_UNCONNECTED[11:0]),
+ .pipe_rxcommadet(NLW_inst_pipe_rxcommadet_UNCONNECTED[3:0]),
+ .pipe_rxdisperr(NLW_inst_pipe_rxdisperr_UNCONNECTED[31:0]),
+ .pipe_rxdlysresetdone(NLW_inst_pipe_rxdlysresetdone_UNCONNECTED[3:0]),
+ .pipe_rxnotintable(NLW_inst_pipe_rxnotintable_UNCONNECTED[31:0]),
+ .pipe_rxoutclk_in({1'b0,1'b0,1'b0,1'b0}),
+ .pipe_rxoutclk_out(pipe_rxoutclk_out),
+ .pipe_rxphaligndone(NLW_inst_pipe_rxphaligndone_UNCONNECTED[3:0]),
+ .pipe_rxpmaresetdone(NLW_inst_pipe_rxpmaresetdone_UNCONNECTED[3:0]),
+ .pipe_rxprbscntreset(1'b0),
+ .pipe_rxprbserr(NLW_inst_pipe_rxprbserr_UNCONNECTED[3:0]),
+ .pipe_rxprbssel({1'b0,1'b0,1'b0}),
+ .pipe_rxstatus(NLW_inst_pipe_rxstatus_UNCONNECTED[11:0]),
+ .pipe_rxsyncdone(NLW_inst_pipe_rxsyncdone_UNCONNECTED[3:0]),
+ .pipe_rxusrclk_in(pipe_rxusrclk_in),
+ .pipe_sync_fsm_rx(NLW_inst_pipe_sync_fsm_rx_UNCONNECTED[27:0]),
+ .pipe_sync_fsm_tx(NLW_inst_pipe_sync_fsm_tx_UNCONNECTED[23:0]),
+ .pipe_tx_0_sigs(NLW_inst_pipe_tx_0_sigs_UNCONNECTED[24:0]),
+ .pipe_tx_1_sigs(NLW_inst_pipe_tx_1_sigs_UNCONNECTED[24:0]),
+ .pipe_tx_2_sigs(NLW_inst_pipe_tx_2_sigs_UNCONNECTED[24:0]),
+ .pipe_tx_3_sigs(NLW_inst_pipe_tx_3_sigs_UNCONNECTED[24:0]),
+ .pipe_tx_4_sigs(NLW_inst_pipe_tx_4_sigs_UNCONNECTED[24:0]),
+ .pipe_tx_5_sigs(NLW_inst_pipe_tx_5_sigs_UNCONNECTED[24:0]),
+ .pipe_tx_6_sigs(NLW_inst_pipe_tx_6_sigs_UNCONNECTED[24:0]),
+ .pipe_tx_7_sigs(NLW_inst_pipe_tx_7_sigs_UNCONNECTED[24:0]),
+ .pipe_txdlysresetdone(NLW_inst_pipe_txdlysresetdone_UNCONNECTED[3:0]),
+ .pipe_txinhibit({1'b0,1'b0,1'b0,1'b0}),
+ .pipe_txoutclk_out(pipe_txoutclk_out),
+ .pipe_txphaligndone(NLW_inst_pipe_txphaligndone_UNCONNECTED[3:0]),
+ .pipe_txphinitdone(NLW_inst_pipe_txphinitdone_UNCONNECTED[3:0]),
+ .pipe_txprbsforceerr(1'b0),
+ .pipe_txprbssel({1'b0,1'b0,1'b0}),
+ .pipe_userclk1_in(pipe_userclk1_in),
+ .pipe_userclk2_in(pipe_userclk2_in),
+ .pl_directed_change_done(pl_directed_change_done),
+ .pl_directed_link_auton(pl_directed_link_auton),
+ .pl_directed_link_change(pl_directed_link_change),
+ .pl_directed_link_speed(pl_directed_link_speed),
+ .pl_directed_link_width(pl_directed_link_width),
+ .pl_downstream_deemph_source(pl_downstream_deemph_source),
+ .pl_initial_link_width(pl_initial_link_width),
+ .pl_lane_reversal_mode(pl_lane_reversal_mode),
+ .pl_link_gen2_cap(pl_link_gen2_cap),
+ .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported),
+ .pl_link_upcfg_cap(pl_link_upcfg_cap),
+ .pl_ltssm_state(pl_ltssm_state),
+ .pl_phy_lnk_up(pl_phy_lnk_up),
+ .pl_received_hot_rst(pl_received_hot_rst),
+ .pl_rx_pm_state(pl_rx_pm_state),
+ .pl_sel_lnk_rate(pl_sel_lnk_rate),
+ .pl_sel_lnk_width(pl_sel_lnk_width),
+ .pl_transmit_hot_rst(pl_transmit_hot_rst),
+ .pl_tx_pm_state(pl_tx_pm_state),
+ .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph),
+ .qpll_drp_clk(NLW_inst_qpll_drp_clk_UNCONNECTED),
+ .qpll_drp_crscode({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .qpll_drp_done({1'b0,1'b0}),
+ .qpll_drp_fsm({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .qpll_drp_gen3(NLW_inst_qpll_drp_gen3_UNCONNECTED),
+ .qpll_drp_ovrd(NLW_inst_qpll_drp_ovrd_UNCONNECTED),
+ .qpll_drp_reset({1'b0,1'b0}),
+ .qpll_drp_rst_n(NLW_inst_qpll_drp_rst_n_UNCONNECTED),
+ .qpll_drp_start(NLW_inst_qpll_drp_start_UNCONNECTED),
+ .qpll_qplld(NLW_inst_qpll_qplld_UNCONNECTED),
+ .qpll_qplllock({1'b0,1'b0}),
+ .qpll_qplloutclk({1'b0,1'b0}),
+ .qpll_qplloutrefclk({1'b0,1'b0}),
+ .qpll_qpllreset(NLW_inst_qpll_qpllreset_UNCONNECTED[1:0]),
+ .rx_np_ok(rx_np_ok),
+ .rx_np_req(rx_np_req),
+ .s_axis_tx_tdata(s_axis_tx_tdata),
+ .s_axis_tx_tkeep({s_axis_tx_tkeep[7],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .s_axis_tx_tlast(s_axis_tx_tlast),
+ .s_axis_tx_tready(s_axis_tx_tready),
+ .s_axis_tx_tuser(s_axis_tx_tuser),
+ .s_axis_tx_tvalid(s_axis_tx_tvalid),
+ .startup_cfgclk(NLW_inst_startup_cfgclk_UNCONNECTED),
+ .startup_cfgmclk(NLW_inst_startup_cfgmclk_UNCONNECTED),
+ .startup_clk(1'b0),
+ .startup_eos(NLW_inst_startup_eos_UNCONNECTED),
+ .startup_eos_in(1'b0),
+ .startup_gsr(1'b0),
+ .startup_gts(1'b0),
+ .startup_keyclearb(1'b1),
+ .startup_pack(1'b0),
+ .startup_preq(NLW_inst_startup_preq_UNCONNECTED),
+ .startup_usrcclko(1'b1),
+ .startup_usrcclkts(1'b0),
+ .startup_usrdoneo(1'b0),
+ .startup_usrdonets(1'b1),
+ .sys_clk(sys_clk),
+ .sys_rst_n(sys_rst_n),
+ .tx_buf_av(tx_buf_av),
+ .tx_cfg_gnt(tx_cfg_gnt),
+ .tx_cfg_req(tx_cfg_req),
+ .tx_err_drop(tx_err_drop),
+ .user_app_rdy(NLW_inst_user_app_rdy_UNCONNECTED),
+ .user_clk_out(user_clk_out),
+ .user_lnk_up(user_lnk_up),
+ .user_reset_out(user_reset_out));
+endmodule
+
+module pcie_7x_0_pcie_7x_0_axi_basic_rx
+ (E,
+ trn_rsrc_dsc_d,
+ m_axis_rx_tvalid_reg,
+ m_axis_rx_tkeep,
+ m_axis_rx_tlast,
+ trn_in_packet,
+ reg_dsc_detect_reg,
+ m_axis_rx_tuser,
+ Q,
+ \trn_rbar_hit_prev_reg[0] ,
+ pipe_userclk2_in,
+ trn_rrem,
+ trn_rsrc_dsc,
+ rsrc_rdy_filtered,
+ trn_reof,
+ trn_rsrc_dsc_prev0,
+ trn_rsof,
+ trn_recrc_err,
+ trn_rerrfwd,
+ trn_in_packet_reg,
+ m_axis_rx_tready,
+ dsc_detect,
+ trn_rd,
+ trn_rbar_hit);
+ output [0:0]E;
+ output trn_rsrc_dsc_d;
+ output m_axis_rx_tvalid_reg;
+ output [0:0]m_axis_rx_tkeep;
+ output m_axis_rx_tlast;
+ output trn_in_packet;
+ output reg_dsc_detect_reg;
+ output [12:0]m_axis_rx_tuser;
+ output [63:0]Q;
+ input \trn_rbar_hit_prev_reg[0] ;
+ input pipe_userclk2_in;
+ input [0:0]trn_rrem;
+ input trn_rsrc_dsc;
+ input rsrc_rdy_filtered;
+ input trn_reof;
+ input trn_rsrc_dsc_prev0;
+ input trn_rsof;
+ input trn_recrc_err;
+ input trn_rerrfwd;
+ input trn_in_packet_reg;
+ input m_axis_rx_tready;
+ input dsc_detect;
+ input [63:0]trn_rd;
+ input [6:0]trn_rbar_hit;
+
+ wire [0:0]E;
+ wire [63:0]Q;
+ wire dsc_detect;
+ wire [0:0]m_axis_rx_tkeep;
+ wire m_axis_rx_tlast;
+ wire m_axis_rx_tready;
+ wire [12:0]m_axis_rx_tuser;
+ wire m_axis_rx_tvalid_reg;
+ wire [10:0]new_pkt_len;
+ wire null_mux_sel;
+ wire pipe_userclk2_in;
+ wire reg_dsc_detect_reg;
+ wire rsrc_rdy_filtered;
+ wire rx_null_gen_inst_n_0;
+ wire rx_null_gen_inst_n_1;
+ wire rx_null_gen_inst_n_2;
+ wire rx_null_gen_inst_n_3;
+ wire rx_null_gen_inst_n_4;
+ wire rx_null_gen_inst_n_5;
+ wire rx_null_gen_inst_n_6;
+ wire rx_null_gen_inst_n_7;
+ wire rx_null_gen_inst_n_8;
+ wire rx_pipeline_inst_n_73;
+ wire rx_pipeline_inst_n_74;
+ wire rx_pipeline_inst_n_8;
+ wire trn_in_packet;
+ wire trn_in_packet_reg;
+ wire [6:0]trn_rbar_hit;
+ wire \trn_rbar_hit_prev_reg[0] ;
+ wire [63:0]trn_rd;
+ wire trn_recrc_err;
+ wire trn_reof;
+ wire trn_rerrfwd;
+ wire [0:0]trn_rrem;
+ wire trn_rsof;
+ wire trn_rsrc_dsc;
+ wire trn_rsrc_dsc_d;
+ wire trn_rsrc_dsc_prev0;
+
+ pcie_7x_0_pcie_7x_0_axi_basic_rx_null_gen rx_null_gen_inst
+ (.D({rx_null_gen_inst_n_0,rx_null_gen_inst_n_1}),
+ .Q({Q[30:29],Q[15],Q[1:0]}),
+ .S({rx_null_gen_inst_n_7,rx_null_gen_inst_n_8}),
+ .cur_state_reg_0(\trn_rbar_hit_prev_reg[0] ),
+ .cur_state_reg_1(m_axis_rx_tvalid_reg),
+ .m_axis_rx_tready(m_axis_rx_tready),
+ .m_axis_rx_tuser(m_axis_rx_tuser[12]),
+ .\m_axis_rx_tuser_reg[19] (rx_pipeline_inst_n_74),
+ .\m_axis_rx_tuser_reg[21] (rx_pipeline_inst_n_73),
+ .new_pkt_len(new_pkt_len),
+ .null_mux_sel(null_mux_sel),
+ .null_mux_sel_reg(rx_null_gen_inst_n_5),
+ .null_mux_sel_reg_0(rx_null_gen_inst_n_6),
+ .null_mux_sel_reg_1(rx_pipeline_inst_n_8),
+ .pipe_userclk2_in(pipe_userclk2_in),
+ .\reg_pkt_len_counter_reg[0]_0 (rx_null_gen_inst_n_4),
+ .\reg_pkt_len_counter_reg[3]_0 (rx_null_gen_inst_n_3),
+ .\reg_tkeep[7]_i_7_0 (rx_null_gen_inst_n_2));
+ pcie_7x_0_pcie_7x_0_axi_basic_rx_pipeline rx_pipeline_inst
+ (.D({rx_null_gen_inst_n_0,rx_null_gen_inst_n_1}),
+ .E(E),
+ .Q(Q),
+ .S({rx_null_gen_inst_n_7,rx_null_gen_inst_n_8}),
+ .data_prev_reg_0(rx_pipeline_inst_n_73),
+ .data_prev_reg_1(rx_pipeline_inst_n_74),
+ .dsc_detect(dsc_detect),
+ .m_axis_rx_tkeep(m_axis_rx_tkeep),
+ .m_axis_rx_tlast(m_axis_rx_tlast),
+ .m_axis_rx_tready(m_axis_rx_tready),
+ .m_axis_rx_tuser(m_axis_rx_tuser),
+ .m_axis_rx_tvalid_reg_0(m_axis_rx_tvalid_reg),
+ .new_pkt_len(new_pkt_len),
+ .null_mux_sel(null_mux_sel),
+ .null_mux_sel_reg_0(rx_null_gen_inst_n_5),
+ .pipe_userclk2_in(pipe_userclk2_in),
+ .reg_dsc_detect_reg_0(reg_dsc_detect_reg),
+ .\reg_tkeep_reg[7]_0 (rx_null_gen_inst_n_3),
+ .reg_tlast_reg_0(rx_null_gen_inst_n_6),
+ .rsrc_rdy_filtered(rsrc_rdy_filtered),
+ .trn_in_packet(trn_in_packet),
+ .trn_in_packet_reg_0(trn_in_packet_reg),
+ .trn_rbar_hit(trn_rbar_hit),
+ .\trn_rbar_hit_prev_reg[0]_0 (\trn_rbar_hit_prev_reg[0] ),
+ .trn_rd(trn_rd),
+ .trn_rdst_rdy_reg_0(rx_null_gen_inst_n_2),
+ .trn_rdst_rdy_reg_1(rx_null_gen_inst_n_4),
+ .trn_recrc_err(trn_recrc_err),
+ .trn_reof(trn_reof),
+ .trn_rerrfwd(trn_rerrfwd),
+ .trn_rrem(trn_rrem),
+ .trn_rsof(trn_rsof),
+ .trn_rsrc_dsc(trn_rsrc_dsc),
+ .trn_rsrc_dsc_d(trn_rsrc_dsc_d),
+ .trn_rsrc_dsc_prev0(trn_rsrc_dsc_prev0),
+ .user_reset_out_reg(rx_pipeline_inst_n_8));
+endmodule
+
+module pcie_7x_0_pcie_7x_0_axi_basic_rx_null_gen
+ (D,
+ \reg_tkeep[7]_i_7_0 ,
+ \reg_pkt_len_counter_reg[3]_0 ,
+ \reg_pkt_len_counter_reg[0]_0 ,
+ null_mux_sel_reg,
+ null_mux_sel_reg_0,
+ S,
+ cur_state_reg_0,
+ pipe_userclk2_in,
+ null_mux_sel,
+ \m_axis_rx_tuser_reg[19] ,
+ new_pkt_len,
+ m_axis_rx_tready,
+ null_mux_sel_reg_1,
+ cur_state_reg_1,
+ m_axis_rx_tuser,
+ \m_axis_rx_tuser_reg[21] ,
+ Q);
+ output [1:0]D;
+ output \reg_tkeep[7]_i_7_0 ;
+ output \reg_pkt_len_counter_reg[3]_0 ;
+ output \reg_pkt_len_counter_reg[0]_0 ;
+ output null_mux_sel_reg;
+ output null_mux_sel_reg_0;
+ output [1:0]S;
+ input cur_state_reg_0;
+ input pipe_userclk2_in;
+ input null_mux_sel;
+ input \m_axis_rx_tuser_reg[19] ;
+ input [10:0]new_pkt_len;
+ input m_axis_rx_tready;
+ input null_mux_sel_reg_1;
+ input cur_state_reg_1;
+ input [0:0]m_axis_rx_tuser;
+ input \m_axis_rx_tuser_reg[21] ;
+ input [4:0]Q;
+
+ wire [1:0]D;
+ wire [4:0]Q;
+ wire [1:0]S;
+ wire cur_state;
+ wire cur_state_reg_0;
+ wire cur_state_reg_1;
+ wire m_axis_rx_tready;
+ wire [0:0]m_axis_rx_tuser;
+ wire \m_axis_rx_tuser_reg[19] ;
+ wire \m_axis_rx_tuser_reg[21] ;
+ wire [10:0]new_pkt_len;
+ wire next_state;
+ wire null_mux_sel;
+ wire null_mux_sel_reg;
+ wire null_mux_sel_reg_0;
+ wire null_mux_sel_reg_1;
+ wire pipe_userclk2_in;
+ wire [11:1]pkt_len_counter;
+ wire [1:0]pkt_len_counter_0;
+ wire pkt_len_counter_dec__0_carry__0_i_1_n_0;
+ wire pkt_len_counter_dec__0_carry__0_i_2_n_0;
+ wire pkt_len_counter_dec__0_carry__0_i_3_n_0;
+ wire pkt_len_counter_dec__0_carry__0_i_4_n_0;
+ wire pkt_len_counter_dec__0_carry__0_n_0;
+ wire pkt_len_counter_dec__0_carry__0_n_1;
+ wire pkt_len_counter_dec__0_carry__0_n_2;
+ wire pkt_len_counter_dec__0_carry__0_n_3;
+ wire pkt_len_counter_dec__0_carry__1_i_1_n_0;
+ wire pkt_len_counter_dec__0_carry__1_i_2_n_0;
+ wire pkt_len_counter_dec__0_carry__1_i_3_n_0;
+ wire pkt_len_counter_dec__0_carry__1_n_2;
+ wire pkt_len_counter_dec__0_carry__1_n_3;
+ wire pkt_len_counter_dec__0_carry_i_1_n_0;
+ wire pkt_len_counter_dec__0_carry_i_2_n_0;
+ wire pkt_len_counter_dec__0_carry_i_3_n_0;
+ wire pkt_len_counter_dec__0_carry_i_4_n_0;
+ wire pkt_len_counter_dec__0_carry_i_5_n_0;
+ wire pkt_len_counter_dec__0_carry_n_0;
+ wire pkt_len_counter_dec__0_carry_n_1;
+ wire pkt_len_counter_dec__0_carry_n_2;
+ wire pkt_len_counter_dec__0_carry_n_3;
+ wire [11:0]reg_pkt_len_counter;
+ wire \reg_pkt_len_counter[11]_i_2_n_0 ;
+ wire \reg_pkt_len_counter[11]_i_3_n_0 ;
+ wire \reg_pkt_len_counter[11]_i_4_n_0 ;
+ wire \reg_pkt_len_counter_reg[0]_0 ;
+ wire \reg_pkt_len_counter_reg[3]_0 ;
+ wire \reg_tkeep[7]_i_4_n_0 ;
+ wire \reg_tkeep[7]_i_5_n_0 ;
+ wire \reg_tkeep[7]_i_6_n_0 ;
+ wire \reg_tkeep[7]_i_7_0 ;
+ wire \reg_tkeep[7]_i_7_n_0 ;
+ wire [11:2]sel0;
+ wire [3:2]NLW_pkt_len_counter_dec__0_carry__1_CO_UNCONNECTED;
+ wire [3:3]NLW_pkt_len_counter_dec__0_carry__1_O_UNCONNECTED;
+
+ LUT5 #(
+ .INIT(32'hAAAAAAEA))
+ cur_state_i_1
+ (.I0(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I1(m_axis_rx_tready),
+ .I2(cur_state_reg_1),
+ .I3(cur_state),
+ .I4(m_axis_rx_tuser),
+ .O(next_state));
+ FDRE cur_state_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(next_state),
+ .Q(cur_state),
+ .R(cur_state_reg_0));
+ LUT6 #(
+ .INIT(64'h5555555500000400))
+ \m_axis_rx_tuser[19]_i_1
+ (.I0(cur_state_reg_0),
+ .I1(\reg_tkeep[7]_i_7_0 ),
+ .I2(\reg_pkt_len_counter_reg[3]_0 ),
+ .I3(null_mux_sel),
+ .I4(pkt_len_counter_0[0]),
+ .I5(\m_axis_rx_tuser_reg[19] ),
+ .O(D[0]));
+ LUT6 #(
+ .INIT(64'h00000000FF80FF08))
+ \m_axis_rx_tuser[21]_i_2
+ (.I0(\reg_tkeep[7]_i_7_0 ),
+ .I1(null_mux_sel),
+ .I2(\reg_pkt_len_counter_reg[3]_0 ),
+ .I3(\m_axis_rx_tuser_reg[21] ),
+ .I4(pkt_len_counter_0[0]),
+ .I5(cur_state_reg_0),
+ .O(D[1]));
+ LUT6 #(
+ .INIT(64'h0000000077F7FFFF))
+ null_mux_sel_i_1
+ (.I0(\reg_tkeep[7]_i_7_0 ),
+ .I1(null_mux_sel),
+ .I2(pkt_len_counter_0[0]),
+ .I3(\reg_pkt_len_counter_reg[3]_0 ),
+ .I4(m_axis_rx_tready),
+ .I5(null_mux_sel_reg_1),
+ .O(null_mux_sel_reg));
+ (* ADDER_THRESHOLD = "35" *)
+ CARRY4 pkt_len_counter_dec__0_carry
+ (.CI(1'b0),
+ .CO({pkt_len_counter_dec__0_carry_n_0,pkt_len_counter_dec__0_carry_n_1,pkt_len_counter_dec__0_carry_n_2,pkt_len_counter_dec__0_carry_n_3}),
+ .CYINIT(1'b0),
+ .DI({reg_pkt_len_counter[3:2],pkt_len_counter_dec__0_carry_i_1_n_0,1'b0}),
+ .O(pkt_len_counter[4:1]),
+ .S({pkt_len_counter_dec__0_carry_i_2_n_0,pkt_len_counter_dec__0_carry_i_3_n_0,pkt_len_counter_dec__0_carry_i_4_n_0,pkt_len_counter_dec__0_carry_i_5_n_0}));
+ (* ADDER_THRESHOLD = "35" *)
+ CARRY4 pkt_len_counter_dec__0_carry__0
+ (.CI(pkt_len_counter_dec__0_carry_n_0),
+ .CO({pkt_len_counter_dec__0_carry__0_n_0,pkt_len_counter_dec__0_carry__0_n_1,pkt_len_counter_dec__0_carry__0_n_2,pkt_len_counter_dec__0_carry__0_n_3}),
+ .CYINIT(1'b0),
+ .DI(reg_pkt_len_counter[7:4]),
+ .O(pkt_len_counter[8:5]),
+ .S({pkt_len_counter_dec__0_carry__0_i_1_n_0,pkt_len_counter_dec__0_carry__0_i_2_n_0,pkt_len_counter_dec__0_carry__0_i_3_n_0,pkt_len_counter_dec__0_carry__0_i_4_n_0}));
+ LUT2 #(
+ .INIT(4'h9))
+ pkt_len_counter_dec__0_carry__0_i_1
+ (.I0(reg_pkt_len_counter[7]),
+ .I1(reg_pkt_len_counter[8]),
+ .O(pkt_len_counter_dec__0_carry__0_i_1_n_0));
+ LUT2 #(
+ .INIT(4'h9))
+ pkt_len_counter_dec__0_carry__0_i_2
+ (.I0(reg_pkt_len_counter[6]),
+ .I1(reg_pkt_len_counter[7]),
+ .O(pkt_len_counter_dec__0_carry__0_i_2_n_0));
+ LUT2 #(
+ .INIT(4'h9))
+ pkt_len_counter_dec__0_carry__0_i_3
+ (.I0(reg_pkt_len_counter[5]),
+ .I1(reg_pkt_len_counter[6]),
+ .O(pkt_len_counter_dec__0_carry__0_i_3_n_0));
+ LUT2 #(
+ .INIT(4'h9))
+ pkt_len_counter_dec__0_carry__0_i_4
+ (.I0(reg_pkt_len_counter[4]),
+ .I1(reg_pkt_len_counter[5]),
+ .O(pkt_len_counter_dec__0_carry__0_i_4_n_0));
+ (* ADDER_THRESHOLD = "35" *)
+ CARRY4 pkt_len_counter_dec__0_carry__1
+ (.CI(pkt_len_counter_dec__0_carry__0_n_0),
+ .CO({NLW_pkt_len_counter_dec__0_carry__1_CO_UNCONNECTED[3:2],pkt_len_counter_dec__0_carry__1_n_2,pkt_len_counter_dec__0_carry__1_n_3}),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,reg_pkt_len_counter[9:8]}),
+ .O({NLW_pkt_len_counter_dec__0_carry__1_O_UNCONNECTED[3],pkt_len_counter[11:9]}),
+ .S({1'b0,pkt_len_counter_dec__0_carry__1_i_1_n_0,pkt_len_counter_dec__0_carry__1_i_2_n_0,pkt_len_counter_dec__0_carry__1_i_3_n_0}));
+ LUT2 #(
+ .INIT(4'h9))
+ pkt_len_counter_dec__0_carry__1_i_1
+ (.I0(reg_pkt_len_counter[10]),
+ .I1(reg_pkt_len_counter[11]),
+ .O(pkt_len_counter_dec__0_carry__1_i_1_n_0));
+ LUT2 #(
+ .INIT(4'h9))
+ pkt_len_counter_dec__0_carry__1_i_2
+ (.I0(reg_pkt_len_counter[9]),
+ .I1(reg_pkt_len_counter[10]),
+ .O(pkt_len_counter_dec__0_carry__1_i_2_n_0));
+ LUT2 #(
+ .INIT(4'h9))
+ pkt_len_counter_dec__0_carry__1_i_3
+ (.I0(reg_pkt_len_counter[8]),
+ .I1(reg_pkt_len_counter[9]),
+ .O(pkt_len_counter_dec__0_carry__1_i_3_n_0));
+ LUT2 #(
+ .INIT(4'hB))
+ pkt_len_counter_dec__0_carry_i_1
+ (.I0(reg_pkt_len_counter[1]),
+ .I1(m_axis_rx_tready),
+ .O(pkt_len_counter_dec__0_carry_i_1_n_0));
+ LUT2 #(
+ .INIT(4'h9))
+ pkt_len_counter_dec__0_carry_i_2
+ (.I0(reg_pkt_len_counter[3]),
+ .I1(reg_pkt_len_counter[4]),
+ .O(pkt_len_counter_dec__0_carry_i_2_n_0));
+ LUT2 #(
+ .INIT(4'h9))
+ pkt_len_counter_dec__0_carry_i_3
+ (.I0(reg_pkt_len_counter[2]),
+ .I1(reg_pkt_len_counter[3]),
+ .O(pkt_len_counter_dec__0_carry_i_3_n_0));
+ LUT3 #(
+ .INIT(8'hD2))
+ pkt_len_counter_dec__0_carry_i_4
+ (.I0(m_axis_rx_tready),
+ .I1(reg_pkt_len_counter[1]),
+ .I2(reg_pkt_len_counter[2]),
+ .O(pkt_len_counter_dec__0_carry_i_4_n_0));
+ LUT2 #(
+ .INIT(4'h6))
+ pkt_len_counter_dec__0_carry_i_5
+ (.I0(reg_pkt_len_counter[1]),
+ .I1(m_axis_rx_tready),
+ .O(pkt_len_counter_dec__0_carry_i_5_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair214" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \reg_pkt_len_counter[0]_i_1
+ (.I0(reg_pkt_len_counter[0]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I2(new_pkt_len[0]),
+ .O(pkt_len_counter_0[0]));
+ (* SOFT_HLUTNM = "soft_lutpair211" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \reg_pkt_len_counter[10]_i_1
+ (.I0(pkt_len_counter[10]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I2(new_pkt_len[10]),
+ .O(sel0[10]));
+ (* SOFT_HLUTNM = "soft_lutpair211" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \reg_pkt_len_counter[11]_i_1
+ (.I0(pkt_len_counter[11]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .O(sel0[11]));
+ LUT6 #(
+ .INIT(64'hAAAAAAA8AAAAAAAA))
+ \reg_pkt_len_counter[11]_i_2
+ (.I0(cur_state),
+ .I1(reg_pkt_len_counter[3]),
+ .I2(reg_pkt_len_counter[8]),
+ .I3(reg_pkt_len_counter[7]),
+ .I4(\reg_pkt_len_counter[11]_i_3_n_0 ),
+ .I5(\reg_pkt_len_counter[11]_i_4_n_0 ),
+ .O(\reg_pkt_len_counter[11]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'hFFEF))
+ \reg_pkt_len_counter[11]_i_3
+ (.I0(reg_pkt_len_counter[5]),
+ .I1(reg_pkt_len_counter[4]),
+ .I2(m_axis_rx_tready),
+ .I3(reg_pkt_len_counter[9]),
+ .O(\reg_pkt_len_counter[11]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000007))
+ \reg_pkt_len_counter[11]_i_4
+ (.I0(reg_pkt_len_counter[0]),
+ .I1(reg_pkt_len_counter[1]),
+ .I2(reg_pkt_len_counter[2]),
+ .I3(reg_pkt_len_counter[6]),
+ .I4(reg_pkt_len_counter[10]),
+ .I5(reg_pkt_len_counter[11]),
+ .O(\reg_pkt_len_counter[11]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'hE2))
+ \reg_pkt_len_counter[1]_i_1
+ (.I0(new_pkt_len[1]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I2(pkt_len_counter[1]),
+ .O(pkt_len_counter_0[1]));
+ (* SOFT_HLUTNM = "soft_lutpair210" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \reg_pkt_len_counter[2]_i_1
+ (.I0(pkt_len_counter[2]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I2(new_pkt_len[2]),
+ .O(sel0[2]));
+ (* SOFT_HLUTNM = "soft_lutpair214" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \reg_pkt_len_counter[3]_i_1
+ (.I0(pkt_len_counter[3]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I2(new_pkt_len[3]),
+ .O(sel0[3]));
+ LUT4 #(
+ .INIT(16'h1EEE))
+ \reg_pkt_len_counter[3]_i_7
+ (.I0(Q[2]),
+ .I1(Q[3]),
+ .I2(Q[1]),
+ .I3(Q[4]),
+ .O(S[1]));
+ LUT4 #(
+ .INIT(16'h6999))
+ \reg_pkt_len_counter[3]_i_8
+ (.I0(Q[3]),
+ .I1(Q[2]),
+ .I2(Q[4]),
+ .I3(Q[0]),
+ .O(S[0]));
+ (* SOFT_HLUTNM = "soft_lutpair208" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \reg_pkt_len_counter[4]_i_1
+ (.I0(pkt_len_counter[4]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I2(new_pkt_len[4]),
+ .O(sel0[4]));
+ (* SOFT_HLUTNM = "soft_lutpair212" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \reg_pkt_len_counter[5]_i_1
+ (.I0(pkt_len_counter[5]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I2(new_pkt_len[5]),
+ .O(sel0[5]));
+ (* SOFT_HLUTNM = "soft_lutpair209" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \reg_pkt_len_counter[6]_i_1
+ (.I0(pkt_len_counter[6]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I2(new_pkt_len[6]),
+ .O(sel0[6]));
+ (* SOFT_HLUTNM = "soft_lutpair213" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \reg_pkt_len_counter[7]_i_1
+ (.I0(pkt_len_counter[7]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I2(new_pkt_len[7]),
+ .O(sel0[7]));
+ (* SOFT_HLUTNM = "soft_lutpair207" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \reg_pkt_len_counter[8]_i_1
+ (.I0(pkt_len_counter[8]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I2(new_pkt_len[8]),
+ .O(sel0[8]));
+ (* SOFT_HLUTNM = "soft_lutpair212" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \reg_pkt_len_counter[9]_i_1
+ (.I0(pkt_len_counter[9]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I2(new_pkt_len[9]),
+ .O(sel0[9]));
+ FDRE \reg_pkt_len_counter_reg[0]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(pkt_len_counter_0[0]),
+ .Q(reg_pkt_len_counter[0]),
+ .R(cur_state_reg_0));
+ FDRE \reg_pkt_len_counter_reg[10]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(sel0[10]),
+ .Q(reg_pkt_len_counter[10]),
+ .R(cur_state_reg_0));
+ FDRE \reg_pkt_len_counter_reg[11]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(sel0[11]),
+ .Q(reg_pkt_len_counter[11]),
+ .R(cur_state_reg_0));
+ FDRE \reg_pkt_len_counter_reg[1]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(pkt_len_counter_0[1]),
+ .Q(reg_pkt_len_counter[1]),
+ .R(cur_state_reg_0));
+ FDRE \reg_pkt_len_counter_reg[2]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(sel0[2]),
+ .Q(reg_pkt_len_counter[2]),
+ .R(cur_state_reg_0));
+ FDRE \reg_pkt_len_counter_reg[3]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(sel0[3]),
+ .Q(reg_pkt_len_counter[3]),
+ .R(cur_state_reg_0));
+ FDRE \reg_pkt_len_counter_reg[4]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(sel0[4]),
+ .Q(reg_pkt_len_counter[4]),
+ .R(cur_state_reg_0));
+ FDRE \reg_pkt_len_counter_reg[5]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(sel0[5]),
+ .Q(reg_pkt_len_counter[5]),
+ .R(cur_state_reg_0));
+ FDRE \reg_pkt_len_counter_reg[6]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(sel0[6]),
+ .Q(reg_pkt_len_counter[6]),
+ .R(cur_state_reg_0));
+ FDRE \reg_pkt_len_counter_reg[7]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(sel0[7]),
+ .Q(reg_pkt_len_counter[7]),
+ .R(cur_state_reg_0));
+ FDRE \reg_pkt_len_counter_reg[8]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(sel0[8]),
+ .Q(reg_pkt_len_counter[8]),
+ .R(cur_state_reg_0));
+ FDRE \reg_pkt_len_counter_reg[9]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(sel0[9]),
+ .Q(reg_pkt_len_counter[9]),
+ .R(cur_state_reg_0));
+ LUT6 #(
+ .INIT(64'h0000000000000001))
+ \reg_tkeep[7]_i_2
+ (.I0(sel0[11]),
+ .I1(sel0[10]),
+ .I2(\reg_tkeep[7]_i_4_n_0 ),
+ .I3(\reg_tkeep[7]_i_5_n_0 ),
+ .I4(\reg_tkeep[7]_i_6_n_0 ),
+ .I5(\reg_tkeep[7]_i_7_n_0 ),
+ .O(\reg_tkeep[7]_i_7_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair213" *)
+ LUT3 #(
+ .INIT(8'h47))
+ \reg_tkeep[7]_i_3
+ (.I0(pkt_len_counter[1]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I2(new_pkt_len[1]),
+ .O(\reg_pkt_len_counter_reg[3]_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair207" *)
+ LUT5 #(
+ .INIT(32'hFFFACCFA))
+ \reg_tkeep[7]_i_4
+ (.I0(new_pkt_len[8]),
+ .I1(pkt_len_counter[8]),
+ .I2(new_pkt_len[9]),
+ .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I4(pkt_len_counter[9]),
+ .O(\reg_tkeep[7]_i_4_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair209" *)
+ LUT5 #(
+ .INIT(32'hFFFACCFA))
+ \reg_tkeep[7]_i_5
+ (.I0(new_pkt_len[6]),
+ .I1(pkt_len_counter[6]),
+ .I2(new_pkt_len[7]),
+ .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I4(pkt_len_counter[7]),
+ .O(\reg_tkeep[7]_i_5_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair208" *)
+ LUT5 #(
+ .INIT(32'hFFFACCFA))
+ \reg_tkeep[7]_i_6
+ (.I0(new_pkt_len[4]),
+ .I1(pkt_len_counter[4]),
+ .I2(new_pkt_len[5]),
+ .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I4(pkt_len_counter[5]),
+ .O(\reg_tkeep[7]_i_6_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair210" *)
+ LUT5 #(
+ .INIT(32'hFFFACCFA))
+ \reg_tkeep[7]_i_7
+ (.I0(new_pkt_len[2]),
+ .I1(pkt_len_counter[2]),
+ .I2(new_pkt_len[3]),
+ .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I4(pkt_len_counter[3]),
+ .O(\reg_tkeep[7]_i_7_n_0 ));
+ LUT5 #(
+ .INIT(32'hFFFFB000))
+ reg_tlast_i_1
+ (.I0(\reg_pkt_len_counter_reg[3]_0 ),
+ .I1(pkt_len_counter_0[0]),
+ .I2(null_mux_sel),
+ .I3(\reg_tkeep[7]_i_7_0 ),
+ .I4(\m_axis_rx_tuser_reg[21] ),
+ .O(null_mux_sel_reg_0));
+ LUT6 #(
+ .INIT(64'hB8308800FFFFFFFF))
+ trn_rdst_rdy_i_3
+ (.I0(pkt_len_counter[1]),
+ .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
+ .I2(new_pkt_len[1]),
+ .I3(reg_pkt_len_counter[0]),
+ .I4(new_pkt_len[0]),
+ .I5(null_mux_sel),
+ .O(\reg_pkt_len_counter_reg[0]_0 ));
+endmodule
+
+module pcie_7x_0_pcie_7x_0_axi_basic_rx_pipeline
+ (E,
+ trn_rsrc_dsc_d,
+ m_axis_rx_tvalid_reg_0,
+ m_axis_rx_tkeep,
+ m_axis_rx_tlast,
+ null_mux_sel,
+ trn_in_packet,
+ reg_dsc_detect_reg_0,
+ user_reset_out_reg,
+ Q,
+ data_prev_reg_0,
+ data_prev_reg_1,
+ new_pkt_len,
+ m_axis_rx_tuser,
+ \trn_rbar_hit_prev_reg[0]_0 ,
+ pipe_userclk2_in,
+ trn_rrem,
+ trn_rsrc_dsc,
+ rsrc_rdy_filtered,
+ trn_reof,
+ reg_tlast_reg_0,
+ trn_rsrc_dsc_prev0,
+ trn_rsof,
+ trn_recrc_err,
+ trn_rerrfwd,
+ null_mux_sel_reg_0,
+ trn_in_packet_reg_0,
+ m_axis_rx_tready,
+ dsc_detect,
+ trn_rdst_rdy_reg_0,
+ trn_rdst_rdy_reg_1,
+ \reg_tkeep_reg[7]_0 ,
+ trn_rd,
+ trn_rbar_hit,
+ S,
+ D);
+ output [0:0]E;
+ output trn_rsrc_dsc_d;
+ output m_axis_rx_tvalid_reg_0;
+ output [0:0]m_axis_rx_tkeep;
+ output m_axis_rx_tlast;
+ output null_mux_sel;
+ output trn_in_packet;
+ output reg_dsc_detect_reg_0;
+ output user_reset_out_reg;
+ output [63:0]Q;
+ output data_prev_reg_0;
+ output data_prev_reg_1;
+ output [10:0]new_pkt_len;
+ output [12:0]m_axis_rx_tuser;
+ input \trn_rbar_hit_prev_reg[0]_0 ;
+ input pipe_userclk2_in;
+ input [0:0]trn_rrem;
+ input trn_rsrc_dsc;
+ input rsrc_rdy_filtered;
+ input trn_reof;
+ input reg_tlast_reg_0;
+ input trn_rsrc_dsc_prev0;
+ input trn_rsof;
+ input trn_recrc_err;
+ input trn_rerrfwd;
+ input null_mux_sel_reg_0;
+ input trn_in_packet_reg_0;
+ input m_axis_rx_tready;
+ input dsc_detect;
+ input trn_rdst_rdy_reg_0;
+ input trn_rdst_rdy_reg_1;
+ input \reg_tkeep_reg[7]_0 ;
+ input [63:0]trn_rd;
+ input [6:0]trn_rbar_hit;
+ input [1:0]S;
+ input [1:0]D;
+
+ wire [1:0]D;
+ wire [0:0]E;
+ wire [63:0]Q;
+ wire [1:0]S;
+ wire data_hold;
+ wire data_prev;
+ wire data_prev_reg_0;
+ wire data_prev_reg_1;
+ wire dsc_detect;
+ wire \m_axis_rx_tdata[63]_i_1_n_0 ;
+ wire [0:0]m_axis_rx_tkeep;
+ wire m_axis_rx_tlast;
+ wire m_axis_rx_tready;
+ wire [12:0]m_axis_rx_tuser;
+ wire \m_axis_rx_tuser[0]_i_1_n_0 ;
+ wire \m_axis_rx_tuser[14]_i_1_n_0 ;
+ wire \m_axis_rx_tuser[14]_i_2_n_0 ;
+ wire \m_axis_rx_tuser[18]_i_1_n_0 ;
+ wire \m_axis_rx_tuser[1]_i_1_n_0 ;
+ wire \m_axis_rx_tuser[21]_i_1_n_0 ;
+ wire \m_axis_rx_tuser[2]_i_1_n_0 ;
+ wire \m_axis_rx_tuser[3]_i_1_n_0 ;
+ wire \m_axis_rx_tuser[4]_i_1_n_0 ;
+ wire \m_axis_rx_tuser[5]_i_1_n_0 ;
+ wire \m_axis_rx_tuser[6]_i_1_n_0 ;
+ wire \m_axis_rx_tuser[7]_i_1_n_0 ;
+ wire \m_axis_rx_tuser[8]_i_1_n_0 ;
+ wire m_axis_rx_tvalid_i_1_n_0;
+ wire m_axis_rx_tvalid_reg_0;
+ wire [10:0]new_pkt_len;
+ wire null_mux_sel;
+ wire null_mux_sel_reg_0;
+ wire [63:0]p_1_in;
+ wire [1:0]packet_overhead;
+ wire pipe_userclk2_in;
+ wire reg_dsc_detect_i_1_n_0;
+ wire reg_dsc_detect_reg_0;
+ wire \reg_pkt_len_counter[10]_i_3_n_0 ;
+ wire \reg_pkt_len_counter[10]_i_4_n_0 ;
+ wire \reg_pkt_len_counter[3]_i_5_n_0 ;
+ wire \reg_pkt_len_counter[3]_i_6_n_0 ;
+ wire \reg_pkt_len_counter[7]_i_3_n_0 ;
+ wire \reg_pkt_len_counter[7]_i_4_n_0 ;
+ wire \reg_pkt_len_counter[7]_i_5_n_0 ;
+ wire \reg_pkt_len_counter[7]_i_6_n_0 ;
+ wire \reg_pkt_len_counter_reg[10]_i_2_n_3 ;
+ wire \reg_pkt_len_counter_reg[3]_i_2_n_0 ;
+ wire \reg_pkt_len_counter_reg[3]_i_2_n_1 ;
+ wire \reg_pkt_len_counter_reg[3]_i_2_n_2 ;
+ wire \reg_pkt_len_counter_reg[3]_i_2_n_3 ;
+ wire \reg_pkt_len_counter_reg[7]_i_2_n_0 ;
+ wire \reg_pkt_len_counter_reg[7]_i_2_n_1 ;
+ wire \reg_pkt_len_counter_reg[7]_i_2_n_2 ;
+ wire \reg_pkt_len_counter_reg[7]_i_2_n_3 ;
+ wire [7:7]reg_tkeep;
+ wire \reg_tkeep_reg[7]_0 ;
+ wire reg_tlast_reg_0;
+ wire rsrc_rdy_filtered;
+ wire trn_in_packet;
+ wire trn_in_packet_reg_0;
+ wire [6:0]trn_rbar_hit;
+ wire [6:0]trn_rbar_hit_prev;
+ wire \trn_rbar_hit_prev_reg[0]_0 ;
+ wire [63:0]trn_rd;
+ wire [63:0]trn_rd_prev;
+ wire trn_rdst_rdy_i_1_n_0;
+ wire trn_rdst_rdy_i_2_n_0;
+ wire trn_rdst_rdy_reg_0;
+ wire trn_rdst_rdy_reg_1;
+ wire trn_recrc_err;
+ wire trn_recrc_err_prev;
+ wire trn_reof;
+ wire trn_reof_prev;
+ wire trn_rerrfwd;
+ wire trn_rerrfwd_prev;
+ wire [0:0]trn_rrem;
+ wire trn_rrem_prev;
+ wire trn_rsof;
+ wire trn_rsof_prev;
+ wire trn_rsrc_dsc;
+ wire trn_rsrc_dsc_d;
+ wire trn_rsrc_dsc_prev;
+ wire trn_rsrc_dsc_prev0;
+ wire trn_rsrc_rdy_prev;
+ wire user_reset_out_reg;
+ wire [3:1]\NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED ;
+ wire [3:2]\NLW_reg_pkt_len_counter_reg[10]_i_2_O_UNCONNECTED ;
+
+ LUT2 #(
+ .INIT(4'h2))
+ data_prev_i_1
+ (.I0(m_axis_rx_tvalid_reg_0),
+ .I1(m_axis_rx_tready),
+ .O(data_hold));
+ FDRE data_prev_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(data_hold),
+ .Q(data_prev),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair243" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[0]_i_1
+ (.I0(trn_rd_prev[0]),
+ .I1(data_prev),
+ .I2(trn_rd[32]),
+ .O(p_1_in[0]));
+ (* SOFT_HLUTNM = "soft_lutpair246" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[10]_i_1
+ (.I0(trn_rd_prev[10]),
+ .I1(data_prev),
+ .I2(trn_rd[42]),
+ .O(p_1_in[10]));
+ (* SOFT_HLUTNM = "soft_lutpair244" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[11]_i_1
+ (.I0(trn_rd_prev[11]),
+ .I1(data_prev),
+ .I2(trn_rd[43]),
+ .O(p_1_in[11]));
+ (* SOFT_HLUTNM = "soft_lutpair241" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[12]_i_1
+ (.I0(trn_rd_prev[12]),
+ .I1(data_prev),
+ .I2(trn_rd[44]),
+ .O(p_1_in[12]));
+ (* SOFT_HLUTNM = "soft_lutpair239" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[13]_i_1
+ (.I0(trn_rd_prev[13]),
+ .I1(data_prev),
+ .I2(trn_rd[45]),
+ .O(p_1_in[13]));
+ (* SOFT_HLUTNM = "soft_lutpair249" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[14]_i_1
+ (.I0(trn_rd_prev[14]),
+ .I1(data_prev),
+ .I2(trn_rd[46]),
+ .O(p_1_in[14]));
+ (* SOFT_HLUTNM = "soft_lutpair242" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[15]_i_1
+ (.I0(trn_rd_prev[15]),
+ .I1(data_prev),
+ .I2(trn_rd[47]),
+ .O(p_1_in[15]));
+ (* SOFT_HLUTNM = "soft_lutpair238" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[16]_i_1
+ (.I0(trn_rd_prev[16]),
+ .I1(data_prev),
+ .I2(trn_rd[48]),
+ .O(p_1_in[16]));
+ (* SOFT_HLUTNM = "soft_lutpair234" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[17]_i_1
+ (.I0(trn_rd_prev[17]),
+ .I1(data_prev),
+ .I2(trn_rd[49]),
+ .O(p_1_in[17]));
+ (* SOFT_HLUTNM = "soft_lutpair232" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[18]_i_1
+ (.I0(trn_rd_prev[18]),
+ .I1(data_prev),
+ .I2(trn_rd[50]),
+ .O(p_1_in[18]));
+ (* SOFT_HLUTNM = "soft_lutpair246" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[19]_i_1
+ (.I0(trn_rd_prev[19]),
+ .I1(data_prev),
+ .I2(trn_rd[51]),
+ .O(p_1_in[19]));
+ (* SOFT_HLUTNM = "soft_lutpair249" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[1]_i_1
+ (.I0(trn_rd_prev[1]),
+ .I1(data_prev),
+ .I2(trn_rd[33]),
+ .O(p_1_in[1]));
+ (* SOFT_HLUTNM = "soft_lutpair242" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[20]_i_1
+ (.I0(trn_rd_prev[20]),
+ .I1(data_prev),
+ .I2(trn_rd[52]),
+ .O(p_1_in[20]));
+ (* SOFT_HLUTNM = "soft_lutpair237" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[21]_i_1
+ (.I0(trn_rd_prev[21]),
+ .I1(data_prev),
+ .I2(trn_rd[53]),
+ .O(p_1_in[21]));
+ (* SOFT_HLUTNM = "soft_lutpair245" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[22]_i_1
+ (.I0(trn_rd_prev[22]),
+ .I1(data_prev),
+ .I2(trn_rd[54]),
+ .O(p_1_in[22]));
+ (* SOFT_HLUTNM = "soft_lutpair247" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[23]_i_1
+ (.I0(trn_rd_prev[23]),
+ .I1(data_prev),
+ .I2(trn_rd[55]),
+ .O(p_1_in[23]));
+ (* SOFT_HLUTNM = "soft_lutpair240" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[24]_i_1
+ (.I0(trn_rd_prev[24]),
+ .I1(data_prev),
+ .I2(trn_rd[56]),
+ .O(p_1_in[24]));
+ (* SOFT_HLUTNM = "soft_lutpair231" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[25]_i_1
+ (.I0(trn_rd_prev[25]),
+ .I1(data_prev),
+ .I2(trn_rd[57]),
+ .O(p_1_in[25]));
+ (* SOFT_HLUTNM = "soft_lutpair229" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[26]_i_1
+ (.I0(trn_rd_prev[26]),
+ .I1(data_prev),
+ .I2(trn_rd[58]),
+ .O(p_1_in[26]));
+ (* SOFT_HLUTNM = "soft_lutpair232" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[27]_i_1
+ (.I0(trn_rd_prev[27]),
+ .I1(data_prev),
+ .I2(trn_rd[59]),
+ .O(p_1_in[27]));
+ (* SOFT_HLUTNM = "soft_lutpair236" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[28]_i_1
+ (.I0(trn_rd_prev[28]),
+ .I1(data_prev),
+ .I2(trn_rd[60]),
+ .O(p_1_in[28]));
+ (* SOFT_HLUTNM = "soft_lutpair228" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[29]_i_1
+ (.I0(trn_rd_prev[29]),
+ .I1(data_prev),
+ .I2(trn_rd[61]),
+ .O(p_1_in[29]));
+ (* SOFT_HLUTNM = "soft_lutpair240" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[2]_i_1
+ (.I0(trn_rd_prev[2]),
+ .I1(data_prev),
+ .I2(trn_rd[34]),
+ .O(p_1_in[2]));
+ (* SOFT_HLUTNM = "soft_lutpair227" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[30]_i_1
+ (.I0(trn_rd_prev[30]),
+ .I1(data_prev),
+ .I2(trn_rd[62]),
+ .O(p_1_in[30]));
+ (* SOFT_HLUTNM = "soft_lutpair222" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[31]_i_1
+ (.I0(trn_rd_prev[31]),
+ .I1(data_prev),
+ .I2(trn_rd[63]),
+ .O(p_1_in[31]));
+ (* SOFT_HLUTNM = "soft_lutpair226" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[32]_i_1
+ (.I0(trn_rd_prev[32]),
+ .I1(data_prev),
+ .I2(trn_rd[0]),
+ .O(p_1_in[32]));
+ (* SOFT_HLUTNM = "soft_lutpair218" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[33]_i_1
+ (.I0(trn_rd_prev[33]),
+ .I1(data_prev),
+ .I2(trn_rd[1]),
+ .O(p_1_in[33]));
+ (* SOFT_HLUTNM = "soft_lutpair225" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[34]_i_1
+ (.I0(trn_rd_prev[34]),
+ .I1(data_prev),
+ .I2(trn_rd[2]),
+ .O(p_1_in[34]));
+ (* SOFT_HLUTNM = "soft_lutpair219" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[35]_i_1
+ (.I0(trn_rd_prev[35]),
+ .I1(data_prev),
+ .I2(trn_rd[3]),
+ .O(p_1_in[35]));
+ (* SOFT_HLUTNM = "soft_lutpair227" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[36]_i_1
+ (.I0(trn_rd_prev[36]),
+ .I1(data_prev),
+ .I2(trn_rd[4]),
+ .O(p_1_in[36]));
+ (* SOFT_HLUTNM = "soft_lutpair218" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[37]_i_1
+ (.I0(trn_rd_prev[37]),
+ .I1(data_prev),
+ .I2(trn_rd[5]),
+ .O(p_1_in[37]));
+ (* SOFT_HLUTNM = "soft_lutpair225" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[38]_i_1
+ (.I0(trn_rd_prev[38]),
+ .I1(data_prev),
+ .I2(trn_rd[6]),
+ .O(p_1_in[38]));
+ (* SOFT_HLUTNM = "soft_lutpair221" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[39]_i_1
+ (.I0(trn_rd_prev[39]),
+ .I1(data_prev),
+ .I2(trn_rd[7]),
+ .O(p_1_in[39]));
+ (* SOFT_HLUTNM = "soft_lutpair248" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[3]_i_1
+ (.I0(trn_rd_prev[3]),
+ .I1(data_prev),
+ .I2(trn_rd[35]),
+ .O(p_1_in[3]));
+ (* SOFT_HLUTNM = "soft_lutpair223" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[40]_i_1
+ (.I0(trn_rd_prev[40]),
+ .I1(data_prev),
+ .I2(trn_rd[8]),
+ .O(p_1_in[40]));
+ (* SOFT_HLUTNM = "soft_lutpair222" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[41]_i_1
+ (.I0(trn_rd_prev[41]),
+ .I1(data_prev),
+ .I2(trn_rd[9]),
+ .O(p_1_in[41]));
+ (* SOFT_HLUTNM = "soft_lutpair221" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[42]_i_1
+ (.I0(trn_rd_prev[42]),
+ .I1(data_prev),
+ .I2(trn_rd[10]),
+ .O(p_1_in[42]));
+ (* SOFT_HLUTNM = "soft_lutpair223" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[43]_i_1
+ (.I0(trn_rd_prev[43]),
+ .I1(data_prev),
+ .I2(trn_rd[11]),
+ .O(p_1_in[43]));
+ (* SOFT_HLUTNM = "soft_lutpair229" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[44]_i_1
+ (.I0(trn_rd_prev[44]),
+ .I1(data_prev),
+ .I2(trn_rd[12]),
+ .O(p_1_in[44]));
+ (* SOFT_HLUTNM = "soft_lutpair228" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[45]_i_1
+ (.I0(trn_rd_prev[45]),
+ .I1(data_prev),
+ .I2(trn_rd[13]),
+ .O(p_1_in[45]));
+ (* SOFT_HLUTNM = "soft_lutpair220" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[46]_i_1
+ (.I0(trn_rd_prev[46]),
+ .I1(data_prev),
+ .I2(trn_rd[14]),
+ .O(p_1_in[46]));
+ (* SOFT_HLUTNM = "soft_lutpair231" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[47]_i_1
+ (.I0(trn_rd_prev[47]),
+ .I1(data_prev),
+ .I2(trn_rd[15]),
+ .O(p_1_in[47]));
+ (* SOFT_HLUTNM = "soft_lutpair220" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[48]_i_1
+ (.I0(trn_rd_prev[48]),
+ .I1(data_prev),
+ .I2(trn_rd[16]),
+ .O(p_1_in[48]));
+ (* SOFT_HLUTNM = "soft_lutpair235" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[49]_i_1
+ (.I0(trn_rd_prev[49]),
+ .I1(data_prev),
+ .I2(trn_rd[17]),
+ .O(p_1_in[49]));
+ (* SOFT_HLUTNM = "soft_lutpair248" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[4]_i_1
+ (.I0(trn_rd_prev[4]),
+ .I1(data_prev),
+ .I2(trn_rd[36]),
+ .O(p_1_in[4]));
+ (* SOFT_HLUTNM = "soft_lutpair233" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[50]_i_1
+ (.I0(trn_rd_prev[50]),
+ .I1(data_prev),
+ .I2(trn_rd[18]),
+ .O(p_1_in[50]));
+ (* SOFT_HLUTNM = "soft_lutpair230" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[51]_i_1
+ (.I0(trn_rd_prev[51]),
+ .I1(data_prev),
+ .I2(trn_rd[19]),
+ .O(p_1_in[51]));
+ (* SOFT_HLUTNM = "soft_lutpair219" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[52]_i_1
+ (.I0(trn_rd_prev[52]),
+ .I1(data_prev),
+ .I2(trn_rd[20]),
+ .O(p_1_in[52]));
+ (* SOFT_HLUTNM = "soft_lutpair226" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[53]_i_1
+ (.I0(trn_rd_prev[53]),
+ .I1(data_prev),
+ .I2(trn_rd[21]),
+ .O(p_1_in[53]));
+ (* SOFT_HLUTNM = "soft_lutpair224" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[54]_i_1
+ (.I0(trn_rd_prev[54]),
+ .I1(data_prev),
+ .I2(trn_rd[22]),
+ .O(p_1_in[54]));
+ (* SOFT_HLUTNM = "soft_lutpair224" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[55]_i_1
+ (.I0(trn_rd_prev[55]),
+ .I1(data_prev),
+ .I2(trn_rd[23]),
+ .O(p_1_in[55]));
+ (* SOFT_HLUTNM = "soft_lutpair239" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[56]_i_1
+ (.I0(trn_rd_prev[56]),
+ .I1(data_prev),
+ .I2(trn_rd[24]),
+ .O(p_1_in[56]));
+ (* SOFT_HLUTNM = "soft_lutpair236" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[57]_i_1
+ (.I0(trn_rd_prev[57]),
+ .I1(data_prev),
+ .I2(trn_rd[25]),
+ .O(p_1_in[57]));
+ (* SOFT_HLUTNM = "soft_lutpair238" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[58]_i_1
+ (.I0(trn_rd_prev[58]),
+ .I1(data_prev),
+ .I2(trn_rd[26]),
+ .O(p_1_in[58]));
+ (* SOFT_HLUTNM = "soft_lutpair230" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[59]_i_1
+ (.I0(trn_rd_prev[59]),
+ .I1(data_prev),
+ .I2(trn_rd[27]),
+ .O(p_1_in[59]));
+ (* SOFT_HLUTNM = "soft_lutpair237" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[5]_i_1
+ (.I0(trn_rd_prev[5]),
+ .I1(data_prev),
+ .I2(trn_rd[37]),
+ .O(p_1_in[5]));
+ (* SOFT_HLUTNM = "soft_lutpair233" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[60]_i_1
+ (.I0(trn_rd_prev[60]),
+ .I1(data_prev),
+ .I2(trn_rd[28]),
+ .O(p_1_in[60]));
+ (* SOFT_HLUTNM = "soft_lutpair243" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[61]_i_1
+ (.I0(trn_rd_prev[61]),
+ .I1(data_prev),
+ .I2(trn_rd[29]),
+ .O(p_1_in[61]));
+ (* SOFT_HLUTNM = "soft_lutpair234" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[62]_i_1
+ (.I0(trn_rd_prev[62]),
+ .I1(data_prev),
+ .I2(trn_rd[30]),
+ .O(p_1_in[62]));
+ LUT2 #(
+ .INIT(4'hB))
+ \m_axis_rx_tdata[63]_i_1
+ (.I0(m_axis_rx_tready),
+ .I1(m_axis_rx_tvalid_reg_0),
+ .O(\m_axis_rx_tdata[63]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair247" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[63]_i_2
+ (.I0(trn_rd_prev[63]),
+ .I1(data_prev),
+ .I2(trn_rd[31]),
+ .O(p_1_in[63]));
+ (* SOFT_HLUTNM = "soft_lutpair235" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[6]_i_1
+ (.I0(trn_rd_prev[6]),
+ .I1(data_prev),
+ .I2(trn_rd[38]),
+ .O(p_1_in[6]));
+ (* SOFT_HLUTNM = "soft_lutpair245" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[7]_i_1
+ (.I0(trn_rd_prev[7]),
+ .I1(data_prev),
+ .I2(trn_rd[39]),
+ .O(p_1_in[7]));
+ (* SOFT_HLUTNM = "soft_lutpair244" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[8]_i_1
+ (.I0(trn_rd_prev[8]),
+ .I1(data_prev),
+ .I2(trn_rd[40]),
+ .O(p_1_in[8]));
+ (* SOFT_HLUTNM = "soft_lutpair241" *)
+ LUT3 #(
+ .INIT(8'hB8))
+ \m_axis_rx_tdata[9]_i_1
+ (.I0(trn_rd_prev[9]),
+ .I1(data_prev),
+ .I2(trn_rd[41]),
+ .O(p_1_in[9]));
+ FDRE \m_axis_rx_tdata_reg[0]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[0]),
+ .Q(Q[0]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[10]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[10]),
+ .Q(Q[10]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[11]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[11]),
+ .Q(Q[11]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[12]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[12]),
+ .Q(Q[12]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[13]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[13]),
+ .Q(Q[13]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[14]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[14]),
+ .Q(Q[14]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[15]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[15]),
+ .Q(Q[15]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[16]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[16]),
+ .Q(Q[16]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[17]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[17]),
+ .Q(Q[17]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[18]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[18]),
+ .Q(Q[18]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[19]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[19]),
+ .Q(Q[19]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[1]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[1]),
+ .Q(Q[1]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[20]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[20]),
+ .Q(Q[20]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[21]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[21]),
+ .Q(Q[21]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[22]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[22]),
+ .Q(Q[22]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[23]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[23]),
+ .Q(Q[23]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[24]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[24]),
+ .Q(Q[24]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[25]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[25]),
+ .Q(Q[25]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[26]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[26]),
+ .Q(Q[26]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[27]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[27]),
+ .Q(Q[27]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[28]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[28]),
+ .Q(Q[28]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[29]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[29]),
+ .Q(Q[29]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[2]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[2]),
+ .Q(Q[2]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[30]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[30]),
+ .Q(Q[30]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[31]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[31]),
+ .Q(Q[31]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[32]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[32]),
+ .Q(Q[32]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[33]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[33]),
+ .Q(Q[33]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[34]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[34]),
+ .Q(Q[34]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[35]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[35]),
+ .Q(Q[35]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[36]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[36]),
+ .Q(Q[36]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[37]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[37]),
+ .Q(Q[37]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[38]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[38]),
+ .Q(Q[38]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[39]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[39]),
+ .Q(Q[39]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[3]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[3]),
+ .Q(Q[3]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[40]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[40]),
+ .Q(Q[40]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[41]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[41]),
+ .Q(Q[41]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[42]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[42]),
+ .Q(Q[42]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[43]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[43]),
+ .Q(Q[43]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[44]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[44]),
+ .Q(Q[44]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[45]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[45]),
+ .Q(Q[45]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[46]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[46]),
+ .Q(Q[46]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[47]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[47]),
+ .Q(Q[47]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[48]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[48]),
+ .Q(Q[48]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[49]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[49]),
+ .Q(Q[49]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[4]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[4]),
+ .Q(Q[4]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[50]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[50]),
+ .Q(Q[50]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[51]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[51]),
+ .Q(Q[51]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[52]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[52]),
+ .Q(Q[52]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[53]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[53]),
+ .Q(Q[53]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[54]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[54]),
+ .Q(Q[54]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[55]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[55]),
+ .Q(Q[55]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[56]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[56]),
+ .Q(Q[56]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[57]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[57]),
+ .Q(Q[57]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[58]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[58]),
+ .Q(Q[58]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[59]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[59]),
+ .Q(Q[59]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[5]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[5]),
+ .Q(Q[5]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[60]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[60]),
+ .Q(Q[60]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[61]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[61]),
+ .Q(Q[61]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[62]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[62]),
+ .Q(Q[62]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[63]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[63]),
+ .Q(Q[63]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[6]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[6]),
+ .Q(Q[6]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[7]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[7]),
+ .Q(Q[7]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[8]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[8]),
+ .Q(Q[8]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \m_axis_rx_tdata_reg[9]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(p_1_in[9]),
+ .Q(Q[9]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ LUT5 #(
+ .INIT(32'h000000E2))
+ \m_axis_rx_tuser[0]_i_1
+ (.I0(trn_recrc_err),
+ .I1(data_prev),
+ .I2(trn_recrc_err_prev),
+ .I3(\trn_rbar_hit_prev_reg[0]_0 ),
+ .I4(null_mux_sel),
+ .O(\m_axis_rx_tuser[0]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000004F40404))
+ \m_axis_rx_tuser[14]_i_1
+ (.I0(trn_rsrc_dsc),
+ .I1(trn_rsof),
+ .I2(data_prev),
+ .I3(trn_rsrc_dsc_prev),
+ .I4(trn_rsof_prev),
+ .I5(\m_axis_rx_tuser[14]_i_2_n_0 ),
+ .O(\m_axis_rx_tuser[14]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair215" *)
+ LUT2 #(
+ .INIT(4'hE))
+ \m_axis_rx_tuser[14]_i_2
+ (.I0(\trn_rbar_hit_prev_reg[0]_0 ),
+ .I1(null_mux_sel),
+ .O(\m_axis_rx_tuser[14]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair216" *)
+ LUT1 #(
+ .INIT(2'h1))
+ \m_axis_rx_tuser[18]_i_1
+ (.I0(\trn_rbar_hit_prev_reg[0]_0 ),
+ .O(\m_axis_rx_tuser[18]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'h00E2))
+ \m_axis_rx_tuser[19]_i_2
+ (.I0(trn_rrem),
+ .I1(data_prev),
+ .I2(trn_rrem_prev),
+ .I3(null_mux_sel),
+ .O(data_prev_reg_1));
+ LUT5 #(
+ .INIT(32'h000000B8))
+ \m_axis_rx_tuser[1]_i_1
+ (.I0(trn_rerrfwd_prev),
+ .I1(data_prev),
+ .I2(trn_rerrfwd),
+ .I3(\trn_rbar_hit_prev_reg[0]_0 ),
+ .I4(null_mux_sel),
+ .O(\m_axis_rx_tuser[1]_i_1_n_0 ));
+ LUT3 #(
+ .INIT(8'hEF))
+ \m_axis_rx_tuser[21]_i_1
+ (.I0(\trn_rbar_hit_prev_reg[0]_0 ),
+ .I1(m_axis_rx_tready),
+ .I2(m_axis_rx_tvalid_reg_0),
+ .O(\m_axis_rx_tuser[21]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair216" *)
+ LUT5 #(
+ .INIT(32'h000000B8))
+ \m_axis_rx_tuser[2]_i_1
+ (.I0(trn_rbar_hit_prev[0]),
+ .I1(data_prev),
+ .I2(trn_rbar_hit[0]),
+ .I3(\trn_rbar_hit_prev_reg[0]_0 ),
+ .I4(null_mux_sel),
+ .O(\m_axis_rx_tuser[2]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'h000000E2))
+ \m_axis_rx_tuser[3]_i_1
+ (.I0(trn_rbar_hit[1]),
+ .I1(data_prev),
+ .I2(trn_rbar_hit_prev[1]),
+ .I3(\trn_rbar_hit_prev_reg[0]_0 ),
+ .I4(null_mux_sel),
+ .O(\m_axis_rx_tuser[3]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'h000000E2))
+ \m_axis_rx_tuser[4]_i_1
+ (.I0(trn_rbar_hit[2]),
+ .I1(data_prev),
+ .I2(trn_rbar_hit_prev[2]),
+ .I3(\trn_rbar_hit_prev_reg[0]_0 ),
+ .I4(null_mux_sel),
+ .O(\m_axis_rx_tuser[4]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'h000000B8))
+ \m_axis_rx_tuser[5]_i_1
+ (.I0(trn_rbar_hit_prev[3]),
+ .I1(data_prev),
+ .I2(trn_rbar_hit[3]),
+ .I3(\trn_rbar_hit_prev_reg[0]_0 ),
+ .I4(null_mux_sel),
+ .O(\m_axis_rx_tuser[5]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'h000000B8))
+ \m_axis_rx_tuser[6]_i_1
+ (.I0(trn_rbar_hit_prev[4]),
+ .I1(data_prev),
+ .I2(trn_rbar_hit[4]),
+ .I3(\trn_rbar_hit_prev_reg[0]_0 ),
+ .I4(null_mux_sel),
+ .O(\m_axis_rx_tuser[6]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair215" *)
+ LUT5 #(
+ .INIT(32'h000000E2))
+ \m_axis_rx_tuser[7]_i_1
+ (.I0(trn_rbar_hit[5]),
+ .I1(data_prev),
+ .I2(trn_rbar_hit_prev[5]),
+ .I3(\trn_rbar_hit_prev_reg[0]_0 ),
+ .I4(null_mux_sel),
+ .O(\m_axis_rx_tuser[7]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'h000000E2))
+ \m_axis_rx_tuser[8]_i_1
+ (.I0(trn_rbar_hit[6]),
+ .I1(data_prev),
+ .I2(trn_rbar_hit_prev[6]),
+ .I3(\trn_rbar_hit_prev_reg[0]_0 ),
+ .I4(null_mux_sel),
+ .O(\m_axis_rx_tuser[8]_i_1_n_0 ));
+ FDRE \m_axis_rx_tuser_reg[0]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
+ .D(\m_axis_rx_tuser[0]_i_1_n_0 ),
+ .Q(m_axis_rx_tuser[0]),
+ .R(1'b0));
+ FDRE \m_axis_rx_tuser_reg[14]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
+ .D(\m_axis_rx_tuser[14]_i_1_n_0 ),
+ .Q(m_axis_rx_tuser[9]),
+ .R(1'b0));
+ FDRE \m_axis_rx_tuser_reg[18]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
+ .D(\m_axis_rx_tuser[18]_i_1_n_0 ),
+ .Q(m_axis_rx_tuser[10]),
+ .R(1'b0));
+ FDRE \m_axis_rx_tuser_reg[19]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
+ .D(D[0]),
+ .Q(m_axis_rx_tuser[11]),
+ .R(1'b0));
+ FDRE \m_axis_rx_tuser_reg[1]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
+ .D(\m_axis_rx_tuser[1]_i_1_n_0 ),
+ .Q(m_axis_rx_tuser[1]),
+ .R(1'b0));
+ FDRE \m_axis_rx_tuser_reg[21]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
+ .D(D[1]),
+ .Q(m_axis_rx_tuser[12]),
+ .R(1'b0));
+ FDRE \m_axis_rx_tuser_reg[2]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
+ .D(\m_axis_rx_tuser[2]_i_1_n_0 ),
+ .Q(m_axis_rx_tuser[2]),
+ .R(1'b0));
+ FDRE \m_axis_rx_tuser_reg[3]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
+ .D(\m_axis_rx_tuser[3]_i_1_n_0 ),
+ .Q(m_axis_rx_tuser[3]),
+ .R(1'b0));
+ FDRE \m_axis_rx_tuser_reg[4]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
+ .D(\m_axis_rx_tuser[4]_i_1_n_0 ),
+ .Q(m_axis_rx_tuser[4]),
+ .R(1'b0));
+ FDRE \m_axis_rx_tuser_reg[5]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
+ .D(\m_axis_rx_tuser[5]_i_1_n_0 ),
+ .Q(m_axis_rx_tuser[5]),
+ .R(1'b0));
+ FDRE \m_axis_rx_tuser_reg[6]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
+ .D(\m_axis_rx_tuser[6]_i_1_n_0 ),
+ .Q(m_axis_rx_tuser[6]),
+ .R(1'b0));
+ FDRE \m_axis_rx_tuser_reg[7]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
+ .D(\m_axis_rx_tuser[7]_i_1_n_0 ),
+ .Q(m_axis_rx_tuser[7]),
+ .R(1'b0));
+ FDRE \m_axis_rx_tuser_reg[8]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
+ .D(\m_axis_rx_tuser[8]_i_1_n_0 ),
+ .Q(m_axis_rx_tuser[8]),
+ .R(1'b0));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFFFECE))
+ m_axis_rx_tvalid_i_1
+ (.I0(rsrc_rdy_filtered),
+ .I1(null_mux_sel),
+ .I2(data_prev),
+ .I3(trn_rsrc_rdy_prev),
+ .I4(reg_dsc_detect_reg_0),
+ .I5(dsc_detect),
+ .O(m_axis_rx_tvalid_i_1_n_0));
+ FDRE m_axis_rx_tvalid_reg
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(m_axis_rx_tvalid_i_1_n_0),
+ .Q(m_axis_rx_tvalid_reg_0),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ LUT6 #(
+ .INIT(64'hABAAABAAABAABBBB))
+ null_mux_sel_i_2
+ (.I0(\trn_rbar_hit_prev_reg[0]_0 ),
+ .I1(null_mux_sel),
+ .I2(m_axis_rx_tready),
+ .I3(m_axis_rx_tvalid_reg_0),
+ .I4(dsc_detect),
+ .I5(reg_dsc_detect_reg_0),
+ .O(user_reset_out_reg));
+ FDRE null_mux_sel_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(null_mux_sel_reg_0),
+ .Q(null_mux_sel),
+ .R(1'b0));
+ (* SOFT_HLUTNM = "soft_lutpair217" *)
+ LUT3 #(
+ .INIT(8'hDC))
+ reg_dsc_detect_i_1
+ (.I0(null_mux_sel),
+ .I1(dsc_detect),
+ .I2(reg_dsc_detect_reg_0),
+ .O(reg_dsc_detect_i_1_n_0));
+ FDRE reg_dsc_detect_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(reg_dsc_detect_i_1_n_0),
+ .Q(reg_dsc_detect_reg_0),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ LUT2 #(
+ .INIT(4'h8))
+ \reg_pkt_len_counter[10]_i_3
+ (.I0(Q[30]),
+ .I1(Q[9]),
+ .O(\reg_pkt_len_counter[10]_i_3_n_0 ));
+ LUT2 #(
+ .INIT(4'h8))
+ \reg_pkt_len_counter[10]_i_4
+ (.I0(Q[30]),
+ .I1(Q[8]),
+ .O(\reg_pkt_len_counter[10]_i_4_n_0 ));
+ LUT2 #(
+ .INIT(4'hE))
+ \reg_pkt_len_counter[3]_i_3
+ (.I0(Q[29]),
+ .I1(Q[15]),
+ .O(packet_overhead[1]));
+ LUT2 #(
+ .INIT(4'h9))
+ \reg_pkt_len_counter[3]_i_4
+ (.I0(Q[15]),
+ .I1(Q[29]),
+ .O(packet_overhead[0]));
+ LUT2 #(
+ .INIT(4'h8))
+ \reg_pkt_len_counter[3]_i_5
+ (.I0(Q[30]),
+ .I1(Q[3]),
+ .O(\reg_pkt_len_counter[3]_i_5_n_0 ));
+ LUT2 #(
+ .INIT(4'h8))
+ \reg_pkt_len_counter[3]_i_6
+ (.I0(Q[30]),
+ .I1(Q[2]),
+ .O(\reg_pkt_len_counter[3]_i_6_n_0 ));
+ LUT2 #(
+ .INIT(4'h8))
+ \reg_pkt_len_counter[7]_i_3
+ (.I0(Q[30]),
+ .I1(Q[7]),
+ .O(\reg_pkt_len_counter[7]_i_3_n_0 ));
+ LUT2 #(
+ .INIT(4'h8))
+ \reg_pkt_len_counter[7]_i_4
+ (.I0(Q[30]),
+ .I1(Q[6]),
+ .O(\reg_pkt_len_counter[7]_i_4_n_0 ));
+ LUT2 #(
+ .INIT(4'h8))
+ \reg_pkt_len_counter[7]_i_5
+ (.I0(Q[30]),
+ .I1(Q[5]),
+ .O(\reg_pkt_len_counter[7]_i_5_n_0 ));
+ LUT2 #(
+ .INIT(4'h8))
+ \reg_pkt_len_counter[7]_i_6
+ (.I0(Q[30]),
+ .I1(Q[4]),
+ .O(\reg_pkt_len_counter[7]_i_6_n_0 ));
+ CARRY4 \reg_pkt_len_counter_reg[10]_i_2
+ (.CI(\reg_pkt_len_counter_reg[7]_i_2_n_0 ),
+ .CO({\NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED [3],new_pkt_len[10],\NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED [1],\reg_pkt_len_counter_reg[10]_i_2_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O({\NLW_reg_pkt_len_counter_reg[10]_i_2_O_UNCONNECTED [3:2],new_pkt_len[9:8]}),
+ .S({1'b0,1'b1,\reg_pkt_len_counter[10]_i_3_n_0 ,\reg_pkt_len_counter[10]_i_4_n_0 }));
+ CARRY4 \reg_pkt_len_counter_reg[3]_i_2
+ (.CI(1'b0),
+ .CO({\reg_pkt_len_counter_reg[3]_i_2_n_0 ,\reg_pkt_len_counter_reg[3]_i_2_n_1 ,\reg_pkt_len_counter_reg[3]_i_2_n_2 ,\reg_pkt_len_counter_reg[3]_i_2_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,packet_overhead}),
+ .O(new_pkt_len[3:0]),
+ .S({\reg_pkt_len_counter[3]_i_5_n_0 ,\reg_pkt_len_counter[3]_i_6_n_0 ,S}));
+ CARRY4 \reg_pkt_len_counter_reg[7]_i_2
+ (.CI(\reg_pkt_len_counter_reg[3]_i_2_n_0 ),
+ .CO({\reg_pkt_len_counter_reg[7]_i_2_n_0 ,\reg_pkt_len_counter_reg[7]_i_2_n_1 ,\reg_pkt_len_counter_reg[7]_i_2_n_2 ,\reg_pkt_len_counter_reg[7]_i_2_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O(new_pkt_len[7:4]),
+ .S({\reg_pkt_len_counter[7]_i_3_n_0 ,\reg_pkt_len_counter[7]_i_4_n_0 ,\reg_pkt_len_counter[7]_i_5_n_0 ,\reg_pkt_len_counter[7]_i_6_n_0 }));
+ LUT6 #(
+ .INIT(64'h7F7F7F7070707F70))
+ \reg_tkeep[7]_i_1
+ (.I0(trn_rdst_rdy_reg_0),
+ .I1(\reg_tkeep_reg[7]_0 ),
+ .I2(null_mux_sel),
+ .I3(trn_rrem),
+ .I4(data_prev),
+ .I5(trn_rrem_prev),
+ .O(reg_tkeep));
+ FDSE \reg_tkeep_reg[7]
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(reg_tkeep),
+ .Q(m_axis_rx_tkeep),
+ .S(\trn_rbar_hit_prev_reg[0]_0 ));
+ LUT4 #(
+ .INIT(16'h00E2))
+ reg_tlast_i_2
+ (.I0(trn_reof),
+ .I1(data_prev),
+ .I2(trn_reof_prev),
+ .I3(null_mux_sel),
+ .O(data_prev_reg_0));
+ FDRE reg_tlast_reg
+ (.C(pipe_userclk2_in),
+ .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
+ .D(reg_tlast_reg_0),
+ .Q(m_axis_rx_tlast),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE trn_in_packet_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(trn_in_packet_reg_0),
+ .Q(trn_in_packet),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rbar_hit_prev_reg[0]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rbar_hit[0]),
+ .Q(trn_rbar_hit_prev[0]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rbar_hit_prev_reg[1]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rbar_hit[1]),
+ .Q(trn_rbar_hit_prev[1]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rbar_hit_prev_reg[2]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rbar_hit[2]),
+ .Q(trn_rbar_hit_prev[2]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rbar_hit_prev_reg[3]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rbar_hit[3]),
+ .Q(trn_rbar_hit_prev[3]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rbar_hit_prev_reg[4]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rbar_hit[4]),
+ .Q(trn_rbar_hit_prev[4]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rbar_hit_prev_reg[5]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rbar_hit[5]),
+ .Q(trn_rbar_hit_prev[5]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rbar_hit_prev_reg[6]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rbar_hit[6]),
+ .Q(trn_rbar_hit_prev[6]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[0]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[32]),
+ .Q(trn_rd_prev[0]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[10]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[42]),
+ .Q(trn_rd_prev[10]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[11]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[43]),
+ .Q(trn_rd_prev[11]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[12]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[44]),
+ .Q(trn_rd_prev[12]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[13]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[45]),
+ .Q(trn_rd_prev[13]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[14]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[46]),
+ .Q(trn_rd_prev[14]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[15]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[47]),
+ .Q(trn_rd_prev[15]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[16]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[48]),
+ .Q(trn_rd_prev[16]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[17]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[49]),
+ .Q(trn_rd_prev[17]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[18]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[50]),
+ .Q(trn_rd_prev[18]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[19]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[51]),
+ .Q(trn_rd_prev[19]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[1]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[33]),
+ .Q(trn_rd_prev[1]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[20]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[52]),
+ .Q(trn_rd_prev[20]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[21]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[53]),
+ .Q(trn_rd_prev[21]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[22]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[54]),
+ .Q(trn_rd_prev[22]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[23]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[55]),
+ .Q(trn_rd_prev[23]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[24]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[56]),
+ .Q(trn_rd_prev[24]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[25]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[57]),
+ .Q(trn_rd_prev[25]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[26]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[58]),
+ .Q(trn_rd_prev[26]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[27]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[59]),
+ .Q(trn_rd_prev[27]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[28]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[60]),
+ .Q(trn_rd_prev[28]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[29]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[61]),
+ .Q(trn_rd_prev[29]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[2]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[34]),
+ .Q(trn_rd_prev[2]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[30]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[62]),
+ .Q(trn_rd_prev[30]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[31]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[63]),
+ .Q(trn_rd_prev[31]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[32]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[0]),
+ .Q(trn_rd_prev[32]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[33]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[1]),
+ .Q(trn_rd_prev[33]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[34]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[2]),
+ .Q(trn_rd_prev[34]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[35]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[3]),
+ .Q(trn_rd_prev[35]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[36]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[4]),
+ .Q(trn_rd_prev[36]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[37]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[5]),
+ .Q(trn_rd_prev[37]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[38]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[6]),
+ .Q(trn_rd_prev[38]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[39]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[7]),
+ .Q(trn_rd_prev[39]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[3]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[35]),
+ .Q(trn_rd_prev[3]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[40]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[8]),
+ .Q(trn_rd_prev[40]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[41]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[9]),
+ .Q(trn_rd_prev[41]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[42]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[10]),
+ .Q(trn_rd_prev[42]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[43]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[11]),
+ .Q(trn_rd_prev[43]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[44]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[12]),
+ .Q(trn_rd_prev[44]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[45]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[13]),
+ .Q(trn_rd_prev[45]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[46]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[14]),
+ .Q(trn_rd_prev[46]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[47]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[15]),
+ .Q(trn_rd_prev[47]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[48]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[16]),
+ .Q(trn_rd_prev[48]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[49]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[17]),
+ .Q(trn_rd_prev[49]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[4]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[36]),
+ .Q(trn_rd_prev[4]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[50]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[18]),
+ .Q(trn_rd_prev[50]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[51]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[19]),
+ .Q(trn_rd_prev[51]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[52]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[20]),
+ .Q(trn_rd_prev[52]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[53]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[21]),
+ .Q(trn_rd_prev[53]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[54]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[22]),
+ .Q(trn_rd_prev[54]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[55]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[23]),
+ .Q(trn_rd_prev[55]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[56]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[24]),
+ .Q(trn_rd_prev[56]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[57]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[25]),
+ .Q(trn_rd_prev[57]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[58]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[26]),
+ .Q(trn_rd_prev[58]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[59]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[27]),
+ .Q(trn_rd_prev[59]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[5]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[37]),
+ .Q(trn_rd_prev[5]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[60]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[28]),
+ .Q(trn_rd_prev[60]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[61]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[29]),
+ .Q(trn_rd_prev[61]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[62]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[30]),
+ .Q(trn_rd_prev[62]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[63]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[31]),
+ .Q(trn_rd_prev[63]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[6]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[38]),
+ .Q(trn_rd_prev[6]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[7]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[39]),
+ .Q(trn_rd_prev[7]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[8]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[40]),
+ .Q(trn_rd_prev[8]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rd_prev_reg[9]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rd[41]),
+ .Q(trn_rd_prev[9]),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ LUT6 #(
+ .INIT(64'h3030FF3050505050))
+ trn_rdst_rdy_i_1
+ (.I0(m_axis_rx_tvalid_reg_0),
+ .I1(null_mux_sel),
+ .I2(trn_rdst_rdy_i_2_n_0),
+ .I3(trn_rdst_rdy_reg_0),
+ .I4(trn_rdst_rdy_reg_1),
+ .I5(m_axis_rx_tready),
+ .O(trn_rdst_rdy_i_1_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair217" *)
+ LUT2 #(
+ .INIT(4'h1))
+ trn_rdst_rdy_i_2
+ (.I0(reg_dsc_detect_reg_0),
+ .I1(dsc_detect),
+ .O(trn_rdst_rdy_i_2_n_0));
+ FDRE trn_rdst_rdy_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(trn_rdst_rdy_i_1_n_0),
+ .Q(E),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE trn_recrc_err_prev_reg
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_recrc_err),
+ .Q(trn_recrc_err_prev),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE trn_reof_prev_reg
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_reof),
+ .Q(trn_reof_prev),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE trn_rerrfwd_prev_reg
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rerrfwd),
+ .Q(trn_rerrfwd_prev),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE \trn_rrem_prev_reg[0]
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rrem),
+ .Q(trn_rrem_prev),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE trn_rsof_prev_reg
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rsof),
+ .Q(trn_rsof_prev),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE trn_rsrc_dsc_d_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(trn_rsrc_dsc),
+ .Q(trn_rsrc_dsc_d),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE trn_rsrc_dsc_prev_reg
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(trn_rsrc_dsc_prev0),
+ .Q(trn_rsrc_dsc_prev),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+ FDRE trn_rsrc_rdy_prev_reg
+ (.C(pipe_userclk2_in),
+ .CE(E),
+ .D(rsrc_rdy_filtered),
+ .Q(trn_rsrc_rdy_prev),
+ .R(\trn_rbar_hit_prev_reg[0]_0 ));
+endmodule
+
+module pcie_7x_0_pcie_7x_0_axi_basic_top
+ (E,
+ trn_rsrc_dsc_d,
+ m_axis_rx_tvalid_reg,
+ m_axis_rx_tkeep,
+ m_axis_rx_tlast,
+ reg_tcfg_gnt,
+ tready_thrtl_reg,
+ trn_teof,
+ trn_tsrc_rdy,
+ trn_trem,
+ trn_in_packet,
+ reg_dsc_detect,
+ ppm_L1_thrtl,
+ lnk_up_thrtl,
+ m_axis_rx_tuser,
+ ppm_L1_trig,
+ cfg_pm_turnoff_ok_n,
+ trn_tcfg_gnt,
+ trn_tsof,
+ Q,
+ \throttle_ctl_pipeline.reg_tdata_reg[63] ,
+ \throttle_ctl_pipeline.reg_tuser_reg[3] ,
+ \throttle_ctl_pipeline.reg_tkeep_reg[7] ,
+ pipe_userclk2_in,
+ trn_rrem,
+ trn_rsrc_dsc,
+ rsrc_rdy_filtered,
+ trn_reof,
+ trn_rsrc_dsc_prev0,
+ trn_rsof,
+ trn_recrc_err,
+ trn_rerrfwd,
+ tx_cfg_gnt,
+ trn_tcfg_req,
+ trn_tdst_rdy,
+ tbuf_av_min_trig,
+ cfg_turnoff_ok,
+ s_axis_tx_tlast,
+ s_axis_tx_tvalid,
+ s_axis_tx_tkeep,
+ trn_in_packet_reg,
+ ppm_L1_thrtl_reg,
+ lnk_up_thrtl_reg,
+ m_axis_rx_tready,
+ dsc_detect,
+ out,
+ tcfg_req_trig,
+ tready_thrtl_i_5,
+ cfg_pcie_link_state,
+ s_axis_tx_tdata,
+ s_axis_tx_tuser,
+ trn_tbuf_av,
+ trn_rd,
+ trn_rbar_hit,
+ cfg_to_turnoff);
+ output [0:0]E;
+ output trn_rsrc_dsc_d;
+ output m_axis_rx_tvalid_reg;
+ output [0:0]m_axis_rx_tkeep;
+ output m_axis_rx_tlast;
+ output reg_tcfg_gnt;
+ output tready_thrtl_reg;
+ output trn_teof;
+ output trn_tsrc_rdy;
+ output [0:0]trn_trem;
+ output trn_in_packet;
+ output reg_dsc_detect;
+ output ppm_L1_thrtl;
+ output lnk_up_thrtl;
+ output [12:0]m_axis_rx_tuser;
+ output ppm_L1_trig;
+ output cfg_pm_turnoff_ok_n;
+ output trn_tcfg_gnt;
+ output trn_tsof;
+ output [63:0]Q;
+ output [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63] ;
+ output [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3] ;
+ input \throttle_ctl_pipeline.reg_tkeep_reg[7] ;
+ input pipe_userclk2_in;
+ input [0:0]trn_rrem;
+ input trn_rsrc_dsc;
+ input rsrc_rdy_filtered;
+ input trn_reof;
+ input trn_rsrc_dsc_prev0;
+ input trn_rsof;
+ input trn_recrc_err;
+ input trn_rerrfwd;
+ input tx_cfg_gnt;
+ input trn_tcfg_req;
+ input trn_tdst_rdy;
+ input tbuf_av_min_trig;
+ input cfg_turnoff_ok;
+ input s_axis_tx_tlast;
+ input s_axis_tx_tvalid;
+ input [0:0]s_axis_tx_tkeep;
+ input trn_in_packet_reg;
+ input ppm_L1_thrtl_reg;
+ input lnk_up_thrtl_reg;
+ input m_axis_rx_tready;
+ input dsc_detect;
+ input out;
+ input tcfg_req_trig;
+ input tready_thrtl_i_5;
+ input [2:0]cfg_pcie_link_state;
+ input [63:0]s_axis_tx_tdata;
+ input [3:0]s_axis_tx_tuser;
+ input [5:0]trn_tbuf_av;
+ input [63:0]trn_rd;
+ input [6:0]trn_rbar_hit;
+ input cfg_to_turnoff;
+
+ wire [0:0]E;
+ wire [63:0]Q;
+ wire [2:0]cfg_pcie_link_state;
+ wire cfg_pm_turnoff_ok_n;
+ wire cfg_to_turnoff;
+ wire cfg_turnoff_ok;
+ wire dsc_detect;
+ wire lnk_up_thrtl;
+ wire lnk_up_thrtl_reg;
+ wire [0:0]m_axis_rx_tkeep;
+ wire m_axis_rx_tlast;
+ wire m_axis_rx_tready;
+ wire [12:0]m_axis_rx_tuser;
+ wire m_axis_rx_tvalid_reg;
+ wire out;
+ wire pipe_userclk2_in;
+ wire ppm_L1_thrtl;
+ wire ppm_L1_thrtl_reg;
+ wire ppm_L1_trig;
+ wire reg_dsc_detect;
+ wire reg_tcfg_gnt;
+ wire rsrc_rdy_filtered;
+ wire [63:0]s_axis_tx_tdata;
+ wire [0:0]s_axis_tx_tkeep;
+ wire s_axis_tx_tlast;
+ wire [3:0]s_axis_tx_tuser;
+ wire s_axis_tx_tvalid;
+ wire tbuf_av_min_trig;
+ wire tcfg_req_trig;
+ wire [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63] ;
+ wire \throttle_ctl_pipeline.reg_tkeep_reg[7] ;
+ wire [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3] ;
+ wire tready_thrtl_i_5;
+ wire tready_thrtl_reg;
+ wire trn_in_packet;
+ wire trn_in_packet_reg;
+ wire [6:0]trn_rbar_hit;
+ wire [63:0]trn_rd;
+ wire trn_recrc_err;
+ wire trn_reof;
+ wire trn_rerrfwd;
+ wire [0:0]trn_rrem;
+ wire trn_rsof;
+ wire trn_rsrc_dsc;
+ wire trn_rsrc_dsc_d;
+ wire trn_rsrc_dsc_prev0;
+ wire [5:0]trn_tbuf_av;
+ wire trn_tcfg_gnt;
+ wire trn_tcfg_req;
+ wire trn_tdst_rdy;
+ wire trn_teof;
+ wire [0:0]trn_trem;
+ wire trn_tsof;
+ wire trn_tsrc_rdy;
+ wire tx_cfg_gnt;
+
+ pcie_7x_0_pcie_7x_0_axi_basic_rx rx_inst
+ (.E(E),
+ .Q(Q),
+ .dsc_detect(dsc_detect),
+ .m_axis_rx_tkeep(m_axis_rx_tkeep),
+ .m_axis_rx_tlast(m_axis_rx_tlast),
+ .m_axis_rx_tready(m_axis_rx_tready),
+ .m_axis_rx_tuser(m_axis_rx_tuser),
+ .m_axis_rx_tvalid_reg(m_axis_rx_tvalid_reg),
+ .pipe_userclk2_in(pipe_userclk2_in),
+ .reg_dsc_detect_reg(reg_dsc_detect),
+ .rsrc_rdy_filtered(rsrc_rdy_filtered),
+ .trn_in_packet(trn_in_packet),
+ .trn_in_packet_reg(trn_in_packet_reg),
+ .trn_rbar_hit(trn_rbar_hit),
+ .\trn_rbar_hit_prev_reg[0] (\throttle_ctl_pipeline.reg_tkeep_reg[7] ),
+ .trn_rd(trn_rd),
+ .trn_recrc_err(trn_recrc_err),
+ .trn_reof(trn_reof),
+ .trn_rerrfwd(trn_rerrfwd),
+ .trn_rrem(trn_rrem),
+ .trn_rsof(trn_rsof),
+ .trn_rsrc_dsc(trn_rsrc_dsc),
+ .trn_rsrc_dsc_d(trn_rsrc_dsc_d),
+ .trn_rsrc_dsc_prev0(trn_rsrc_dsc_prev0));
+ pcie_7x_0_pcie_7x_0_axi_basic_tx tx_inst
+ (.cfg_pcie_link_state(cfg_pcie_link_state),
+ .cfg_pm_turnoff_ok_n(cfg_pm_turnoff_ok_n),
+ .cfg_to_turnoff(cfg_to_turnoff),
+ .cfg_turnoff_ok(cfg_turnoff_ok),
+ .lnk_up_thrtl(lnk_up_thrtl),
+ .lnk_up_thrtl_reg(lnk_up_thrtl_reg),
+ .out(out),
+ .pipe_userclk2_in(pipe_userclk2_in),
+ .ppm_L1_thrtl(ppm_L1_thrtl),
+ .ppm_L1_thrtl_reg(ppm_L1_thrtl_reg),
+ .ppm_L1_trig(ppm_L1_trig),
+ .reg_tcfg_gnt(reg_tcfg_gnt),
+ .s_axis_tx_tdata(s_axis_tx_tdata),
+ .s_axis_tx_tkeep(s_axis_tx_tkeep),
+ .s_axis_tx_tlast(s_axis_tx_tlast),
+ .s_axis_tx_tuser(s_axis_tx_tuser),
+ .s_axis_tx_tvalid(s_axis_tx_tvalid),
+ .tbuf_av_min_trig(tbuf_av_min_trig),
+ .tcfg_req_trig(tcfg_req_trig),
+ .\throttle_ctl_pipeline.reg_tdata_reg[63] (\throttle_ctl_pipeline.reg_tdata_reg[63] ),
+ .\throttle_ctl_pipeline.reg_tkeep_reg[7] (\throttle_ctl_pipeline.reg_tkeep_reg[7] ),
+ .\throttle_ctl_pipeline.reg_tuser_reg[3] (\throttle_ctl_pipeline.reg_tuser_reg[3] ),
+ .tready_thrtl_i_5(tready_thrtl_i_5),
+ .tready_thrtl_reg(tready_thrtl_reg),
+ .trn_tbuf_av(trn_tbuf_av),
+ .trn_tcfg_gnt(trn_tcfg_gnt),
+ .trn_tcfg_req(trn_tcfg_req),
+ .trn_tdst_rdy(trn_tdst_rdy),
+ .trn_teof(trn_teof),
+ .trn_trem(trn_trem),
+ .trn_tsof(trn_tsof),
+ .trn_tsrc_rdy(trn_tsrc_rdy),
+ .tx_cfg_gnt(tx_cfg_gnt));
+endmodule
+
+module pcie_7x_0_pcie_7x_0_axi_basic_tx
+ (reg_tcfg_gnt,
+ tready_thrtl_reg,
+ trn_teof,
+ trn_tsrc_rdy,
+ trn_trem,
+ ppm_L1_thrtl,
+ lnk_up_thrtl,
+ ppm_L1_trig,
+ cfg_pm_turnoff_ok_n,
+ trn_tcfg_gnt,
+ trn_tsof,
+ \throttle_ctl_pipeline.reg_tdata_reg[63] ,
+ \throttle_ctl_pipeline.reg_tuser_reg[3] ,
+ \throttle_ctl_pipeline.reg_tkeep_reg[7] ,
+ tx_cfg_gnt,
+ pipe_userclk2_in,
+ trn_tcfg_req,
+ trn_tdst_rdy,
+ tbuf_av_min_trig,
+ cfg_turnoff_ok,
+ s_axis_tx_tlast,
+ s_axis_tx_tvalid,
+ s_axis_tx_tkeep,
+ ppm_L1_thrtl_reg,
+ lnk_up_thrtl_reg,
+ out,
+ tcfg_req_trig,
+ tready_thrtl_i_5,
+ cfg_pcie_link_state,
+ s_axis_tx_tdata,
+ s_axis_tx_tuser,
+ trn_tbuf_av,
+ cfg_to_turnoff);
+ output reg_tcfg_gnt;
+ output tready_thrtl_reg;
+ output trn_teof;
+ output trn_tsrc_rdy;
+ output [0:0]trn_trem;
+ output ppm_L1_thrtl;
+ output lnk_up_thrtl;
+ output ppm_L1_trig;
+ output cfg_pm_turnoff_ok_n;
+ output trn_tcfg_gnt;
+ output trn_tsof;
+ output [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63] ;
+ output [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3] ;
+ input \throttle_ctl_pipeline.reg_tkeep_reg[7] ;
+ input tx_cfg_gnt;
+ input pipe_userclk2_in;
+ input trn_tcfg_req;
+ input trn_tdst_rdy;
+ input tbuf_av_min_trig;
+ input cfg_turnoff_ok;
+ input s_axis_tx_tlast;
+ input s_axis_tx_tvalid;
+ input [0:0]s_axis_tx_tkeep;
+ input ppm_L1_thrtl_reg;
+ input lnk_up_thrtl_reg;
+ input out;
+ input tcfg_req_trig;
+ input tready_thrtl_i_5;
+ input [2:0]cfg_pcie_link_state;
+ input [63:0]s_axis_tx_tdata;
+ input [3:0]s_axis_tx_tuser;
+ input [5:0]trn_tbuf_av;
+ input cfg_to_turnoff;
+
+ wire axi_in_packet;
+ wire [2:0]cfg_pcie_link_state;
+ wire cfg_pm_turnoff_ok_n;
+ wire cfg_to_turnoff;
+ wire cfg_turnoff_ok;
+ wire lnk_up_thrtl;
+ wire lnk_up_thrtl_reg;
+ wire out;
+ wire pipe_userclk2_in;
+ wire ppm_L1_thrtl;
+ wire ppm_L1_thrtl_reg;
+ wire ppm_L1_trig;
+ wire reg_disable_trn;
+ wire reg_tcfg_gnt;
+ wire reg_tsrc_rdy0;
+ wire [63:0]s_axis_tx_tdata;
+ wire [0:0]s_axis_tx_tkeep;
+ wire s_axis_tx_tlast;
+ wire [3:0]s_axis_tx_tuser;
+ wire s_axis_tx_tvalid;
+ wire tbuf_av_min_trig;
+ wire tcfg_req_trig;
+ wire [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63] ;
+ wire \throttle_ctl_pipeline.reg_tkeep_reg[7] ;
+ wire [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3] ;
+ wire \thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4 ;
+ wire tready_thrtl_i_5;
+ wire tready_thrtl_reg;
+ wire [5:0]trn_tbuf_av;
+ wire trn_tcfg_gnt;
+ wire trn_tcfg_req;
+ wire trn_tdst_rdy;
+ wire trn_teof;
+ wire [0:0]trn_trem;
+ wire trn_tsof;
+ wire trn_tsrc_rdy;
+ wire tx_cfg_gnt;
+
+ pcie_7x_0_pcie_7x_0_axi_basic_tx_thrtl_ctl \thrtl_ctl_enabled.tx_thrl_ctl_inst
+ (.axi_in_packet(axi_in_packet),
+ .cfg_pcie_link_state(cfg_pcie_link_state),
+ .cfg_pm_turnoff_ok_n(cfg_pm_turnoff_ok_n),
+ .cfg_to_turnoff(cfg_to_turnoff),
+ .cfg_turnoff_ok(cfg_turnoff_ok),
+ .lnk_up_thrtl(lnk_up_thrtl),
+ .lnk_up_thrtl_reg_0(lnk_up_thrtl_reg),
+ .out(out),
+ .pipe_userclk2_in(pipe_userclk2_in),
+ .ppm_L1_thrtl(ppm_L1_thrtl),
+ .ppm_L1_thrtl_reg_0(ppm_L1_thrtl_reg),
+ .ppm_L1_trig(ppm_L1_trig),
+ .reg_disable_trn(reg_disable_trn),
+ .reg_tcfg_gnt(reg_tcfg_gnt),
+ .reg_tsrc_rdy0(reg_tsrc_rdy0),
+ .s_axis_tx_tdata({s_axis_tx_tdata[30:29],s_axis_tx_tdata[15],s_axis_tx_tdata[0]}),
+ .s_axis_tx_tlast(s_axis_tx_tlast),
+ .s_axis_tx_tlast_0(\thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4 ),
+ .s_axis_tx_tuser(s_axis_tx_tuser[0]),
+ .s_axis_tx_tvalid(s_axis_tx_tvalid),
+ .tbuf_av_min_trig(tbuf_av_min_trig),
+ .\tbuf_gap_cnt_reg[0]_0 (\throttle_ctl_pipeline.reg_tkeep_reg[7] ),
+ .tcfg_req_trig(tcfg_req_trig),
+ .tready_thrtl_i_5_0(tready_thrtl_i_5),
+ .tready_thrtl_reg_0(tready_thrtl_reg),
+ .trn_tbuf_av(trn_tbuf_av),
+ .trn_tcfg_gnt(trn_tcfg_gnt),
+ .trn_tcfg_req(trn_tcfg_req),
+ .trn_tdst_rdy(trn_tdst_rdy),
+ .tx_cfg_gnt(tx_cfg_gnt));
+ pcie_7x_0_pcie_7x_0_axi_basic_tx_pipeline tx_pipeline_inst
+ (.axi_in_packet(axi_in_packet),
+ .axi_in_packet_reg_0(\thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4 ),
+ .out(out),
+ .pipe_userclk2_in(pipe_userclk2_in),
+ .reg_disable_trn(reg_disable_trn),
+ .reg_tsrc_rdy0(reg_tsrc_rdy0),
+ .s_axis_tx_tdata(s_axis_tx_tdata),
+ .s_axis_tx_tkeep(s_axis_tx_tkeep),
+ .s_axis_tx_tlast(s_axis_tx_tlast),
+ .s_axis_tx_tuser(s_axis_tx_tuser),
+ .s_axis_tx_tvalid(s_axis_tx_tvalid),
+ .\throttle_ctl_pipeline.reg_tdata_reg[63]_0 (\throttle_ctl_pipeline.reg_tdata_reg[63] ),
+ .\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 (\throttle_ctl_pipeline.reg_tkeep_reg[7] ),
+ .\throttle_ctl_pipeline.reg_tuser_reg[3]_0 (\throttle_ctl_pipeline.reg_tuser_reg[3] ),
+ .\thrtl_ctl_trn_flush.reg_disable_trn_reg_0 (tready_thrtl_reg),
+ .trn_tdst_rdy(trn_tdst_rdy),
+ .trn_teof(trn_teof),
+ .trn_trem(trn_trem),
+ .trn_tsof(trn_tsof),
+ .trn_tsrc_rdy(trn_tsrc_rdy));
+endmodule
+
+module pcie_7x_0_pcie_7x_0_axi_basic_tx_pipeline
+ (trn_teof,
+ trn_tsrc_rdy,
+ trn_trem,
+ axi_in_packet,
+ reg_disable_trn,
+ trn_tsof,
+ \throttle_ctl_pipeline.reg_tdata_reg[63]_0 ,
+ \throttle_ctl_pipeline.reg_tuser_reg[3]_0 ,
+ \throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ,
+ s_axis_tx_tlast,
+ pipe_userclk2_in,
+ reg_tsrc_rdy0,
+ s_axis_tx_tvalid,
+ s_axis_tx_tkeep,
+ axi_in_packet_reg_0,
+ out,
+ \thrtl_ctl_trn_flush.reg_disable_trn_reg_0 ,
+ trn_tdst_rdy,
+ s_axis_tx_tdata,
+ s_axis_tx_tuser);
+ output trn_teof;
+ output trn_tsrc_rdy;
+ output [0:0]trn_trem;
+ output axi_in_packet;
+ output reg_disable_trn;
+ output trn_tsof;
+ output [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63]_0 ;
+ output [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3]_0 ;
+ input \throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ;
+ input s_axis_tx_tlast;
+ input pipe_userclk2_in;
+ input reg_tsrc_rdy0;
+ input s_axis_tx_tvalid;
+ input [0:0]s_axis_tx_tkeep;
+ input axi_in_packet_reg_0;
+ input out;
+ input \thrtl_ctl_trn_flush.reg_disable_trn_reg_0 ;
+ input trn_tdst_rdy;
+ input [63:0]s_axis_tx_tdata;
+ input [3:0]s_axis_tx_tuser;
+
+ wire axi_in_packet;
+ wire axi_in_packet_reg_0;
+ wire out;
+ wire pipe_userclk2_in;
+ wire reg_disable_trn;
+ wire reg_tsrc_rdy0;
+ wire reg_tvalid;
+ wire [63:0]s_axis_tx_tdata;
+ wire [0:0]s_axis_tx_tkeep;
+ wire s_axis_tx_tlast;
+ wire [3:0]s_axis_tx_tuser;
+ wire s_axis_tx_tvalid;
+ wire [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63]_0 ;
+ wire \throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ;
+ wire [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3]_0 ;
+ wire \thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0 ;
+ wire \thrtl_ctl_trn_flush.reg_disable_trn_reg_0 ;
+ wire trn_in_packet;
+ wire trn_in_packet_i_1__0_n_0;
+ wire trn_tdst_rdy;
+ wire trn_teof;
+ wire [0:0]trn_trem;
+ wire trn_tsof;
+ wire trn_tsrc_rdy;
+
+ FDRE axi_in_packet_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(axi_in_packet_reg_0),
+ .Q(axi_in_packet),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ pcie_block_i_i_31
+ (.I0(reg_tvalid),
+ .I1(trn_in_packet),
+ .O(trn_tsof));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[0]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[0]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [0]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[10]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[10]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [10]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[11]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[11]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [11]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[12]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[12]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [12]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[13]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[13]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [13]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[14]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[14]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [14]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[15]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[15]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [15]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[16]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[16]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [16]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[17]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[17]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [17]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[18]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[18]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [18]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[19]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[19]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [19]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[1]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[1]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [1]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[20]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[20]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [20]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[21]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[21]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [21]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[22]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[22]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [22]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[23]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[23]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [23]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[24]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[24]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [24]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[25]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[25]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [25]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[26]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[26]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [26]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[27]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[27]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [27]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[28]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[28]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [28]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[29]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[29]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [29]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[2]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[2]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [2]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[30]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[30]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [30]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[31]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[31]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [31]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[32]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[32]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [32]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[33]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[33]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [33]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[34]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[34]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [34]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[35]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[35]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [35]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[36]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[36]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [36]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[37]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[37]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [37]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[38]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[38]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [38]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[39]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[39]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [39]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[3]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[3]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [3]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[40]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[40]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [40]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[41]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[41]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [41]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[42]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[42]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [42]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[43]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[43]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [43]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[44]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[44]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [44]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[45]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[45]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [45]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[46]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[46]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [46]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[47]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[47]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [47]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[48]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[48]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [48]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[49]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[49]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [49]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[4]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[4]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [4]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[50]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[50]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [50]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[51]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[51]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [51]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[52]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[52]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [52]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[53]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[53]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [53]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[54]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[54]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [54]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[55]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[55]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [55]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[56]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[56]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [56]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[57]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[57]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [57]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[58]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[58]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [58]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[59]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[59]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [59]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[5]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[5]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [5]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[60]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[60]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [60]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[61]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[61]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [61]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[62]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[62]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [62]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[63]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[63]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [63]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[6]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[6]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [6]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[7]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[7]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [7]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[8]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[8]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [8]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tdata_reg[9]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tdata[9]),
+ .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [9]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tkeep_reg[7]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tkeep),
+ .Q(trn_trem),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tlast_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tlast),
+ .Q(trn_teof),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tsrc_rdy_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(reg_tsrc_rdy0),
+ .Q(trn_tsrc_rdy),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tuser_reg[0]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tuser[0]),
+ .Q(\throttle_ctl_pipeline.reg_tuser_reg[3]_0 [0]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tuser_reg[1]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tuser[1]),
+ .Q(\throttle_ctl_pipeline.reg_tuser_reg[3]_0 [1]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tuser_reg[2]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tuser[2]),
+ .Q(\throttle_ctl_pipeline.reg_tuser_reg[3]_0 [2]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tuser_reg[3]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tuser[3]),
+ .Q(\throttle_ctl_pipeline.reg_tuser_reg[3]_0 [3]),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ FDRE \throttle_ctl_pipeline.reg_tvalid_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(s_axis_tx_tvalid),
+ .Q(reg_tvalid),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ LUT6 #(
+ .INIT(64'h0FFFFFFF04444444))
+ \thrtl_ctl_trn_flush.reg_disable_trn_i_1
+ (.I0(out),
+ .I1(axi_in_packet),
+ .I2(\thrtl_ctl_trn_flush.reg_disable_trn_reg_0 ),
+ .I3(s_axis_tx_tvalid),
+ .I4(s_axis_tx_tlast),
+ .I5(reg_disable_trn),
+ .O(\thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0 ));
+ FDRE \thrtl_ctl_trn_flush.reg_disable_trn_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(\thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0 ),
+ .Q(reg_disable_trn),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+ LUT6 #(
+ .INIT(64'h0000F088F000F000))
+ trn_in_packet_i_1__0
+ (.I0(trn_tdst_rdy),
+ .I1(reg_tvalid),
+ .I2(out),
+ .I3(trn_in_packet),
+ .I4(trn_teof),
+ .I5(trn_tsrc_rdy),
+ .O(trn_in_packet_i_1__0_n_0));
+ FDRE trn_in_packet_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(trn_in_packet_i_1__0_n_0),
+ .Q(trn_in_packet),
+ .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
+endmodule
+
+module pcie_7x_0_pcie_7x_0_axi_basic_tx_thrtl_ctl
+ (reg_tcfg_gnt,
+ tready_thrtl_reg_0,
+ ppm_L1_thrtl,
+ lnk_up_thrtl,
+ s_axis_tx_tlast_0,
+ ppm_L1_trig,
+ cfg_pm_turnoff_ok_n,
+ trn_tcfg_gnt,
+ reg_tsrc_rdy0,
+ \tbuf_gap_cnt_reg[0]_0 ,
+ tx_cfg_gnt,
+ pipe_userclk2_in,
+ trn_tcfg_req,
+ trn_tdst_rdy,
+ tbuf_av_min_trig,
+ cfg_turnoff_ok,
+ ppm_L1_thrtl_reg_0,
+ lnk_up_thrtl_reg_0,
+ s_axis_tx_tlast,
+ s_axis_tx_tvalid,
+ axi_in_packet,
+ out,
+ tcfg_req_trig,
+ tready_thrtl_i_5_0,
+ cfg_pcie_link_state,
+ s_axis_tx_tdata,
+ s_axis_tx_tuser,
+ reg_disable_trn,
+ trn_tbuf_av,
+ cfg_to_turnoff);
+ output reg_tcfg_gnt;
+ output tready_thrtl_reg_0;
+ output ppm_L1_thrtl;
+ output lnk_up_thrtl;
+ output s_axis_tx_tlast_0;
+ output ppm_L1_trig;
+ output cfg_pm_turnoff_ok_n;
+ output trn_tcfg_gnt;
+ output reg_tsrc_rdy0;
+ input \tbuf_gap_cnt_reg[0]_0 ;
+ input tx_cfg_gnt;
+ input pipe_userclk2_in;
+ input trn_tcfg_req;
+ input trn_tdst_rdy;
+ input tbuf_av_min_trig;
+ input cfg_turnoff_ok;
+ input ppm_L1_thrtl_reg_0;
+ input lnk_up_thrtl_reg_0;
+ input s_axis_tx_tlast;
+ input s_axis_tx_tvalid;
+ input axi_in_packet;
+ input out;
+ input tcfg_req_trig;
+ input tready_thrtl_i_5_0;
+ input [2:0]cfg_pcie_link_state;
+ input [3:0]s_axis_tx_tdata;
+ input [0:0]s_axis_tx_tuser;
+ input reg_disable_trn;
+ input [5:0]trn_tbuf_av;
+ input cfg_to_turnoff;
+
+ wire \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ;
+ wire \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1_n_0 ;
+ wire axi_in_packet;
+ wire [2:0]cfg_pcie_link_state;
+ wire [2:0]cfg_pcie_link_state_d;
+ wire cfg_pm_turnoff_ok_n;
+ wire cfg_to_turnoff;
+ wire cfg_turnoff_ok;
+ wire cfg_turnoff_ok_pending;
+ wire cfg_turnoff_ok_pending_i_1_n_0;
+ wire cur_state;
+ wire cur_state_i_2_n_0;
+ wire \ecrc_pause_enabled.reg_tx_ecrc_pkt ;
+ wire \ecrc_pause_enabled.reg_tx_ecrc_pkt021_out ;
+ wire \ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1_n_0 ;
+ wire lnk_up_thrtl;
+ wire lnk_up_thrtl_reg_0;
+ wire next_state;
+ wire out;
+ wire p_2_in;
+ wire pcie_block_i_i_36_n_0;
+ wire pipe_userclk2_in;
+ wire ppm_L1_thrtl;
+ wire ppm_L1_thrtl_reg_0;
+ wire ppm_L1_trig;
+ wire ppm_L23_thrtl;
+ wire ppm_L23_thrtl_i_1_n_0;
+ wire ppm_L23_trig;
+ wire reg_axi_in_pkt;
+ wire reg_axi_in_pkt_i_1_n_0;
+ wire reg_disable_trn;
+ wire reg_tcfg_gnt;
+ wire reg_tsrc_rdy0;
+ wire reg_turnoff_ok;
+ wire [3:0]s_axis_tx_tdata;
+ wire s_axis_tx_tlast;
+ wire s_axis_tx_tlast_0;
+ wire [0:0]s_axis_tx_tuser;
+ wire s_axis_tx_tvalid;
+ wire [5:0]tbuf_av_d;
+ wire tbuf_av_gap_thrtl;
+ wire tbuf_av_gap_thrtl_i_1_n_0;
+ wire tbuf_av_gap_trig;
+ wire tbuf_av_min_thrtl;
+ wire tbuf_av_min_trig;
+ wire \tbuf_gap_cnt[0]_i_1_n_0 ;
+ wire \tbuf_gap_cnt_reg[0]_0 ;
+ wire \tbuf_gap_cnt_reg_n_0_[0] ;
+ wire tcfg_gnt_pending;
+ wire tcfg_gnt_pending_i_1_n_0;
+ wire [1:0]tcfg_req_cnt;
+ wire \tcfg_req_cnt[0]_i_1_n_0 ;
+ wire \tcfg_req_cnt[1]_i_1_n_0 ;
+ wire tcfg_req_thrtl;
+ wire tcfg_req_thrtl_i_1_n_0;
+ wire tcfg_req_trig;
+ wire tready_thrtl0;
+ wire tready_thrtl_i_10_n_0;
+ wire tready_thrtl_i_12_n_0;
+ wire tready_thrtl_i_2_n_0;
+ wire tready_thrtl_i_3_n_0;
+ wire tready_thrtl_i_4_n_0;
+ wire tready_thrtl_i_5_0;
+ wire tready_thrtl_i_6_n_0;
+ wire tready_thrtl_i_7_n_0;
+ wire tready_thrtl_reg_0;
+ wire [5:0]trn_tbuf_av;
+ wire trn_tcfg_gnt;
+ wire trn_tcfg_req;
+ wire trn_tcfg_req_d;
+ wire trn_tdst_rdy;
+ wire trn_tdst_rdy_d;
+ wire tx_cfg_gnt;
+
+ FDRE \L23_thrtl_ep.reg_turnoff_ok_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(cfg_turnoff_ok),
+ .Q(reg_turnoff_ok),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair255" *)
+ LUT2 #(
+ .INIT(4'hE))
+ \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1
+ (.I0(cfg_to_turnoff),
+ .I1(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ),
+ .O(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1_n_0 ));
+ FDRE \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1_n_0 ),
+ .Q(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ LUT4 #(
+ .INIT(16'h7F40))
+ axi_in_packet_i_1
+ (.I0(s_axis_tx_tlast),
+ .I1(s_axis_tx_tvalid),
+ .I2(tready_thrtl_reg_0),
+ .I3(axi_in_packet),
+ .O(s_axis_tx_tlast_0));
+ FDRE \cfg_pcie_link_state_d_reg[0]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(cfg_pcie_link_state[0]),
+ .Q(cfg_pcie_link_state_d[0]),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ FDRE \cfg_pcie_link_state_d_reg[1]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(cfg_pcie_link_state[1]),
+ .Q(cfg_pcie_link_state_d[1]),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ FDRE \cfg_pcie_link_state_d_reg[2]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(cfg_pcie_link_state[2]),
+ .Q(cfg_pcie_link_state_d[2]),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair252" *)
+ LUT5 #(
+ .INIT(32'h75553000))
+ cfg_turnoff_ok_pending_i_1
+ (.I0(cfg_pm_turnoff_ok_n),
+ .I1(ppm_L23_thrtl),
+ .I2(reg_turnoff_ok),
+ .I3(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ),
+ .I4(cfg_turnoff_ok_pending),
+ .O(cfg_turnoff_ok_pending_i_1_n_0));
+ FDRE cfg_turnoff_ok_pending_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(cfg_turnoff_ok_pending_i_1_n_0),
+ .Q(cfg_turnoff_ok_pending),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ LUT6 #(
+ .INIT(64'h5455445554555555))
+ cur_state_i_1__0
+ (.I0(cur_state_i_2_n_0),
+ .I1(cur_state),
+ .I2(s_axis_tx_tlast),
+ .I3(tready_thrtl_reg_0),
+ .I4(s_axis_tx_tvalid),
+ .I5(reg_axi_in_pkt),
+ .O(next_state));
+ LUT6 #(
+ .INIT(64'h0000000000000001))
+ cur_state_i_2
+ (.I0(ppm_L1_thrtl),
+ .I1(lnk_up_thrtl),
+ .I2(tcfg_req_thrtl),
+ .I3(ppm_L23_thrtl),
+ .I4(tbuf_av_gap_thrtl),
+ .I5(tbuf_av_min_thrtl),
+ .O(cur_state_i_2_n_0));
+ FDSE cur_state_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(next_state),
+ .Q(cur_state),
+ .S(\tbuf_gap_cnt_reg[0]_0 ));
+ LUT5 #(
+ .INIT(32'hBFFFAAAA))
+ \ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1
+ (.I0(\ecrc_pause_enabled.reg_tx_ecrc_pkt021_out ),
+ .I1(tready_thrtl_reg_0),
+ .I2(s_axis_tx_tvalid),
+ .I3(s_axis_tx_tlast),
+ .I4(\ecrc_pause_enabled.reg_tx_ecrc_pkt ),
+ .O(\ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair253" *)
+ LUT5 #(
+ .INIT(32'h00001444))
+ \ecrc_pause_enabled.reg_tx_ecrc_pkt_i_2
+ (.I0(tready_thrtl_i_7_n_0),
+ .I1(s_axis_tx_tdata[2]),
+ .I2(s_axis_tx_tdata[3]),
+ .I3(s_axis_tx_tdata[0]),
+ .I4(s_axis_tx_tlast),
+ .O(\ecrc_pause_enabled.reg_tx_ecrc_pkt021_out ));
+ FDRE \ecrc_pause_enabled.reg_tx_ecrc_pkt_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(\ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1_n_0 ),
+ .Q(\ecrc_pause_enabled.reg_tx_ecrc_pkt ),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ FDSE lnk_up_thrtl_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(lnk_up_thrtl_reg_0),
+ .Q(lnk_up_thrtl),
+ .S(\tbuf_gap_cnt_reg[0]_0 ));
+ LUT6 #(
+ .INIT(64'h20202020A0AFA0A0))
+ pcie_block_i_i_26
+ (.I0(cfg_turnoff_ok_pending),
+ .I1(tcfg_gnt_pending),
+ .I2(cur_state),
+ .I3(pcie_block_i_i_36_n_0),
+ .I4(ppm_L23_thrtl),
+ .I5(tcfg_req_thrtl),
+ .O(cfg_pm_turnoff_ok_n));
+ (* SOFT_HLUTNM = "soft_lutpair254" *)
+ LUT4 #(
+ .INIT(16'hA202))
+ pcie_block_i_i_30
+ (.I0(tcfg_req_thrtl),
+ .I1(pcie_block_i_i_36_n_0),
+ .I2(cur_state),
+ .I3(tcfg_gnt_pending),
+ .O(trn_tcfg_gnt));
+ (* SOFT_HLUTNM = "soft_lutpair250" *)
+ LUT5 #(
+ .INIT(32'hFFFF20E0))
+ pcie_block_i_i_36
+ (.I0(reg_axi_in_pkt),
+ .I1(s_axis_tx_tvalid),
+ .I2(tready_thrtl_reg_0),
+ .I3(s_axis_tx_tlast),
+ .I4(cur_state_i_2_n_0),
+ .O(pcie_block_i_i_36_n_0));
+ LUT6 #(
+ .INIT(64'h0000010000000000))
+ ppm_L1_thrtl_i_2
+ (.I0(cfg_pcie_link_state_d[1]),
+ .I1(cfg_pcie_link_state_d[2]),
+ .I2(cfg_pcie_link_state_d[0]),
+ .I3(cfg_pcie_link_state[0]),
+ .I4(cfg_pcie_link_state[1]),
+ .I5(cfg_pcie_link_state[2]),
+ .O(ppm_L1_trig));
+ FDRE ppm_L1_thrtl_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(ppm_L1_thrtl_reg_0),
+ .Q(ppm_L1_thrtl),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair252" *)
+ LUT3 #(
+ .INIT(8'hF8))
+ ppm_L23_thrtl_i_1
+ (.I0(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ),
+ .I1(reg_turnoff_ok),
+ .I2(ppm_L23_thrtl),
+ .O(ppm_L23_thrtl_i_1_n_0));
+ FDRE ppm_L23_thrtl_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(ppm_L23_thrtl_i_1_n_0),
+ .Q(ppm_L23_thrtl),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ LUT5 #(
+ .INIT(32'h00005F40))
+ reg_axi_in_pkt_i_1
+ (.I0(s_axis_tx_tlast),
+ .I1(tready_thrtl_reg_0),
+ .I2(s_axis_tx_tvalid),
+ .I3(reg_axi_in_pkt),
+ .I4(\tbuf_gap_cnt_reg[0]_0 ),
+ .O(reg_axi_in_pkt_i_1_n_0));
+ FDRE reg_axi_in_pkt_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(reg_axi_in_pkt_i_1_n_0),
+ .Q(reg_axi_in_pkt),
+ .R(1'b0));
+ FDRE reg_tcfg_gnt_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(tx_cfg_gnt),
+ .Q(reg_tcfg_gnt),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ FDRE \tbuf_av_d_reg[0]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(trn_tbuf_av[0]),
+ .Q(tbuf_av_d[0]),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ FDRE \tbuf_av_d_reg[1]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(trn_tbuf_av[1]),
+ .Q(tbuf_av_d[1]),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ FDRE \tbuf_av_d_reg[2]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(trn_tbuf_av[2]),
+ .Q(tbuf_av_d[2]),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ FDRE \tbuf_av_d_reg[3]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(trn_tbuf_av[3]),
+ .Q(tbuf_av_d[3]),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ FDRE \tbuf_av_d_reg[4]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(trn_tbuf_av[4]),
+ .Q(tbuf_av_d[4]),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ FDRE \tbuf_av_d_reg[5]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(trn_tbuf_av[5]),
+ .Q(tbuf_av_d[5]),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ LUT3 #(
+ .INIT(8'hEA))
+ tbuf_av_gap_thrtl_i_1
+ (.I0(tbuf_av_gap_trig),
+ .I1(\tbuf_gap_cnt_reg_n_0_[0] ),
+ .I2(tbuf_av_gap_thrtl),
+ .O(tbuf_av_gap_thrtl_i_1_n_0));
+ FDRE tbuf_av_gap_thrtl_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(tbuf_av_gap_thrtl_i_1_n_0),
+ .Q(tbuf_av_gap_thrtl),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ FDRE tbuf_av_min_thrtl_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(tbuf_av_min_trig),
+ .Q(tbuf_av_min_thrtl),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair254" *)
+ LUT2 #(
+ .INIT(4'h7))
+ \tbuf_gap_cnt[0]_i_1
+ (.I0(tbuf_av_gap_thrtl),
+ .I1(cur_state),
+ .O(\tbuf_gap_cnt[0]_i_1_n_0 ));
+ FDRE \tbuf_gap_cnt_reg[0]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(\tbuf_gap_cnt[0]_i_1_n_0 ),
+ .Q(\tbuf_gap_cnt_reg_n_0_[0] ),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ LUT6 #(
+ .INIT(64'h44F44444F4F4F4F4))
+ tcfg_gnt_pending_i_1
+ (.I0(trn_tcfg_req_d),
+ .I1(trn_tcfg_req),
+ .I2(tcfg_gnt_pending),
+ .I3(cur_state),
+ .I4(pcie_block_i_i_36_n_0),
+ .I5(tcfg_req_thrtl),
+ .O(tcfg_gnt_pending_i_1_n_0));
+ FDRE tcfg_gnt_pending_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(tcfg_gnt_pending_i_1_n_0),
+ .Q(tcfg_gnt_pending),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000D00))
+ \tcfg_req_cnt[0]_i_1
+ (.I0(trn_tcfg_req),
+ .I1(trn_tcfg_req_d),
+ .I2(tcfg_gnt_pending),
+ .I3(tcfg_req_cnt[1]),
+ .I4(tcfg_req_cnt[0]),
+ .I5(\tbuf_gap_cnt_reg[0]_0 ),
+ .O(\tcfg_req_cnt[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair251" *)
+ LUT5 #(
+ .INIT(32'hFFFF88F8))
+ \tcfg_req_cnt[1]_i_1
+ (.I0(tcfg_req_cnt[0]),
+ .I1(tcfg_req_cnt[1]),
+ .I2(trn_tcfg_req),
+ .I3(trn_tcfg_req_d),
+ .I4(tcfg_gnt_pending),
+ .O(\tcfg_req_cnt[1]_i_1_n_0 ));
+ FDRE \tcfg_req_cnt_reg[0]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(\tcfg_req_cnt[0]_i_1_n_0 ),
+ .Q(tcfg_req_cnt[0]),
+ .R(1'b0));
+ FDRE \tcfg_req_cnt_reg[1]
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(\tcfg_req_cnt[1]_i_1_n_0 ),
+ .Q(tcfg_req_cnt[1]),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFF8FF88888888))
+ tcfg_req_thrtl_i_1
+ (.I0(reg_tcfg_gnt),
+ .I1(trn_tcfg_req),
+ .I2(trn_tdst_rdy_d),
+ .I3(trn_tdst_rdy),
+ .I4(p_2_in),
+ .I5(tcfg_req_thrtl),
+ .O(tcfg_req_thrtl_i_1_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair251" *)
+ LUT2 #(
+ .INIT(4'hE))
+ tcfg_req_thrtl_i_2
+ (.I0(tcfg_req_cnt[1]),
+ .I1(tcfg_req_cnt[0]),
+ .O(p_2_in));
+ FDRE tcfg_req_thrtl_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(tcfg_req_thrtl_i_1_n_0),
+ .Q(tcfg_req_thrtl),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ LUT4 #(
+ .INIT(16'h0080))
+ \throttle_ctl_pipeline.reg_tsrc_rdy_i_1
+ (.I0(tready_thrtl_reg_0),
+ .I1(s_axis_tx_tvalid),
+ .I2(out),
+ .I3(reg_disable_trn),
+ .O(reg_tsrc_rdy0));
+ LUT6 #(
+ .INIT(64'hF1F1F1F10000F100))
+ tready_thrtl_i_1
+ (.I0(\ecrc_pause_enabled.reg_tx_ecrc_pkt ),
+ .I1(tready_thrtl_i_2_n_0),
+ .I2(tready_thrtl_i_3_n_0),
+ .I3(tready_thrtl_i_4_n_0),
+ .I4(tbuf_av_gap_trig),
+ .I5(tready_thrtl_i_6_n_0),
+ .O(tready_thrtl0));
+ LUT6 #(
+ .INIT(64'h00002000AAAAAAAA))
+ tready_thrtl_i_10
+ (.I0(tready_thrtl_i_5_0),
+ .I1(tbuf_av_d[4]),
+ .I2(tbuf_av_d[0]),
+ .I3(tbuf_av_d[1]),
+ .I4(tready_thrtl_i_12_n_0),
+ .I5(tready_thrtl_i_3_n_0),
+ .O(tready_thrtl_i_10_n_0));
+ LUT4 #(
+ .INIT(16'hFFEF))
+ tready_thrtl_i_12
+ (.I0(tbuf_av_d[5]),
+ .I1(tbuf_av_d[2]),
+ .I2(trn_tbuf_av[1]),
+ .I3(tbuf_av_d[3]),
+ .O(tready_thrtl_i_12_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair253" *)
+ LUT4 #(
+ .INIT(16'h0078))
+ tready_thrtl_i_2
+ (.I0(s_axis_tx_tdata[0]),
+ .I1(s_axis_tx_tdata[3]),
+ .I2(s_axis_tx_tdata[2]),
+ .I3(tready_thrtl_i_7_n_0),
+ .O(tready_thrtl_i_2_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair250" *)
+ LUT3 #(
+ .INIT(8'h7F))
+ tready_thrtl_i_3
+ (.I0(s_axis_tx_tlast),
+ .I1(s_axis_tx_tvalid),
+ .I2(tready_thrtl_reg_0),
+ .O(tready_thrtl_i_3_n_0));
+ LUT6 #(
+ .INIT(64'h0000000000040000))
+ tready_thrtl_i_4
+ (.I0(ppm_L23_trig),
+ .I1(out),
+ .I2(tcfg_req_trig),
+ .I3(ppm_L1_trig),
+ .I4(cur_state_i_2_n_0),
+ .I5(tbuf_av_min_trig),
+ .O(tready_thrtl_i_4_n_0));
+ LUT6 #(
+ .INIT(64'hFFFFFFFF00100000))
+ tready_thrtl_i_5
+ (.I0(tcfg_req_cnt[0]),
+ .I1(tcfg_req_cnt[1]),
+ .I2(trn_tdst_rdy),
+ .I3(trn_tdst_rdy_d),
+ .I4(tcfg_req_thrtl),
+ .I5(tready_thrtl_i_10_n_0),
+ .O(tbuf_av_gap_trig));
+ LUT5 #(
+ .INIT(32'h000020E0))
+ tready_thrtl_i_6
+ (.I0(reg_axi_in_pkt),
+ .I1(s_axis_tx_tvalid),
+ .I2(tready_thrtl_reg_0),
+ .I3(s_axis_tx_tlast),
+ .I4(cur_state),
+ .O(tready_thrtl_i_6_n_0));
+ LUT5 #(
+ .INIT(32'hFFFFDFFF))
+ tready_thrtl_i_7
+ (.I0(s_axis_tx_tuser),
+ .I1(s_axis_tx_tdata[1]),
+ .I2(s_axis_tx_tvalid),
+ .I3(tready_thrtl_reg_0),
+ .I4(reg_axi_in_pkt),
+ .O(tready_thrtl_i_7_n_0));
+ (* SOFT_HLUTNM = "soft_lutpair255" *)
+ LUT2 #(
+ .INIT(4'h8))
+ tready_thrtl_i_8
+ (.I0(reg_turnoff_ok),
+ .I1(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ),
+ .O(ppm_L23_trig));
+ FDRE tready_thrtl_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(tready_thrtl0),
+ .Q(tready_thrtl_reg_0),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ FDRE trn_tcfg_req_d_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(trn_tcfg_req),
+ .Q(trn_tcfg_req_d),
+ .R(\tbuf_gap_cnt_reg[0]_0 ));
+ FDSE trn_tdst_rdy_d_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(trn_tdst_rdy),
+ .Q(trn_tdst_rdy_d),
+ .S(\tbuf_gap_cnt_reg[0]_0 ));
+endmodule
+
+module pcie_7x_0_pcie_7x_0_core_top
+ (pl_ltssm_state,
+ pl_phy_lnk_up,
+ user_reset_out,
+ m_axis_rx_tvalid,
+ s_axis_tx_tready,
+ cfg_aer_ecrc_check_en,
+ cfg_aer_ecrc_gen_en,
+ cfg_aer_rooterr_corr_err_received,
+ cfg_aer_rooterr_corr_err_reporting_en,
+ cfg_aer_rooterr_fatal_err_received,
+ cfg_aer_rooterr_fatal_err_reporting_en,
+ cfg_aer_rooterr_non_fatal_err_received,
+ cfg_aer_rooterr_non_fatal_err_reporting_en,
+ cfg_bridge_serr_en,
+ cfg_command,
+ cfg_dcommand2,
+ cfg_dcommand,
+ cfg_dstatus,
+ cfg_interrupt_msienable,
+ cfg_interrupt_msixenable,
+ cfg_interrupt_msixfm,
+ cfg_lcommand,
+ cfg_lstatus,
+ cfg_msg_received,
+ cfg_msg_received_assert_int_a,
+ cfg_msg_received_assert_int_b,
+ cfg_msg_received_assert_int_c,
+ cfg_msg_received_assert_int_d,
+ cfg_msg_received_deassert_int_a,
+ cfg_msg_received_deassert_int_b,
+ cfg_msg_received_deassert_int_c,
+ cfg_msg_received_deassert_int_d,
+ cfg_msg_received_err_cor,
+ cfg_msg_received_err_fatal,
+ cfg_msg_received_err_non_fatal,
+ cfg_msg_received_pm_as_nak,
+ cfg_to_turnoff,
+ cfg_msg_received_pme_to_ack,
+ cfg_msg_received_pm_pme,
+ cfg_msg_received_setslotpowerlimit,
+ cfg_pmcsr_pme_en,
+ cfg_pmcsr_pme_status,
+ cfg_root_control_pme_int_en,
+ cfg_root_control_syserr_corr_err_en,
+ cfg_root_control_syserr_fatal_err_en,
+ cfg_root_control_syserr_non_fatal_err_en,
+ cfg_slot_control_electromech_il_ctl_pulse,
+ pcie_drp_rdy,
+ pl_directed_change_done,
+ pl_link_gen2_cap,
+ pl_link_partner_gen2_supported,
+ pl_link_upcfg_cap,
+ pl_sel_lnk_rate,
+ tx_cfg_req,
+ tx_err_drop,
+ fc_cpld,
+ fc_npd,
+ fc_pd,
+ cfg_msg_data,
+ pcie_drp_do,
+ cfg_pmcsr_powerstate,
+ pl_lane_reversal_mode,
+ pl_rx_pm_state,
+ pl_sel_lnk_width,
+ cfg_interrupt_mmenable,
+ cfg_pcie_link_state,
+ pl_initial_link_width,
+ pl_tx_pm_state,
+ cfg_mgmt_do,
+ tx_buf_av,
+ cfg_vc_tcvc_map,
+ cfg_interrupt_do,
+ fc_cplh,
+ fc_nph,
+ fc_ph,
+ pipe_pclk_sel_out,
+ gen3_reg,
+ pci_exp_txn,
+ pci_exp_txp,
+ pipe_rxoutclk_out,
+ pipe_txoutclk_out,
+ user_lnk_up,
+ m_axis_rx_tdata,
+ m_axis_rx_tkeep,
+ m_axis_rx_tlast,
+ m_axis_rx_tuser,
+ cfg_bus_number,
+ cfg_device_number,
+ cfg_function_number,
+ pl_received_hot_rst,
+ cfg_mgmt_rd_wr_done,
+ cfg_err_aer_headerlog_set,
+ cfg_err_cpl_rdy,
+ cfg_interrupt_rdy,
+ cfg_received_func_lvl_rst,
+ pipe_pclk_in,
+ m_axis_rx_tready,
+ s_axis_tx_tlast,
+ s_axis_tx_tvalid,
+ pipe_userclk2_in,
+ pipe_userclk1_in,
+ pcie_drp_clk,
+ pcie_drp_en,
+ pcie_drp_we,
+ pl_directed_link_auton,
+ pl_directed_link_speed,
+ pl_downstream_deemph_source,
+ pl_transmit_hot_rst,
+ pl_upstream_prefer_deemph,
+ rx_np_ok,
+ rx_np_req,
+ cfg_err_aer_headerlog,
+ pcie_drp_di,
+ cfg_pm_force_state,
+ pl_directed_link_change,
+ pl_directed_link_width,
+ cfg_ds_function_number,
+ fc_sel,
+ cfg_mgmt_di,
+ cfg_err_tlp_cpl_header,
+ cfg_aer_interrupt_msgnum,
+ cfg_ds_device_number,
+ cfg_pciecap_interrupt_msgnum,
+ cfg_dsn,
+ cfg_ds_bus_number,
+ cfg_interrupt_di,
+ pcie_drp_addr,
+ cfg_mgmt_dwaddr,
+ pipe_mmcm_lock_in,
+ pipe_rxusrclk_in,
+ pipe_dclk_in,
+ sys_clk,
+ pipe_oobclk_in,
+ pci_exp_rxn,
+ pci_exp_rxp,
+ sys_rst_n,
+ tx_cfg_gnt,
+ cfg_turnoff_ok,
+ s_axis_tx_tdata,
+ s_axis_tx_tuser,
+ s_axis_tx_tkeep,
+ cfg_mgmt_byte_en,
+ cfg_trn_pending,
+ cfg_mgmt_wr_rw1c_as_rw,
+ cfg_mgmt_wr_readonly,
+ cfg_mgmt_wr_en,
+ cfg_mgmt_rd_en,
+ cfg_err_malformed,
+ cfg_err_cor,
+ cfg_err_ur,
+ cfg_err_ecrc,
+ cfg_err_cpl_timeout,
+ cfg_err_cpl_abort,
+ cfg_err_cpl_unexpect,
+ cfg_err_poisoned,
+ cfg_err_atomic_egress_blocked,
+ cfg_err_mc_blocked,
+ cfg_err_internal_uncor,
+ cfg_err_internal_cor,
+ cfg_err_posted,
+ cfg_err_locked,
+ cfg_err_norecovery,
+ cfg_interrupt,
+ cfg_interrupt_assert,
+ cfg_interrupt_stat,
+ cfg_pm_halt_aspm_l0s,
+ cfg_pm_halt_aspm_l1,
+ cfg_pm_force_state_en,
+ cfg_pm_wake);
+ output [5:0]pl_ltssm_state;
+ output pl_phy_lnk_up;
+ output user_reset_out;
+ output m_axis_rx_tvalid;
+ output s_axis_tx_tready;
+ output cfg_aer_ecrc_check_en;
+ output cfg_aer_ecrc_gen_en;
+ output cfg_aer_rooterr_corr_err_received;
+ output cfg_aer_rooterr_corr_err_reporting_en;
+ output cfg_aer_rooterr_fatal_err_received;
+ output cfg_aer_rooterr_fatal_err_reporting_en;
+ output cfg_aer_rooterr_non_fatal_err_received;
+ output cfg_aer_rooterr_non_fatal_err_reporting_en;
+ output cfg_bridge_serr_en;
+ output [4:0]cfg_command;
+ output [11:0]cfg_dcommand2;
+ output [14:0]cfg_dcommand;
+ output [3:0]cfg_dstatus;
+ output cfg_interrupt_msienable;
+ output cfg_interrupt_msixenable;
+ output cfg_interrupt_msixfm;
+ output [10:0]cfg_lcommand;
+ output [9:0]cfg_lstatus;
+ output cfg_msg_received;
+ output cfg_msg_received_assert_int_a;
+ output cfg_msg_received_assert_int_b;
+ output cfg_msg_received_assert_int_c;
+ output cfg_msg_received_assert_int_d;
+ output cfg_msg_received_deassert_int_a;
+ output cfg_msg_received_deassert_int_b;
+ output cfg_msg_received_deassert_int_c;
+ output cfg_msg_received_deassert_int_d;
+ output cfg_msg_received_err_cor;
+ output cfg_msg_received_err_fatal;
+ output cfg_msg_received_err_non_fatal;
+ output cfg_msg_received_pm_as_nak;
+ output cfg_to_turnoff;
+ output cfg_msg_received_pme_to_ack;
+ output cfg_msg_received_pm_pme;
+ output cfg_msg_received_setslotpowerlimit;
+ output cfg_pmcsr_pme_en;
+ output cfg_pmcsr_pme_status;
+ output cfg_root_control_pme_int_en;
+ output cfg_root_control_syserr_corr_err_en;
+ output cfg_root_control_syserr_fatal_err_en;
+ output cfg_root_control_syserr_non_fatal_err_en;
+ output cfg_slot_control_electromech_il_ctl_pulse;
+ output pcie_drp_rdy;
+ output pl_directed_change_done;
+ output pl_link_gen2_cap;
+ output pl_link_partner_gen2_supported;
+ output pl_link_upcfg_cap;
+ output pl_sel_lnk_rate;
+ output tx_cfg_req;
+ output tx_err_drop;
+ output [11:0]fc_cpld;
+ output [11:0]fc_npd;
+ output [11:0]fc_pd;
+ output [15:0]cfg_msg_data;
+ output [15:0]pcie_drp_do;
+ output [1:0]cfg_pmcsr_powerstate;
+ output [1:0]pl_lane_reversal_mode;
+ output [1:0]pl_rx_pm_state;
+ output [1:0]pl_sel_lnk_width;
+ output [2:0]cfg_interrupt_mmenable;
+ output [2:0]cfg_pcie_link_state;
+ output [2:0]pl_initial_link_width;
+ output [2:0]pl_tx_pm_state;
+ output [31:0]cfg_mgmt_do;
+ output [5:0]tx_buf_av;
+ output [6:0]cfg_vc_tcvc_map;
+ output [7:0]cfg_interrupt_do;
+ output [7:0]fc_cplh;
+ output [7:0]fc_nph;
+ output [7:0]fc_ph;
+ output [3:0]pipe_pclk_sel_out;
+ output gen3_reg;
+ output [3:0]pci_exp_txn;
+ output [3:0]pci_exp_txp;
+ output [3:0]pipe_rxoutclk_out;
+ output pipe_txoutclk_out;
+ output user_lnk_up;
+ output [63:0]m_axis_rx_tdata;
+ output [0:0]m_axis_rx_tkeep;
+ output m_axis_rx_tlast;
+ output [12:0]m_axis_rx_tuser;
+ output [7:0]cfg_bus_number;
+ output [4:0]cfg_device_number;
+ output [2:0]cfg_function_number;
+ output pl_received_hot_rst;
+ output cfg_mgmt_rd_wr_done;
+ output cfg_err_aer_headerlog_set;
+ output cfg_err_cpl_rdy;
+ output cfg_interrupt_rdy;
+ output cfg_received_func_lvl_rst;
+ input pipe_pclk_in;
+ input m_axis_rx_tready;
+ input s_axis_tx_tlast;
+ input s_axis_tx_tvalid;
+ input pipe_userclk2_in;
+ input pipe_userclk1_in;
+ input pcie_drp_clk;
+ input pcie_drp_en;
+ input pcie_drp_we;
+ input pl_directed_link_auton;
+ input pl_directed_link_speed;
+ input pl_downstream_deemph_source;
+ input pl_transmit_hot_rst;
+ input pl_upstream_prefer_deemph;
+ input rx_np_ok;
+ input rx_np_req;
+ input [127:0]cfg_err_aer_headerlog;
+ input [15:0]pcie_drp_di;
+ input [1:0]cfg_pm_force_state;
+ input [1:0]pl_directed_link_change;
+ input [1:0]pl_directed_link_width;
+ input [2:0]cfg_ds_function_number;
+ input [2:0]fc_sel;
+ input [31:0]cfg_mgmt_di;
+ input [47:0]cfg_err_tlp_cpl_header;
+ input [4:0]cfg_aer_interrupt_msgnum;
+ input [4:0]cfg_ds_device_number;
+ input [4:0]cfg_pciecap_interrupt_msgnum;
+ input [63:0]cfg_dsn;
+ input [7:0]cfg_ds_bus_number;
+ input [7:0]cfg_interrupt_di;
+ input [8:0]pcie_drp_addr;
+ input [9:0]cfg_mgmt_dwaddr;
+ input pipe_mmcm_lock_in;
+ input pipe_rxusrclk_in;
+ input pipe_dclk_in;
+ input sys_clk;
+ input pipe_oobclk_in;
+ input [3:0]pci_exp_rxn;
+ input [3:0]pci_exp_rxp;
+ input sys_rst_n;
+ input tx_cfg_gnt;
+ input cfg_turnoff_ok;
+ input [63:0]s_axis_tx_tdata;
+ input [3:0]s_axis_tx_tuser;
+ input [0:0]s_axis_tx_tkeep;
+ input [3:0]cfg_mgmt_byte_en;
+ input cfg_trn_pending;
+ input cfg_mgmt_wr_rw1c_as_rw;
+ input cfg_mgmt_wr_readonly;
+ input cfg_mgmt_wr_en;
+ input cfg_mgmt_rd_en;
+ input cfg_err_malformed;
+ input cfg_err_cor;
+ input cfg_err_ur;
+ input cfg_err_ecrc;
+ input cfg_err_cpl_timeout;
+ input cfg_err_cpl_abort;
+ input cfg_err_cpl_unexpect;
+ input cfg_err_poisoned;
+ input cfg_err_atomic_egress_blocked;
+ input cfg_err_mc_blocked;
+ input cfg_err_internal_uncor;
+ input cfg_err_internal_cor;
+ input cfg_err_posted;
+ input cfg_err_locked;
+ input cfg_err_norecovery;
+ input cfg_interrupt;
+ input cfg_interrupt_assert;
+ input cfg_interrupt_stat;
+ input cfg_pm_halt_aspm_l0s;
+ input cfg_pm_halt_aspm_l1;
+ input cfg_pm_force_state_en;
+ input cfg_pm_wake;
+
+ wire \_inferred__0/store_ltssm_inferred_i_2_n_0 ;
+ wire \_inferred__0/store_ltssm_inferred_i_3_n_0 ;
+ wire bridge_reset_int;
+ wire cfg_aer_ecrc_check_en;
+ wire cfg_aer_ecrc_gen_en;
+ wire [4:0]cfg_aer_interrupt_msgnum;
+ wire cfg_aer_rooterr_corr_err_received;
+ wire cfg_aer_rooterr_corr_err_reporting_en;
+ wire cfg_aer_rooterr_fatal_err_received;
+ wire cfg_aer_rooterr_fatal_err_reporting_en;
+ wire cfg_aer_rooterr_non_fatal_err_received;
+ wire cfg_aer_rooterr_non_fatal_err_reporting_en;
+ wire cfg_bridge_serr_en;
+ wire [7:0]cfg_bus_number;
+ wire [4:0]cfg_command;
+ wire [14:0]cfg_dcommand;
+ wire [11:0]cfg_dcommand2;
+ wire [4:0]cfg_device_number;
+ wire [7:0]cfg_ds_bus_number;
+ wire [4:0]cfg_ds_device_number;
+ wire [2:0]cfg_ds_function_number;
+ wire [63:0]cfg_dsn;
+ wire [3:0]cfg_dstatus;
+ wire [127:0]cfg_err_aer_headerlog;
+ wire cfg_err_aer_headerlog_set;
+ wire cfg_err_atomic_egress_blocked;
+ wire cfg_err_cor;
+ wire cfg_err_cpl_abort;
+ wire cfg_err_cpl_rdy;
+ wire cfg_err_cpl_timeout;
+ wire cfg_err_cpl_unexpect;
+ wire cfg_err_ecrc;
+ wire cfg_err_internal_cor;
+ wire cfg_err_internal_uncor;
+ wire cfg_err_locked;
+ wire cfg_err_malformed;
+ wire cfg_err_mc_blocked;
+ wire cfg_err_norecovery;
+ wire cfg_err_poisoned;
+ wire cfg_err_posted;
+ wire [47:0]cfg_err_tlp_cpl_header;
+ wire cfg_err_ur;
+ wire [2:0]cfg_function_number;
+ wire cfg_interrupt;
+ wire cfg_interrupt_assert;
+ wire [7:0]cfg_interrupt_di;
+ wire [7:0]cfg_interrupt_do;
+ wire [2:0]cfg_interrupt_mmenable;
+ wire cfg_interrupt_msienable;
+ wire cfg_interrupt_msixenable;
+ wire cfg_interrupt_msixfm;
+ wire cfg_interrupt_rdy;
+ wire cfg_interrupt_stat;
+ wire [10:0]cfg_lcommand;
+ wire [9:0]cfg_lstatus;
+ wire [3:0]cfg_mgmt_byte_en;
+ wire [31:0]cfg_mgmt_di;
+ wire [31:0]cfg_mgmt_do;
+ wire [9:0]cfg_mgmt_dwaddr;
+ wire cfg_mgmt_rd_en;
+ wire cfg_mgmt_rd_wr_done;
+ wire cfg_mgmt_wr_en;
+ wire cfg_mgmt_wr_readonly;
+ wire cfg_mgmt_wr_rw1c_as_rw;
+ wire [15:0]cfg_msg_data;
+ wire cfg_msg_received;
+ wire cfg_msg_received_assert_int_a;
+ wire cfg_msg_received_assert_int_b;
+ wire cfg_msg_received_assert_int_c;
+ wire cfg_msg_received_assert_int_d;
+ wire cfg_msg_received_deassert_int_a;
+ wire cfg_msg_received_deassert_int_b;
+ wire cfg_msg_received_deassert_int_c;
+ wire cfg_msg_received_deassert_int_d;
+ wire cfg_msg_received_err_cor;
+ wire cfg_msg_received_err_fatal;
+ wire cfg_msg_received_err_non_fatal;
+ wire cfg_msg_received_pm_as_nak;
+ wire cfg_msg_received_pm_pme;
+ wire cfg_msg_received_pme_to_ack;
+ wire cfg_msg_received_setslotpowerlimit;
+ wire [2:0]cfg_pcie_link_state;
+ wire [4:0]cfg_pciecap_interrupt_msgnum;
+ wire [1:0]cfg_pm_force_state;
+ wire cfg_pm_force_state_en;
+ wire cfg_pm_halt_aspm_l0s;
+ wire cfg_pm_halt_aspm_l1;
+ wire cfg_pm_wake;
+ wire cfg_pmcsr_pme_en;
+ wire cfg_pmcsr_pme_status;
+ wire [1:0]cfg_pmcsr_powerstate;
+ wire cfg_received_func_lvl_rst;
+ wire cfg_root_control_pme_int_en;
+ wire cfg_root_control_syserr_corr_err_en;
+ wire cfg_root_control_syserr_fatal_err_en;
+ wire cfg_root_control_syserr_non_fatal_err_en;
+ wire cfg_slot_control_electromech_il_ctl_pulse;
+ wire cfg_to_turnoff;
+ wire cfg_trn_pending;
+ wire cfg_turnoff_ok;
+ wire [6:0]cfg_vc_tcvc_map;
+ wire [11:0]fc_cpld;
+ wire [7:0]fc_cplh;
+ wire [11:0]fc_npd;
+ wire [7:0]fc_nph;
+ wire [11:0]fc_pd;
+ wire [7:0]fc_ph;
+ wire [2:0]fc_sel;
+ wire gen3_reg;
+ wire gt_rx_phy_status_q;
+ wire gt_rxelecidle_q;
+ wire gt_top_i_n_10;
+ wire gt_top_i_n_120;
+ wire gt_top_i_n_13;
+ wire gt_top_i_n_5;
+ wire gt_top_i_n_6;
+ wire gt_top_i_n_7;
+ wire gt_top_i_n_78;
+ wire gt_top_i_n_79;
+ wire gt_top_i_n_8;
+ wire gt_top_i_n_80;
+ wire gt_top_i_n_81;
+ wire gt_top_i_n_82;
+ wire gt_top_i_n_83;
+ wire gt_top_i_n_84;
+ wire gt_top_i_n_85;
+ wire gt_top_i_n_86;
+ wire gt_top_i_n_87;
+ wire gt_top_i_n_88;
+ wire gt_top_i_n_89;
+ wire gt_top_i_n_9;
+ wire \ltssm_reg1_reg[0]_srl2_n_0 ;
+ wire \ltssm_reg1_reg[1]_srl2_n_0 ;
+ wire \ltssm_reg1_reg[2]_srl2_n_0 ;
+ wire \ltssm_reg1_reg[3]_srl2_n_0 ;
+ wire \ltssm_reg1_reg[4]_srl2_n_0 ;
+ wire \ltssm_reg1_reg[5]_srl2_n_0 ;
+ wire [5:0]ltssm_reg2;
+ wire [63:0]m_axis_rx_tdata;
+ wire [0:0]m_axis_rx_tkeep;
+ wire m_axis_rx_tlast;
+ wire m_axis_rx_tready;
+ wire [12:0]m_axis_rx_tuser;
+ wire m_axis_rx_tvalid;
+ wire [3:0]pci_exp_rxn;
+ wire [3:0]pci_exp_rxp;
+ wire [3:0]pci_exp_txn;
+ wire [3:0]pci_exp_txp;
+ wire pcie_block_i_i_32_n_0;
+ wire pcie_block_i_i_33_n_0;
+ wire pcie_block_i_i_34_n_0;
+ wire pcie_block_i_i_35_n_0;
+ wire [8:0]pcie_drp_addr;
+ wire pcie_drp_clk;
+ wire [15:0]pcie_drp_di;
+ wire [15:0]pcie_drp_do;
+ wire pcie_drp_en;
+ wire pcie_drp_rdy;
+ wire pcie_drp_we;
+ wire pcie_top_i_n_20;
+ wire phy_rdy_n;
+ wire pipe_dclk_in;
+ wire pipe_mmcm_lock_in;
+ wire pipe_oobclk_in;
+ wire pipe_pclk_in;
+ wire [3:0]pipe_pclk_sel_out;
+ wire pipe_rx0_chanisaligned_gt;
+ wire [1:0]pipe_rx0_char_is_k_gt;
+ wire [15:0]pipe_rx0_data_gt;
+ wire pipe_rx0_polarity_gt;
+ wire pipe_rx0_valid_gt;
+ wire pipe_rx1_chanisaligned_gt;
+ wire [1:0]pipe_rx1_char_is_k_gt;
+ wire [15:0]pipe_rx1_data_gt;
+ wire pipe_rx1_polarity_gt;
+ wire pipe_rx1_valid_gt;
+ wire pipe_rx2_chanisaligned_gt;
+ wire [1:0]pipe_rx2_char_is_k_gt;
+ wire [15:0]pipe_rx2_data_gt;
+ wire pipe_rx2_polarity_gt;
+ wire pipe_rx2_valid_gt;
+ wire pipe_rx3_chanisaligned_gt;
+ wire [1:0]pipe_rx3_char_is_k_gt;
+ wire [15:0]pipe_rx3_data_gt;
+ wire pipe_rx3_polarity_gt;
+ wire pipe_rx3_valid_gt;
+ wire [3:0]pipe_rxoutclk_out;
+ wire pipe_rxusrclk_in;
+ wire [1:0]pipe_tx0_char_is_k_gt;
+ wire pipe_tx0_compliance_gt;
+ wire [15:0]pipe_tx0_data_gt;
+ wire pipe_tx0_elec_idle_gt;
+ wire [1:0]pipe_tx0_powerdown_gt;
+ wire [1:0]pipe_tx1_char_is_k_gt;
+ wire pipe_tx1_compliance_gt;
+ wire [15:0]pipe_tx1_data_gt;
+ wire pipe_tx1_elec_idle_gt;
+ wire [1:0]pipe_tx1_powerdown_gt;
+ wire [1:0]pipe_tx2_char_is_k_gt;
+ wire pipe_tx2_compliance_gt;
+ wire [15:0]pipe_tx2_data_gt;
+ wire pipe_tx2_elec_idle_gt;
+ wire [1:0]pipe_tx2_powerdown_gt;
+ wire [1:0]pipe_tx3_char_is_k_gt;
+ wire pipe_tx3_compliance_gt;
+ wire [15:0]pipe_tx3_data_gt;
+ wire pipe_tx3_elec_idle_gt;
+ wire [1:0]pipe_tx3_powerdown_gt;
+ wire pipe_tx_deemph_gt;
+ wire [2:0]pipe_tx_margin_gt;
+ wire pipe_tx_rate_gt;
+ wire pipe_tx_rcvr_det_gt;
+ wire pipe_txoutclk_out;
+ wire pipe_userclk1_in;
+ wire pipe_userclk2_in;
+ wire pl_directed_change_done;
+ wire pl_directed_link_auton;
+ wire [1:0]pl_directed_link_change;
+ wire pl_directed_link_speed;
+ wire [1:0]pl_directed_link_width;
+ wire pl_downstream_deemph_source;
+ wire [2:0]pl_initial_link_width;
+ wire [1:0]pl_lane_reversal_mode;
+ wire pl_link_gen2_cap;
+ wire pl_link_partner_gen2_supported;
+ wire pl_link_upcfg_cap;
+ wire [5:0]pl_ltssm_state;
+ wire pl_phy_lnk_up;
+ wire pl_phy_lnk_up_sync;
+ wire pl_phy_lnk_up_wire;
+ wire pl_received_hot_rst;
+ wire pl_received_hot_rst_sync;
+ wire pl_received_hot_rst_wire;
+ wire [1:0]pl_rx_pm_state;
+ wire pl_sel_lnk_rate;
+ wire [1:0]pl_sel_lnk_width;
+ wire pl_transmit_hot_rst;
+ wire [2:0]pl_tx_pm_state;
+ wire pl_upstream_prefer_deemph;
+ wire rx_np_ok;
+ wire rx_np_req;
+ wire [63:0]s_axis_tx_tdata;
+ wire [0:0]s_axis_tx_tkeep;
+ wire s_axis_tx_tlast;
+ wire s_axis_tx_tready;
+ wire [3:0]s_axis_tx_tuser;
+ wire s_axis_tx_tvalid;
+ (* DONT_TOUCH *) wire store_ltssm;
+ wire sys_clk;
+ wire sys_or_hot_rst;
+ wire sys_rst_n;
+ wire trn_lnk_up;
+ wire [5:0]tx_buf_av;
+ wire tx_cfg_gnt;
+ wire tx_cfg_req;
+ wire tx_err_drop;
+ (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire user_lnk_up_int;
+ (* async_reg = "true" *) wire user_lnk_up_mux;
+ wire user_reset_out;
+
+ assign user_lnk_up = user_lnk_up_int;
+ LUT2 #(
+ .INIT(4'hE))
+ \_inferred__0/store_ltssm_inferred_i_1
+ (.I0(\_inferred__0/store_ltssm_inferred_i_2_n_0 ),
+ .I1(\_inferred__0/store_ltssm_inferred_i_3_n_0 ),
+ .O(store_ltssm));
+ LUT6 #(
+ .INIT(64'h6FF6FFFFFFFF6FF6))
+ \_inferred__0/store_ltssm_inferred_i_2
+ (.I0(ltssm_reg2[0]),
+ .I1(pl_ltssm_state[0]),
+ .I2(pl_ltssm_state[2]),
+ .I3(ltssm_reg2[2]),
+ .I4(pl_ltssm_state[1]),
+ .I5(ltssm_reg2[1]),
+ .O(\_inferred__0/store_ltssm_inferred_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h6FF6FFFFFFFF6FF6))
+ \_inferred__0/store_ltssm_inferred_i_3
+ (.I0(ltssm_reg2[3]),
+ .I1(pl_ltssm_state[3]),
+ .I2(pl_ltssm_state[5]),
+ .I3(ltssm_reg2[5]),
+ .I4(pl_ltssm_state[4]),
+ .I5(ltssm_reg2[4]),
+ .O(\_inferred__0/store_ltssm_inferred_i_3_n_0 ));
+ pcie_7x_0_pcie_7x_0_gt_top gt_top_i
+ (.D(pipe_rx0_char_is_k_gt),
+ .PIPE_POWERDOWN({pipe_tx3_powerdown_gt,pipe_tx2_powerdown_gt,pipe_tx1_powerdown_gt,pipe_tx0_powerdown_gt}),
+ .PIPE_RXCHANISALIGNED({pipe_rx3_chanisaligned_gt,pipe_rx2_chanisaligned_gt,pipe_rx1_chanisaligned_gt,pipe_rx0_chanisaligned_gt}),
+ .PIPE_RXPOLARITY({pipe_rx3_polarity_gt,pipe_rx2_polarity_gt,pipe_rx1_polarity_gt,pipe_rx0_polarity_gt}),
+ .PIPE_TXCOMPLIANCE({pipe_tx3_compliance_gt,pipe_tx2_compliance_gt,pipe_tx1_compliance_gt,pipe_tx0_compliance_gt}),
+ .PIPE_TXDATA({pipe_tx3_data_gt,pipe_tx2_data_gt,pipe_tx1_data_gt,pipe_tx0_data_gt}),
+ .PIPE_TXDATAK({pipe_tx3_char_is_k_gt,pipe_tx2_char_is_k_gt,pipe_tx1_char_is_k_gt,pipe_tx0_char_is_k_gt}),
+ .PIPE_TXELECIDLE({pipe_tx3_elec_idle_gt,pipe_tx2_elec_idle_gt,pipe_tx1_elec_idle_gt,pipe_tx0_elec_idle_gt}),
+ .Q(pipe_rx0_data_gt),
+ .USER_RATE_GEN3(gen3_reg),
+ .\cplllock_reg1_reg[3] (pipe_tx_margin_gt),
+ .gt_rx_phy_status_q(gt_rx_phy_status_q),
+ .gt_rx_phy_status_q_reg(gt_top_i_n_5),
+ .gt_rx_phy_status_q_reg_0(gt_top_i_n_7),
+ .gt_rx_phy_status_q_reg_1(gt_top_i_n_9),
+ .\gt_rx_status_q_reg[2] ({gt_top_i_n_78,gt_top_i_n_79,gt_top_i_n_80}),
+ .\gt_rx_status_q_reg[2]_0 ({gt_top_i_n_81,gt_top_i_n_82,gt_top_i_n_83}),
+ .\gt_rx_status_q_reg[2]_1 ({gt_top_i_n_84,gt_top_i_n_85,gt_top_i_n_86}),
+ .\gt_rx_status_q_reg[2]_2 ({gt_top_i_n_87,gt_top_i_n_88,gt_top_i_n_89}),
+ .\gt_rxdata_q_reg[15] (pipe_rx1_data_gt),
+ .\gt_rxdata_q_reg[15]_0 (pipe_rx2_data_gt),
+ .\gt_rxdata_q_reg[15]_1 (pipe_rx3_data_gt),
+ .gt_rxelecidle_q(gt_rxelecidle_q),
+ .gt_rxelecidle_q_reg(gt_top_i_n_6),
+ .gt_rxelecidle_q_reg_0(gt_top_i_n_8),
+ .gt_rxelecidle_q_reg_1(gt_top_i_n_10),
+ .gt_rxvalid_q_reg(pipe_rx1_char_is_k_gt),
+ .gt_rxvalid_q_reg_0(pipe_rx2_char_is_k_gt),
+ .gt_rxvalid_q_reg_1(pipe_rx3_char_is_k_gt),
+ .pci_exp_rxn(pci_exp_rxn),
+ .pci_exp_rxp(pci_exp_rxp),
+ .pci_exp_txn(pci_exp_txn),
+ .pci_exp_txp(pci_exp_txp),
+ .phy_rdy_n(phy_rdy_n),
+ .pipe_dclk_in(pipe_dclk_in),
+ .pipe_mmcm_lock_in(pipe_mmcm_lock_in),
+ .pipe_oobclk_in(pipe_oobclk_in),
+ .pipe_pclk_in(pipe_pclk_in),
+ .pipe_pclk_sel_out(pipe_pclk_sel_out),
+ .pipe_rx0_valid_gt(pipe_rx0_valid_gt),
+ .pipe_rx1_valid_gt(pipe_rx1_valid_gt),
+ .pipe_rx2_valid_gt(pipe_rx2_valid_gt),
+ .pipe_rx3_valid_gt(pipe_rx3_valid_gt),
+ .pipe_rxoutclk_out(pipe_rxoutclk_out),
+ .pipe_rxusrclk_in(pipe_rxusrclk_in),
+ .pipe_tx_deemph_gt(pipe_tx_deemph_gt),
+ .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt),
+ .pipe_txoutclk_out(pipe_txoutclk_out),
+ .pl_ltssm_state(pl_ltssm_state),
+ .\rate_reg1_reg[0] (pipe_tx_rate_gt),
+ .reset_n_reg1_reg(sys_rst_n),
+ .sys_clk(sys_clk),
+ .sys_rst_n(gt_top_i_n_13),
+ .sys_rst_n_0(gt_top_i_n_120));
+ (* srl_bus_name = "inst/\inst/ltssm_reg1_reg " *)
+ (* srl_name = "inst/\inst/ltssm_reg1_reg[0]_srl2 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \ltssm_reg1_reg[0]_srl2
+ (.A0(1'b1),
+ .A1(1'b0),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(1'b1),
+ .CLK(pipe_pclk_in),
+ .D(pl_ltssm_state[0]),
+ .Q(\ltssm_reg1_reg[0]_srl2_n_0 ));
+ (* srl_bus_name = "inst/\inst/ltssm_reg1_reg " *)
+ (* srl_name = "inst/\inst/ltssm_reg1_reg[1]_srl2 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \ltssm_reg1_reg[1]_srl2
+ (.A0(1'b1),
+ .A1(1'b0),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(1'b1),
+ .CLK(pipe_pclk_in),
+ .D(pl_ltssm_state[1]),
+ .Q(\ltssm_reg1_reg[1]_srl2_n_0 ));
+ (* srl_bus_name = "inst/\inst/ltssm_reg1_reg " *)
+ (* srl_name = "inst/\inst/ltssm_reg1_reg[2]_srl2 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \ltssm_reg1_reg[2]_srl2
+ (.A0(1'b1),
+ .A1(1'b0),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(1'b1),
+ .CLK(pipe_pclk_in),
+ .D(pl_ltssm_state[2]),
+ .Q(\ltssm_reg1_reg[2]_srl2_n_0 ));
+ (* srl_bus_name = "inst/\inst/ltssm_reg1_reg " *)
+ (* srl_name = "inst/\inst/ltssm_reg1_reg[3]_srl2 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \ltssm_reg1_reg[3]_srl2
+ (.A0(1'b1),
+ .A1(1'b0),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(1'b1),
+ .CLK(pipe_pclk_in),
+ .D(pl_ltssm_state[3]),
+ .Q(\ltssm_reg1_reg[3]_srl2_n_0 ));
+ (* srl_bus_name = "inst/\inst/ltssm_reg1_reg " *)
+ (* srl_name = "inst/\inst/ltssm_reg1_reg[4]_srl2 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \ltssm_reg1_reg[4]_srl2
+ (.A0(1'b1),
+ .A1(1'b0),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(1'b1),
+ .CLK(pipe_pclk_in),
+ .D(pl_ltssm_state[4]),
+ .Q(\ltssm_reg1_reg[4]_srl2_n_0 ));
+ (* srl_bus_name = "inst/\inst/ltssm_reg1_reg " *)
+ (* srl_name = "inst/\inst/ltssm_reg1_reg[5]_srl2 " *)
+ SRL16E #(
+ .INIT(16'h0000))
+ \ltssm_reg1_reg[5]_srl2
+ (.A0(1'b1),
+ .A1(1'b0),
+ .A2(1'b0),
+ .A3(1'b0),
+ .CE(1'b1),
+ .CLK(pipe_pclk_in),
+ .D(pl_ltssm_state[5]),
+ .Q(\ltssm_reg1_reg[5]_srl2_n_0 ));
+ FDRE #(
+ .INIT(1'b0))
+ \ltssm_reg2_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\ltssm_reg1_reg[0]_srl2_n_0 ),
+ .Q(ltssm_reg2[0]),
+ .R(1'b0));
+ FDRE #(
+ .INIT(1'b0))
+ \ltssm_reg2_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\ltssm_reg1_reg[1]_srl2_n_0 ),
+ .Q(ltssm_reg2[1]),
+ .R(1'b0));
+ FDRE #(
+ .INIT(1'b0))
+ \ltssm_reg2_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\ltssm_reg1_reg[2]_srl2_n_0 ),
+ .Q(ltssm_reg2[2]),
+ .R(1'b0));
+ FDRE #(
+ .INIT(1'b0))
+ \ltssm_reg2_reg[3]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\ltssm_reg1_reg[3]_srl2_n_0 ),
+ .Q(ltssm_reg2[3]),
+ .R(1'b0));
+ FDRE #(
+ .INIT(1'b0))
+ \ltssm_reg2_reg[4]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\ltssm_reg1_reg[4]_srl2_n_0 ),
+ .Q(ltssm_reg2[4]),
+ .R(1'b0));
+ FDRE #(
+ .INIT(1'b0))
+ \ltssm_reg2_reg[5]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\ltssm_reg1_reg[5]_srl2_n_0 ),
+ .Q(ltssm_reg2[5]),
+ .R(1'b0));
+ LUT1 #(
+ .INIT(2'h1))
+ pcie_block_i_i_32
+ (.I0(cfg_mgmt_byte_en[3]),
+ .O(pcie_block_i_i_32_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ pcie_block_i_i_33
+ (.I0(cfg_mgmt_byte_en[2]),
+ .O(pcie_block_i_i_33_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ pcie_block_i_i_34
+ (.I0(cfg_mgmt_byte_en[1]),
+ .O(pcie_block_i_i_34_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ pcie_block_i_i_35
+ (.I0(cfg_mgmt_byte_en[0]),
+ .O(pcie_block_i_i_35_n_0));
+ pcie_7x_0_pcie_7x_0_pcie_top pcie_top_i
+ (.D(pipe_rx1_char_is_k_gt),
+ .PIPE_POWERDOWN({pipe_tx3_powerdown_gt,pipe_tx2_powerdown_gt,pipe_tx1_powerdown_gt,pipe_tx0_powerdown_gt}),
+ .PIPE_RXCHANISALIGNED({pipe_rx3_chanisaligned_gt,pipe_rx2_chanisaligned_gt,pipe_rx1_chanisaligned_gt,pipe_rx0_chanisaligned_gt}),
+ .PIPE_RXPOLARITY({pipe_rx3_polarity_gt,pipe_rx2_polarity_gt,pipe_rx1_polarity_gt,pipe_rx0_polarity_gt}),
+ .PIPE_TXCOMPLIANCE({pipe_tx3_compliance_gt,pipe_tx2_compliance_gt,pipe_tx1_compliance_gt,pipe_tx0_compliance_gt}),
+ .PIPE_TXDATA({pipe_tx3_data_gt,pipe_tx2_data_gt,pipe_tx1_data_gt,pipe_tx0_data_gt}),
+ .PIPE_TXDATAK({pipe_tx3_char_is_k_gt,pipe_tx2_char_is_k_gt,pipe_tx1_char_is_k_gt,pipe_tx0_char_is_k_gt}),
+ .PIPE_TXELECIDLE({pipe_tx3_elec_idle_gt,pipe_tx2_elec_idle_gt,pipe_tx1_elec_idle_gt,pipe_tx0_elec_idle_gt}),
+ .Q(pipe_tx_margin_gt),
+ .SR(phy_rdy_n),
+ .bridge_reset_int(bridge_reset_int),
+ .cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en),
+ .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en),
+ .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum),
+ .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received),
+ .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en),
+ .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received),
+ .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en),
+ .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received),
+ .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en),
+ .cfg_bridge_serr_en(cfg_bridge_serr_en),
+ .cfg_bus_number(cfg_bus_number),
+ .cfg_command(cfg_command),
+ .cfg_dcommand(cfg_dcommand),
+ .cfg_dcommand2(cfg_dcommand2),
+ .cfg_device_number(cfg_device_number),
+ .cfg_ds_bus_number(cfg_ds_bus_number),
+ .cfg_ds_device_number(cfg_ds_device_number),
+ .cfg_ds_function_number(cfg_ds_function_number),
+ .cfg_dsn(cfg_dsn),
+ .cfg_dstatus(cfg_dstatus),
+ .cfg_err_aer_headerlog(cfg_err_aer_headerlog),
+ .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set),
+ .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked),
+ .cfg_err_cor(cfg_err_cor),
+ .cfg_err_cpl_abort(cfg_err_cpl_abort),
+ .cfg_err_cpl_rdy(cfg_err_cpl_rdy),
+ .cfg_err_cpl_timeout(cfg_err_cpl_timeout),
+ .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect),
+ .cfg_err_ecrc(cfg_err_ecrc),
+ .cfg_err_internal_cor(cfg_err_internal_cor),
+ .cfg_err_internal_uncor(cfg_err_internal_uncor),
+ .cfg_err_locked(cfg_err_locked),
+ .cfg_err_malformed(cfg_err_malformed),
+ .cfg_err_mc_blocked(cfg_err_mc_blocked),
+ .cfg_err_norecovery(cfg_err_norecovery),
+ .cfg_err_poisoned(cfg_err_poisoned),
+ .cfg_err_posted(cfg_err_posted),
+ .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header),
+ .cfg_err_ur(cfg_err_ur),
+ .cfg_function_number(cfg_function_number),
+ .cfg_interrupt(cfg_interrupt),
+ .cfg_interrupt_assert(cfg_interrupt_assert),
+ .cfg_interrupt_di(cfg_interrupt_di),
+ .cfg_interrupt_do(cfg_interrupt_do),
+ .cfg_interrupt_mmenable(cfg_interrupt_mmenable),
+ .cfg_interrupt_msienable(cfg_interrupt_msienable),
+ .cfg_interrupt_msixenable(cfg_interrupt_msixenable),
+ .cfg_interrupt_msixfm(cfg_interrupt_msixfm),
+ .cfg_interrupt_rdy(cfg_interrupt_rdy),
+ .cfg_interrupt_stat(cfg_interrupt_stat),
+ .cfg_lcommand(cfg_lcommand),
+ .cfg_lstatus(cfg_lstatus),
+ .cfg_mgmt_byte_en_n({pcie_block_i_i_32_n_0,pcie_block_i_i_33_n_0,pcie_block_i_i_34_n_0,pcie_block_i_i_35_n_0}),
+ .cfg_mgmt_di(cfg_mgmt_di),
+ .cfg_mgmt_do(cfg_mgmt_do),
+ .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr),
+ .cfg_mgmt_rd_en(cfg_mgmt_rd_en),
+ .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done),
+ .cfg_mgmt_wr_en(cfg_mgmt_wr_en),
+ .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly),
+ .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw),
+ .cfg_msg_data(cfg_msg_data),
+ .cfg_msg_received(cfg_msg_received),
+ .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a),
+ .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b),
+ .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c),
+ .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d),
+ .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a),
+ .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b),
+ .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c),
+ .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d),
+ .cfg_msg_received_err_cor(cfg_msg_received_err_cor),
+ .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal),
+ .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal),
+ .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak),
+ .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme),
+ .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack),
+ .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit),
+ .cfg_pcie_link_state(cfg_pcie_link_state),
+ .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum),
+ .cfg_pm_force_state(cfg_pm_force_state),
+ .cfg_pm_force_state_en(cfg_pm_force_state_en),
+ .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s),
+ .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1),
+ .cfg_pm_wake(cfg_pm_wake),
+ .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en),
+ .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status),
+ .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate),
+ .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst),
+ .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en),
+ .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en),
+ .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en),
+ .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en),
+ .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse),
+ .cfg_to_turnoff(cfg_to_turnoff),
+ .cfg_trn_pending(cfg_trn_pending),
+ .cfg_turnoff_ok(cfg_turnoff_ok),
+ .cfg_vc_tcvc_map(cfg_vc_tcvc_map),
+ .fc_cpld(fc_cpld),
+ .fc_cplh(fc_cplh),
+ .fc_npd(fc_npd),
+ .fc_nph(fc_nph),
+ .fc_pd(fc_pd),
+ .fc_ph(fc_ph),
+ .fc_sel(fc_sel),
+ .gt_rx_phy_status_q(gt_rx_phy_status_q),
+ .gt_rxelecidle_q(gt_rxelecidle_q),
+ .m_axis_rx_tdata(m_axis_rx_tdata),
+ .m_axis_rx_tkeep(m_axis_rx_tkeep),
+ .m_axis_rx_tlast(m_axis_rx_tlast),
+ .m_axis_rx_tready(m_axis_rx_tready),
+ .m_axis_rx_tuser(m_axis_rx_tuser),
+ .m_axis_rx_tvalid_reg(m_axis_rx_tvalid),
+ .out(user_lnk_up_int),
+ .pcie_drp_addr(pcie_drp_addr),
+ .pcie_drp_clk(pcie_drp_clk),
+ .pcie_drp_di(pcie_drp_di),
+ .pcie_drp_do(pcie_drp_do),
+ .pcie_drp_en(pcie_drp_en),
+ .pcie_drp_rdy(pcie_drp_rdy),
+ .pcie_drp_we(pcie_drp_we),
+ .pipe_pclk_in(pipe_pclk_in),
+ .pipe_rx0_valid_gt(pipe_rx0_valid_gt),
+ .pipe_rx1_valid_gt(pipe_rx1_valid_gt),
+ .pipe_rx2_valid_gt(pipe_rx2_valid_gt),
+ .pipe_rx3_valid_gt(pipe_rx3_valid_gt),
+ .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (pipe_rx2_char_is_k_gt),
+ .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 (pipe_rx3_char_is_k_gt),
+ .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 (pipe_rx0_char_is_k_gt),
+ .\pipe_stages_1.pipe_rx_data_q_reg[15] (pipe_rx1_data_gt),
+ .\pipe_stages_1.pipe_rx_data_q_reg[15]_0 (pipe_rx2_data_gt),
+ .\pipe_stages_1.pipe_rx_data_q_reg[15]_1 (pipe_rx3_data_gt),
+ .\pipe_stages_1.pipe_rx_data_q_reg[15]_2 (pipe_rx0_data_gt),
+ .\pipe_stages_1.pipe_rx_elec_idle_q_reg (gt_top_i_n_6),
+ .\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 (gt_top_i_n_8),
+ .\pipe_stages_1.pipe_rx_elec_idle_q_reg_1 (gt_top_i_n_10),
+ .\pipe_stages_1.pipe_rx_phy_status_q_reg (gt_top_i_n_5),
+ .\pipe_stages_1.pipe_rx_phy_status_q_reg_0 (gt_top_i_n_7),
+ .\pipe_stages_1.pipe_rx_phy_status_q_reg_1 (gt_top_i_n_9),
+ .\pipe_stages_1.pipe_rx_status_q_reg[2] ({gt_top_i_n_78,gt_top_i_n_79,gt_top_i_n_80}),
+ .\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ({gt_top_i_n_81,gt_top_i_n_82,gt_top_i_n_83}),
+ .\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ({gt_top_i_n_84,gt_top_i_n_85,gt_top_i_n_86}),
+ .\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ({gt_top_i_n_87,gt_top_i_n_88,gt_top_i_n_89}),
+ .\pipe_stages_1.pipe_tx_rate_q_reg (pipe_tx_rate_gt),
+ .pipe_tx_deemph_gt(pipe_tx_deemph_gt),
+ .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt),
+ .pipe_userclk1_in(pipe_userclk1_in),
+ .pipe_userclk2_in(pipe_userclk2_in),
+ .pl_directed_change_done(pl_directed_change_done),
+ .pl_directed_link_auton(pl_directed_link_auton),
+ .pl_directed_link_change(pl_directed_link_change),
+ .pl_directed_link_speed(pl_directed_link_speed),
+ .pl_directed_link_width(pl_directed_link_width),
+ .pl_downstream_deemph_source(pl_downstream_deemph_source),
+ .pl_initial_link_width(pl_initial_link_width),
+ .pl_lane_reversal_mode(pl_lane_reversal_mode),
+ .pl_link_gen2_cap(pl_link_gen2_cap),
+ .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported),
+ .pl_link_upcfg_cap(pl_link_upcfg_cap),
+ .pl_ltssm_state(pl_ltssm_state),
+ .pl_phy_lnk_up(pl_phy_lnk_up),
+ .pl_received_hot_rst(pl_received_hot_rst_wire),
+ .pl_rx_pm_state(pl_rx_pm_state),
+ .pl_sel_lnk_rate(pl_sel_lnk_rate),
+ .pl_sel_lnk_width(pl_sel_lnk_width),
+ .pl_transmit_hot_rst(pl_transmit_hot_rst),
+ .pl_tx_pm_state(pl_tx_pm_state),
+ .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph),
+ .rx_np_ok(rx_np_ok),
+ .rx_np_req(rx_np_req),
+ .s_axis_tx_tdata(s_axis_tx_tdata),
+ .s_axis_tx_tkeep(s_axis_tx_tkeep),
+ .s_axis_tx_tlast(s_axis_tx_tlast),
+ .s_axis_tx_tuser(s_axis_tx_tuser),
+ .s_axis_tx_tvalid(s_axis_tx_tvalid),
+ .src_in(pl_phy_lnk_up_wire),
+ .sys_rst_n(gt_top_i_n_13),
+ .\throttle_ctl_pipeline.reg_tkeep_reg[7] (user_reset_out),
+ .tready_thrtl_reg(s_axis_tx_tready),
+ .trn_lnk_up(trn_lnk_up),
+ .trn_tbuf_av(tx_buf_av),
+ .trn_tcfg_req(tx_cfg_req),
+ .tx_cfg_gnt(tx_cfg_gnt),
+ .tx_err_drop(tx_err_drop),
+ .user_reset_int_reg(pcie_top_i_n_20));
+ (* DEST_SYNC_FF = "2" *)
+ (* INIT_SYNC_FF = "0" *)
+ (* SIM_ASSERT_CHK = "0" *)
+ (* SRC_INPUT_REG = "0" *)
+ (* VERSION = "0" *)
+ (* XPM_CDC = "SINGLE" *)
+ (* XPM_MODULE = "TRUE" *)
+ pcie_7x_0_xpm_cdc_single__2 phy_lnk_up_cdc
+ (.dest_clk(pipe_userclk2_in),
+ .dest_out(pl_phy_lnk_up_sync),
+ .src_clk(1'b0),
+ .src_in(pl_phy_lnk_up_wire));
+ FDRE pl_phy_lnk_up_q_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(pl_phy_lnk_up_sync),
+ .Q(pl_phy_lnk_up),
+ .R(gt_top_i_n_120));
+ (* DEST_SYNC_FF = "2" *)
+ (* INIT_SYNC_FF = "0" *)
+ (* SIM_ASSERT_CHK = "0" *)
+ (* SRC_INPUT_REG = "0" *)
+ (* VERSION = "0" *)
+ (* XPM_CDC = "SINGLE" *)
+ (* XPM_MODULE = "TRUE" *)
+ pcie_7x_0_xpm_cdc_single pl_received_hot_rst_cdc
+ (.dest_clk(pipe_userclk2_in),
+ .dest_out(pl_received_hot_rst_sync),
+ .src_clk(1'b0),
+ .src_in(pl_received_hot_rst_wire));
+ FDRE pl_received_hot_rst_q_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(pl_received_hot_rst_sync),
+ .Q(pl_received_hot_rst),
+ .R(gt_top_i_n_120));
+ (* ASYNC_REG *)
+ (* KEEP = "yes" *)
+ FDRE user_lnk_up_int_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(trn_lnk_up),
+ .Q(user_lnk_up_int),
+ .R(gt_top_i_n_120));
+ (* ASYNC_REG *)
+ (* KEEP = "yes" *)
+ FDRE user_lnk_up_mux_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(user_lnk_up_int),
+ .Q(user_lnk_up_mux),
+ .R(gt_top_i_n_120));
+ FDPE user_reset_int_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(pcie_top_i_n_20),
+ .PRE(sys_or_hot_rst),
+ .Q(bridge_reset_int));
+ LUT2 #(
+ .INIT(4'hB))
+ user_reset_out_i_1
+ (.I0(pl_received_hot_rst),
+ .I1(sys_rst_n),
+ .O(sys_or_hot_rst));
+ FDPE user_reset_out_reg
+ (.C(pipe_userclk2_in),
+ .CE(1'b1),
+ .D(bridge_reset_int),
+ .PRE(sys_or_hot_rst),
+ .Q(user_reset_out));
+endmodule
+
+module pcie_7x_0_pcie_7x_0_gt_common
+ (QPLL_QPLLLOCK,
+ QPLL_QPLLOUTCLK,
+ QPLL_QPLLOUTREFCLK,
+ QPLL_DRP_DONE,
+ RST_DCLK_RESET,
+ pipe_dclk_in,
+ sys_clk,
+ QPLL_QPLLPD,
+ QPLL_QPLLRESET,
+ QRST_DRP_START,
+ QPLL_DRP_GEN3);
+ output QPLL_QPLLLOCK;
+ output QPLL_QPLLOUTCLK;
+ output QPLL_QPLLOUTREFCLK;
+ output QPLL_DRP_DONE;
+ input RST_DCLK_RESET;
+ input pipe_dclk_in;
+ input sys_clk;
+ input QPLL_QPLLPD;
+ input QPLL_QPLLRESET;
+ input QRST_DRP_START;
+ input QPLL_DRP_GEN3;
+
+ wire QPLL_DRP_DONE;
+ wire QPLL_DRP_GEN3;
+ wire QPLL_QPLLLOCK;
+ wire QPLL_QPLLOUTCLK;
+ wire QPLL_QPLLOUTREFCLK;
+ wire QPLL_QPLLPD;
+ wire QPLL_QPLLRESET;
+ wire QRST_DRP_START;
+ wire RST_DCLK_RESET;
+ wire pipe_dclk_in;
+ wire [7:0]qpll_drp_addr;
+ wire [15:0]qpll_drp_di;
+ wire [15:0]qpll_drp_do;
+ wire qpll_drp_en;
+ wire qpll_drp_rdy;
+ wire qpll_drp_we;
+ wire sys_clk;
+
+ pcie_7x_0_pcie_7x_0_qpll_drp qpll_drp_i
+ (.D(qpll_drp_do),
+ .Q({qpll_drp_addr[7],qpll_drp_addr[5],qpll_drp_addr[2:0]}),
+ .QPLL_DRP_DONE(QPLL_DRP_DONE),
+ .QPLL_DRP_GEN3(QPLL_DRP_GEN3),
+ .QPLL_QPLLLOCK(QPLL_QPLLLOCK),
+ .QRST_DRP_START(QRST_DRP_START),
+ .RST_DCLK_RESET(RST_DCLK_RESET),
+ .\di_reg[15]_0 (qpll_drp_di),
+ .pipe_dclk_in(pipe_dclk_in),
+ .qpll_drp_en(qpll_drp_en),
+ .qpll_drp_rdy(qpll_drp_rdy),
+ .qpll_drp_we(qpll_drp_we));
+ pcie_7x_0_pcie_7x_0_qpll_wrapper qpll_wrapper_i
+ (.D(qpll_drp_do),
+ .Q({qpll_drp_addr[7],qpll_drp_addr[5],qpll_drp_addr[2:0]}),
+ .QPLL_QPLLLOCK(QPLL_QPLLLOCK),
+ .QPLL_QPLLOUTCLK(QPLL_QPLLOUTCLK),
+ .QPLL_QPLLOUTREFCLK(QPLL_QPLLOUTREFCLK),
+ .QPLL_QPLLPD(QPLL_QPLLPD),
+ .QPLL_QPLLRESET(QPLL_QPLLRESET),
+ .pipe_dclk_in(pipe_dclk_in),
+ .qpll_drp_en(qpll_drp_en),
+ .qpll_drp_rdy(qpll_drp_rdy),
+ .qpll_drp_we(qpll_drp_we),
+ .rdy_reg1_reg(qpll_drp_di),
+ .sys_clk(sys_clk));
+endmodule
+
+module pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x
+ (gt_rxvalid_q_reg_0,
+ gt_rx_phy_status_q,
+ gt_rxelecidle_q,
+ \pl_ltssm_state_q_reg[5] ,
+ Q,
+ D,
+ \gt_rx_status_q_reg[2]_0 ,
+ SR,
+ pipe_pclk_in,
+ gt_rx_phy_status_wire_filter,
+ PIPE_RXELECIDLE,
+ gt_rxvalid_q_reg_1,
+ PIPE_RXSTATUS,
+ \gt_rx_status_q_reg[0]_0 ,
+ PIPE_RXDATAK,
+ PIPE_RXDATA);
+ output gt_rxvalid_q_reg_0;
+ output gt_rx_phy_status_q;
+ output gt_rxelecidle_q;
+ output \pl_ltssm_state_q_reg[5] ;
+ output [15:0]Q;
+ output [1:0]D;
+ output [2:0]\gt_rx_status_q_reg[2]_0 ;
+ input [0:0]SR;
+ input pipe_pclk_in;
+ input [0:0]gt_rx_phy_status_wire_filter;
+ input [0:0]PIPE_RXELECIDLE;
+ input gt_rxvalid_q_reg_1;
+ input [2:0]PIPE_RXSTATUS;
+ input [5:0]\gt_rx_status_q_reg[0]_0 ;
+ input [1:0]PIPE_RXDATAK;
+ input [15:0]PIPE_RXDATA;
+
+ wire [1:0]D;
+ wire [15:0]PIPE_RXDATA;
+ wire [1:0]PIPE_RXDATAK;
+ wire [0:0]PIPE_RXELECIDLE;
+ wire [2:0]PIPE_RXSTATUS;
+ wire [15:0]Q;
+ wire [0:0]SR;
+ wire gt_rx_phy_status_q;
+ wire [0:0]gt_rx_phy_status_wire_filter;
+ wire \gt_rx_status_q[0]_i_1__2_n_0 ;
+ wire \gt_rx_status_q[1]_i_1__2_n_0 ;
+ wire \gt_rx_status_q[2]_i_1__2_n_0 ;
+ wire [5:0]\gt_rx_status_q_reg[0]_0 ;
+ wire [2:0]\gt_rx_status_q_reg[2]_0 ;
+ wire \gt_rxcharisk_q_reg_n_0_[0] ;
+ wire gt_rxelecidle_q;
+ wire gt_rxvalid_q__0;
+ wire gt_rxvalid_q_i_2_n_0;
+ wire gt_rxvalid_q_n_0;
+ wire gt_rxvalid_q_reg_0;
+ wire gt_rxvalid_q_reg_1;
+ wire p_1_in;
+ wire [4:0]p_1_in__0;
+ wire pipe_pclk_in;
+ wire \pl_ltssm_state_q_reg[5] ;
+ wire \reg_state_eios_det[0]_i_2_n_0 ;
+ wire \reg_state_eios_det[0]_i_3_n_0 ;
+ wire \reg_state_eios_det[0]_i_4_n_0 ;
+ wire \reg_state_eios_det[0]_i_5_n_0 ;
+ wire \reg_state_eios_det[1]_i_2_n_0 ;
+ wire \reg_state_eios_det[1]_i_3_n_0 ;
+ wire \reg_state_eios_det[2]_i_2_n_0 ;
+ wire \reg_state_eios_det[2]_i_3_n_0 ;
+ wire \reg_state_eios_det[3]_i_2_n_0 ;
+ wire \reg_state_eios_det[4]_i_1_n_0 ;
+ wire \reg_state_eios_det[4]_i_3_n_0 ;
+ wire reg_symbol_after_eios;
+ wire reg_symbol_after_eios_i_2_n_0;
+ wire [4:0]state_eios_det;
+ wire symbol_after_eios;
+
+ FDRE gt_rx_phy_status_q_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(gt_rx_phy_status_wire_filter),
+ .Q(gt_rx_phy_status_q),
+ .R(SR));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT3 #(
+ .INIT(8'hE0))
+ \gt_rx_status_q[0]_i_1__2
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\pl_ltssm_state_q_reg[5] ),
+ .I2(PIPE_RXSTATUS[0]),
+ .O(\gt_rx_status_q[0]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT3 #(
+ .INIT(8'hE0))
+ \gt_rx_status_q[1]_i_1__2
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\pl_ltssm_state_q_reg[5] ),
+ .I2(PIPE_RXSTATUS[1]),
+ .O(\gt_rx_status_q[1]_i_1__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT3 #(
+ .INIT(8'hE0))
+ \gt_rx_status_q[2]_i_1__2
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\pl_ltssm_state_q_reg[5] ),
+ .I2(PIPE_RXSTATUS[2]),
+ .O(\gt_rx_status_q[2]_i_1__2_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFBFFFFFF))
+ \gt_rx_status_q[2]_i_2
+ (.I0(\gt_rx_status_q_reg[0]_0 [5]),
+ .I1(\gt_rx_status_q_reg[0]_0 [4]),
+ .I2(\gt_rx_status_q_reg[0]_0 [3]),
+ .I3(\gt_rx_status_q_reg[0]_0 [2]),
+ .I4(\gt_rx_status_q_reg[0]_0 [1]),
+ .I5(\gt_rx_status_q_reg[0]_0 [0]),
+ .O(\pl_ltssm_state_q_reg[5] ));
+ FDRE \gt_rx_status_q_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\gt_rx_status_q[0]_i_1__2_n_0 ),
+ .Q(\gt_rx_status_q_reg[2]_0 [0]),
+ .R(SR));
+ FDRE \gt_rx_status_q_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\gt_rx_status_q[1]_i_1__2_n_0 ),
+ .Q(\gt_rx_status_q_reg[2]_0 [1]),
+ .R(SR));
+ FDRE \gt_rx_status_q_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\gt_rx_status_q[2]_i_1__2_n_0 ),
+ .Q(\gt_rx_status_q_reg[2]_0 [2]),
+ .R(SR));
+ FDRE \gt_rxcharisk_q_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATAK[0]),
+ .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
+ .R(SR));
+ FDRE \gt_rxcharisk_q_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATAK[1]),
+ .Q(p_1_in),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[0]),
+ .Q(Q[0]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[10]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[10]),
+ .Q(Q[10]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[11]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[11]),
+ .Q(Q[11]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[12]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[12]),
+ .Q(Q[12]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[13]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[13]),
+ .Q(Q[13]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[14]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[14]),
+ .Q(Q[14]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[15]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[15]),
+ .Q(Q[15]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[1]),
+ .Q(Q[1]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[2]),
+ .Q(Q[2]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[3]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[3]),
+ .Q(Q[3]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[4]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[4]),
+ .Q(Q[4]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[5]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[5]),
+ .Q(Q[5]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[6]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[6]),
+ .Q(Q[6]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[7]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[7]),
+ .Q(Q[7]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[8]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[8]),
+ .Q(Q[8]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[9]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[9]),
+ .Q(Q[9]),
+ .R(SR));
+ FDRE gt_rxelecidle_q_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXELECIDLE),
+ .Q(gt_rxelecidle_q),
+ .R(SR));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT5 #(
+ .INIT(32'h00010116))
+ gt_rxvalid_q
+ (.I0(state_eios_det[0]),
+ .I1(state_eios_det[1]),
+ .I2(state_eios_det[2]),
+ .I3(state_eios_det[3]),
+ .I4(state_eios_det[4]),
+ .O(gt_rxvalid_q_n_0));
+ LUT5 #(
+ .INIT(32'hFFAAEAAA))
+ gt_rxvalid_q_i_1
+ (.I0(gt_rxvalid_q_i_2_n_0),
+ .I1(state_eios_det[2]),
+ .I2(\reg_state_eios_det[3]_i_2_n_0 ),
+ .I3(gt_rxvalid_q_reg_1),
+ .I4(state_eios_det[0]),
+ .O(gt_rxvalid_q__0));
+ LUT6 #(
+ .INIT(64'hFFF50000CC550000))
+ gt_rxvalid_q_i_2
+ (.I0(gt_rxvalid_q_n_0),
+ .I1(\pl_ltssm_state_q_reg[5] ),
+ .I2(\reg_state_eios_det[4]_i_3_n_0 ),
+ .I3(state_eios_det[4]),
+ .I4(gt_rxvalid_q_reg_1),
+ .I5(\reg_state_eios_det[0]_i_3_n_0 ),
+ .O(gt_rxvalid_q_i_2_n_0));
+ FDRE gt_rxvalid_q_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(gt_rxvalid_q__0),
+ .Q(gt_rxvalid_q_reg_0),
+ .R(SR));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
+ .O(D[0]));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT3 #(
+ .INIT(8'h08))
+ \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(p_1_in),
+ .I2(symbol_after_eios),
+ .O(D[1]));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFEFEFEEE))
+ \reg_state_eios_det[0]_i_1
+ (.I0(state_eios_det[4]),
+ .I1(\reg_state_eios_det[0]_i_2_n_0 ),
+ .I2(\reg_state_eios_det[1]_i_2_n_0 ),
+ .I3(\reg_state_eios_det[0]_i_3_n_0 ),
+ .I4(\reg_state_eios_det[0]_i_4_n_0 ),
+ .I5(\reg_state_eios_det[0]_i_5_n_0 ),
+ .O(p_1_in__0[0]));
+ LUT6 #(
+ .INIT(64'hFFF3AAFFAA00AAAA))
+ \reg_state_eios_det[0]_i_2
+ (.I0(state_eios_det[2]),
+ .I1(Q[7]),
+ .I2(Q[6]),
+ .I3(Q[15]),
+ .I4(Q[14]),
+ .I5(state_eios_det[0]),
+ .O(\reg_state_eios_det[0]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT3 #(
+ .INIT(8'hFE))
+ \reg_state_eios_det[0]_i_3
+ (.I0(state_eios_det[3]),
+ .I1(state_eios_det[1]),
+ .I2(state_eios_det[2]),
+ .O(\reg_state_eios_det[0]_i_3_n_0 ));
+ LUT2 #(
+ .INIT(4'h8))
+ \reg_state_eios_det[0]_i_4
+ (.I0(Q[14]),
+ .I1(state_eios_det[0]),
+ .O(\reg_state_eios_det[0]_i_4_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFE0E0E0FFE0FFE0))
+ \reg_state_eios_det[0]_i_5
+ (.I0(state_eios_det[0]),
+ .I1(state_eios_det[2]),
+ .I2(\reg_state_eios_det[2]_i_2_n_0 ),
+ .I3(\reg_state_eios_det[0]_i_3_n_0 ),
+ .I4(Q[7]),
+ .I5(Q[6]),
+ .O(\reg_state_eios_det[0]_i_5_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT5 #(
+ .INIT(32'h00000040))
+ \reg_state_eios_det[1]_i_1
+ (.I0(\reg_state_eios_det[1]_i_2_n_0 ),
+ .I1(state_eios_det[0]),
+ .I2(Q[7]),
+ .I3(Q[6]),
+ .I4(\reg_state_eios_det[3]_i_2_n_0 ),
+ .O(p_1_in__0[1]));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT4 #(
+ .INIT(16'hBFFF))
+ \reg_state_eios_det[1]_i_2
+ (.I0(\reg_state_eios_det[1]_i_3_n_0 ),
+ .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
+ .I2(Q[4]),
+ .I3(Q[5]),
+ .O(\reg_state_eios_det[1]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'hEFFF))
+ \reg_state_eios_det[1]_i_3
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(Q[3]),
+ .I3(Q[2]),
+ .O(\reg_state_eios_det[1]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT4 #(
+ .INIT(16'h0040))
+ \reg_state_eios_det[2]_i_1
+ (.I0(Q[14]),
+ .I1(Q[15]),
+ .I2(state_eios_det[0]),
+ .I3(\reg_state_eios_det[2]_i_2_n_0 ),
+ .O(p_1_in__0[2]));
+ LUT4 #(
+ .INIT(16'hBFFF))
+ \reg_state_eios_det[2]_i_2
+ (.I0(\reg_state_eios_det[2]_i_3_n_0 ),
+ .I1(p_1_in),
+ .I2(Q[12]),
+ .I3(Q[13]),
+ .O(\reg_state_eios_det[2]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'hEFFF))
+ \reg_state_eios_det[2]_i_3
+ (.I0(Q[9]),
+ .I1(Q[8]),
+ .I2(Q[11]),
+ .I3(Q[10]),
+ .O(\reg_state_eios_det[2]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT3 #(
+ .INIT(8'h04))
+ \reg_state_eios_det[3]_i_1
+ (.I0(\reg_state_eios_det[3]_i_2_n_0 ),
+ .I1(state_eios_det[2]),
+ .I2(\reg_state_eios_det[4]_i_3_n_0 ),
+ .O(p_1_in__0[3]));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT3 #(
+ .INIT(8'hFD))
+ \reg_state_eios_det[3]_i_2
+ (.I0(Q[14]),
+ .I1(Q[15]),
+ .I2(\reg_state_eios_det[2]_i_2_n_0 ),
+ .O(\reg_state_eios_det[3]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'h00010116))
+ \reg_state_eios_det[4]_i_1
+ (.I0(state_eios_det[0]),
+ .I1(state_eios_det[4]),
+ .I2(state_eios_det[2]),
+ .I3(state_eios_det[1]),
+ .I4(state_eios_det[3]),
+ .O(\reg_state_eios_det[4]_i_1_n_0 ));
+ LUT3 #(
+ .INIT(8'h0E))
+ \reg_state_eios_det[4]_i_2
+ (.I0(state_eios_det[3]),
+ .I1(state_eios_det[1]),
+ .I2(\reg_state_eios_det[4]_i_3_n_0 ),
+ .O(p_1_in__0[4]));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT3 #(
+ .INIT(8'hFD))
+ \reg_state_eios_det[4]_i_3
+ (.I0(Q[6]),
+ .I1(Q[7]),
+ .I2(\reg_state_eios_det[1]_i_2_n_0 ),
+ .O(\reg_state_eios_det[4]_i_3_n_0 ));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDSE \reg_state_eios_det_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1_n_0 ),
+ .D(p_1_in__0[0]),
+ .Q(state_eios_det[0]),
+ .S(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1_n_0 ),
+ .D(p_1_in__0[1]),
+ .Q(state_eios_det[1]),
+ .R(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1_n_0 ),
+ .D(p_1_in__0[2]),
+ .Q(state_eios_det[2]),
+ .R(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[3]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1_n_0 ),
+ .D(p_1_in__0[3]),
+ .Q(state_eios_det[3]),
+ .R(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[4]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1_n_0 ),
+ .D(p_1_in__0[4]),
+ .Q(state_eios_det[4]),
+ .R(SR));
+ LUT6 #(
+ .INIT(64'h0000000000000010))
+ reg_symbol_after_eios_i_1
+ (.I0(\reg_state_eios_det[3]_i_2_n_0 ),
+ .I1(state_eios_det[0]),
+ .I2(state_eios_det[2]),
+ .I3(state_eios_det[3]),
+ .I4(state_eios_det[1]),
+ .I5(reg_symbol_after_eios_i_2_n_0),
+ .O(reg_symbol_after_eios));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT2 #(
+ .INIT(4'hE))
+ reg_symbol_after_eios_i_2
+ (.I0(\reg_state_eios_det[4]_i_3_n_0 ),
+ .I1(state_eios_det[4]),
+ .O(reg_symbol_after_eios_i_2_n_0));
+ FDRE reg_symbol_after_eios_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(reg_symbol_after_eios),
+ .Q(symbol_after_eios),
+ .R(SR));
+endmodule
+
+(* ORIG_REF_NAME = "pcie_7x_0_gt_rx_valid_filter_7x" *)
+module pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_34
+ (gt_rxvalid_q_reg_0,
+ gt_rx_phy_status_q_reg_0,
+ gt_rxelecidle_q_reg_0,
+ Q,
+ gt_rxvalid_q_reg_1,
+ \gt_rx_status_q_reg[2]_0 ,
+ SR,
+ pipe_pclk_in,
+ gt_rx_phy_status_wire_filter,
+ PIPE_RXELECIDLE,
+ gt_rxvalid_q_reg_2,
+ \gt_rx_status_q_reg[0]_0 ,
+ PIPE_RXSTATUS,
+ PIPE_RXDATAK,
+ PIPE_RXDATA);
+ output gt_rxvalid_q_reg_0;
+ output gt_rx_phy_status_q_reg_0;
+ output gt_rxelecidle_q_reg_0;
+ output [15:0]Q;
+ output [1:0]gt_rxvalid_q_reg_1;
+ output [2:0]\gt_rx_status_q_reg[2]_0 ;
+ input [0:0]SR;
+ input pipe_pclk_in;
+ input [0:0]gt_rx_phy_status_wire_filter;
+ input [0:0]PIPE_RXELECIDLE;
+ input gt_rxvalid_q_reg_2;
+ input \gt_rx_status_q_reg[0]_0 ;
+ input [2:0]PIPE_RXSTATUS;
+ input [1:0]PIPE_RXDATAK;
+ input [15:0]PIPE_RXDATA;
+
+ wire [15:0]PIPE_RXDATA;
+ wire [1:0]PIPE_RXDATAK;
+ wire [0:0]PIPE_RXELECIDLE;
+ wire [2:0]PIPE_RXSTATUS;
+ wire [15:0]Q;
+ wire [0:0]SR;
+ wire gt_rx_phy_status_q_reg_0;
+ wire [0:0]gt_rx_phy_status_wire_filter;
+ wire \gt_rx_status_q[0]_i_1__1_n_0 ;
+ wire \gt_rx_status_q[1]_i_1__1_n_0 ;
+ wire \gt_rx_status_q[2]_i_1__1_n_0 ;
+ wire \gt_rx_status_q_reg[0]_0 ;
+ wire [2:0]\gt_rx_status_q_reg[2]_0 ;
+ wire \gt_rxcharisk_q_reg_n_0_[0] ;
+ wire gt_rxelecidle_q_reg_0;
+ wire gt_rxvalid_q__0;
+ wire gt_rxvalid_q_i_2__0_n_0;
+ wire gt_rxvalid_q_n_0;
+ wire gt_rxvalid_q_reg_0;
+ wire [1:0]gt_rxvalid_q_reg_1;
+ wire gt_rxvalid_q_reg_2;
+ wire p_1_in;
+ wire [4:0]p_1_in__0;
+ wire pipe_pclk_in;
+ wire \reg_state_eios_det[0]_i_2__0_n_0 ;
+ wire \reg_state_eios_det[0]_i_3__0_n_0 ;
+ wire \reg_state_eios_det[0]_i_4__0_n_0 ;
+ wire \reg_state_eios_det[0]_i_5__0_n_0 ;
+ wire \reg_state_eios_det[1]_i_2__0_n_0 ;
+ wire \reg_state_eios_det[1]_i_3__0_n_0 ;
+ wire \reg_state_eios_det[2]_i_2__0_n_0 ;
+ wire \reg_state_eios_det[2]_i_3__0_n_0 ;
+ wire \reg_state_eios_det[3]_i_2__0_n_0 ;
+ wire \reg_state_eios_det[4]_i_1__0_n_0 ;
+ wire \reg_state_eios_det[4]_i_3__0_n_0 ;
+ wire reg_symbol_after_eios;
+ wire reg_symbol_after_eios_i_2__0_n_0;
+ wire [4:0]state_eios_det;
+ wire symbol_after_eios;
+
+ FDRE gt_rx_phy_status_q_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(gt_rx_phy_status_wire_filter),
+ .Q(gt_rx_phy_status_q_reg_0),
+ .R(SR));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT3 #(
+ .INIT(8'hE0))
+ \gt_rx_status_q[0]_i_1__1
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\gt_rx_status_q_reg[0]_0 ),
+ .I2(PIPE_RXSTATUS[0]),
+ .O(\gt_rx_status_q[0]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT3 #(
+ .INIT(8'hE0))
+ \gt_rx_status_q[1]_i_1__1
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\gt_rx_status_q_reg[0]_0 ),
+ .I2(PIPE_RXSTATUS[1]),
+ .O(\gt_rx_status_q[1]_i_1__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT3 #(
+ .INIT(8'hE0))
+ \gt_rx_status_q[2]_i_1__1
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\gt_rx_status_q_reg[0]_0 ),
+ .I2(PIPE_RXSTATUS[2]),
+ .O(\gt_rx_status_q[2]_i_1__1_n_0 ));
+ FDRE \gt_rx_status_q_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\gt_rx_status_q[0]_i_1__1_n_0 ),
+ .Q(\gt_rx_status_q_reg[2]_0 [0]),
+ .R(SR));
+ FDRE \gt_rx_status_q_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\gt_rx_status_q[1]_i_1__1_n_0 ),
+ .Q(\gt_rx_status_q_reg[2]_0 [1]),
+ .R(SR));
+ FDRE \gt_rx_status_q_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\gt_rx_status_q[2]_i_1__1_n_0 ),
+ .Q(\gt_rx_status_q_reg[2]_0 [2]),
+ .R(SR));
+ FDRE \gt_rxcharisk_q_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATAK[0]),
+ .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
+ .R(SR));
+ FDRE \gt_rxcharisk_q_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATAK[1]),
+ .Q(p_1_in),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[0]),
+ .Q(Q[0]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[10]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[10]),
+ .Q(Q[10]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[11]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[11]),
+ .Q(Q[11]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[12]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[12]),
+ .Q(Q[12]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[13]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[13]),
+ .Q(Q[13]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[14]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[14]),
+ .Q(Q[14]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[15]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[15]),
+ .Q(Q[15]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[1]),
+ .Q(Q[1]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[2]),
+ .Q(Q[2]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[3]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[3]),
+ .Q(Q[3]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[4]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[4]),
+ .Q(Q[4]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[5]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[5]),
+ .Q(Q[5]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[6]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[6]),
+ .Q(Q[6]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[7]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[7]),
+ .Q(Q[7]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[8]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[8]),
+ .Q(Q[8]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[9]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[9]),
+ .Q(Q[9]),
+ .R(SR));
+ FDRE gt_rxelecidle_q_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXELECIDLE),
+ .Q(gt_rxelecidle_q_reg_0),
+ .R(SR));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT5 #(
+ .INIT(32'h00010116))
+ gt_rxvalid_q
+ (.I0(state_eios_det[0]),
+ .I1(state_eios_det[1]),
+ .I2(state_eios_det[2]),
+ .I3(state_eios_det[3]),
+ .I4(state_eios_det[4]),
+ .O(gt_rxvalid_q_n_0));
+ LUT5 #(
+ .INIT(32'hFFAAEAAA))
+ gt_rxvalid_q_i_1__0
+ (.I0(gt_rxvalid_q_i_2__0_n_0),
+ .I1(state_eios_det[2]),
+ .I2(\reg_state_eios_det[3]_i_2__0_n_0 ),
+ .I3(gt_rxvalid_q_reg_2),
+ .I4(state_eios_det[0]),
+ .O(gt_rxvalid_q__0));
+ LUT6 #(
+ .INIT(64'hFFF50000CC550000))
+ gt_rxvalid_q_i_2__0
+ (.I0(gt_rxvalid_q_n_0),
+ .I1(\gt_rx_status_q_reg[0]_0 ),
+ .I2(\reg_state_eios_det[4]_i_3__0_n_0 ),
+ .I3(state_eios_det[4]),
+ .I4(gt_rxvalid_q_reg_2),
+ .I5(\reg_state_eios_det[0]_i_3__0_n_0 ),
+ .O(gt_rxvalid_q_i_2__0_n_0));
+ FDRE gt_rxvalid_q_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(gt_rxvalid_q__0),
+ .Q(gt_rxvalid_q_reg_0),
+ .R(SR));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__0
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
+ .O(gt_rxvalid_q_reg_1[0]));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT3 #(
+ .INIT(8'h08))
+ \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__0
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(p_1_in),
+ .I2(symbol_after_eios),
+ .O(gt_rxvalid_q_reg_1[1]));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFEFEFEEE))
+ \reg_state_eios_det[0]_i_1__0
+ (.I0(state_eios_det[4]),
+ .I1(\reg_state_eios_det[0]_i_2__0_n_0 ),
+ .I2(\reg_state_eios_det[1]_i_2__0_n_0 ),
+ .I3(\reg_state_eios_det[0]_i_3__0_n_0 ),
+ .I4(\reg_state_eios_det[0]_i_4__0_n_0 ),
+ .I5(\reg_state_eios_det[0]_i_5__0_n_0 ),
+ .O(p_1_in__0[0]));
+ LUT6 #(
+ .INIT(64'hFFF3AAFFAA00AAAA))
+ \reg_state_eios_det[0]_i_2__0
+ (.I0(state_eios_det[2]),
+ .I1(Q[7]),
+ .I2(Q[6]),
+ .I3(Q[15]),
+ .I4(Q[14]),
+ .I5(state_eios_det[0]),
+ .O(\reg_state_eios_det[0]_i_2__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT3 #(
+ .INIT(8'hFE))
+ \reg_state_eios_det[0]_i_3__0
+ (.I0(state_eios_det[3]),
+ .I1(state_eios_det[1]),
+ .I2(state_eios_det[2]),
+ .O(\reg_state_eios_det[0]_i_3__0_n_0 ));
+ LUT2 #(
+ .INIT(4'h8))
+ \reg_state_eios_det[0]_i_4__0
+ (.I0(Q[14]),
+ .I1(state_eios_det[0]),
+ .O(\reg_state_eios_det[0]_i_4__0_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFE0E0E0FFE0FFE0))
+ \reg_state_eios_det[0]_i_5__0
+ (.I0(state_eios_det[0]),
+ .I1(state_eios_det[2]),
+ .I2(\reg_state_eios_det[2]_i_2__0_n_0 ),
+ .I3(\reg_state_eios_det[0]_i_3__0_n_0 ),
+ .I4(Q[7]),
+ .I5(Q[6]),
+ .O(\reg_state_eios_det[0]_i_5__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT5 #(
+ .INIT(32'h00000040))
+ \reg_state_eios_det[1]_i_1__0
+ (.I0(\reg_state_eios_det[1]_i_2__0_n_0 ),
+ .I1(state_eios_det[0]),
+ .I2(Q[7]),
+ .I3(Q[6]),
+ .I4(\reg_state_eios_det[3]_i_2__0_n_0 ),
+ .O(p_1_in__0[1]));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT4 #(
+ .INIT(16'hBFFF))
+ \reg_state_eios_det[1]_i_2__0
+ (.I0(\reg_state_eios_det[1]_i_3__0_n_0 ),
+ .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
+ .I2(Q[4]),
+ .I3(Q[5]),
+ .O(\reg_state_eios_det[1]_i_2__0_n_0 ));
+ LUT4 #(
+ .INIT(16'hEFFF))
+ \reg_state_eios_det[1]_i_3__0
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(Q[3]),
+ .I3(Q[2]),
+ .O(\reg_state_eios_det[1]_i_3__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT4 #(
+ .INIT(16'h0040))
+ \reg_state_eios_det[2]_i_1__0
+ (.I0(Q[14]),
+ .I1(Q[15]),
+ .I2(state_eios_det[0]),
+ .I3(\reg_state_eios_det[2]_i_2__0_n_0 ),
+ .O(p_1_in__0[2]));
+ LUT4 #(
+ .INIT(16'hBFFF))
+ \reg_state_eios_det[2]_i_2__0
+ (.I0(\reg_state_eios_det[2]_i_3__0_n_0 ),
+ .I1(p_1_in),
+ .I2(Q[12]),
+ .I3(Q[13]),
+ .O(\reg_state_eios_det[2]_i_2__0_n_0 ));
+ LUT4 #(
+ .INIT(16'hEFFF))
+ \reg_state_eios_det[2]_i_3__0
+ (.I0(Q[9]),
+ .I1(Q[8]),
+ .I2(Q[11]),
+ .I3(Q[10]),
+ .O(\reg_state_eios_det[2]_i_3__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT3 #(
+ .INIT(8'h04))
+ \reg_state_eios_det[3]_i_1__0
+ (.I0(\reg_state_eios_det[3]_i_2__0_n_0 ),
+ .I1(state_eios_det[2]),
+ .I2(\reg_state_eios_det[4]_i_3__0_n_0 ),
+ .O(p_1_in__0[3]));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT3 #(
+ .INIT(8'hFD))
+ \reg_state_eios_det[3]_i_2__0
+ (.I0(Q[14]),
+ .I1(Q[15]),
+ .I2(\reg_state_eios_det[2]_i_2__0_n_0 ),
+ .O(\reg_state_eios_det[3]_i_2__0_n_0 ));
+ LUT5 #(
+ .INIT(32'h00010116))
+ \reg_state_eios_det[4]_i_1__0
+ (.I0(state_eios_det[0]),
+ .I1(state_eios_det[4]),
+ .I2(state_eios_det[2]),
+ .I3(state_eios_det[1]),
+ .I4(state_eios_det[3]),
+ .O(\reg_state_eios_det[4]_i_1__0_n_0 ));
+ LUT3 #(
+ .INIT(8'h0E))
+ \reg_state_eios_det[4]_i_2__0
+ (.I0(state_eios_det[3]),
+ .I1(state_eios_det[1]),
+ .I2(\reg_state_eios_det[4]_i_3__0_n_0 ),
+ .O(p_1_in__0[4]));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT3 #(
+ .INIT(8'hFD))
+ \reg_state_eios_det[4]_i_3__0
+ (.I0(Q[6]),
+ .I1(Q[7]),
+ .I2(\reg_state_eios_det[1]_i_2__0_n_0 ),
+ .O(\reg_state_eios_det[4]_i_3__0_n_0 ));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDSE \reg_state_eios_det_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__0_n_0 ),
+ .D(p_1_in__0[0]),
+ .Q(state_eios_det[0]),
+ .S(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__0_n_0 ),
+ .D(p_1_in__0[1]),
+ .Q(state_eios_det[1]),
+ .R(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__0_n_0 ),
+ .D(p_1_in__0[2]),
+ .Q(state_eios_det[2]),
+ .R(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[3]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__0_n_0 ),
+ .D(p_1_in__0[3]),
+ .Q(state_eios_det[3]),
+ .R(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[4]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__0_n_0 ),
+ .D(p_1_in__0[4]),
+ .Q(state_eios_det[4]),
+ .R(SR));
+ LUT6 #(
+ .INIT(64'h0000000000000010))
+ reg_symbol_after_eios_i_1__0
+ (.I0(\reg_state_eios_det[3]_i_2__0_n_0 ),
+ .I1(state_eios_det[0]),
+ .I2(state_eios_det[2]),
+ .I3(state_eios_det[3]),
+ .I4(state_eios_det[1]),
+ .I5(reg_symbol_after_eios_i_2__0_n_0),
+ .O(reg_symbol_after_eios));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT2 #(
+ .INIT(4'hE))
+ reg_symbol_after_eios_i_2__0
+ (.I0(\reg_state_eios_det[4]_i_3__0_n_0 ),
+ .I1(state_eios_det[4]),
+ .O(reg_symbol_after_eios_i_2__0_n_0));
+ FDRE reg_symbol_after_eios_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(reg_symbol_after_eios),
+ .Q(symbol_after_eios),
+ .R(SR));
+endmodule
+
+(* ORIG_REF_NAME = "pcie_7x_0_gt_rx_valid_filter_7x" *)
+module pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_35
+ (gt_rxvalid_q_reg_0,
+ gt_rx_phy_status_q_reg_0,
+ gt_rxelecidle_q_reg_0,
+ Q,
+ gt_rxvalid_q_reg_1,
+ \gt_rx_status_q_reg[2]_0 ,
+ SR,
+ pipe_pclk_in,
+ gt_rx_phy_status_wire_filter,
+ PIPE_RXELECIDLE,
+ gt_rxvalid_q_reg_2,
+ \gt_rx_status_q_reg[0]_0 ,
+ PIPE_RXSTATUS,
+ PIPE_RXDATAK,
+ PIPE_RXDATA);
+ output gt_rxvalid_q_reg_0;
+ output gt_rx_phy_status_q_reg_0;
+ output gt_rxelecidle_q_reg_0;
+ output [15:0]Q;
+ output [1:0]gt_rxvalid_q_reg_1;
+ output [2:0]\gt_rx_status_q_reg[2]_0 ;
+ input [0:0]SR;
+ input pipe_pclk_in;
+ input [0:0]gt_rx_phy_status_wire_filter;
+ input [0:0]PIPE_RXELECIDLE;
+ input gt_rxvalid_q_reg_2;
+ input \gt_rx_status_q_reg[0]_0 ;
+ input [2:0]PIPE_RXSTATUS;
+ input [1:0]PIPE_RXDATAK;
+ input [15:0]PIPE_RXDATA;
+
+ wire [15:0]PIPE_RXDATA;
+ wire [1:0]PIPE_RXDATAK;
+ wire [0:0]PIPE_RXELECIDLE;
+ wire [2:0]PIPE_RXSTATUS;
+ wire [15:0]Q;
+ wire [0:0]SR;
+ wire gt_rx_phy_status_q_reg_0;
+ wire [0:0]gt_rx_phy_status_wire_filter;
+ wire \gt_rx_status_q[0]_i_1__0_n_0 ;
+ wire \gt_rx_status_q[1]_i_1__0_n_0 ;
+ wire \gt_rx_status_q[2]_i_1__0_n_0 ;
+ wire \gt_rx_status_q_reg[0]_0 ;
+ wire [2:0]\gt_rx_status_q_reg[2]_0 ;
+ wire \gt_rxcharisk_q_reg_n_0_[0] ;
+ wire gt_rxelecidle_q_reg_0;
+ wire gt_rxvalid_q__0;
+ wire gt_rxvalid_q_i_2__1_n_0;
+ wire gt_rxvalid_q_n_0;
+ wire gt_rxvalid_q_reg_0;
+ wire [1:0]gt_rxvalid_q_reg_1;
+ wire gt_rxvalid_q_reg_2;
+ wire p_1_in;
+ wire [4:0]p_1_in__0;
+ wire pipe_pclk_in;
+ wire \reg_state_eios_det[0]_i_2__1_n_0 ;
+ wire \reg_state_eios_det[0]_i_3__1_n_0 ;
+ wire \reg_state_eios_det[0]_i_4__1_n_0 ;
+ wire \reg_state_eios_det[0]_i_5__1_n_0 ;
+ wire \reg_state_eios_det[1]_i_2__1_n_0 ;
+ wire \reg_state_eios_det[1]_i_3__1_n_0 ;
+ wire \reg_state_eios_det[2]_i_2__1_n_0 ;
+ wire \reg_state_eios_det[2]_i_3__1_n_0 ;
+ wire \reg_state_eios_det[3]_i_2__1_n_0 ;
+ wire \reg_state_eios_det[4]_i_1__1_n_0 ;
+ wire \reg_state_eios_det[4]_i_3__1_n_0 ;
+ wire reg_symbol_after_eios;
+ wire reg_symbol_after_eios_i_2__1_n_0;
+ wire [4:0]state_eios_det;
+ wire symbol_after_eios;
+
+ FDRE gt_rx_phy_status_q_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(gt_rx_phy_status_wire_filter),
+ .Q(gt_rx_phy_status_q_reg_0),
+ .R(SR));
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
+ LUT3 #(
+ .INIT(8'hE0))
+ \gt_rx_status_q[0]_i_1__0
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\gt_rx_status_q_reg[0]_0 ),
+ .I2(PIPE_RXSTATUS[0]),
+ .O(\gt_rx_status_q[0]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
+ LUT3 #(
+ .INIT(8'hE0))
+ \gt_rx_status_q[1]_i_1__0
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\gt_rx_status_q_reg[0]_0 ),
+ .I2(PIPE_RXSTATUS[1]),
+ .O(\gt_rx_status_q[1]_i_1__0_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
+ LUT3 #(
+ .INIT(8'hE0))
+ \gt_rx_status_q[2]_i_1__0
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\gt_rx_status_q_reg[0]_0 ),
+ .I2(PIPE_RXSTATUS[2]),
+ .O(\gt_rx_status_q[2]_i_1__0_n_0 ));
+ FDRE \gt_rx_status_q_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\gt_rx_status_q[0]_i_1__0_n_0 ),
+ .Q(\gt_rx_status_q_reg[2]_0 [0]),
+ .R(SR));
+ FDRE \gt_rx_status_q_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\gt_rx_status_q[1]_i_1__0_n_0 ),
+ .Q(\gt_rx_status_q_reg[2]_0 [1]),
+ .R(SR));
+ FDRE \gt_rx_status_q_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\gt_rx_status_q[2]_i_1__0_n_0 ),
+ .Q(\gt_rx_status_q_reg[2]_0 [2]),
+ .R(SR));
+ FDRE \gt_rxcharisk_q_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATAK[0]),
+ .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
+ .R(SR));
+ FDRE \gt_rxcharisk_q_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATAK[1]),
+ .Q(p_1_in),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[0]),
+ .Q(Q[0]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[10]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[10]),
+ .Q(Q[10]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[11]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[11]),
+ .Q(Q[11]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[12]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[12]),
+ .Q(Q[12]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[13]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[13]),
+ .Q(Q[13]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[14]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[14]),
+ .Q(Q[14]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[15]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[15]),
+ .Q(Q[15]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[1]),
+ .Q(Q[1]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[2]),
+ .Q(Q[2]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[3]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[3]),
+ .Q(Q[3]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[4]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[4]),
+ .Q(Q[4]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[5]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[5]),
+ .Q(Q[5]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[6]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[6]),
+ .Q(Q[6]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[7]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[7]),
+ .Q(Q[7]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[8]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[8]),
+ .Q(Q[8]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[9]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[9]),
+ .Q(Q[9]),
+ .R(SR));
+ FDRE gt_rxelecidle_q_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXELECIDLE),
+ .Q(gt_rxelecidle_q_reg_0),
+ .R(SR));
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
+ LUT5 #(
+ .INIT(32'h00010116))
+ gt_rxvalid_q
+ (.I0(state_eios_det[0]),
+ .I1(state_eios_det[1]),
+ .I2(state_eios_det[2]),
+ .I3(state_eios_det[3]),
+ .I4(state_eios_det[4]),
+ .O(gt_rxvalid_q_n_0));
+ LUT5 #(
+ .INIT(32'hFFAAEAAA))
+ gt_rxvalid_q_i_1__1
+ (.I0(gt_rxvalid_q_i_2__1_n_0),
+ .I1(state_eios_det[2]),
+ .I2(\reg_state_eios_det[3]_i_2__1_n_0 ),
+ .I3(gt_rxvalid_q_reg_2),
+ .I4(state_eios_det[0]),
+ .O(gt_rxvalid_q__0));
+ LUT6 #(
+ .INIT(64'hFFF50000CC550000))
+ gt_rxvalid_q_i_2__1
+ (.I0(gt_rxvalid_q_n_0),
+ .I1(\gt_rx_status_q_reg[0]_0 ),
+ .I2(\reg_state_eios_det[4]_i_3__1_n_0 ),
+ .I3(state_eios_det[4]),
+ .I4(gt_rxvalid_q_reg_2),
+ .I5(\reg_state_eios_det[0]_i_3__1_n_0 ),
+ .O(gt_rxvalid_q_i_2__1_n_0));
+ FDRE gt_rxvalid_q_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(gt_rxvalid_q__0),
+ .Q(gt_rxvalid_q_reg_0),
+ .R(SR));
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__1
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
+ .O(gt_rxvalid_q_reg_1[0]));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
+ LUT3 #(
+ .INIT(8'h08))
+ \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__1
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(p_1_in),
+ .I2(symbol_after_eios),
+ .O(gt_rxvalid_q_reg_1[1]));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFEFEFEEE))
+ \reg_state_eios_det[0]_i_1__1
+ (.I0(state_eios_det[4]),
+ .I1(\reg_state_eios_det[0]_i_2__1_n_0 ),
+ .I2(\reg_state_eios_det[1]_i_2__1_n_0 ),
+ .I3(\reg_state_eios_det[0]_i_3__1_n_0 ),
+ .I4(\reg_state_eios_det[0]_i_4__1_n_0 ),
+ .I5(\reg_state_eios_det[0]_i_5__1_n_0 ),
+ .O(p_1_in__0[0]));
+ LUT6 #(
+ .INIT(64'hFFF3AAFFAA00AAAA))
+ \reg_state_eios_det[0]_i_2__1
+ (.I0(state_eios_det[2]),
+ .I1(Q[7]),
+ .I2(Q[6]),
+ .I3(Q[15]),
+ .I4(Q[14]),
+ .I5(state_eios_det[0]),
+ .O(\reg_state_eios_det[0]_i_2__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
+ LUT3 #(
+ .INIT(8'hFE))
+ \reg_state_eios_det[0]_i_3__1
+ (.I0(state_eios_det[3]),
+ .I1(state_eios_det[1]),
+ .I2(state_eios_det[2]),
+ .O(\reg_state_eios_det[0]_i_3__1_n_0 ));
+ LUT2 #(
+ .INIT(4'h8))
+ \reg_state_eios_det[0]_i_4__1
+ (.I0(Q[14]),
+ .I1(state_eios_det[0]),
+ .O(\reg_state_eios_det[0]_i_4__1_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFE0E0E0FFE0FFE0))
+ \reg_state_eios_det[0]_i_5__1
+ (.I0(state_eios_det[0]),
+ .I1(state_eios_det[2]),
+ .I2(\reg_state_eios_det[2]_i_2__1_n_0 ),
+ .I3(\reg_state_eios_det[0]_i_3__1_n_0 ),
+ .I4(Q[7]),
+ .I5(Q[6]),
+ .O(\reg_state_eios_det[0]_i_5__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT5 #(
+ .INIT(32'h00000040))
+ \reg_state_eios_det[1]_i_1__1
+ (.I0(\reg_state_eios_det[1]_i_2__1_n_0 ),
+ .I1(state_eios_det[0]),
+ .I2(Q[7]),
+ .I3(Q[6]),
+ .I4(\reg_state_eios_det[3]_i_2__1_n_0 ),
+ .O(p_1_in__0[1]));
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT4 #(
+ .INIT(16'hBFFF))
+ \reg_state_eios_det[1]_i_2__1
+ (.I0(\reg_state_eios_det[1]_i_3__1_n_0 ),
+ .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
+ .I2(Q[4]),
+ .I3(Q[5]),
+ .O(\reg_state_eios_det[1]_i_2__1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEFFF))
+ \reg_state_eios_det[1]_i_3__1
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(Q[3]),
+ .I3(Q[2]),
+ .O(\reg_state_eios_det[1]_i_3__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
+ LUT4 #(
+ .INIT(16'h0040))
+ \reg_state_eios_det[2]_i_1__1
+ (.I0(Q[14]),
+ .I1(Q[15]),
+ .I2(state_eios_det[0]),
+ .I3(\reg_state_eios_det[2]_i_2__1_n_0 ),
+ .O(p_1_in__0[2]));
+ LUT4 #(
+ .INIT(16'hBFFF))
+ \reg_state_eios_det[2]_i_2__1
+ (.I0(\reg_state_eios_det[2]_i_3__1_n_0 ),
+ .I1(p_1_in),
+ .I2(Q[12]),
+ .I3(Q[13]),
+ .O(\reg_state_eios_det[2]_i_2__1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEFFF))
+ \reg_state_eios_det[2]_i_3__1
+ (.I0(Q[9]),
+ .I1(Q[8]),
+ .I2(Q[11]),
+ .I3(Q[10]),
+ .O(\reg_state_eios_det[2]_i_3__1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
+ LUT3 #(
+ .INIT(8'h04))
+ \reg_state_eios_det[3]_i_1__1
+ (.I0(\reg_state_eios_det[3]_i_2__1_n_0 ),
+ .I1(state_eios_det[2]),
+ .I2(\reg_state_eios_det[4]_i_3__1_n_0 ),
+ .O(p_1_in__0[3]));
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
+ LUT3 #(
+ .INIT(8'hFD))
+ \reg_state_eios_det[3]_i_2__1
+ (.I0(Q[14]),
+ .I1(Q[15]),
+ .I2(\reg_state_eios_det[2]_i_2__1_n_0 ),
+ .O(\reg_state_eios_det[3]_i_2__1_n_0 ));
+ LUT5 #(
+ .INIT(32'h00010116))
+ \reg_state_eios_det[4]_i_1__1
+ (.I0(state_eios_det[0]),
+ .I1(state_eios_det[4]),
+ .I2(state_eios_det[2]),
+ .I3(state_eios_det[1]),
+ .I4(state_eios_det[3]),
+ .O(\reg_state_eios_det[4]_i_1__1_n_0 ));
+ LUT3 #(
+ .INIT(8'h0E))
+ \reg_state_eios_det[4]_i_2__1
+ (.I0(state_eios_det[3]),
+ .I1(state_eios_det[1]),
+ .I2(\reg_state_eios_det[4]_i_3__1_n_0 ),
+ .O(p_1_in__0[4]));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT3 #(
+ .INIT(8'hFD))
+ \reg_state_eios_det[4]_i_3__1
+ (.I0(Q[6]),
+ .I1(Q[7]),
+ .I2(\reg_state_eios_det[1]_i_2__1_n_0 ),
+ .O(\reg_state_eios_det[4]_i_3__1_n_0 ));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDSE \reg_state_eios_det_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__1_n_0 ),
+ .D(p_1_in__0[0]),
+ .Q(state_eios_det[0]),
+ .S(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__1_n_0 ),
+ .D(p_1_in__0[1]),
+ .Q(state_eios_det[1]),
+ .R(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__1_n_0 ),
+ .D(p_1_in__0[2]),
+ .Q(state_eios_det[2]),
+ .R(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[3]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__1_n_0 ),
+ .D(p_1_in__0[3]),
+ .Q(state_eios_det[3]),
+ .R(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[4]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__1_n_0 ),
+ .D(p_1_in__0[4]),
+ .Q(state_eios_det[4]),
+ .R(SR));
+ LUT6 #(
+ .INIT(64'h0000000000000010))
+ reg_symbol_after_eios_i_1__1
+ (.I0(\reg_state_eios_det[3]_i_2__1_n_0 ),
+ .I1(state_eios_det[0]),
+ .I2(state_eios_det[2]),
+ .I3(state_eios_det[3]),
+ .I4(state_eios_det[1]),
+ .I5(reg_symbol_after_eios_i_2__1_n_0),
+ .O(reg_symbol_after_eios));
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
+ LUT2 #(
+ .INIT(4'hE))
+ reg_symbol_after_eios_i_2__1
+ (.I0(\reg_state_eios_det[4]_i_3__1_n_0 ),
+ .I1(state_eios_det[4]),
+ .O(reg_symbol_after_eios_i_2__1_n_0));
+ FDRE reg_symbol_after_eios_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(reg_symbol_after_eios),
+ .Q(symbol_after_eios),
+ .R(SR));
+endmodule
+
+(* ORIG_REF_NAME = "pcie_7x_0_gt_rx_valid_filter_7x" *)
+module pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_36
+ (gt_rxvalid_q_reg_0,
+ gt_rx_phy_status_q_reg_0,
+ gt_rxelecidle_q_reg_0,
+ Q,
+ gt_rxvalid_q_reg_1,
+ \gt_rx_status_q_reg[2]_0 ,
+ SR,
+ pipe_pclk_in,
+ gt_rx_phy_status_wire_filter,
+ PIPE_RXELECIDLE,
+ gt_rxvalid_q_reg_2,
+ \gt_rx_status_q_reg[0]_0 ,
+ PIPE_RXSTATUS,
+ PIPE_RXDATAK,
+ PIPE_RXDATA);
+ output gt_rxvalid_q_reg_0;
+ output gt_rx_phy_status_q_reg_0;
+ output gt_rxelecidle_q_reg_0;
+ output [15:0]Q;
+ output [1:0]gt_rxvalid_q_reg_1;
+ output [2:0]\gt_rx_status_q_reg[2]_0 ;
+ input [0:0]SR;
+ input pipe_pclk_in;
+ input [0:0]gt_rx_phy_status_wire_filter;
+ input [0:0]PIPE_RXELECIDLE;
+ input gt_rxvalid_q_reg_2;
+ input \gt_rx_status_q_reg[0]_0 ;
+ input [2:0]PIPE_RXSTATUS;
+ input [1:0]PIPE_RXDATAK;
+ input [15:0]PIPE_RXDATA;
+
+ wire [15:0]PIPE_RXDATA;
+ wire [1:0]PIPE_RXDATAK;
+ wire [0:0]PIPE_RXELECIDLE;
+ wire [2:0]PIPE_RXSTATUS;
+ wire [15:0]Q;
+ wire [0:0]SR;
+ wire gt_rx_phy_status_q_reg_0;
+ wire [0:0]gt_rx_phy_status_wire_filter;
+ wire \gt_rx_status_q[0]_i_1_n_0 ;
+ wire \gt_rx_status_q[1]_i_1_n_0 ;
+ wire \gt_rx_status_q[2]_i_1_n_0 ;
+ wire \gt_rx_status_q_reg[0]_0 ;
+ wire [2:0]\gt_rx_status_q_reg[2]_0 ;
+ wire \gt_rxcharisk_q_reg_n_0_[0] ;
+ wire gt_rxelecidle_q_reg_0;
+ wire gt_rxvalid_q__0;
+ wire gt_rxvalid_q_i_2__2_n_0;
+ wire gt_rxvalid_q_n_0;
+ wire gt_rxvalid_q_reg_0;
+ wire [1:0]gt_rxvalid_q_reg_1;
+ wire gt_rxvalid_q_reg_2;
+ wire p_1_in;
+ wire [4:0]p_1_in__0;
+ wire pipe_pclk_in;
+ wire \reg_state_eios_det[0]_i_2__2_n_0 ;
+ wire \reg_state_eios_det[0]_i_3__2_n_0 ;
+ wire \reg_state_eios_det[0]_i_4__2_n_0 ;
+ wire \reg_state_eios_det[0]_i_5__2_n_0 ;
+ wire \reg_state_eios_det[1]_i_2__2_n_0 ;
+ wire \reg_state_eios_det[1]_i_3__2_n_0 ;
+ wire \reg_state_eios_det[2]_i_2__2_n_0 ;
+ wire \reg_state_eios_det[2]_i_3__2_n_0 ;
+ wire \reg_state_eios_det[3]_i_2__2_n_0 ;
+ wire \reg_state_eios_det[4]_i_1__2_n_0 ;
+ wire \reg_state_eios_det[4]_i_3__2_n_0 ;
+ wire reg_symbol_after_eios;
+ wire reg_symbol_after_eios_i_2__2_n_0;
+ wire [4:0]state_eios_det;
+ wire symbol_after_eios;
+
+ FDRE gt_rx_phy_status_q_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(gt_rx_phy_status_wire_filter),
+ .Q(gt_rx_phy_status_q_reg_0),
+ .R(SR));
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
+ LUT3 #(
+ .INIT(8'hE0))
+ \gt_rx_status_q[0]_i_1
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\gt_rx_status_q_reg[0]_0 ),
+ .I2(PIPE_RXSTATUS[0]),
+ .O(\gt_rx_status_q[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
+ LUT3 #(
+ .INIT(8'hE0))
+ \gt_rx_status_q[1]_i_1
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\gt_rx_status_q_reg[0]_0 ),
+ .I2(PIPE_RXSTATUS[1]),
+ .O(\gt_rx_status_q[1]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
+ LUT3 #(
+ .INIT(8'hE0))
+ \gt_rx_status_q[2]_i_1
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\gt_rx_status_q_reg[0]_0 ),
+ .I2(PIPE_RXSTATUS[2]),
+ .O(\gt_rx_status_q[2]_i_1_n_0 ));
+ FDRE \gt_rx_status_q_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\gt_rx_status_q[0]_i_1_n_0 ),
+ .Q(\gt_rx_status_q_reg[2]_0 [0]),
+ .R(SR));
+ FDRE \gt_rx_status_q_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\gt_rx_status_q[1]_i_1_n_0 ),
+ .Q(\gt_rx_status_q_reg[2]_0 [1]),
+ .R(SR));
+ FDRE \gt_rx_status_q_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(\gt_rx_status_q[2]_i_1_n_0 ),
+ .Q(\gt_rx_status_q_reg[2]_0 [2]),
+ .R(SR));
+ FDRE \gt_rxcharisk_q_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATAK[0]),
+ .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
+ .R(SR));
+ FDRE \gt_rxcharisk_q_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATAK[1]),
+ .Q(p_1_in),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[0]),
+ .Q(Q[0]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[10]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[10]),
+ .Q(Q[10]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[11]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[11]),
+ .Q(Q[11]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[12]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[12]),
+ .Q(Q[12]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[13]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[13]),
+ .Q(Q[13]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[14]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[14]),
+ .Q(Q[14]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[15]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[15]),
+ .Q(Q[15]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[1]),
+ .Q(Q[1]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[2]),
+ .Q(Q[2]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[3]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[3]),
+ .Q(Q[3]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[4]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[4]),
+ .Q(Q[4]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[5]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[5]),
+ .Q(Q[5]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[6]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[6]),
+ .Q(Q[6]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[7]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[7]),
+ .Q(Q[7]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[8]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[8]),
+ .Q(Q[8]),
+ .R(SR));
+ FDRE \gt_rxdata_q_reg[9]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXDATA[9]),
+ .Q(Q[9]),
+ .R(SR));
+ FDRE gt_rxelecidle_q_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(PIPE_RXELECIDLE),
+ .Q(gt_rxelecidle_q_reg_0),
+ .R(SR));
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
+ LUT5 #(
+ .INIT(32'h00010116))
+ gt_rxvalid_q
+ (.I0(state_eios_det[0]),
+ .I1(state_eios_det[1]),
+ .I2(state_eios_det[2]),
+ .I3(state_eios_det[3]),
+ .I4(state_eios_det[4]),
+ .O(gt_rxvalid_q_n_0));
+ LUT5 #(
+ .INIT(32'hFFAAEAAA))
+ gt_rxvalid_q_i_1__2
+ (.I0(gt_rxvalid_q_i_2__2_n_0),
+ .I1(state_eios_det[2]),
+ .I2(\reg_state_eios_det[3]_i_2__2_n_0 ),
+ .I3(gt_rxvalid_q_reg_2),
+ .I4(state_eios_det[0]),
+ .O(gt_rxvalid_q__0));
+ LUT6 #(
+ .INIT(64'hFFF50000CC550000))
+ gt_rxvalid_q_i_2__2
+ (.I0(gt_rxvalid_q_n_0),
+ .I1(\gt_rx_status_q_reg[0]_0 ),
+ .I2(\reg_state_eios_det[4]_i_3__2_n_0 ),
+ .I3(state_eios_det[4]),
+ .I4(gt_rxvalid_q_reg_2),
+ .I5(\reg_state_eios_det[0]_i_3__2_n_0 ),
+ .O(gt_rxvalid_q_i_2__2_n_0));
+ FDRE gt_rxvalid_q_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(gt_rxvalid_q__0),
+ .Q(gt_rxvalid_q_reg_0),
+ .R(SR));
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__2
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
+ .O(gt_rxvalid_q_reg_1[0]));
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
+ LUT3 #(
+ .INIT(8'h08))
+ \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__2
+ (.I0(gt_rxvalid_q_reg_0),
+ .I1(p_1_in),
+ .I2(symbol_after_eios),
+ .O(gt_rxvalid_q_reg_1[1]));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFEFEFEEE))
+ \reg_state_eios_det[0]_i_1__2
+ (.I0(state_eios_det[4]),
+ .I1(\reg_state_eios_det[0]_i_2__2_n_0 ),
+ .I2(\reg_state_eios_det[1]_i_2__2_n_0 ),
+ .I3(\reg_state_eios_det[0]_i_3__2_n_0 ),
+ .I4(\reg_state_eios_det[0]_i_4__2_n_0 ),
+ .I5(\reg_state_eios_det[0]_i_5__2_n_0 ),
+ .O(p_1_in__0[0]));
+ LUT6 #(
+ .INIT(64'hFFAA8A8AFF00FFAA))
+ \reg_state_eios_det[0]_i_2__2
+ (.I0(state_eios_det[0]),
+ .I1(Q[6]),
+ .I2(Q[7]),
+ .I3(state_eios_det[2]),
+ .I4(Q[15]),
+ .I5(Q[14]),
+ .O(\reg_state_eios_det[0]_i_2__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
+ LUT3 #(
+ .INIT(8'hFE))
+ \reg_state_eios_det[0]_i_3__2
+ (.I0(state_eios_det[3]),
+ .I1(state_eios_det[1]),
+ .I2(state_eios_det[2]),
+ .O(\reg_state_eios_det[0]_i_3__2_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \reg_state_eios_det[0]_i_4__2
+ (.I0(state_eios_det[0]),
+ .I1(Q[15]),
+ .O(\reg_state_eios_det[0]_i_4__2_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFE0E0E0FFE0FFE0))
+ \reg_state_eios_det[0]_i_5__2
+ (.I0(state_eios_det[0]),
+ .I1(state_eios_det[2]),
+ .I2(\reg_state_eios_det[2]_i_2__2_n_0 ),
+ .I3(\reg_state_eios_det[0]_i_3__2_n_0 ),
+ .I4(Q[7]),
+ .I5(Q[6]),
+ .O(\reg_state_eios_det[0]_i_5__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
+ LUT5 #(
+ .INIT(32'h00000040))
+ \reg_state_eios_det[1]_i_1__2
+ (.I0(\reg_state_eios_det[1]_i_2__2_n_0 ),
+ .I1(state_eios_det[0]),
+ .I2(Q[7]),
+ .I3(Q[6]),
+ .I4(\reg_state_eios_det[3]_i_2__2_n_0 ),
+ .O(p_1_in__0[1]));
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
+ LUT4 #(
+ .INIT(16'hBFFF))
+ \reg_state_eios_det[1]_i_2__2
+ (.I0(\reg_state_eios_det[1]_i_3__2_n_0 ),
+ .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
+ .I2(Q[4]),
+ .I3(Q[5]),
+ .O(\reg_state_eios_det[1]_i_2__2_n_0 ));
+ LUT4 #(
+ .INIT(16'hEFFF))
+ \reg_state_eios_det[1]_i_3__2
+ (.I0(Q[1]),
+ .I1(Q[0]),
+ .I2(Q[3]),
+ .I3(Q[2]),
+ .O(\reg_state_eios_det[1]_i_3__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
+ LUT4 #(
+ .INIT(16'h0040))
+ \reg_state_eios_det[2]_i_1__2
+ (.I0(Q[14]),
+ .I1(Q[15]),
+ .I2(state_eios_det[0]),
+ .I3(\reg_state_eios_det[2]_i_2__2_n_0 ),
+ .O(p_1_in__0[2]));
+ LUT4 #(
+ .INIT(16'hBFFF))
+ \reg_state_eios_det[2]_i_2__2
+ (.I0(\reg_state_eios_det[2]_i_3__2_n_0 ),
+ .I1(p_1_in),
+ .I2(Q[12]),
+ .I3(Q[13]),
+ .O(\reg_state_eios_det[2]_i_2__2_n_0 ));
+ LUT4 #(
+ .INIT(16'hEFFF))
+ \reg_state_eios_det[2]_i_3__2
+ (.I0(Q[9]),
+ .I1(Q[8]),
+ .I2(Q[11]),
+ .I3(Q[10]),
+ .O(\reg_state_eios_det[2]_i_3__2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
+ LUT3 #(
+ .INIT(8'h04))
+ \reg_state_eios_det[3]_i_1__2
+ (.I0(\reg_state_eios_det[3]_i_2__2_n_0 ),
+ .I1(state_eios_det[2]),
+ .I2(\reg_state_eios_det[4]_i_3__2_n_0 ),
+ .O(p_1_in__0[3]));
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
+ LUT3 #(
+ .INIT(8'hFD))
+ \reg_state_eios_det[3]_i_2__2
+ (.I0(Q[14]),
+ .I1(Q[15]),
+ .I2(\reg_state_eios_det[2]_i_2__2_n_0 ),
+ .O(\reg_state_eios_det[3]_i_2__2_n_0 ));
+ LUT5 #(
+ .INIT(32'h00010116))
+ \reg_state_eios_det[4]_i_1__2
+ (.I0(state_eios_det[0]),
+ .I1(state_eios_det[4]),
+ .I2(state_eios_det[2]),
+ .I3(state_eios_det[1]),
+ .I4(state_eios_det[3]),
+ .O(\reg_state_eios_det[4]_i_1__2_n_0 ));
+ LUT3 #(
+ .INIT(8'h0E))
+ \reg_state_eios_det[4]_i_2__2
+ (.I0(state_eios_det[3]),
+ .I1(state_eios_det[1]),
+ .I2(\reg_state_eios_det[4]_i_3__2_n_0 ),
+ .O(p_1_in__0[4]));
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
+ LUT3 #(
+ .INIT(8'hFD))
+ \reg_state_eios_det[4]_i_3__2
+ (.I0(Q[6]),
+ .I1(Q[7]),
+ .I2(\reg_state_eios_det[1]_i_2__2_n_0 ),
+ .O(\reg_state_eios_det[4]_i_3__2_n_0 ));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDSE \reg_state_eios_det_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__2_n_0 ),
+ .D(p_1_in__0[0]),
+ .Q(state_eios_det[0]),
+ .S(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__2_n_0 ),
+ .D(p_1_in__0[1]),
+ .Q(state_eios_det[1]),
+ .R(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__2_n_0 ),
+ .D(p_1_in__0[2]),
+ .Q(state_eios_det[2]),
+ .R(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[3]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__2_n_0 ),
+ .D(p_1_in__0[3]),
+ .Q(state_eios_det[3]),
+ .R(SR));
+ (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *)
+ FDRE \reg_state_eios_det_reg[4]
+ (.C(pipe_pclk_in),
+ .CE(\reg_state_eios_det[4]_i_1__2_n_0 ),
+ .D(p_1_in__0[4]),
+ .Q(state_eios_det[4]),
+ .R(SR));
+ LUT6 #(
+ .INIT(64'h0000000000000010))
+ reg_symbol_after_eios_i_1__2
+ (.I0(\reg_state_eios_det[3]_i_2__2_n_0 ),
+ .I1(state_eios_det[0]),
+ .I2(state_eios_det[2]),
+ .I3(state_eios_det[3]),
+ .I4(state_eios_det[1]),
+ .I5(reg_symbol_after_eios_i_2__2_n_0),
+ .O(reg_symbol_after_eios));
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
+ LUT2 #(
+ .INIT(4'hE))
+ reg_symbol_after_eios_i_2__2
+ (.I0(\reg_state_eios_det[4]_i_3__2_n_0 ),
+ .I1(state_eios_det[4]),
+ .O(reg_symbol_after_eios_i_2__2_n_0));
+ FDRE reg_symbol_after_eios_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(reg_symbol_after_eios),
+ .Q(symbol_after_eios),
+ .R(SR));
+endmodule
+
+module pcie_7x_0_pcie_7x_0_gt_top
+ (pipe_rx0_valid_gt,
+ phy_rdy_n,
+ pipe_rx1_valid_gt,
+ pipe_rx2_valid_gt,
+ pipe_rx3_valid_gt,
+ gt_rx_phy_status_q_reg,
+ gt_rxelecidle_q_reg,
+ gt_rx_phy_status_q_reg_0,
+ gt_rxelecidle_q_reg_0,
+ gt_rx_phy_status_q_reg_1,
+ gt_rxelecidle_q_reg_1,
+ gt_rx_phy_status_q,
+ gt_rxelecidle_q,
+ sys_rst_n,
+ Q,
+ \gt_rxdata_q_reg[15] ,
+ \gt_rxdata_q_reg[15]_0 ,
+ \gt_rxdata_q_reg[15]_1 ,
+ \gt_rx_status_q_reg[2] ,
+ \gt_rx_status_q_reg[2]_0 ,
+ \gt_rx_status_q_reg[2]_1 ,
+ \gt_rx_status_q_reg[2]_2 ,
+ D,
+ gt_rxvalid_q_reg,
+ gt_rxvalid_q_reg_0,
+ gt_rxvalid_q_reg_1,
+ pipe_pclk_sel_out,
+ USER_RATE_GEN3,
+ pci_exp_txn,
+ pci_exp_txp,
+ PIPE_RXCHANISALIGNED,
+ pipe_rxoutclk_out,
+ pipe_txoutclk_out,
+ sys_rst_n_0,
+ pipe_pclk_in,
+ pipe_mmcm_lock_in,
+ pl_ltssm_state,
+ pipe_rxusrclk_in,
+ pipe_dclk_in,
+ \rate_reg1_reg[0] ,
+ sys_clk,
+ pipe_oobclk_in,
+ PIPE_TXELECIDLE,
+ PIPE_TXCOMPLIANCE,
+ pci_exp_rxn,
+ pci_exp_rxp,
+ PIPE_RXPOLARITY,
+ pipe_tx_deemph_gt,
+ pipe_tx_rcvr_det_gt,
+ PIPE_POWERDOWN,
+ \cplllock_reg1_reg[3] ,
+ PIPE_TXDATA,
+ PIPE_TXDATAK,
+ reset_n_reg1_reg);
+ output pipe_rx0_valid_gt;
+ output phy_rdy_n;
+ output pipe_rx1_valid_gt;
+ output pipe_rx2_valid_gt;
+ output pipe_rx3_valid_gt;
+ output gt_rx_phy_status_q_reg;
+ output gt_rxelecidle_q_reg;
+ output gt_rx_phy_status_q_reg_0;
+ output gt_rxelecidle_q_reg_0;
+ output gt_rx_phy_status_q_reg_1;
+ output gt_rxelecidle_q_reg_1;
+ output gt_rx_phy_status_q;
+ output gt_rxelecidle_q;
+ output sys_rst_n;
+ output [15:0]Q;
+ output [15:0]\gt_rxdata_q_reg[15] ;
+ output [15:0]\gt_rxdata_q_reg[15]_0 ;
+ output [15:0]\gt_rxdata_q_reg[15]_1 ;
+ output [2:0]\gt_rx_status_q_reg[2] ;
+ output [2:0]\gt_rx_status_q_reg[2]_0 ;
+ output [2:0]\gt_rx_status_q_reg[2]_1 ;
+ output [2:0]\gt_rx_status_q_reg[2]_2 ;
+ output [1:0]D;
+ output [1:0]gt_rxvalid_q_reg;
+ output [1:0]gt_rxvalid_q_reg_0;
+ output [1:0]gt_rxvalid_q_reg_1;
+ output [3:0]pipe_pclk_sel_out;
+ output USER_RATE_GEN3;
+ output [3:0]pci_exp_txn;
+ output [3:0]pci_exp_txp;
+ output [3:0]PIPE_RXCHANISALIGNED;
+ output [3:0]pipe_rxoutclk_out;
+ output pipe_txoutclk_out;
+ output sys_rst_n_0;
+ input pipe_pclk_in;
+ input pipe_mmcm_lock_in;
+ input [5:0]pl_ltssm_state;
+ input pipe_rxusrclk_in;
+ input pipe_dclk_in;
+ input [0:0]\rate_reg1_reg[0] ;
+ input sys_clk;
+ input pipe_oobclk_in;
+ input [3:0]PIPE_TXELECIDLE;
+ input [3:0]PIPE_TXCOMPLIANCE;
+ input [3:0]pci_exp_rxn;
+ input [3:0]pci_exp_rxp;
+ input [3:0]PIPE_RXPOLARITY;
+ input pipe_tx_deemph_gt;
+ input pipe_tx_rcvr_det_gt;
+ input [7:0]PIPE_POWERDOWN;
+ input [2:0]\cplllock_reg1_reg[3] ;
+ input [63:0]PIPE_TXDATA;
+ input [7:0]PIPE_TXDATAK;
+ input reset_n_reg1_reg;
+
+ wire [1:0]D;
+ wire [7:0]PIPE_POWERDOWN;
+ wire [3:0]PIPE_RXCHANISALIGNED;
+ wire [3:0]PIPE_RXPOLARITY;
+ wire [3:0]PIPE_TXCOMPLIANCE;
+ wire [63:0]PIPE_TXDATA;
+ wire [7:0]PIPE_TXDATAK;
+ wire [3:0]PIPE_TXELECIDLE;
+ wire [15:0]Q;
+ wire USER_RATE_GEN3;
+ wire [2:0]\cplllock_reg1_reg[3] ;
+ wire [13:0]gt_rx_data_k_wire_filter;
+ wire [111:0]gt_rx_data_wire_filter;
+ wire [3:0]gt_rx_elec_idle_wire_filter;
+ wire gt_rx_phy_status_q;
+ wire gt_rx_phy_status_q_reg;
+ wire gt_rx_phy_status_q_reg_0;
+ wire gt_rx_phy_status_q_reg_1;
+ wire [3:0]gt_rx_phy_status_wire_filter;
+ wire [2:0]\gt_rx_status_q_reg[2] ;
+ wire [2:0]\gt_rx_status_q_reg[2]_0 ;
+ wire [2:0]\gt_rx_status_q_reg[2]_1 ;
+ wire [2:0]\gt_rx_status_q_reg[2]_2 ;
+ wire \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ;
+ wire [15:0]\gt_rxdata_q_reg[15] ;
+ wire [15:0]\gt_rxdata_q_reg[15]_0 ;
+ wire [15:0]\gt_rxdata_q_reg[15]_1 ;
+ wire gt_rxelecidle_q;
+ wire gt_rxelecidle_q_reg;
+ wire gt_rxelecidle_q_reg_0;
+ wire gt_rxelecidle_q_reg_1;
+ wire [1:0]gt_rxvalid_q_reg;
+ wire [1:0]gt_rxvalid_q_reg_0;
+ wire [1:0]gt_rxvalid_q_reg_1;
+ wire [3:0]pci_exp_rxn;
+ wire [3:0]pci_exp_rxp;
+ wire [3:0]pci_exp_txn;
+ wire [3:0]pci_exp_txp;
+ wire phy_rdy_n;
+ wire pipe_dclk_in;
+ wire \pipe_lane[0].gt_wrapper_i/CPLLPD0 ;
+ wire \pipe_lane[0].gt_wrapper_i/cpllpd ;
+ wire \pipe_lane[1].gt_wrapper_i/CPLLPD0 ;
+ wire \pipe_lane[1].gt_wrapper_i/cpllpd ;
+ wire \pipe_lane[2].gt_wrapper_i/CPLLPD0 ;
+ wire \pipe_lane[2].gt_wrapper_i/cpllpd ;
+ wire \pipe_lane[3].gt_wrapper_i/CPLLPD0 ;
+ wire \pipe_lane[3].gt_wrapper_i/cpllpd ;
+ wire pipe_mmcm_lock_in;
+ wire pipe_oobclk_in;
+ wire pipe_pclk_in;
+ wire [3:0]pipe_pclk_sel_out;
+ wire pipe_rx0_valid_gt;
+ wire pipe_rx1_valid_gt;
+ wire pipe_rx2_valid_gt;
+ wire pipe_rx3_valid_gt;
+ wire [3:0]pipe_rxoutclk_out;
+ wire pipe_rxusrclk_in;
+ wire pipe_tx_deemph_gt;
+ wire pipe_tx_rcvr_det_gt;
+ wire pipe_txoutclk_out;
+ wire pipe_wrapper_i_n_100;
+ wire pipe_wrapper_i_n_101;
+ wire pipe_wrapper_i_n_102;
+ wire pipe_wrapper_i_n_103;
+ wire pipe_wrapper_i_n_104;
+ wire pipe_wrapper_i_n_105;
+ wire pipe_wrapper_i_n_106;
+ wire pipe_wrapper_i_n_107;
+ wire pipe_wrapper_i_n_108;
+ wire pipe_wrapper_i_n_109;
+ wire pipe_wrapper_i_n_110;
+ wire pipe_wrapper_i_n_111;
+ wire pipe_wrapper_i_n_112;
+ wire pipe_wrapper_i_n_113;
+ wire pipe_wrapper_i_n_25;
+ wire pipe_wrapper_i_n_26;
+ wire pipe_wrapper_i_n_27;
+ wire [5:0]pl_ltssm_state;
+ wire [5:0]pl_ltssm_state_q;
+ wire rate_cpllpd_0;
+ wire rate_cpllpd_1;
+ wire rate_cpllpd_2;
+ wire rate_cpllpd_3;
+ wire [0:0]\rate_reg1_reg[0] ;
+ wire reg_clock_locked;
+ wire reg_clock_locked_i_1_n_0;
+ wire reset_n_reg1_reg;
+ wire sys_clk;
+ wire sys_rst_n;
+ wire sys_rst_n_0;
+
+ pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst
+ (.D(D),
+ .PIPE_RXDATA(gt_rx_data_wire_filter[15:0]),
+ .PIPE_RXDATAK(gt_rx_data_k_wire_filter[1:0]),
+ .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[0]),
+ .PIPE_RXSTATUS({pipe_wrapper_i_n_25,pipe_wrapper_i_n_26,pipe_wrapper_i_n_27}),
+ .Q(Q),
+ .SR(phy_rdy_n),
+ .gt_rx_phy_status_q(gt_rx_phy_status_q),
+ .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[0]),
+ .\gt_rx_status_q_reg[0]_0 (pl_ltssm_state_q),
+ .\gt_rx_status_q_reg[2]_0 (\gt_rx_status_q_reg[2]_2 ),
+ .gt_rxelecidle_q(gt_rxelecidle_q),
+ .gt_rxvalid_q_reg_0(pipe_rx0_valid_gt),
+ .gt_rxvalid_q_reg_1(pipe_wrapper_i_n_110),
+ .pipe_pclk_in(pipe_pclk_in),
+ .\pl_ltssm_state_q_reg[5] (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ));
+ pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_34 \gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst
+ (.PIPE_RXDATA(gt_rx_data_wire_filter[47:32]),
+ .PIPE_RXDATAK(gt_rx_data_k_wire_filter[5:4]),
+ .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[1]),
+ .PIPE_RXSTATUS({pipe_wrapper_i_n_100,pipe_wrapper_i_n_101,pipe_wrapper_i_n_102}),
+ .Q(\gt_rxdata_q_reg[15] ),
+ .SR(phy_rdy_n),
+ .gt_rx_phy_status_q_reg_0(gt_rx_phy_status_q_reg),
+ .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[1]),
+ .\gt_rx_status_q_reg[0]_0 (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ),
+ .\gt_rx_status_q_reg[2]_0 (\gt_rx_status_q_reg[2] ),
+ .gt_rxelecidle_q_reg_0(gt_rxelecidle_q_reg),
+ .gt_rxvalid_q_reg_0(pipe_rx1_valid_gt),
+ .gt_rxvalid_q_reg_1(gt_rxvalid_q_reg),
+ .gt_rxvalid_q_reg_2(pipe_wrapper_i_n_111),
+ .pipe_pclk_in(pipe_pclk_in));
+ pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_35 \gt_rx_valid_filter[2].GT_RX_VALID_FILTER_7x_inst
+ (.PIPE_RXDATA(gt_rx_data_wire_filter[79:64]),
+ .PIPE_RXDATAK(gt_rx_data_k_wire_filter[9:8]),
+ .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[2]),
+ .PIPE_RXSTATUS({pipe_wrapper_i_n_103,pipe_wrapper_i_n_104,pipe_wrapper_i_n_105}),
+ .Q(\gt_rxdata_q_reg[15]_0 ),
+ .SR(phy_rdy_n),
+ .gt_rx_phy_status_q_reg_0(gt_rx_phy_status_q_reg_0),
+ .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[2]),
+ .\gt_rx_status_q_reg[0]_0 (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ),
+ .\gt_rx_status_q_reg[2]_0 (\gt_rx_status_q_reg[2]_0 ),
+ .gt_rxelecidle_q_reg_0(gt_rxelecidle_q_reg_0),
+ .gt_rxvalid_q_reg_0(pipe_rx2_valid_gt),
+ .gt_rxvalid_q_reg_1(gt_rxvalid_q_reg_0),
+ .gt_rxvalid_q_reg_2(pipe_wrapper_i_n_112),
+ .pipe_pclk_in(pipe_pclk_in));
+ pcie_7x_0_pcie_7x_0_gt_rx_valid_filter_7x_36 \gt_rx_valid_filter[3].GT_RX_VALID_FILTER_7x_inst
+ (.PIPE_RXDATA(gt_rx_data_wire_filter[111:96]),
+ .PIPE_RXDATAK(gt_rx_data_k_wire_filter[13:12]),
+ .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[3]),
+ .PIPE_RXSTATUS({pipe_wrapper_i_n_106,pipe_wrapper_i_n_107,pipe_wrapper_i_n_108}),
+ .Q(\gt_rxdata_q_reg[15]_1 ),
+ .SR(phy_rdy_n),
+ .gt_rx_phy_status_q_reg_0(gt_rx_phy_status_q_reg_1),
+ .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[3]),
+ .\gt_rx_status_q_reg[0]_0 (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ),
+ .\gt_rx_status_q_reg[2]_0 (\gt_rx_status_q_reg[2]_1 ),
+ .gt_rxelecidle_q_reg_0(gt_rxelecidle_q_reg_1),
+ .gt_rxvalid_q_reg_0(pipe_rx3_valid_gt),
+ .gt_rxvalid_q_reg_1(gt_rxvalid_q_reg_1),
+ .gt_rxvalid_q_reg_2(pipe_wrapper_i_n_113),
+ .pipe_pclk_in(pipe_pclk_in));
+ LUT2 #(
+ .INIT(4'hE))
+ \gtx_channel.gtxe2_channel_i_i_1
+ (.I0(\pipe_lane[0].gt_wrapper_i/cpllpd ),
+ .I1(rate_cpllpd_0),
+ .O(\pipe_lane[0].gt_wrapper_i/CPLLPD0 ));
+ LUT2 #(
+ .INIT(4'hE))
+ \gtx_channel.gtxe2_channel_i_i_1__0
+ (.I0(\pipe_lane[1].gt_wrapper_i/cpllpd ),
+ .I1(rate_cpllpd_1),
+ .O(\pipe_lane[1].gt_wrapper_i/CPLLPD0 ));
+ LUT2 #(
+ .INIT(4'hE))
+ \gtx_channel.gtxe2_channel_i_i_1__1
+ (.I0(\pipe_lane[2].gt_wrapper_i/cpllpd ),
+ .I1(rate_cpllpd_2),
+ .O(\pipe_lane[2].gt_wrapper_i/CPLLPD0 ));
+ LUT2 #(
+ .INIT(4'hE))
+ \gtx_channel.gtxe2_channel_i_i_1__2
+ (.I0(\pipe_lane[3].gt_wrapper_i/cpllpd ),
+ .I1(rate_cpllpd_3),
+ .O(\pipe_lane[3].gt_wrapper_i/CPLLPD0 ));
+ LUT1 #(
+ .INIT(2'h1))
+ pcie_block_i_i_29
+ (.I0(phy_rdy_n),
+ .O(sys_rst_n));
+ FDRE phy_rdy_n_int_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .D(pipe_wrapper_i_n_109),
+ .Q(phy_rdy_n),
+ .R(1'b0));
+ pcie_7x_0_pcie_7x_0_pipe_wrapper pipe_wrapper_i
+ (.CPLLPD0(\pipe_lane[0].gt_wrapper_i/CPLLPD0 ),
+ .CPLLPD0_3(\pipe_lane[1].gt_wrapper_i/CPLLPD0 ),
+ .CPLLPD0_4(\pipe_lane[2].gt_wrapper_i/CPLLPD0 ),
+ .CPLLPD0_5(\pipe_lane[3].gt_wrapper_i/CPLLPD0 ),
+ .PIPE_POWERDOWN(PIPE_POWERDOWN),
+ .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
+ .PIPE_RXPOLARITY(PIPE_RXPOLARITY),
+ .PIPE_RXSTATUS({pipe_wrapper_i_n_25,pipe_wrapper_i_n_26,pipe_wrapper_i_n_27}),
+ .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE),
+ .PIPE_TXDATA(PIPE_TXDATA),
+ .PIPE_TXDATAK(PIPE_TXDATAK),
+ .PIPE_TXELECIDLE(PIPE_TXELECIDLE),
+ .\cplllock_reg1_reg[3] (\cplllock_reg1_reg[3] ),
+ .cpllpd(\pipe_lane[0].gt_wrapper_i/cpllpd ),
+ .cpllpd_0(\pipe_lane[1].gt_wrapper_i/cpllpd ),
+ .cpllpd_1(\pipe_lane[2].gt_wrapper_i/cpllpd ),
+ .cpllpd_2(\pipe_lane[3].gt_wrapper_i/cpllpd ),
+ .gen3_reg(USER_RATE_GEN3),
+ .gt_rx_data_k_wire_filter({gt_rx_data_k_wire_filter[13:12],gt_rx_data_k_wire_filter[9:8],gt_rx_data_k_wire_filter[5:4],gt_rx_data_k_wire_filter[1:0]}),
+ .gt_rx_data_wire_filter({gt_rx_data_wire_filter[111:96],gt_rx_data_wire_filter[79:64],gt_rx_data_wire_filter[47:32],gt_rx_data_wire_filter[15:0]}),
+ .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter),
+ .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter),
+ .gt_rxvalid_q_reg(pipe_wrapper_i_n_110),
+ .gt_rxvalid_q_reg_0(pipe_wrapper_i_n_111),
+ .gt_rxvalid_q_reg_1(pipe_wrapper_i_n_112),
+ .gt_rxvalid_q_reg_2(pipe_wrapper_i_n_113),
+ .pci_exp_rxn(pci_exp_rxn),
+ .pci_exp_rxp(pci_exp_rxp),
+ .pci_exp_txn(pci_exp_txn),
+ .pci_exp_txp(pci_exp_txp),
+ .pipe_dclk_in(pipe_dclk_in),
+ .pipe_dclk_in_0({pipe_wrapper_i_n_100,pipe_wrapper_i_n_101,pipe_wrapper_i_n_102}),
+ .pipe_dclk_in_1({pipe_wrapper_i_n_103,pipe_wrapper_i_n_104,pipe_wrapper_i_n_105}),
+ .pipe_dclk_in_2({pipe_wrapper_i_n_106,pipe_wrapper_i_n_107,pipe_wrapper_i_n_108}),
+ .pipe_mmcm_lock_in(pipe_mmcm_lock_in),
+ .pipe_oobclk_in(pipe_oobclk_in),
+ .pipe_pclk_in(pipe_pclk_in),
+ .pipe_pclk_sel_out(pipe_pclk_sel_out),
+ .pipe_rx0_valid_gt(pipe_rx0_valid_gt),
+ .pipe_rx1_valid_gt(pipe_rx1_valid_gt),
+ .pipe_rx2_valid_gt(pipe_rx2_valid_gt),
+ .pipe_rx3_valid_gt(pipe_rx3_valid_gt),
+ .pipe_rxoutclk_out(pipe_rxoutclk_out),
+ .pipe_rxusrclk_in(pipe_rxusrclk_in),
+ .pipe_tx_deemph_gt(pipe_tx_deemph_gt),
+ .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt),
+ .pipe_txoutclk_out(pipe_txoutclk_out),
+ .rate_cpllpd_0(rate_cpllpd_0),
+ .rate_cpllpd_1(rate_cpllpd_1),
+ .rate_cpllpd_2(rate_cpllpd_2),
+ .rate_cpllpd_3(rate_cpllpd_3),
+ .\rate_reg1_reg[0] (\rate_reg1_reg[0] ),
+ .reg_clock_locked(reg_clock_locked),
+ .reg_clock_locked_reg(pipe_wrapper_i_n_109),
+ .reset_n_reg1_reg_0(sys_rst_n_0),
+ .sys_clk(sys_clk));
+ FDCE \pl_ltssm_state_q_reg[0]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .CLR(reg_clock_locked_i_1_n_0),
+ .D(pl_ltssm_state[0]),
+ .Q(pl_ltssm_state_q[0]));
+ FDCE \pl_ltssm_state_q_reg[1]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .CLR(reg_clock_locked_i_1_n_0),
+ .D(pl_ltssm_state[1]),
+ .Q(pl_ltssm_state_q[1]));
+ FDCE \pl_ltssm_state_q_reg[2]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .CLR(reg_clock_locked_i_1_n_0),
+ .D(pl_ltssm_state[2]),
+ .Q(pl_ltssm_state_q[2]));
+ FDCE \pl_ltssm_state_q_reg[3]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .CLR(reg_clock_locked_i_1_n_0),
+ .D(pl_ltssm_state[3]),
+ .Q(pl_ltssm_state_q[3]));
+ FDCE \pl_ltssm_state_q_reg[4]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .CLR(reg_clock_locked_i_1_n_0),
+ .D(pl_ltssm_state[4]),
+ .Q(pl_ltssm_state_q[4]));
+ FDCE \pl_ltssm_state_q_reg[5]
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .CLR(reg_clock_locked_i_1_n_0),
+ .D(pl_ltssm_state[5]),
+ .Q(pl_ltssm_state_q[5]));
+ LUT1 #(
+ .INIT(2'h1))
+ pl_phy_lnk_up_q_i_1
+ (.I0(reset_n_reg1_reg),
+ .O(sys_rst_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ reg_clock_locked_i_1
+ (.I0(pipe_mmcm_lock_in),
+ .O(reg_clock_locked_i_1_n_0));
+ FDCE reg_clock_locked_reg
+ (.C(pipe_pclk_in),
+ .CE(1'b1),
+ .CLR(reg_clock_locked_i_1_n_0),
+ .D(1'b1),
+ .Q(reg_clock_locked));
+endmodule
+
+module pcie_7x_0_pcie_7x_0_gt_wrapper
+ (cpllpd,
+ QRST_CPLLLOCK,
+ DRP_RDY,
+ pci_exp_txn,
+ pci_exp_txp,
+ RATE_PHYSTATUS,
+ gt_rxcdrlock_0,
+ PIPE_RXCHANISALIGNED,
+ pipe_dclk_in_0,
+ gt_rx_elec_idle_wire_filter,
+ pipe_rxoutclk_out,
+ SYNC_RXPHALIGNDONE_M,
+ RATE_RXRATEDONE,
+ USER_RXRESETDONE,
+ gt_rxvalid_0,
+ pipe_dclk_in_1,
+ pipe_txoutclk_out,
+ pipe_dclk_in_2,
+ pipe_dclk_in_3,
+ RATE_TXRATEDONE,
+ USER_TXRESETDONE,
+ DRP_DO,
+ PIPE_RXSTATUS,
+ RXCHBONDO,
+ gt_rx_data_wire_filter,
+ gt_rx_data_k_wire_filter,
+ gt_cpllpdrefclk,
+ CPLLPD0,
+ pipe_dclk_in,
+ \cplllock_reg1_reg[0] ,
+ \cplllock_reg1_reg[0]_0 ,
+ sys_clk,
+ DRP_GTXRESET,
+ pci_exp_rxn,
+ pci_exp_rxp,
+ QPLL_QPLLOUTCLK,
+ QPLL_QPLLOUTREFCLK,
+ rxchbonden_0,
+ \cplllock_reg1_reg[0]_1 ,
+ rate_txpmareset_0,
+ PIPE_RXPOLARITY,
+ rst_userrdy,
+ pipe_rxusrclk_in,
+ pipe_tx_deemph_gt,
+ pipe_tx_rcvr_det_gt,
+ sync_txdlyen_0,
+ SYNC_TXDLYSRESET,
+ PIPE_TXELECIDLE,
+ SYNC_TXPHALIGN,
+ SYNC_TXPHINIT,
+ pipe_pclk_in,
+ DRPDI,
+ PIPE_POWERDOWN,
+ RXSYSCLKSEL,
+ RXRATE,
+ \cplllock_reg1_reg[0]_2 ,
+ USER_OOBCLK,
+ TXPOSTCURSOR,
+ TXPRECURSOR,
+ PIPE_TXDATA,
+ TXMAINCURSOR,
+ PIPE_TXCOMPLIANCE,
+ PIPE_TXDATAK,
+ DRPADDR,
+ rate_cpllreset_0,
+ RST_CPLLRESET);
+ output cpllpd;
+ output [0:0]QRST_CPLLLOCK;
+ output DRP_RDY;
+ output [0:0]pci_exp_txn;
+ output [0:0]pci_exp_txp;
+ output RATE_PHYSTATUS;
+ output gt_rxcdrlock_0;
+ output [0:0]PIPE_RXCHANISALIGNED;
+ output pipe_dclk_in_0;
+ output [0:0]gt_rx_elec_idle_wire_filter;
+ output [0:0]pipe_rxoutclk_out;
+ output SYNC_RXPHALIGNDONE_M;
+ output RATE_RXRATEDONE;
+ output USER_RXRESETDONE;
+ output gt_rxvalid_0;
+ output pipe_dclk_in_1;
+ output pipe_txoutclk_out;
+ output pipe_dclk_in_2;
+ output pipe_dclk_in_3;
+ output RATE_TXRATEDONE;
+ output USER_TXRESETDONE;
+ output [15:0]DRP_DO;
+ output [2:0]PIPE_RXSTATUS;
+ output [4:0]RXCHBONDO;
+ output [15:0]gt_rx_data_wire_filter;
+ output [1:0]gt_rx_data_k_wire_filter;
+ input gt_cpllpdrefclk;
+ input CPLLPD0;
+ input pipe_dclk_in;
+ input \cplllock_reg1_reg[0] ;
+ input \cplllock_reg1_reg[0]_0 ;
+ input sys_clk;
+ input DRP_GTXRESET;
+ input [0:0]pci_exp_rxn;
+ input [0:0]pci_exp_rxp;
+ input QPLL_QPLLOUTCLK;
+ input QPLL_QPLLOUTREFCLK;
+ input rxchbonden_0;
+ input \cplllock_reg1_reg[0]_1 ;
+ input rate_txpmareset_0;
+ input [0:0]PIPE_RXPOLARITY;
+ input rst_userrdy;
+ input pipe_rxusrclk_in;
+ input pipe_tx_deemph_gt;
+ input pipe_tx_rcvr_det_gt;
+ input sync_txdlyen_0;
+ input SYNC_TXDLYSRESET;
+ input [0:0]PIPE_TXELECIDLE;
+ input SYNC_TXPHALIGN;
+ input SYNC_TXPHINIT;
+ input pipe_pclk_in;
+ input [15:0]DRPDI;
+ input [1:0]PIPE_POWERDOWN;
+ input [0:0]RXSYSCLKSEL;
+ input [0:0]RXRATE;
+ input [2:0]\cplllock_reg1_reg[0]_2 ;
+ input USER_OOBCLK;
+ input [4:0]TXPOSTCURSOR;
+ input [4:0]TXPRECURSOR;
+ input [15:0]PIPE_TXDATA;
+ input [6:0]TXMAINCURSOR;
+ input [0:0]PIPE_TXCOMPLIANCE;
+ input [1:0]PIPE_TXDATAK;
+ input [7:0]DRPADDR;
+ input rate_cpllreset_0;
+ input RST_CPLLRESET;
+
+ wire CPLLPD0;
+ wire CPLLRESET0;
+ wire [7:0]DRPADDR;
+ wire [15:0]DRPDI;
+ wire [15:0]DRP_DO;
+ wire DRP_GTXRESET;
+ wire DRP_RDY;
+ wire [1:0]PIPE_POWERDOWN;
+ wire [0:0]PIPE_RXCHANISALIGNED;
+ wire [0:0]PIPE_RXPOLARITY;
+ wire [2:0]PIPE_RXSTATUS;
+ wire [0:0]PIPE_TXCOMPLIANCE;
+ wire [15:0]PIPE_TXDATA;
+ wire [1:0]PIPE_TXDATAK;
+ wire [0:0]PIPE_TXELECIDLE;
+ wire QPLL_QPLLOUTCLK;
+ wire QPLL_QPLLOUTREFCLK;
+ wire [0:0]QRST_CPLLLOCK;
+ wire RATE_PHYSTATUS;
+ wire RATE_RXRATEDONE;
+ wire RATE_TXRATEDONE;
+ wire RST_CPLLRESET;
+ wire [4:0]RXCHBONDO;
+ wire [0:0]RXRATE;
+ wire [0:0]RXSYSCLKSEL;
+ wire SYNC_RXPHALIGNDONE_M;
+ wire SYNC_TXDLYSRESET;
+ wire SYNC_TXPHALIGN;
+ wire SYNC_TXPHINIT;
+ wire [6:0]TXMAINCURSOR;
+ wire [4:0]TXPOSTCURSOR;
+ wire [4:0]TXPRECURSOR;
+ wire USER_OOBCLK;
+ wire USER_RXRESETDONE;
+ wire USER_TXRESETDONE;
+ wire \cplllock_reg1_reg[0] ;
+ wire \cplllock_reg1_reg[0]_0 ;
+ wire \cplllock_reg1_reg[0]_1 ;
+ wire [2:0]\cplllock_reg1_reg[0]_2 ;
+ wire cpllpd;
+ wire gt_cpllpdrefclk;
+ wire [1:0]gt_rx_data_k_wire_filter;
+ wire [15:0]gt_rx_data_wire_filter;
+ wire [0:0]gt_rx_elec_idle_wire_filter;
+ wire gt_rxcdrlock_0;
+ wire gt_rxvalid_0;
+ wire \gtx_channel.gtxe2_channel_i_n_10 ;
+ wire \gtx_channel.gtxe2_channel_i_n_138 ;
+ wire \gtx_channel.gtxe2_channel_i_n_139 ;
+ wire \gtx_channel.gtxe2_channel_i_n_140 ;
+ wire \gtx_channel.gtxe2_channel_i_n_141 ;
+ wire \gtx_channel.gtxe2_channel_i_n_142 ;
+ wire \gtx_channel.gtxe2_channel_i_n_143 ;
+ wire \gtx_channel.gtxe2_channel_i_n_144 ;
+ wire \gtx_channel.gtxe2_channel_i_n_145 ;
+ wire \gtx_channel.gtxe2_channel_i_n_146 ;
+ wire \gtx_channel.gtxe2_channel_i_n_147 ;
+ wire \gtx_channel.gtxe2_channel_i_n_148 ;
+ wire \gtx_channel.gtxe2_channel_i_n_149 ;
+ wire \gtx_channel.gtxe2_channel_i_n_150 ;
+ wire \gtx_channel.gtxe2_channel_i_n_151 ;
+ wire \gtx_channel.gtxe2_channel_i_n_152 ;
+ wire \gtx_channel.gtxe2_channel_i_n_153 ;
+ wire \gtx_channel.gtxe2_channel_i_n_16 ;
+ wire \gtx_channel.gtxe2_channel_i_n_177 ;
+ wire \gtx_channel.gtxe2_channel_i_n_178 ;
+ wire \gtx_channel.gtxe2_channel_i_n_179 ;
+ wire \gtx_channel.gtxe2_channel_i_n_180 ;
+ wire \gtx_channel.gtxe2_channel_i_n_181 ;
+ wire \gtx_channel.gtxe2_channel_i_n_182 ;
+ wire \gtx_channel.gtxe2_channel_i_n_183 ;
+ wire \gtx_channel.gtxe2_channel_i_n_184 ;
+ wire \gtx_channel.gtxe2_channel_i_n_189 ;
+ wire \gtx_channel.gtxe2_channel_i_n_190 ;
+ wire \gtx_channel.gtxe2_channel_i_n_191 ;
+ wire \gtx_channel.gtxe2_channel_i_n_192 ;
+ wire \gtx_channel.gtxe2_channel_i_n_197 ;
+ wire \gtx_channel.gtxe2_channel_i_n_198 ;
+ wire \gtx_channel.gtxe2_channel_i_n_201 ;
+ wire \gtx_channel.gtxe2_channel_i_n_202 ;
+ wire \gtx_channel.gtxe2_channel_i_n_203 ;
+ wire \gtx_channel.gtxe2_channel_i_n_204 ;
+ wire \gtx_channel.gtxe2_channel_i_n_205 ;
+ wire \gtx_channel.gtxe2_channel_i_n_206 ;
+ wire \gtx_channel.gtxe2_channel_i_n_207 ;
+ wire \gtx_channel.gtxe2_channel_i_n_208 ;
+ wire \gtx_channel.gtxe2_channel_i_n_209 ;
+ wire \gtx_channel.gtxe2_channel_i_n_210 ;
+ wire \gtx_channel.gtxe2_channel_i_n_211 ;
+ wire \gtx_channel.gtxe2_channel_i_n_212 ;
+ wire \gtx_channel.gtxe2_channel_i_n_213 ;
+ wire \gtx_channel.gtxe2_channel_i_n_214 ;
+ wire \gtx_channel.gtxe2_channel_i_n_215 ;
+ wire \gtx_channel.gtxe2_channel_i_n_216 ;
+ wire \gtx_channel.gtxe2_channel_i_n_27 ;
+ wire \gtx_channel.gtxe2_channel_i_n_4 ;
+ wire \gtx_channel.gtxe2_channel_i_n_82 ;
+ wire \gtx_channel.gtxe2_channel_i_n_83 ;
+ wire \gtx_channel.gtxe2_channel_i_n_84 ;
+ wire \gtx_channel.gtxe2_channel_i_n_9 ;
+ wire [0:0]pci_exp_rxn;
+ wire [0:0]pci_exp_rxp;
+ wire [0:0]pci_exp_txn;
+ wire [0:0]pci_exp_txp;
+ wire pipe_dclk_in;
+ wire pipe_dclk_in_0;
+ wire pipe_dclk_in_1;
+ wire pipe_dclk_in_2;
+ wire pipe_dclk_in_3;
+ wire pipe_pclk_in;
+ wire [0:0]pipe_rxoutclk_out;
+ wire pipe_rxusrclk_in;
+ wire pipe_tx_deemph_gt;
+ wire pipe_tx_rcvr_det_gt;
+ wire pipe_txoutclk_out;
+ wire rate_cpllreset_0;
+ wire rate_txpmareset_0;
+ wire rst_userrdy;
+ wire rxchbonden_0;
+ wire sync_txdlyen_0;
+ wire sys_clk;
+ wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ;
+ wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
+ wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ;
+ wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ;
+ wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
+ wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ;
+ wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ;
+ wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ;
+ wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ;
+ wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
+ wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ;
+ wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ;
+
+ pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_60 cpllPDInst
+ (.CPLLRESET0(CPLLRESET0),
+ .RST_CPLLRESET(RST_CPLLRESET),
+ .cpllpd(cpllpd),
+ .gt_cpllpdrefclk(gt_cpllpdrefclk),
+ .rate_cpllreset_0(rate_cpllreset_0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ GTXE2_CHANNEL #(
+ .ALIGN_COMMA_DOUBLE("FALSE"),
+ .ALIGN_COMMA_ENABLE(10'b1111111111),
+ .ALIGN_COMMA_WORD(1),
+ .ALIGN_MCOMMA_DET("TRUE"),
+ .ALIGN_MCOMMA_VALUE(10'b1010000011),
+ .ALIGN_PCOMMA_DET("TRUE"),
+ .ALIGN_PCOMMA_VALUE(10'b0101111100),
+ .CBCC_DATA_SOURCE_SEL("DECODED"),
+ .CHAN_BOND_KEEP_ALIGN("TRUE"),
+ .CHAN_BOND_MAX_SKEW(7),
+ .CHAN_BOND_SEQ_1_1(10'b0001001010),
+ .CHAN_BOND_SEQ_1_2(10'b0001001010),
+ .CHAN_BOND_SEQ_1_3(10'b0001001010),
+ .CHAN_BOND_SEQ_1_4(10'b0110111100),
+ .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
+ .CHAN_BOND_SEQ_2_1(10'b0001000101),
+ .CHAN_BOND_SEQ_2_2(10'b0001000101),
+ .CHAN_BOND_SEQ_2_3(10'b0001000101),
+ .CHAN_BOND_SEQ_2_4(10'b0110111100),
+ .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
+ .CHAN_BOND_SEQ_2_USE("TRUE"),
+ .CHAN_BOND_SEQ_LEN(4),
+ .CLK_CORRECT_USE("TRUE"),
+ .CLK_COR_KEEP_IDLE("TRUE"),
+ .CLK_COR_MAX_LAT(20),
+ .CLK_COR_MIN_LAT(18),
+ .CLK_COR_PRECEDENCE("TRUE"),
+ .CLK_COR_REPEAT_WAIT(0),
+ .CLK_COR_SEQ_1_1(10'b0100011100),
+ .CLK_COR_SEQ_1_2(10'b0000000000),
+ .CLK_COR_SEQ_1_3(10'b0000000000),
+ .CLK_COR_SEQ_1_4(10'b0000000000),
+ .CLK_COR_SEQ_1_ENABLE(4'b1111),
+ .CLK_COR_SEQ_2_1(10'b0000000000),
+ .CLK_COR_SEQ_2_2(10'b0000000000),
+ .CLK_COR_SEQ_2_3(10'b0000000000),
+ .CLK_COR_SEQ_2_4(10'b0000000000),
+ .CLK_COR_SEQ_2_ENABLE(4'b0000),
+ .CLK_COR_SEQ_2_USE("FALSE"),
+ .CLK_COR_SEQ_LEN(1),
+ .CPLL_CFG(24'hA407CC),
+ .CPLL_FBDIV(5),
+ .CPLL_FBDIV_45(5),
+ .CPLL_INIT_CFG(24'h00001E),
+ .CPLL_LOCK_CFG(16'h01E8),
+ .CPLL_REFCLK_DIV(1),
+ .DEC_MCOMMA_DETECT("TRUE"),
+ .DEC_PCOMMA_DETECT("TRUE"),
+ .DEC_VALID_COMMA_ONLY("FALSE"),
+ .DMONITOR_CFG(24'h000B01),
+ .ES_CONTROL(6'b000000),
+ .ES_ERRDET_EN("FALSE"),
+ .ES_EYE_SCAN_EN("FALSE"),
+ .ES_HORZ_OFFSET(12'h000),
+ .ES_PMA_CFG(10'b0000000000),
+ .ES_PRESCALE(5'b00000),
+ .ES_QUALIFIER(80'h00000000000000000000),
+ .ES_QUAL_MASK(80'h00000000000000000000),
+ .ES_SDATA_MASK(80'h00000000000000000000),
+ .ES_VERT_OFFSET(9'b000000000),
+ .FTS_DESKEW_SEQ_ENABLE(4'b1111),
+ .FTS_LANE_DESKEW_CFG(4'b1111),
+ .FTS_LANE_DESKEW_EN("TRUE"),
+ .GEARBOX_MODE(3'b000),
+ .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
+ .IS_DRPCLK_INVERTED(1'b0),
+ .IS_GTGREFCLK_INVERTED(1'b0),
+ .IS_RXUSRCLK2_INVERTED(1'b0),
+ .IS_RXUSRCLK_INVERTED(1'b0),
+ .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
+ .IS_TXUSRCLK2_INVERTED(1'b0),
+ .IS_TXUSRCLK_INVERTED(1'b0),
+ .OUTREFCLK_SEL_INV(2'b11),
+ .PCS_PCIE_EN("TRUE"),
+ .PCS_RSVD_ATTR(48'h0000000001CF),
+ .PD_TRANS_TIME_FROM_P2(12'h03C),
+ .PD_TRANS_TIME_NONE_P2(8'h09),
+ .PD_TRANS_TIME_TO_P2(8'h64),
+ .PMA_RSV(32'h00018480),
+ .PMA_RSV2(16'h2050),
+ .PMA_RSV3(2'b00),
+ .PMA_RSV4(32'h00000000),
+ .RXBUFRESET_TIME(5'b00001),
+ .RXBUF_ADDR_MODE("FULL"),
+ .RXBUF_EIDLE_HI_CNT(4'b0100),
+ .RXBUF_EIDLE_LO_CNT(4'b0000),
+ .RXBUF_EN("TRUE"),
+ .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
+ .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
+ .RXBUF_RESET_ON_EIDLE("TRUE"),
+ .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
+ .RXBUF_THRESH_OVFLW(61),
+ .RXBUF_THRESH_OVRD("FALSE"),
+ .RXBUF_THRESH_UNDFLW(4),
+ .RXCDRFREQRESET_TIME(5'b00001),
+ .RXCDRPHRESET_TIME(5'b00001),
+ .RXCDR_CFG(72'h03000023FF10200020),
+ .RXCDR_FR_RESET_ON_EIDLE(1'b0),
+ .RXCDR_HOLD_DURING_EIDLE(1'b1),
+ .RXCDR_LOCK_CFG(6'b010101),
+ .RXCDR_PH_RESET_ON_EIDLE(1'b0),
+ .RXDFELPMRESET_TIME(7'b0001111),
+ .RXDLY_CFG(16'h001F),
+ .RXDLY_LCFG(9'h030),
+ .RXDLY_TAP_CFG(16'h0000),
+ .RXGEARBOX_EN("FALSE"),
+ .RXISCANRESET_TIME(5'b00001),
+ .RXLPM_HF_CFG(14'b00000011110000),
+ .RXLPM_LF_CFG(14'b00000011110000),
+ .RXOOB_CFG(7'b0000110),
+ .RXOUT_DIV(2),
+ .RXPCSRESET_TIME(5'b00001),
+ .RXPHDLY_CFG(24'h004020),
+ .RXPH_CFG(24'h000000),
+ .RXPH_MONITOR_SEL(5'b00000),
+ .RXPMARESET_TIME(5'b00011),
+ .RXPRBS_ERR_LOOPBACK(1'b0),
+ .RXSLIDE_AUTO_WAIT(7),
+ .RXSLIDE_MODE("PMA"),
+ .RX_BIAS_CFG(12'b000000000100),
+ .RX_BUFFER_CFG(6'b000000),
+ .RX_CLK25_DIV(4),
+ .RX_CLKMUX_PD(1'b1),
+ .RX_CM_SEL(2'b11),
+ .RX_CM_TRIM(3'b010),
+ .RX_DATA_WIDTH(20),
+ .RX_DDI_SEL(6'b000000),
+ .RX_DEBUG_CFG(12'b000000000000),
+ .RX_DEFER_RESET_BUF_EN("TRUE"),
+ .RX_DFE_GAIN_CFG(23'h020FEA),
+ .RX_DFE_H2_CFG(12'b000000000000),
+ .RX_DFE_H3_CFG(12'b000001000000),
+ .RX_DFE_H4_CFG(11'b00011110000),
+ .RX_DFE_H5_CFG(11'b00011100000),
+ .RX_DFE_KL_CFG(13'b0000011111110),
+ .RX_DFE_KL_CFG2(32'h3290D86C),
+ .RX_DFE_LPM_CFG(16'h0954),
+ .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1),
+ .RX_DFE_UT_CFG(17'b10001111000000000),
+ .RX_DFE_VP_CFG(17'b00011111100000011),
+ .RX_DFE_XYD_CFG(13'b0000000000000),
+ .RX_DISPERR_SEQ_MATCH("TRUE"),
+ .RX_INT_DATAWIDTH(0),
+ .RX_OS_CFG(13'b0000010000000),
+ .RX_SIG_VALID_DLY(4),
+ .RX_XCLK_SEL("RXREC"),
+ .SAS_MAX_COM(64),
+ .SAS_MIN_COM(36),
+ .SATA_BURST_SEQ_LEN(4'b1111),
+ .SATA_BURST_VAL(3'b100),
+ .SATA_CPLL_CFG("VCO_3000MHZ"),
+ .SATA_EIDLE_VAL(3'b100),
+ .SATA_MAX_BURST(8),
+ .SATA_MAX_INIT(21),
+ .SATA_MAX_WAKE(7),
+ .SATA_MIN_BURST(4),
+ .SATA_MIN_INIT(12),
+ .SATA_MIN_WAKE(4),
+ .SHOW_REALIGN_COMMA("FALSE"),
+ .SIM_CPLLREFCLK_SEL(3'b001),
+ .SIM_RECEIVER_DETECT_PASS("TRUE"),
+ .SIM_RESET_SPEEDUP("FALSE"),
+ .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
+ .SIM_VERSION("3.0"),
+ .TERM_RCAL_CFG(5'b10000),
+ .TERM_RCAL_OVRD(1'b0),
+ .TRANS_TIME_RATE(8'h0E),
+ .TST_RSV(32'h00000000),
+ .TXBUF_EN("FALSE"),
+ .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
+ .TXDLY_CFG(16'h001F),
+ .TXDLY_LCFG(9'h030),
+ .TXDLY_TAP_CFG(16'h0000),
+ .TXGEARBOX_EN("FALSE"),
+ .TXOUT_DIV(2),
+ .TXPCSRESET_TIME(5'b00001),
+ .TXPHDLY_CFG(24'h084020),
+ .TXPH_CFG(16'h0780),
+ .TXPH_MONITOR_SEL(5'b00000),
+ .TXPMARESET_TIME(5'b00011),
+ .TX_CLK25_DIV(4),
+ .TX_CLKMUX_PD(1'b1),
+ .TX_DATA_WIDTH(20),
+ .TX_DEEMPH0(5'b10100),
+ .TX_DEEMPH1(5'b01011),
+ .TX_DRIVE_MODE("PIPE"),
+ .TX_EIDLE_ASSERT_DELAY(3'b010),
+ .TX_EIDLE_DEASSERT_DELAY(3'b100),
+ .TX_INT_DATAWIDTH(0),
+ .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
+ .TX_MAINCURSOR_SEL(1'b0),
+ .TX_MARGIN_FULL_0(7'b1001111),
+ .TX_MARGIN_FULL_1(7'b1001110),
+ .TX_MARGIN_FULL_2(7'b1001101),
+ .TX_MARGIN_FULL_3(7'b1001100),
+ .TX_MARGIN_FULL_4(7'b1000011),
+ .TX_MARGIN_LOW_0(7'b1000101),
+ .TX_MARGIN_LOW_1(7'b1000110),
+ .TX_MARGIN_LOW_2(7'b1000011),
+ .TX_MARGIN_LOW_3(7'b1000010),
+ .TX_MARGIN_LOW_4(7'b1000000),
+ .TX_PREDRIVER_MODE(1'b0),
+ .TX_QPI_STATUS_EN(1'b0),
+ .TX_RXDETECT_CFG(14'h0064),
+ .TX_RXDETECT_REF(3'b011),
+ .TX_XCLK_SEL("TXUSR"),
+ .UCODEER_CLR(1'b0))
+ \gtx_channel.gtxe2_channel_i
+ (.CFGRESET(1'b0),
+ .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}),
+ .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ),
+ .CPLLLOCK(QRST_CPLLLOCK),
+ .CPLLLOCKDETCLK(1'b0),
+ .CPLLLOCKEN(1'b1),
+ .CPLLPD(CPLLPD0),
+ .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ),
+ .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
+ .CPLLRESET(CPLLRESET0),
+ .DMONITOROUT({\gtx_channel.gtxe2_channel_i_n_177 ,\gtx_channel.gtxe2_channel_i_n_178 ,\gtx_channel.gtxe2_channel_i_n_179 ,\gtx_channel.gtxe2_channel_i_n_180 ,\gtx_channel.gtxe2_channel_i_n_181 ,\gtx_channel.gtxe2_channel_i_n_182 ,\gtx_channel.gtxe2_channel_i_n_183 ,\gtx_channel.gtxe2_channel_i_n_184 }),
+ .DRPADDR({1'b0,DRPADDR}),
+ .DRPCLK(pipe_dclk_in),
+ .DRPDI(DRPDI),
+ .DRPDO(DRP_DO),
+ .DRPEN(\cplllock_reg1_reg[0] ),
+ .DRPRDY(DRP_RDY),
+ .DRPWE(\cplllock_reg1_reg[0]_0 ),
+ .EYESCANDATAERROR(\gtx_channel.gtxe2_channel_i_n_4 ),
+ .EYESCANMODE(1'b0),
+ .EYESCANRESET(1'b0),
+ .EYESCANTRIGGER(1'b0),
+ .GTGREFCLK(1'b0),
+ .GTNORTHREFCLK0(1'b0),
+ .GTNORTHREFCLK1(1'b0),
+ .GTREFCLK0(sys_clk),
+ .GTREFCLK1(1'b0),
+ .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ),
+ .GTRESETSEL(1'b0),
+ .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .GTRXRESET(DRP_GTXRESET),
+ .GTSOUTHREFCLK0(1'b0),
+ .GTSOUTHREFCLK1(1'b0),
+ .GTTXRESET(DRP_GTXRESET),
+ .GTXRXN(pci_exp_rxn),
+ .GTXRXP(pci_exp_rxp),
+ .GTXTXN(pci_exp_txn),
+ .GTXTXP(pci_exp_txp),
+ .LOOPBACK({1'b0,1'b0,1'b0}),
+ .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
+ .PHYSTATUS(RATE_PHYSTATUS),
+ .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .QPLLCLK(QPLL_QPLLOUTCLK),
+ .QPLLREFCLK(QPLL_QPLLOUTREFCLK),
+ .RESETOVRD(1'b0),
+ .RX8B10BEN(rxchbonden_0),
+ .RXBUFRESET(1'b0),
+ .RXBUFSTATUS({\gtx_channel.gtxe2_channel_i_n_82 ,\gtx_channel.gtxe2_channel_i_n_83 ,\gtx_channel.gtxe2_channel_i_n_84 }),
+ .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ),
+ .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ),
+ .RXCDRFREQRESET(1'b0),
+ .RXCDRHOLD(1'b0),
+ .RXCDRLOCK(gt_rxcdrlock_0),
+ .RXCDROVRDEN(1'b0),
+ .RXCDRRESET(1'b0),
+ .RXCDRRESETRSV(1'b0),
+ .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
+ .RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
+ .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
+ .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }),
+ .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,gt_rx_data_k_wire_filter}),
+ .RXCHBONDEN(rxchbonden_0),
+ .RXCHBONDI({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .RXCHBONDLEVEL({1'b0,1'b0,1'b1}),
+ .RXCHBONDMASTER(rxchbonden_0),
+ .RXCHBONDO(RXCHBONDO),
+ .RXCHBONDSLAVE(1'b0),
+ .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
+ .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ),
+ .RXCOMMADET(\gtx_channel.gtxe2_channel_i_n_16 ),
+ .RXCOMMADETEN(1'b1),
+ .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ),
+ .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
+ .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,gt_rx_data_wire_filter}),
+ .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ),
+ .RXDDIEN(1'b0),
+ .RXDFEAGCHOLD(\cplllock_reg1_reg[0]_1 ),
+ .RXDFEAGCOVRDEN(1'b0),
+ .RXDFECM1EN(1'b0),
+ .RXDFELFHOLD(1'b0),
+ .RXDFELFOVRDEN(1'b1),
+ .RXDFELPMRESET(1'b0),
+ .RXDFETAP2HOLD(1'b0),
+ .RXDFETAP2OVRDEN(1'b0),
+ .RXDFETAP3HOLD(1'b0),
+ .RXDFETAP3OVRDEN(1'b0),
+ .RXDFETAP4HOLD(1'b0),
+ .RXDFETAP4OVRDEN(1'b0),
+ .RXDFETAP5HOLD(1'b0),
+ .RXDFETAP5OVRDEN(1'b0),
+ .RXDFEUTHOLD(1'b0),
+ .RXDFEUTOVRDEN(1'b0),
+ .RXDFEVPHOLD(1'b0),
+ .RXDFEVPOVRDEN(1'b0),
+ .RXDFEVSEN(1'b0),
+ .RXDFEXYDEN(1'b0),
+ .RXDFEXYDHOLD(1'b0),
+ .RXDFEXYDOVRDEN(1'b0),
+ .RXDISPERR({\gtx_channel.gtxe2_channel_i_n_201 ,\gtx_channel.gtxe2_channel_i_n_202 ,\gtx_channel.gtxe2_channel_i_n_203 ,\gtx_channel.gtxe2_channel_i_n_204 ,\gtx_channel.gtxe2_channel_i_n_205 ,\gtx_channel.gtxe2_channel_i_n_206 ,\gtx_channel.gtxe2_channel_i_n_207 ,\gtx_channel.gtxe2_channel_i_n_208 }),
+ .RXDLYBYPASS(1'b1),
+ .RXDLYEN(1'b0),
+ .RXDLYOVRDEN(1'b0),
+ .RXDLYSRESET(1'b0),
+ .RXDLYSRESETDONE(pipe_dclk_in_0),
+ .RXELECIDLE(gt_rx_elec_idle_wire_filter),
+ .RXELECIDLEMODE({1'b0,1'b0}),
+ .RXGEARBOXSLIP(1'b0),
+ .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
+ .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ),
+ .RXLPMEN(rxchbonden_0),
+ .RXLPMHFHOLD(1'b0),
+ .RXLPMHFOVRDEN(1'b0),
+ .RXLPMLFHOLD(1'b0),
+ .RXLPMLFKLOVRDEN(1'b0),
+ .RXMCOMMAALIGNEN(rxchbonden_0),
+ .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]),
+ .RXMONITORSEL({1'b0,1'b0}),
+ .RXNOTINTABLE({\gtx_channel.gtxe2_channel_i_n_209 ,\gtx_channel.gtxe2_channel_i_n_210 ,\gtx_channel.gtxe2_channel_i_n_211 ,\gtx_channel.gtxe2_channel_i_n_212 ,\gtx_channel.gtxe2_channel_i_n_213 ,\gtx_channel.gtxe2_channel_i_n_214 ,\gtx_channel.gtxe2_channel_i_n_215 ,\gtx_channel.gtxe2_channel_i_n_216 }),
+ .RXOOBRESET(1'b0),
+ .RXOSHOLD(1'b0),
+ .RXOSOVRDEN(1'b0),
+ .RXOUTCLK(pipe_rxoutclk_out),
+ .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
+ .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
+ .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
+ .RXPCOMMAALIGNEN(rxchbonden_0),
+ .RXPCSRESET(1'b0),
+ .RXPD(PIPE_POWERDOWN),
+ .RXPHALIGN(1'b0),
+ .RXPHALIGNDONE(SYNC_RXPHALIGNDONE_M),
+ .RXPHALIGNEN(1'b0),
+ .RXPHDLYPD(1'b0),
+ .RXPHDLYRESET(1'b0),
+ .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
+ .RXPHOVRDEN(1'b0),
+ .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
+ .RXPMARESET(rate_txpmareset_0),
+ .RXPOLARITY(PIPE_RXPOLARITY),
+ .RXPRBSCNTRESET(1'b0),
+ .RXPRBSERR(\gtx_channel.gtxe2_channel_i_n_27 ),
+ .RXPRBSSEL({1'b0,1'b0,1'b0}),
+ .RXQPIEN(1'b0),
+ .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ),
+ .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ),
+ .RXRATE({1'b0,1'b0,RXRATE}),
+ .RXRATEDONE(RATE_RXRATEDONE),
+ .RXRESETDONE(USER_RXRESETDONE),
+ .RXSLIDE(1'b0),
+ .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ),
+ .RXSTATUS(PIPE_RXSTATUS),
+ .RXSYSCLKSEL({1'b0,RXSYSCLKSEL}),
+ .RXUSERRDY(rst_userrdy),
+ .RXUSRCLK(pipe_rxusrclk_in),
+ .RXUSRCLK2(pipe_rxusrclk_in),
+ .RXVALID(gt_rxvalid_0),
+ .SETERRSTATUS(1'b0),
+ .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]),
+ .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .TX8B10BEN(rxchbonden_0),
+ .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
+ .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
+ .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}),
+ .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}),
+ .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ),
+ .TXCOMINIT(1'b0),
+ .TXCOMSAS(1'b0),
+ .TXCOMWAKE(1'b0),
+ .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}),
+ .TXDEEMPH(pipe_tx_deemph_gt),
+ .TXDETECTRX(pipe_tx_rcvr_det_gt),
+ .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
+ .TXDIFFPD(1'b0),
+ .TXDLYBYPASS(1'b0),
+ .TXDLYEN(sync_txdlyen_0),
+ .TXDLYHOLD(1'b0),
+ .TXDLYOVRDEN(1'b0),
+ .TXDLYSRESET(SYNC_TXDLYSRESET),
+ .TXDLYSRESETDONE(pipe_dclk_in_1),
+ .TXDLYUPDOWN(1'b0),
+ .TXELECIDLE(PIPE_TXELECIDLE),
+ .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
+ .TXHEADER({1'b0,1'b0,1'b0}),
+ .TXINHIBIT(1'b0),
+ .TXMAINCURSOR(TXMAINCURSOR),
+ .TXMARGIN(\cplllock_reg1_reg[0]_2 ),
+ .TXOUTCLK(pipe_txoutclk_out),
+ .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
+ .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
+ .TXOUTCLKSEL({1'b0,1'b1,1'b1}),
+ .TXPCSRESET(1'b0),
+ .TXPD(PIPE_POWERDOWN),
+ .TXPDELECIDLEMODE(1'b0),
+ .TXPHALIGN(SYNC_TXPHALIGN),
+ .TXPHALIGNDONE(pipe_dclk_in_2),
+ .TXPHALIGNEN(1'b1),
+ .TXPHDLYPD(1'b0),
+ .TXPHDLYRESET(1'b0),
+ .TXPHDLYTSTCLK(1'b0),
+ .TXPHINIT(SYNC_TXPHINIT),
+ .TXPHINITDONE(pipe_dclk_in_3),
+ .TXPHOVRDEN(1'b0),
+ .TXPISOPD(1'b0),
+ .TXPMARESET(rate_txpmareset_0),
+ .TXPOLARITY(1'b0),
+ .TXPOSTCURSOR(TXPOSTCURSOR),
+ .TXPOSTCURSORINV(1'b0),
+ .TXPRBSFORCEERR(1'b0),
+ .TXPRBSSEL({1'b0,1'b0,1'b0}),
+ .TXPRECURSOR(TXPRECURSOR),
+ .TXPRECURSORINV(1'b0),
+ .TXQPIBIASEN(1'b0),
+ .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ),
+ .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ),
+ .TXQPISTRONGPDOWN(1'b0),
+ .TXQPIWEAKPUP(1'b0),
+ .TXRATE({1'b0,1'b0,RXRATE}),
+ .TXRATEDONE(RATE_TXRATEDONE),
+ .TXRESETDONE(USER_TXRESETDONE),
+ .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .TXSTARTSEQ(1'b0),
+ .TXSWING(1'b0),
+ .TXSYSCLKSEL({1'b0,RXSYSCLKSEL}),
+ .TXUSERRDY(rst_userrdy),
+ .TXUSRCLK(pipe_pclk_in),
+ .TXUSRCLK2(pipe_pclk_in));
+endmodule
+
+(* ORIG_REF_NAME = "pcie_7x_0_gt_wrapper" *)
+module pcie_7x_0_pcie_7x_0_gt_wrapper_37
+ (cpllpd_0,
+ QRST_CPLLLOCK,
+ DRP_RDY,
+ pci_exp_txn,
+ pci_exp_txp,
+ RATE_PHYSTATUS,
+ gt_rxcdrlock_1,
+ PIPE_RXCHANISALIGNED,
+ pipe_dclk_in_0,
+ gt_rx_elec_idle_wire_filter,
+ pipe_rxoutclk_out,
+ pipe_dclk_in_1,
+ RATE_RXRATEDONE,
+ USER_RXRESETDONE,
+ gt_rxvalid_1,
+ pipe_dclk_in_2,
+ pipe_dclk_in_3,
+ pipe_dclk_in_4,
+ RATE_TXRATEDONE,
+ USER_TXRESETDONE,
+ DRP_DO,
+ pipe_dclk_in_5,
+ gt_rx_data_wire_filter,
+ gt_rx_data_k_wire_filter,
+ gt_cpllpdrefclk,
+ CPLLPD0_3,
+ pipe_dclk_in,
+ \cplllock_reg1_reg[1] ,
+ \cplllock_reg1_reg[1]_0 ,
+ sys_clk,
+ DRP_GTXRESET,
+ pci_exp_rxn,
+ pci_exp_rxp,
+ QPLL_QPLLOUTCLK,
+ QPLL_QPLLOUTREFCLK,
+ rxchbonden_1,
+ \cplllock_reg1_reg[1]_1 ,
+ rate_txpmareset_1,
+ PIPE_RXPOLARITY,
+ rst_userrdy,
+ pipe_rxusrclk_in,
+ pipe_tx_deemph_gt,
+ pipe_tx_rcvr_det_gt,
+ SYNC_TXDLYSRESET,
+ PIPE_TXELECIDLE,
+ SYNC_TXPHALIGN,
+ SYNC_TXPHINIT,
+ pipe_pclk_in,
+ DRPDI,
+ PIPE_POWERDOWN,
+ RXSYSCLKSEL,
+ RXRATE,
+ \cplllock_reg1_reg[1]_2 ,
+ USER_OOBCLK,
+ RXCHBONDO,
+ TXPOSTCURSOR,
+ TXPRECURSOR,
+ PIPE_TXDATA,
+ TXMAINCURSOR,
+ PIPE_TXCOMPLIANCE,
+ PIPE_TXDATAK,
+ DRPADDR,
+ rate_cpllreset_1,
+ RST_CPLLRESET);
+ output cpllpd_0;
+ output [0:0]QRST_CPLLLOCK;
+ output DRP_RDY;
+ output [0:0]pci_exp_txn;
+ output [0:0]pci_exp_txp;
+ output RATE_PHYSTATUS;
+ output gt_rxcdrlock_1;
+ output [0:0]PIPE_RXCHANISALIGNED;
+ output pipe_dclk_in_0;
+ output [0:0]gt_rx_elec_idle_wire_filter;
+ output [0:0]pipe_rxoutclk_out;
+ output pipe_dclk_in_1;
+ output RATE_RXRATEDONE;
+ output USER_RXRESETDONE;
+ output gt_rxvalid_1;
+ output pipe_dclk_in_2;
+ output pipe_dclk_in_3;
+ output pipe_dclk_in_4;
+ output RATE_TXRATEDONE;
+ output USER_TXRESETDONE;
+ output [15:0]DRP_DO;
+ output [2:0]pipe_dclk_in_5;
+ output [15:0]gt_rx_data_wire_filter;
+ output [1:0]gt_rx_data_k_wire_filter;
+ input gt_cpllpdrefclk;
+ input CPLLPD0_3;
+ input pipe_dclk_in;
+ input \cplllock_reg1_reg[1] ;
+ input \cplllock_reg1_reg[1]_0 ;
+ input sys_clk;
+ input DRP_GTXRESET;
+ input [0:0]pci_exp_rxn;
+ input [0:0]pci_exp_rxp;
+ input QPLL_QPLLOUTCLK;
+ input QPLL_QPLLOUTREFCLK;
+ input rxchbonden_1;
+ input \cplllock_reg1_reg[1]_1 ;
+ input rate_txpmareset_1;
+ input [0:0]PIPE_RXPOLARITY;
+ input rst_userrdy;
+ input pipe_rxusrclk_in;
+ input pipe_tx_deemph_gt;
+ input pipe_tx_rcvr_det_gt;
+ input SYNC_TXDLYSRESET;
+ input [0:0]PIPE_TXELECIDLE;
+ input SYNC_TXPHALIGN;
+ input SYNC_TXPHINIT;
+ input pipe_pclk_in;
+ input [15:0]DRPDI;
+ input [1:0]PIPE_POWERDOWN;
+ input [0:0]RXSYSCLKSEL;
+ input [0:0]RXRATE;
+ input [2:0]\cplllock_reg1_reg[1]_2 ;
+ input USER_OOBCLK;
+ input [4:0]RXCHBONDO;
+ input [4:0]TXPOSTCURSOR;
+ input [4:0]TXPRECURSOR;
+ input [15:0]PIPE_TXDATA;
+ input [6:0]TXMAINCURSOR;
+ input [0:0]PIPE_TXCOMPLIANCE;
+ input [1:0]PIPE_TXDATAK;
+ input [7:0]DRPADDR;
+ input rate_cpllreset_1;
+ input RST_CPLLRESET;
+
+ wire CPLLPD0_3;
+ wire CPLLRESET0;
+ wire [7:0]DRPADDR;
+ wire [15:0]DRPDI;
+ wire [15:0]DRP_DO;
+ wire DRP_GTXRESET;
+ wire DRP_RDY;
+ wire [1:0]PIPE_POWERDOWN;
+ wire [0:0]PIPE_RXCHANISALIGNED;
+ wire [0:0]PIPE_RXPOLARITY;
+ wire [0:0]PIPE_TXCOMPLIANCE;
+ wire [15:0]PIPE_TXDATA;
+ wire [1:0]PIPE_TXDATAK;
+ wire [0:0]PIPE_TXELECIDLE;
+ wire QPLL_QPLLOUTCLK;
+ wire QPLL_QPLLOUTREFCLK;
+ wire [0:0]QRST_CPLLLOCK;
+ wire RATE_PHYSTATUS;
+ wire RATE_RXRATEDONE;
+ wire RATE_TXRATEDONE;
+ wire RST_CPLLRESET;
+ wire [4:0]RXCHBONDO;
+ wire [0:0]RXRATE;
+ wire [0:0]RXSYSCLKSEL;
+ wire SYNC_TXDLYSRESET;
+ wire SYNC_TXPHALIGN;
+ wire SYNC_TXPHINIT;
+ wire [6:0]TXMAINCURSOR;
+ wire [4:0]TXPOSTCURSOR;
+ wire [4:0]TXPRECURSOR;
+ wire USER_OOBCLK;
+ wire USER_RXRESETDONE;
+ wire USER_TXRESETDONE;
+ wire \cplllock_reg1_reg[1] ;
+ wire \cplllock_reg1_reg[1]_0 ;
+ wire \cplllock_reg1_reg[1]_1 ;
+ wire [2:0]\cplllock_reg1_reg[1]_2 ;
+ wire cpllpd_0;
+ wire gt_cpllpdrefclk;
+ wire [1:0]gt_rx_data_k_wire_filter;
+ wire [15:0]gt_rx_data_wire_filter;
+ wire [0:0]gt_rx_elec_idle_wire_filter;
+ wire gt_rxcdrlock_1;
+ wire gt_rxvalid_1;
+ wire \gtx_channel.gtxe2_channel_i_n_10 ;
+ wire \gtx_channel.gtxe2_channel_i_n_138 ;
+ wire \gtx_channel.gtxe2_channel_i_n_139 ;
+ wire \gtx_channel.gtxe2_channel_i_n_140 ;
+ wire \gtx_channel.gtxe2_channel_i_n_141 ;
+ wire \gtx_channel.gtxe2_channel_i_n_142 ;
+ wire \gtx_channel.gtxe2_channel_i_n_143 ;
+ wire \gtx_channel.gtxe2_channel_i_n_144 ;
+ wire \gtx_channel.gtxe2_channel_i_n_145 ;
+ wire \gtx_channel.gtxe2_channel_i_n_146 ;
+ wire \gtx_channel.gtxe2_channel_i_n_147 ;
+ wire \gtx_channel.gtxe2_channel_i_n_148 ;
+ wire \gtx_channel.gtxe2_channel_i_n_149 ;
+ wire \gtx_channel.gtxe2_channel_i_n_150 ;
+ wire \gtx_channel.gtxe2_channel_i_n_151 ;
+ wire \gtx_channel.gtxe2_channel_i_n_152 ;
+ wire \gtx_channel.gtxe2_channel_i_n_153 ;
+ wire \gtx_channel.gtxe2_channel_i_n_16 ;
+ wire \gtx_channel.gtxe2_channel_i_n_177 ;
+ wire \gtx_channel.gtxe2_channel_i_n_178 ;
+ wire \gtx_channel.gtxe2_channel_i_n_179 ;
+ wire \gtx_channel.gtxe2_channel_i_n_180 ;
+ wire \gtx_channel.gtxe2_channel_i_n_181 ;
+ wire \gtx_channel.gtxe2_channel_i_n_182 ;
+ wire \gtx_channel.gtxe2_channel_i_n_183 ;
+ wire \gtx_channel.gtxe2_channel_i_n_184 ;
+ wire \gtx_channel.gtxe2_channel_i_n_189 ;
+ wire \gtx_channel.gtxe2_channel_i_n_190 ;
+ wire \gtx_channel.gtxe2_channel_i_n_191 ;
+ wire \gtx_channel.gtxe2_channel_i_n_192 ;
+ wire \gtx_channel.gtxe2_channel_i_n_197 ;
+ wire \gtx_channel.gtxe2_channel_i_n_198 ;
+ wire \gtx_channel.gtxe2_channel_i_n_201 ;
+ wire \gtx_channel.gtxe2_channel_i_n_202 ;
+ wire \gtx_channel.gtxe2_channel_i_n_203 ;
+ wire \gtx_channel.gtxe2_channel_i_n_204 ;
+ wire \gtx_channel.gtxe2_channel_i_n_205 ;
+ wire \gtx_channel.gtxe2_channel_i_n_206 ;
+ wire \gtx_channel.gtxe2_channel_i_n_207 ;
+ wire \gtx_channel.gtxe2_channel_i_n_208 ;
+ wire \gtx_channel.gtxe2_channel_i_n_209 ;
+ wire \gtx_channel.gtxe2_channel_i_n_210 ;
+ wire \gtx_channel.gtxe2_channel_i_n_211 ;
+ wire \gtx_channel.gtxe2_channel_i_n_212 ;
+ wire \gtx_channel.gtxe2_channel_i_n_213 ;
+ wire \gtx_channel.gtxe2_channel_i_n_214 ;
+ wire \gtx_channel.gtxe2_channel_i_n_215 ;
+ wire \gtx_channel.gtxe2_channel_i_n_216 ;
+ wire \gtx_channel.gtxe2_channel_i_n_27 ;
+ wire \gtx_channel.gtxe2_channel_i_n_37 ;
+ wire \gtx_channel.gtxe2_channel_i_n_4 ;
+ wire \gtx_channel.gtxe2_channel_i_n_82 ;
+ wire \gtx_channel.gtxe2_channel_i_n_83 ;
+ wire \gtx_channel.gtxe2_channel_i_n_84 ;
+ wire \gtx_channel.gtxe2_channel_i_n_9 ;
+ wire \gtx_channel.gtxe2_channel_i_n_91 ;
+ wire \gtx_channel.gtxe2_channel_i_n_92 ;
+ wire \gtx_channel.gtxe2_channel_i_n_93 ;
+ wire \gtx_channel.gtxe2_channel_i_n_94 ;
+ wire \gtx_channel.gtxe2_channel_i_n_95 ;
+ wire [0:0]pci_exp_rxn;
+ wire [0:0]pci_exp_rxp;
+ wire [0:0]pci_exp_txn;
+ wire [0:0]pci_exp_txp;
+ wire pipe_dclk_in;
+ wire pipe_dclk_in_0;
+ wire pipe_dclk_in_1;
+ wire pipe_dclk_in_2;
+ wire pipe_dclk_in_3;
+ wire pipe_dclk_in_4;
+ wire [2:0]pipe_dclk_in_5;
+ wire pipe_pclk_in;
+ wire [0:0]pipe_rxoutclk_out;
+ wire pipe_rxusrclk_in;
+ wire pipe_tx_deemph_gt;
+ wire pipe_tx_rcvr_det_gt;
+ wire rate_cpllreset_1;
+ wire rate_txpmareset_1;
+ wire rst_userrdy;
+ wire rxchbonden_1;
+ wire sys_clk;
+ wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ;
+ wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
+ wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ;
+ wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ;
+ wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
+ wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ;
+ wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ;
+ wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ;
+ wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ;
+ wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
+ wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ;
+ wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ;
+
+ pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_58 cpllPDInst
+ (.CPLLRESET0(CPLLRESET0),
+ .RST_CPLLRESET(RST_CPLLRESET),
+ .cpllpd_0(cpllpd_0),
+ .gt_cpllpdrefclk(gt_cpllpdrefclk),
+ .rate_cpllreset_1(rate_cpllreset_1));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ GTXE2_CHANNEL #(
+ .ALIGN_COMMA_DOUBLE("FALSE"),
+ .ALIGN_COMMA_ENABLE(10'b1111111111),
+ .ALIGN_COMMA_WORD(1),
+ .ALIGN_MCOMMA_DET("TRUE"),
+ .ALIGN_MCOMMA_VALUE(10'b1010000011),
+ .ALIGN_PCOMMA_DET("TRUE"),
+ .ALIGN_PCOMMA_VALUE(10'b0101111100),
+ .CBCC_DATA_SOURCE_SEL("DECODED"),
+ .CHAN_BOND_KEEP_ALIGN("TRUE"),
+ .CHAN_BOND_MAX_SKEW(7),
+ .CHAN_BOND_SEQ_1_1(10'b0001001010),
+ .CHAN_BOND_SEQ_1_2(10'b0001001010),
+ .CHAN_BOND_SEQ_1_3(10'b0001001010),
+ .CHAN_BOND_SEQ_1_4(10'b0110111100),
+ .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
+ .CHAN_BOND_SEQ_2_1(10'b0001000101),
+ .CHAN_BOND_SEQ_2_2(10'b0001000101),
+ .CHAN_BOND_SEQ_2_3(10'b0001000101),
+ .CHAN_BOND_SEQ_2_4(10'b0110111100),
+ .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
+ .CHAN_BOND_SEQ_2_USE("TRUE"),
+ .CHAN_BOND_SEQ_LEN(4),
+ .CLK_CORRECT_USE("TRUE"),
+ .CLK_COR_KEEP_IDLE("TRUE"),
+ .CLK_COR_MAX_LAT(20),
+ .CLK_COR_MIN_LAT(18),
+ .CLK_COR_PRECEDENCE("TRUE"),
+ .CLK_COR_REPEAT_WAIT(0),
+ .CLK_COR_SEQ_1_1(10'b0100011100),
+ .CLK_COR_SEQ_1_2(10'b0000000000),
+ .CLK_COR_SEQ_1_3(10'b0000000000),
+ .CLK_COR_SEQ_1_4(10'b0000000000),
+ .CLK_COR_SEQ_1_ENABLE(4'b1111),
+ .CLK_COR_SEQ_2_1(10'b0000000000),
+ .CLK_COR_SEQ_2_2(10'b0000000000),
+ .CLK_COR_SEQ_2_3(10'b0000000000),
+ .CLK_COR_SEQ_2_4(10'b0000000000),
+ .CLK_COR_SEQ_2_ENABLE(4'b0000),
+ .CLK_COR_SEQ_2_USE("FALSE"),
+ .CLK_COR_SEQ_LEN(1),
+ .CPLL_CFG(24'hA407CC),
+ .CPLL_FBDIV(5),
+ .CPLL_FBDIV_45(5),
+ .CPLL_INIT_CFG(24'h00001E),
+ .CPLL_LOCK_CFG(16'h01E8),
+ .CPLL_REFCLK_DIV(1),
+ .DEC_MCOMMA_DETECT("TRUE"),
+ .DEC_PCOMMA_DETECT("TRUE"),
+ .DEC_VALID_COMMA_ONLY("FALSE"),
+ .DMONITOR_CFG(24'h000B01),
+ .ES_CONTROL(6'b000000),
+ .ES_ERRDET_EN("FALSE"),
+ .ES_EYE_SCAN_EN("FALSE"),
+ .ES_HORZ_OFFSET(12'h000),
+ .ES_PMA_CFG(10'b0000000000),
+ .ES_PRESCALE(5'b00000),
+ .ES_QUALIFIER(80'h00000000000000000000),
+ .ES_QUAL_MASK(80'h00000000000000000000),
+ .ES_SDATA_MASK(80'h00000000000000000000),
+ .ES_VERT_OFFSET(9'b000000000),
+ .FTS_DESKEW_SEQ_ENABLE(4'b1111),
+ .FTS_LANE_DESKEW_CFG(4'b1111),
+ .FTS_LANE_DESKEW_EN("TRUE"),
+ .GEARBOX_MODE(3'b000),
+ .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
+ .IS_DRPCLK_INVERTED(1'b0),
+ .IS_GTGREFCLK_INVERTED(1'b0),
+ .IS_RXUSRCLK2_INVERTED(1'b0),
+ .IS_RXUSRCLK_INVERTED(1'b0),
+ .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
+ .IS_TXUSRCLK2_INVERTED(1'b0),
+ .IS_TXUSRCLK_INVERTED(1'b0),
+ .OUTREFCLK_SEL_INV(2'b11),
+ .PCS_PCIE_EN("TRUE"),
+ .PCS_RSVD_ATTR(48'h0000000001CF),
+ .PD_TRANS_TIME_FROM_P2(12'h03C),
+ .PD_TRANS_TIME_NONE_P2(8'h09),
+ .PD_TRANS_TIME_TO_P2(8'h64),
+ .PMA_RSV(32'h00018480),
+ .PMA_RSV2(16'h2050),
+ .PMA_RSV3(2'b00),
+ .PMA_RSV4(32'h00000000),
+ .RXBUFRESET_TIME(5'b00001),
+ .RXBUF_ADDR_MODE("FULL"),
+ .RXBUF_EIDLE_HI_CNT(4'b0100),
+ .RXBUF_EIDLE_LO_CNT(4'b0000),
+ .RXBUF_EN("TRUE"),
+ .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
+ .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
+ .RXBUF_RESET_ON_EIDLE("TRUE"),
+ .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
+ .RXBUF_THRESH_OVFLW(61),
+ .RXBUF_THRESH_OVRD("FALSE"),
+ .RXBUF_THRESH_UNDFLW(4),
+ .RXCDRFREQRESET_TIME(5'b00001),
+ .RXCDRPHRESET_TIME(5'b00001),
+ .RXCDR_CFG(72'h03000023FF10200020),
+ .RXCDR_FR_RESET_ON_EIDLE(1'b0),
+ .RXCDR_HOLD_DURING_EIDLE(1'b1),
+ .RXCDR_LOCK_CFG(6'b010101),
+ .RXCDR_PH_RESET_ON_EIDLE(1'b0),
+ .RXDFELPMRESET_TIME(7'b0001111),
+ .RXDLY_CFG(16'h001F),
+ .RXDLY_LCFG(9'h030),
+ .RXDLY_TAP_CFG(16'h0000),
+ .RXGEARBOX_EN("FALSE"),
+ .RXISCANRESET_TIME(5'b00001),
+ .RXLPM_HF_CFG(14'b00000011110000),
+ .RXLPM_LF_CFG(14'b00000011110000),
+ .RXOOB_CFG(7'b0000110),
+ .RXOUT_DIV(2),
+ .RXPCSRESET_TIME(5'b00001),
+ .RXPHDLY_CFG(24'h004020),
+ .RXPH_CFG(24'h000000),
+ .RXPH_MONITOR_SEL(5'b00000),
+ .RXPMARESET_TIME(5'b00011),
+ .RXPRBS_ERR_LOOPBACK(1'b0),
+ .RXSLIDE_AUTO_WAIT(7),
+ .RXSLIDE_MODE("PMA"),
+ .RX_BIAS_CFG(12'b000000000100),
+ .RX_BUFFER_CFG(6'b000000),
+ .RX_CLK25_DIV(4),
+ .RX_CLKMUX_PD(1'b1),
+ .RX_CM_SEL(2'b11),
+ .RX_CM_TRIM(3'b010),
+ .RX_DATA_WIDTH(20),
+ .RX_DDI_SEL(6'b000000),
+ .RX_DEBUG_CFG(12'b000000000000),
+ .RX_DEFER_RESET_BUF_EN("TRUE"),
+ .RX_DFE_GAIN_CFG(23'h020FEA),
+ .RX_DFE_H2_CFG(12'b000000000000),
+ .RX_DFE_H3_CFG(12'b000001000000),
+ .RX_DFE_H4_CFG(11'b00011110000),
+ .RX_DFE_H5_CFG(11'b00011100000),
+ .RX_DFE_KL_CFG(13'b0000011111110),
+ .RX_DFE_KL_CFG2(32'h3290D86C),
+ .RX_DFE_LPM_CFG(16'h0954),
+ .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1),
+ .RX_DFE_UT_CFG(17'b10001111000000000),
+ .RX_DFE_VP_CFG(17'b00011111100000011),
+ .RX_DFE_XYD_CFG(13'b0000000000000),
+ .RX_DISPERR_SEQ_MATCH("TRUE"),
+ .RX_INT_DATAWIDTH(0),
+ .RX_OS_CFG(13'b0000010000000),
+ .RX_SIG_VALID_DLY(4),
+ .RX_XCLK_SEL("RXREC"),
+ .SAS_MAX_COM(64),
+ .SAS_MIN_COM(36),
+ .SATA_BURST_SEQ_LEN(4'b1111),
+ .SATA_BURST_VAL(3'b100),
+ .SATA_CPLL_CFG("VCO_3000MHZ"),
+ .SATA_EIDLE_VAL(3'b100),
+ .SATA_MAX_BURST(8),
+ .SATA_MAX_INIT(21),
+ .SATA_MAX_WAKE(7),
+ .SATA_MIN_BURST(4),
+ .SATA_MIN_INIT(12),
+ .SATA_MIN_WAKE(4),
+ .SHOW_REALIGN_COMMA("FALSE"),
+ .SIM_CPLLREFCLK_SEL(3'b001),
+ .SIM_RECEIVER_DETECT_PASS("TRUE"),
+ .SIM_RESET_SPEEDUP("FALSE"),
+ .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
+ .SIM_VERSION("3.0"),
+ .TERM_RCAL_CFG(5'b10000),
+ .TERM_RCAL_OVRD(1'b0),
+ .TRANS_TIME_RATE(8'h0E),
+ .TST_RSV(32'h00000000),
+ .TXBUF_EN("FALSE"),
+ .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
+ .TXDLY_CFG(16'h001F),
+ .TXDLY_LCFG(9'h030),
+ .TXDLY_TAP_CFG(16'h0000),
+ .TXGEARBOX_EN("FALSE"),
+ .TXOUT_DIV(2),
+ .TXPCSRESET_TIME(5'b00001),
+ .TXPHDLY_CFG(24'h084020),
+ .TXPH_CFG(16'h0780),
+ .TXPH_MONITOR_SEL(5'b00000),
+ .TXPMARESET_TIME(5'b00011),
+ .TX_CLK25_DIV(4),
+ .TX_CLKMUX_PD(1'b1),
+ .TX_DATA_WIDTH(20),
+ .TX_DEEMPH0(5'b10100),
+ .TX_DEEMPH1(5'b01011),
+ .TX_DRIVE_MODE("PIPE"),
+ .TX_EIDLE_ASSERT_DELAY(3'b010),
+ .TX_EIDLE_DEASSERT_DELAY(3'b100),
+ .TX_INT_DATAWIDTH(0),
+ .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
+ .TX_MAINCURSOR_SEL(1'b0),
+ .TX_MARGIN_FULL_0(7'b1001111),
+ .TX_MARGIN_FULL_1(7'b1001110),
+ .TX_MARGIN_FULL_2(7'b1001101),
+ .TX_MARGIN_FULL_3(7'b1001100),
+ .TX_MARGIN_FULL_4(7'b1000011),
+ .TX_MARGIN_LOW_0(7'b1000101),
+ .TX_MARGIN_LOW_1(7'b1000110),
+ .TX_MARGIN_LOW_2(7'b1000011),
+ .TX_MARGIN_LOW_3(7'b1000010),
+ .TX_MARGIN_LOW_4(7'b1000000),
+ .TX_PREDRIVER_MODE(1'b0),
+ .TX_QPI_STATUS_EN(1'b0),
+ .TX_RXDETECT_CFG(14'h0064),
+ .TX_RXDETECT_REF(3'b011),
+ .TX_XCLK_SEL("TXUSR"),
+ .UCODEER_CLR(1'b0))
+ \gtx_channel.gtxe2_channel_i
+ (.CFGRESET(1'b0),
+ .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}),
+ .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ),
+ .CPLLLOCK(QRST_CPLLLOCK),
+ .CPLLLOCKDETCLK(1'b0),
+ .CPLLLOCKEN(1'b1),
+ .CPLLPD(CPLLPD0_3),
+ .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ),
+ .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
+ .CPLLRESET(CPLLRESET0),
+ .DMONITOROUT({\gtx_channel.gtxe2_channel_i_n_177 ,\gtx_channel.gtxe2_channel_i_n_178 ,\gtx_channel.gtxe2_channel_i_n_179 ,\gtx_channel.gtxe2_channel_i_n_180 ,\gtx_channel.gtxe2_channel_i_n_181 ,\gtx_channel.gtxe2_channel_i_n_182 ,\gtx_channel.gtxe2_channel_i_n_183 ,\gtx_channel.gtxe2_channel_i_n_184 }),
+ .DRPADDR({1'b0,DRPADDR}),
+ .DRPCLK(pipe_dclk_in),
+ .DRPDI(DRPDI),
+ .DRPDO(DRP_DO),
+ .DRPEN(\cplllock_reg1_reg[1] ),
+ .DRPRDY(DRP_RDY),
+ .DRPWE(\cplllock_reg1_reg[1]_0 ),
+ .EYESCANDATAERROR(\gtx_channel.gtxe2_channel_i_n_4 ),
+ .EYESCANMODE(1'b0),
+ .EYESCANRESET(1'b0),
+ .EYESCANTRIGGER(1'b0),
+ .GTGREFCLK(1'b0),
+ .GTNORTHREFCLK0(1'b0),
+ .GTNORTHREFCLK1(1'b0),
+ .GTREFCLK0(sys_clk),
+ .GTREFCLK1(1'b0),
+ .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ),
+ .GTRESETSEL(1'b0),
+ .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .GTRXRESET(DRP_GTXRESET),
+ .GTSOUTHREFCLK0(1'b0),
+ .GTSOUTHREFCLK1(1'b0),
+ .GTTXRESET(DRP_GTXRESET),
+ .GTXRXN(pci_exp_rxn),
+ .GTXRXP(pci_exp_rxp),
+ .GTXTXN(pci_exp_txn),
+ .GTXTXP(pci_exp_txp),
+ .LOOPBACK({1'b0,1'b0,1'b0}),
+ .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
+ .PHYSTATUS(RATE_PHYSTATUS),
+ .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .QPLLCLK(QPLL_QPLLOUTCLK),
+ .QPLLREFCLK(QPLL_QPLLOUTREFCLK),
+ .RESETOVRD(1'b0),
+ .RX8B10BEN(rxchbonden_1),
+ .RXBUFRESET(1'b0),
+ .RXBUFSTATUS({\gtx_channel.gtxe2_channel_i_n_82 ,\gtx_channel.gtxe2_channel_i_n_83 ,\gtx_channel.gtxe2_channel_i_n_84 }),
+ .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ),
+ .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ),
+ .RXCDRFREQRESET(1'b0),
+ .RXCDRHOLD(1'b0),
+ .RXCDRLOCK(gt_rxcdrlock_1),
+ .RXCDROVRDEN(1'b0),
+ .RXCDRRESET(1'b0),
+ .RXCDRRESETRSV(1'b0),
+ .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
+ .RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
+ .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
+ .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }),
+ .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,gt_rx_data_k_wire_filter}),
+ .RXCHBONDEN(rxchbonden_1),
+ .RXCHBONDI(RXCHBONDO),
+ .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
+ .RXCHBONDMASTER(1'b0),
+ .RXCHBONDO({\gtx_channel.gtxe2_channel_i_n_91 ,\gtx_channel.gtxe2_channel_i_n_92 ,\gtx_channel.gtxe2_channel_i_n_93 ,\gtx_channel.gtxe2_channel_i_n_94 ,\gtx_channel.gtxe2_channel_i_n_95 }),
+ .RXCHBONDSLAVE(rxchbonden_1),
+ .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
+ .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ),
+ .RXCOMMADET(\gtx_channel.gtxe2_channel_i_n_16 ),
+ .RXCOMMADETEN(1'b1),
+ .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ),
+ .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
+ .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,gt_rx_data_wire_filter}),
+ .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ),
+ .RXDDIEN(1'b0),
+ .RXDFEAGCHOLD(\cplllock_reg1_reg[1]_1 ),
+ .RXDFEAGCOVRDEN(1'b0),
+ .RXDFECM1EN(1'b0),
+ .RXDFELFHOLD(1'b0),
+ .RXDFELFOVRDEN(1'b1),
+ .RXDFELPMRESET(1'b0),
+ .RXDFETAP2HOLD(1'b0),
+ .RXDFETAP2OVRDEN(1'b0),
+ .RXDFETAP3HOLD(1'b0),
+ .RXDFETAP3OVRDEN(1'b0),
+ .RXDFETAP4HOLD(1'b0),
+ .RXDFETAP4OVRDEN(1'b0),
+ .RXDFETAP5HOLD(1'b0),
+ .RXDFETAP5OVRDEN(1'b0),
+ .RXDFEUTHOLD(1'b0),
+ .RXDFEUTOVRDEN(1'b0),
+ .RXDFEVPHOLD(1'b0),
+ .RXDFEVPOVRDEN(1'b0),
+ .RXDFEVSEN(1'b0),
+ .RXDFEXYDEN(1'b0),
+ .RXDFEXYDHOLD(1'b0),
+ .RXDFEXYDOVRDEN(1'b0),
+ .RXDISPERR({\gtx_channel.gtxe2_channel_i_n_201 ,\gtx_channel.gtxe2_channel_i_n_202 ,\gtx_channel.gtxe2_channel_i_n_203 ,\gtx_channel.gtxe2_channel_i_n_204 ,\gtx_channel.gtxe2_channel_i_n_205 ,\gtx_channel.gtxe2_channel_i_n_206 ,\gtx_channel.gtxe2_channel_i_n_207 ,\gtx_channel.gtxe2_channel_i_n_208 }),
+ .RXDLYBYPASS(1'b1),
+ .RXDLYEN(1'b0),
+ .RXDLYOVRDEN(1'b0),
+ .RXDLYSRESET(1'b0),
+ .RXDLYSRESETDONE(pipe_dclk_in_0),
+ .RXELECIDLE(gt_rx_elec_idle_wire_filter),
+ .RXELECIDLEMODE({1'b0,1'b0}),
+ .RXGEARBOXSLIP(1'b0),
+ .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
+ .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ),
+ .RXLPMEN(rxchbonden_1),
+ .RXLPMHFHOLD(1'b0),
+ .RXLPMHFOVRDEN(1'b0),
+ .RXLPMLFHOLD(1'b0),
+ .RXLPMLFKLOVRDEN(1'b0),
+ .RXMCOMMAALIGNEN(rxchbonden_1),
+ .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]),
+ .RXMONITORSEL({1'b0,1'b0}),
+ .RXNOTINTABLE({\gtx_channel.gtxe2_channel_i_n_209 ,\gtx_channel.gtxe2_channel_i_n_210 ,\gtx_channel.gtxe2_channel_i_n_211 ,\gtx_channel.gtxe2_channel_i_n_212 ,\gtx_channel.gtxe2_channel_i_n_213 ,\gtx_channel.gtxe2_channel_i_n_214 ,\gtx_channel.gtxe2_channel_i_n_215 ,\gtx_channel.gtxe2_channel_i_n_216 }),
+ .RXOOBRESET(1'b0),
+ .RXOSHOLD(1'b0),
+ .RXOSOVRDEN(1'b0),
+ .RXOUTCLK(pipe_rxoutclk_out),
+ .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
+ .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
+ .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
+ .RXPCOMMAALIGNEN(rxchbonden_1),
+ .RXPCSRESET(1'b0),
+ .RXPD(PIPE_POWERDOWN),
+ .RXPHALIGN(1'b0),
+ .RXPHALIGNDONE(pipe_dclk_in_1),
+ .RXPHALIGNEN(1'b0),
+ .RXPHDLYPD(1'b0),
+ .RXPHDLYRESET(1'b0),
+ .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
+ .RXPHOVRDEN(1'b0),
+ .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
+ .RXPMARESET(rate_txpmareset_1),
+ .RXPOLARITY(PIPE_RXPOLARITY),
+ .RXPRBSCNTRESET(1'b0),
+ .RXPRBSERR(\gtx_channel.gtxe2_channel_i_n_27 ),
+ .RXPRBSSEL({1'b0,1'b0,1'b0}),
+ .RXQPIEN(1'b0),
+ .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ),
+ .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ),
+ .RXRATE({1'b0,1'b0,RXRATE}),
+ .RXRATEDONE(RATE_RXRATEDONE),
+ .RXRESETDONE(USER_RXRESETDONE),
+ .RXSLIDE(1'b0),
+ .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ),
+ .RXSTATUS(pipe_dclk_in_5),
+ .RXSYSCLKSEL({1'b0,RXSYSCLKSEL}),
+ .RXUSERRDY(rst_userrdy),
+ .RXUSRCLK(pipe_rxusrclk_in),
+ .RXUSRCLK2(pipe_rxusrclk_in),
+ .RXVALID(gt_rxvalid_1),
+ .SETERRSTATUS(1'b0),
+ .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]),
+ .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .TX8B10BEN(rxchbonden_1),
+ .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
+ .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
+ .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}),
+ .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}),
+ .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ),
+ .TXCOMINIT(1'b0),
+ .TXCOMSAS(1'b0),
+ .TXCOMWAKE(1'b0),
+ .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}),
+ .TXDEEMPH(pipe_tx_deemph_gt),
+ .TXDETECTRX(pipe_tx_rcvr_det_gt),
+ .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
+ .TXDIFFPD(1'b0),
+ .TXDLYBYPASS(1'b0),
+ .TXDLYEN(1'b0),
+ .TXDLYHOLD(1'b0),
+ .TXDLYOVRDEN(1'b0),
+ .TXDLYSRESET(SYNC_TXDLYSRESET),
+ .TXDLYSRESETDONE(pipe_dclk_in_2),
+ .TXDLYUPDOWN(1'b0),
+ .TXELECIDLE(PIPE_TXELECIDLE),
+ .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
+ .TXHEADER({1'b0,1'b0,1'b0}),
+ .TXINHIBIT(1'b0),
+ .TXMAINCURSOR(TXMAINCURSOR),
+ .TXMARGIN(\cplllock_reg1_reg[1]_2 ),
+ .TXOUTCLK(\gtx_channel.gtxe2_channel_i_n_37 ),
+ .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
+ .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
+ .TXOUTCLKSEL({1'b0,1'b0,1'b0}),
+ .TXPCSRESET(1'b0),
+ .TXPD(PIPE_POWERDOWN),
+ .TXPDELECIDLEMODE(1'b0),
+ .TXPHALIGN(SYNC_TXPHALIGN),
+ .TXPHALIGNDONE(pipe_dclk_in_3),
+ .TXPHALIGNEN(1'b1),
+ .TXPHDLYPD(1'b0),
+ .TXPHDLYRESET(1'b0),
+ .TXPHDLYTSTCLK(1'b0),
+ .TXPHINIT(SYNC_TXPHINIT),
+ .TXPHINITDONE(pipe_dclk_in_4),
+ .TXPHOVRDEN(1'b0),
+ .TXPISOPD(1'b0),
+ .TXPMARESET(rate_txpmareset_1),
+ .TXPOLARITY(1'b0),
+ .TXPOSTCURSOR(TXPOSTCURSOR),
+ .TXPOSTCURSORINV(1'b0),
+ .TXPRBSFORCEERR(1'b0),
+ .TXPRBSSEL({1'b0,1'b0,1'b0}),
+ .TXPRECURSOR(TXPRECURSOR),
+ .TXPRECURSORINV(1'b0),
+ .TXQPIBIASEN(1'b0),
+ .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ),
+ .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ),
+ .TXQPISTRONGPDOWN(1'b0),
+ .TXQPIWEAKPUP(1'b0),
+ .TXRATE({1'b0,1'b0,RXRATE}),
+ .TXRATEDONE(RATE_TXRATEDONE),
+ .TXRESETDONE(USER_TXRESETDONE),
+ .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .TXSTARTSEQ(1'b0),
+ .TXSWING(1'b0),
+ .TXSYSCLKSEL({1'b0,RXSYSCLKSEL}),
+ .TXUSERRDY(rst_userrdy),
+ .TXUSRCLK(pipe_pclk_in),
+ .TXUSRCLK2(pipe_pclk_in));
+endmodule
+
+(* ORIG_REF_NAME = "pcie_7x_0_gt_wrapper" *)
+module pcie_7x_0_pcie_7x_0_gt_wrapper_43
+ (cpllpd_1,
+ QRST_CPLLLOCK,
+ DRP_RDY,
+ pci_exp_txn,
+ pci_exp_txp,
+ RATE_PHYSTATUS,
+ gt_rxcdrlock_2,
+ PIPE_RXCHANISALIGNED,
+ pipe_dclk_in_0,
+ gt_rx_elec_idle_wire_filter,
+ pipe_rxoutclk_out,
+ pipe_dclk_in_1,
+ RATE_RXRATEDONE,
+ USER_RXRESETDONE,
+ gt_rxvalid_2,
+ pipe_dclk_in_2,
+ pipe_dclk_in_3,
+ pipe_dclk_in_4,
+ RATE_TXRATEDONE,
+ USER_TXRESETDONE,
+ DRP_DO,
+ pipe_dclk_in_5,
+ gt_rx_data_wire_filter,
+ gt_rx_data_k_wire_filter,
+ gt_cpllpdrefclk,
+ CPLLPD0_4,
+ pipe_dclk_in,
+ \cplllock_reg1_reg[2] ,
+ \cplllock_reg1_reg[2]_0 ,
+ sys_clk,
+ DRP_GTXRESET,
+ pci_exp_rxn,
+ pci_exp_rxp,
+ QPLL_QPLLOUTCLK,
+ QPLL_QPLLOUTREFCLK,
+ rxchbonden_2,
+ \cplllock_reg1_reg[2]_1 ,
+ rate_txpmareset_2,
+ PIPE_RXPOLARITY,
+ rst_userrdy,
+ pipe_rxusrclk_in,
+ pipe_tx_deemph_gt,
+ pipe_tx_rcvr_det_gt,
+ SYNC_TXDLYSRESET,
+ PIPE_TXELECIDLE,
+ SYNC_TXPHALIGN,
+ SYNC_TXPHINIT,
+ pipe_pclk_in,
+ DRPDI,
+ PIPE_POWERDOWN,
+ RXSYSCLKSEL,
+ RXRATE,
+ \cplllock_reg1_reg[2]_2 ,
+ USER_OOBCLK,
+ RXCHBONDO,
+ TXPOSTCURSOR,
+ TXPRECURSOR,
+ PIPE_TXDATA,
+ TXMAINCURSOR,
+ PIPE_TXCOMPLIANCE,
+ PIPE_TXDATAK,
+ DRPADDR,
+ rate_cpllreset_2,
+ RST_CPLLRESET);
+ output cpllpd_1;
+ output [0:0]QRST_CPLLLOCK;
+ output DRP_RDY;
+ output [0:0]pci_exp_txn;
+ output [0:0]pci_exp_txp;
+ output RATE_PHYSTATUS;
+ output gt_rxcdrlock_2;
+ output [0:0]PIPE_RXCHANISALIGNED;
+ output pipe_dclk_in_0;
+ output [0:0]gt_rx_elec_idle_wire_filter;
+ output [0:0]pipe_rxoutclk_out;
+ output pipe_dclk_in_1;
+ output RATE_RXRATEDONE;
+ output USER_RXRESETDONE;
+ output gt_rxvalid_2;
+ output pipe_dclk_in_2;
+ output pipe_dclk_in_3;
+ output pipe_dclk_in_4;
+ output RATE_TXRATEDONE;
+ output USER_TXRESETDONE;
+ output [15:0]DRP_DO;
+ output [2:0]pipe_dclk_in_5;
+ output [15:0]gt_rx_data_wire_filter;
+ output [1:0]gt_rx_data_k_wire_filter;
+ input gt_cpllpdrefclk;
+ input CPLLPD0_4;
+ input pipe_dclk_in;
+ input \cplllock_reg1_reg[2] ;
+ input \cplllock_reg1_reg[2]_0 ;
+ input sys_clk;
+ input DRP_GTXRESET;
+ input [0:0]pci_exp_rxn;
+ input [0:0]pci_exp_rxp;
+ input QPLL_QPLLOUTCLK;
+ input QPLL_QPLLOUTREFCLK;
+ input rxchbonden_2;
+ input \cplllock_reg1_reg[2]_1 ;
+ input rate_txpmareset_2;
+ input [0:0]PIPE_RXPOLARITY;
+ input rst_userrdy;
+ input pipe_rxusrclk_in;
+ input pipe_tx_deemph_gt;
+ input pipe_tx_rcvr_det_gt;
+ input SYNC_TXDLYSRESET;
+ input [0:0]PIPE_TXELECIDLE;
+ input SYNC_TXPHALIGN;
+ input SYNC_TXPHINIT;
+ input pipe_pclk_in;
+ input [15:0]DRPDI;
+ input [1:0]PIPE_POWERDOWN;
+ input [0:0]RXSYSCLKSEL;
+ input [0:0]RXRATE;
+ input [2:0]\cplllock_reg1_reg[2]_2 ;
+ input USER_OOBCLK;
+ input [4:0]RXCHBONDO;
+ input [4:0]TXPOSTCURSOR;
+ input [4:0]TXPRECURSOR;
+ input [15:0]PIPE_TXDATA;
+ input [6:0]TXMAINCURSOR;
+ input [0:0]PIPE_TXCOMPLIANCE;
+ input [1:0]PIPE_TXDATAK;
+ input [7:0]DRPADDR;
+ input rate_cpllreset_2;
+ input RST_CPLLRESET;
+
+ wire CPLLPD0_4;
+ wire CPLLRESET0;
+ wire [7:0]DRPADDR;
+ wire [15:0]DRPDI;
+ wire [15:0]DRP_DO;
+ wire DRP_GTXRESET;
+ wire DRP_RDY;
+ wire [1:0]PIPE_POWERDOWN;
+ wire [0:0]PIPE_RXCHANISALIGNED;
+ wire [0:0]PIPE_RXPOLARITY;
+ wire [0:0]PIPE_TXCOMPLIANCE;
+ wire [15:0]PIPE_TXDATA;
+ wire [1:0]PIPE_TXDATAK;
+ wire [0:0]PIPE_TXELECIDLE;
+ wire QPLL_QPLLOUTCLK;
+ wire QPLL_QPLLOUTREFCLK;
+ wire [0:0]QRST_CPLLLOCK;
+ wire RATE_PHYSTATUS;
+ wire RATE_RXRATEDONE;
+ wire RATE_TXRATEDONE;
+ wire RST_CPLLRESET;
+ wire [4:0]RXCHBONDO;
+ wire [0:0]RXRATE;
+ wire [0:0]RXSYSCLKSEL;
+ wire SYNC_TXDLYSRESET;
+ wire SYNC_TXPHALIGN;
+ wire SYNC_TXPHINIT;
+ wire [6:0]TXMAINCURSOR;
+ wire [4:0]TXPOSTCURSOR;
+ wire [4:0]TXPRECURSOR;
+ wire USER_OOBCLK;
+ wire USER_RXRESETDONE;
+ wire USER_TXRESETDONE;
+ wire \cplllock_reg1_reg[2] ;
+ wire \cplllock_reg1_reg[2]_0 ;
+ wire \cplllock_reg1_reg[2]_1 ;
+ wire [2:0]\cplllock_reg1_reg[2]_2 ;
+ wire cpllpd_1;
+ wire gt_cpllpdrefclk;
+ wire [1:0]gt_rx_data_k_wire_filter;
+ wire [15:0]gt_rx_data_wire_filter;
+ wire [0:0]gt_rx_elec_idle_wire_filter;
+ wire gt_rxcdrlock_2;
+ wire gt_rxvalid_2;
+ wire \gtx_channel.gtxe2_channel_i_n_10 ;
+ wire \gtx_channel.gtxe2_channel_i_n_138 ;
+ wire \gtx_channel.gtxe2_channel_i_n_139 ;
+ wire \gtx_channel.gtxe2_channel_i_n_140 ;
+ wire \gtx_channel.gtxe2_channel_i_n_141 ;
+ wire \gtx_channel.gtxe2_channel_i_n_142 ;
+ wire \gtx_channel.gtxe2_channel_i_n_143 ;
+ wire \gtx_channel.gtxe2_channel_i_n_144 ;
+ wire \gtx_channel.gtxe2_channel_i_n_145 ;
+ wire \gtx_channel.gtxe2_channel_i_n_146 ;
+ wire \gtx_channel.gtxe2_channel_i_n_147 ;
+ wire \gtx_channel.gtxe2_channel_i_n_148 ;
+ wire \gtx_channel.gtxe2_channel_i_n_149 ;
+ wire \gtx_channel.gtxe2_channel_i_n_150 ;
+ wire \gtx_channel.gtxe2_channel_i_n_151 ;
+ wire \gtx_channel.gtxe2_channel_i_n_152 ;
+ wire \gtx_channel.gtxe2_channel_i_n_153 ;
+ wire \gtx_channel.gtxe2_channel_i_n_16 ;
+ wire \gtx_channel.gtxe2_channel_i_n_177 ;
+ wire \gtx_channel.gtxe2_channel_i_n_178 ;
+ wire \gtx_channel.gtxe2_channel_i_n_179 ;
+ wire \gtx_channel.gtxe2_channel_i_n_180 ;
+ wire \gtx_channel.gtxe2_channel_i_n_181 ;
+ wire \gtx_channel.gtxe2_channel_i_n_182 ;
+ wire \gtx_channel.gtxe2_channel_i_n_183 ;
+ wire \gtx_channel.gtxe2_channel_i_n_184 ;
+ wire \gtx_channel.gtxe2_channel_i_n_189 ;
+ wire \gtx_channel.gtxe2_channel_i_n_190 ;
+ wire \gtx_channel.gtxe2_channel_i_n_191 ;
+ wire \gtx_channel.gtxe2_channel_i_n_192 ;
+ wire \gtx_channel.gtxe2_channel_i_n_197 ;
+ wire \gtx_channel.gtxe2_channel_i_n_198 ;
+ wire \gtx_channel.gtxe2_channel_i_n_201 ;
+ wire \gtx_channel.gtxe2_channel_i_n_202 ;
+ wire \gtx_channel.gtxe2_channel_i_n_203 ;
+ wire \gtx_channel.gtxe2_channel_i_n_204 ;
+ wire \gtx_channel.gtxe2_channel_i_n_205 ;
+ wire \gtx_channel.gtxe2_channel_i_n_206 ;
+ wire \gtx_channel.gtxe2_channel_i_n_207 ;
+ wire \gtx_channel.gtxe2_channel_i_n_208 ;
+ wire \gtx_channel.gtxe2_channel_i_n_209 ;
+ wire \gtx_channel.gtxe2_channel_i_n_210 ;
+ wire \gtx_channel.gtxe2_channel_i_n_211 ;
+ wire \gtx_channel.gtxe2_channel_i_n_212 ;
+ wire \gtx_channel.gtxe2_channel_i_n_213 ;
+ wire \gtx_channel.gtxe2_channel_i_n_214 ;
+ wire \gtx_channel.gtxe2_channel_i_n_215 ;
+ wire \gtx_channel.gtxe2_channel_i_n_216 ;
+ wire \gtx_channel.gtxe2_channel_i_n_27 ;
+ wire \gtx_channel.gtxe2_channel_i_n_37 ;
+ wire \gtx_channel.gtxe2_channel_i_n_4 ;
+ wire \gtx_channel.gtxe2_channel_i_n_82 ;
+ wire \gtx_channel.gtxe2_channel_i_n_83 ;
+ wire \gtx_channel.gtxe2_channel_i_n_84 ;
+ wire \gtx_channel.gtxe2_channel_i_n_9 ;
+ wire \gtx_channel.gtxe2_channel_i_n_91 ;
+ wire \gtx_channel.gtxe2_channel_i_n_92 ;
+ wire \gtx_channel.gtxe2_channel_i_n_93 ;
+ wire \gtx_channel.gtxe2_channel_i_n_94 ;
+ wire \gtx_channel.gtxe2_channel_i_n_95 ;
+ wire [0:0]pci_exp_rxn;
+ wire [0:0]pci_exp_rxp;
+ wire [0:0]pci_exp_txn;
+ wire [0:0]pci_exp_txp;
+ wire pipe_dclk_in;
+ wire pipe_dclk_in_0;
+ wire pipe_dclk_in_1;
+ wire pipe_dclk_in_2;
+ wire pipe_dclk_in_3;
+ wire pipe_dclk_in_4;
+ wire [2:0]pipe_dclk_in_5;
+ wire pipe_pclk_in;
+ wire [0:0]pipe_rxoutclk_out;
+ wire pipe_rxusrclk_in;
+ wire pipe_tx_deemph_gt;
+ wire pipe_tx_rcvr_det_gt;
+ wire rate_cpllreset_2;
+ wire rate_txpmareset_2;
+ wire rst_userrdy;
+ wire rxchbonden_2;
+ wire sys_clk;
+ wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ;
+ wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
+ wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ;
+ wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ;
+ wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
+ wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ;
+ wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ;
+ wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ;
+ wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ;
+ wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
+ wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ;
+ wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ;
+
+ pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_56 cpllPDInst
+ (.CPLLRESET0(CPLLRESET0),
+ .RST_CPLLRESET(RST_CPLLRESET),
+ .cpllpd_1(cpllpd_1),
+ .gt_cpllpdrefclk(gt_cpllpdrefclk),
+ .rate_cpllreset_2(rate_cpllreset_2));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ GTXE2_CHANNEL #(
+ .ALIGN_COMMA_DOUBLE("FALSE"),
+ .ALIGN_COMMA_ENABLE(10'b1111111111),
+ .ALIGN_COMMA_WORD(1),
+ .ALIGN_MCOMMA_DET("TRUE"),
+ .ALIGN_MCOMMA_VALUE(10'b1010000011),
+ .ALIGN_PCOMMA_DET("TRUE"),
+ .ALIGN_PCOMMA_VALUE(10'b0101111100),
+ .CBCC_DATA_SOURCE_SEL("DECODED"),
+ .CHAN_BOND_KEEP_ALIGN("TRUE"),
+ .CHAN_BOND_MAX_SKEW(7),
+ .CHAN_BOND_SEQ_1_1(10'b0001001010),
+ .CHAN_BOND_SEQ_1_2(10'b0001001010),
+ .CHAN_BOND_SEQ_1_3(10'b0001001010),
+ .CHAN_BOND_SEQ_1_4(10'b0110111100),
+ .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
+ .CHAN_BOND_SEQ_2_1(10'b0001000101),
+ .CHAN_BOND_SEQ_2_2(10'b0001000101),
+ .CHAN_BOND_SEQ_2_3(10'b0001000101),
+ .CHAN_BOND_SEQ_2_4(10'b0110111100),
+ .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
+ .CHAN_BOND_SEQ_2_USE("TRUE"),
+ .CHAN_BOND_SEQ_LEN(4),
+ .CLK_CORRECT_USE("TRUE"),
+ .CLK_COR_KEEP_IDLE("TRUE"),
+ .CLK_COR_MAX_LAT(20),
+ .CLK_COR_MIN_LAT(18),
+ .CLK_COR_PRECEDENCE("TRUE"),
+ .CLK_COR_REPEAT_WAIT(0),
+ .CLK_COR_SEQ_1_1(10'b0100011100),
+ .CLK_COR_SEQ_1_2(10'b0000000000),
+ .CLK_COR_SEQ_1_3(10'b0000000000),
+ .CLK_COR_SEQ_1_4(10'b0000000000),
+ .CLK_COR_SEQ_1_ENABLE(4'b1111),
+ .CLK_COR_SEQ_2_1(10'b0000000000),
+ .CLK_COR_SEQ_2_2(10'b0000000000),
+ .CLK_COR_SEQ_2_3(10'b0000000000),
+ .CLK_COR_SEQ_2_4(10'b0000000000),
+ .CLK_COR_SEQ_2_ENABLE(4'b0000),
+ .CLK_COR_SEQ_2_USE("FALSE"),
+ .CLK_COR_SEQ_LEN(1),
+ .CPLL_CFG(24'hA407CC),
+ .CPLL_FBDIV(5),
+ .CPLL_FBDIV_45(5),
+ .CPLL_INIT_CFG(24'h00001E),
+ .CPLL_LOCK_CFG(16'h01E8),
+ .CPLL_REFCLK_DIV(1),
+ .DEC_MCOMMA_DETECT("TRUE"),
+ .DEC_PCOMMA_DETECT("TRUE"),
+ .DEC_VALID_COMMA_ONLY("FALSE"),
+ .DMONITOR_CFG(24'h000B01),
+ .ES_CONTROL(6'b000000),
+ .ES_ERRDET_EN("FALSE"),
+ .ES_EYE_SCAN_EN("FALSE"),
+ .ES_HORZ_OFFSET(12'h000),
+ .ES_PMA_CFG(10'b0000000000),
+ .ES_PRESCALE(5'b00000),
+ .ES_QUALIFIER(80'h00000000000000000000),
+ .ES_QUAL_MASK(80'h00000000000000000000),
+ .ES_SDATA_MASK(80'h00000000000000000000),
+ .ES_VERT_OFFSET(9'b000000000),
+ .FTS_DESKEW_SEQ_ENABLE(4'b1111),
+ .FTS_LANE_DESKEW_CFG(4'b1111),
+ .FTS_LANE_DESKEW_EN("TRUE"),
+ .GEARBOX_MODE(3'b000),
+ .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
+ .IS_DRPCLK_INVERTED(1'b0),
+ .IS_GTGREFCLK_INVERTED(1'b0),
+ .IS_RXUSRCLK2_INVERTED(1'b0),
+ .IS_RXUSRCLK_INVERTED(1'b0),
+ .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
+ .IS_TXUSRCLK2_INVERTED(1'b0),
+ .IS_TXUSRCLK_INVERTED(1'b0),
+ .OUTREFCLK_SEL_INV(2'b11),
+ .PCS_PCIE_EN("TRUE"),
+ .PCS_RSVD_ATTR(48'h0000000001CF),
+ .PD_TRANS_TIME_FROM_P2(12'h03C),
+ .PD_TRANS_TIME_NONE_P2(8'h09),
+ .PD_TRANS_TIME_TO_P2(8'h64),
+ .PMA_RSV(32'h00018480),
+ .PMA_RSV2(16'h2050),
+ .PMA_RSV3(2'b00),
+ .PMA_RSV4(32'h00000000),
+ .RXBUFRESET_TIME(5'b00001),
+ .RXBUF_ADDR_MODE("FULL"),
+ .RXBUF_EIDLE_HI_CNT(4'b0100),
+ .RXBUF_EIDLE_LO_CNT(4'b0000),
+ .RXBUF_EN("TRUE"),
+ .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
+ .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
+ .RXBUF_RESET_ON_EIDLE("TRUE"),
+ .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
+ .RXBUF_THRESH_OVFLW(61),
+ .RXBUF_THRESH_OVRD("FALSE"),
+ .RXBUF_THRESH_UNDFLW(4),
+ .RXCDRFREQRESET_TIME(5'b00001),
+ .RXCDRPHRESET_TIME(5'b00001),
+ .RXCDR_CFG(72'h03000023FF10200020),
+ .RXCDR_FR_RESET_ON_EIDLE(1'b0),
+ .RXCDR_HOLD_DURING_EIDLE(1'b1),
+ .RXCDR_LOCK_CFG(6'b010101),
+ .RXCDR_PH_RESET_ON_EIDLE(1'b0),
+ .RXDFELPMRESET_TIME(7'b0001111),
+ .RXDLY_CFG(16'h001F),
+ .RXDLY_LCFG(9'h030),
+ .RXDLY_TAP_CFG(16'h0000),
+ .RXGEARBOX_EN("FALSE"),
+ .RXISCANRESET_TIME(5'b00001),
+ .RXLPM_HF_CFG(14'b00000011110000),
+ .RXLPM_LF_CFG(14'b00000011110000),
+ .RXOOB_CFG(7'b0000110),
+ .RXOUT_DIV(2),
+ .RXPCSRESET_TIME(5'b00001),
+ .RXPHDLY_CFG(24'h004020),
+ .RXPH_CFG(24'h000000),
+ .RXPH_MONITOR_SEL(5'b00000),
+ .RXPMARESET_TIME(5'b00011),
+ .RXPRBS_ERR_LOOPBACK(1'b0),
+ .RXSLIDE_AUTO_WAIT(7),
+ .RXSLIDE_MODE("PMA"),
+ .RX_BIAS_CFG(12'b000000000100),
+ .RX_BUFFER_CFG(6'b000000),
+ .RX_CLK25_DIV(4),
+ .RX_CLKMUX_PD(1'b1),
+ .RX_CM_SEL(2'b11),
+ .RX_CM_TRIM(3'b010),
+ .RX_DATA_WIDTH(20),
+ .RX_DDI_SEL(6'b000000),
+ .RX_DEBUG_CFG(12'b000000000000),
+ .RX_DEFER_RESET_BUF_EN("TRUE"),
+ .RX_DFE_GAIN_CFG(23'h020FEA),
+ .RX_DFE_H2_CFG(12'b000000000000),
+ .RX_DFE_H3_CFG(12'b000001000000),
+ .RX_DFE_H4_CFG(11'b00011110000),
+ .RX_DFE_H5_CFG(11'b00011100000),
+ .RX_DFE_KL_CFG(13'b0000011111110),
+ .RX_DFE_KL_CFG2(32'h3290D86C),
+ .RX_DFE_LPM_CFG(16'h0954),
+ .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1),
+ .RX_DFE_UT_CFG(17'b10001111000000000),
+ .RX_DFE_VP_CFG(17'b00011111100000011),
+ .RX_DFE_XYD_CFG(13'b0000000000000),
+ .RX_DISPERR_SEQ_MATCH("TRUE"),
+ .RX_INT_DATAWIDTH(0),
+ .RX_OS_CFG(13'b0000010000000),
+ .RX_SIG_VALID_DLY(4),
+ .RX_XCLK_SEL("RXREC"),
+ .SAS_MAX_COM(64),
+ .SAS_MIN_COM(36),
+ .SATA_BURST_SEQ_LEN(4'b1111),
+ .SATA_BURST_VAL(3'b100),
+ .SATA_CPLL_CFG("VCO_3000MHZ"),
+ .SATA_EIDLE_VAL(3'b100),
+ .SATA_MAX_BURST(8),
+ .SATA_MAX_INIT(21),
+ .SATA_MAX_WAKE(7),
+ .SATA_MIN_BURST(4),
+ .SATA_MIN_INIT(12),
+ .SATA_MIN_WAKE(4),
+ .SHOW_REALIGN_COMMA("FALSE"),
+ .SIM_CPLLREFCLK_SEL(3'b001),
+ .SIM_RECEIVER_DETECT_PASS("TRUE"),
+ .SIM_RESET_SPEEDUP("FALSE"),
+ .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
+ .SIM_VERSION("3.0"),
+ .TERM_RCAL_CFG(5'b10000),
+ .TERM_RCAL_OVRD(1'b0),
+ .TRANS_TIME_RATE(8'h0E),
+ .TST_RSV(32'h00000000),
+ .TXBUF_EN("FALSE"),
+ .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
+ .TXDLY_CFG(16'h001F),
+ .TXDLY_LCFG(9'h030),
+ .TXDLY_TAP_CFG(16'h0000),
+ .TXGEARBOX_EN("FALSE"),
+ .TXOUT_DIV(2),
+ .TXPCSRESET_TIME(5'b00001),
+ .TXPHDLY_CFG(24'h084020),
+ .TXPH_CFG(16'h0780),
+ .TXPH_MONITOR_SEL(5'b00000),
+ .TXPMARESET_TIME(5'b00011),
+ .TX_CLK25_DIV(4),
+ .TX_CLKMUX_PD(1'b1),
+ .TX_DATA_WIDTH(20),
+ .TX_DEEMPH0(5'b10100),
+ .TX_DEEMPH1(5'b01011),
+ .TX_DRIVE_MODE("PIPE"),
+ .TX_EIDLE_ASSERT_DELAY(3'b010),
+ .TX_EIDLE_DEASSERT_DELAY(3'b100),
+ .TX_INT_DATAWIDTH(0),
+ .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
+ .TX_MAINCURSOR_SEL(1'b0),
+ .TX_MARGIN_FULL_0(7'b1001111),
+ .TX_MARGIN_FULL_1(7'b1001110),
+ .TX_MARGIN_FULL_2(7'b1001101),
+ .TX_MARGIN_FULL_3(7'b1001100),
+ .TX_MARGIN_FULL_4(7'b1000011),
+ .TX_MARGIN_LOW_0(7'b1000101),
+ .TX_MARGIN_LOW_1(7'b1000110),
+ .TX_MARGIN_LOW_2(7'b1000011),
+ .TX_MARGIN_LOW_3(7'b1000010),
+ .TX_MARGIN_LOW_4(7'b1000000),
+ .TX_PREDRIVER_MODE(1'b0),
+ .TX_QPI_STATUS_EN(1'b0),
+ .TX_RXDETECT_CFG(14'h0064),
+ .TX_RXDETECT_REF(3'b011),
+ .TX_XCLK_SEL("TXUSR"),
+ .UCODEER_CLR(1'b0))
+ \gtx_channel.gtxe2_channel_i
+ (.CFGRESET(1'b0),
+ .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}),
+ .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ),
+ .CPLLLOCK(QRST_CPLLLOCK),
+ .CPLLLOCKDETCLK(1'b0),
+ .CPLLLOCKEN(1'b1),
+ .CPLLPD(CPLLPD0_4),
+ .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ),
+ .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
+ .CPLLRESET(CPLLRESET0),
+ .DMONITOROUT({\gtx_channel.gtxe2_channel_i_n_177 ,\gtx_channel.gtxe2_channel_i_n_178 ,\gtx_channel.gtxe2_channel_i_n_179 ,\gtx_channel.gtxe2_channel_i_n_180 ,\gtx_channel.gtxe2_channel_i_n_181 ,\gtx_channel.gtxe2_channel_i_n_182 ,\gtx_channel.gtxe2_channel_i_n_183 ,\gtx_channel.gtxe2_channel_i_n_184 }),
+ .DRPADDR({1'b0,DRPADDR}),
+ .DRPCLK(pipe_dclk_in),
+ .DRPDI(DRPDI),
+ .DRPDO(DRP_DO),
+ .DRPEN(\cplllock_reg1_reg[2] ),
+ .DRPRDY(DRP_RDY),
+ .DRPWE(\cplllock_reg1_reg[2]_0 ),
+ .EYESCANDATAERROR(\gtx_channel.gtxe2_channel_i_n_4 ),
+ .EYESCANMODE(1'b0),
+ .EYESCANRESET(1'b0),
+ .EYESCANTRIGGER(1'b0),
+ .GTGREFCLK(1'b0),
+ .GTNORTHREFCLK0(1'b0),
+ .GTNORTHREFCLK1(1'b0),
+ .GTREFCLK0(sys_clk),
+ .GTREFCLK1(1'b0),
+ .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ),
+ .GTRESETSEL(1'b0),
+ .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .GTRXRESET(DRP_GTXRESET),
+ .GTSOUTHREFCLK0(1'b0),
+ .GTSOUTHREFCLK1(1'b0),
+ .GTTXRESET(DRP_GTXRESET),
+ .GTXRXN(pci_exp_rxn),
+ .GTXRXP(pci_exp_rxp),
+ .GTXTXN(pci_exp_txn),
+ .GTXTXP(pci_exp_txp),
+ .LOOPBACK({1'b0,1'b0,1'b0}),
+ .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
+ .PHYSTATUS(RATE_PHYSTATUS),
+ .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .QPLLCLK(QPLL_QPLLOUTCLK),
+ .QPLLREFCLK(QPLL_QPLLOUTREFCLK),
+ .RESETOVRD(1'b0),
+ .RX8B10BEN(rxchbonden_2),
+ .RXBUFRESET(1'b0),
+ .RXBUFSTATUS({\gtx_channel.gtxe2_channel_i_n_82 ,\gtx_channel.gtxe2_channel_i_n_83 ,\gtx_channel.gtxe2_channel_i_n_84 }),
+ .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ),
+ .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ),
+ .RXCDRFREQRESET(1'b0),
+ .RXCDRHOLD(1'b0),
+ .RXCDRLOCK(gt_rxcdrlock_2),
+ .RXCDROVRDEN(1'b0),
+ .RXCDRRESET(1'b0),
+ .RXCDRRESETRSV(1'b0),
+ .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
+ .RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
+ .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
+ .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }),
+ .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,gt_rx_data_k_wire_filter}),
+ .RXCHBONDEN(rxchbonden_2),
+ .RXCHBONDI(RXCHBONDO),
+ .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
+ .RXCHBONDMASTER(1'b0),
+ .RXCHBONDO({\gtx_channel.gtxe2_channel_i_n_91 ,\gtx_channel.gtxe2_channel_i_n_92 ,\gtx_channel.gtxe2_channel_i_n_93 ,\gtx_channel.gtxe2_channel_i_n_94 ,\gtx_channel.gtxe2_channel_i_n_95 }),
+ .RXCHBONDSLAVE(rxchbonden_2),
+ .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
+ .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ),
+ .RXCOMMADET(\gtx_channel.gtxe2_channel_i_n_16 ),
+ .RXCOMMADETEN(1'b1),
+ .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ),
+ .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
+ .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,gt_rx_data_wire_filter}),
+ .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ),
+ .RXDDIEN(1'b0),
+ .RXDFEAGCHOLD(\cplllock_reg1_reg[2]_1 ),
+ .RXDFEAGCOVRDEN(1'b0),
+ .RXDFECM1EN(1'b0),
+ .RXDFELFHOLD(1'b0),
+ .RXDFELFOVRDEN(1'b1),
+ .RXDFELPMRESET(1'b0),
+ .RXDFETAP2HOLD(1'b0),
+ .RXDFETAP2OVRDEN(1'b0),
+ .RXDFETAP3HOLD(1'b0),
+ .RXDFETAP3OVRDEN(1'b0),
+ .RXDFETAP4HOLD(1'b0),
+ .RXDFETAP4OVRDEN(1'b0),
+ .RXDFETAP5HOLD(1'b0),
+ .RXDFETAP5OVRDEN(1'b0),
+ .RXDFEUTHOLD(1'b0),
+ .RXDFEUTOVRDEN(1'b0),
+ .RXDFEVPHOLD(1'b0),
+ .RXDFEVPOVRDEN(1'b0),
+ .RXDFEVSEN(1'b0),
+ .RXDFEXYDEN(1'b0),
+ .RXDFEXYDHOLD(1'b0),
+ .RXDFEXYDOVRDEN(1'b0),
+ .RXDISPERR({\gtx_channel.gtxe2_channel_i_n_201 ,\gtx_channel.gtxe2_channel_i_n_202 ,\gtx_channel.gtxe2_channel_i_n_203 ,\gtx_channel.gtxe2_channel_i_n_204 ,\gtx_channel.gtxe2_channel_i_n_205 ,\gtx_channel.gtxe2_channel_i_n_206 ,\gtx_channel.gtxe2_channel_i_n_207 ,\gtx_channel.gtxe2_channel_i_n_208 }),
+ .RXDLYBYPASS(1'b1),
+ .RXDLYEN(1'b0),
+ .RXDLYOVRDEN(1'b0),
+ .RXDLYSRESET(1'b0),
+ .RXDLYSRESETDONE(pipe_dclk_in_0),
+ .RXELECIDLE(gt_rx_elec_idle_wire_filter),
+ .RXELECIDLEMODE({1'b0,1'b0}),
+ .RXGEARBOXSLIP(1'b0),
+ .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
+ .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ),
+ .RXLPMEN(rxchbonden_2),
+ .RXLPMHFHOLD(1'b0),
+ .RXLPMHFOVRDEN(1'b0),
+ .RXLPMLFHOLD(1'b0),
+ .RXLPMLFKLOVRDEN(1'b0),
+ .RXMCOMMAALIGNEN(rxchbonden_2),
+ .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]),
+ .RXMONITORSEL({1'b0,1'b0}),
+ .RXNOTINTABLE({\gtx_channel.gtxe2_channel_i_n_209 ,\gtx_channel.gtxe2_channel_i_n_210 ,\gtx_channel.gtxe2_channel_i_n_211 ,\gtx_channel.gtxe2_channel_i_n_212 ,\gtx_channel.gtxe2_channel_i_n_213 ,\gtx_channel.gtxe2_channel_i_n_214 ,\gtx_channel.gtxe2_channel_i_n_215 ,\gtx_channel.gtxe2_channel_i_n_216 }),
+ .RXOOBRESET(1'b0),
+ .RXOSHOLD(1'b0),
+ .RXOSOVRDEN(1'b0),
+ .RXOUTCLK(pipe_rxoutclk_out),
+ .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
+ .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
+ .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
+ .RXPCOMMAALIGNEN(rxchbonden_2),
+ .RXPCSRESET(1'b0),
+ .RXPD(PIPE_POWERDOWN),
+ .RXPHALIGN(1'b0),
+ .RXPHALIGNDONE(pipe_dclk_in_1),
+ .RXPHALIGNEN(1'b0),
+ .RXPHDLYPD(1'b0),
+ .RXPHDLYRESET(1'b0),
+ .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
+ .RXPHOVRDEN(1'b0),
+ .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
+ .RXPMARESET(rate_txpmareset_2),
+ .RXPOLARITY(PIPE_RXPOLARITY),
+ .RXPRBSCNTRESET(1'b0),
+ .RXPRBSERR(\gtx_channel.gtxe2_channel_i_n_27 ),
+ .RXPRBSSEL({1'b0,1'b0,1'b0}),
+ .RXQPIEN(1'b0),
+ .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ),
+ .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ),
+ .RXRATE({1'b0,1'b0,RXRATE}),
+ .RXRATEDONE(RATE_RXRATEDONE),
+ .RXRESETDONE(USER_RXRESETDONE),
+ .RXSLIDE(1'b0),
+ .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ),
+ .RXSTATUS(pipe_dclk_in_5),
+ .RXSYSCLKSEL({1'b0,RXSYSCLKSEL}),
+ .RXUSERRDY(rst_userrdy),
+ .RXUSRCLK(pipe_rxusrclk_in),
+ .RXUSRCLK2(pipe_rxusrclk_in),
+ .RXVALID(gt_rxvalid_2),
+ .SETERRSTATUS(1'b0),
+ .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]),
+ .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .TX8B10BEN(rxchbonden_2),
+ .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
+ .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
+ .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}),
+ .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}),
+ .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ),
+ .TXCOMINIT(1'b0),
+ .TXCOMSAS(1'b0),
+ .TXCOMWAKE(1'b0),
+ .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}),
+ .TXDEEMPH(pipe_tx_deemph_gt),
+ .TXDETECTRX(pipe_tx_rcvr_det_gt),
+ .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
+ .TXDIFFPD(1'b0),
+ .TXDLYBYPASS(1'b0),
+ .TXDLYEN(1'b0),
+ .TXDLYHOLD(1'b0),
+ .TXDLYOVRDEN(1'b0),
+ .TXDLYSRESET(SYNC_TXDLYSRESET),
+ .TXDLYSRESETDONE(pipe_dclk_in_2),
+ .TXDLYUPDOWN(1'b0),
+ .TXELECIDLE(PIPE_TXELECIDLE),
+ .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
+ .TXHEADER({1'b0,1'b0,1'b0}),
+ .TXINHIBIT(1'b0),
+ .TXMAINCURSOR(TXMAINCURSOR),
+ .TXMARGIN(\cplllock_reg1_reg[2]_2 ),
+ .TXOUTCLK(\gtx_channel.gtxe2_channel_i_n_37 ),
+ .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
+ .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
+ .TXOUTCLKSEL({1'b0,1'b0,1'b0}),
+ .TXPCSRESET(1'b0),
+ .TXPD(PIPE_POWERDOWN),
+ .TXPDELECIDLEMODE(1'b0),
+ .TXPHALIGN(SYNC_TXPHALIGN),
+ .TXPHALIGNDONE(pipe_dclk_in_3),
+ .TXPHALIGNEN(1'b1),
+ .TXPHDLYPD(1'b0),
+ .TXPHDLYRESET(1'b0),
+ .TXPHDLYTSTCLK(1'b0),
+ .TXPHINIT(SYNC_TXPHINIT),
+ .TXPHINITDONE(pipe_dclk_in_4),
+ .TXPHOVRDEN(1'b0),
+ .TXPISOPD(1'b0),
+ .TXPMARESET(rate_txpmareset_2),
+ .TXPOLARITY(1'b0),
+ .TXPOSTCURSOR(TXPOSTCURSOR),
+ .TXPOSTCURSORINV(1'b0),
+ .TXPRBSFORCEERR(1'b0),
+ .TXPRBSSEL({1'b0,1'b0,1'b0}),
+ .TXPRECURSOR(TXPRECURSOR),
+ .TXPRECURSORINV(1'b0),
+ .TXQPIBIASEN(1'b0),
+ .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ),
+ .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ),
+ .TXQPISTRONGPDOWN(1'b0),
+ .TXQPIWEAKPUP(1'b0),
+ .TXRATE({1'b0,1'b0,RXRATE}),
+ .TXRATEDONE(RATE_TXRATEDONE),
+ .TXRESETDONE(USER_TXRESETDONE),
+ .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .TXSTARTSEQ(1'b0),
+ .TXSWING(1'b0),
+ .TXSYSCLKSEL({1'b0,RXSYSCLKSEL}),
+ .TXUSERRDY(rst_userrdy),
+ .TXUSRCLK(pipe_pclk_in),
+ .TXUSRCLK2(pipe_pclk_in));
+endmodule
+
+(* ORIG_REF_NAME = "pcie_7x_0_gt_wrapper" *)
+module pcie_7x_0_pcie_7x_0_gt_wrapper_49
+ (cpllpd_2,
+ QRST_CPLLLOCK,
+ DRP_RDY,
+ pci_exp_txn,
+ pci_exp_txp,
+ RATE_PHYSTATUS,
+ gt_rxcdrlock_3,
+ PIPE_RXCHANISALIGNED,
+ pipe_dclk_in_0,
+ gt_rx_elec_idle_wire_filter,
+ pipe_rxoutclk_out,
+ pipe_dclk_in_1,
+ RATE_RXRATEDONE,
+ USER_RXRESETDONE,
+ gt_rxvalid_3,
+ pipe_dclk_in_2,
+ pipe_dclk_in_3,
+ pipe_dclk_in_4,
+ RATE_TXRATEDONE,
+ USER_TXRESETDONE,
+ DRP_DO,
+ pipe_dclk_in_5,
+ gt_rx_data_wire_filter,
+ gt_rx_data_k_wire_filter,
+ gt_cpllpdrefclk,
+ CPLLPD0_5,
+ pipe_dclk_in,
+ \cplllock_reg1_reg[3] ,
+ \cplllock_reg1_reg[3]_0 ,
+ sys_clk,
+ DRP_GTXRESET,
+ pci_exp_rxn,
+ pci_exp_rxp,
+ QPLL_QPLLOUTCLK,
+ QPLL_QPLLOUTREFCLK,
+ rxchbonden_3,
+ \cplllock_reg1_reg[3]_1 ,
+ rate_txpmareset_3,
+ PIPE_RXPOLARITY,
+ rst_userrdy,
+ pipe_rxusrclk_in,
+ pipe_tx_deemph_gt,
+ pipe_tx_rcvr_det_gt,
+ SYNC_TXDLYSRESET,
+ PIPE_TXELECIDLE,
+ SYNC_TXPHALIGN,
+ SYNC_TXPHINIT,
+ pipe_pclk_in,
+ DRPDI,
+ PIPE_POWERDOWN,
+ RXSYSCLKSEL,
+ RXRATE,
+ \cplllock_reg1_reg[3]_2 ,
+ USER_OOBCLK,
+ RXCHBONDO,
+ TXPOSTCURSOR,
+ TXPRECURSOR,
+ PIPE_TXDATA,
+ TXMAINCURSOR,
+ PIPE_TXCOMPLIANCE,
+ PIPE_TXDATAK,
+ DRPADDR,
+ rate_cpllreset_3,
+ RST_CPLLRESET);
+ output cpllpd_2;
+ output [0:0]QRST_CPLLLOCK;
+ output DRP_RDY;
+ output [0:0]pci_exp_txn;
+ output [0:0]pci_exp_txp;
+ output RATE_PHYSTATUS;
+ output gt_rxcdrlock_3;
+ output [0:0]PIPE_RXCHANISALIGNED;
+ output pipe_dclk_in_0;
+ output [0:0]gt_rx_elec_idle_wire_filter;
+ output [0:0]pipe_rxoutclk_out;
+ output pipe_dclk_in_1;
+ output RATE_RXRATEDONE;
+ output USER_RXRESETDONE;
+ output gt_rxvalid_3;
+ output pipe_dclk_in_2;
+ output pipe_dclk_in_3;
+ output pipe_dclk_in_4;
+ output RATE_TXRATEDONE;
+ output USER_TXRESETDONE;
+ output [15:0]DRP_DO;
+ output [2:0]pipe_dclk_in_5;
+ output [15:0]gt_rx_data_wire_filter;
+ output [1:0]gt_rx_data_k_wire_filter;
+ input gt_cpllpdrefclk;
+ input CPLLPD0_5;
+ input pipe_dclk_in;
+ input \cplllock_reg1_reg[3] ;
+ input \cplllock_reg1_reg[3]_0 ;
+ input sys_clk;
+ input DRP_GTXRESET;
+ input [0:0]pci_exp_rxn;
+ input [0:0]pci_exp_rxp;
+ input QPLL_QPLLOUTCLK;
+ input QPLL_QPLLOUTREFCLK;
+ input rxchbonden_3;
+ input \cplllock_reg1_reg[3]_1 ;
+ input rate_txpmareset_3;
+ input [0:0]PIPE_RXPOLARITY;
+ input rst_userrdy;
+ input pipe_rxusrclk_in;
+ input pipe_tx_deemph_gt;
+ input pipe_tx_rcvr_det_gt;
+ input SYNC_TXDLYSRESET;
+ input [0:0]PIPE_TXELECIDLE;
+ input SYNC_TXPHALIGN;
+ input SYNC_TXPHINIT;
+ input pipe_pclk_in;
+ input [15:0]DRPDI;
+ input [1:0]PIPE_POWERDOWN;
+ input [0:0]RXSYSCLKSEL;
+ input [0:0]RXRATE;
+ input [2:0]\cplllock_reg1_reg[3]_2 ;
+ input USER_OOBCLK;
+ input [4:0]RXCHBONDO;
+ input [4:0]TXPOSTCURSOR;
+ input [4:0]TXPRECURSOR;
+ input [15:0]PIPE_TXDATA;
+ input [6:0]TXMAINCURSOR;
+ input [0:0]PIPE_TXCOMPLIANCE;
+ input [1:0]PIPE_TXDATAK;
+ input [7:0]DRPADDR;
+ input rate_cpllreset_3;
+ input RST_CPLLRESET;
+
+ wire CPLLPD0_5;
+ wire CPLLRESET0;
+ wire [7:0]DRPADDR;
+ wire [15:0]DRPDI;
+ wire [15:0]DRP_DO;
+ wire DRP_GTXRESET;
+ wire DRP_RDY;
+ wire [1:0]PIPE_POWERDOWN;
+ wire [0:0]PIPE_RXCHANISALIGNED;
+ wire [0:0]PIPE_RXPOLARITY;
+ wire [0:0]PIPE_TXCOMPLIANCE;
+ wire [15:0]PIPE_TXDATA;
+ wire [1:0]PIPE_TXDATAK;
+ wire [0:0]PIPE_TXELECIDLE;
+ wire QPLL_QPLLOUTCLK;
+ wire QPLL_QPLLOUTREFCLK;
+ wire [0:0]QRST_CPLLLOCK;
+ wire RATE_PHYSTATUS;
+ wire RATE_RXRATEDONE;
+ wire RATE_TXRATEDONE;
+ wire RST_CPLLRESET;
+ wire [4:0]RXCHBONDO;
+ wire [0:0]RXRATE;
+ wire [0:0]RXSYSCLKSEL;
+ wire SYNC_TXDLYSRESET;
+ wire SYNC_TXPHALIGN;
+ wire SYNC_TXPHINIT;
+ wire [6:0]TXMAINCURSOR;
+ wire [4:0]TXPOSTCURSOR;
+ wire [4:0]TXPRECURSOR;
+ wire USER_OOBCLK;
+ wire USER_RXRESETDONE;
+ wire USER_TXRESETDONE;
+ wire \cplllock_reg1_reg[3] ;
+ wire \cplllock_reg1_reg[3]_0 ;
+ wire \cplllock_reg1_reg[3]_1 ;
+ wire [2:0]\cplllock_reg1_reg[3]_2 ;
+ wire cpllpd_2;
+ wire gt_cpllpdrefclk;
+ wire [1:0]gt_rx_data_k_wire_filter;
+ wire [15:0]gt_rx_data_wire_filter;
+ wire [0:0]gt_rx_elec_idle_wire_filter;
+ wire gt_rxcdrlock_3;
+ wire gt_rxvalid_3;
+ wire \gtx_channel.gtxe2_channel_i_n_10 ;
+ wire \gtx_channel.gtxe2_channel_i_n_138 ;
+ wire \gtx_channel.gtxe2_channel_i_n_139 ;
+ wire \gtx_channel.gtxe2_channel_i_n_140 ;
+ wire \gtx_channel.gtxe2_channel_i_n_141 ;
+ wire \gtx_channel.gtxe2_channel_i_n_142 ;
+ wire \gtx_channel.gtxe2_channel_i_n_143 ;
+ wire \gtx_channel.gtxe2_channel_i_n_144 ;
+ wire \gtx_channel.gtxe2_channel_i_n_145 ;
+ wire \gtx_channel.gtxe2_channel_i_n_146 ;
+ wire \gtx_channel.gtxe2_channel_i_n_147 ;
+ wire \gtx_channel.gtxe2_channel_i_n_148 ;
+ wire \gtx_channel.gtxe2_channel_i_n_149 ;
+ wire \gtx_channel.gtxe2_channel_i_n_150 ;
+ wire \gtx_channel.gtxe2_channel_i_n_151 ;
+ wire \gtx_channel.gtxe2_channel_i_n_152 ;
+ wire \gtx_channel.gtxe2_channel_i_n_153 ;
+ wire \gtx_channel.gtxe2_channel_i_n_16 ;
+ wire \gtx_channel.gtxe2_channel_i_n_177 ;
+ wire \gtx_channel.gtxe2_channel_i_n_178 ;
+ wire \gtx_channel.gtxe2_channel_i_n_179 ;
+ wire \gtx_channel.gtxe2_channel_i_n_180 ;
+ wire \gtx_channel.gtxe2_channel_i_n_181 ;
+ wire \gtx_channel.gtxe2_channel_i_n_182 ;
+ wire \gtx_channel.gtxe2_channel_i_n_183 ;
+ wire \gtx_channel.gtxe2_channel_i_n_184 ;
+ wire \gtx_channel.gtxe2_channel_i_n_189 ;
+ wire \gtx_channel.gtxe2_channel_i_n_190 ;
+ wire \gtx_channel.gtxe2_channel_i_n_191 ;
+ wire \gtx_channel.gtxe2_channel_i_n_192 ;
+ wire \gtx_channel.gtxe2_channel_i_n_197 ;
+ wire \gtx_channel.gtxe2_channel_i_n_198 ;
+ wire \gtx_channel.gtxe2_channel_i_n_201 ;
+ wire \gtx_channel.gtxe2_channel_i_n_202 ;
+ wire \gtx_channel.gtxe2_channel_i_n_203 ;
+ wire \gtx_channel.gtxe2_channel_i_n_204 ;
+ wire \gtx_channel.gtxe2_channel_i_n_205 ;
+ wire \gtx_channel.gtxe2_channel_i_n_206 ;
+ wire \gtx_channel.gtxe2_channel_i_n_207 ;
+ wire \gtx_channel.gtxe2_channel_i_n_208 ;
+ wire \gtx_channel.gtxe2_channel_i_n_209 ;
+ wire \gtx_channel.gtxe2_channel_i_n_210 ;
+ wire \gtx_channel.gtxe2_channel_i_n_211 ;
+ wire \gtx_channel.gtxe2_channel_i_n_212 ;
+ wire \gtx_channel.gtxe2_channel_i_n_213 ;
+ wire \gtx_channel.gtxe2_channel_i_n_214 ;
+ wire \gtx_channel.gtxe2_channel_i_n_215 ;
+ wire \gtx_channel.gtxe2_channel_i_n_216 ;
+ wire \gtx_channel.gtxe2_channel_i_n_27 ;
+ wire \gtx_channel.gtxe2_channel_i_n_37 ;
+ wire \gtx_channel.gtxe2_channel_i_n_4 ;
+ wire \gtx_channel.gtxe2_channel_i_n_82 ;
+ wire \gtx_channel.gtxe2_channel_i_n_83 ;
+ wire \gtx_channel.gtxe2_channel_i_n_84 ;
+ wire \gtx_channel.gtxe2_channel_i_n_9 ;
+ wire \gtx_channel.gtxe2_channel_i_n_91 ;
+ wire \gtx_channel.gtxe2_channel_i_n_92 ;
+ wire \gtx_channel.gtxe2_channel_i_n_93 ;
+ wire \gtx_channel.gtxe2_channel_i_n_94 ;
+ wire \gtx_channel.gtxe2_channel_i_n_95 ;
+ wire [0:0]pci_exp_rxn;
+ wire [0:0]pci_exp_rxp;
+ wire [0:0]pci_exp_txn;
+ wire [0:0]pci_exp_txp;
+ wire pipe_dclk_in;
+ wire pipe_dclk_in_0;
+ wire pipe_dclk_in_1;
+ wire pipe_dclk_in_2;
+ wire pipe_dclk_in_3;
+ wire pipe_dclk_in_4;
+ wire [2:0]pipe_dclk_in_5;
+ wire pipe_pclk_in;
+ wire [0:0]pipe_rxoutclk_out;
+ wire pipe_rxusrclk_in;
+ wire pipe_tx_deemph_gt;
+ wire pipe_tx_rcvr_det_gt;
+ wire rate_cpllreset_3;
+ wire rate_txpmareset_3;
+ wire rst_userrdy;
+ wire rxchbonden_3;
+ wire sys_clk;
+ wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ;
+ wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ;
+ wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
+ wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ;
+ wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ;
+ wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
+ wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ;
+ wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ;
+ wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ;
+ wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ;
+ wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
+ wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ;
+ wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ;
+
+ pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd cpllPDInst
+ (.CPLLRESET0(CPLLRESET0),
+ .RST_CPLLRESET(RST_CPLLRESET),
+ .cpllpd_2(cpllpd_2),
+ .gt_cpllpdrefclk(gt_cpllpdrefclk),
+ .rate_cpllreset_3(rate_cpllreset_3));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ GTXE2_CHANNEL #(
+ .ALIGN_COMMA_DOUBLE("FALSE"),
+ .ALIGN_COMMA_ENABLE(10'b1111111111),
+ .ALIGN_COMMA_WORD(1),
+ .ALIGN_MCOMMA_DET("TRUE"),
+ .ALIGN_MCOMMA_VALUE(10'b1010000011),
+ .ALIGN_PCOMMA_DET("TRUE"),
+ .ALIGN_PCOMMA_VALUE(10'b0101111100),
+ .CBCC_DATA_SOURCE_SEL("DECODED"),
+ .CHAN_BOND_KEEP_ALIGN("TRUE"),
+ .CHAN_BOND_MAX_SKEW(7),
+ .CHAN_BOND_SEQ_1_1(10'b0001001010),
+ .CHAN_BOND_SEQ_1_2(10'b0001001010),
+ .CHAN_BOND_SEQ_1_3(10'b0001001010),
+ .CHAN_BOND_SEQ_1_4(10'b0110111100),
+ .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
+ .CHAN_BOND_SEQ_2_1(10'b0001000101),
+ .CHAN_BOND_SEQ_2_2(10'b0001000101),
+ .CHAN_BOND_SEQ_2_3(10'b0001000101),
+ .CHAN_BOND_SEQ_2_4(10'b0110111100),
+ .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
+ .CHAN_BOND_SEQ_2_USE("TRUE"),
+ .CHAN_BOND_SEQ_LEN(4),
+ .CLK_CORRECT_USE("TRUE"),
+ .CLK_COR_KEEP_IDLE("TRUE"),
+ .CLK_COR_MAX_LAT(20),
+ .CLK_COR_MIN_LAT(18),
+ .CLK_COR_PRECEDENCE("TRUE"),
+ .CLK_COR_REPEAT_WAIT(0),
+ .CLK_COR_SEQ_1_1(10'b0100011100),
+ .CLK_COR_SEQ_1_2(10'b0000000000),
+ .CLK_COR_SEQ_1_3(10'b0000000000),
+ .CLK_COR_SEQ_1_4(10'b0000000000),
+ .CLK_COR_SEQ_1_ENABLE(4'b1111),
+ .CLK_COR_SEQ_2_1(10'b0000000000),
+ .CLK_COR_SEQ_2_2(10'b0000000000),
+ .CLK_COR_SEQ_2_3(10'b0000000000),
+ .CLK_COR_SEQ_2_4(10'b0000000000),
+ .CLK_COR_SEQ_2_ENABLE(4'b0000),
+ .CLK_COR_SEQ_2_USE("FALSE"),
+ .CLK_COR_SEQ_LEN(1),
+ .CPLL_CFG(24'hA407CC),
+ .CPLL_FBDIV(5),
+ .CPLL_FBDIV_45(5),
+ .CPLL_INIT_CFG(24'h00001E),
+ .CPLL_LOCK_CFG(16'h01E8),
+ .CPLL_REFCLK_DIV(1),
+ .DEC_MCOMMA_DETECT("TRUE"),
+ .DEC_PCOMMA_DETECT("TRUE"),
+ .DEC_VALID_COMMA_ONLY("FALSE"),
+ .DMONITOR_CFG(24'h000B01),
+ .ES_CONTROL(6'b000000),
+ .ES_ERRDET_EN("FALSE"),
+ .ES_EYE_SCAN_EN("FALSE"),
+ .ES_HORZ_OFFSET(12'h000),
+ .ES_PMA_CFG(10'b0000000000),
+ .ES_PRESCALE(5'b00000),
+ .ES_QUALIFIER(80'h00000000000000000000),
+ .ES_QUAL_MASK(80'h00000000000000000000),
+ .ES_SDATA_MASK(80'h00000000000000000000),
+ .ES_VERT_OFFSET(9'b000000000),
+ .FTS_DESKEW_SEQ_ENABLE(4'b1111),
+ .FTS_LANE_DESKEW_CFG(4'b1111),
+ .FTS_LANE_DESKEW_EN("TRUE"),
+ .GEARBOX_MODE(3'b000),
+ .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
+ .IS_DRPCLK_INVERTED(1'b0),
+ .IS_GTGREFCLK_INVERTED(1'b0),
+ .IS_RXUSRCLK2_INVERTED(1'b0),
+ .IS_RXUSRCLK_INVERTED(1'b0),
+ .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
+ .IS_TXUSRCLK2_INVERTED(1'b0),
+ .IS_TXUSRCLK_INVERTED(1'b0),
+ .OUTREFCLK_SEL_INV(2'b11),
+ .PCS_PCIE_EN("TRUE"),
+ .PCS_RSVD_ATTR(48'h0000000001CF),
+ .PD_TRANS_TIME_FROM_P2(12'h03C),
+ .PD_TRANS_TIME_NONE_P2(8'h09),
+ .PD_TRANS_TIME_TO_P2(8'h64),
+ .PMA_RSV(32'h00018480),
+ .PMA_RSV2(16'h2050),
+ .PMA_RSV3(2'b00),
+ .PMA_RSV4(32'h00000000),
+ .RXBUFRESET_TIME(5'b00001),
+ .RXBUF_ADDR_MODE("FULL"),
+ .RXBUF_EIDLE_HI_CNT(4'b0100),
+ .RXBUF_EIDLE_LO_CNT(4'b0000),
+ .RXBUF_EN("TRUE"),
+ .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
+ .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
+ .RXBUF_RESET_ON_EIDLE("TRUE"),
+ .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
+ .RXBUF_THRESH_OVFLW(61),
+ .RXBUF_THRESH_OVRD("FALSE"),
+ .RXBUF_THRESH_UNDFLW(4),
+ .RXCDRFREQRESET_TIME(5'b00001),
+ .RXCDRPHRESET_TIME(5'b00001),
+ .RXCDR_CFG(72'h03000023FF10200020),
+ .RXCDR_FR_RESET_ON_EIDLE(1'b0),
+ .RXCDR_HOLD_DURING_EIDLE(1'b1),
+ .RXCDR_LOCK_CFG(6'b010101),
+ .RXCDR_PH_RESET_ON_EIDLE(1'b0),
+ .RXDFELPMRESET_TIME(7'b0001111),
+ .RXDLY_CFG(16'h001F),
+ .RXDLY_LCFG(9'h030),
+ .RXDLY_TAP_CFG(16'h0000),
+ .RXGEARBOX_EN("FALSE"),
+ .RXISCANRESET_TIME(5'b00001),
+ .RXLPM_HF_CFG(14'b00000011110000),
+ .RXLPM_LF_CFG(14'b00000011110000),
+ .RXOOB_CFG(7'b0000110),
+ .RXOUT_DIV(2),
+ .RXPCSRESET_TIME(5'b00001),
+ .RXPHDLY_CFG(24'h004020),
+ .RXPH_CFG(24'h000000),
+ .RXPH_MONITOR_SEL(5'b00000),
+ .RXPMARESET_TIME(5'b00011),
+ .RXPRBS_ERR_LOOPBACK(1'b0),
+ .RXSLIDE_AUTO_WAIT(7),
+ .RXSLIDE_MODE("PMA"),
+ .RX_BIAS_CFG(12'b000000000100),
+ .RX_BUFFER_CFG(6'b000000),
+ .RX_CLK25_DIV(4),
+ .RX_CLKMUX_PD(1'b1),
+ .RX_CM_SEL(2'b11),
+ .RX_CM_TRIM(3'b010),
+ .RX_DATA_WIDTH(20),
+ .RX_DDI_SEL(6'b000000),
+ .RX_DEBUG_CFG(12'b000000000000),
+ .RX_DEFER_RESET_BUF_EN("TRUE"),
+ .RX_DFE_GAIN_CFG(23'h020FEA),
+ .RX_DFE_H2_CFG(12'b000000000000),
+ .RX_DFE_H3_CFG(12'b000001000000),
+ .RX_DFE_H4_CFG(11'b00011110000),
+ .RX_DFE_H5_CFG(11'b00011100000),
+ .RX_DFE_KL_CFG(13'b0000011111110),
+ .RX_DFE_KL_CFG2(32'h3290D86C),
+ .RX_DFE_LPM_CFG(16'h0954),
+ .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1),
+ .RX_DFE_UT_CFG(17'b10001111000000000),
+ .RX_DFE_VP_CFG(17'b00011111100000011),
+ .RX_DFE_XYD_CFG(13'b0000000000000),
+ .RX_DISPERR_SEQ_MATCH("TRUE"),
+ .RX_INT_DATAWIDTH(0),
+ .RX_OS_CFG(13'b0000010000000),
+ .RX_SIG_VALID_DLY(4),
+ .RX_XCLK_SEL("RXREC"),
+ .SAS_MAX_COM(64),
+ .SAS_MIN_COM(36),
+ .SATA_BURST_SEQ_LEN(4'b1111),
+ .SATA_BURST_VAL(3'b100),
+ .SATA_CPLL_CFG("VCO_3000MHZ"),
+ .SATA_EIDLE_VAL(3'b100),
+ .SATA_MAX_BURST(8),
+ .SATA_MAX_INIT(21),
+ .SATA_MAX_WAKE(7),
+ .SATA_MIN_BURST(4),
+ .SATA_MIN_INIT(12),
+ .SATA_MIN_WAKE(4),
+ .SHOW_REALIGN_COMMA("FALSE"),
+ .SIM_CPLLREFCLK_SEL(3'b001),
+ .SIM_RECEIVER_DETECT_PASS("TRUE"),
+ .SIM_RESET_SPEEDUP("FALSE"),
+ .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
+ .SIM_VERSION("3.0"),
+ .TERM_RCAL_CFG(5'b10000),
+ .TERM_RCAL_OVRD(1'b0),
+ .TRANS_TIME_RATE(8'h0E),
+ .TST_RSV(32'h00000000),
+ .TXBUF_EN("FALSE"),
+ .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
+ .TXDLY_CFG(16'h001F),
+ .TXDLY_LCFG(9'h030),
+ .TXDLY_TAP_CFG(16'h0000),
+ .TXGEARBOX_EN("FALSE"),
+ .TXOUT_DIV(2),
+ .TXPCSRESET_TIME(5'b00001),
+ .TXPHDLY_CFG(24'h084020),
+ .TXPH_CFG(16'h0780),
+ .TXPH_MONITOR_SEL(5'b00000),
+ .TXPMARESET_TIME(5'b00011),
+ .TX_CLK25_DIV(4),
+ .TX_CLKMUX_PD(1'b1),
+ .TX_DATA_WIDTH(20),
+ .TX_DEEMPH0(5'b10100),
+ .TX_DEEMPH1(5'b01011),
+ .TX_DRIVE_MODE("PIPE"),
+ .TX_EIDLE_ASSERT_DELAY(3'b010),
+ .TX_EIDLE_DEASSERT_DELAY(3'b100),
+ .TX_INT_DATAWIDTH(0),
+ .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
+ .TX_MAINCURSOR_SEL(1'b0),
+ .TX_MARGIN_FULL_0(7'b1001111),
+ .TX_MARGIN_FULL_1(7'b1001110),
+ .TX_MARGIN_FULL_2(7'b1001101),
+ .TX_MARGIN_FULL_3(7'b1001100),
+ .TX_MARGIN_FULL_4(7'b1000011),
+ .TX_MARGIN_LOW_0(7'b1000101),
+ .TX_MARGIN_LOW_1(7'b1000110),
+ .TX_MARGIN_LOW_2(7'b1000011),
+ .TX_MARGIN_LOW_3(7'b1000010),
+ .TX_MARGIN_LOW_4(7'b1000000),
+ .TX_PREDRIVER_MODE(1'b0),
+ .TX_QPI_STATUS_EN(1'b0),
+ .TX_RXDETECT_CFG(14'h0064),
+ .TX_RXDETECT_REF(3'b011),
+ .TX_XCLK_SEL("TXUSR"),
+ .UCODEER_CLR(1'b0))
+ \gtx_channel.gtxe2_channel_i
+ (.CFGRESET(1'b0),
+ .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}),
+ .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ),
+ .CPLLLOCK(QRST_CPLLLOCK),
+ .CPLLLOCKDETCLK(1'b0),
+ .CPLLLOCKEN(1'b1),
+ .CPLLPD(CPLLPD0_5),
+ .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ),
+ .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
+ .CPLLRESET(CPLLRESET0),
+ .DMONITOROUT({\gtx_channel.gtxe2_channel_i_n_177 ,\gtx_channel.gtxe2_channel_i_n_178 ,\gtx_channel.gtxe2_channel_i_n_179 ,\gtx_channel.gtxe2_channel_i_n_180 ,\gtx_channel.gtxe2_channel_i_n_181 ,\gtx_channel.gtxe2_channel_i_n_182 ,\gtx_channel.gtxe2_channel_i_n_183 ,\gtx_channel.gtxe2_channel_i_n_184 }),
+ .DRPADDR({1'b0,DRPADDR}),
+ .DRPCLK(pipe_dclk_in),
+ .DRPDI(DRPDI),
+ .DRPDO(DRP_DO),
+ .DRPEN(\cplllock_reg1_reg[3] ),
+ .DRPRDY(DRP_RDY),
+ .DRPWE(\cplllock_reg1_reg[3]_0 ),
+ .EYESCANDATAERROR(\gtx_channel.gtxe2_channel_i_n_4 ),
+ .EYESCANMODE(1'b0),
+ .EYESCANRESET(1'b0),
+ .EYESCANTRIGGER(1'b0),
+ .GTGREFCLK(1'b0),
+ .GTNORTHREFCLK0(1'b0),
+ .GTNORTHREFCLK1(1'b0),
+ .GTREFCLK0(sys_clk),
+ .GTREFCLK1(1'b0),
+ .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ),
+ .GTRESETSEL(1'b0),
+ .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .GTRXRESET(DRP_GTXRESET),
+ .GTSOUTHREFCLK0(1'b0),
+ .GTSOUTHREFCLK1(1'b0),
+ .GTTXRESET(DRP_GTXRESET),
+ .GTXRXN(pci_exp_rxn),
+ .GTXRXP(pci_exp_rxp),
+ .GTXTXN(pci_exp_txn),
+ .GTXTXP(pci_exp_txp),
+ .LOOPBACK({1'b0,1'b0,1'b0}),
+ .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
+ .PHYSTATUS(RATE_PHYSTATUS),
+ .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .QPLLCLK(QPLL_QPLLOUTCLK),
+ .QPLLREFCLK(QPLL_QPLLOUTREFCLK),
+ .RESETOVRD(1'b0),
+ .RX8B10BEN(rxchbonden_3),
+ .RXBUFRESET(1'b0),
+ .RXBUFSTATUS({\gtx_channel.gtxe2_channel_i_n_82 ,\gtx_channel.gtxe2_channel_i_n_83 ,\gtx_channel.gtxe2_channel_i_n_84 }),
+ .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ),
+ .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ),
+ .RXCDRFREQRESET(1'b0),
+ .RXCDRHOLD(1'b0),
+ .RXCDRLOCK(gt_rxcdrlock_3),
+ .RXCDROVRDEN(1'b0),
+ .RXCDRRESET(1'b0),
+ .RXCDRRESETRSV(1'b0),
+ .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
+ .RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
+ .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
+ .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }),
+ .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,gt_rx_data_k_wire_filter}),
+ .RXCHBONDEN(rxchbonden_3),
+ .RXCHBONDI(RXCHBONDO),
+ .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
+ .RXCHBONDMASTER(1'b0),
+ .RXCHBONDO({\gtx_channel.gtxe2_channel_i_n_91 ,\gtx_channel.gtxe2_channel_i_n_92 ,\gtx_channel.gtxe2_channel_i_n_93 ,\gtx_channel.gtxe2_channel_i_n_94 ,\gtx_channel.gtxe2_channel_i_n_95 }),
+ .RXCHBONDSLAVE(rxchbonden_3),
+ .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
+ .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ),
+ .RXCOMMADET(\gtx_channel.gtxe2_channel_i_n_16 ),
+ .RXCOMMADETEN(1'b1),
+ .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ),
+ .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
+ .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,gt_rx_data_wire_filter}),
+ .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ),
+ .RXDDIEN(1'b0),
+ .RXDFEAGCHOLD(\cplllock_reg1_reg[3]_1 ),
+ .RXDFEAGCOVRDEN(1'b0),
+ .RXDFECM1EN(1'b0),
+ .RXDFELFHOLD(1'b0),
+ .RXDFELFOVRDEN(1'b1),
+ .RXDFELPMRESET(1'b0),
+ .RXDFETAP2HOLD(1'b0),
+ .RXDFETAP2OVRDEN(1'b0),
+ .RXDFETAP3HOLD(1'b0),
+ .RXDFETAP3OVRDEN(1'b0),
+ .RXDFETAP4HOLD(1'b0),
+ .RXDFETAP4OVRDEN(1'b0),
+ .RXDFETAP5HOLD(1'b0),
+ .RXDFETAP5OVRDEN(1'b0),
+ .RXDFEUTHOLD(1'b0),
+ .RXDFEUTOVRDEN(1'b0),
+ .RXDFEVPHOLD(1'b0),
+ .RXDFEVPOVRDEN(1'b0),
+ .RXDFEVSEN(1'b0),
+ .RXDFEXYDEN(1'b0),
+ .RXDFEXYDHOLD(1'b0),
+ .RXDFEXYDOVRDEN(1'b0),
+ .RXDISPERR({\gtx_channel.gtxe2_channel_i_n_201 ,\gtx_channel.gtxe2_channel_i_n_202 ,\gtx_channel.gtxe2_channel_i_n_203 ,\gtx_channel.gtxe2_channel_i_n_204 ,\gtx_channel.gtxe2_channel_i_n_205 ,\gtx_channel.gtxe2_channel_i_n_206 ,\gtx_channel.gtxe2_channel_i_n_207 ,\gtx_channel.gtxe2_channel_i_n_208 }),
+ .RXDLYBYPASS(1'b1),
+ .RXDLYEN(1'b0),
+ .RXDLYOVRDEN(1'b0),
+ .RXDLYSRESET(1'b0),
+ .RXDLYSRESETDONE(pipe_dclk_in_0),
+ .RXELECIDLE(gt_rx_elec_idle_wire_filter),
+ .RXELECIDLEMODE({1'b0,1'b0}),
+ .RXGEARBOXSLIP(1'b0),
+ .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
+ .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ),
+ .RXLPMEN(rxchbonden_3),
+ .RXLPMHFHOLD(1'b0),
+ .RXLPMHFOVRDEN(1'b0),
+ .RXLPMLFHOLD(1'b0),
+ .RXLPMLFKLOVRDEN(1'b0),
+ .RXMCOMMAALIGNEN(rxchbonden_3),
+ .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]),
+ .RXMONITORSEL({1'b0,1'b0}),
+ .RXNOTINTABLE({\gtx_channel.gtxe2_channel_i_n_209 ,\gtx_channel.gtxe2_channel_i_n_210 ,\gtx_channel.gtxe2_channel_i_n_211 ,\gtx_channel.gtxe2_channel_i_n_212 ,\gtx_channel.gtxe2_channel_i_n_213 ,\gtx_channel.gtxe2_channel_i_n_214 ,\gtx_channel.gtxe2_channel_i_n_215 ,\gtx_channel.gtxe2_channel_i_n_216 }),
+ .RXOOBRESET(1'b0),
+ .RXOSHOLD(1'b0),
+ .RXOSOVRDEN(1'b0),
+ .RXOUTCLK(pipe_rxoutclk_out),
+ .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
+ .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
+ .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
+ .RXPCOMMAALIGNEN(rxchbonden_3),
+ .RXPCSRESET(1'b0),
+ .RXPD(PIPE_POWERDOWN),
+ .RXPHALIGN(1'b0),
+ .RXPHALIGNDONE(pipe_dclk_in_1),
+ .RXPHALIGNEN(1'b0),
+ .RXPHDLYPD(1'b0),
+ .RXPHDLYRESET(1'b0),
+ .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
+ .RXPHOVRDEN(1'b0),
+ .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
+ .RXPMARESET(rate_txpmareset_3),
+ .RXPOLARITY(PIPE_RXPOLARITY),
+ .RXPRBSCNTRESET(1'b0),
+ .RXPRBSERR(\gtx_channel.gtxe2_channel_i_n_27 ),
+ .RXPRBSSEL({1'b0,1'b0,1'b0}),
+ .RXQPIEN(1'b0),
+ .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ),
+ .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ),
+ .RXRATE({1'b0,1'b0,RXRATE}),
+ .RXRATEDONE(RATE_RXRATEDONE),
+ .RXRESETDONE(USER_RXRESETDONE),
+ .RXSLIDE(1'b0),
+ .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ),
+ .RXSTATUS(pipe_dclk_in_5),
+ .RXSYSCLKSEL({1'b0,RXSYSCLKSEL}),
+ .RXUSERRDY(rst_userrdy),
+ .RXUSRCLK(pipe_rxusrclk_in),
+ .RXUSRCLK2(pipe_rxusrclk_in),
+ .RXVALID(gt_rxvalid_3),
+ .SETERRSTATUS(1'b0),
+ .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]),
+ .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .TX8B10BEN(rxchbonden_3),
+ .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
+ .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
+ .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}),
+ .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}),
+ .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ),
+ .TXCOMINIT(1'b0),
+ .TXCOMSAS(1'b0),
+ .TXCOMWAKE(1'b0),
+ .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}),
+ .TXDEEMPH(pipe_tx_deemph_gt),
+ .TXDETECTRX(pipe_tx_rcvr_det_gt),
+ .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
+ .TXDIFFPD(1'b0),
+ .TXDLYBYPASS(1'b0),
+ .TXDLYEN(1'b0),
+ .TXDLYHOLD(1'b0),
+ .TXDLYOVRDEN(1'b0),
+ .TXDLYSRESET(SYNC_TXDLYSRESET),
+ .TXDLYSRESETDONE(pipe_dclk_in_2),
+ .TXDLYUPDOWN(1'b0),
+ .TXELECIDLE(PIPE_TXELECIDLE),
+ .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
+ .TXHEADER({1'b0,1'b0,1'b0}),
+ .TXINHIBIT(1'b0),
+ .TXMAINCURSOR(TXMAINCURSOR),
+ .TXMARGIN(\cplllock_reg1_reg[3]_2 ),
+ .TXOUTCLK(\gtx_channel.gtxe2_channel_i_n_37 ),
+ .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
+ .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
+ .TXOUTCLKSEL({1'b0,1'b0,1'b0}),
+ .TXPCSRESET(1'b0),
+ .TXPD(PIPE_POWERDOWN),
+ .TXPDELECIDLEMODE(1'b0),
+ .TXPHALIGN(SYNC_TXPHALIGN),
+ .TXPHALIGNDONE(pipe_dclk_in_3),
+ .TXPHALIGNEN(1'b1),
+ .TXPHDLYPD(1'b0),
+ .TXPHDLYRESET(1'b0),
+ .TXPHDLYTSTCLK(1'b0),
+ .TXPHINIT(SYNC_TXPHINIT),
+ .TXPHINITDONE(pipe_dclk_in_4),
+ .TXPHOVRDEN(1'b0),
+ .TXPISOPD(1'b0),
+ .TXPMARESET(rate_txpmareset_3),
+ .TXPOLARITY(1'b0),
+ .TXPOSTCURSOR(TXPOSTCURSOR),
+ .TXPOSTCURSORINV(1'b0),
+ .TXPRBSFORCEERR(1'b0),
+ .TXPRBSSEL({1'b0,1'b0,1'b0}),
+ .TXPRECURSOR(TXPRECURSOR),
+ .TXPRECURSORINV(1'b0),
+ .TXQPIBIASEN(1'b0),
+ .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ),
+ .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ),
+ .TXQPISTRONGPDOWN(1'b0),
+ .TXQPIWEAKPUP(1'b0),
+ .TXRATE({1'b0,1'b0,RXRATE}),
+ .TXRATEDONE(RATE_TXRATEDONE),
+ .TXRESETDONE(USER_TXRESETDONE),
+ .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .TXSTARTSEQ(1'b0),
+ .TXSWING(1'b0),
+ .TXSYSCLKSEL({1'b0,RXSYSCLKSEL}),
+ .TXUSERRDY(rst_userrdy),
+ .TXUSRCLK(pipe_pclk_in),
+ .TXUSRCLK2(pipe_pclk_in));
+endmodule
+
+module pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd
+ (cpllpd_2,
+ CPLLRESET0,
+ gt_cpllpdrefclk,
+ rate_cpllreset_3,
+ RST_CPLLRESET);
+ output cpllpd_2;
+ output CPLLRESET0;
+ input gt_cpllpdrefclk;
+ input rate_cpllreset_3;
+ input RST_CPLLRESET;
+
+ wire CPLLRESET0;
+ wire RST_CPLLRESET;
+ wire cpllpd_2;
+ wire \cpllpd_wait_reg[31]_srl32_n_1 ;
+ wire \cpllpd_wait_reg[63]_srl32_n_1 ;
+ wire \cpllpd_wait_reg[94]_srl31_n_0 ;
+ wire \cpllreset_wait_reg[126]_srl31_n_0 ;
+ wire \cpllreset_wait_reg[31]_srl32_n_1 ;
+ wire \cpllreset_wait_reg[63]_srl32_n_1 ;
+ wire \cpllreset_wait_reg[95]_srl32_n_1 ;
+ wire cpllrst;
+ wire gt_cpllpdrefclk;
+ wire rate_cpllreset_3;
+ wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;
+
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'hFFFFFFFF))
+ \cpllpd_wait_reg[31]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(1'b0),
+ .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'hFFFFFFFF))
+ \cpllpd_wait_reg[63]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
+ .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *)
+ SRLC32E #(
+ .INIT(32'h7FFFFFFF))
+ \cpllpd_wait_reg[94]_srl31
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
+ .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
+ .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
+ (* equivalent_register_removal = "no" *)
+ FDRE #(
+ .INIT(1'b1))
+ \cpllpd_wait_reg[95]
+ (.C(gt_cpllpdrefclk),
+ .CE(1'b1),
+ .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
+ .Q(cpllpd_2),
+ .R(1'b0));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \cpllreset_wait_reg[126]_srl31
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
+ .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
+ .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
+ (* equivalent_register_removal = "no" *)
+ FDRE #(
+ .INIT(1'b0))
+ \cpllreset_wait_reg[127]
+ (.C(gt_cpllpdrefclk),
+ .CE(1'b1),
+ .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
+ .Q(cpllrst),
+ .R(1'b0));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h000000FF))
+ \cpllreset_wait_reg[31]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(1'b0),
+ .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \cpllreset_wait_reg[63]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
+ .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \cpllreset_wait_reg[95]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
+ .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
+ LUT3 #(
+ .INIT(8'hFE))
+ \gtx_channel.gtxe2_channel_i_i_2__2
+ (.I0(cpllrst),
+ .I1(rate_cpllreset_3),
+ .I2(RST_CPLLRESET),
+ .O(CPLLRESET0));
+endmodule
+
+(* ORIG_REF_NAME = "pcie_7x_0_gtx_cpllpd_ovrd" *)
+module pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_56
+ (cpllpd_1,
+ CPLLRESET0,
+ gt_cpllpdrefclk,
+ rate_cpllreset_2,
+ RST_CPLLRESET);
+ output cpllpd_1;
+ output CPLLRESET0;
+ input gt_cpllpdrefclk;
+ input rate_cpllreset_2;
+ input RST_CPLLRESET;
+
+ wire CPLLRESET0;
+ wire RST_CPLLRESET;
+ wire cpllpd_1;
+ wire \cpllpd_wait_reg[31]_srl32_n_1 ;
+ wire \cpllpd_wait_reg[63]_srl32_n_1 ;
+ wire \cpllpd_wait_reg[94]_srl31_n_0 ;
+ wire \cpllreset_wait_reg[126]_srl31_n_0 ;
+ wire \cpllreset_wait_reg[31]_srl32_n_1 ;
+ wire \cpllreset_wait_reg[63]_srl32_n_1 ;
+ wire \cpllreset_wait_reg[95]_srl32_n_1 ;
+ wire cpllrst;
+ wire gt_cpllpdrefclk;
+ wire rate_cpllreset_2;
+ wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;
+
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'hFFFFFFFF))
+ \cpllpd_wait_reg[31]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(1'b0),
+ .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'hFFFFFFFF))
+ \cpllpd_wait_reg[63]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
+ .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *)
+ SRLC32E #(
+ .INIT(32'h7FFFFFFF))
+ \cpllpd_wait_reg[94]_srl31
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
+ .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
+ .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
+ (* equivalent_register_removal = "no" *)
+ FDRE #(
+ .INIT(1'b1))
+ \cpllpd_wait_reg[95]
+ (.C(gt_cpllpdrefclk),
+ .CE(1'b1),
+ .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
+ .Q(cpllpd_1),
+ .R(1'b0));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \cpllreset_wait_reg[126]_srl31
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
+ .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
+ .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
+ (* equivalent_register_removal = "no" *)
+ FDRE #(
+ .INIT(1'b0))
+ \cpllreset_wait_reg[127]
+ (.C(gt_cpllpdrefclk),
+ .CE(1'b1),
+ .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
+ .Q(cpllrst),
+ .R(1'b0));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h000000FF))
+ \cpllreset_wait_reg[31]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(1'b0),
+ .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \cpllreset_wait_reg[63]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
+ .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \cpllreset_wait_reg[95]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
+ .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
+ LUT3 #(
+ .INIT(8'hFE))
+ \gtx_channel.gtxe2_channel_i_i_2__1
+ (.I0(cpllrst),
+ .I1(rate_cpllreset_2),
+ .I2(RST_CPLLRESET),
+ .O(CPLLRESET0));
+endmodule
+
+(* ORIG_REF_NAME = "pcie_7x_0_gtx_cpllpd_ovrd" *)
+module pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_58
+ (cpllpd_0,
+ CPLLRESET0,
+ gt_cpllpdrefclk,
+ rate_cpllreset_1,
+ RST_CPLLRESET);
+ output cpllpd_0;
+ output CPLLRESET0;
+ input gt_cpllpdrefclk;
+ input rate_cpllreset_1;
+ input RST_CPLLRESET;
+
+ wire CPLLRESET0;
+ wire RST_CPLLRESET;
+ wire cpllpd_0;
+ wire \cpllpd_wait_reg[31]_srl32_n_1 ;
+ wire \cpllpd_wait_reg[63]_srl32_n_1 ;
+ wire \cpllpd_wait_reg[94]_srl31_n_0 ;
+ wire \cpllreset_wait_reg[126]_srl31_n_0 ;
+ wire \cpllreset_wait_reg[31]_srl32_n_1 ;
+ wire \cpllreset_wait_reg[63]_srl32_n_1 ;
+ wire \cpllreset_wait_reg[95]_srl32_n_1 ;
+ wire cpllrst;
+ wire gt_cpllpdrefclk;
+ wire rate_cpllreset_1;
+ wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;
+
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'hFFFFFFFF))
+ \cpllpd_wait_reg[31]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(1'b0),
+ .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'hFFFFFFFF))
+ \cpllpd_wait_reg[63]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
+ .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *)
+ SRLC32E #(
+ .INIT(32'h7FFFFFFF))
+ \cpllpd_wait_reg[94]_srl31
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
+ .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
+ .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
+ (* equivalent_register_removal = "no" *)
+ FDRE #(
+ .INIT(1'b1))
+ \cpllpd_wait_reg[95]
+ (.C(gt_cpllpdrefclk),
+ .CE(1'b1),
+ .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
+ .Q(cpllpd_0),
+ .R(1'b0));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \cpllreset_wait_reg[126]_srl31
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
+ .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
+ .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
+ (* equivalent_register_removal = "no" *)
+ FDRE #(
+ .INIT(1'b0))
+ \cpllreset_wait_reg[127]
+ (.C(gt_cpllpdrefclk),
+ .CE(1'b1),
+ .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
+ .Q(cpllrst),
+ .R(1'b0));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h000000FF))
+ \cpllreset_wait_reg[31]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(1'b0),
+ .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \cpllreset_wait_reg[63]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
+ .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \cpllreset_wait_reg[95]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
+ .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
+ LUT3 #(
+ .INIT(8'hFE))
+ \gtx_channel.gtxe2_channel_i_i_2__0
+ (.I0(cpllrst),
+ .I1(rate_cpllreset_1),
+ .I2(RST_CPLLRESET),
+ .O(CPLLRESET0));
+endmodule
+
+(* ORIG_REF_NAME = "pcie_7x_0_gtx_cpllpd_ovrd" *)
+module pcie_7x_0_pcie_7x_0_gtx_cpllpd_ovrd_60
+ (cpllpd,
+ CPLLRESET0,
+ gt_cpllpdrefclk,
+ rate_cpllreset_0,
+ RST_CPLLRESET);
+ output cpllpd;
+ output CPLLRESET0;
+ input gt_cpllpdrefclk;
+ input rate_cpllreset_0;
+ input RST_CPLLRESET;
+
+ wire CPLLRESET0;
+ wire RST_CPLLRESET;
+ wire cpllpd;
+ wire \cpllpd_wait_reg[31]_srl32_n_1 ;
+ wire \cpllpd_wait_reg[63]_srl32_n_1 ;
+ wire \cpllpd_wait_reg[94]_srl31_n_0 ;
+ wire \cpllreset_wait_reg[126]_srl31_n_0 ;
+ wire \cpllreset_wait_reg[31]_srl32_n_1 ;
+ wire \cpllreset_wait_reg[63]_srl32_n_1 ;
+ wire \cpllreset_wait_reg[95]_srl32_n_1 ;
+ wire cpllrst;
+ wire gt_cpllpdrefclk;
+ wire rate_cpllreset_0;
+ wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
+ wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;
+
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'hFFFFFFFF))
+ \cpllpd_wait_reg[31]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(1'b0),
+ .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'hFFFFFFFF))
+ \cpllpd_wait_reg[63]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
+ .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *)
+ SRLC32E #(
+ .INIT(32'h7FFFFFFF))
+ \cpllpd_wait_reg[94]_srl31
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
+ .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
+ .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
+ (* equivalent_register_removal = "no" *)
+ FDRE #(
+ .INIT(1'b1))
+ \cpllpd_wait_reg[95]
+ (.C(gt_cpllpdrefclk),
+ .CE(1'b1),
+ .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
+ .Q(cpllpd),
+ .R(1'b0));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \cpllreset_wait_reg[126]_srl31
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
+ .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
+ .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
+ (* equivalent_register_removal = "no" *)
+ FDRE #(
+ .INIT(1'b0))
+ \cpllreset_wait_reg[127]
+ (.C(gt_cpllpdrefclk),
+ .CE(1'b1),
+ .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
+ .Q(cpllrst),
+ .R(1'b0));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h000000FF))
+ \cpllreset_wait_reg[31]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(1'b0),
+ .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \cpllreset_wait_reg[63]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
+ .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
+ (* srl_bus_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *)
+ (* srl_name = "inst/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *)
+ SRLC32E #(
+ .INIT(32'h00000000))
+ \cpllreset_wait_reg[95]_srl32
+ (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .CE(1'b1),
+ .CLK(gt_cpllpdrefclk),
+ .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
+ .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
+ .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
+ LUT3 #(
+ .INIT(8'hFE))
+ \gtx_channel.gtxe2_channel_i_i_2
+ (.I0(cpllrst),
+ .I1(rate_cpllreset_0),
+ .I2(RST_CPLLRESET),
+ .O(CPLLRESET0));
+endmodule
+
+(* CFG_CTL_IF = "TRUE" *) (* CFG_FC_IF = "TRUE" *) (* CFG_MGMT_IF = "TRUE" *)
+(* CFG_STATUS_IF = "TRUE" *) (* C_DATA_WIDTH = "64" *) (* DowngradeIPIdentifiedWarnings = "yes" *)
+(* ENABLE_JTAG_DBG = "FALSE" *) (* ERR_REPORTING_IF = "TRUE" *) (* EXT_CH_GT_DRP = "FALSE" *)
+(* EXT_PIPE_INTERFACE = "FALSE" *) (* EXT_STARTUP_PRIMITIVE = "FALSE" *) (* KEEP_WIDTH = "8" *)
+(* LINK_CAP_MAX_LINK_WIDTH = "4" *) (* PCIE_ASYNC_EN = "FALSE" *) (* PCIE_EXT_CLK = "TRUE" *)
+(* PCIE_EXT_GT_COMMON = "FALSE" *) (* PIPE_SIM = "FALSE" *) (* PL_INTERFACE = "TRUE" *)
+(* RCV_MSG_IF = "TRUE" *) (* REDUCE_OOB_FREQ = "FALSE" *) (* SHARED_LOGIC_IN_CORE = "FALSE" *)
+(* TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE" *) (* bar_0 = "FFFF0000" *) (* bar_1 = "00000000" *)
+(* bar_2 = "00000000" *) (* bar_3 = "00000000" *) (* bar_4 = "00000000" *)
+(* bar_5 = "00000000" *) (* bram_lat = "0" *) (* c_aer_base_ptr = "000" *)
+(* c_aer_cap_ecrc_check_capable = "FALSE" *) (* c_aer_cap_ecrc_gen_capable = "FALSE" *) (* c_aer_cap_multiheader = "FALSE" *)
+(* c_aer_cap_nextptr = "000" *) (* c_aer_cap_on = "FALSE" *) (* c_aer_cap_optional_err_support = "000000" *)
+(* c_aer_cap_permit_rooterr_update = "FALSE" *) (* c_buf_opt_bma = "TRUE" *) (* c_component_name = "pcie_7x_0" *)
+(* c_cpl_inf = "TRUE" *) (* c_cpl_infinite = "TRUE" *) (* c_cpl_timeout_disable_sup = "FALSE" *)
+(* c_cpl_timeout_range = "0010" *) (* c_cpl_timeout_ranges_sup = "2" *) (* c_d1_support = "FALSE" *)
+(* c_d2_support = "FALSE" *) (* c_de_emph = "FALSE" *) (* c_dev_cap2_ari_forwarding_supported = "FALSE" *)
+(* c_dev_cap2_atomicop32_completer_supported = "FALSE" *) (* c_dev_cap2_atomicop64_completer_supported = "FALSE" *) (* c_dev_cap2_atomicop_routing_supported = "FALSE" *)
+(* c_dev_cap2_cas128_completer_supported = "FALSE" *) (* c_dev_cap2_tph_completer_supported = "00" *) (* c_dev_control_ext_tag_default = "FALSE" *)
+(* c_dev_port_type = "0" *) (* c_dis_lane_reverse = "TRUE" *) (* c_disable_rx_poisoned_resp = "FALSE" *)
+(* c_disable_scrambling = "FALSE" *) (* c_disable_tx_aspm_l0s = "FALSE" *) (* c_dll_lnk_actv_cap = "FALSE" *)
+(* c_dsi_bool = "FALSE" *) (* c_dsn_base_ptr = "100" *) (* c_dsn_cap_enabled = "TRUE" *)
+(* c_dsn_next_ptr = "000" *) (* c_enable_msg_route = "00000000000" *) (* c_ep_l0s_accpt_lat = "0" *)
+(* c_ep_l1_accpt_lat = "7" *) (* c_ext_pci_cfg_space_addr = "3FF" *) (* c_external_clocking = "TRUE" *)
+(* c_fc_cpld = "973" *) (* c_fc_cplh = "36" *) (* c_fc_npd = "24" *)
+(* c_fc_nph = "12" *) (* c_fc_pd = "949" *) (* c_fc_ph = "32" *)
+(* c_gen1 = "1'b1" *) (* c_header_type = "00" *) (* c_hw_auton_spd_disable = "FALSE" *)
+(* c_int_width = "64" *) (* c_last_cfg_dw = "10C" *) (* c_link_cap_aspm_optionality = "FALSE" *)
+(* c_ll_ack_timeout = "0000" *) (* c_ll_ack_timeout_enable = "FALSE" *) (* c_ll_ack_timeout_function = "0" *)
+(* c_ll_replay_timeout = "0000" *) (* c_ll_replay_timeout_enable = "FALSE" *) (* c_ll_replay_timeout_func = "1" *)
+(* c_lnk_bndwdt_notif = "FALSE" *) (* c_msi = "0" *) (* c_msi_64b_addr = "TRUE" *)
+(* c_msi_cap_on = "FALSE" *) (* c_msi_mult_msg_extn = "0" *) (* c_msi_per_vctr_mask_cap = "FALSE" *)
+(* c_msix_cap_on = "FALSE" *) (* c_msix_next_ptr = "00" *) (* c_msix_pba_bir = "0" *)
+(* c_msix_pba_offset = "0" *) (* c_msix_table_bir = "0" *) (* c_msix_table_offset = "0" *)
+(* c_msix_table_size = "000" *) (* c_pci_cfg_space_addr = "3F" *) (* c_pcie_blk_locn = "0" *)
+(* c_pcie_cap_next_ptr = "00" *) (* c_pcie_cap_slot_implemented = "FALSE" *) (* c_pcie_dbg_ports = "TRUE" *)
+(* c_pcie_fast_config = "0" *) (* c_perf_level_high = "TRUE" *) (* c_phantom_functions = "0" *)
+(* c_pm_cap_next_ptr = "60" *) (* c_pme_support = "0F" *) (* c_rbar_base_ptr = "000" *)
+(* c_rbar_cap_control_encodedbar0 = "00" *) (* c_rbar_cap_control_encodedbar1 = "00" *) (* c_rbar_cap_control_encodedbar2 = "00" *)
+(* c_rbar_cap_control_encodedbar3 = "00" *) (* c_rbar_cap_control_encodedbar4 = "00" *) (* c_rbar_cap_control_encodedbar5 = "00" *)
+(* c_rbar_cap_index0 = "0" *) (* c_rbar_cap_index1 = "0" *) (* c_rbar_cap_index2 = "0" *)
+(* c_rbar_cap_index3 = "0" *) (* c_rbar_cap_index4 = "0" *) (* c_rbar_cap_index5 = "0" *)
+(* c_rbar_cap_nextptr = "000" *) (* c_rbar_cap_on = "FALSE" *) (* c_rbar_cap_sup0 = "00001" *)
+(* c_rbar_cap_sup1 = "00001" *) (* c_rbar_cap_sup2 = "00001" *) (* c_rbar_cap_sup3 = "00001" *)
+(* c_rbar_cap_sup4 = "00001" *) (* c_rbar_cap_sup5 = "00001" *) (* c_rbar_num = "0" *)
+(* c_rcb = "0" *) (* c_recrc_check = "0" *) (* c_recrc_check_trim = "FALSE" *)
+(* c_rev_gt_order = "FALSE" *) (* c_root_cap_crs = "FALSE" *) (* c_rx_raddr_lat = "0" *)
+(* c_rx_ram_limit = "FFF" *) (* c_rx_rdata_lat = "2" *) (* c_rx_write_lat = "0" *)
+(* c_silicon_rev = "2" *) (* c_slot_cap_attn_butn = "FALSE" *) (* c_slot_cap_attn_ind = "FALSE" *)
+(* c_slot_cap_elec_interlock = "FALSE" *) (* c_slot_cap_hotplug_cap = "FALSE" *) (* c_slot_cap_hotplug_surprise = "FALSE" *)
+(* c_slot_cap_mrl = "FALSE" *) (* c_slot_cap_no_cmd_comp_sup = "FALSE" *) (* c_slot_cap_physical_slot_num = "0" *)
+(* c_slot_cap_pwr_ctrl = "FALSE" *) (* c_slot_cap_pwr_ind = "FALSE" *) (* c_slot_cap_pwr_limit_scale = "0" *)
+(* c_slot_cap_pwr_limit_value = "0" *) (* c_surprise_dn_err_cap = "FALSE" *) (* c_trgt_lnk_spd = "2" *)
+(* c_trn_np_fc = "TRUE" *) (* c_tx_last_tlp = "30" *) (* c_tx_raddr_lat = "0" *)
+(* c_tx_rdata_lat = "2" *) (* c_tx_write_lat = "0" *) (* c_upconfig_capable = "TRUE" *)
+(* c_upstream_facing = "TRUE" *) (* c_ur_atomic = "FALSE" *) (* c_ur_inv_req = "TRUE" *)
+(* c_ur_prs_response = "TRUE" *) (* c_vc_base_ptr = "000" *) (* c_vc_cap_enabled = "FALSE" *)
+(* c_vc_cap_reject_snoop = "FALSE" *) (* c_vc_next_ptr = "000" *) (* c_vsec_base_ptr = "000" *)
+(* c_vsec_cap_enabled = "FALSE" *) (* c_vsec_next_ptr = "000" *) (* c_xlnx_ref_board = "ZC706" *)
+(* cap_ver = "2" *) (* cardbus_cis_ptr = "00000000" *) (* class_code = "050000" *)
+(* cmps = "3" *) (* con_scl_fctr_d0_state = "0" *) (* con_scl_fctr_d1_state = "0" *)
+(* con_scl_fctr_d2_state = "0" *) (* con_scl_fctr_d3_state = "0" *) (* cost_table = "1" *)
+(* d1_sup = "0" *) (* d2_sup = "0" *) (* dev_id = "7024" *)
+(* dev_port_type = "0000" *) (* dis_scl_fctr_d0_state = "0" *) (* dis_scl_fctr_d1_state = "0" *)
+(* dis_scl_fctr_d2_state = "0" *) (* dis_scl_fctr_d3_state = "0" *) (* dsi = "0" *)
+(* ep_l0s_accpt_lat = "000" *) (* ep_l1_accpt_lat = "111" *) (* ext_tag_fld_sup = "FALSE" *)
+(* int_pin = "1" *) (* intx = "TRUE" *) (* max_lnk_spd = "2" *)
+(* max_lnk_wdt = "000100" *) (* mps = "011" *) (* no_soft_rst = "TRUE" *)
+(* pci_exp_int_freq = "3" *) (* pci_exp_ref_freq = "0" *) (* phantm_func_sup = "00" *)
+(* pme_sup = "0F" *) (* pwr_con_d0_state = "00" *) (* pwr_con_d1_state = "00" *)
+(* pwr_con_d2_state = "00" *) (* pwr_con_d3_state = "00" *) (* pwr_dis_d0_state = "00" *)
+(* pwr_dis_d1_state = "00" *) (* pwr_dis_d2_state = "00" *) (* pwr_dis_d3_state = "00" *)
+(* rev_id = "00" *) (* slot_clk = "TRUE" *) (* subsys_id = "0007" *)
+(* subsys_ven_id = "10EE" *) (* ven_id = "10EE" *) (* xrom_bar = "00000000" *)
+module pcie_7x_0_pcie_7x_0_pcie2_top
+ (pci_exp_txn,
+ pci_exp_txp,
+ pci_exp_rxn,
+ pci_exp_rxp,
+ int_pclk_out_slave,
+ int_pipe_rxusrclk_out,
+ int_rxoutclk_out,
+ int_dclk_out,
+ int_userclk1_out,
+ int_userclk2_out,
+ int_oobclk_out,
+ int_mmcm_lock_out,
+ int_qplllock_out,
+ int_qplloutclk_out,
+ int_qplloutrefclk_out,
+ int_pclk_sel_slave,
+ pipe_pclk_in,
+ pipe_rxusrclk_in,
+ pipe_rxoutclk_in,
+ pipe_dclk_in,
+ pipe_userclk1_in,
+ pipe_userclk2_in,
+ pipe_oobclk_in,
+ pipe_mmcm_lock_in,
+ pipe_txoutclk_out,
+ pipe_rxoutclk_out,
+ pipe_pclk_sel_out,
+ pipe_gen3_out,
+ qpll_drp_crscode,
+ qpll_drp_fsm,
+ qpll_drp_done,
+ qpll_drp_reset,
+ qpll_qplllock,
+ qpll_qplloutclk,
+ qpll_qplloutrefclk,
+ qpll_qplld,
+ qpll_qpllreset,
+ qpll_drp_clk,
+ qpll_drp_rst_n,
+ qpll_drp_ovrd,
+ qpll_drp_gen3,
+ qpll_drp_start,
+ user_clk_out,
+ user_reset_out,
+ user_lnk_up,
+ user_app_rdy,
+ tx_buf_av,
+ tx_err_drop,
+ tx_cfg_req,
+ s_axis_tx_tdata,
+ s_axis_tx_tvalid,
+ s_axis_tx_tready,
+ s_axis_tx_tkeep,
+ s_axis_tx_tlast,
+ s_axis_tx_tuser,
+ tx_cfg_gnt,
+ m_axis_rx_tdata,
+ m_axis_rx_tvalid,
+ m_axis_rx_tready,
+ m_axis_rx_tkeep,
+ m_axis_rx_tlast,
+ m_axis_rx_tuser,
+ rx_np_ok,
+ rx_np_req,
+ fc_cpld,
+ fc_cplh,
+ fc_npd,
+ fc_nph,
+ fc_pd,
+ fc_ph,
+ fc_sel,
+ cfg_mgmt_do,
+ cfg_mgmt_rd_wr_done,
+ cfg_status,
+ cfg_command,
+ cfg_dstatus,
+ cfg_dcommand,
+ cfg_lstatus,
+ cfg_lcommand,
+ cfg_dcommand2,
+ cfg_pcie_link_state,
+ cfg_pmcsr_pme_en,
+ cfg_pmcsr_powerstate,
+ cfg_pmcsr_pme_status,
+ cfg_received_func_lvl_rst,
+ cfg_mgmt_di,
+ cfg_mgmt_byte_en,
+ cfg_mgmt_dwaddr,
+ cfg_mgmt_wr_en,
+ cfg_mgmt_rd_en,
+ cfg_mgmt_wr_readonly,
+ cfg_err_ecrc,
+ cfg_err_ur,
+ cfg_err_cpl_timeout,
+ cfg_err_cpl_unexpect,
+ cfg_err_cpl_abort,
+ cfg_err_posted,
+ cfg_err_cor,
+ cfg_err_atomic_egress_blocked,
+ cfg_err_internal_cor,
+ cfg_err_malformed,
+ cfg_err_mc_blocked,
+ cfg_err_poisoned,
+ cfg_err_norecovery,
+ cfg_err_tlp_cpl_header,
+ cfg_err_cpl_rdy,
+ cfg_err_locked,
+ cfg_err_acs,
+ cfg_err_internal_uncor,
+ cfg_trn_pending,
+ cfg_pm_halt_aspm_l0s,
+ cfg_pm_halt_aspm_l1,
+ cfg_pm_force_state_en,
+ cfg_pm_force_state,
+ cfg_dsn,
+ cfg_msg_received,
+ cfg_msg_data,
+ cfg_interrupt,
+ cfg_interrupt_rdy,
+ cfg_interrupt_assert,
+ cfg_interrupt_di,
+ cfg_interrupt_do,
+ cfg_interrupt_mmenable,
+ cfg_interrupt_msienable,
+ cfg_interrupt_msixenable,
+ cfg_interrupt_msixfm,
+ cfg_interrupt_stat,
+ cfg_pciecap_interrupt_msgnum,
+ cfg_to_turnoff,
+ cfg_turnoff_ok,
+ cfg_bus_number,
+ cfg_device_number,
+ cfg_function_number,
+ cfg_pm_wake,
+ cfg_msg_received_pm_as_nak,
+ cfg_msg_received_setslotpowerlimit,
+ cfg_pm_send_pme_to,
+ cfg_ds_bus_number,
+ cfg_ds_device_number,
+ cfg_ds_function_number,
+ cfg_mgmt_wr_rw1c_as_rw,
+ cfg_bridge_serr_en,
+ cfg_slot_control_electromech_il_ctl_pulse,
+ cfg_root_control_syserr_corr_err_en,
+ cfg_root_control_syserr_non_fatal_err_en,
+ cfg_root_control_syserr_fatal_err_en,
+ cfg_root_control_pme_int_en,
+ cfg_aer_rooterr_corr_err_reporting_en,
+ cfg_aer_rooterr_non_fatal_err_reporting_en,
+ cfg_aer_rooterr_fatal_err_reporting_en,
+ cfg_aer_rooterr_corr_err_received,
+ cfg_aer_rooterr_non_fatal_err_received,
+ cfg_aer_rooterr_fatal_err_received,
+ cfg_msg_received_err_cor,
+ cfg_msg_received_err_non_fatal,
+ cfg_msg_received_err_fatal,
+ cfg_msg_received_pm_pme,
+ cfg_msg_received_pme_to_ack,
+ cfg_msg_received_assert_int_a,
+ cfg_msg_received_assert_int_b,
+ cfg_msg_received_assert_int_c,
+ cfg_msg_received_assert_int_d,
+ cfg_msg_received_deassert_int_a,
+ cfg_msg_received_deassert_int_b,
+ cfg_msg_received_deassert_int_c,
+ cfg_msg_received_deassert_int_d,
+ pl_directed_link_change,
+ pl_directed_link_width,
+ pl_directed_link_speed,
+ pl_directed_link_auton,
+ pl_upstream_prefer_deemph,
+ pl_sel_lnk_rate,
+ pl_sel_lnk_width,
+ pl_ltssm_state,
+ pl_lane_reversal_mode,
+ pl_phy_lnk_up,
+ pl_tx_pm_state,
+ pl_rx_pm_state,
+ pl_link_upcfg_cap,
+ pl_link_gen2_cap,
+ pl_link_partner_gen2_supported,
+ pl_initial_link_width,
+ pl_directed_change_done,
+ pl_received_hot_rst,
+ pl_transmit_hot_rst,
+ pl_downstream_deemph_source,
+ cfg_err_aer_headerlog,
+ cfg_aer_interrupt_msgnum,
+ cfg_err_aer_headerlog_set,
+ cfg_aer_ecrc_check_en,
+ cfg_aer_ecrc_gen_en,
+ cfg_vc_tcvc_map,
+ pcie_drp_clk,
+ pcie_drp_en,
+ pcie_drp_we,
+ pcie_drp_addr,
+ pcie_drp_di,
+ pcie_drp_rdy,
+ pcie_drp_do,
+ startup_eos_in,
+ startup_cfgclk,
+ startup_cfgmclk,
+ startup_eos,
+ startup_preq,
+ startup_clk,
+ startup_gsr,
+ startup_gts,
+ startup_keyclearb,
+ startup_pack,
+ startup_usrcclko,
+ startup_usrcclkts,
+ startup_usrdoneo,
+ startup_usrdonets,
+ icap_clk,
+ icap_csib,
+ icap_rdwrb,
+ icap_i,
+ icap_o,
+ pipe_txprbssel,
+ pipe_rxprbssel,
+ pipe_txprbsforceerr,
+ pipe_rxprbscntreset,
+ pipe_loopback,
+ pipe_rxprbserr,
+ pipe_txinhibit,
+ pipe_rst_fsm,
+ pipe_qrst_fsm,
+ pipe_rate_fsm,
+ pipe_sync_fsm_tx,
+ pipe_sync_fsm_rx,
+ pipe_drp_fsm,
+ pipe_rst_idle,
+ pipe_qrst_idle,
+ pipe_rate_idle,
+ pipe_eyescandataerror,
+ pipe_rxstatus,
+ pipe_dmonitorout,
+ pipe_cpll_lock,
+ pipe_qpll_lock,
+ pipe_rxpmaresetdone,
+ pipe_rxbufstatus,
+ pipe_txphaligndone,
+ pipe_txphinitdone,
+ pipe_txdlysresetdone,
+ pipe_rxphaligndone,
+ pipe_rxdlysresetdone,
+ pipe_rxsyncdone,
+ pipe_rxdisperr,
+ pipe_rxnotintable,
+ pipe_rxcommadet,
+ gt_ch_drp_rdy,
+ pipe_debug_0,
+ pipe_debug_1,
+ pipe_debug_2,
+ pipe_debug_3,
+ pipe_debug_4,
+ pipe_debug_5,
+ pipe_debug_6,
+ pipe_debug_7,
+ pipe_debug_8,
+ pipe_debug_9,
+ pipe_debug,
+ ext_ch_gt_drpclk,
+ ext_ch_gt_drpaddr,
+ ext_ch_gt_drpen,
+ ext_ch_gt_drpdi,
+ ext_ch_gt_drpwe,
+ ext_ch_gt_drpdo,
+ ext_ch_gt_drprdy,
+ common_commands_in,
+ pipe_rx_0_sigs,
+ pipe_rx_1_sigs,
+ pipe_rx_2_sigs,
+ pipe_rx_3_sigs,
+ pipe_rx_4_sigs,
+ pipe_rx_5_sigs,
+ pipe_rx_6_sigs,
+ pipe_rx_7_sigs,
+ common_commands_out,
+ pipe_tx_0_sigs,
+ pipe_tx_1_sigs,
+ pipe_tx_2_sigs,
+ pipe_tx_3_sigs,
+ pipe_tx_4_sigs,
+ pipe_tx_5_sigs,
+ pipe_tx_6_sigs,
+ pipe_tx_7_sigs,
+ pipe_mmcm_rst_n,
+ sys_clk,
+ sys_rst_n);
+ output [3:0]pci_exp_txn;
+ output [3:0]pci_exp_txp;
+ input [3:0]pci_exp_rxn;
+ input [3:0]pci_exp_rxp;
+ output int_pclk_out_slave;
+ output int_pipe_rxusrclk_out;
+ output [3:0]int_rxoutclk_out;
+ output int_dclk_out;
+ output int_userclk1_out;
+ output int_userclk2_out;
+ output int_oobclk_out;
+ output int_mmcm_lock_out;
+ output [1:0]int_qplllock_out;
+ output [1:0]int_qplloutclk_out;
+ output [1:0]int_qplloutrefclk_out;
+ input [3:0]int_pclk_sel_slave;
+ input pipe_pclk_in;
+ input pipe_rxusrclk_in;
+ input [3:0]pipe_rxoutclk_in;
+ input pipe_dclk_in;
+ input pipe_userclk1_in;
+ input pipe_userclk2_in;
+ input pipe_oobclk_in;
+ input pipe_mmcm_lock_in;
+ output pipe_txoutclk_out;
+ output [3:0]pipe_rxoutclk_out;
+ output [3:0]pipe_pclk_sel_out;
+ output pipe_gen3_out;
+ input [11:0]qpll_drp_crscode;
+ input [17:0]qpll_drp_fsm;
+ input [1:0]qpll_drp_done;
+ input [1:0]qpll_drp_reset;
+ input [1:0]qpll_qplllock;
+ input [1:0]qpll_qplloutclk;
+ input [1:0]qpll_qplloutrefclk;
+ output qpll_qplld;
+ output [1:0]qpll_qpllreset;
+ output qpll_drp_clk;
+ output qpll_drp_rst_n;
+ output qpll_drp_ovrd;
+ output qpll_drp_gen3;
+ output qpll_drp_start;
+ output user_clk_out;
+ output user_reset_out;
+ output user_lnk_up;
+ output user_app_rdy;
+ output [5:0]tx_buf_av;
+ output tx_err_drop;
+ output tx_cfg_req;
+ input [63:0]s_axis_tx_tdata;
+ input s_axis_tx_tvalid;
+ output s_axis_tx_tready;
+ input [7:0]s_axis_tx_tkeep;
+ input s_axis_tx_tlast;
+ input [3:0]s_axis_tx_tuser;
+ input tx_cfg_gnt;
+ output [63:0]m_axis_rx_tdata;
+ output m_axis_rx_tvalid;
+ input m_axis_rx_tready;
+ output [7:0]m_axis_rx_tkeep;
+ output m_axis_rx_tlast;
+ output [21:0]m_axis_rx_tuser;
+ input rx_np_ok;
+ input rx_np_req;
+ output [11:0]fc_cpld;
+ output [7:0]fc_cplh;
+ output [11:0]fc_npd;
+ output [7:0]fc_nph;
+ output [11:0]fc_pd;
+ output [7:0]fc_ph;
+ input [2:0]fc_sel;
+ output [31:0]cfg_mgmt_do;
+ output cfg_mgmt_rd_wr_done;
+ output [15:0]cfg_status;
+ output [15:0]cfg_command;
+ output [15:0]cfg_dstatus;
+ output [15:0]cfg_dcommand;
+ output [15:0]cfg_lstatus;
+ output [15:0]cfg_lcommand;
+ output [15:0]cfg_dcommand2;
+ output [2:0]cfg_pcie_link_state;
+ output cfg_pmcsr_pme_en;
+ output [1:0]cfg_pmcsr_powerstate;
+ output cfg_pmcsr_pme_status;
+ output cfg_received_func_lvl_rst;
+ input [31:0]cfg_mgmt_di;
+ input [3:0]cfg_mgmt_byte_en;
+ input [9:0]cfg_mgmt_dwaddr;
+ input cfg_mgmt_wr_en;
+ input cfg_mgmt_rd_en;
+ input cfg_mgmt_wr_readonly;
+ input cfg_err_ecrc;
+ input cfg_err_ur;
+ input cfg_err_cpl_timeout;
+ input cfg_err_cpl_unexpect;
+ input cfg_err_cpl_abort;
+ input cfg_err_posted;
+ input cfg_err_cor;
+ input cfg_err_atomic_egress_blocked;
+ input cfg_err_internal_cor;
+ input cfg_err_malformed;
+ input cfg_err_mc_blocked;
+ input cfg_err_poisoned;
+ input cfg_err_norecovery;
+ input [47:0]cfg_err_tlp_cpl_header;
+ output cfg_err_cpl_rdy;
+ input cfg_err_locked;
+ input cfg_err_acs;
+ input cfg_err_internal_uncor;
+ input cfg_trn_pending;
+ input cfg_pm_halt_aspm_l0s;
+ input cfg_pm_halt_aspm_l1;
+ input cfg_pm_force_state_en;
+ input [1:0]cfg_pm_force_state;
+ input [63:0]cfg_dsn;
+ output cfg_msg_received;
+ output [15:0]cfg_msg_data;
+ input cfg_interrupt;
+ output cfg_interrupt_rdy;
+ input cfg_interrupt_assert;
+ input [7:0]cfg_interrupt_di;
+ output [7:0]cfg_interrupt_do;
+ output [2:0]cfg_interrupt_mmenable;
+ output cfg_interrupt_msienable;
+ output cfg_interrupt_msixenable;
+ output cfg_interrupt_msixfm;
+ input cfg_interrupt_stat;
+ input [4:0]cfg_pciecap_interrupt_msgnum;
+ output cfg_to_turnoff;
+ input cfg_turnoff_ok;
+ output [7:0]cfg_bus_number;
+ output [4:0]cfg_device_number;
+ output [2:0]cfg_function_number;
+ input cfg_pm_wake;
+ output cfg_msg_received_pm_as_nak;
+ output cfg_msg_received_setslotpowerlimit;
+ input cfg_pm_send_pme_to;
+ input [7:0]cfg_ds_bus_number;
+ input [4:0]cfg_ds_device_number;
+ input [2:0]cfg_ds_function_number;
+ input cfg_mgmt_wr_rw1c_as_rw;
+ output cfg_bridge_serr_en;
+ output cfg_slot_control_electromech_il_ctl_pulse;
+ output cfg_root_control_syserr_corr_err_en;
+ output cfg_root_control_syserr_non_fatal_err_en;
+ output cfg_root_control_syserr_fatal_err_en;
+ output cfg_root_control_pme_int_en;
+ output cfg_aer_rooterr_corr_err_reporting_en;
+ output cfg_aer_rooterr_non_fatal_err_reporting_en;
+ output cfg_aer_rooterr_fatal_err_reporting_en;
+ output cfg_aer_rooterr_corr_err_received;
+ output cfg_aer_rooterr_non_fatal_err_received;
+ output cfg_aer_rooterr_fatal_err_received;
+ output cfg_msg_received_err_cor;
+ output cfg_msg_received_err_non_fatal;
+ output cfg_msg_received_err_fatal;
+ output cfg_msg_received_pm_pme;
+ output cfg_msg_received_pme_to_ack;
+ output cfg_msg_received_assert_int_a;
+ output cfg_msg_received_assert_int_b;
+ output cfg_msg_received_assert_int_c;
+ output cfg_msg_received_assert_int_d;
+ output cfg_msg_received_deassert_int_a;
+ output cfg_msg_received_deassert_int_b;
+ output cfg_msg_received_deassert_int_c;
+ output cfg_msg_received_deassert_int_d;
+ input [1:0]pl_directed_link_change;
+ input [1:0]pl_directed_link_width;
+ input pl_directed_link_speed;
+ input pl_directed_link_auton;
+ input pl_upstream_prefer_deemph;
+ output pl_sel_lnk_rate;
+ output [1:0]pl_sel_lnk_width;
+ output [5:0]pl_ltssm_state;
+ output [1:0]pl_lane_reversal_mode;
+ output pl_phy_lnk_up;
+ output [2:0]pl_tx_pm_state;
+ output [1:0]pl_rx_pm_state;
+ output pl_link_upcfg_cap;
+ output pl_link_gen2_cap;
+ output pl_link_partner_gen2_supported;
+ output [2:0]pl_initial_link_width;
+ output pl_directed_change_done;
+ output pl_received_hot_rst;
+ input pl_transmit_hot_rst;
+ input pl_downstream_deemph_source;
+ input [127:0]cfg_err_aer_headerlog;
+ input [4:0]cfg_aer_interrupt_msgnum;
+ output cfg_err_aer_headerlog_set;
+ output cfg_aer_ecrc_check_en;
+ output cfg_aer_ecrc_gen_en;
+ output [6:0]cfg_vc_tcvc_map;
+ input pcie_drp_clk;
+ input pcie_drp_en;
+ input pcie_drp_we;
+ input [8:0]pcie_drp_addr;
+ input [15:0]pcie_drp_di;
+ output pcie_drp_rdy;
+ output [15:0]pcie_drp_do;
+ input startup_eos_in;
+ output startup_cfgclk;
+ output startup_cfgmclk;
+ output startup_eos;
+ output startup_preq;
+ input startup_clk;
+ input startup_gsr;
+ input startup_gts;
+ input startup_keyclearb;
+ input startup_pack;
+ input startup_usrcclko;
+ input startup_usrcclkts;
+ input startup_usrdoneo;
+ input startup_usrdonets;
+ input icap_clk;
+ input icap_csib;
+ input icap_rdwrb;
+ input [31:0]icap_i;
+ output [31:0]icap_o;
+ input [2:0]pipe_txprbssel;
+ input [2:0]pipe_rxprbssel;
+ input pipe_txprbsforceerr;
+ input pipe_rxprbscntreset;
+ input [2:0]pipe_loopback;
+ output [3:0]pipe_rxprbserr;
+ input [3:0]pipe_txinhibit;
+ output [4:0]pipe_rst_fsm;
+ output [11:0]pipe_qrst_fsm;
+ output [19:0]pipe_rate_fsm;
+ output [23:0]pipe_sync_fsm_tx;
+ output [27:0]pipe_sync_fsm_rx;
+ output [27:0]pipe_drp_fsm;
+ output pipe_rst_idle;
+ output pipe_qrst_idle;
+ output pipe_rate_idle;
+ output [3:0]pipe_eyescandataerror;
+ output [11:0]pipe_rxstatus;
+ output [59:0]pipe_dmonitorout;
+ output [3:0]pipe_cpll_lock;
+ output [0:0]pipe_qpll_lock;
+ output [3:0]pipe_rxpmaresetdone;
+ output [11:0]pipe_rxbufstatus;
+ output [3:0]pipe_txphaligndone;
+ output [3:0]pipe_txphinitdone;
+ output [3:0]pipe_txdlysresetdone;
+ output [3:0]pipe_rxphaligndone;
+ output [3:0]pipe_rxdlysresetdone;
+ output [3:0]pipe_rxsyncdone;
+ output [31:0]pipe_rxdisperr;
+ output [31:0]pipe_rxnotintable;
+ output [3:0]pipe_rxcommadet;
+ output [3:0]gt_ch_drp_rdy;
+ output [3:0]pipe_debug_0;
+ output [3:0]pipe_debug_1;
+ output [3:0]pipe_debug_2;
+ output [3:0]pipe_debug_3;
+ output [3:0]pipe_debug_4;
+ output [3:0]pipe_debug_5;
+ output [3:0]pipe_debug_6;
+ output [3:0]pipe_debug_7;
+ output [3:0]pipe_debug_8;
+ output [3:0]pipe_debug_9;
+ output [31:0]pipe_debug;
+ output ext_ch_gt_drpclk;
+ input [35:0]ext_ch_gt_drpaddr;
+ input [3:0]ext_ch_gt_drpen;
+ input [63:0]ext_ch_gt_drpdi;
+ input [3:0]ext_ch_gt_drpwe;
+ output [63:0]ext_ch_gt_drpdo;
+ output [3:0]ext_ch_gt_drprdy;
+ input [11:0]common_commands_in;
+ input [24:0]pipe_rx_0_sigs;
+ input [24:0]pipe_rx_1_sigs;
+ input [24:0]pipe_rx_2_sigs;
+ input [24:0]pipe_rx_3_sigs;
+ input [24:0]pipe_rx_4_sigs;
+ input [24:0]pipe_rx_5_sigs;
+ input [24:0]pipe_rx_6_sigs;
+ input [24:0]pipe_rx_7_sigs;
+ output [11:0]common_commands_out;
+ output [24:0]pipe_tx_0_sigs;
+ output [24:0]pipe_tx_1_sigs;
+ output [24:0]pipe_tx_2_sigs;
+ output [24:0]pipe_tx_3_sigs;
+ output [24:0]pipe_tx_4_sigs;
+ output [24:0]pipe_tx_5_sigs;
+ output [24:0]pipe_tx_6_sigs;
+ output [24:0]pipe_tx_7_sigs;
+ input pipe_mmcm_rst_n;
+ input sys_clk;
+ input sys_rst_n;
+
+ wire \ ;
+ wire cfg_aer_ecrc_check_en;
+ wire cfg_aer_ecrc_gen_en;
+ wire [4:0]cfg_aer_interrupt_msgnum;
+ wire cfg_aer_rooterr_corr_err_received;
+ wire cfg_aer_rooterr_corr_err_reporting_en;
+ wire cfg_aer_rooterr_fatal_err_received;
+ wire cfg_aer_rooterr_fatal_err_reporting_en;
+ wire cfg_aer_rooterr_non_fatal_err_received;
+ wire cfg_aer_rooterr_non_fatal_err_reporting_en;
+ wire cfg_bridge_serr_en;
+ wire [7:0]cfg_bus_number;
+ wire [10:0]\^cfg_command ;
+ wire [14:0]\^cfg_dcommand ;
+ wire [11:0]\^cfg_dcommand2 ;
+ wire [4:0]cfg_device_number;
+ wire [7:0]cfg_ds_bus_number;
+ wire [4:0]cfg_ds_device_number;
+ wire [2:0]cfg_ds_function_number;
+ wire [63:0]cfg_dsn;
+ wire [3:0]\^cfg_dstatus ;
+ wire [127:0]cfg_err_aer_headerlog;
+ wire cfg_err_aer_headerlog_set;
+ wire cfg_err_atomic_egress_blocked;
+ wire cfg_err_cor;
+ wire cfg_err_cpl_abort;
+ wire cfg_err_cpl_rdy;
+ wire cfg_err_cpl_timeout;
+ wire cfg_err_cpl_unexpect;
+ wire cfg_err_ecrc;
+ wire cfg_err_internal_cor;
+ wire cfg_err_internal_uncor;
+ wire cfg_err_locked;
+ wire cfg_err_malformed;
+ wire cfg_err_mc_blocked;
+ wire cfg_err_norecovery;
+ wire cfg_err_poisoned;
+ wire cfg_err_posted;
+ wire [47:0]cfg_err_tlp_cpl_header;
+ wire cfg_err_ur;
+ wire [2:0]cfg_function_number;
+ wire cfg_interrupt;
+ wire cfg_interrupt_assert;
+ wire [7:0]cfg_interrupt_di;
+ wire [7:0]cfg_interrupt_do;
+ wire [2:0]cfg_interrupt_mmenable;
+ wire cfg_interrupt_msienable;
+ wire cfg_interrupt_msixenable;
+ wire cfg_interrupt_msixfm;
+ wire cfg_interrupt_rdy;
+ wire cfg_interrupt_stat;
+ wire [11:0]\^cfg_lcommand ;
+ wire [15:0]\^cfg_lstatus ;
+ wire [3:0]cfg_mgmt_byte_en;
+ wire [31:0]cfg_mgmt_di;
+ wire [31:0]cfg_mgmt_do;
+ wire [9:0]cfg_mgmt_dwaddr;
+ wire cfg_mgmt_rd_en;
+ wire cfg_mgmt_rd_wr_done;
+ wire cfg_mgmt_wr_en;
+ wire cfg_mgmt_wr_readonly;
+ wire cfg_mgmt_wr_rw1c_as_rw;
+ wire [15:0]cfg_msg_data;
+ wire cfg_msg_received;
+ wire cfg_msg_received_assert_int_a;
+ wire cfg_msg_received_assert_int_b;
+ wire cfg_msg_received_assert_int_c;
+ wire cfg_msg_received_assert_int_d;
+ wire cfg_msg_received_deassert_int_a;
+ wire cfg_msg_received_deassert_int_b;
+ wire cfg_msg_received_deassert_int_c;
+ wire cfg_msg_received_deassert_int_d;
+ wire cfg_msg_received_err_cor;
+ wire cfg_msg_received_err_fatal;
+ wire cfg_msg_received_err_non_fatal;
+ wire cfg_msg_received_pm_as_nak;
+ wire cfg_msg_received_pm_pme;
+ wire cfg_msg_received_pme_to_ack;
+ wire cfg_msg_received_setslotpowerlimit;
+ wire [2:0]cfg_pcie_link_state;
+ wire [4:0]cfg_pciecap_interrupt_msgnum;
+ wire [1:0]cfg_pm_force_state;
+ wire cfg_pm_force_state_en;
+ wire cfg_pm_halt_aspm_l0s;
+ wire cfg_pm_halt_aspm_l1;
+ wire cfg_pm_wake;
+ wire cfg_pmcsr_pme_en;
+ wire cfg_pmcsr_pme_status;
+ wire [1:0]cfg_pmcsr_powerstate;
+ wire cfg_received_func_lvl_rst;
+ wire cfg_root_control_pme_int_en;
+ wire cfg_root_control_syserr_corr_err_en;
+ wire cfg_root_control_syserr_fatal_err_en;
+ wire cfg_root_control_syserr_non_fatal_err_en;
+ wire cfg_slot_control_electromech_il_ctl_pulse;
+ wire cfg_to_turnoff;
+ wire cfg_trn_pending;
+ wire cfg_turnoff_ok;
+ wire [6:0]cfg_vc_tcvc_map;
+ wire [11:0]fc_cpld;
+ wire [7:0]fc_cplh;
+ wire [11:0]fc_npd;
+ wire [7:0]fc_nph;
+ wire [11:0]fc_pd;
+ wire [7:0]fc_ph;
+ wire [2:0]fc_sel;
+ wire [63:0]m_axis_rx_tdata;
+ wire [6:6]\^m_axis_rx_tkeep ;
+ wire m_axis_rx_tlast;
+ wire m_axis_rx_tready;
+ wire [21:0]\^m_axis_rx_tuser ;
+ wire m_axis_rx_tvalid;
+ wire [3:0]pci_exp_rxn;
+ wire [3:0]pci_exp_rxp;
+ wire [3:0]pci_exp_txn;
+ wire [3:0]pci_exp_txp;
+ wire [8:0]pcie_drp_addr;
+ wire pcie_drp_clk;
+ wire [15:0]pcie_drp_di;
+ wire [15:0]pcie_drp_do;
+ wire pcie_drp_en;
+ wire pcie_drp_rdy;
+ wire pcie_drp_we;
+ wire pipe_dclk_in;
+ wire pipe_gen3_out;
+ wire pipe_mmcm_lock_in;
+ wire pipe_oobclk_in;
+ wire pipe_pclk_in;
+ wire [3:0]pipe_pclk_sel_out;
+ wire [3:0]pipe_rxoutclk_out;
+ wire pipe_rxusrclk_in;
+ wire pipe_txoutclk_out;
+ wire pipe_userclk1_in;
+ wire pipe_userclk2_in;
+ wire pl_directed_change_done;
+ wire pl_directed_link_auton;
+ wire [1:0]pl_directed_link_change;
+ wire pl_directed_link_speed;
+ wire [1:0]pl_directed_link_width;
+ wire pl_downstream_deemph_source;
+ wire [2:0]pl_initial_link_width;
+ wire [1:0]pl_lane_reversal_mode;
+ wire pl_link_gen2_cap;
+ wire pl_link_partner_gen2_supported;
+ wire pl_link_upcfg_cap;
+ wire [5:0]pl_ltssm_state;
+ wire pl_phy_lnk_up;
+ wire pl_received_hot_rst;
+ wire [1:0]pl_rx_pm_state;
+ wire pl_sel_lnk_rate;
+ wire [1:0]pl_sel_lnk_width;
+ wire pl_transmit_hot_rst;
+ wire [2:0]pl_tx_pm_state;
+ wire pl_upstream_prefer_deemph;
+ wire rx_np_ok;
+ wire rx_np_req;
+ wire [63:0]s_axis_tx_tdata;
+ wire [7:0]s_axis_tx_tkeep;
+ wire s_axis_tx_tlast;
+ wire s_axis_tx_tready;
+ wire [3:0]s_axis_tx_tuser;
+ wire s_axis_tx_tvalid;
+ wire sys_clk;
+ wire sys_rst_n;
+ wire [5:0]tx_buf_av;
+ wire tx_cfg_gnt;
+ wire tx_cfg_req;
+ wire tx_err_drop;
+ wire user_lnk_up;
+ wire user_reset_out;
+
+ assign cfg_command[15] = \ ;
+ assign cfg_command[14] = \ ;
+ assign cfg_command[13] = \ ;
+ assign cfg_command[12] = \ ;
+ assign cfg_command[11] = \ ;
+ assign cfg_command[10] = \^cfg_command [10];
+ assign cfg_command[9] = \ ;
+ assign cfg_command[8] = \^cfg_command [8];
+ assign cfg_command[7] = \ ;
+ assign cfg_command[6] = \ ;
+ assign cfg_command[5] = \ ;
+ assign cfg_command[4] = \ ;
+ assign cfg_command[3] = \ ;
+ assign cfg_command[2:0] = \^cfg_command [2:0];
+ assign cfg_dcommand[15] = \ ;
+ assign cfg_dcommand[14:0] = \^cfg_dcommand [14:0];
+ assign cfg_dcommand2[15] = \ ;
+ assign cfg_dcommand2[14] = \ ;
+ assign cfg_dcommand2[13] = \ ;
+ assign cfg_dcommand2[12] = \ ;
+ assign cfg_dcommand2[11:0] = \^cfg_dcommand2 [11:0];
+ assign cfg_dstatus[15] = \ ;
+ assign cfg_dstatus[14] = \ ;
+ assign cfg_dstatus[13] = \ ;
+ assign cfg_dstatus[12] = \ ;
+ assign cfg_dstatus[11] = \ ;
+ assign cfg_dstatus[10] = \ ;
+ assign cfg_dstatus[9] = \ ;
+ assign cfg_dstatus[8] = \ ;
+ assign cfg_dstatus[7] = \ ;
+ assign cfg_dstatus[6] = \ ;
+ assign cfg_dstatus[5] = cfg_trn_pending;
+ assign cfg_dstatus[4] = \ ;
+ assign cfg_dstatus[3:0] = \^cfg_dstatus [3:0];
+ assign cfg_lcommand[15] = \ ;
+ assign cfg_lcommand[14] = \ ;
+ assign cfg_lcommand[13] = \ ;
+ assign cfg_lcommand[12] = \ ;
+ assign cfg_lcommand[11:3] = \^cfg_lcommand [11:3];
+ assign cfg_lcommand[2] = \ ;
+ assign cfg_lcommand[1:0] = \^cfg_lcommand [1:0];
+ assign cfg_lstatus[15:13] = \^cfg_lstatus [15:13];
+ assign cfg_lstatus[12] = \ ;
+ assign cfg_lstatus[11] = \^cfg_lstatus [11];
+ assign cfg_lstatus[10] = \ ;
+ assign cfg_lstatus[9] = \ ;
+ assign cfg_lstatus[8] = \ ;
+ assign cfg_lstatus[7:4] = \^cfg_lstatus [7:4];
+ assign cfg_lstatus[3] = \ ;
+ assign cfg_lstatus[2] = \ ;
+ assign cfg_lstatus[1:0] = \^cfg_lstatus [1:0];
+ assign cfg_status[15] = \ ;
+ assign cfg_status[14] = \ ;
+ assign cfg_status[13] = \ ;
+ assign cfg_status[12] = \ ;
+ assign cfg_status[11] = \ ;
+ assign cfg_status[10] = \ ;
+ assign cfg_status[9] = \ ;
+ assign cfg_status[8] = \ ;
+ assign cfg_status[7] = \ ;
+ assign cfg_status[6] = \ ;
+ assign cfg_status[5] = \ ;
+ assign cfg_status[4] = \ ;
+ assign cfg_status[3] = \ ;
+ assign cfg_status[2] = \ ;
+ assign cfg_status[1] = \ ;
+ assign cfg_status[0] = \ ;
+ assign common_commands_out[11] = \ ;
+ assign common_commands_out[10] = \ ;
+ assign common_commands_out[9] = \ ;
+ assign common_commands_out[8] = \ ;
+ assign common_commands_out[7] = \ ;
+ assign common_commands_out[6] = \ ;
+ assign common_commands_out[5] = \ ;
+ assign common_commands_out[4] = \ ;
+ assign common_commands_out[3] = \ ;
+ assign common_commands_out[2] = \ ;
+ assign common_commands_out[1] = \ ;
+ assign common_commands_out[0] = \ ;
+ assign ext_ch_gt_drpclk = \ ;
+ assign ext_ch_gt_drpdo[63] = \ ;
+ assign ext_ch_gt_drpdo[62] = \ ;
+ assign ext_ch_gt_drpdo[61] = \ ;
+ assign ext_ch_gt_drpdo[60] = \ ;
+ assign ext_ch_gt_drpdo[59] = \ ;
+ assign ext_ch_gt_drpdo[58] = \ ;
+ assign ext_ch_gt_drpdo[57] = \ ;
+ assign ext_ch_gt_drpdo[56] = \ ;
+ assign ext_ch_gt_drpdo[55] = \ ;
+ assign ext_ch_gt_drpdo[54] = \ ;
+ assign ext_ch_gt_drpdo[53] = \ ;
+ assign ext_ch_gt_drpdo[52] = \ ;
+ assign ext_ch_gt_drpdo[51] = \ ;
+ assign ext_ch_gt_drpdo[50] = \ ;
+ assign ext_ch_gt_drpdo[49] = \ ;
+ assign ext_ch_gt_drpdo[48] = \ ;
+ assign ext_ch_gt_drpdo[47] = \ ;
+ assign ext_ch_gt_drpdo[46] = \ ;
+ assign ext_ch_gt_drpdo[45] = \ ;
+ assign ext_ch_gt_drpdo[44] = \ ;
+ assign ext_ch_gt_drpdo[43] = \ ;
+ assign ext_ch_gt_drpdo[42] = \ ;
+ assign ext_ch_gt_drpdo[41] = \ ;
+ assign ext_ch_gt_drpdo[40] = \ ;
+ assign ext_ch_gt_drpdo[39] = \ ;
+ assign ext_ch_gt_drpdo[38] = \ ;
+ assign ext_ch_gt_drpdo[37] = \ ;
+ assign ext_ch_gt_drpdo[36] = \ ;
+ assign ext_ch_gt_drpdo[35] = \ ;
+ assign ext_ch_gt_drpdo[34] = \ ;
+ assign ext_ch_gt_drpdo[33] = \ ;
+ assign ext_ch_gt_drpdo[32] = \ ;
+ assign ext_ch_gt_drpdo[31] = \ ;
+ assign ext_ch_gt_drpdo[30] = \ ;
+ assign ext_ch_gt_drpdo[29] = \ ;
+ assign ext_ch_gt_drpdo[28] = \ ;
+ assign ext_ch_gt_drpdo[27] = \ ;
+ assign ext_ch_gt_drpdo[26] = \ ;
+ assign ext_ch_gt_drpdo[25] = \ ;
+ assign ext_ch_gt_drpdo[24] = \ ;
+ assign ext_ch_gt_drpdo[23] = \ ;
+ assign ext_ch_gt_drpdo[22] = \ ;
+ assign ext_ch_gt_drpdo[21] = \ ;
+ assign ext_ch_gt_drpdo[20] = \ ;
+ assign ext_ch_gt_drpdo[19] = \ ;
+ assign ext_ch_gt_drpdo[18] = \ ;
+ assign ext_ch_gt_drpdo[17] = \ ;
+ assign ext_ch_gt_drpdo[16] = \ ;
+ assign ext_ch_gt_drpdo[15] = \ ;
+ assign ext_ch_gt_drpdo[14] = \ ;
+ assign ext_ch_gt_drpdo[13] = \ ;
+ assign ext_ch_gt_drpdo[12] = \ ;
+ assign ext_ch_gt_drpdo[11] = \ ;
+ assign ext_ch_gt_drpdo[10] = \ ;
+ assign ext_ch_gt_drpdo[9] = \ ;
+ assign ext_ch_gt_drpdo[8] = \ ;
+ assign ext_ch_gt_drpdo[7] = \ ;
+ assign ext_ch_gt_drpdo[6] = \ ;
+ assign ext_ch_gt_drpdo[5] = \ ;
+ assign ext_ch_gt_drpdo[4] = \ ;
+ assign ext_ch_gt_drpdo[3] = \ ;
+ assign ext_ch_gt_drpdo[2] = \ ;
+ assign ext_ch_gt_drpdo[1] = \ ;
+ assign ext_ch_gt_drpdo[0] = \ ;
+ assign ext_ch_gt_drprdy[3] = \ ;
+ assign ext_ch_gt_drprdy[2] = \ ;
+ assign ext_ch_gt_drprdy[1] = \ ;
+ assign ext_ch_gt_drprdy[0] = \ ;
+ assign gt_ch_drp_rdy[3] = \ ;
+ assign gt_ch_drp_rdy[2] = \ ;
+ assign gt_ch_drp_rdy[1] = \ ;
+ assign gt_ch_drp_rdy[0] = \ ;
+ assign icap_o[31] = \ ;
+ assign icap_o[30] = \ ;
+ assign icap_o[29] = \ ;
+ assign icap_o[28] = \ ;
+ assign icap_o[27] = \ ;
+ assign icap_o[26] = \ ;
+ assign icap_o[25] = \ ;
+ assign icap_o[24] = \ ;
+ assign icap_o[23] = \ ;
+ assign icap_o[22] = \ ;
+ assign icap_o[21] = \ ;
+ assign icap_o[20] = \ ;
+ assign icap_o[19] = \ ;
+ assign icap_o[18] = \ ;
+ assign icap_o[17] = \ ;
+ assign icap_o[16] = \ ;
+ assign icap_o[15] = \ ;
+ assign icap_o[14] = \ ;
+ assign icap_o[13] = \ ;
+ assign icap_o[12] = \ ;
+ assign icap_o[11] = \ ;
+ assign icap_o[10] = \ ;
+ assign icap_o[9] = \ ;
+ assign icap_o[8] = \ ;
+ assign icap_o[7] = \ ;
+ assign icap_o[6] = \ ;
+ assign icap_o[5] = \ ;
+ assign icap_o[4] = \ ;
+ assign icap_o[3] = \ ;
+ assign icap_o[2] = \ ;
+ assign icap_o[1] = \ ;
+ assign icap_o[0] = \ ;
+ assign int_dclk_out = \ ;
+ assign int_mmcm_lock_out = \ ;
+ assign int_oobclk_out = \ ;
+ assign int_pclk_out_slave = \ ;
+ assign int_pipe_rxusrclk_out = \ ;
+ assign int_qplllock_out[1] = \ ;
+ assign int_qplllock_out[0] = \ ;
+ assign int_qplloutclk_out[1] = \ ;
+ assign int_qplloutclk_out[0] = \ ;
+ assign int_qplloutrefclk_out[1] = \ ;
+ assign int_qplloutrefclk_out[0] = \